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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
37aa5c36 GL |
40 | #if defined(CONFIG_X86) |
41 | #include <asm/pat.h> | |
42 | #endif | |
e126ba97 | 43 | #include <linux/sched.h> |
7c2344c3 | 44 | #include <linux/delay.h> |
e126ba97 | 45 | #include <rdma/ib_user_verbs.h> |
3f89a643 | 46 | #include <rdma/ib_addr.h> |
2811ba51 | 47 | #include <rdma/ib_cache.h> |
ada68c31 | 48 | #include <linux/mlx5/port.h> |
1b5daf11 | 49 | #include <linux/mlx5/vport.h> |
7c2344c3 | 50 | #include <linux/list.h> |
e126ba97 EC |
51 | #include <rdma/ib_smi.h> |
52 | #include <rdma/ib_umem.h> | |
038d2ef8 MG |
53 | #include <linux/in.h> |
54 | #include <linux/etherdevice.h> | |
55 | #include <linux/mlx5/fs.h> | |
e126ba97 EC |
56 | #include "user.h" |
57 | #include "mlx5_ib.h" | |
58 | ||
59 | #define DRIVER_NAME "mlx5_ib" | |
169a1d85 AV |
60 | #define DRIVER_VERSION "2.2-1" |
61 | #define DRIVER_RELDATE "Feb 2014" | |
e126ba97 EC |
62 | |
63 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); | |
64 | MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); | |
65 | MODULE_LICENSE("Dual BSD/GPL"); | |
66 | MODULE_VERSION(DRIVER_VERSION); | |
67 | ||
9603b61d JM |
68 | static int deprecated_prof_sel = 2; |
69 | module_param_named(prof_sel, deprecated_prof_sel, int, 0444); | |
70 | MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); | |
e126ba97 EC |
71 | |
72 | static char mlx5_version[] = | |
73 | DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" | |
74 | DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; | |
75 | ||
da7525d2 EBE |
76 | enum { |
77 | MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, | |
78 | }; | |
79 | ||
1b5daf11 | 80 | static enum rdma_link_layer |
ebd61f68 | 81 | mlx5_port_type_cap_to_rdma_ll(int port_type_cap) |
1b5daf11 | 82 | { |
ebd61f68 | 83 | switch (port_type_cap) { |
1b5daf11 MD |
84 | case MLX5_CAP_PORT_TYPE_IB: |
85 | return IB_LINK_LAYER_INFINIBAND; | |
86 | case MLX5_CAP_PORT_TYPE_ETH: | |
87 | return IB_LINK_LAYER_ETHERNET; | |
88 | default: | |
89 | return IB_LINK_LAYER_UNSPECIFIED; | |
90 | } | |
91 | } | |
92 | ||
ebd61f68 AS |
93 | static enum rdma_link_layer |
94 | mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) | |
95 | { | |
96 | struct mlx5_ib_dev *dev = to_mdev(device); | |
97 | int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); | |
98 | ||
99 | return mlx5_port_type_cap_to_rdma_ll(port_type_cap); | |
100 | } | |
101 | ||
fc24fc5e AS |
102 | static int mlx5_netdev_event(struct notifier_block *this, |
103 | unsigned long event, void *ptr) | |
104 | { | |
105 | struct net_device *ndev = netdev_notifier_info_to_dev(ptr); | |
106 | struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, | |
107 | roce.nb); | |
108 | ||
109 | if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) | |
110 | return NOTIFY_DONE; | |
111 | ||
112 | write_lock(&ibdev->roce.netdev_lock); | |
113 | if (ndev->dev.parent == &ibdev->mdev->pdev->dev) | |
114 | ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; | |
115 | write_unlock(&ibdev->roce.netdev_lock); | |
116 | ||
117 | return NOTIFY_DONE; | |
118 | } | |
119 | ||
120 | static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, | |
121 | u8 port_num) | |
122 | { | |
123 | struct mlx5_ib_dev *ibdev = to_mdev(device); | |
124 | struct net_device *ndev; | |
125 | ||
126 | /* Ensure ndev does not disappear before we invoke dev_hold() | |
127 | */ | |
128 | read_lock(&ibdev->roce.netdev_lock); | |
129 | ndev = ibdev->roce.netdev; | |
130 | if (ndev) | |
131 | dev_hold(ndev); | |
132 | read_unlock(&ibdev->roce.netdev_lock); | |
133 | ||
134 | return ndev; | |
135 | } | |
136 | ||
3f89a643 AS |
137 | static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, |
138 | struct ib_port_attr *props) | |
139 | { | |
140 | struct mlx5_ib_dev *dev = to_mdev(device); | |
141 | struct net_device *ndev; | |
142 | enum ib_mtu ndev_ib_mtu; | |
c876a1b7 | 143 | u16 qkey_viol_cntr; |
3f89a643 AS |
144 | |
145 | memset(props, 0, sizeof(*props)); | |
146 | ||
147 | props->port_cap_flags |= IB_PORT_CM_SUP; | |
148 | props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; | |
149 | ||
150 | props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, | |
151 | roce_address_table_size); | |
152 | props->max_mtu = IB_MTU_4096; | |
153 | props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); | |
154 | props->pkey_tbl_len = 1; | |
155 | props->state = IB_PORT_DOWN; | |
156 | props->phys_state = 3; | |
157 | ||
c876a1b7 LR |
158 | mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); |
159 | props->qkey_viol_cntr = qkey_viol_cntr; | |
3f89a643 AS |
160 | |
161 | ndev = mlx5_ib_get_netdev(device, port_num); | |
162 | if (!ndev) | |
163 | return 0; | |
164 | ||
165 | if (netif_running(ndev) && netif_carrier_ok(ndev)) { | |
166 | props->state = IB_PORT_ACTIVE; | |
167 | props->phys_state = 5; | |
168 | } | |
169 | ||
170 | ndev_ib_mtu = iboe_get_mtu(ndev->mtu); | |
171 | ||
172 | dev_put(ndev); | |
173 | ||
174 | props->active_mtu = min(props->max_mtu, ndev_ib_mtu); | |
175 | ||
176 | props->active_width = IB_WIDTH_4X; /* TODO */ | |
177 | props->active_speed = IB_SPEED_QDR; /* TODO */ | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
3cca2606 AS |
182 | static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, |
183 | const struct ib_gid_attr *attr, | |
184 | void *mlx5_addr) | |
185 | { | |
186 | #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) | |
187 | char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, | |
188 | source_l3_address); | |
189 | void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, | |
190 | source_mac_47_32); | |
191 | ||
192 | if (!gid) | |
193 | return; | |
194 | ||
195 | ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); | |
196 | ||
197 | if (is_vlan_dev(attr->ndev)) { | |
198 | MLX5_SET_RA(mlx5_addr, vlan_valid, 1); | |
199 | MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); | |
200 | } | |
201 | ||
202 | switch (attr->gid_type) { | |
203 | case IB_GID_TYPE_IB: | |
204 | MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); | |
205 | break; | |
206 | case IB_GID_TYPE_ROCE_UDP_ENCAP: | |
207 | MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); | |
208 | break; | |
209 | ||
210 | default: | |
211 | WARN_ON(true); | |
212 | } | |
213 | ||
214 | if (attr->gid_type != IB_GID_TYPE_IB) { | |
215 | if (ipv6_addr_v4mapped((void *)gid)) | |
216 | MLX5_SET_RA(mlx5_addr, roce_l3_type, | |
217 | MLX5_ROCE_L3_TYPE_IPV4); | |
218 | else | |
219 | MLX5_SET_RA(mlx5_addr, roce_l3_type, | |
220 | MLX5_ROCE_L3_TYPE_IPV6); | |
221 | } | |
222 | ||
223 | if ((attr->gid_type == IB_GID_TYPE_IB) || | |
224 | !ipv6_addr_v4mapped((void *)gid)) | |
225 | memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); | |
226 | else | |
227 | memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); | |
228 | } | |
229 | ||
230 | static int set_roce_addr(struct ib_device *device, u8 port_num, | |
231 | unsigned int index, | |
232 | const union ib_gid *gid, | |
233 | const struct ib_gid_attr *attr) | |
234 | { | |
235 | struct mlx5_ib_dev *dev = to_mdev(device); | |
236 | u32 in[MLX5_ST_SZ_DW(set_roce_address_in)]; | |
237 | u32 out[MLX5_ST_SZ_DW(set_roce_address_out)]; | |
238 | void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); | |
239 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); | |
240 | ||
241 | if (ll != IB_LINK_LAYER_ETHERNET) | |
242 | return -EINVAL; | |
243 | ||
244 | memset(in, 0, sizeof(in)); | |
245 | ||
246 | ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); | |
247 | ||
248 | MLX5_SET(set_roce_address_in, in, roce_address_index, index); | |
249 | MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); | |
250 | ||
251 | memset(out, 0, sizeof(out)); | |
252 | return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); | |
253 | } | |
254 | ||
255 | static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, | |
256 | unsigned int index, const union ib_gid *gid, | |
257 | const struct ib_gid_attr *attr, | |
258 | __always_unused void **context) | |
259 | { | |
260 | return set_roce_addr(device, port_num, index, gid, attr); | |
261 | } | |
262 | ||
263 | static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, | |
264 | unsigned int index, __always_unused void **context) | |
265 | { | |
266 | return set_roce_addr(device, port_num, index, NULL, NULL); | |
267 | } | |
268 | ||
2811ba51 AS |
269 | __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, |
270 | int index) | |
271 | { | |
272 | struct ib_gid_attr attr; | |
273 | union ib_gid gid; | |
274 | ||
275 | if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) | |
276 | return 0; | |
277 | ||
278 | if (!attr.ndev) | |
279 | return 0; | |
280 | ||
281 | dev_put(attr.ndev); | |
282 | ||
283 | if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) | |
284 | return 0; | |
285 | ||
286 | return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); | |
287 | } | |
288 | ||
1b5daf11 MD |
289 | static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) |
290 | { | |
d603c809 | 291 | return !MLX5_CAP_GEN(dev->mdev, ib_virt); |
1b5daf11 MD |
292 | } |
293 | ||
294 | enum { | |
295 | MLX5_VPORT_ACCESS_METHOD_MAD, | |
296 | MLX5_VPORT_ACCESS_METHOD_HCA, | |
297 | MLX5_VPORT_ACCESS_METHOD_NIC, | |
298 | }; | |
299 | ||
300 | static int mlx5_get_vport_access_method(struct ib_device *ibdev) | |
301 | { | |
302 | if (mlx5_use_mad_ifc(to_mdev(ibdev))) | |
303 | return MLX5_VPORT_ACCESS_METHOD_MAD; | |
304 | ||
ebd61f68 | 305 | if (mlx5_ib_port_link_layer(ibdev, 1) == |
1b5daf11 MD |
306 | IB_LINK_LAYER_ETHERNET) |
307 | return MLX5_VPORT_ACCESS_METHOD_NIC; | |
308 | ||
309 | return MLX5_VPORT_ACCESS_METHOD_HCA; | |
310 | } | |
311 | ||
da7525d2 EBE |
312 | static void get_atomic_caps(struct mlx5_ib_dev *dev, |
313 | struct ib_device_attr *props) | |
314 | { | |
315 | u8 tmp; | |
316 | u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); | |
317 | u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); | |
318 | u8 atomic_req_8B_endianness_mode = | |
319 | MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); | |
320 | ||
321 | /* Check if HW supports 8 bytes standard atomic operations and capable | |
322 | * of host endianness respond | |
323 | */ | |
324 | tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; | |
325 | if (((atomic_operations & tmp) == tmp) && | |
326 | (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && | |
327 | (atomic_req_8B_endianness_mode)) { | |
328 | props->atomic_cap = IB_ATOMIC_HCA; | |
329 | } else { | |
330 | props->atomic_cap = IB_ATOMIC_NONE; | |
331 | } | |
332 | } | |
333 | ||
1b5daf11 MD |
334 | static int mlx5_query_system_image_guid(struct ib_device *ibdev, |
335 | __be64 *sys_image_guid) | |
336 | { | |
337 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
338 | struct mlx5_core_dev *mdev = dev->mdev; | |
339 | u64 tmp; | |
340 | int err; | |
341 | ||
342 | switch (mlx5_get_vport_access_method(ibdev)) { | |
343 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
344 | return mlx5_query_mad_ifc_system_image_guid(ibdev, | |
345 | sys_image_guid); | |
346 | ||
347 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
348 | err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); | |
3f89a643 AS |
349 | break; |
350 | ||
351 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
352 | err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); | |
353 | break; | |
1b5daf11 MD |
354 | |
355 | default: | |
356 | return -EINVAL; | |
357 | } | |
3f89a643 AS |
358 | |
359 | if (!err) | |
360 | *sys_image_guid = cpu_to_be64(tmp); | |
361 | ||
362 | return err; | |
363 | ||
1b5daf11 MD |
364 | } |
365 | ||
366 | static int mlx5_query_max_pkeys(struct ib_device *ibdev, | |
367 | u16 *max_pkeys) | |
368 | { | |
369 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
370 | struct mlx5_core_dev *mdev = dev->mdev; | |
371 | ||
372 | switch (mlx5_get_vport_access_method(ibdev)) { | |
373 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
374 | return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); | |
375 | ||
376 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
377 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
378 | *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, | |
379 | pkey_table_size)); | |
380 | return 0; | |
381 | ||
382 | default: | |
383 | return -EINVAL; | |
384 | } | |
385 | } | |
386 | ||
387 | static int mlx5_query_vendor_id(struct ib_device *ibdev, | |
388 | u32 *vendor_id) | |
389 | { | |
390 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
391 | ||
392 | switch (mlx5_get_vport_access_method(ibdev)) { | |
393 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
394 | return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); | |
395 | ||
396 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
397 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
398 | return mlx5_core_query_vendor_id(dev->mdev, vendor_id); | |
399 | ||
400 | default: | |
401 | return -EINVAL; | |
402 | } | |
403 | } | |
404 | ||
405 | static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, | |
406 | __be64 *node_guid) | |
407 | { | |
408 | u64 tmp; | |
409 | int err; | |
410 | ||
411 | switch (mlx5_get_vport_access_method(&dev->ib_dev)) { | |
412 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
413 | return mlx5_query_mad_ifc_node_guid(dev, node_guid); | |
414 | ||
415 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
416 | err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); | |
3f89a643 AS |
417 | break; |
418 | ||
419 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
420 | err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); | |
421 | break; | |
1b5daf11 MD |
422 | |
423 | default: | |
424 | return -EINVAL; | |
425 | } | |
3f89a643 AS |
426 | |
427 | if (!err) | |
428 | *node_guid = cpu_to_be64(tmp); | |
429 | ||
430 | return err; | |
1b5daf11 MD |
431 | } |
432 | ||
433 | struct mlx5_reg_node_desc { | |
434 | u8 desc[64]; | |
435 | }; | |
436 | ||
437 | static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) | |
438 | { | |
439 | struct mlx5_reg_node_desc in; | |
440 | ||
441 | if (mlx5_use_mad_ifc(dev)) | |
442 | return mlx5_query_mad_ifc_node_desc(dev, node_desc); | |
443 | ||
444 | memset(&in, 0, sizeof(in)); | |
445 | ||
446 | return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, | |
447 | sizeof(struct mlx5_reg_node_desc), | |
448 | MLX5_REG_NODE_DESC, 0, 0); | |
449 | } | |
450 | ||
e126ba97 | 451 | static int mlx5_ib_query_device(struct ib_device *ibdev, |
2528e33e MB |
452 | struct ib_device_attr *props, |
453 | struct ib_udata *uhw) | |
e126ba97 EC |
454 | { |
455 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
938fe83c | 456 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 EC |
457 | int err = -ENOMEM; |
458 | int max_rq_sg; | |
459 | int max_sq_sg; | |
e0238a6a | 460 | u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); |
402ca536 BW |
461 | struct mlx5_ib_query_device_resp resp = {}; |
462 | size_t resp_len; | |
463 | u64 max_tso; | |
e126ba97 | 464 | |
402ca536 BW |
465 | resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); |
466 | if (uhw->outlen && uhw->outlen < resp_len) | |
467 | return -EINVAL; | |
468 | else | |
469 | resp.response_length = resp_len; | |
470 | ||
471 | if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) | |
2528e33e MB |
472 | return -EINVAL; |
473 | ||
1b5daf11 MD |
474 | memset(props, 0, sizeof(*props)); |
475 | err = mlx5_query_system_image_guid(ibdev, | |
476 | &props->sys_image_guid); | |
477 | if (err) | |
478 | return err; | |
e126ba97 | 479 | |
1b5daf11 | 480 | err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); |
e126ba97 | 481 | if (err) |
1b5daf11 | 482 | return err; |
e126ba97 | 483 | |
1b5daf11 MD |
484 | err = mlx5_query_vendor_id(ibdev, &props->vendor_id); |
485 | if (err) | |
486 | return err; | |
e126ba97 | 487 | |
9603b61d JM |
488 | props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | |
489 | (fw_rev_min(dev->mdev) << 16) | | |
490 | fw_rev_sub(dev->mdev); | |
e126ba97 EC |
491 | props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | |
492 | IB_DEVICE_PORT_ACTIVE_EVENT | | |
493 | IB_DEVICE_SYS_IMAGE_GUID | | |
1a4c3a3d | 494 | IB_DEVICE_RC_RNR_NAK_GEN; |
938fe83c SM |
495 | |
496 | if (MLX5_CAP_GEN(mdev, pkv)) | |
e126ba97 | 497 | props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; |
938fe83c | 498 | if (MLX5_CAP_GEN(mdev, qkv)) |
e126ba97 | 499 | props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; |
938fe83c | 500 | if (MLX5_CAP_GEN(mdev, apm)) |
e126ba97 | 501 | props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; |
938fe83c | 502 | if (MLX5_CAP_GEN(mdev, xrc)) |
e126ba97 | 503 | props->device_cap_flags |= IB_DEVICE_XRC; |
d2370e0a MB |
504 | if (MLX5_CAP_GEN(mdev, imaicl)) { |
505 | props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | | |
506 | IB_DEVICE_MEM_WINDOW_TYPE_2B; | |
507 | props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); | |
b005d316 SG |
508 | /* We support 'Gappy' memory registration too */ |
509 | props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; | |
d2370e0a | 510 | } |
e126ba97 | 511 | props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; |
938fe83c | 512 | if (MLX5_CAP_GEN(mdev, sho)) { |
2dea9094 SG |
513 | props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; |
514 | /* At this stage no support for signature handover */ | |
515 | props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | | |
516 | IB_PROT_T10DIF_TYPE_2 | | |
517 | IB_PROT_T10DIF_TYPE_3; | |
518 | props->sig_guard_cap = IB_GUARD_T10DIF_CRC | | |
519 | IB_GUARD_T10DIF_CSUM; | |
520 | } | |
938fe83c | 521 | if (MLX5_CAP_GEN(mdev, block_lb_mc)) |
f360d88a | 522 | props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; |
e126ba97 | 523 | |
402ca536 BW |
524 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { |
525 | if (MLX5_CAP_ETH(mdev, csum_cap)) | |
88115fe7 BW |
526 | props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; |
527 | ||
402ca536 BW |
528 | if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { |
529 | max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); | |
530 | if (max_tso) { | |
531 | resp.tso_caps.max_tso = 1 << max_tso; | |
532 | resp.tso_caps.supported_qpts |= | |
533 | 1 << IB_QPT_RAW_PACKET; | |
534 | resp.response_length += sizeof(resp.tso_caps); | |
535 | } | |
536 | } | |
537 | } | |
538 | ||
f0313965 ES |
539 | if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { |
540 | props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; | |
541 | props->device_cap_flags |= IB_DEVICE_UD_TSO; | |
542 | } | |
543 | ||
cff5a0f3 MD |
544 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && |
545 | MLX5_CAP_ETH(dev->mdev, scatter_fcs)) | |
546 | props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; | |
547 | ||
da6d6ba3 MG |
548 | if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) |
549 | props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; | |
550 | ||
1b5daf11 MD |
551 | props->vendor_part_id = mdev->pdev->device; |
552 | props->hw_ver = mdev->pdev->revision; | |
e126ba97 EC |
553 | |
554 | props->max_mr_size = ~0ull; | |
e0238a6a | 555 | props->page_size_cap = ~(min_page_size - 1); |
938fe83c SM |
556 | props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); |
557 | props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); | |
558 | max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / | |
559 | sizeof(struct mlx5_wqe_data_seg); | |
560 | max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - | |
561 | sizeof(struct mlx5_wqe_ctrl_seg)) / | |
562 | sizeof(struct mlx5_wqe_data_seg); | |
e126ba97 | 563 | props->max_sge = min(max_rq_sg, max_sq_sg); |
986ef95e | 564 | props->max_sge_rd = MLX5_MAX_SGE_RD; |
938fe83c | 565 | props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); |
9f177686 | 566 | props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; |
938fe83c SM |
567 | props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); |
568 | props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); | |
569 | props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); | |
570 | props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); | |
571 | props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); | |
572 | props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; | |
573 | props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); | |
e126ba97 | 574 | props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; |
e126ba97 | 575 | props->max_srq_sge = max_rq_sg - 1; |
911f4331 SG |
576 | props->max_fast_reg_page_list_len = |
577 | 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); | |
da7525d2 | 578 | get_atomic_caps(dev, props); |
81bea28f | 579 | props->masked_atomic_cap = IB_ATOMIC_NONE; |
938fe83c SM |
580 | props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); |
581 | props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); | |
e126ba97 EC |
582 | props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * |
583 | props->max_mcast_grp; | |
584 | props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ | |
7c60bcbb MB |
585 | props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); |
586 | props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; | |
e126ba97 | 587 | |
8cdd312c | 588 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
938fe83c | 589 | if (MLX5_CAP_GEN(mdev, pg)) |
8cdd312c HE |
590 | props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; |
591 | props->odp_caps = dev->odp_caps; | |
592 | #endif | |
593 | ||
051f2630 LR |
594 | if (MLX5_CAP_GEN(mdev, cd)) |
595 | props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; | |
596 | ||
eff901d3 EC |
597 | if (!mlx5_core_is_pf(mdev)) |
598 | props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; | |
599 | ||
402ca536 BW |
600 | if (uhw->outlen) { |
601 | err = ib_copy_to_udata(uhw, &resp, resp.response_length); | |
602 | ||
603 | if (err) | |
604 | return err; | |
605 | } | |
606 | ||
1b5daf11 | 607 | return 0; |
e126ba97 EC |
608 | } |
609 | ||
1b5daf11 MD |
610 | enum mlx5_ib_width { |
611 | MLX5_IB_WIDTH_1X = 1 << 0, | |
612 | MLX5_IB_WIDTH_2X = 1 << 1, | |
613 | MLX5_IB_WIDTH_4X = 1 << 2, | |
614 | MLX5_IB_WIDTH_8X = 1 << 3, | |
615 | MLX5_IB_WIDTH_12X = 1 << 4 | |
616 | }; | |
617 | ||
618 | static int translate_active_width(struct ib_device *ibdev, u8 active_width, | |
619 | u8 *ib_width) | |
e126ba97 EC |
620 | { |
621 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
1b5daf11 MD |
622 | int err = 0; |
623 | ||
624 | if (active_width & MLX5_IB_WIDTH_1X) { | |
625 | *ib_width = IB_WIDTH_1X; | |
626 | } else if (active_width & MLX5_IB_WIDTH_2X) { | |
627 | mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", | |
628 | (int)active_width); | |
629 | err = -EINVAL; | |
630 | } else if (active_width & MLX5_IB_WIDTH_4X) { | |
631 | *ib_width = IB_WIDTH_4X; | |
632 | } else if (active_width & MLX5_IB_WIDTH_8X) { | |
633 | *ib_width = IB_WIDTH_8X; | |
634 | } else if (active_width & MLX5_IB_WIDTH_12X) { | |
635 | *ib_width = IB_WIDTH_12X; | |
636 | } else { | |
637 | mlx5_ib_dbg(dev, "Invalid active_width %d\n", | |
638 | (int)active_width); | |
639 | err = -EINVAL; | |
e126ba97 EC |
640 | } |
641 | ||
1b5daf11 MD |
642 | return err; |
643 | } | |
e126ba97 | 644 | |
1b5daf11 MD |
645 | static int mlx5_mtu_to_ib_mtu(int mtu) |
646 | { | |
647 | switch (mtu) { | |
648 | case 256: return 1; | |
649 | case 512: return 2; | |
650 | case 1024: return 3; | |
651 | case 2048: return 4; | |
652 | case 4096: return 5; | |
653 | default: | |
654 | pr_warn("invalid mtu\n"); | |
655 | return -1; | |
e126ba97 | 656 | } |
1b5daf11 | 657 | } |
e126ba97 | 658 | |
1b5daf11 MD |
659 | enum ib_max_vl_num { |
660 | __IB_MAX_VL_0 = 1, | |
661 | __IB_MAX_VL_0_1 = 2, | |
662 | __IB_MAX_VL_0_3 = 3, | |
663 | __IB_MAX_VL_0_7 = 4, | |
664 | __IB_MAX_VL_0_14 = 5, | |
665 | }; | |
e126ba97 | 666 | |
1b5daf11 MD |
667 | enum mlx5_vl_hw_cap { |
668 | MLX5_VL_HW_0 = 1, | |
669 | MLX5_VL_HW_0_1 = 2, | |
670 | MLX5_VL_HW_0_2 = 3, | |
671 | MLX5_VL_HW_0_3 = 4, | |
672 | MLX5_VL_HW_0_4 = 5, | |
673 | MLX5_VL_HW_0_5 = 6, | |
674 | MLX5_VL_HW_0_6 = 7, | |
675 | MLX5_VL_HW_0_7 = 8, | |
676 | MLX5_VL_HW_0_14 = 15 | |
677 | }; | |
e126ba97 | 678 | |
1b5daf11 MD |
679 | static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, |
680 | u8 *max_vl_num) | |
681 | { | |
682 | switch (vl_hw_cap) { | |
683 | case MLX5_VL_HW_0: | |
684 | *max_vl_num = __IB_MAX_VL_0; | |
685 | break; | |
686 | case MLX5_VL_HW_0_1: | |
687 | *max_vl_num = __IB_MAX_VL_0_1; | |
688 | break; | |
689 | case MLX5_VL_HW_0_3: | |
690 | *max_vl_num = __IB_MAX_VL_0_3; | |
691 | break; | |
692 | case MLX5_VL_HW_0_7: | |
693 | *max_vl_num = __IB_MAX_VL_0_7; | |
694 | break; | |
695 | case MLX5_VL_HW_0_14: | |
696 | *max_vl_num = __IB_MAX_VL_0_14; | |
697 | break; | |
e126ba97 | 698 | |
1b5daf11 MD |
699 | default: |
700 | return -EINVAL; | |
e126ba97 | 701 | } |
e126ba97 | 702 | |
1b5daf11 | 703 | return 0; |
e126ba97 EC |
704 | } |
705 | ||
1b5daf11 MD |
706 | static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, |
707 | struct ib_port_attr *props) | |
e126ba97 | 708 | { |
1b5daf11 MD |
709 | struct mlx5_ib_dev *dev = to_mdev(ibdev); |
710 | struct mlx5_core_dev *mdev = dev->mdev; | |
711 | struct mlx5_hca_vport_context *rep; | |
046339ea SM |
712 | u16 max_mtu; |
713 | u16 oper_mtu; | |
1b5daf11 MD |
714 | int err; |
715 | u8 ib_link_width_oper; | |
716 | u8 vl_hw_cap; | |
e126ba97 | 717 | |
1b5daf11 MD |
718 | rep = kzalloc(sizeof(*rep), GFP_KERNEL); |
719 | if (!rep) { | |
720 | err = -ENOMEM; | |
e126ba97 | 721 | goto out; |
e126ba97 | 722 | } |
e126ba97 | 723 | |
1b5daf11 | 724 | memset(props, 0, sizeof(*props)); |
e126ba97 | 725 | |
1b5daf11 | 726 | err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); |
e126ba97 EC |
727 | if (err) |
728 | goto out; | |
729 | ||
1b5daf11 MD |
730 | props->lid = rep->lid; |
731 | props->lmc = rep->lmc; | |
732 | props->sm_lid = rep->sm_lid; | |
733 | props->sm_sl = rep->sm_sl; | |
734 | props->state = rep->vport_state; | |
735 | props->phys_state = rep->port_physical_state; | |
736 | props->port_cap_flags = rep->cap_mask1; | |
737 | props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); | |
738 | props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); | |
739 | props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); | |
740 | props->bad_pkey_cntr = rep->pkey_violation_counter; | |
741 | props->qkey_viol_cntr = rep->qkey_violation_counter; | |
742 | props->subnet_timeout = rep->subnet_timeout; | |
743 | props->init_type_reply = rep->init_type_reply; | |
eff901d3 | 744 | props->grh_required = rep->grh_required; |
e126ba97 | 745 | |
1b5daf11 MD |
746 | err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); |
747 | if (err) | |
e126ba97 | 748 | goto out; |
e126ba97 | 749 | |
1b5daf11 MD |
750 | err = translate_active_width(ibdev, ib_link_width_oper, |
751 | &props->active_width); | |
752 | if (err) | |
753 | goto out; | |
754 | err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB, | |
755 | port); | |
e126ba97 EC |
756 | if (err) |
757 | goto out; | |
758 | ||
facc9699 | 759 | mlx5_query_port_max_mtu(mdev, &max_mtu, port); |
e126ba97 | 760 | |
1b5daf11 | 761 | props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); |
e126ba97 | 762 | |
facc9699 | 763 | mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); |
e126ba97 | 764 | |
1b5daf11 | 765 | props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); |
e126ba97 | 766 | |
1b5daf11 MD |
767 | err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); |
768 | if (err) | |
769 | goto out; | |
e126ba97 | 770 | |
1b5daf11 MD |
771 | err = translate_max_vl_num(ibdev, vl_hw_cap, |
772 | &props->max_vl_num); | |
e126ba97 | 773 | out: |
1b5daf11 | 774 | kfree(rep); |
e126ba97 EC |
775 | return err; |
776 | } | |
777 | ||
1b5daf11 MD |
778 | int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, |
779 | struct ib_port_attr *props) | |
e126ba97 | 780 | { |
1b5daf11 MD |
781 | switch (mlx5_get_vport_access_method(ibdev)) { |
782 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
783 | return mlx5_query_mad_ifc_port(ibdev, port, props); | |
e126ba97 | 784 | |
1b5daf11 MD |
785 | case MLX5_VPORT_ACCESS_METHOD_HCA: |
786 | return mlx5_query_hca_port(ibdev, port, props); | |
e126ba97 | 787 | |
3f89a643 AS |
788 | case MLX5_VPORT_ACCESS_METHOD_NIC: |
789 | return mlx5_query_port_roce(ibdev, port, props); | |
790 | ||
1b5daf11 MD |
791 | default: |
792 | return -EINVAL; | |
793 | } | |
794 | } | |
e126ba97 | 795 | |
1b5daf11 MD |
796 | static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, |
797 | union ib_gid *gid) | |
798 | { | |
799 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
800 | struct mlx5_core_dev *mdev = dev->mdev; | |
e126ba97 | 801 | |
1b5daf11 MD |
802 | switch (mlx5_get_vport_access_method(ibdev)) { |
803 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
804 | return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); | |
e126ba97 | 805 | |
1b5daf11 MD |
806 | case MLX5_VPORT_ACCESS_METHOD_HCA: |
807 | return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); | |
808 | ||
809 | default: | |
810 | return -EINVAL; | |
811 | } | |
e126ba97 | 812 | |
e126ba97 EC |
813 | } |
814 | ||
1b5daf11 MD |
815 | static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, |
816 | u16 *pkey) | |
817 | { | |
818 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
819 | struct mlx5_core_dev *mdev = dev->mdev; | |
820 | ||
821 | switch (mlx5_get_vport_access_method(ibdev)) { | |
822 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
823 | return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); | |
824 | ||
825 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
826 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
827 | return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, | |
828 | pkey); | |
829 | default: | |
830 | return -EINVAL; | |
831 | } | |
832 | } | |
e126ba97 EC |
833 | |
834 | static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, | |
835 | struct ib_device_modify *props) | |
836 | { | |
837 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
838 | struct mlx5_reg_node_desc in; | |
839 | struct mlx5_reg_node_desc out; | |
840 | int err; | |
841 | ||
842 | if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) | |
843 | return -EOPNOTSUPP; | |
844 | ||
845 | if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) | |
846 | return 0; | |
847 | ||
848 | /* | |
849 | * If possible, pass node desc to FW, so it can generate | |
850 | * a 144 trap. If cmd fails, just ignore. | |
851 | */ | |
852 | memcpy(&in, props->node_desc, 64); | |
9603b61d | 853 | err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, |
e126ba97 EC |
854 | sizeof(out), MLX5_REG_NODE_DESC, 0, 1); |
855 | if (err) | |
856 | return err; | |
857 | ||
858 | memcpy(ibdev->node_desc, props->node_desc, 64); | |
859 | ||
860 | return err; | |
861 | } | |
862 | ||
863 | static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, | |
864 | struct ib_port_modify *props) | |
865 | { | |
866 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
867 | struct ib_port_attr attr; | |
868 | u32 tmp; | |
869 | int err; | |
870 | ||
871 | mutex_lock(&dev->cap_mask_mutex); | |
872 | ||
873 | err = mlx5_ib_query_port(ibdev, port, &attr); | |
874 | if (err) | |
875 | goto out; | |
876 | ||
877 | tmp = (attr.port_cap_flags | props->set_port_cap_mask) & | |
878 | ~props->clr_port_cap_mask; | |
879 | ||
9603b61d | 880 | err = mlx5_set_port_caps(dev->mdev, port, tmp); |
e126ba97 EC |
881 | |
882 | out: | |
883 | mutex_unlock(&dev->cap_mask_mutex); | |
884 | return err; | |
885 | } | |
886 | ||
887 | static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, | |
888 | struct ib_udata *udata) | |
889 | { | |
890 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
b368d7cb MB |
891 | struct mlx5_ib_alloc_ucontext_req_v2 req = {}; |
892 | struct mlx5_ib_alloc_ucontext_resp resp = {}; | |
e126ba97 EC |
893 | struct mlx5_ib_ucontext *context; |
894 | struct mlx5_uuar_info *uuari; | |
895 | struct mlx5_uar *uars; | |
c1be5232 | 896 | int gross_uuars; |
e126ba97 | 897 | int num_uars; |
78c0f98c | 898 | int ver; |
e126ba97 EC |
899 | int uuarn; |
900 | int err; | |
901 | int i; | |
f241e749 | 902 | size_t reqlen; |
a168a41c MD |
903 | size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, |
904 | max_cqe_version); | |
e126ba97 EC |
905 | |
906 | if (!dev->ib_active) | |
907 | return ERR_PTR(-EAGAIN); | |
908 | ||
dfbee859 HA |
909 | if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) |
910 | return ERR_PTR(-EINVAL); | |
911 | ||
78c0f98c EC |
912 | reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); |
913 | if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) | |
914 | ver = 0; | |
a168a41c | 915 | else if (reqlen >= min_req_v2) |
78c0f98c EC |
916 | ver = 2; |
917 | else | |
918 | return ERR_PTR(-EINVAL); | |
919 | ||
b368d7cb | 920 | err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); |
e126ba97 EC |
921 | if (err) |
922 | return ERR_PTR(err); | |
923 | ||
b368d7cb | 924 | if (req.flags) |
78c0f98c EC |
925 | return ERR_PTR(-EINVAL); |
926 | ||
e126ba97 EC |
927 | if (req.total_num_uuars > MLX5_MAX_UUARS) |
928 | return ERR_PTR(-ENOMEM); | |
929 | ||
930 | if (req.total_num_uuars == 0) | |
931 | return ERR_PTR(-EINVAL); | |
932 | ||
f72300c5 | 933 | if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) |
b368d7cb MB |
934 | return ERR_PTR(-EOPNOTSUPP); |
935 | ||
936 | if (reqlen > sizeof(req) && | |
937 | !ib_is_udata_cleared(udata, sizeof(req), | |
dfbee859 | 938 | reqlen - sizeof(req))) |
b368d7cb MB |
939 | return ERR_PTR(-EOPNOTSUPP); |
940 | ||
c1be5232 EC |
941 | req.total_num_uuars = ALIGN(req.total_num_uuars, |
942 | MLX5_NON_FP_BF_REGS_PER_PAGE); | |
e126ba97 EC |
943 | if (req.num_low_latency_uuars > req.total_num_uuars - 1) |
944 | return ERR_PTR(-EINVAL); | |
945 | ||
c1be5232 EC |
946 | num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; |
947 | gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; | |
938fe83c | 948 | resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); |
2cc6ad5f NO |
949 | if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) |
950 | resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); | |
938fe83c SM |
951 | resp.cache_line_size = L1_CACHE_BYTES; |
952 | resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); | |
953 | resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); | |
954 | resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); | |
955 | resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); | |
956 | resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); | |
f72300c5 HA |
957 | resp.cqe_version = min_t(__u8, |
958 | (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), | |
959 | req.max_cqe_version); | |
b368d7cb MB |
960 | resp.response_length = min(offsetof(typeof(resp), response_length) + |
961 | sizeof(resp.response_length), udata->outlen); | |
e126ba97 EC |
962 | |
963 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
964 | if (!context) | |
965 | return ERR_PTR(-ENOMEM); | |
966 | ||
967 | uuari = &context->uuari; | |
968 | mutex_init(&uuari->lock); | |
969 | uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); | |
970 | if (!uars) { | |
971 | err = -ENOMEM; | |
972 | goto out_ctx; | |
973 | } | |
974 | ||
c1be5232 | 975 | uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), |
e126ba97 EC |
976 | sizeof(*uuari->bitmap), |
977 | GFP_KERNEL); | |
978 | if (!uuari->bitmap) { | |
979 | err = -ENOMEM; | |
980 | goto out_uar_ctx; | |
981 | } | |
982 | /* | |
983 | * clear all fast path uuars | |
984 | */ | |
c1be5232 | 985 | for (i = 0; i < gross_uuars; i++) { |
e126ba97 EC |
986 | uuarn = i & 3; |
987 | if (uuarn == 2 || uuarn == 3) | |
988 | set_bit(i, uuari->bitmap); | |
989 | } | |
990 | ||
c1be5232 | 991 | uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); |
e126ba97 EC |
992 | if (!uuari->count) { |
993 | err = -ENOMEM; | |
994 | goto out_bitmap; | |
995 | } | |
996 | ||
997 | for (i = 0; i < num_uars; i++) { | |
9603b61d | 998 | err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); |
e126ba97 EC |
999 | if (err) |
1000 | goto out_count; | |
1001 | } | |
1002 | ||
b4cfe447 HE |
1003 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1004 | context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; | |
1005 | #endif | |
1006 | ||
146d2f1a | 1007 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { |
1008 | err = mlx5_core_alloc_transport_domain(dev->mdev, | |
1009 | &context->tdn); | |
1010 | if (err) | |
1011 | goto out_uars; | |
1012 | } | |
1013 | ||
7c2344c3 | 1014 | INIT_LIST_HEAD(&context->vma_private_list); |
e126ba97 EC |
1015 | INIT_LIST_HEAD(&context->db_page_list); |
1016 | mutex_init(&context->db_page_mutex); | |
1017 | ||
1018 | resp.tot_uuars = req.total_num_uuars; | |
938fe83c | 1019 | resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); |
b368d7cb | 1020 | |
f72300c5 HA |
1021 | if (field_avail(typeof(resp), cqe_version, udata->outlen)) |
1022 | resp.response_length += sizeof(resp.cqe_version); | |
b368d7cb | 1023 | |
402ca536 BW |
1024 | if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { |
1025 | resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE; | |
1026 | resp.response_length += sizeof(resp.cmds_supp_uhw); | |
1027 | } | |
1028 | ||
bc5c6eed NO |
1029 | /* |
1030 | * We don't want to expose information from the PCI bar that is located | |
1031 | * after 4096 bytes, so if the arch only supports larger pages, let's | |
1032 | * pretend we don't support reading the HCA's core clock. This is also | |
1033 | * forced by mmap function. | |
1034 | */ | |
1035 | if (PAGE_SIZE <= 4096 && | |
1036 | field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { | |
b368d7cb MB |
1037 | resp.comp_mask |= |
1038 | MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; | |
1039 | resp.hca_core_clock_offset = | |
1040 | offsetof(struct mlx5_init_seg, internal_timer_h) % | |
1041 | PAGE_SIZE; | |
f72300c5 | 1042 | resp.response_length += sizeof(resp.hca_core_clock_offset) + |
402ca536 | 1043 | sizeof(resp.reserved2); |
b368d7cb MB |
1044 | } |
1045 | ||
1046 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
e126ba97 | 1047 | if (err) |
146d2f1a | 1048 | goto out_td; |
e126ba97 | 1049 | |
78c0f98c | 1050 | uuari->ver = ver; |
e126ba97 EC |
1051 | uuari->num_low_latency_uuars = req.num_low_latency_uuars; |
1052 | uuari->uars = uars; | |
1053 | uuari->num_uars = num_uars; | |
f72300c5 HA |
1054 | context->cqe_version = resp.cqe_version; |
1055 | ||
e126ba97 EC |
1056 | return &context->ibucontext; |
1057 | ||
146d2f1a | 1058 | out_td: |
1059 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) | |
1060 | mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); | |
1061 | ||
e126ba97 EC |
1062 | out_uars: |
1063 | for (i--; i >= 0; i--) | |
9603b61d | 1064 | mlx5_cmd_free_uar(dev->mdev, uars[i].index); |
e126ba97 EC |
1065 | out_count: |
1066 | kfree(uuari->count); | |
1067 | ||
1068 | out_bitmap: | |
1069 | kfree(uuari->bitmap); | |
1070 | ||
1071 | out_uar_ctx: | |
1072 | kfree(uars); | |
1073 | ||
1074 | out_ctx: | |
1075 | kfree(context); | |
1076 | return ERR_PTR(err); | |
1077 | } | |
1078 | ||
1079 | static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) | |
1080 | { | |
1081 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1082 | struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); | |
1083 | struct mlx5_uuar_info *uuari = &context->uuari; | |
1084 | int i; | |
1085 | ||
146d2f1a | 1086 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) |
1087 | mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); | |
1088 | ||
e126ba97 | 1089 | for (i = 0; i < uuari->num_uars; i++) { |
9603b61d | 1090 | if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) |
e126ba97 EC |
1091 | mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); |
1092 | } | |
1093 | ||
1094 | kfree(uuari->count); | |
1095 | kfree(uuari->bitmap); | |
1096 | kfree(uuari->uars); | |
1097 | kfree(context); | |
1098 | ||
1099 | return 0; | |
1100 | } | |
1101 | ||
1102 | static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) | |
1103 | { | |
9603b61d | 1104 | return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; |
e126ba97 EC |
1105 | } |
1106 | ||
1107 | static int get_command(unsigned long offset) | |
1108 | { | |
1109 | return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; | |
1110 | } | |
1111 | ||
1112 | static int get_arg(unsigned long offset) | |
1113 | { | |
1114 | return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); | |
1115 | } | |
1116 | ||
1117 | static int get_index(unsigned long offset) | |
1118 | { | |
1119 | return get_arg(offset); | |
1120 | } | |
1121 | ||
7c2344c3 MG |
1122 | static void mlx5_ib_vma_open(struct vm_area_struct *area) |
1123 | { | |
1124 | /* vma_open is called when a new VMA is created on top of our VMA. This | |
1125 | * is done through either mremap flow or split_vma (usually due to | |
1126 | * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, | |
1127 | * as this VMA is strongly hardware related. Therefore we set the | |
1128 | * vm_ops of the newly created/cloned VMA to NULL, to prevent it from | |
1129 | * calling us again and trying to do incorrect actions. We assume that | |
1130 | * the original VMA size is exactly a single page, and therefore all | |
1131 | * "splitting" operation will not happen to it. | |
1132 | */ | |
1133 | area->vm_ops = NULL; | |
1134 | } | |
1135 | ||
1136 | static void mlx5_ib_vma_close(struct vm_area_struct *area) | |
1137 | { | |
1138 | struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; | |
1139 | ||
1140 | /* It's guaranteed that all VMAs opened on a FD are closed before the | |
1141 | * file itself is closed, therefore no sync is needed with the regular | |
1142 | * closing flow. (e.g. mlx5 ib_dealloc_ucontext) | |
1143 | * However need a sync with accessing the vma as part of | |
1144 | * mlx5_ib_disassociate_ucontext. | |
1145 | * The close operation is usually called under mm->mmap_sem except when | |
1146 | * process is exiting. | |
1147 | * The exiting case is handled explicitly as part of | |
1148 | * mlx5_ib_disassociate_ucontext. | |
1149 | */ | |
1150 | mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; | |
1151 | ||
1152 | /* setting the vma context pointer to null in the mlx5_ib driver's | |
1153 | * private data, to protect a race condition in | |
1154 | * mlx5_ib_disassociate_ucontext(). | |
1155 | */ | |
1156 | mlx5_ib_vma_priv_data->vma = NULL; | |
1157 | list_del(&mlx5_ib_vma_priv_data->list); | |
1158 | kfree(mlx5_ib_vma_priv_data); | |
1159 | } | |
1160 | ||
1161 | static const struct vm_operations_struct mlx5_ib_vm_ops = { | |
1162 | .open = mlx5_ib_vma_open, | |
1163 | .close = mlx5_ib_vma_close | |
1164 | }; | |
1165 | ||
1166 | static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, | |
1167 | struct mlx5_ib_ucontext *ctx) | |
1168 | { | |
1169 | struct mlx5_ib_vma_private_data *vma_prv; | |
1170 | struct list_head *vma_head = &ctx->vma_private_list; | |
1171 | ||
1172 | vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); | |
1173 | if (!vma_prv) | |
1174 | return -ENOMEM; | |
1175 | ||
1176 | vma_prv->vma = vma; | |
1177 | vma->vm_private_data = vma_prv; | |
1178 | vma->vm_ops = &mlx5_ib_vm_ops; | |
1179 | ||
1180 | list_add(&vma_prv->list, vma_head); | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
1185 | static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) | |
1186 | { | |
1187 | int ret; | |
1188 | struct vm_area_struct *vma; | |
1189 | struct mlx5_ib_vma_private_data *vma_private, *n; | |
1190 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1191 | struct task_struct *owning_process = NULL; | |
1192 | struct mm_struct *owning_mm = NULL; | |
1193 | ||
1194 | owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); | |
1195 | if (!owning_process) | |
1196 | return; | |
1197 | ||
1198 | owning_mm = get_task_mm(owning_process); | |
1199 | if (!owning_mm) { | |
1200 | pr_info("no mm, disassociate ucontext is pending task termination\n"); | |
1201 | while (1) { | |
1202 | put_task_struct(owning_process); | |
1203 | usleep_range(1000, 2000); | |
1204 | owning_process = get_pid_task(ibcontext->tgid, | |
1205 | PIDTYPE_PID); | |
1206 | if (!owning_process || | |
1207 | owning_process->state == TASK_DEAD) { | |
1208 | pr_info("disassociate ucontext done, task was terminated\n"); | |
1209 | /* in case task was dead need to release the | |
1210 | * task struct. | |
1211 | */ | |
1212 | if (owning_process) | |
1213 | put_task_struct(owning_process); | |
1214 | return; | |
1215 | } | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | /* need to protect from a race on closing the vma as part of | |
1220 | * mlx5_ib_vma_close. | |
1221 | */ | |
1222 | down_read(&owning_mm->mmap_sem); | |
1223 | list_for_each_entry_safe(vma_private, n, &context->vma_private_list, | |
1224 | list) { | |
1225 | vma = vma_private->vma; | |
1226 | ret = zap_vma_ptes(vma, vma->vm_start, | |
1227 | PAGE_SIZE); | |
1228 | WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__); | |
1229 | /* context going to be destroyed, should | |
1230 | * not access ops any more. | |
1231 | */ | |
1232 | vma->vm_ops = NULL; | |
1233 | list_del(&vma_private->list); | |
1234 | kfree(vma_private); | |
1235 | } | |
1236 | up_read(&owning_mm->mmap_sem); | |
1237 | mmput(owning_mm); | |
1238 | put_task_struct(owning_process); | |
1239 | } | |
1240 | ||
37aa5c36 GL |
1241 | static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) |
1242 | { | |
1243 | switch (cmd) { | |
1244 | case MLX5_IB_MMAP_WC_PAGE: | |
1245 | return "WC"; | |
1246 | case MLX5_IB_MMAP_REGULAR_PAGE: | |
1247 | return "best effort WC"; | |
1248 | case MLX5_IB_MMAP_NC_PAGE: | |
1249 | return "NC"; | |
1250 | default: | |
1251 | return NULL; | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, | |
7c2344c3 MG |
1256 | struct vm_area_struct *vma, |
1257 | struct mlx5_ib_ucontext *context) | |
37aa5c36 | 1258 | { |
7c2344c3 | 1259 | struct mlx5_uuar_info *uuari = &context->uuari; |
37aa5c36 GL |
1260 | int err; |
1261 | unsigned long idx; | |
1262 | phys_addr_t pfn, pa; | |
1263 | pgprot_t prot; | |
1264 | ||
1265 | switch (cmd) { | |
1266 | case MLX5_IB_MMAP_WC_PAGE: | |
1267 | /* Some architectures don't support WC memory */ | |
1268 | #if defined(CONFIG_X86) | |
1269 | if (!pat_enabled()) | |
1270 | return -EPERM; | |
1271 | #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) | |
1272 | return -EPERM; | |
1273 | #endif | |
1274 | /* fall through */ | |
1275 | case MLX5_IB_MMAP_REGULAR_PAGE: | |
1276 | /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ | |
1277 | prot = pgprot_writecombine(vma->vm_page_prot); | |
1278 | break; | |
1279 | case MLX5_IB_MMAP_NC_PAGE: | |
1280 | prot = pgprot_noncached(vma->vm_page_prot); | |
1281 | break; | |
1282 | default: | |
1283 | return -EINVAL; | |
1284 | } | |
1285 | ||
1286 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) | |
1287 | return -EINVAL; | |
1288 | ||
1289 | idx = get_index(vma->vm_pgoff); | |
1290 | if (idx >= uuari->num_uars) | |
1291 | return -EINVAL; | |
1292 | ||
1293 | pfn = uar_index2pfn(dev, uuari->uars[idx].index); | |
1294 | mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); | |
1295 | ||
1296 | vma->vm_page_prot = prot; | |
1297 | err = io_remap_pfn_range(vma, vma->vm_start, pfn, | |
1298 | PAGE_SIZE, vma->vm_page_prot); | |
1299 | if (err) { | |
1300 | mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n", | |
1301 | err, vma->vm_start, &pfn, mmap_cmd2str(cmd)); | |
1302 | return -EAGAIN; | |
1303 | } | |
1304 | ||
1305 | pa = pfn << PAGE_SHIFT; | |
1306 | mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd), | |
1307 | vma->vm_start, &pa); | |
1308 | ||
7c2344c3 | 1309 | return mlx5_ib_set_vma_data(vma, context); |
37aa5c36 GL |
1310 | } |
1311 | ||
e126ba97 EC |
1312 | static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) |
1313 | { | |
1314 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1315 | struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); | |
e126ba97 | 1316 | unsigned long command; |
e126ba97 EC |
1317 | phys_addr_t pfn; |
1318 | ||
1319 | command = get_command(vma->vm_pgoff); | |
1320 | switch (command) { | |
37aa5c36 GL |
1321 | case MLX5_IB_MMAP_WC_PAGE: |
1322 | case MLX5_IB_MMAP_NC_PAGE: | |
e126ba97 | 1323 | case MLX5_IB_MMAP_REGULAR_PAGE: |
7c2344c3 | 1324 | return uar_mmap(dev, command, vma, context); |
e126ba97 EC |
1325 | |
1326 | case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: | |
1327 | return -ENOSYS; | |
1328 | ||
d69e3bcf | 1329 | case MLX5_IB_MMAP_CORE_CLOCK: |
d69e3bcf MB |
1330 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) |
1331 | return -EINVAL; | |
1332 | ||
6cbac1e4 | 1333 | if (vma->vm_flags & VM_WRITE) |
d69e3bcf MB |
1334 | return -EPERM; |
1335 | ||
1336 | /* Don't expose to user-space information it shouldn't have */ | |
1337 | if (PAGE_SIZE > 4096) | |
1338 | return -EOPNOTSUPP; | |
1339 | ||
1340 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
1341 | pfn = (dev->mdev->iseg_base + | |
1342 | offsetof(struct mlx5_init_seg, internal_timer_h)) >> | |
1343 | PAGE_SHIFT; | |
1344 | if (io_remap_pfn_range(vma, vma->vm_start, pfn, | |
1345 | PAGE_SIZE, vma->vm_page_prot)) | |
1346 | return -EAGAIN; | |
1347 | ||
1348 | mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", | |
1349 | vma->vm_start, | |
1350 | (unsigned long long)pfn << PAGE_SHIFT); | |
1351 | break; | |
d69e3bcf | 1352 | |
e126ba97 EC |
1353 | default: |
1354 | return -EINVAL; | |
1355 | } | |
1356 | ||
1357 | return 0; | |
1358 | } | |
1359 | ||
e126ba97 EC |
1360 | static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, |
1361 | struct ib_ucontext *context, | |
1362 | struct ib_udata *udata) | |
1363 | { | |
1364 | struct mlx5_ib_alloc_pd_resp resp; | |
1365 | struct mlx5_ib_pd *pd; | |
1366 | int err; | |
1367 | ||
1368 | pd = kmalloc(sizeof(*pd), GFP_KERNEL); | |
1369 | if (!pd) | |
1370 | return ERR_PTR(-ENOMEM); | |
1371 | ||
9603b61d | 1372 | err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); |
e126ba97 EC |
1373 | if (err) { |
1374 | kfree(pd); | |
1375 | return ERR_PTR(err); | |
1376 | } | |
1377 | ||
1378 | if (context) { | |
1379 | resp.pdn = pd->pdn; | |
1380 | if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { | |
9603b61d | 1381 | mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); |
e126ba97 EC |
1382 | kfree(pd); |
1383 | return ERR_PTR(-EFAULT); | |
1384 | } | |
e126ba97 EC |
1385 | } |
1386 | ||
1387 | return &pd->ibpd; | |
1388 | } | |
1389 | ||
1390 | static int mlx5_ib_dealloc_pd(struct ib_pd *pd) | |
1391 | { | |
1392 | struct mlx5_ib_dev *mdev = to_mdev(pd->device); | |
1393 | struct mlx5_ib_pd *mpd = to_mpd(pd); | |
1394 | ||
9603b61d | 1395 | mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); |
e126ba97 EC |
1396 | kfree(mpd); |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
038d2ef8 MG |
1401 | static bool outer_header_zero(u32 *match_criteria) |
1402 | { | |
1403 | int size = MLX5_ST_SZ_BYTES(fte_match_param); | |
1404 | char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, | |
1405 | outer_headers); | |
1406 | ||
1407 | return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, | |
1408 | outer_headers_c + 1, | |
1409 | size - 1); | |
1410 | } | |
1411 | ||
1412 | static int parse_flow_attr(u32 *match_c, u32 *match_v, | |
1413 | union ib_flow_spec *ib_spec) | |
1414 | { | |
1415 | void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, | |
1416 | outer_headers); | |
1417 | void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
1418 | outer_headers); | |
1419 | switch (ib_spec->type) { | |
1420 | case IB_FLOW_SPEC_ETH: | |
1421 | if (ib_spec->size != sizeof(ib_spec->eth)) | |
1422 | return -EINVAL; | |
1423 | ||
1424 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1425 | dmac_47_16), | |
1426 | ib_spec->eth.mask.dst_mac); | |
1427 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1428 | dmac_47_16), | |
1429 | ib_spec->eth.val.dst_mac); | |
1430 | ||
1431 | if (ib_spec->eth.mask.vlan_tag) { | |
1432 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1433 | vlan_tag, 1); | |
1434 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1435 | vlan_tag, 1); | |
1436 | ||
1437 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1438 | first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); | |
1439 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1440 | first_vid, ntohs(ib_spec->eth.val.vlan_tag)); | |
1441 | ||
1442 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1443 | first_cfi, | |
1444 | ntohs(ib_spec->eth.mask.vlan_tag) >> 12); | |
1445 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1446 | first_cfi, | |
1447 | ntohs(ib_spec->eth.val.vlan_tag) >> 12); | |
1448 | ||
1449 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1450 | first_prio, | |
1451 | ntohs(ib_spec->eth.mask.vlan_tag) >> 13); | |
1452 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1453 | first_prio, | |
1454 | ntohs(ib_spec->eth.val.vlan_tag) >> 13); | |
1455 | } | |
1456 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1457 | ethertype, ntohs(ib_spec->eth.mask.ether_type)); | |
1458 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1459 | ethertype, ntohs(ib_spec->eth.val.ether_type)); | |
1460 | break; | |
1461 | case IB_FLOW_SPEC_IPV4: | |
1462 | if (ib_spec->size != sizeof(ib_spec->ipv4)) | |
1463 | return -EINVAL; | |
1464 | ||
1465 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1466 | ethertype, 0xffff); | |
1467 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1468 | ethertype, ETH_P_IP); | |
1469 | ||
1470 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1471 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
1472 | &ib_spec->ipv4.mask.src_ip, | |
1473 | sizeof(ib_spec->ipv4.mask.src_ip)); | |
1474 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1475 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
1476 | &ib_spec->ipv4.val.src_ip, | |
1477 | sizeof(ib_spec->ipv4.val.src_ip)); | |
1478 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1479 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
1480 | &ib_spec->ipv4.mask.dst_ip, | |
1481 | sizeof(ib_spec->ipv4.mask.dst_ip)); | |
1482 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1483 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
1484 | &ib_spec->ipv4.val.dst_ip, | |
1485 | sizeof(ib_spec->ipv4.val.dst_ip)); | |
1486 | break; | |
026bae0c MG |
1487 | case IB_FLOW_SPEC_IPV6: |
1488 | if (ib_spec->size != sizeof(ib_spec->ipv6)) | |
1489 | return -EINVAL; | |
1490 | ||
1491 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1492 | ethertype, 0xffff); | |
1493 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1494 | ethertype, ETH_P_IPV6); | |
1495 | ||
1496 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1497 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
1498 | &ib_spec->ipv6.mask.src_ip, | |
1499 | sizeof(ib_spec->ipv6.mask.src_ip)); | |
1500 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1501 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
1502 | &ib_spec->ipv6.val.src_ip, | |
1503 | sizeof(ib_spec->ipv6.val.src_ip)); | |
1504 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1505 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
1506 | &ib_spec->ipv6.mask.dst_ip, | |
1507 | sizeof(ib_spec->ipv6.mask.dst_ip)); | |
1508 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1509 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
1510 | &ib_spec->ipv6.val.dst_ip, | |
1511 | sizeof(ib_spec->ipv6.val.dst_ip)); | |
1512 | break; | |
038d2ef8 MG |
1513 | case IB_FLOW_SPEC_TCP: |
1514 | if (ib_spec->size != sizeof(ib_spec->tcp_udp)) | |
1515 | return -EINVAL; | |
1516 | ||
1517 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, | |
1518 | 0xff); | |
1519 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, | |
1520 | IPPROTO_TCP); | |
1521 | ||
1522 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, | |
1523 | ntohs(ib_spec->tcp_udp.mask.src_port)); | |
1524 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, | |
1525 | ntohs(ib_spec->tcp_udp.val.src_port)); | |
1526 | ||
1527 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, | |
1528 | ntohs(ib_spec->tcp_udp.mask.dst_port)); | |
1529 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, | |
1530 | ntohs(ib_spec->tcp_udp.val.dst_port)); | |
1531 | break; | |
1532 | case IB_FLOW_SPEC_UDP: | |
1533 | if (ib_spec->size != sizeof(ib_spec->tcp_udp)) | |
1534 | return -EINVAL; | |
1535 | ||
1536 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, | |
1537 | 0xff); | |
1538 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, | |
1539 | IPPROTO_UDP); | |
1540 | ||
1541 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, | |
1542 | ntohs(ib_spec->tcp_udp.mask.src_port)); | |
1543 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, | |
1544 | ntohs(ib_spec->tcp_udp.val.src_port)); | |
1545 | ||
1546 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, | |
1547 | ntohs(ib_spec->tcp_udp.mask.dst_port)); | |
1548 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, | |
1549 | ntohs(ib_spec->tcp_udp.val.dst_port)); | |
1550 | break; | |
1551 | default: | |
1552 | return -EINVAL; | |
1553 | } | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | /* If a flow could catch both multicast and unicast packets, | |
1559 | * it won't fall into the multicast flow steering table and this rule | |
1560 | * could steal other multicast packets. | |
1561 | */ | |
1562 | static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) | |
1563 | { | |
1564 | struct ib_flow_spec_eth *eth_spec; | |
1565 | ||
1566 | if (ib_attr->type != IB_FLOW_ATTR_NORMAL || | |
1567 | ib_attr->size < sizeof(struct ib_flow_attr) + | |
1568 | sizeof(struct ib_flow_spec_eth) || | |
1569 | ib_attr->num_of_specs < 1) | |
1570 | return false; | |
1571 | ||
1572 | eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); | |
1573 | if (eth_spec->type != IB_FLOW_SPEC_ETH || | |
1574 | eth_spec->size != sizeof(*eth_spec)) | |
1575 | return false; | |
1576 | ||
1577 | return is_multicast_ether_addr(eth_spec->mask.dst_mac) && | |
1578 | is_multicast_ether_addr(eth_spec->val.dst_mac); | |
1579 | } | |
1580 | ||
1581 | static bool is_valid_attr(struct ib_flow_attr *flow_attr) | |
1582 | { | |
1583 | union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); | |
1584 | bool has_ipv4_spec = false; | |
1585 | bool eth_type_ipv4 = true; | |
1586 | unsigned int spec_index; | |
1587 | ||
1588 | /* Validate that ethertype is correct */ | |
1589 | for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
1590 | if (ib_spec->type == IB_FLOW_SPEC_ETH && | |
1591 | ib_spec->eth.mask.ether_type) { | |
1592 | if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && | |
1593 | ib_spec->eth.val.ether_type == htons(ETH_P_IP))) | |
1594 | eth_type_ipv4 = false; | |
1595 | } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { | |
1596 | has_ipv4_spec = true; | |
1597 | } | |
1598 | ib_spec = (void *)ib_spec + ib_spec->size; | |
1599 | } | |
1600 | return !has_ipv4_spec || eth_type_ipv4; | |
1601 | } | |
1602 | ||
1603 | static void put_flow_table(struct mlx5_ib_dev *dev, | |
1604 | struct mlx5_ib_flow_prio *prio, bool ft_added) | |
1605 | { | |
1606 | prio->refcount -= !!ft_added; | |
1607 | if (!prio->refcount) { | |
1608 | mlx5_destroy_flow_table(prio->flow_table); | |
1609 | prio->flow_table = NULL; | |
1610 | } | |
1611 | } | |
1612 | ||
1613 | static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) | |
1614 | { | |
1615 | struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); | |
1616 | struct mlx5_ib_flow_handler *handler = container_of(flow_id, | |
1617 | struct mlx5_ib_flow_handler, | |
1618 | ibflow); | |
1619 | struct mlx5_ib_flow_handler *iter, *tmp; | |
1620 | ||
1621 | mutex_lock(&dev->flow_db.lock); | |
1622 | ||
1623 | list_for_each_entry_safe(iter, tmp, &handler->list, list) { | |
1624 | mlx5_del_flow_rule(iter->rule); | |
1625 | list_del(&iter->list); | |
1626 | kfree(iter); | |
1627 | } | |
1628 | ||
1629 | mlx5_del_flow_rule(handler->rule); | |
1630 | put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); | |
1631 | mutex_unlock(&dev->flow_db.lock); | |
1632 | ||
1633 | kfree(handler); | |
1634 | ||
1635 | return 0; | |
1636 | } | |
1637 | ||
35d19011 MG |
1638 | static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) |
1639 | { | |
1640 | priority *= 2; | |
1641 | if (!dont_trap) | |
1642 | priority++; | |
1643 | return priority; | |
1644 | } | |
1645 | ||
038d2ef8 MG |
1646 | #define MLX5_FS_MAX_TYPES 10 |
1647 | #define MLX5_FS_MAX_ENTRIES 32000UL | |
1648 | static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, | |
1649 | struct ib_flow_attr *flow_attr) | |
1650 | { | |
35d19011 | 1651 | bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; |
038d2ef8 MG |
1652 | struct mlx5_flow_namespace *ns = NULL; |
1653 | struct mlx5_ib_flow_prio *prio; | |
1654 | struct mlx5_flow_table *ft; | |
1655 | int num_entries; | |
1656 | int num_groups; | |
1657 | int priority; | |
1658 | int err = 0; | |
1659 | ||
1660 | if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { | |
35d19011 MG |
1661 | if (flow_is_multicast_only(flow_attr) && |
1662 | !dont_trap) | |
038d2ef8 MG |
1663 | priority = MLX5_IB_FLOW_MCAST_PRIO; |
1664 | else | |
35d19011 MG |
1665 | priority = ib_prio_to_core_prio(flow_attr->priority, |
1666 | dont_trap); | |
038d2ef8 MG |
1667 | ns = mlx5_get_flow_namespace(dev->mdev, |
1668 | MLX5_FLOW_NAMESPACE_BYPASS); | |
1669 | num_entries = MLX5_FS_MAX_ENTRIES; | |
1670 | num_groups = MLX5_FS_MAX_TYPES; | |
1671 | prio = &dev->flow_db.prios[priority]; | |
1672 | } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || | |
1673 | flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
1674 | ns = mlx5_get_flow_namespace(dev->mdev, | |
1675 | MLX5_FLOW_NAMESPACE_LEFTOVERS); | |
1676 | build_leftovers_ft_param(&priority, | |
1677 | &num_entries, | |
1678 | &num_groups); | |
1679 | prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; | |
1680 | } | |
1681 | ||
1682 | if (!ns) | |
1683 | return ERR_PTR(-ENOTSUPP); | |
1684 | ||
1685 | ft = prio->flow_table; | |
1686 | if (!ft) { | |
1687 | ft = mlx5_create_auto_grouped_flow_table(ns, priority, | |
1688 | num_entries, | |
d63cd286 MG |
1689 | num_groups, |
1690 | 0); | |
038d2ef8 MG |
1691 | |
1692 | if (!IS_ERR(ft)) { | |
1693 | prio->refcount = 0; | |
1694 | prio->flow_table = ft; | |
1695 | } else { | |
1696 | err = PTR_ERR(ft); | |
1697 | } | |
1698 | } | |
1699 | ||
1700 | return err ? ERR_PTR(err) : prio; | |
1701 | } | |
1702 | ||
1703 | static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, | |
1704 | struct mlx5_ib_flow_prio *ft_prio, | |
1705 | struct ib_flow_attr *flow_attr, | |
1706 | struct mlx5_flow_destination *dst) | |
1707 | { | |
1708 | struct mlx5_flow_table *ft = ft_prio->flow_table; | |
1709 | struct mlx5_ib_flow_handler *handler; | |
c5bb1730 | 1710 | struct mlx5_flow_spec *spec; |
038d2ef8 | 1711 | void *ib_flow = flow_attr + 1; |
038d2ef8 | 1712 | unsigned int spec_index; |
35d19011 | 1713 | u32 action; |
038d2ef8 MG |
1714 | int err = 0; |
1715 | ||
1716 | if (!is_valid_attr(flow_attr)) | |
1717 | return ERR_PTR(-EINVAL); | |
1718 | ||
c5bb1730 | 1719 | spec = mlx5_vzalloc(sizeof(*spec)); |
038d2ef8 | 1720 | handler = kzalloc(sizeof(*handler), GFP_KERNEL); |
c5bb1730 | 1721 | if (!handler || !spec) { |
038d2ef8 MG |
1722 | err = -ENOMEM; |
1723 | goto free; | |
1724 | } | |
1725 | ||
1726 | INIT_LIST_HEAD(&handler->list); | |
1727 | ||
1728 | for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
c5bb1730 MG |
1729 | err = parse_flow_attr(spec->match_criteria, |
1730 | spec->match_value, ib_flow); | |
038d2ef8 MG |
1731 | if (err < 0) |
1732 | goto free; | |
1733 | ||
1734 | ib_flow += ((union ib_flow_spec *)ib_flow)->size; | |
1735 | } | |
1736 | ||
1737 | /* Outer header support only */ | |
c5bb1730 MG |
1738 | spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria)) |
1739 | << 0; | |
35d19011 MG |
1740 | action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : |
1741 | MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; | |
c5bb1730 | 1742 | handler->rule = mlx5_add_flow_rule(ft, spec, |
35d19011 | 1743 | action, |
038d2ef8 MG |
1744 | MLX5_FS_DEFAULT_FLOW_TAG, |
1745 | dst); | |
1746 | ||
1747 | if (IS_ERR(handler->rule)) { | |
1748 | err = PTR_ERR(handler->rule); | |
1749 | goto free; | |
1750 | } | |
1751 | ||
1752 | handler->prio = ft_prio - dev->flow_db.prios; | |
1753 | ||
1754 | ft_prio->flow_table = ft; | |
1755 | free: | |
1756 | if (err) | |
1757 | kfree(handler); | |
c5bb1730 | 1758 | kvfree(spec); |
038d2ef8 MG |
1759 | return err ? ERR_PTR(err) : handler; |
1760 | } | |
1761 | ||
35d19011 MG |
1762 | static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, |
1763 | struct mlx5_ib_flow_prio *ft_prio, | |
1764 | struct ib_flow_attr *flow_attr, | |
1765 | struct mlx5_flow_destination *dst) | |
1766 | { | |
1767 | struct mlx5_ib_flow_handler *handler_dst = NULL; | |
1768 | struct mlx5_ib_flow_handler *handler = NULL; | |
1769 | ||
1770 | handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); | |
1771 | if (!IS_ERR(handler)) { | |
1772 | handler_dst = create_flow_rule(dev, ft_prio, | |
1773 | flow_attr, dst); | |
1774 | if (IS_ERR(handler_dst)) { | |
1775 | mlx5_del_flow_rule(handler->rule); | |
1776 | kfree(handler); | |
1777 | handler = handler_dst; | |
1778 | } else { | |
1779 | list_add(&handler_dst->list, &handler->list); | |
1780 | } | |
1781 | } | |
1782 | ||
1783 | return handler; | |
1784 | } | |
038d2ef8 MG |
1785 | enum { |
1786 | LEFTOVERS_MC, | |
1787 | LEFTOVERS_UC, | |
1788 | }; | |
1789 | ||
1790 | static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, | |
1791 | struct mlx5_ib_flow_prio *ft_prio, | |
1792 | struct ib_flow_attr *flow_attr, | |
1793 | struct mlx5_flow_destination *dst) | |
1794 | { | |
1795 | struct mlx5_ib_flow_handler *handler_ucast = NULL; | |
1796 | struct mlx5_ib_flow_handler *handler = NULL; | |
1797 | ||
1798 | static struct { | |
1799 | struct ib_flow_attr flow_attr; | |
1800 | struct ib_flow_spec_eth eth_flow; | |
1801 | } leftovers_specs[] = { | |
1802 | [LEFTOVERS_MC] = { | |
1803 | .flow_attr = { | |
1804 | .num_of_specs = 1, | |
1805 | .size = sizeof(leftovers_specs[0]) | |
1806 | }, | |
1807 | .eth_flow = { | |
1808 | .type = IB_FLOW_SPEC_ETH, | |
1809 | .size = sizeof(struct ib_flow_spec_eth), | |
1810 | .mask = {.dst_mac = {0x1} }, | |
1811 | .val = {.dst_mac = {0x1} } | |
1812 | } | |
1813 | }, | |
1814 | [LEFTOVERS_UC] = { | |
1815 | .flow_attr = { | |
1816 | .num_of_specs = 1, | |
1817 | .size = sizeof(leftovers_specs[0]) | |
1818 | }, | |
1819 | .eth_flow = { | |
1820 | .type = IB_FLOW_SPEC_ETH, | |
1821 | .size = sizeof(struct ib_flow_spec_eth), | |
1822 | .mask = {.dst_mac = {0x1} }, | |
1823 | .val = {.dst_mac = {} } | |
1824 | } | |
1825 | } | |
1826 | }; | |
1827 | ||
1828 | handler = create_flow_rule(dev, ft_prio, | |
1829 | &leftovers_specs[LEFTOVERS_MC].flow_attr, | |
1830 | dst); | |
1831 | if (!IS_ERR(handler) && | |
1832 | flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { | |
1833 | handler_ucast = create_flow_rule(dev, ft_prio, | |
1834 | &leftovers_specs[LEFTOVERS_UC].flow_attr, | |
1835 | dst); | |
1836 | if (IS_ERR(handler_ucast)) { | |
1837 | kfree(handler); | |
1838 | handler = handler_ucast; | |
1839 | } else { | |
1840 | list_add(&handler_ucast->list, &handler->list); | |
1841 | } | |
1842 | } | |
1843 | ||
1844 | return handler; | |
1845 | } | |
1846 | ||
1847 | static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, | |
1848 | struct ib_flow_attr *flow_attr, | |
1849 | int domain) | |
1850 | { | |
1851 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
1852 | struct mlx5_ib_flow_handler *handler = NULL; | |
1853 | struct mlx5_flow_destination *dst = NULL; | |
1854 | struct mlx5_ib_flow_prio *ft_prio; | |
1855 | int err; | |
1856 | ||
1857 | if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) | |
1858 | return ERR_PTR(-ENOSPC); | |
1859 | ||
1860 | if (domain != IB_FLOW_DOMAIN_USER || | |
1861 | flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || | |
35d19011 | 1862 | (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) |
038d2ef8 MG |
1863 | return ERR_PTR(-EINVAL); |
1864 | ||
1865 | dst = kzalloc(sizeof(*dst), GFP_KERNEL); | |
1866 | if (!dst) | |
1867 | return ERR_PTR(-ENOMEM); | |
1868 | ||
1869 | mutex_lock(&dev->flow_db.lock); | |
1870 | ||
1871 | ft_prio = get_flow_table(dev, flow_attr); | |
1872 | if (IS_ERR(ft_prio)) { | |
1873 | err = PTR_ERR(ft_prio); | |
1874 | goto unlock; | |
1875 | } | |
1876 | ||
1877 | dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; | |
1878 | dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn; | |
1879 | ||
1880 | if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { | |
35d19011 MG |
1881 | if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { |
1882 | handler = create_dont_trap_rule(dev, ft_prio, | |
1883 | flow_attr, dst); | |
1884 | } else { | |
1885 | handler = create_flow_rule(dev, ft_prio, flow_attr, | |
1886 | dst); | |
1887 | } | |
038d2ef8 MG |
1888 | } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || |
1889 | flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
1890 | handler = create_leftovers_rule(dev, ft_prio, flow_attr, | |
1891 | dst); | |
1892 | } else { | |
1893 | err = -EINVAL; | |
1894 | goto destroy_ft; | |
1895 | } | |
1896 | ||
1897 | if (IS_ERR(handler)) { | |
1898 | err = PTR_ERR(handler); | |
1899 | handler = NULL; | |
1900 | goto destroy_ft; | |
1901 | } | |
1902 | ||
1903 | ft_prio->refcount++; | |
1904 | mutex_unlock(&dev->flow_db.lock); | |
1905 | kfree(dst); | |
1906 | ||
1907 | return &handler->ibflow; | |
1908 | ||
1909 | destroy_ft: | |
1910 | put_flow_table(dev, ft_prio, false); | |
1911 | unlock: | |
1912 | mutex_unlock(&dev->flow_db.lock); | |
1913 | kfree(dst); | |
1914 | kfree(handler); | |
1915 | return ERR_PTR(err); | |
1916 | } | |
1917 | ||
e126ba97 EC |
1918 | static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) |
1919 | { | |
1920 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
1921 | int err; | |
1922 | ||
9603b61d | 1923 | err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); |
e126ba97 EC |
1924 | if (err) |
1925 | mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", | |
1926 | ibqp->qp_num, gid->raw); | |
1927 | ||
1928 | return err; | |
1929 | } | |
1930 | ||
1931 | static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) | |
1932 | { | |
1933 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
1934 | int err; | |
1935 | ||
9603b61d | 1936 | err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); |
e126ba97 EC |
1937 | if (err) |
1938 | mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", | |
1939 | ibqp->qp_num, gid->raw); | |
1940 | ||
1941 | return err; | |
1942 | } | |
1943 | ||
1944 | static int init_node_data(struct mlx5_ib_dev *dev) | |
1945 | { | |
1b5daf11 | 1946 | int err; |
e126ba97 | 1947 | |
1b5daf11 | 1948 | err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); |
e126ba97 | 1949 | if (err) |
1b5daf11 | 1950 | return err; |
e126ba97 | 1951 | |
1b5daf11 | 1952 | dev->mdev->rev_id = dev->mdev->pdev->revision; |
e126ba97 | 1953 | |
1b5daf11 | 1954 | return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); |
e126ba97 EC |
1955 | } |
1956 | ||
1957 | static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, | |
1958 | char *buf) | |
1959 | { | |
1960 | struct mlx5_ib_dev *dev = | |
1961 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
1962 | ||
9603b61d | 1963 | return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); |
e126ba97 EC |
1964 | } |
1965 | ||
1966 | static ssize_t show_reg_pages(struct device *device, | |
1967 | struct device_attribute *attr, char *buf) | |
1968 | { | |
1969 | struct mlx5_ib_dev *dev = | |
1970 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
1971 | ||
6aec21f6 | 1972 | return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); |
e126ba97 EC |
1973 | } |
1974 | ||
1975 | static ssize_t show_hca(struct device *device, struct device_attribute *attr, | |
1976 | char *buf) | |
1977 | { | |
1978 | struct mlx5_ib_dev *dev = | |
1979 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
9603b61d | 1980 | return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); |
e126ba97 EC |
1981 | } |
1982 | ||
e126ba97 EC |
1983 | static ssize_t show_rev(struct device *device, struct device_attribute *attr, |
1984 | char *buf) | |
1985 | { | |
1986 | struct mlx5_ib_dev *dev = | |
1987 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
9603b61d | 1988 | return sprintf(buf, "%x\n", dev->mdev->rev_id); |
e126ba97 EC |
1989 | } |
1990 | ||
1991 | static ssize_t show_board(struct device *device, struct device_attribute *attr, | |
1992 | char *buf) | |
1993 | { | |
1994 | struct mlx5_ib_dev *dev = | |
1995 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
1996 | return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, | |
9603b61d | 1997 | dev->mdev->board_id); |
e126ba97 EC |
1998 | } |
1999 | ||
2000 | static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); | |
e126ba97 EC |
2001 | static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); |
2002 | static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); | |
2003 | static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); | |
2004 | static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); | |
2005 | ||
2006 | static struct device_attribute *mlx5_class_attributes[] = { | |
2007 | &dev_attr_hw_rev, | |
e126ba97 EC |
2008 | &dev_attr_hca_type, |
2009 | &dev_attr_board_id, | |
2010 | &dev_attr_fw_pages, | |
2011 | &dev_attr_reg_pages, | |
2012 | }; | |
2013 | ||
7722f47e HE |
2014 | static void pkey_change_handler(struct work_struct *work) |
2015 | { | |
2016 | struct mlx5_ib_port_resources *ports = | |
2017 | container_of(work, struct mlx5_ib_port_resources, | |
2018 | pkey_change_work); | |
2019 | ||
2020 | mutex_lock(&ports->devr->mutex); | |
2021 | mlx5_ib_gsi_pkey_change(ports->gsi); | |
2022 | mutex_unlock(&ports->devr->mutex); | |
2023 | } | |
2024 | ||
89ea94a7 MG |
2025 | static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) |
2026 | { | |
2027 | struct mlx5_ib_qp *mqp; | |
2028 | struct mlx5_ib_cq *send_mcq, *recv_mcq; | |
2029 | struct mlx5_core_cq *mcq; | |
2030 | struct list_head cq_armed_list; | |
2031 | unsigned long flags_qp; | |
2032 | unsigned long flags_cq; | |
2033 | unsigned long flags; | |
2034 | ||
2035 | INIT_LIST_HEAD(&cq_armed_list); | |
2036 | ||
2037 | /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ | |
2038 | spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); | |
2039 | list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { | |
2040 | spin_lock_irqsave(&mqp->sq.lock, flags_qp); | |
2041 | if (mqp->sq.tail != mqp->sq.head) { | |
2042 | send_mcq = to_mcq(mqp->ibqp.send_cq); | |
2043 | spin_lock_irqsave(&send_mcq->lock, flags_cq); | |
2044 | if (send_mcq->mcq.comp && | |
2045 | mqp->ibqp.send_cq->comp_handler) { | |
2046 | if (!send_mcq->mcq.reset_notify_added) { | |
2047 | send_mcq->mcq.reset_notify_added = 1; | |
2048 | list_add_tail(&send_mcq->mcq.reset_notify, | |
2049 | &cq_armed_list); | |
2050 | } | |
2051 | } | |
2052 | spin_unlock_irqrestore(&send_mcq->lock, flags_cq); | |
2053 | } | |
2054 | spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); | |
2055 | spin_lock_irqsave(&mqp->rq.lock, flags_qp); | |
2056 | /* no handling is needed for SRQ */ | |
2057 | if (!mqp->ibqp.srq) { | |
2058 | if (mqp->rq.tail != mqp->rq.head) { | |
2059 | recv_mcq = to_mcq(mqp->ibqp.recv_cq); | |
2060 | spin_lock_irqsave(&recv_mcq->lock, flags_cq); | |
2061 | if (recv_mcq->mcq.comp && | |
2062 | mqp->ibqp.recv_cq->comp_handler) { | |
2063 | if (!recv_mcq->mcq.reset_notify_added) { | |
2064 | recv_mcq->mcq.reset_notify_added = 1; | |
2065 | list_add_tail(&recv_mcq->mcq.reset_notify, | |
2066 | &cq_armed_list); | |
2067 | } | |
2068 | } | |
2069 | spin_unlock_irqrestore(&recv_mcq->lock, | |
2070 | flags_cq); | |
2071 | } | |
2072 | } | |
2073 | spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); | |
2074 | } | |
2075 | /*At that point all inflight post send were put to be executed as of we | |
2076 | * lock/unlock above locks Now need to arm all involved CQs. | |
2077 | */ | |
2078 | list_for_each_entry(mcq, &cq_armed_list, reset_notify) { | |
2079 | mcq->comp(mcq); | |
2080 | } | |
2081 | spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); | |
2082 | } | |
2083 | ||
9603b61d | 2084 | static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 2085 | enum mlx5_dev_event event, unsigned long param) |
e126ba97 | 2086 | { |
9603b61d | 2087 | struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; |
e126ba97 | 2088 | struct ib_event ibev; |
9603b61d | 2089 | |
e126ba97 EC |
2090 | u8 port = 0; |
2091 | ||
2092 | switch (event) { | |
2093 | case MLX5_DEV_EVENT_SYS_ERROR: | |
2094 | ibdev->ib_active = false; | |
2095 | ibev.event = IB_EVENT_DEVICE_FATAL; | |
89ea94a7 | 2096 | mlx5_ib_handle_internal_error(ibdev); |
e126ba97 EC |
2097 | break; |
2098 | ||
2099 | case MLX5_DEV_EVENT_PORT_UP: | |
2100 | ibev.event = IB_EVENT_PORT_ACTIVE; | |
4d2f9bbb | 2101 | port = (u8)param; |
e126ba97 EC |
2102 | break; |
2103 | ||
2104 | case MLX5_DEV_EVENT_PORT_DOWN: | |
2788cf3b | 2105 | case MLX5_DEV_EVENT_PORT_INITIALIZED: |
e126ba97 | 2106 | ibev.event = IB_EVENT_PORT_ERR; |
4d2f9bbb | 2107 | port = (u8)param; |
e126ba97 EC |
2108 | break; |
2109 | ||
e126ba97 EC |
2110 | case MLX5_DEV_EVENT_LID_CHANGE: |
2111 | ibev.event = IB_EVENT_LID_CHANGE; | |
4d2f9bbb | 2112 | port = (u8)param; |
e126ba97 EC |
2113 | break; |
2114 | ||
2115 | case MLX5_DEV_EVENT_PKEY_CHANGE: | |
2116 | ibev.event = IB_EVENT_PKEY_CHANGE; | |
4d2f9bbb | 2117 | port = (u8)param; |
7722f47e HE |
2118 | |
2119 | schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); | |
e126ba97 EC |
2120 | break; |
2121 | ||
2122 | case MLX5_DEV_EVENT_GUID_CHANGE: | |
2123 | ibev.event = IB_EVENT_GID_CHANGE; | |
4d2f9bbb | 2124 | port = (u8)param; |
e126ba97 EC |
2125 | break; |
2126 | ||
2127 | case MLX5_DEV_EVENT_CLIENT_REREG: | |
2128 | ibev.event = IB_EVENT_CLIENT_REREGISTER; | |
4d2f9bbb | 2129 | port = (u8)param; |
e126ba97 EC |
2130 | break; |
2131 | } | |
2132 | ||
2133 | ibev.device = &ibdev->ib_dev; | |
2134 | ibev.element.port_num = port; | |
2135 | ||
a0c84c32 EC |
2136 | if (port < 1 || port > ibdev->num_ports) { |
2137 | mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); | |
2138 | return; | |
2139 | } | |
2140 | ||
e126ba97 EC |
2141 | if (ibdev->ib_active) |
2142 | ib_dispatch_event(&ibev); | |
2143 | } | |
2144 | ||
2145 | static void get_ext_port_caps(struct mlx5_ib_dev *dev) | |
2146 | { | |
2147 | int port; | |
2148 | ||
938fe83c | 2149 | for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) |
e126ba97 EC |
2150 | mlx5_query_ext_port_caps(dev, port); |
2151 | } | |
2152 | ||
2153 | static int get_port_caps(struct mlx5_ib_dev *dev) | |
2154 | { | |
2155 | struct ib_device_attr *dprops = NULL; | |
2156 | struct ib_port_attr *pprops = NULL; | |
f614fc15 | 2157 | int err = -ENOMEM; |
e126ba97 | 2158 | int port; |
2528e33e | 2159 | struct ib_udata uhw = {.inlen = 0, .outlen = 0}; |
e126ba97 EC |
2160 | |
2161 | pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); | |
2162 | if (!pprops) | |
2163 | goto out; | |
2164 | ||
2165 | dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); | |
2166 | if (!dprops) | |
2167 | goto out; | |
2168 | ||
2528e33e | 2169 | err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); |
e126ba97 EC |
2170 | if (err) { |
2171 | mlx5_ib_warn(dev, "query_device failed %d\n", err); | |
2172 | goto out; | |
2173 | } | |
2174 | ||
938fe83c | 2175 | for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { |
e126ba97 EC |
2176 | err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); |
2177 | if (err) { | |
938fe83c SM |
2178 | mlx5_ib_warn(dev, "query_port %d failed %d\n", |
2179 | port, err); | |
e126ba97 EC |
2180 | break; |
2181 | } | |
938fe83c SM |
2182 | dev->mdev->port_caps[port - 1].pkey_table_len = |
2183 | dprops->max_pkeys; | |
2184 | dev->mdev->port_caps[port - 1].gid_table_len = | |
2185 | pprops->gid_tbl_len; | |
e126ba97 EC |
2186 | mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", |
2187 | dprops->max_pkeys, pprops->gid_tbl_len); | |
2188 | } | |
2189 | ||
2190 | out: | |
2191 | kfree(pprops); | |
2192 | kfree(dprops); | |
2193 | ||
2194 | return err; | |
2195 | } | |
2196 | ||
2197 | static void destroy_umrc_res(struct mlx5_ib_dev *dev) | |
2198 | { | |
2199 | int err; | |
2200 | ||
2201 | err = mlx5_mr_cache_cleanup(dev); | |
2202 | if (err) | |
2203 | mlx5_ib_warn(dev, "mr cache cleanup failed\n"); | |
2204 | ||
2205 | mlx5_ib_destroy_qp(dev->umrc.qp); | |
add08d76 | 2206 | ib_free_cq(dev->umrc.cq); |
e126ba97 EC |
2207 | ib_dealloc_pd(dev->umrc.pd); |
2208 | } | |
2209 | ||
2210 | enum { | |
2211 | MAX_UMR_WR = 128, | |
2212 | }; | |
2213 | ||
2214 | static int create_umr_res(struct mlx5_ib_dev *dev) | |
2215 | { | |
2216 | struct ib_qp_init_attr *init_attr = NULL; | |
2217 | struct ib_qp_attr *attr = NULL; | |
2218 | struct ib_pd *pd; | |
2219 | struct ib_cq *cq; | |
2220 | struct ib_qp *qp; | |
e126ba97 EC |
2221 | int ret; |
2222 | ||
2223 | attr = kzalloc(sizeof(*attr), GFP_KERNEL); | |
2224 | init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); | |
2225 | if (!attr || !init_attr) { | |
2226 | ret = -ENOMEM; | |
2227 | goto error_0; | |
2228 | } | |
2229 | ||
2230 | pd = ib_alloc_pd(&dev->ib_dev); | |
2231 | if (IS_ERR(pd)) { | |
2232 | mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); | |
2233 | ret = PTR_ERR(pd); | |
2234 | goto error_0; | |
2235 | } | |
2236 | ||
add08d76 | 2237 | cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); |
e126ba97 EC |
2238 | if (IS_ERR(cq)) { |
2239 | mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); | |
2240 | ret = PTR_ERR(cq); | |
2241 | goto error_2; | |
2242 | } | |
e126ba97 EC |
2243 | |
2244 | init_attr->send_cq = cq; | |
2245 | init_attr->recv_cq = cq; | |
2246 | init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; | |
2247 | init_attr->cap.max_send_wr = MAX_UMR_WR; | |
2248 | init_attr->cap.max_send_sge = 1; | |
2249 | init_attr->qp_type = MLX5_IB_QPT_REG_UMR; | |
2250 | init_attr->port_num = 1; | |
2251 | qp = mlx5_ib_create_qp(pd, init_attr, NULL); | |
2252 | if (IS_ERR(qp)) { | |
2253 | mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); | |
2254 | ret = PTR_ERR(qp); | |
2255 | goto error_3; | |
2256 | } | |
2257 | qp->device = &dev->ib_dev; | |
2258 | qp->real_qp = qp; | |
2259 | qp->uobject = NULL; | |
2260 | qp->qp_type = MLX5_IB_QPT_REG_UMR; | |
2261 | ||
2262 | attr->qp_state = IB_QPS_INIT; | |
2263 | attr->port_num = 1; | |
2264 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | | |
2265 | IB_QP_PORT, NULL); | |
2266 | if (ret) { | |
2267 | mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); | |
2268 | goto error_4; | |
2269 | } | |
2270 | ||
2271 | memset(attr, 0, sizeof(*attr)); | |
2272 | attr->qp_state = IB_QPS_RTR; | |
2273 | attr->path_mtu = IB_MTU_256; | |
2274 | ||
2275 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); | |
2276 | if (ret) { | |
2277 | mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); | |
2278 | goto error_4; | |
2279 | } | |
2280 | ||
2281 | memset(attr, 0, sizeof(*attr)); | |
2282 | attr->qp_state = IB_QPS_RTS; | |
2283 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); | |
2284 | if (ret) { | |
2285 | mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); | |
2286 | goto error_4; | |
2287 | } | |
2288 | ||
2289 | dev->umrc.qp = qp; | |
2290 | dev->umrc.cq = cq; | |
e126ba97 EC |
2291 | dev->umrc.pd = pd; |
2292 | ||
2293 | sema_init(&dev->umrc.sem, MAX_UMR_WR); | |
2294 | ret = mlx5_mr_cache_init(dev); | |
2295 | if (ret) { | |
2296 | mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); | |
2297 | goto error_4; | |
2298 | } | |
2299 | ||
2300 | kfree(attr); | |
2301 | kfree(init_attr); | |
2302 | ||
2303 | return 0; | |
2304 | ||
2305 | error_4: | |
2306 | mlx5_ib_destroy_qp(qp); | |
2307 | ||
2308 | error_3: | |
add08d76 | 2309 | ib_free_cq(cq); |
e126ba97 EC |
2310 | |
2311 | error_2: | |
e126ba97 EC |
2312 | ib_dealloc_pd(pd); |
2313 | ||
2314 | error_0: | |
2315 | kfree(attr); | |
2316 | kfree(init_attr); | |
2317 | return ret; | |
2318 | } | |
2319 | ||
2320 | static int create_dev_resources(struct mlx5_ib_resources *devr) | |
2321 | { | |
2322 | struct ib_srq_init_attr attr; | |
2323 | struct mlx5_ib_dev *dev; | |
bcf4c1ea | 2324 | struct ib_cq_init_attr cq_attr = {.cqe = 1}; |
7722f47e | 2325 | int port; |
e126ba97 EC |
2326 | int ret = 0; |
2327 | ||
2328 | dev = container_of(devr, struct mlx5_ib_dev, devr); | |
2329 | ||
d16e91da HE |
2330 | mutex_init(&devr->mutex); |
2331 | ||
e126ba97 EC |
2332 | devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); |
2333 | if (IS_ERR(devr->p0)) { | |
2334 | ret = PTR_ERR(devr->p0); | |
2335 | goto error0; | |
2336 | } | |
2337 | devr->p0->device = &dev->ib_dev; | |
2338 | devr->p0->uobject = NULL; | |
2339 | atomic_set(&devr->p0->usecnt, 0); | |
2340 | ||
bcf4c1ea | 2341 | devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); |
e126ba97 EC |
2342 | if (IS_ERR(devr->c0)) { |
2343 | ret = PTR_ERR(devr->c0); | |
2344 | goto error1; | |
2345 | } | |
2346 | devr->c0->device = &dev->ib_dev; | |
2347 | devr->c0->uobject = NULL; | |
2348 | devr->c0->comp_handler = NULL; | |
2349 | devr->c0->event_handler = NULL; | |
2350 | devr->c0->cq_context = NULL; | |
2351 | atomic_set(&devr->c0->usecnt, 0); | |
2352 | ||
2353 | devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); | |
2354 | if (IS_ERR(devr->x0)) { | |
2355 | ret = PTR_ERR(devr->x0); | |
2356 | goto error2; | |
2357 | } | |
2358 | devr->x0->device = &dev->ib_dev; | |
2359 | devr->x0->inode = NULL; | |
2360 | atomic_set(&devr->x0->usecnt, 0); | |
2361 | mutex_init(&devr->x0->tgt_qp_mutex); | |
2362 | INIT_LIST_HEAD(&devr->x0->tgt_qp_list); | |
2363 | ||
2364 | devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); | |
2365 | if (IS_ERR(devr->x1)) { | |
2366 | ret = PTR_ERR(devr->x1); | |
2367 | goto error3; | |
2368 | } | |
2369 | devr->x1->device = &dev->ib_dev; | |
2370 | devr->x1->inode = NULL; | |
2371 | atomic_set(&devr->x1->usecnt, 0); | |
2372 | mutex_init(&devr->x1->tgt_qp_mutex); | |
2373 | INIT_LIST_HEAD(&devr->x1->tgt_qp_list); | |
2374 | ||
2375 | memset(&attr, 0, sizeof(attr)); | |
2376 | attr.attr.max_sge = 1; | |
2377 | attr.attr.max_wr = 1; | |
2378 | attr.srq_type = IB_SRQT_XRC; | |
2379 | attr.ext.xrc.cq = devr->c0; | |
2380 | attr.ext.xrc.xrcd = devr->x0; | |
2381 | ||
2382 | devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); | |
2383 | if (IS_ERR(devr->s0)) { | |
2384 | ret = PTR_ERR(devr->s0); | |
2385 | goto error4; | |
2386 | } | |
2387 | devr->s0->device = &dev->ib_dev; | |
2388 | devr->s0->pd = devr->p0; | |
2389 | devr->s0->uobject = NULL; | |
2390 | devr->s0->event_handler = NULL; | |
2391 | devr->s0->srq_context = NULL; | |
2392 | devr->s0->srq_type = IB_SRQT_XRC; | |
2393 | devr->s0->ext.xrc.xrcd = devr->x0; | |
2394 | devr->s0->ext.xrc.cq = devr->c0; | |
2395 | atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); | |
2396 | atomic_inc(&devr->s0->ext.xrc.cq->usecnt); | |
2397 | atomic_inc(&devr->p0->usecnt); | |
2398 | atomic_set(&devr->s0->usecnt, 0); | |
2399 | ||
4aa17b28 HA |
2400 | memset(&attr, 0, sizeof(attr)); |
2401 | attr.attr.max_sge = 1; | |
2402 | attr.attr.max_wr = 1; | |
2403 | attr.srq_type = IB_SRQT_BASIC; | |
2404 | devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); | |
2405 | if (IS_ERR(devr->s1)) { | |
2406 | ret = PTR_ERR(devr->s1); | |
2407 | goto error5; | |
2408 | } | |
2409 | devr->s1->device = &dev->ib_dev; | |
2410 | devr->s1->pd = devr->p0; | |
2411 | devr->s1->uobject = NULL; | |
2412 | devr->s1->event_handler = NULL; | |
2413 | devr->s1->srq_context = NULL; | |
2414 | devr->s1->srq_type = IB_SRQT_BASIC; | |
2415 | devr->s1->ext.xrc.cq = devr->c0; | |
2416 | atomic_inc(&devr->p0->usecnt); | |
2417 | atomic_set(&devr->s0->usecnt, 0); | |
2418 | ||
7722f47e HE |
2419 | for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { |
2420 | INIT_WORK(&devr->ports[port].pkey_change_work, | |
2421 | pkey_change_handler); | |
2422 | devr->ports[port].devr = devr; | |
2423 | } | |
2424 | ||
e126ba97 EC |
2425 | return 0; |
2426 | ||
4aa17b28 HA |
2427 | error5: |
2428 | mlx5_ib_destroy_srq(devr->s0); | |
e126ba97 EC |
2429 | error4: |
2430 | mlx5_ib_dealloc_xrcd(devr->x1); | |
2431 | error3: | |
2432 | mlx5_ib_dealloc_xrcd(devr->x0); | |
2433 | error2: | |
2434 | mlx5_ib_destroy_cq(devr->c0); | |
2435 | error1: | |
2436 | mlx5_ib_dealloc_pd(devr->p0); | |
2437 | error0: | |
2438 | return ret; | |
2439 | } | |
2440 | ||
2441 | static void destroy_dev_resources(struct mlx5_ib_resources *devr) | |
2442 | { | |
7722f47e HE |
2443 | struct mlx5_ib_dev *dev = |
2444 | container_of(devr, struct mlx5_ib_dev, devr); | |
2445 | int port; | |
2446 | ||
4aa17b28 | 2447 | mlx5_ib_destroy_srq(devr->s1); |
e126ba97 EC |
2448 | mlx5_ib_destroy_srq(devr->s0); |
2449 | mlx5_ib_dealloc_xrcd(devr->x0); | |
2450 | mlx5_ib_dealloc_xrcd(devr->x1); | |
2451 | mlx5_ib_destroy_cq(devr->c0); | |
2452 | mlx5_ib_dealloc_pd(devr->p0); | |
7722f47e HE |
2453 | |
2454 | /* Make sure no change P_Key work items are still executing */ | |
2455 | for (port = 0; port < dev->num_ports; ++port) | |
2456 | cancel_work_sync(&devr->ports[port].pkey_change_work); | |
e126ba97 EC |
2457 | } |
2458 | ||
e53505a8 AS |
2459 | static u32 get_core_cap_flags(struct ib_device *ibdev) |
2460 | { | |
2461 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
2462 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); | |
2463 | u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); | |
2464 | u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); | |
2465 | u32 ret = 0; | |
2466 | ||
2467 | if (ll == IB_LINK_LAYER_INFINIBAND) | |
2468 | return RDMA_CORE_PORT_IBA_IB; | |
2469 | ||
2470 | if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) | |
2471 | return 0; | |
2472 | ||
2473 | if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) | |
2474 | return 0; | |
2475 | ||
2476 | if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) | |
2477 | ret |= RDMA_CORE_PORT_IBA_ROCE; | |
2478 | ||
2479 | if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) | |
2480 | ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; | |
2481 | ||
2482 | return ret; | |
2483 | } | |
2484 | ||
7738613e IW |
2485 | static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, |
2486 | struct ib_port_immutable *immutable) | |
2487 | { | |
2488 | struct ib_port_attr attr; | |
2489 | int err; | |
2490 | ||
2491 | err = mlx5_ib_query_port(ibdev, port_num, &attr); | |
2492 | if (err) | |
2493 | return err; | |
2494 | ||
2495 | immutable->pkey_tbl_len = attr.pkey_tbl_len; | |
2496 | immutable->gid_tbl_len = attr.gid_tbl_len; | |
e53505a8 | 2497 | immutable->core_cap_flags = get_core_cap_flags(ibdev); |
337877a4 | 2498 | immutable->max_mad_size = IB_MGMT_MAD_SIZE; |
7738613e IW |
2499 | |
2500 | return 0; | |
2501 | } | |
2502 | ||
c7342823 IW |
2503 | static void get_dev_fw_str(struct ib_device *ibdev, char *str, |
2504 | size_t str_len) | |
2505 | { | |
2506 | struct mlx5_ib_dev *dev = | |
2507 | container_of(ibdev, struct mlx5_ib_dev, ib_dev); | |
2508 | snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), | |
2509 | fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); | |
2510 | } | |
2511 | ||
fc24fc5e AS |
2512 | static int mlx5_enable_roce(struct mlx5_ib_dev *dev) |
2513 | { | |
e53505a8 AS |
2514 | int err; |
2515 | ||
fc24fc5e | 2516 | dev->roce.nb.notifier_call = mlx5_netdev_event; |
e53505a8 AS |
2517 | err = register_netdevice_notifier(&dev->roce.nb); |
2518 | if (err) | |
2519 | return err; | |
2520 | ||
2521 | err = mlx5_nic_vport_enable_roce(dev->mdev); | |
2522 | if (err) | |
2523 | goto err_unregister_netdevice_notifier; | |
2524 | ||
2525 | return 0; | |
2526 | ||
2527 | err_unregister_netdevice_notifier: | |
2528 | unregister_netdevice_notifier(&dev->roce.nb); | |
2529 | return err; | |
fc24fc5e AS |
2530 | } |
2531 | ||
2532 | static void mlx5_disable_roce(struct mlx5_ib_dev *dev) | |
2533 | { | |
e53505a8 | 2534 | mlx5_nic_vport_disable_roce(dev->mdev); |
fc24fc5e AS |
2535 | unregister_netdevice_notifier(&dev->roce.nb); |
2536 | } | |
2537 | ||
0837e86a MB |
2538 | static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) |
2539 | { | |
2540 | unsigned int i; | |
2541 | ||
2542 | for (i = 0; i < dev->num_ports; i++) | |
2543 | mlx5_core_dealloc_q_counter(dev->mdev, | |
2544 | dev->port[i].q_cnt_id); | |
2545 | } | |
2546 | ||
2547 | static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) | |
2548 | { | |
2549 | int i; | |
2550 | int ret; | |
2551 | ||
2552 | for (i = 0; i < dev->num_ports; i++) { | |
2553 | ret = mlx5_core_alloc_q_counter(dev->mdev, | |
2554 | &dev->port[i].q_cnt_id); | |
2555 | if (ret) { | |
2556 | mlx5_ib_warn(dev, | |
2557 | "couldn't allocate queue counter for port %d, err %d\n", | |
2558 | i + 1, ret); | |
2559 | goto dealloc_counters; | |
2560 | } | |
2561 | } | |
2562 | ||
2563 | return 0; | |
2564 | ||
2565 | dealloc_counters: | |
2566 | while (--i >= 0) | |
2567 | mlx5_core_dealloc_q_counter(dev->mdev, | |
2568 | dev->port[i].q_cnt_id); | |
2569 | ||
2570 | return ret; | |
2571 | } | |
2572 | ||
61961500 | 2573 | static const char * const names[] = { |
0ad17a8f MB |
2574 | "rx_write_requests", |
2575 | "rx_read_requests", | |
2576 | "rx_atomic_requests", | |
2577 | "out_of_buffer", | |
2578 | "out_of_sequence", | |
2579 | "duplicate_request", | |
2580 | "rnr_nak_retry_err", | |
2581 | "packet_seq_err", | |
2582 | "implied_nak_seq_err", | |
2583 | "local_ack_timeout_err", | |
2584 | }; | |
2585 | ||
2586 | static const size_t stats_offsets[] = { | |
2587 | MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), | |
2588 | MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), | |
2589 | MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), | |
2590 | MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), | |
2591 | MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), | |
2592 | MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), | |
2593 | MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), | |
2594 | MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), | |
2595 | MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), | |
2596 | MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), | |
2597 | }; | |
2598 | ||
2599 | static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, | |
2600 | u8 port_num) | |
2601 | { | |
2602 | BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); | |
2603 | ||
2604 | /* We support only per port stats */ | |
2605 | if (port_num == 0) | |
2606 | return NULL; | |
2607 | ||
2608 | return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), | |
2609 | RDMA_HW_STATS_DEFAULT_LIFESPAN); | |
2610 | } | |
2611 | ||
2612 | static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, | |
2613 | struct rdma_hw_stats *stats, | |
2614 | u8 port, int index) | |
2615 | { | |
2616 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
2617 | int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); | |
2618 | void *out; | |
2619 | __be32 val; | |
2620 | int ret; | |
2621 | int i; | |
2622 | ||
2623 | if (!port || !stats) | |
2624 | return -ENOSYS; | |
2625 | ||
2626 | out = mlx5_vzalloc(outlen); | |
2627 | if (!out) | |
2628 | return -ENOMEM; | |
2629 | ||
2630 | ret = mlx5_core_query_q_counter(dev->mdev, | |
2631 | dev->port[port - 1].q_cnt_id, 0, | |
2632 | out, outlen); | |
2633 | if (ret) | |
2634 | goto free; | |
2635 | ||
2636 | for (i = 0; i < ARRAY_SIZE(names); i++) { | |
2637 | val = *(__be32 *)(out + stats_offsets[i]); | |
2638 | stats->value[i] = (u64)be32_to_cpu(val); | |
2639 | } | |
2640 | free: | |
2641 | kvfree(out); | |
2642 | return ARRAY_SIZE(names); | |
2643 | } | |
2644 | ||
9603b61d | 2645 | static void *mlx5_ib_add(struct mlx5_core_dev *mdev) |
e126ba97 | 2646 | { |
e126ba97 | 2647 | struct mlx5_ib_dev *dev; |
ebd61f68 AS |
2648 | enum rdma_link_layer ll; |
2649 | int port_type_cap; | |
e126ba97 EC |
2650 | int err; |
2651 | int i; | |
2652 | ||
ebd61f68 AS |
2653 | port_type_cap = MLX5_CAP_GEN(mdev, port_type); |
2654 | ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); | |
2655 | ||
e53505a8 | 2656 | if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) |
647241ea MD |
2657 | return NULL; |
2658 | ||
e126ba97 EC |
2659 | printk_once(KERN_INFO "%s", mlx5_version); |
2660 | ||
2661 | dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); | |
2662 | if (!dev) | |
9603b61d | 2663 | return NULL; |
e126ba97 | 2664 | |
9603b61d | 2665 | dev->mdev = mdev; |
e126ba97 | 2666 | |
0837e86a MB |
2667 | dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), |
2668 | GFP_KERNEL); | |
2669 | if (!dev->port) | |
2670 | goto err_dealloc; | |
2671 | ||
fc24fc5e | 2672 | rwlock_init(&dev->roce.netdev_lock); |
e126ba97 EC |
2673 | err = get_port_caps(dev); |
2674 | if (err) | |
0837e86a | 2675 | goto err_free_port; |
e126ba97 | 2676 | |
1b5daf11 MD |
2677 | if (mlx5_use_mad_ifc(dev)) |
2678 | get_ext_port_caps(dev); | |
e126ba97 | 2679 | |
e126ba97 EC |
2680 | MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); |
2681 | ||
2682 | strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); | |
2683 | dev->ib_dev.owner = THIS_MODULE; | |
2684 | dev->ib_dev.node_type = RDMA_NODE_IB_CA; | |
c6790aa9 | 2685 | dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; |
938fe83c | 2686 | dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); |
e126ba97 | 2687 | dev->ib_dev.phys_port_cnt = dev->num_ports; |
233d05d2 SM |
2688 | dev->ib_dev.num_comp_vectors = |
2689 | dev->mdev->priv.eq_table.num_comp_vectors; | |
e126ba97 EC |
2690 | dev->ib_dev.dma_device = &mdev->pdev->dev; |
2691 | ||
2692 | dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; | |
2693 | dev->ib_dev.uverbs_cmd_mask = | |
2694 | (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | | |
2695 | (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | | |
2696 | (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | | |
2697 | (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | | |
2698 | (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | | |
2699 | (1ull << IB_USER_VERBS_CMD_REG_MR) | | |
56e11d62 | 2700 | (1ull << IB_USER_VERBS_CMD_REREG_MR) | |
e126ba97 EC |
2701 | (1ull << IB_USER_VERBS_CMD_DEREG_MR) | |
2702 | (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | | |
2703 | (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | | |
2704 | (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | | |
2705 | (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | | |
2706 | (1ull << IB_USER_VERBS_CMD_CREATE_QP) | | |
2707 | (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | | |
2708 | (1ull << IB_USER_VERBS_CMD_QUERY_QP) | | |
2709 | (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | | |
2710 | (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | | |
2711 | (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | | |
2712 | (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | | |
2713 | (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | | |
2714 | (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | | |
2715 | (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | | |
2716 | (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | | |
2717 | (1ull << IB_USER_VERBS_CMD_OPEN_QP); | |
1707cb4a | 2718 | dev->ib_dev.uverbs_ex_cmd_mask = |
d4584ddf MB |
2719 | (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | |
2720 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | | |
2721 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); | |
e126ba97 EC |
2722 | |
2723 | dev->ib_dev.query_device = mlx5_ib_query_device; | |
2724 | dev->ib_dev.query_port = mlx5_ib_query_port; | |
ebd61f68 | 2725 | dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; |
fc24fc5e AS |
2726 | if (ll == IB_LINK_LAYER_ETHERNET) |
2727 | dev->ib_dev.get_netdev = mlx5_ib_get_netdev; | |
e126ba97 | 2728 | dev->ib_dev.query_gid = mlx5_ib_query_gid; |
3cca2606 AS |
2729 | dev->ib_dev.add_gid = mlx5_ib_add_gid; |
2730 | dev->ib_dev.del_gid = mlx5_ib_del_gid; | |
e126ba97 EC |
2731 | dev->ib_dev.query_pkey = mlx5_ib_query_pkey; |
2732 | dev->ib_dev.modify_device = mlx5_ib_modify_device; | |
2733 | dev->ib_dev.modify_port = mlx5_ib_modify_port; | |
2734 | dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; | |
2735 | dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; | |
2736 | dev->ib_dev.mmap = mlx5_ib_mmap; | |
2737 | dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; | |
2738 | dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; | |
2739 | dev->ib_dev.create_ah = mlx5_ib_create_ah; | |
2740 | dev->ib_dev.query_ah = mlx5_ib_query_ah; | |
2741 | dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; | |
2742 | dev->ib_dev.create_srq = mlx5_ib_create_srq; | |
2743 | dev->ib_dev.modify_srq = mlx5_ib_modify_srq; | |
2744 | dev->ib_dev.query_srq = mlx5_ib_query_srq; | |
2745 | dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; | |
2746 | dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; | |
2747 | dev->ib_dev.create_qp = mlx5_ib_create_qp; | |
2748 | dev->ib_dev.modify_qp = mlx5_ib_modify_qp; | |
2749 | dev->ib_dev.query_qp = mlx5_ib_query_qp; | |
2750 | dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; | |
2751 | dev->ib_dev.post_send = mlx5_ib_post_send; | |
2752 | dev->ib_dev.post_recv = mlx5_ib_post_recv; | |
2753 | dev->ib_dev.create_cq = mlx5_ib_create_cq; | |
2754 | dev->ib_dev.modify_cq = mlx5_ib_modify_cq; | |
2755 | dev->ib_dev.resize_cq = mlx5_ib_resize_cq; | |
2756 | dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; | |
2757 | dev->ib_dev.poll_cq = mlx5_ib_poll_cq; | |
2758 | dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; | |
2759 | dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; | |
2760 | dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; | |
56e11d62 | 2761 | dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; |
e126ba97 EC |
2762 | dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; |
2763 | dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; | |
2764 | dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; | |
2765 | dev->ib_dev.process_mad = mlx5_ib_process_mad; | |
9bee178b | 2766 | dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; |
8a187ee5 | 2767 | dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; |
d5436ba0 | 2768 | dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; |
7738613e | 2769 | dev->ib_dev.get_port_immutable = mlx5_port_immutable; |
c7342823 | 2770 | dev->ib_dev.get_dev_fw_str = get_dev_fw_str; |
eff901d3 EC |
2771 | if (mlx5_core_is_pf(mdev)) { |
2772 | dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; | |
2773 | dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; | |
2774 | dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; | |
2775 | dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; | |
2776 | } | |
e126ba97 | 2777 | |
7c2344c3 MG |
2778 | dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; |
2779 | ||
938fe83c | 2780 | mlx5_ib_internal_fill_odp_caps(dev); |
8cdd312c | 2781 | |
d2370e0a MB |
2782 | if (MLX5_CAP_GEN(mdev, imaicl)) { |
2783 | dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; | |
2784 | dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; | |
2785 | dev->ib_dev.uverbs_cmd_mask |= | |
2786 | (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | | |
2787 | (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); | |
2788 | } | |
2789 | ||
0ad17a8f MB |
2790 | if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && |
2791 | MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { | |
2792 | dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; | |
2793 | dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; | |
2794 | } | |
2795 | ||
938fe83c | 2796 | if (MLX5_CAP_GEN(mdev, xrc)) { |
e126ba97 EC |
2797 | dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; |
2798 | dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; | |
2799 | dev->ib_dev.uverbs_cmd_mask |= | |
2800 | (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | | |
2801 | (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); | |
2802 | } | |
2803 | ||
048ccca8 | 2804 | if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == |
038d2ef8 MG |
2805 | IB_LINK_LAYER_ETHERNET) { |
2806 | dev->ib_dev.create_flow = mlx5_ib_create_flow; | |
2807 | dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; | |
79b20a6c YH |
2808 | dev->ib_dev.create_wq = mlx5_ib_create_wq; |
2809 | dev->ib_dev.modify_wq = mlx5_ib_modify_wq; | |
2810 | dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; | |
c5f90929 YH |
2811 | dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; |
2812 | dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; | |
038d2ef8 MG |
2813 | dev->ib_dev.uverbs_ex_cmd_mask |= |
2814 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | | |
79b20a6c YH |
2815 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | |
2816 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | | |
2817 | (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | | |
c5f90929 YH |
2818 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | |
2819 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | | |
2820 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); | |
038d2ef8 | 2821 | } |
e126ba97 EC |
2822 | err = init_node_data(dev); |
2823 | if (err) | |
233d05d2 | 2824 | goto err_dealloc; |
e126ba97 | 2825 | |
038d2ef8 | 2826 | mutex_init(&dev->flow_db.lock); |
e126ba97 | 2827 | mutex_init(&dev->cap_mask_mutex); |
89ea94a7 MG |
2828 | INIT_LIST_HEAD(&dev->qp_list); |
2829 | spin_lock_init(&dev->reset_flow_resource_lock); | |
e126ba97 | 2830 | |
fc24fc5e AS |
2831 | if (ll == IB_LINK_LAYER_ETHERNET) { |
2832 | err = mlx5_enable_roce(dev); | |
2833 | if (err) | |
2834 | goto err_dealloc; | |
2835 | } | |
2836 | ||
e126ba97 EC |
2837 | err = create_dev_resources(&dev->devr); |
2838 | if (err) | |
fc24fc5e | 2839 | goto err_disable_roce; |
e126ba97 | 2840 | |
6aec21f6 | 2841 | err = mlx5_ib_odp_init_one(dev); |
281d1a92 | 2842 | if (err) |
e126ba97 EC |
2843 | goto err_rsrc; |
2844 | ||
0837e86a | 2845 | err = mlx5_ib_alloc_q_counters(dev); |
6aec21f6 HE |
2846 | if (err) |
2847 | goto err_odp; | |
2848 | ||
0837e86a MB |
2849 | err = ib_register_device(&dev->ib_dev, NULL); |
2850 | if (err) | |
2851 | goto err_q_cnt; | |
2852 | ||
e126ba97 EC |
2853 | err = create_umr_res(dev); |
2854 | if (err) | |
2855 | goto err_dev; | |
2856 | ||
2857 | for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { | |
281d1a92 WY |
2858 | err = device_create_file(&dev->ib_dev.dev, |
2859 | mlx5_class_attributes[i]); | |
2860 | if (err) | |
e126ba97 EC |
2861 | goto err_umrc; |
2862 | } | |
2863 | ||
2864 | dev->ib_active = true; | |
2865 | ||
9603b61d | 2866 | return dev; |
e126ba97 EC |
2867 | |
2868 | err_umrc: | |
2869 | destroy_umrc_res(dev); | |
2870 | ||
2871 | err_dev: | |
2872 | ib_unregister_device(&dev->ib_dev); | |
2873 | ||
0837e86a MB |
2874 | err_q_cnt: |
2875 | mlx5_ib_dealloc_q_counters(dev); | |
2876 | ||
6aec21f6 HE |
2877 | err_odp: |
2878 | mlx5_ib_odp_remove_one(dev); | |
2879 | ||
e126ba97 EC |
2880 | err_rsrc: |
2881 | destroy_dev_resources(&dev->devr); | |
2882 | ||
fc24fc5e AS |
2883 | err_disable_roce: |
2884 | if (ll == IB_LINK_LAYER_ETHERNET) | |
2885 | mlx5_disable_roce(dev); | |
2886 | ||
0837e86a MB |
2887 | err_free_port: |
2888 | kfree(dev->port); | |
2889 | ||
9603b61d | 2890 | err_dealloc: |
e126ba97 EC |
2891 | ib_dealloc_device((struct ib_device *)dev); |
2892 | ||
9603b61d | 2893 | return NULL; |
e126ba97 EC |
2894 | } |
2895 | ||
9603b61d | 2896 | static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) |
e126ba97 | 2897 | { |
9603b61d | 2898 | struct mlx5_ib_dev *dev = context; |
fc24fc5e | 2899 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); |
6aec21f6 | 2900 | |
e126ba97 | 2901 | ib_unregister_device(&dev->ib_dev); |
0837e86a | 2902 | mlx5_ib_dealloc_q_counters(dev); |
eefd56e5 | 2903 | destroy_umrc_res(dev); |
6aec21f6 | 2904 | mlx5_ib_odp_remove_one(dev); |
e126ba97 | 2905 | destroy_dev_resources(&dev->devr); |
fc24fc5e AS |
2906 | if (ll == IB_LINK_LAYER_ETHERNET) |
2907 | mlx5_disable_roce(dev); | |
0837e86a | 2908 | kfree(dev->port); |
e126ba97 EC |
2909 | ib_dealloc_device(&dev->ib_dev); |
2910 | } | |
2911 | ||
9603b61d JM |
2912 | static struct mlx5_interface mlx5_ib_interface = { |
2913 | .add = mlx5_ib_add, | |
2914 | .remove = mlx5_ib_remove, | |
2915 | .event = mlx5_ib_event, | |
64613d94 | 2916 | .protocol = MLX5_INTERFACE_PROTOCOL_IB, |
e126ba97 EC |
2917 | }; |
2918 | ||
2919 | static int __init mlx5_ib_init(void) | |
2920 | { | |
6aec21f6 HE |
2921 | int err; |
2922 | ||
9603b61d JM |
2923 | if (deprecated_prof_sel != 2) |
2924 | pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); | |
2925 | ||
6aec21f6 HE |
2926 | err = mlx5_ib_odp_init(); |
2927 | if (err) | |
2928 | return err; | |
2929 | ||
2930 | err = mlx5_register_interface(&mlx5_ib_interface); | |
2931 | if (err) | |
2932 | goto clean_odp; | |
2933 | ||
2934 | return err; | |
2935 | ||
2936 | clean_odp: | |
2937 | mlx5_ib_odp_cleanup(); | |
2938 | return err; | |
e126ba97 EC |
2939 | } |
2940 | ||
2941 | static void __exit mlx5_ib_cleanup(void) | |
2942 | { | |
9603b61d | 2943 | mlx5_unregister_interface(&mlx5_ib_interface); |
6aec21f6 | 2944 | mlx5_ib_odp_cleanup(); |
e126ba97 EC |
2945 | } |
2946 | ||
2947 | module_init(mlx5_ib_init); | |
2948 | module_exit(mlx5_ib_cleanup); |