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net/mlx5: Add raw ethernet local loopback firmware command
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
37aa5c36
GL		 40#if defined(CONFIG_X86)
41#include <asm/pat.h>
42#endif
e126ba97 43#include <linux/sched.h>
6e84f315 44#include <linux/sched/mm.h>
0881e7bd 45#include <linux/sched/task.h>
7c2344c3 46#include <linux/delay.h>
e126ba97 47#include <rdma/ib_user_verbs.h>
3f89a643 48#include <rdma/ib_addr.h>
2811ba51 49#include <rdma/ib_cache.h>
ada68c31 50#include <linux/mlx5/port.h>
1b5daf11 51#include <linux/mlx5/vport.h>
7c2344c3 52#include <linux/list.h>
e126ba97
EC		 53#include <rdma/ib_smi.h>
54#include <rdma/ib_umem.h>
038d2ef8
MG		 55#include <linux/in.h>
56#include <linux/etherdevice.h>
57#include <linux/mlx5/fs.h>
78984898 58#include <linux/mlx5/vport.h>
e126ba97 59#include "mlx5_ib.h"
e1f24a79 60#include "cmd.h"
e126ba97
EC		 61
62#define DRIVER_NAME "mlx5_ib"
b359911d 63#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
68MODULE_VERSION(DRIVER_VERSION);
69
e126ba97
EC		 70static char mlx5_version[] =
71 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 72 DRIVER_VERSION "\n";
e126ba97 73
da7525d2
EBE		 74enum {
75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
76};
77
1b5daf11 78static enum rdma_link_layer
ebd61f68 79mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 80{
ebd61f68 81 switch (port_type_cap) {
1b5daf11
MD		 82 case MLX5_CAP_PORT_TYPE_IB:
83 return IB_LINK_LAYER_INFINIBAND;
84 case MLX5_CAP_PORT_TYPE_ETH:
85 return IB_LINK_LAYER_ETHERNET;
86 default:
87 return IB_LINK_LAYER_UNSPECIFIED;
88 }
89}
90
ebd61f68
AS		 91static enum rdma_link_layer
92mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
93{
94 struct mlx5_ib_dev *dev = to_mdev(device);
95 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
96
97 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
98}
99
fc24fc5e
AS		 100static int mlx5_netdev_event(struct notifier_block *this,
101 unsigned long event, void *ptr)
102{
103 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
104 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
105 roce.nb);
106
5ec8c83e
AH		 107 switch (event) {
108 case NETDEV_REGISTER:
109 case NETDEV_UNREGISTER:
110 write_lock(&ibdev->roce.netdev_lock);
111 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
112 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
113 NULL : ndev;
114 write_unlock(&ibdev->roce.netdev_lock);
115 break;
fc24fc5e 116
5ec8c83e 117 case NETDEV_UP:
88621dfe
AH		 118 case NETDEV_DOWN: {
119 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
120 struct net_device *upper = NULL;
121
122 if (lag_ndev) {
123 upper = netdev_master_upper_dev_get(lag_ndev);
124 dev_put(lag_ndev);
125 }
126
127 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
128 && ibdev->ib_active) {
626bc02d 129 struct ib_event ibev = { };
5ec8c83e
AH		 130
131 ibev.device = &ibdev->ib_dev;
132 ibev.event = (event == NETDEV_UP) ?
133 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
134 ibev.element.port_num = 1;
135 ib_dispatch_event(&ibev);
136 }
137 break;
88621dfe 138 }
fc24fc5e 139
5ec8c83e
AH		 140 default:
141 break;
142 }
fc24fc5e
AS		 143
144 return NOTIFY_DONE;
145}
146
147static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
148 u8 port_num)
149{
150 struct mlx5_ib_dev *ibdev = to_mdev(device);
151 struct net_device *ndev;
152
88621dfe
AH		 153 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
154 if (ndev)
155 return ndev;
156
fc24fc5e
AS		 157 /* Ensure ndev does not disappear before we invoke dev_hold()
158 */
159 read_lock(&ibdev->roce.netdev_lock);
160 ndev = ibdev->roce.netdev;
161 if (ndev)
162 dev_hold(ndev);
163 read_unlock(&ibdev->roce.netdev_lock);
164
165 return ndev;
166}
167
f1b65df5
NO		 168static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
169 u8 *active_width)
170{
171 switch (eth_proto_oper) {
172 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
173 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
174 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
175 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
176 *active_width = IB_WIDTH_1X;
177 *active_speed = IB_SPEED_SDR;
178 break;
179 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
180 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
181 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
182 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
183 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
184 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
185 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
186 *active_width = IB_WIDTH_1X;
187 *active_speed = IB_SPEED_QDR;
188 break;
189 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
190 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
191 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
192 *active_width = IB_WIDTH_1X;
193 *active_speed = IB_SPEED_EDR;
194 break;
195 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
196 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
197 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
198 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
199 *active_width = IB_WIDTH_4X;
200 *active_speed = IB_SPEED_QDR;
201 break;
202 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
203 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
204 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_HDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
209 *active_width = IB_WIDTH_4X;
210 *active_speed = IB_SPEED_FDR;
211 break;
212 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
213 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
214 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
215 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
216 *active_width = IB_WIDTH_4X;
217 *active_speed = IB_SPEED_EDR;
218 break;
219 default:
220 return -EINVAL;
221 }
222
223 return 0;
224}
225
095b0927
IT		 226static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
227 struct ib_port_attr *props)
3f89a643
AS		 228{
229 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 230 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 231 struct net_device *ndev, *upper;
3f89a643 232 enum ib_mtu ndev_ib_mtu;
c876a1b7 233 u16 qkey_viol_cntr;
f1b65df5 234 u32 eth_prot_oper;
095b0927 235 int err;
3f89a643 236
f1b65df5
NO		 237 /* Possible bad flows are checked before filling out props so in case
238 * of an error it will still be zeroed out.
50f22fd8 239 */
095b0927
IT		 240 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
241 if (err)
242 return err;
f1b65df5
NO		 243
244 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
245 &props->active_width);
3f89a643
AS		 246
247 props->port_cap_flags |= IB_PORT_CM_SUP;
248 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
249
250 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
251 roce_address_table_size);
252 props->max_mtu = IB_MTU_4096;
253 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
254 props->pkey_tbl_len = 1;
255 props->state = IB_PORT_DOWN;
256 props->phys_state = 3;
257
c876a1b7
LR		 258 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
259 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 260
261 ndev = mlx5_ib_get_netdev(device, port_num);
262 if (!ndev)
095b0927 263 return 0;
3f89a643 264
88621dfe
AH		 265 if (mlx5_lag_is_active(dev->mdev)) {
266 rcu_read_lock();
267 upper = netdev_master_upper_dev_get_rcu(ndev);
268 if (upper) {
269 dev_put(ndev);
270 ndev = upper;
271 dev_hold(ndev);
272 }
273 rcu_read_unlock();
274 }
275
3f89a643
AS		 276 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
277 props->state = IB_PORT_ACTIVE;
278 props->phys_state = 5;
279 }
280
281 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
282
283 dev_put(ndev);
284
285 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 286 return 0;
3f89a643
AS		 287}
288
095b0927
IT		 289static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
290 unsigned int index, const union ib_gid *gid,
291 const struct ib_gid_attr *attr)
3cca2606 292{
095b0927
IT		 293 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
294 u8 roce_version = 0;
295 u8 roce_l3_type = 0;
296 bool vlan = false;
297 u8 mac[ETH_ALEN];
298 u16 vlan_id = 0;
299
300 if (gid) {
301 gid_type = attr->gid_type;
302 ether_addr_copy(mac, attr->ndev->dev_addr);
303
304 if (is_vlan_dev(attr->ndev)) {
305 vlan = true;
306 vlan_id = vlan_dev_vlan_id(attr->ndev);
307 }
3cca2606
AS		 308 }
309
095b0927 310 switch (gid_type) {
3cca2606 311 case IB_GID_TYPE_IB:
095b0927 312 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 313 break;
314 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 315 roce_version = MLX5_ROCE_VERSION_2;
316 if (ipv6_addr_v4mapped((void *)gid))
317 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
318 else
319 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 320 break;
321
322 default:
095b0927 323 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 324 }
325
095b0927
IT		 326 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
327 roce_l3_type, gid->raw, mac, vlan,
328 vlan_id);
3cca2606
AS		 329}
330
331static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
332 unsigned int index, const union ib_gid *gid,
333 const struct ib_gid_attr *attr,
334 __always_unused void **context)
335{
095b0927 336 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 337}
338
339static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
340 unsigned int index, __always_unused void **context)
341{
095b0927 342 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 343}
344
2811ba51
AS		 345__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
346 int index)
347{
348 struct ib_gid_attr attr;
349 union ib_gid gid;
350
351 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
352 return 0;
353
354 if (!attr.ndev)
355 return 0;
356
357 dev_put(attr.ndev);
358
359 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
360 return 0;
361
362 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
363}
364
ed88451e
MD		 365int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
366 int index, enum ib_gid_type *gid_type)
367{
368 struct ib_gid_attr attr;
369 union ib_gid gid;
370 int ret;
371
372 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
373 if (ret)
374 return ret;
375
376 if (!attr.ndev)
377 return -ENODEV;
378
379 dev_put(attr.ndev);
380
381 *gid_type = attr.gid_type;
382
383 return 0;
384}
385
1b5daf11
MD		 386static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
387{
7fae6655
NO		 388 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
389 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
390 return 0;
1b5daf11
MD		 391}
392
393enum {
394 MLX5_VPORT_ACCESS_METHOD_MAD,
395 MLX5_VPORT_ACCESS_METHOD_HCA,
396 MLX5_VPORT_ACCESS_METHOD_NIC,
397};
398
399static int mlx5_get_vport_access_method(struct ib_device *ibdev)
400{
401 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
402 return MLX5_VPORT_ACCESS_METHOD_MAD;
403
ebd61f68 404 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 405 IB_LINK_LAYER_ETHERNET)
406 return MLX5_VPORT_ACCESS_METHOD_NIC;
407
408 return MLX5_VPORT_ACCESS_METHOD_HCA;
409}
410
da7525d2
EBE		 411static void get_atomic_caps(struct mlx5_ib_dev *dev,
412 struct ib_device_attr *props)
413{
414 u8 tmp;
415 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
416 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
417 u8 atomic_req_8B_endianness_mode =
bd10838a 418 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 419
420 /* Check if HW supports 8 bytes standard atomic operations and capable
421 * of host endianness respond
422 */
423 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
424 if (((atomic_operations & tmp) == tmp) &&
425 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
426 (atomic_req_8B_endianness_mode)) {
427 props->atomic_cap = IB_ATOMIC_HCA;
428 } else {
429 props->atomic_cap = IB_ATOMIC_NONE;
430 }
431}
432
1b5daf11
MD		 433static int mlx5_query_system_image_guid(struct ib_device *ibdev,
434 __be64 *sys_image_guid)
435{
436 struct mlx5_ib_dev *dev = to_mdev(ibdev);
437 struct mlx5_core_dev *mdev = dev->mdev;
438 u64 tmp;
439 int err;
440
441 switch (mlx5_get_vport_access_method(ibdev)) {
442 case MLX5_VPORT_ACCESS_METHOD_MAD:
443 return mlx5_query_mad_ifc_system_image_guid(ibdev,
444 sys_image_guid);
445
446 case MLX5_VPORT_ACCESS_METHOD_HCA:
447 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 448 break;
449
450 case MLX5_VPORT_ACCESS_METHOD_NIC:
451 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
452 break;
1b5daf11
MD		 453
454 default:
455 return -EINVAL;
456 }
3f89a643
AS		 457
458 if (!err)
459 *sys_image_guid = cpu_to_be64(tmp);
460
461 return err;
462
1b5daf11
MD		 463}
464
465static int mlx5_query_max_pkeys(struct ib_device *ibdev,
466 u16 *max_pkeys)
467{
468 struct mlx5_ib_dev *dev = to_mdev(ibdev);
469 struct mlx5_core_dev *mdev = dev->mdev;
470
471 switch (mlx5_get_vport_access_method(ibdev)) {
472 case MLX5_VPORT_ACCESS_METHOD_MAD:
473 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 case MLX5_VPORT_ACCESS_METHOD_NIC:
477 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
478 pkey_table_size));
479 return 0;
480
481 default:
482 return -EINVAL;
483 }
484}
485
486static int mlx5_query_vendor_id(struct ib_device *ibdev,
487 u32 *vendor_id)
488{
489 struct mlx5_ib_dev *dev = to_mdev(ibdev);
490
491 switch (mlx5_get_vport_access_method(ibdev)) {
492 case MLX5_VPORT_ACCESS_METHOD_MAD:
493 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
494
495 case MLX5_VPORT_ACCESS_METHOD_HCA:
496 case MLX5_VPORT_ACCESS_METHOD_NIC:
497 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
498
499 default:
500 return -EINVAL;
501 }
502}
503
504static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
505 __be64 *node_guid)
506{
507 u64 tmp;
508 int err;
509
510 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
511 case MLX5_VPORT_ACCESS_METHOD_MAD:
512 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
513
514 case MLX5_VPORT_ACCESS_METHOD_HCA:
515 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 516 break;
517
518 case MLX5_VPORT_ACCESS_METHOD_NIC:
519 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
520 break;
1b5daf11
MD		 521
522 default:
523 return -EINVAL;
524 }
3f89a643
AS		 525
526 if (!err)
527 *node_guid = cpu_to_be64(tmp);
528
529 return err;
1b5daf11
MD		 530}
531
532struct mlx5_reg_node_desc {
bd99fdea 533 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 534};
535
536static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
537{
538 struct mlx5_reg_node_desc in;
539
540 if (mlx5_use_mad_ifc(dev))
541 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
542
543 memset(&in, 0, sizeof(in));
544
545 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
546 sizeof(struct mlx5_reg_node_desc),
547 MLX5_REG_NODE_DESC, 0, 0);
548}
549
e126ba97 550static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 551 struct ib_device_attr *props,
552 struct ib_udata *uhw)
e126ba97
EC		 553{
554 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 555 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 556 int err = -ENOMEM;
288c01b7 557 int max_sq_desc;
e126ba97
EC		 558 int max_rq_sg;
559 int max_sq_sg;
e0238a6a 560 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 561 struct mlx5_ib_query_device_resp resp = {};
562 size_t resp_len;
563 u64 max_tso;
e126ba97 564
402ca536
BW		 565 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
566 if (uhw->outlen && uhw->outlen < resp_len)
567 return -EINVAL;
568 else
569 resp.response_length = resp_len;
570
571 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 572 return -EINVAL;
573
1b5daf11
MD		 574 memset(props, 0, sizeof(*props));
575 err = mlx5_query_system_image_guid(ibdev,
576 &props->sys_image_guid);
577 if (err)
578 return err;
e126ba97 579
1b5daf11 580 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 581 if (err)
1b5daf11 582 return err;
e126ba97 583
1b5daf11
MD		 584 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
585 if (err)
586 return err;
e126ba97 587
9603b61d
JM		 588 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
589 (fw_rev_min(dev->mdev) << 16) |
590 fw_rev_sub(dev->mdev);
e126ba97
EC		 591 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
592 IB_DEVICE_PORT_ACTIVE_EVENT |
593 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 594 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 595
596 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 597 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 598 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 599 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 600 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 601 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 602 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 603 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 604 if (MLX5_CAP_GEN(mdev, imaicl)) {
605 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
606 IB_DEVICE_MEM_WINDOW_TYPE_2B;
607 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 608 /* We support 'Gappy' memory registration too */
609 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 610 }
e126ba97 611 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 612 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 613 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
614 /* At this stage no support for signature handover */
615 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
616 IB_PROT_T10DIF_TYPE_2 |
617 IB_PROT_T10DIF_TYPE_3;
618 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
619 IB_GUARD_T10DIF_CSUM;
620 }
938fe83c 621 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 622 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 623
402ca536 624 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 625 if (MLX5_CAP_ETH(mdev, csum_cap)) {
626 /* Legacy bit to support old userspace libraries */
88115fe7 627 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 628 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
629 }
630
631 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
632 props->raw_packet_caps |=
633 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 634
402ca536
BW		 635 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
636 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
637 if (max_tso) {
638 resp.tso_caps.max_tso = 1 << max_tso;
639 resp.tso_caps.supported_qpts |=
640 1 << IB_QPT_RAW_PACKET;
641 resp.response_length += sizeof(resp.tso_caps);
642 }
643 }
31f69a82
YH		 644
645 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
646 resp.rss_caps.rx_hash_function =
647 MLX5_RX_HASH_FUNC_TOEPLITZ;
648 resp.rss_caps.rx_hash_fields_mask =
649 MLX5_RX_HASH_SRC_IPV4 |
650 MLX5_RX_HASH_DST_IPV4 |
651 MLX5_RX_HASH_SRC_IPV6 |
652 MLX5_RX_HASH_DST_IPV6 |
653 MLX5_RX_HASH_SRC_PORT_TCP |
654 MLX5_RX_HASH_DST_PORT_TCP |
655 MLX5_RX_HASH_SRC_PORT_UDP |
656 MLX5_RX_HASH_DST_PORT_UDP;
657 resp.response_length += sizeof(resp.rss_caps);
658 }
659 } else {
660 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
661 resp.response_length += sizeof(resp.tso_caps);
662 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
663 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 664 }
665
f0313965
ES		 666 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
667 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
668 props->device_cap_flags |= IB_DEVICE_UD_TSO;
669 }
670
cff5a0f3 671 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 672 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
673 /* Legacy bit to support old userspace libraries */
cff5a0f3 674 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 675 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
676 }
cff5a0f3 677
da6d6ba3
MG		 678 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
679 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
680
1b5daf11
MD		 681 props->vendor_part_id = mdev->pdev->device;
682 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 683
684 props->max_mr_size = ~0ull;
e0238a6a 685 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 686 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
687 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
688 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
689 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 690 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
691 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
692 sizeof(struct mlx5_wqe_raddr_seg)) /
693 sizeof(struct mlx5_wqe_data_seg);
e126ba97 694 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 695 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 696 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 697 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 698 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
699 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
700 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
701 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
702 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
703 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
704 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 705 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 706 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 707 props->max_fast_reg_page_list_len =
708 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 709 get_atomic_caps(dev, props);
81bea28f 710 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 711 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
712 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 713 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
714 props->max_mcast_grp;
715 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 716 props->max_ah = INT_MAX;
7c60bcbb
MB		 717 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
718 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 719
8cdd312c 720#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 721 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 722 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
723 props->odp_caps = dev->odp_caps;
724#endif
725
051f2630
LR		 726 if (MLX5_CAP_GEN(mdev, cd))
727 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
728
eff901d3
EC		 729 if (!mlx5_core_is_pf(mdev))
730 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
731
31f69a82
YH		 732 if (mlx5_ib_port_link_layer(ibdev, 1) ==
733 IB_LINK_LAYER_ETHERNET) {
734 props->rss_caps.max_rwq_indirection_tables =
735 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
736 props->rss_caps.max_rwq_indirection_table_size =
737 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
738 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
739 props->max_wq_type_rq =
740 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
741 }
742
7e43a2a5
BW		 743 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
744 resp.cqe_comp_caps.max_num =
745 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
746 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
747 resp.cqe_comp_caps.supported_format =
748 MLX5_IB_CQE_RES_FORMAT_HASH |
749 MLX5_IB_CQE_RES_FORMAT_CSUM;
750 resp.response_length += sizeof(resp.cqe_comp_caps);
751 }
752
d949167d
BW		 753 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
754 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
755 MLX5_CAP_GEN(mdev, qos)) {
756 resp.packet_pacing_caps.qp_rate_limit_max =
757 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
758 resp.packet_pacing_caps.qp_rate_limit_min =
759 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
760 resp.packet_pacing_caps.supported_qpts |=
761 1 << IB_QPT_RAW_PACKET;
762 }
763 resp.response_length += sizeof(resp.packet_pacing_caps);
764 }
765
9f885201
LR		 766 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
767 uhw->outlen)) {
768 resp.mlx5_ib_support_multi_pkt_send_wqes =
769 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
770 resp.response_length +=
771 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
772 }
773
774 if (field_avail(typeof(resp), reserved, uhw->outlen))
775 resp.response_length += sizeof(resp.reserved);
776
402ca536
BW		 777 if (uhw->outlen) {
778 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
779
780 if (err)
781 return err;
782 }
783
1b5daf11 784 return 0;
e126ba97
EC		 785}
786
1b5daf11
MD		 787enum mlx5_ib_width {
788 MLX5_IB_WIDTH_1X = 1 << 0,
789 MLX5_IB_WIDTH_2X = 1 << 1,
790 MLX5_IB_WIDTH_4X = 1 << 2,
791 MLX5_IB_WIDTH_8X = 1 << 3,
792 MLX5_IB_WIDTH_12X = 1 << 4
793};
794
795static int translate_active_width(struct ib_device *ibdev, u8 active_width,
796 u8 *ib_width)
e126ba97
EC		 797{
798 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 799 int err = 0;
800
801 if (active_width & MLX5_IB_WIDTH_1X) {
802 *ib_width = IB_WIDTH_1X;
803 } else if (active_width & MLX5_IB_WIDTH_2X) {
804 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
805 (int)active_width);
806 err = -EINVAL;
807 } else if (active_width & MLX5_IB_WIDTH_4X) {
808 *ib_width = IB_WIDTH_4X;
809 } else if (active_width & MLX5_IB_WIDTH_8X) {
810 *ib_width = IB_WIDTH_8X;
811 } else if (active_width & MLX5_IB_WIDTH_12X) {
812 *ib_width = IB_WIDTH_12X;
813 } else {
814 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
815 (int)active_width);
816 err = -EINVAL;
e126ba97
EC		 817 }
818
1b5daf11
MD		 819 return err;
820}
e126ba97 821
1b5daf11
MD		 822static int mlx5_mtu_to_ib_mtu(int mtu)
823{
824 switch (mtu) {
825 case 256: return 1;
826 case 512: return 2;
827 case 1024: return 3;
828 case 2048: return 4;
829 case 4096: return 5;
830 default:
831 pr_warn("invalid mtu\n");
832 return -1;
e126ba97 833 }
1b5daf11 834}
e126ba97 835
1b5daf11
MD		 836enum ib_max_vl_num {
837 __IB_MAX_VL_0 = 1,
838 __IB_MAX_VL_0_1 = 2,
839 __IB_MAX_VL_0_3 = 3,
840 __IB_MAX_VL_0_7 = 4,
841 __IB_MAX_VL_0_14 = 5,
842};
e126ba97 843
1b5daf11
MD		 844enum mlx5_vl_hw_cap {
845 MLX5_VL_HW_0 = 1,
846 MLX5_VL_HW_0_1 = 2,
847 MLX5_VL_HW_0_2 = 3,
848 MLX5_VL_HW_0_3 = 4,
849 MLX5_VL_HW_0_4 = 5,
850 MLX5_VL_HW_0_5 = 6,
851 MLX5_VL_HW_0_6 = 7,
852 MLX5_VL_HW_0_7 = 8,
853 MLX5_VL_HW_0_14 = 15
854};
e126ba97 855
1b5daf11
MD		 856static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
857 u8 *max_vl_num)
858{
859 switch (vl_hw_cap) {
860 case MLX5_VL_HW_0:
861 *max_vl_num = __IB_MAX_VL_0;
862 break;
863 case MLX5_VL_HW_0_1:
864 *max_vl_num = __IB_MAX_VL_0_1;
865 break;
866 case MLX5_VL_HW_0_3:
867 *max_vl_num = __IB_MAX_VL_0_3;
868 break;
869 case MLX5_VL_HW_0_7:
870 *max_vl_num = __IB_MAX_VL_0_7;
871 break;
872 case MLX5_VL_HW_0_14:
873 *max_vl_num = __IB_MAX_VL_0_14;
874 break;
e126ba97 875
1b5daf11
MD		 876 default:
877 return -EINVAL;
e126ba97 878 }
e126ba97 879
1b5daf11 880 return 0;
e126ba97
EC		 881}
882
1b5daf11
MD		 883static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
884 struct ib_port_attr *props)
e126ba97 885{
1b5daf11
MD		 886 struct mlx5_ib_dev *dev = to_mdev(ibdev);
887 struct mlx5_core_dev *mdev = dev->mdev;
888 struct mlx5_hca_vport_context *rep;
046339ea
SM		 889 u16 max_mtu;
890 u16 oper_mtu;
1b5daf11
MD		 891 int err;
892 u8 ib_link_width_oper;
893 u8 vl_hw_cap;
e126ba97 894
1b5daf11
MD		 895 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
896 if (!rep) {
897 err = -ENOMEM;
e126ba97 898 goto out;
e126ba97 899 }
e126ba97 900
c4550c63 901 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 902
1b5daf11 903 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 904 if (err)
905 goto out;
906
1b5daf11
MD		 907 props->lid = rep->lid;
908 props->lmc = rep->lmc;
909 props->sm_lid = rep->sm_lid;
910 props->sm_sl = rep->sm_sl;
911 props->state = rep->vport_state;
912 props->phys_state = rep->port_physical_state;
913 props->port_cap_flags = rep->cap_mask1;
914 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
915 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
916 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
917 props->bad_pkey_cntr = rep->pkey_violation_counter;
918 props->qkey_viol_cntr = rep->qkey_violation_counter;
919 props->subnet_timeout = rep->subnet_timeout;
920 props->init_type_reply = rep->init_type_reply;
eff901d3 921 props->grh_required = rep->grh_required;
e126ba97 922
1b5daf11
MD		 923 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
924 if (err)
e126ba97 925 goto out;
e126ba97 926
1b5daf11
MD		 927 err = translate_active_width(ibdev, ib_link_width_oper,
928 &props->active_width);
929 if (err)
930 goto out;
d5beb7f2 931 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 932 if (err)
933 goto out;
934
facc9699 935 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 936
1b5daf11 937 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 938
facc9699 939 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 940
1b5daf11 941 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 942
1b5daf11
MD		 943 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
944 if (err)
945 goto out;
e126ba97 946
1b5daf11
MD		 947 err = translate_max_vl_num(ibdev, vl_hw_cap,
948 &props->max_vl_num);
e126ba97 949out:
1b5daf11 950 kfree(rep);
e126ba97
EC		 951 return err;
952}
953
1b5daf11
MD		 954int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
955 struct ib_port_attr *props)
e126ba97 956{
095b0927
IT		 957 unsigned int count;
958 int ret;
959
1b5daf11
MD		 960 switch (mlx5_get_vport_access_method(ibdev)) {
961 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 962 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
963 break;
e126ba97 964
1b5daf11 965 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 966 ret = mlx5_query_hca_port(ibdev, port, props);
967 break;
e126ba97 968
3f89a643 969 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 970 ret = mlx5_query_port_roce(ibdev, port, props);
971 break;
3f89a643 972
1b5daf11 973 default:
095b0927
IT		 974 ret = -EINVAL;
975 }
976
977 if (!ret && props) {
978 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
979 props->gid_tbl_len -= count;
1b5daf11 980 }
095b0927 981 return ret;
1b5daf11 982}
e126ba97 983
1b5daf11
MD		 984static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
985 union ib_gid *gid)
986{
987 struct mlx5_ib_dev *dev = to_mdev(ibdev);
988 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 989
1b5daf11
MD		 990 switch (mlx5_get_vport_access_method(ibdev)) {
991 case MLX5_VPORT_ACCESS_METHOD_MAD:
992 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 993
1b5daf11
MD		 994 case MLX5_VPORT_ACCESS_METHOD_HCA:
995 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
996
997 default:
998 return -EINVAL;
999 }
e126ba97 1000
e126ba97
EC		 1001}
1002
1b5daf11
MD		 1003static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1004 u16 *pkey)
1005{
1006 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1007 struct mlx5_core_dev *mdev = dev->mdev;
1008
1009 switch (mlx5_get_vport_access_method(ibdev)) {
1010 case MLX5_VPORT_ACCESS_METHOD_MAD:
1011 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1012
1013 case MLX5_VPORT_ACCESS_METHOD_HCA:
1014 case MLX5_VPORT_ACCESS_METHOD_NIC:
1015 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1016 pkey);
1017 default:
1018 return -EINVAL;
1019 }
1020}
e126ba97
EC		 1021
1022static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1023 struct ib_device_modify *props)
1024{
1025 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1026 struct mlx5_reg_node_desc in;
1027 struct mlx5_reg_node_desc out;
1028 int err;
1029
1030 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1031 return -EOPNOTSUPP;
1032
1033 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1034 return 0;
1035
1036 /*
1037 * If possible, pass node desc to FW, so it can generate
1038 * a 144 trap. If cmd fails, just ignore.
1039 */
bd99fdea 1040 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1041 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1042 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1043 if (err)
1044 return err;
1045
bd99fdea 1046 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1047
1048 return err;
1049}
1050
cdbe33d0
EC		 1051static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1052 u32 value)
1053{
1054 struct mlx5_hca_vport_context ctx = {};
1055 int err;
1056
1057 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1058 port_num, 0, &ctx);
1059 if (err)
1060 return err;
1061
1062 if (~ctx.cap_mask1_perm & mask) {
1063 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1064 mask, ctx.cap_mask1_perm);
1065 return -EINVAL;
1066 }
1067
1068 ctx.cap_mask1 = value;
1069 ctx.cap_mask1_perm = mask;
1070 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1071 port_num, 0, &ctx);
1072
1073 return err;
1074}
1075
e126ba97
EC		 1076static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1077 struct ib_port_modify *props)
1078{
1079 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1080 struct ib_port_attr attr;
1081 u32 tmp;
1082 int err;
cdbe33d0
EC		 1083 u32 change_mask;
1084 u32 value;
1085 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1086 IB_LINK_LAYER_INFINIBAND);
1087
1088 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1089 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1090 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1091 return set_port_caps_atomic(dev, port, change_mask, value);
1092 }
e126ba97
EC		 1093
1094 mutex_lock(&dev->cap_mask_mutex);
1095
c4550c63 1096 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1097 if (err)
1098 goto out;
1099
1100 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1101 ~props->clr_port_cap_mask;
1102
9603b61d 1103 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1104
1105out:
1106 mutex_unlock(&dev->cap_mask_mutex);
1107 return err;
1108}
1109
30aa60b3
EC		 1110static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1111{
1112 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1113 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1114}
1115
b037c29a
EC		 1116static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1117 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1118 u32 *num_sys_pages)
1119{
1120 int uars_per_sys_page;
1121 int bfregs_per_sys_page;
1122 int ref_bfregs = req->total_num_bfregs;
1123
1124 if (req->total_num_bfregs == 0)
1125 return -EINVAL;
1126
1127 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1128 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1129
1130 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1131 return -ENOMEM;
1132
1133 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1134 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1135 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1136 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1137
1138 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1139 return -EINVAL;
1140
1141 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1142 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1143 lib_uar_4k ? "yes" : "no", ref_bfregs,
1144 req->total_num_bfregs, *num_sys_pages);
1145
1146 return 0;
1147}
1148
1149static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1150{
1151 struct mlx5_bfreg_info *bfregi;
1152 int err;
1153 int i;
1154
1155 bfregi = &context->bfregi;
1156 for (i = 0; i < bfregi->num_sys_pages; i++) {
1157 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1158 if (err)
1159 goto error;
1160
1161 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1162 }
1163 return 0;
1164
1165error:
1166 for (--i; i >= 0; i--)
1167 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1168 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1169
1170 return err;
1171}
1172
1173static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1174{
1175 struct mlx5_bfreg_info *bfregi;
1176 int err;
1177 int i;
1178
1179 bfregi = &context->bfregi;
1180 for (i = 0; i < bfregi->num_sys_pages; i++) {
1181 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1182 if (err) {
1183 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1184 return err;
1185 }
1186 }
1187 return 0;
1188}
1189
e126ba97
EC		 1190static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1191 struct ib_udata *udata)
1192{
1193 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1194 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1195 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1196 struct mlx5_ib_ucontext *context;
2f5ff264 1197 struct mlx5_bfreg_info *bfregi;
78c0f98c 1198 int ver;
e126ba97 1199 int err;
f241e749 1200 size_t reqlen;
a168a41c
MD		 1201 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1202 max_cqe_version);
b037c29a 1203 bool lib_uar_4k;
e126ba97
EC		 1204
1205 if (!dev->ib_active)
1206 return ERR_PTR(-EAGAIN);
1207
dfbee859
HA		 1208 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1209 return ERR_PTR(-EINVAL);
1210
78c0f98c
EC		 1211 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1212 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1213 ver = 0;
a168a41c 1214 else if (reqlen >= min_req_v2)
78c0f98c
EC		 1215 ver = 2;
1216 else
1217 return ERR_PTR(-EINVAL);
1218
b368d7cb 1219 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 1220 if (err)
1221 return ERR_PTR(err);
1222
b368d7cb 1223 if (req.flags)
78c0f98c
EC		 1224 return ERR_PTR(-EINVAL);
1225
f72300c5 1226 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1227 return ERR_PTR(-EOPNOTSUPP);
1228
2f5ff264
EC		 1229 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1230 MLX5_NON_FP_BFREGS_PER_UAR);
1231 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1232 return ERR_PTR(-EINVAL);
1233
938fe83c 1234 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1235 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1236 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1237 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1238 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1239 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1240 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1241 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1242 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1243 resp.cqe_version = min_t(__u8,
1244 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1245 req.max_cqe_version);
30aa60b3
EC		 1246 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1247 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1248 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1249 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1250 resp.response_length = min(offsetof(typeof(resp), response_length) +
1251 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1252
1253 context = kzalloc(sizeof(*context), GFP_KERNEL);
1254 if (!context)
1255 return ERR_PTR(-ENOMEM);
1256
30aa60b3 1257 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1258 bfregi = &context->bfregi;
b037c29a
EC		 1259
1260 /* updates req->total_num_bfregs */
1261 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1262 if (err)
e126ba97 1263 goto out_ctx;
e126ba97 1264
b037c29a
EC		 1265 mutex_init(&bfregi->lock);
1266 bfregi->lib_uar_4k = lib_uar_4k;
1267 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1268 GFP_KERNEL);
b037c29a 1269 if (!bfregi->count) {
e126ba97 1270 err = -ENOMEM;
b037c29a 1271 goto out_ctx;
e126ba97
EC		 1272 }
1273
b037c29a
EC		 1274 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1275 sizeof(*bfregi->sys_pages),
1276 GFP_KERNEL);
1277 if (!bfregi->sys_pages) {
e126ba97 1278 err = -ENOMEM;
b037c29a 1279 goto out_count;
e126ba97
EC		 1280 }
1281
b037c29a
EC		 1282 err = allocate_uars(dev, context);
1283 if (err)
1284 goto out_sys_pages;
e126ba97 1285
b4cfe447
HE		 1286#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1287 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1288#endif
1289
7d0cc6ed
AK		 1290 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1291 if (!context->upd_xlt_page) {
1292 err = -ENOMEM;
1293 goto out_uars;
1294 }
1295 mutex_init(&context->upd_xlt_page_mutex);
1296
146d2f1a 1297 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1298 err = mlx5_core_alloc_transport_domain(dev->mdev,
1299 &context->tdn);
1300 if (err)
7d0cc6ed 1301 goto out_page;
146d2f1a 1302 }
1303
7c2344c3 1304 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1305 INIT_LIST_HEAD(&context->db_page_list);
1306 mutex_init(&context->db_page_mutex);
1307
2f5ff264 1308 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1309 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1310
f72300c5
HA		 1311 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1312 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1313
402ca536 1314 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1315 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1316 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1317 resp.response_length += sizeof(resp.cmds_supp_uhw);
1318 }
1319
78984898
OG		 1320 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1321 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1322 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1323 resp.eth_min_inline++;
1324 }
1325 resp.response_length += sizeof(resp.eth_min_inline);
1326 }
1327
bc5c6eed
NO		 1328 /*
1329 * We don't want to expose information from the PCI bar that is located
1330 * after 4096 bytes, so if the arch only supports larger pages, let's
1331 * pretend we don't support reading the HCA's core clock. This is also
1332 * forced by mmap function.
1333 */
de8d6e02
EC		 1334 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1335 if (PAGE_SIZE <= 4096) {
1336 resp.comp_mask |=
1337 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1338 resp.hca_core_clock_offset =
1339 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1340 }
f72300c5 1341 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1342 sizeof(resp.reserved2);
b368d7cb
MB		 1343 }
1344
30aa60b3
EC		 1345 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1346 resp.response_length += sizeof(resp.log_uar_size);
1347
1348 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1349 resp.response_length += sizeof(resp.num_uars_per_page);
1350
b368d7cb 1351 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1352 if (err)
146d2f1a 1353 goto out_td;
e126ba97 1354
2f5ff264
EC		 1355 bfregi->ver = ver;
1356 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1357 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1358 context->lib_caps = req.lib_caps;
1359 print_lib_caps(dev, context->lib_caps);
f72300c5 1360
e126ba97
EC		 1361 return &context->ibucontext;
1362
146d2f1a 1363out_td:
1364 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1365 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1366
7d0cc6ed
AK		 1367out_page:
1368 free_page(context->upd_xlt_page);
1369
e126ba97 1370out_uars:
b037c29a 1371 deallocate_uars(dev, context);
e126ba97 1372
b037c29a
EC		 1373out_sys_pages:
1374 kfree(bfregi->sys_pages);
e126ba97 1375
b037c29a
EC		 1376out_count:
1377 kfree(bfregi->count);
e126ba97
EC		 1378
1379out_ctx:
1380 kfree(context);
b037c29a 1381
e126ba97
EC		 1382 return ERR_PTR(err);
1383}
1384
1385static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1386{
1387 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1388 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1389 struct mlx5_bfreg_info *bfregi;
e126ba97 1390
b037c29a 1391 bfregi = &context->bfregi;
146d2f1a 1392 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1393 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1394
7d0cc6ed 1395 free_page(context->upd_xlt_page);
b037c29a
EC		 1396 deallocate_uars(dev, context);
1397 kfree(bfregi->sys_pages);
2f5ff264 1398 kfree(bfregi->count);
e126ba97
EC		 1399 kfree(context);
1400
1401 return 0;
1402}
1403
b037c29a
EC		 1404static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1405 struct mlx5_bfreg_info *bfregi,
1406 int idx)
e126ba97 1407{
b037c29a
EC		 1408 int fw_uars_per_page;
1409
1410 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1411
1412 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1413 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1414}
1415
1416static int get_command(unsigned long offset)
1417{
1418 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1419}
1420
1421static int get_arg(unsigned long offset)
1422{
1423 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1424}
1425
1426static int get_index(unsigned long offset)
1427{
1428 return get_arg(offset);
1429}
1430
7c2344c3
MG		 1431static void mlx5_ib_vma_open(struct vm_area_struct *area)
1432{
1433 /* vma_open is called when a new VMA is created on top of our VMA. This
1434 * is done through either mremap flow or split_vma (usually due to
1435 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1436 * as this VMA is strongly hardware related. Therefore we set the
1437 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1438 * calling us again and trying to do incorrect actions. We assume that
1439 * the original VMA size is exactly a single page, and therefore all
1440 * "splitting" operation will not happen to it.
1441 */
1442 area->vm_ops = NULL;
1443}
1444
1445static void mlx5_ib_vma_close(struct vm_area_struct *area)
1446{
1447 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1448
1449 /* It's guaranteed that all VMAs opened on a FD are closed before the
1450 * file itself is closed, therefore no sync is needed with the regular
1451 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1452 * However need a sync with accessing the vma as part of
1453 * mlx5_ib_disassociate_ucontext.
1454 * The close operation is usually called under mm->mmap_sem except when
1455 * process is exiting.
1456 * The exiting case is handled explicitly as part of
1457 * mlx5_ib_disassociate_ucontext.
1458 */
1459 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1460
1461 /* setting the vma context pointer to null in the mlx5_ib driver's
1462 * private data, to protect a race condition in
1463 * mlx5_ib_disassociate_ucontext().
1464 */
1465 mlx5_ib_vma_priv_data->vma = NULL;
1466 list_del(&mlx5_ib_vma_priv_data->list);
1467 kfree(mlx5_ib_vma_priv_data);
1468}
1469
1470static const struct vm_operations_struct mlx5_ib_vm_ops = {
1471 .open = mlx5_ib_vma_open,
1472 .close = mlx5_ib_vma_close
1473};
1474
1475static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1476 struct mlx5_ib_ucontext *ctx)
1477{
1478 struct mlx5_ib_vma_private_data *vma_prv;
1479 struct list_head *vma_head = &ctx->vma_private_list;
1480
1481 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1482 if (!vma_prv)
1483 return -ENOMEM;
1484
1485 vma_prv->vma = vma;
1486 vma->vm_private_data = vma_prv;
1487 vma->vm_ops = &mlx5_ib_vm_ops;
1488
1489 list_add(&vma_prv->list, vma_head);
1490
1491 return 0;
1492}
1493
1494static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1495{
1496 int ret;
1497 struct vm_area_struct *vma;
1498 struct mlx5_ib_vma_private_data *vma_private, *n;
1499 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1500 struct task_struct *owning_process = NULL;
1501 struct mm_struct *owning_mm = NULL;
1502
1503 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1504 if (!owning_process)
1505 return;
1506
1507 owning_mm = get_task_mm(owning_process);
1508 if (!owning_mm) {
1509 pr_info("no mm, disassociate ucontext is pending task termination\n");
1510 while (1) {
1511 put_task_struct(owning_process);
1512 usleep_range(1000, 2000);
1513 owning_process = get_pid_task(ibcontext->tgid,
1514 PIDTYPE_PID);
1515 if (!owning_process ||
1516 owning_process->state == TASK_DEAD) {
1517 pr_info("disassociate ucontext done, task was terminated\n");
1518 /* in case task was dead need to release the
1519 * task struct.
1520 */
1521 if (owning_process)
1522 put_task_struct(owning_process);
1523 return;
1524 }
1525 }
1526 }
1527
1528 /* need to protect from a race on closing the vma as part of
1529 * mlx5_ib_vma_close.
1530 */
ecc7d83b 1531 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1532 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1533 list) {
1534 vma = vma_private->vma;
1535 ret = zap_vma_ptes(vma, vma->vm_start,
1536 PAGE_SIZE);
1537 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1538 /* context going to be destroyed, should
1539 * not access ops any more.
1540 */
13776612 1541 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1542 vma->vm_ops = NULL;
1543 list_del(&vma_private->list);
1544 kfree(vma_private);
1545 }
ecc7d83b 1546 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1547 mmput(owning_mm);
1548 put_task_struct(owning_process);
1549}
1550
37aa5c36
GL		 1551static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1552{
1553 switch (cmd) {
1554 case MLX5_IB_MMAP_WC_PAGE:
1555 return "WC";
1556 case MLX5_IB_MMAP_REGULAR_PAGE:
1557 return "best effort WC";
1558 case MLX5_IB_MMAP_NC_PAGE:
1559 return "NC";
1560 default:
1561 return NULL;
1562 }
1563}
1564
1565static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1566 struct vm_area_struct *vma,
1567 struct mlx5_ib_ucontext *context)
37aa5c36 1568{
2f5ff264 1569 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1570 int err;
1571 unsigned long idx;
1572 phys_addr_t pfn, pa;
1573 pgprot_t prot;
b037c29a
EC		 1574 int uars_per_page;
1575
1576 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1577 return -EINVAL;
1578
1579 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1580 idx = get_index(vma->vm_pgoff);
1581 if (idx % uars_per_page ||
1582 idx * uars_per_page >= bfregi->num_sys_pages) {
1583 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1584 return -EINVAL;
1585 }
37aa5c36
GL		 1586
1587 switch (cmd) {
1588 case MLX5_IB_MMAP_WC_PAGE:
1589/* Some architectures don't support WC memory */
1590#if defined(CONFIG_X86)
1591 if (!pat_enabled())
1592 return -EPERM;
1593#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1594 return -EPERM;
1595#endif
1596 /* fall through */
1597 case MLX5_IB_MMAP_REGULAR_PAGE:
1598 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1599 prot = pgprot_writecombine(vma->vm_page_prot);
1600 break;
1601 case MLX5_IB_MMAP_NC_PAGE:
1602 prot = pgprot_noncached(vma->vm_page_prot);
1603 break;
1604 default:
1605 return -EINVAL;
1606 }
1607
b037c29a 1608 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1609 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1610
1611 vma->vm_page_prot = prot;
1612 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1613 PAGE_SIZE, vma->vm_page_prot);
1614 if (err) {
1615 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1616 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1617 return -EAGAIN;
1618 }
1619
1620 pa = pfn << PAGE_SHIFT;
1621 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1622 vma->vm_start, &pa);
1623
7c2344c3 1624 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1625}
1626
e126ba97
EC		 1627static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1628{
1629 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1630 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1631 unsigned long command;
e126ba97
EC		 1632 phys_addr_t pfn;
1633
1634 command = get_command(vma->vm_pgoff);
1635 switch (command) {
37aa5c36
GL		 1636 case MLX5_IB_MMAP_WC_PAGE:
1637 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1638 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1639 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1640
1641 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1642 return -ENOSYS;
1643
d69e3bcf 1644 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1645 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1646 return -EINVAL;
1647
6cbac1e4 1648 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1649 return -EPERM;
1650
1651 /* Don't expose to user-space information it shouldn't have */
1652 if (PAGE_SIZE > 4096)
1653 return -EOPNOTSUPP;
1654
1655 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1656 pfn = (dev->mdev->iseg_base +
1657 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1658 PAGE_SHIFT;
1659 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1660 PAGE_SIZE, vma->vm_page_prot))
1661 return -EAGAIN;
1662
1663 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1664 vma->vm_start,
1665 (unsigned long long)pfn << PAGE_SHIFT);
1666 break;
d69e3bcf 1667
e126ba97
EC		 1668 default:
1669 return -EINVAL;
1670 }
1671
1672 return 0;
1673}
1674
e126ba97
EC		 1675static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1676 struct ib_ucontext *context,
1677 struct ib_udata *udata)
1678{
1679 struct mlx5_ib_alloc_pd_resp resp;
1680 struct mlx5_ib_pd *pd;
1681 int err;
1682
1683 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1684 if (!pd)
1685 return ERR_PTR(-ENOMEM);
1686
9603b61d 1687 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1688 if (err) {
1689 kfree(pd);
1690 return ERR_PTR(err);
1691 }
1692
1693 if (context) {
1694 resp.pdn = pd->pdn;
1695 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1696 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1697 kfree(pd);
1698 return ERR_PTR(-EFAULT);
1699 }
e126ba97
EC		 1700 }
1701
1702 return &pd->ibpd;
1703}
1704
1705static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1706{
1707 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1708 struct mlx5_ib_pd *mpd = to_mpd(pd);
1709
9603b61d 1710 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1711 kfree(mpd);
1712
1713 return 0;
1714}
1715
466fa6d2
MG		 1716enum {
1717 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1718 MATCH_CRITERIA_ENABLE_MISC_BIT,
1719 MATCH_CRITERIA_ENABLE_INNER_BIT
1720};
1721
1722#define HEADER_IS_ZERO(match_criteria, headers) \
1723 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1724 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1725
466fa6d2 1726static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1727{
466fa6d2 1728 u8 match_criteria_enable;
038d2ef8 1729
466fa6d2
MG		 1730 match_criteria_enable =
1731 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1732 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1733 match_criteria_enable |=
1734 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1735 MATCH_CRITERIA_ENABLE_MISC_BIT;
1736 match_criteria_enable |=
1737 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1738 MATCH_CRITERIA_ENABLE_INNER_BIT;
1739
1740 return match_criteria_enable;
038d2ef8
MG		 1741}
1742
ca0d4753
MG		 1743static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1744{
1745 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1746 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1747}
1748
2d1e697e
MR		 1749static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1750 bool inner)
1751{
1752 if (inner) {
1753 MLX5_SET(fte_match_set_misc,
1754 misc_c, inner_ipv6_flow_label, mask);
1755 MLX5_SET(fte_match_set_misc,
1756 misc_v, inner_ipv6_flow_label, val);
1757 } else {
1758 MLX5_SET(fte_match_set_misc,
1759 misc_c, outer_ipv6_flow_label, mask);
1760 MLX5_SET(fte_match_set_misc,
1761 misc_v, outer_ipv6_flow_label, val);
1762 }
1763}
1764
ca0d4753
MG		 1765static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1766{
1767 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1768 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1769 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1770 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1771}
1772
c47ac6ae
MG		 1773#define LAST_ETH_FIELD vlan_tag
1774#define LAST_IB_FIELD sl
ca0d4753 1775#define LAST_IPV4_FIELD tos
466fa6d2 1776#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1777#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1778#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1779#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1780#define LAST_DROP_FIELD size
c47ac6ae
MG		 1781
1782/* Field is the last supported field */
1783#define FIELDS_NOT_SUPPORTED(filter, field)\
1784 memchr_inv((void *)&filter.field +\
1785 sizeof(filter.field), 0,\
1786 sizeof(filter) -\
1787 offsetof(typeof(filter), field) -\
1788 sizeof(filter.field))
1789
19cc7524
AL		 1790#define IPV4_VERSION 4
1791#define IPV6_VERSION 6
1792static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1793 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1794 u32 *tag_id, bool *is_drop)
038d2ef8 1795{
466fa6d2
MG		 1796 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1797 misc_parameters);
1798 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1799 misc_parameters);
2d1e697e
MR		 1800 void *headers_c;
1801 void *headers_v;
19cc7524 1802 int match_ipv;
2d1e697e
MR		 1803
1804 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1805 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1806 inner_headers);
1807 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1808 inner_headers);
19cc7524
AL		 1809 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1810 ft_field_support.inner_ip_version);
2d1e697e
MR		 1811 } else {
1812 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1813 outer_headers);
1814 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1815 outer_headers);
19cc7524
AL		 1816 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1817 ft_field_support.outer_ip_version);
2d1e697e 1818 }
466fa6d2 1819
2d1e697e 1820 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1821 case IB_FLOW_SPEC_ETH:
c47ac6ae 1822 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1823 return -EOPNOTSUPP;
038d2ef8 1824
2d1e697e 1825 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1826 dmac_47_16),
1827 ib_spec->eth.mask.dst_mac);
2d1e697e 1828 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1829 dmac_47_16),
1830 ib_spec->eth.val.dst_mac);
1831
2d1e697e 1832 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1833 smac_47_16),
1834 ib_spec->eth.mask.src_mac);
2d1e697e 1835 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1836 smac_47_16),
1837 ib_spec->eth.val.src_mac);
1838
038d2ef8 1839 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1840 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1841 cvlan_tag, 1);
2d1e697e 1842 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1843 cvlan_tag, 1);
038d2ef8 1844
2d1e697e 1845 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1846 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1847 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1848 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1849
2d1e697e 1850 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1851 first_cfi,
1852 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1853 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1854 first_cfi,
1855 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1856
2d1e697e 1857 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1858 first_prio,
1859 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1860 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1861 first_prio,
1862 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1863 }
2d1e697e 1864 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1865 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1866 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1867 ethertype, ntohs(ib_spec->eth.val.ether_type));
1868 break;
1869 case IB_FLOW_SPEC_IPV4:
c47ac6ae 1870 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 1871 return -EOPNOTSUPP;
038d2ef8 1872
19cc7524
AL		 1873 if (match_ipv) {
1874 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1875 ip_version, 0xf);
1876 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1877 ip_version, IPV4_VERSION);
1878 } else {
1879 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1880 ethertype, 0xffff);
1881 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1882 ethertype, ETH_P_IP);
1883 }
038d2ef8 1884
2d1e697e 1885 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1886 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1887 &ib_spec->ipv4.mask.src_ip,
1888 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 1889 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1890 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1891 &ib_spec->ipv4.val.src_ip,
1892 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 1893 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1894 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1895 &ib_spec->ipv4.mask.dst_ip,
1896 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 1897 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1898 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1899 &ib_spec->ipv4.val.dst_ip,
1900 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 1901
2d1e697e 1902 set_tos(headers_c, headers_v,
ca0d4753
MG		 1903 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1904
2d1e697e 1905 set_proto(headers_c, headers_v,
ca0d4753 1906 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 1907 break;
026bae0c 1908 case IB_FLOW_SPEC_IPV6:
c47ac6ae 1909 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 1910 return -EOPNOTSUPP;
026bae0c 1911
19cc7524
AL		 1912 if (match_ipv) {
1913 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1914 ip_version, 0xf);
1915 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1916 ip_version, IPV6_VERSION);
1917 } else {
1918 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1919 ethertype, 0xffff);
1920 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1921 ethertype, ETH_P_IPV6);
1922 }
026bae0c 1923
2d1e697e 1924 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1925 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1926 &ib_spec->ipv6.mask.src_ip,
1927 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 1928 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1929 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1930 &ib_spec->ipv6.val.src_ip,
1931 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 1932 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1933 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1934 &ib_spec->ipv6.mask.dst_ip,
1935 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 1936 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1937 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1938 &ib_spec->ipv6.val.dst_ip,
1939 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 1940
2d1e697e 1941 set_tos(headers_c, headers_v,
466fa6d2
MG		 1942 ib_spec->ipv6.mask.traffic_class,
1943 ib_spec->ipv6.val.traffic_class);
1944
2d1e697e 1945 set_proto(headers_c, headers_v,
466fa6d2
MG		 1946 ib_spec->ipv6.mask.next_hdr,
1947 ib_spec->ipv6.val.next_hdr);
1948
2d1e697e
MR		 1949 set_flow_label(misc_params_c, misc_params_v,
1950 ntohl(ib_spec->ipv6.mask.flow_label),
1951 ntohl(ib_spec->ipv6.val.flow_label),
1952 ib_spec->type & IB_FLOW_SPEC_INNER);
1953
026bae0c 1954 break;
038d2ef8 1955 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 1956 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1957 LAST_TCP_UDP_FIELD))
1ffd3a26 1958 return -EOPNOTSUPP;
038d2ef8 1959
2d1e697e 1960 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1961 0xff);
2d1e697e 1962 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1963 IPPROTO_TCP);
1964
2d1e697e 1965 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 1966 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1967 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 1968 ntohs(ib_spec->tcp_udp.val.src_port));
1969
2d1e697e 1970 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 1971 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1972 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 1973 ntohs(ib_spec->tcp_udp.val.dst_port));
1974 break;
1975 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 1976 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1977 LAST_TCP_UDP_FIELD))
1ffd3a26 1978 return -EOPNOTSUPP;
038d2ef8 1979
2d1e697e 1980 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1981 0xff);
2d1e697e 1982 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1983 IPPROTO_UDP);
1984
2d1e697e 1985 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 1986 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1987 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 1988 ntohs(ib_spec->tcp_udp.val.src_port));
1989
2d1e697e 1990 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 1991 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1992 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 1993 ntohs(ib_spec->tcp_udp.val.dst_port));
1994 break;
ffb30d8f
MR		 1995 case IB_FLOW_SPEC_VXLAN_TUNNEL:
1996 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1997 LAST_TUNNEL_FIELD))
1ffd3a26 1998 return -EOPNOTSUPP;
ffb30d8f
MR		 1999
2000 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2001 ntohl(ib_spec->tunnel.mask.tunnel_id));
2002 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2003 ntohl(ib_spec->tunnel.val.tunnel_id));
2004 break;
2ac693f9
MR		 2005 case IB_FLOW_SPEC_ACTION_TAG:
2006 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2007 LAST_FLOW_TAG_FIELD))
2008 return -EOPNOTSUPP;
2009 if (ib_spec->flow_tag.tag_id >= BIT(24))
2010 return -EINVAL;
2011
2012 *tag_id = ib_spec->flow_tag.tag_id;
2013 break;
a22ed86c
SS		 2014 case IB_FLOW_SPEC_ACTION_DROP:
2015 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2016 LAST_DROP_FIELD))
2017 return -EOPNOTSUPP;
2018 *is_drop = true;
2019 break;
038d2ef8
MG		 2020 default:
2021 return -EINVAL;
2022 }
2023
2024 return 0;
2025}
2026
2027/* If a flow could catch both multicast and unicast packets,
2028 * it won't fall into the multicast flow steering table and this rule
2029 * could steal other multicast packets.
2030 */
2031static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2032{
2033 struct ib_flow_spec_eth *eth_spec;
2034
2035 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2036 ib_attr->size < sizeof(struct ib_flow_attr) +
2037 sizeof(struct ib_flow_spec_eth) ||
2038 ib_attr->num_of_specs < 1)
2039 return false;
2040
2041 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2042 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2043 eth_spec->size != sizeof(*eth_spec))
2044 return false;
2045
2046 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2047 is_multicast_ether_addr(eth_spec->val.dst_mac);
2048}
2049
19cc7524
AL		 2050static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2051 const struct ib_flow_attr *flow_attr,
0f750966 2052 bool check_inner)
038d2ef8
MG		 2053{
2054 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2055 int match_ipv = check_inner ?
2056 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2057 ft_field_support.inner_ip_version) :
2058 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2059 ft_field_support.outer_ip_version);
0f750966
AL		 2060 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2061 bool ipv4_spec_valid, ipv6_spec_valid;
2062 unsigned int ip_spec_type = 0;
2063 bool has_ethertype = false;
038d2ef8 2064 unsigned int spec_index;
0f750966
AL		 2065 bool mask_valid = true;
2066 u16 eth_type = 0;
2067 bool type_valid;
038d2ef8
MG		 2068
2069 /* Validate that ethertype is correct */
2070 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2071 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2072 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2073 mask_valid = (ib_spec->eth.mask.ether_type ==
2074 htons(0xffff));
2075 has_ethertype = true;
2076 eth_type = ntohs(ib_spec->eth.val.ether_type);
2077 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2078 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2079 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2080 }
2081 ib_spec = (void *)ib_spec + ib_spec->size;
2082 }
0f750966
AL		 2083
2084 type_valid = (!has_ethertype) || (!ip_spec_type);
2085 if (!type_valid && mask_valid) {
2086 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2087 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2088 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2089 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2090
2091 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2092 (((eth_type == ETH_P_MPLS_UC) ||
2093 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2094 }
2095
2096 return type_valid;
2097}
2098
19cc7524
AL		 2099static bool is_valid_attr(struct mlx5_core_dev *mdev,
2100 const struct ib_flow_attr *flow_attr)
0f750966 2101{
19cc7524
AL		 2102 return is_valid_ethertype(mdev, flow_attr, false) &&
2103 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2104}
2105
2106static void put_flow_table(struct mlx5_ib_dev *dev,
2107 struct mlx5_ib_flow_prio *prio, bool ft_added)
2108{
2109 prio->refcount -= !!ft_added;
2110 if (!prio->refcount) {
2111 mlx5_destroy_flow_table(prio->flow_table);
2112 prio->flow_table = NULL;
2113 }
2114}
2115
2116static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2117{
2118 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2119 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2120 struct mlx5_ib_flow_handler,
2121 ibflow);
2122 struct mlx5_ib_flow_handler *iter, *tmp;
2123
2124 mutex_lock(&dev->flow_db.lock);
2125
2126 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2127 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2128 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2129 list_del(&iter->list);
2130 kfree(iter);
2131 }
2132
74491de9 2133 mlx5_del_flow_rules(handler->rule);
5497adc6 2134 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2135 mutex_unlock(&dev->flow_db.lock);
2136
2137 kfree(handler);
2138
2139 return 0;
2140}
2141
35d19011
MG		 2142static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2143{
2144 priority *= 2;
2145 if (!dont_trap)
2146 priority++;
2147 return priority;
2148}
2149
cc0e5d42
MG		 2150enum flow_table_type {
2151 MLX5_IB_FT_RX,
2152 MLX5_IB_FT_TX
2153};
2154
00b7c2ab
MG		 2155#define MLX5_FS_MAX_TYPES 6
2156#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2157static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2158 struct ib_flow_attr *flow_attr,
2159 enum flow_table_type ft_type)
038d2ef8 2160{
35d19011 2161 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2162 struct mlx5_flow_namespace *ns = NULL;
2163 struct mlx5_ib_flow_prio *prio;
2164 struct mlx5_flow_table *ft;
dac388ef 2165 int max_table_size;
038d2ef8
MG		 2166 int num_entries;
2167 int num_groups;
2168 int priority;
2169 int err = 0;
2170
dac388ef
MG		 2171 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2172 log_max_ft_size));
038d2ef8 2173 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2174 if (flow_is_multicast_only(flow_attr) &&
2175 !dont_trap)
038d2ef8
MG		 2176 priority = MLX5_IB_FLOW_MCAST_PRIO;
2177 else
35d19011
MG		 2178 priority = ib_prio_to_core_prio(flow_attr->priority,
2179 dont_trap);
038d2ef8
MG		 2180 ns = mlx5_get_flow_namespace(dev->mdev,
2181 MLX5_FLOW_NAMESPACE_BYPASS);
2182 num_entries = MLX5_FS_MAX_ENTRIES;
2183 num_groups = MLX5_FS_MAX_TYPES;
2184 prio = &dev->flow_db.prios[priority];
2185 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2186 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2187 ns = mlx5_get_flow_namespace(dev->mdev,
2188 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2189 build_leftovers_ft_param(&priority,
2190 &num_entries,
2191 &num_groups);
2192 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2193 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2194 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2195 allow_sniffer_and_nic_rx_shared_tir))
2196 return ERR_PTR(-ENOTSUPP);
2197
2198 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2199 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2200 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2201
2202 prio = &dev->flow_db.sniffer[ft_type];
2203 priority = 0;
2204 num_entries = 1;
2205 num_groups = 1;
038d2ef8
MG		 2206 }
2207
2208 if (!ns)
2209 return ERR_PTR(-ENOTSUPP);
2210
dac388ef
MG		 2211 if (num_entries > max_table_size)
2212 return ERR_PTR(-ENOMEM);
2213
038d2ef8
MG		 2214 ft = prio->flow_table;
2215 if (!ft) {
2216 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2217 num_entries,
d63cd286 2218 num_groups,
c9f1b073 2219 0, 0);
038d2ef8
MG		 2220
2221 if (!IS_ERR(ft)) {
2222 prio->refcount = 0;
2223 prio->flow_table = ft;
2224 } else {
2225 err = PTR_ERR(ft);
2226 }
2227 }
2228
2229 return err ? ERR_PTR(err) : prio;
2230}
2231
2232static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2233 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 2234 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 2235 struct mlx5_flow_destination *dst)
2236{
2237 struct mlx5_flow_table *ft = ft_prio->flow_table;
2238 struct mlx5_ib_flow_handler *handler;
66958ed9 2239 struct mlx5_flow_act flow_act = {0};
c5bb1730 2240 struct mlx5_flow_spec *spec;
a22ed86c 2241 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2242 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2243 unsigned int spec_index;
2ac693f9 2244 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2245 bool is_drop = false;
038d2ef8 2246 int err = 0;
a22ed86c 2247 int dest_num = 1;
038d2ef8 2248
19cc7524 2249 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2250 return ERR_PTR(-EINVAL);
2251
1b9a07ee 2252 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2253 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2254 if (!handler || !spec) {
038d2ef8
MG		 2255 err = -ENOMEM;
2256 goto free;
2257 }
2258
2259 INIT_LIST_HEAD(&handler->list);
2260
2261 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2262 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2263 spec->match_value,
2264 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2265 if (err < 0)
2266 goto free;
2267
2268 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2269 }
2270
466fa6d2 2271 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2272 if (is_drop) {
2273 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2274 rule_dst = NULL;
2275 dest_num = 0;
2276 } else {
2277 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2278 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2279 }
2ac693f9
MR		 2280
2281 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2282 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2283 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2284 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2285 flow_tag, flow_attr->type);
2286 err = -EINVAL;
2287 goto free;
2288 }
2289 flow_act.flow_tag = flow_tag;
74491de9 2290 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2291 &flow_act,
a22ed86c 2292 rule_dst, dest_num);
038d2ef8
MG		 2293
2294 if (IS_ERR(handler->rule)) {
2295 err = PTR_ERR(handler->rule);
2296 goto free;
2297 }
2298
d9d4980a 2299 ft_prio->refcount++;
5497adc6 2300 handler->prio = ft_prio;
038d2ef8
MG		 2301
2302 ft_prio->flow_table = ft;
2303free:
2304 if (err)
2305 kfree(handler);
c5bb1730 2306 kvfree(spec);
038d2ef8
MG		 2307 return err ? ERR_PTR(err) : handler;
2308}
2309
35d19011
MG		 2310static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2311 struct mlx5_ib_flow_prio *ft_prio,
2312 struct ib_flow_attr *flow_attr,
2313 struct mlx5_flow_destination *dst)
2314{
2315 struct mlx5_ib_flow_handler *handler_dst = NULL;
2316 struct mlx5_ib_flow_handler *handler = NULL;
2317
2318 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2319 if (!IS_ERR(handler)) {
2320 handler_dst = create_flow_rule(dev, ft_prio,
2321 flow_attr, dst);
2322 if (IS_ERR(handler_dst)) {
74491de9 2323 mlx5_del_flow_rules(handler->rule);
d9d4980a 2324 ft_prio->refcount--;
35d19011
MG		 2325 kfree(handler);
2326 handler = handler_dst;
2327 } else {
2328 list_add(&handler_dst->list, &handler->list);
2329 }
2330 }
2331
2332 return handler;
2333}
038d2ef8
MG		 2334enum {
2335 LEFTOVERS_MC,
2336 LEFTOVERS_UC,
2337};
2338
2339static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2340 struct mlx5_ib_flow_prio *ft_prio,
2341 struct ib_flow_attr *flow_attr,
2342 struct mlx5_flow_destination *dst)
2343{
2344 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2345 struct mlx5_ib_flow_handler *handler = NULL;
2346
2347 static struct {
2348 struct ib_flow_attr flow_attr;
2349 struct ib_flow_spec_eth eth_flow;
2350 } leftovers_specs[] = {
2351 [LEFTOVERS_MC] = {
2352 .flow_attr = {
2353 .num_of_specs = 1,
2354 .size = sizeof(leftovers_specs[0])
2355 },
2356 .eth_flow = {
2357 .type = IB_FLOW_SPEC_ETH,
2358 .size = sizeof(struct ib_flow_spec_eth),
2359 .mask = {.dst_mac = {0x1} },
2360 .val = {.dst_mac = {0x1} }
2361 }
2362 },
2363 [LEFTOVERS_UC] = {
2364 .flow_attr = {
2365 .num_of_specs = 1,
2366 .size = sizeof(leftovers_specs[0])
2367 },
2368 .eth_flow = {
2369 .type = IB_FLOW_SPEC_ETH,
2370 .size = sizeof(struct ib_flow_spec_eth),
2371 .mask = {.dst_mac = {0x1} },
2372 .val = {.dst_mac = {} }
2373 }
2374 }
2375 };
2376
2377 handler = create_flow_rule(dev, ft_prio,
2378 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2379 dst);
2380 if (!IS_ERR(handler) &&
2381 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2382 handler_ucast = create_flow_rule(dev, ft_prio,
2383 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2384 dst);
2385 if (IS_ERR(handler_ucast)) {
74491de9 2386 mlx5_del_flow_rules(handler->rule);
d9d4980a 2387 ft_prio->refcount--;
038d2ef8
MG		 2388 kfree(handler);
2389 handler = handler_ucast;
2390 } else {
2391 list_add(&handler_ucast->list, &handler->list);
2392 }
2393 }
2394
2395 return handler;
2396}
2397
cc0e5d42
MG		 2398static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2399 struct mlx5_ib_flow_prio *ft_rx,
2400 struct mlx5_ib_flow_prio *ft_tx,
2401 struct mlx5_flow_destination *dst)
2402{
2403 struct mlx5_ib_flow_handler *handler_rx;
2404 struct mlx5_ib_flow_handler *handler_tx;
2405 int err;
2406 static const struct ib_flow_attr flow_attr = {
2407 .num_of_specs = 0,
2408 .size = sizeof(flow_attr)
2409 };
2410
2411 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2412 if (IS_ERR(handler_rx)) {
2413 err = PTR_ERR(handler_rx);
2414 goto err;
2415 }
2416
2417 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2418 if (IS_ERR(handler_tx)) {
2419 err = PTR_ERR(handler_tx);
2420 goto err_tx;
2421 }
2422
2423 list_add(&handler_tx->list, &handler_rx->list);
2424
2425 return handler_rx;
2426
2427err_tx:
74491de9 2428 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2429 ft_rx->refcount--;
2430 kfree(handler_rx);
2431err:
2432 return ERR_PTR(err);
2433}
2434
038d2ef8
MG		 2435static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2436 struct ib_flow_attr *flow_attr,
2437 int domain)
2438{
2439 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2440 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2441 struct mlx5_ib_flow_handler *handler = NULL;
2442 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2443 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2444 struct mlx5_ib_flow_prio *ft_prio;
2445 int err;
2446
2447 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2448 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2449
2450 if (domain != IB_FLOW_DOMAIN_USER ||
2451 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2452 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2453 return ERR_PTR(-EINVAL);
2454
2455 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2456 if (!dst)
2457 return ERR_PTR(-ENOMEM);
2458
2459 mutex_lock(&dev->flow_db.lock);
2460
cc0e5d42 2461 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2462 if (IS_ERR(ft_prio)) {
2463 err = PTR_ERR(ft_prio);
2464 goto unlock;
2465 }
cc0e5d42
MG		 2466 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2467 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2468 if (IS_ERR(ft_prio_tx)) {
2469 err = PTR_ERR(ft_prio_tx);
2470 ft_prio_tx = NULL;
2471 goto destroy_ft;
2472 }
2473 }
038d2ef8
MG		 2474
2475 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2476 if (mqp->flags & MLX5_IB_QP_RSS)
2477 dst->tir_num = mqp->rss_qp.tirn;
2478 else
2479 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2480
2481 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2482 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2483 handler = create_dont_trap_rule(dev, ft_prio,
2484 flow_attr, dst);
2485 } else {
2486 handler = create_flow_rule(dev, ft_prio, flow_attr,
2487 dst);
2488 }
038d2ef8
MG		 2489 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2490 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2491 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2492 dst);
cc0e5d42
MG		 2493 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2494 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2495 } else {
2496 err = -EINVAL;
2497 goto destroy_ft;
2498 }
2499
2500 if (IS_ERR(handler)) {
2501 err = PTR_ERR(handler);
2502 handler = NULL;
2503 goto destroy_ft;
2504 }
2505
038d2ef8
MG		 2506 mutex_unlock(&dev->flow_db.lock);
2507 kfree(dst);
2508
2509 return &handler->ibflow;
2510
2511destroy_ft:
2512 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2513 if (ft_prio_tx)
2514 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2515unlock:
2516 mutex_unlock(&dev->flow_db.lock);
2517 kfree(dst);
2518 kfree(handler);
2519 return ERR_PTR(err);
2520}
2521
e126ba97
EC		 2522static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2523{
2524 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2525 int err;
2526
9603b61d 2527 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2528 if (err)
2529 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2530 ibqp->qp_num, gid->raw);
2531
2532 return err;
2533}
2534
2535static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2536{
2537 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2538 int err;
2539
9603b61d 2540 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2541 if (err)
2542 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2543 ibqp->qp_num, gid->raw);
2544
2545 return err;
2546}
2547
2548static int init_node_data(struct mlx5_ib_dev *dev)
2549{
1b5daf11 2550 int err;
e126ba97 2551
1b5daf11 2552 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2553 if (err)
1b5daf11 2554 return err;
e126ba97 2555
1b5daf11 2556 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2557
1b5daf11 2558 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2559}
2560
2561static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2562 char *buf)
2563{
2564 struct mlx5_ib_dev *dev =
2565 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2566
9603b61d 2567 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2568}
2569
2570static ssize_t show_reg_pages(struct device *device,
2571 struct device_attribute *attr, char *buf)
2572{
2573 struct mlx5_ib_dev *dev =
2574 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2575
6aec21f6 2576 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2577}
2578
2579static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2580 char *buf)
2581{
2582 struct mlx5_ib_dev *dev =
2583 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2584 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2585}
2586
e126ba97
EC		 2587static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2588 char *buf)
2589{
2590 struct mlx5_ib_dev *dev =
2591 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2592 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2593}
2594
2595static ssize_t show_board(struct device *device, struct device_attribute *attr,
2596 char *buf)
2597{
2598 struct mlx5_ib_dev *dev =
2599 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2600 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2601 dev->mdev->board_id);
e126ba97
EC		 2602}
2603
2604static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2605static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2606static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2607static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2608static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2609
2610static struct device_attribute *mlx5_class_attributes[] = {
2611 &dev_attr_hw_rev,
e126ba97
EC		 2612 &dev_attr_hca_type,
2613 &dev_attr_board_id,
2614 &dev_attr_fw_pages,
2615 &dev_attr_reg_pages,
2616};
2617
7722f47e
HE		 2618static void pkey_change_handler(struct work_struct *work)
2619{
2620 struct mlx5_ib_port_resources *ports =
2621 container_of(work, struct mlx5_ib_port_resources,
2622 pkey_change_work);
2623
2624 mutex_lock(&ports->devr->mutex);
2625 mlx5_ib_gsi_pkey_change(ports->gsi);
2626 mutex_unlock(&ports->devr->mutex);
2627}
2628
89ea94a7
MG		 2629static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2630{
2631 struct mlx5_ib_qp *mqp;
2632 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2633 struct mlx5_core_cq *mcq;
2634 struct list_head cq_armed_list;
2635 unsigned long flags_qp;
2636 unsigned long flags_cq;
2637 unsigned long flags;
2638
2639 INIT_LIST_HEAD(&cq_armed_list);
2640
2641 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2642 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2643 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2644 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2645 if (mqp->sq.tail != mqp->sq.head) {
2646 send_mcq = to_mcq(mqp->ibqp.send_cq);
2647 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2648 if (send_mcq->mcq.comp &&
2649 mqp->ibqp.send_cq->comp_handler) {
2650 if (!send_mcq->mcq.reset_notify_added) {
2651 send_mcq->mcq.reset_notify_added = 1;
2652 list_add_tail(&send_mcq->mcq.reset_notify,
2653 &cq_armed_list);
2654 }
2655 }
2656 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2657 }
2658 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2659 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2660 /* no handling is needed for SRQ */
2661 if (!mqp->ibqp.srq) {
2662 if (mqp->rq.tail != mqp->rq.head) {
2663 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2664 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2665 if (recv_mcq->mcq.comp &&
2666 mqp->ibqp.recv_cq->comp_handler) {
2667 if (!recv_mcq->mcq.reset_notify_added) {
2668 recv_mcq->mcq.reset_notify_added = 1;
2669 list_add_tail(&recv_mcq->mcq.reset_notify,
2670 &cq_armed_list);
2671 }
2672 }
2673 spin_unlock_irqrestore(&recv_mcq->lock,
2674 flags_cq);
2675 }
2676 }
2677 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2678 }
2679 /*At that point all inflight post send were put to be executed as of we
2680 * lock/unlock above locks Now need to arm all involved CQs.
2681 */
2682 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2683 mcq->comp(mcq);
2684 }
2685 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2686}
2687
9603b61d 2688static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2689 enum mlx5_dev_event event, unsigned long param)
e126ba97 2690{
9603b61d 2691 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2692 struct ib_event ibev;
dbaaff2a 2693 bool fatal = false;
e126ba97
EC		 2694 u8 port = 0;
2695
2696 switch (event) {
2697 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2698 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2699 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2700 fatal = true;
e126ba97
EC		 2701 break;
2702
2703 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2704 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2705 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2706 port = (u8)param;
5ec8c83e
AH		 2707
2708 /* In RoCE, port up/down events are handled in
2709 * mlx5_netdev_event().
2710 */
2711 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2712 IB_LINK_LAYER_ETHERNET)
2713 return;
2714
2715 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2716 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2717 break;
2718
e126ba97
EC		 2719 case MLX5_DEV_EVENT_LID_CHANGE:
2720 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2721 port = (u8)param;
e126ba97
EC		 2722 break;
2723
2724 case MLX5_DEV_EVENT_PKEY_CHANGE:
2725 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2726 port = (u8)param;
7722f47e
HE		 2727
2728 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2729 break;
2730
2731 case MLX5_DEV_EVENT_GUID_CHANGE:
2732 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2733 port = (u8)param;
e126ba97
EC		 2734 break;
2735
2736 case MLX5_DEV_EVENT_CLIENT_REREG:
2737 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2738 port = (u8)param;
e126ba97 2739 break;
bdc37924
SM		 2740 default:
2741 return;
e126ba97
EC		 2742 }
2743
2744 ibev.device = &ibdev->ib_dev;
2745 ibev.element.port_num = port;
2746
a0c84c32
EC		 2747 if (port < 1 || port > ibdev->num_ports) {
2748 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2749 return;
2750 }
2751
e126ba97
EC		 2752 if (ibdev->ib_active)
2753 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2754
2755 if (fatal)
2756 ibdev->ib_active = false;
e126ba97
EC		 2757}
2758
c43f1112
MG		 2759static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2760{
2761 struct mlx5_hca_vport_context vport_ctx;
2762 int err;
2763 int port;
2764
2765 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2766 dev->mdev->port_caps[port - 1].has_smi = false;
2767 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2768 MLX5_CAP_PORT_TYPE_IB) {
2769 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2770 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2771 port, 0,
2772 &vport_ctx);
2773 if (err) {
2774 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2775 port, err);
2776 return err;
2777 }
2778 dev->mdev->port_caps[port - 1].has_smi =
2779 vport_ctx.has_smi;
2780 } else {
2781 dev->mdev->port_caps[port - 1].has_smi = true;
2782 }
2783 }
2784 }
2785 return 0;
2786}
2787
e126ba97
EC		 2788static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2789{
2790 int port;
2791
938fe83c 2792 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2793 mlx5_query_ext_port_caps(dev, port);
2794}
2795
2796static int get_port_caps(struct mlx5_ib_dev *dev)
2797{
2798 struct ib_device_attr *dprops = NULL;
2799 struct ib_port_attr *pprops = NULL;
f614fc15 2800 int err = -ENOMEM;
e126ba97 2801 int port;
2528e33e 2802 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2803
2804 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2805 if (!pprops)
2806 goto out;
2807
2808 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2809 if (!dprops)
2810 goto out;
2811
c43f1112
MG		 2812 err = set_has_smi_cap(dev);
2813 if (err)
2814 goto out;
2815
2528e33e 2816 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2817 if (err) {
2818 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2819 goto out;
2820 }
2821
938fe83c 2822 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 2823 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 2824 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2825 if (err) {
938fe83c
SM		 2826 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2827 port, err);
e126ba97
EC		 2828 break;
2829 }
938fe83c
SM		 2830 dev->mdev->port_caps[port - 1].pkey_table_len =
2831 dprops->max_pkeys;
2832 dev->mdev->port_caps[port - 1].gid_table_len =
2833 pprops->gid_tbl_len;
e126ba97
EC		 2834 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2835 dprops->max_pkeys, pprops->gid_tbl_len);
2836 }
2837
2838out:
2839 kfree(pprops);
2840 kfree(dprops);
2841
2842 return err;
2843}
2844
2845static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2846{
2847 int err;
2848
2849 err = mlx5_mr_cache_cleanup(dev);
2850 if (err)
2851 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2852
2853 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2854 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2855 ib_dealloc_pd(dev->umrc.pd);
2856}
2857
2858enum {
2859 MAX_UMR_WR = 128,
2860};
2861
2862static int create_umr_res(struct mlx5_ib_dev *dev)
2863{
2864 struct ib_qp_init_attr *init_attr = NULL;
2865 struct ib_qp_attr *attr = NULL;
2866 struct ib_pd *pd;
2867 struct ib_cq *cq;
2868 struct ib_qp *qp;
e126ba97
EC		 2869 int ret;
2870
2871 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2872 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2873 if (!attr || !init_attr) {
2874 ret = -ENOMEM;
2875 goto error_0;
2876 }
2877
ed082d36 2878 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2879 if (IS_ERR(pd)) {
2880 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2881 ret = PTR_ERR(pd);
2882 goto error_0;
2883 }
2884
add08d76 2885 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2886 if (IS_ERR(cq)) {
2887 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2888 ret = PTR_ERR(cq);
2889 goto error_2;
2890 }
e126ba97
EC		 2891
2892 init_attr->send_cq = cq;
2893 init_attr->recv_cq = cq;
2894 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2895 init_attr->cap.max_send_wr = MAX_UMR_WR;
2896 init_attr->cap.max_send_sge = 1;
2897 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2898 init_attr->port_num = 1;
2899 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2900 if (IS_ERR(qp)) {
2901 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2902 ret = PTR_ERR(qp);
2903 goto error_3;
2904 }
2905 qp->device = &dev->ib_dev;
2906 qp->real_qp = qp;
2907 qp->uobject = NULL;
2908 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2909
2910 attr->qp_state = IB_QPS_INIT;
2911 attr->port_num = 1;
2912 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2913 IB_QP_PORT, NULL);
2914 if (ret) {
2915 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2916 goto error_4;
2917 }
2918
2919 memset(attr, 0, sizeof(*attr));
2920 attr->qp_state = IB_QPS_RTR;
2921 attr->path_mtu = IB_MTU_256;
2922
2923 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2924 if (ret) {
2925 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2926 goto error_4;
2927 }
2928
2929 memset(attr, 0, sizeof(*attr));
2930 attr->qp_state = IB_QPS_RTS;
2931 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2932 if (ret) {
2933 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2934 goto error_4;
2935 }
2936
2937 dev->umrc.qp = qp;
2938 dev->umrc.cq = cq;
e126ba97
EC		 2939 dev->umrc.pd = pd;
2940
2941 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2942 ret = mlx5_mr_cache_init(dev);
2943 if (ret) {
2944 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2945 goto error_4;
2946 }
2947
2948 kfree(attr);
2949 kfree(init_attr);
2950
2951 return 0;
2952
2953error_4:
2954 mlx5_ib_destroy_qp(qp);
2955
2956error_3:
add08d76 2957 ib_free_cq(cq);
e126ba97
EC		 2958
2959error_2:
e126ba97
EC		 2960 ib_dealloc_pd(pd);
2961
2962error_0:
2963 kfree(attr);
2964 kfree(init_attr);
2965 return ret;
2966}
2967
6e8484c5
MG		 2968static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2969{
2970 switch (umr_fence_cap) {
2971 case MLX5_CAP_UMR_FENCE_NONE:
2972 return MLX5_FENCE_MODE_NONE;
2973 case MLX5_CAP_UMR_FENCE_SMALL:
2974 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2975 default:
2976 return MLX5_FENCE_MODE_STRONG_ORDERING;
2977 }
2978}
2979
e126ba97
EC		 2980static int create_dev_resources(struct mlx5_ib_resources *devr)
2981{
2982 struct ib_srq_init_attr attr;
2983 struct mlx5_ib_dev *dev;
bcf4c1ea 2984 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2985 int port;
e126ba97
EC		 2986 int ret = 0;
2987
2988 dev = container_of(devr, struct mlx5_ib_dev, devr);
2989
d16e91da
HE		 2990 mutex_init(&devr->mutex);
2991
e126ba97
EC		 2992 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2993 if (IS_ERR(devr->p0)) {
2994 ret = PTR_ERR(devr->p0);
2995 goto error0;
2996 }
2997 devr->p0->device = &dev->ib_dev;
2998 devr->p0->uobject = NULL;
2999 atomic_set(&devr->p0->usecnt, 0);
3000
bcf4c1ea 3001 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3002 if (IS_ERR(devr->c0)) {
3003 ret = PTR_ERR(devr->c0);
3004 goto error1;
3005 }
3006 devr->c0->device = &dev->ib_dev;
3007 devr->c0->uobject = NULL;
3008 devr->c0->comp_handler = NULL;
3009 devr->c0->event_handler = NULL;
3010 devr->c0->cq_context = NULL;
3011 atomic_set(&devr->c0->usecnt, 0);
3012
3013 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3014 if (IS_ERR(devr->x0)) {
3015 ret = PTR_ERR(devr->x0);
3016 goto error2;
3017 }
3018 devr->x0->device = &dev->ib_dev;
3019 devr->x0->inode = NULL;
3020 atomic_set(&devr->x0->usecnt, 0);
3021 mutex_init(&devr->x0->tgt_qp_mutex);
3022 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3023
3024 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3025 if (IS_ERR(devr->x1)) {
3026 ret = PTR_ERR(devr->x1);
3027 goto error3;
3028 }
3029 devr->x1->device = &dev->ib_dev;
3030 devr->x1->inode = NULL;
3031 atomic_set(&devr->x1->usecnt, 0);
3032 mutex_init(&devr->x1->tgt_qp_mutex);
3033 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3034
3035 memset(&attr, 0, sizeof(attr));
3036 attr.attr.max_sge = 1;
3037 attr.attr.max_wr = 1;
3038 attr.srq_type = IB_SRQT_XRC;
3039 attr.ext.xrc.cq = devr->c0;
3040 attr.ext.xrc.xrcd = devr->x0;
3041
3042 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3043 if (IS_ERR(devr->s0)) {
3044 ret = PTR_ERR(devr->s0);
3045 goto error4;
3046 }
3047 devr->s0->device = &dev->ib_dev;
3048 devr->s0->pd = devr->p0;
3049 devr->s0->uobject = NULL;
3050 devr->s0->event_handler = NULL;
3051 devr->s0->srq_context = NULL;
3052 devr->s0->srq_type = IB_SRQT_XRC;
3053 devr->s0->ext.xrc.xrcd = devr->x0;
3054 devr->s0->ext.xrc.cq = devr->c0;
3055 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3056 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3057 atomic_inc(&devr->p0->usecnt);
3058 atomic_set(&devr->s0->usecnt, 0);
3059
4aa17b28
HA		 3060 memset(&attr, 0, sizeof(attr));
3061 attr.attr.max_sge = 1;
3062 attr.attr.max_wr = 1;
3063 attr.srq_type = IB_SRQT_BASIC;
3064 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3065 if (IS_ERR(devr->s1)) {
3066 ret = PTR_ERR(devr->s1);
3067 goto error5;
3068 }
3069 devr->s1->device = &dev->ib_dev;
3070 devr->s1->pd = devr->p0;
3071 devr->s1->uobject = NULL;
3072 devr->s1->event_handler = NULL;
3073 devr->s1->srq_context = NULL;
3074 devr->s1->srq_type = IB_SRQT_BASIC;
3075 devr->s1->ext.xrc.cq = devr->c0;
3076 atomic_inc(&devr->p0->usecnt);
3077 atomic_set(&devr->s0->usecnt, 0);
3078
7722f47e
HE		 3079 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3080 INIT_WORK(&devr->ports[port].pkey_change_work,
3081 pkey_change_handler);
3082 devr->ports[port].devr = devr;
3083 }
3084
e126ba97
EC		 3085 return 0;
3086
4aa17b28
HA		 3087error5:
3088 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3089error4:
3090 mlx5_ib_dealloc_xrcd(devr->x1);
3091error3:
3092 mlx5_ib_dealloc_xrcd(devr->x0);
3093error2:
3094 mlx5_ib_destroy_cq(devr->c0);
3095error1:
3096 mlx5_ib_dealloc_pd(devr->p0);
3097error0:
3098 return ret;
3099}
3100
3101static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3102{
7722f47e
HE		 3103 struct mlx5_ib_dev *dev =
3104 container_of(devr, struct mlx5_ib_dev, devr);
3105 int port;
3106
4aa17b28 3107 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3108 mlx5_ib_destroy_srq(devr->s0);
3109 mlx5_ib_dealloc_xrcd(devr->x0);
3110 mlx5_ib_dealloc_xrcd(devr->x1);
3111 mlx5_ib_destroy_cq(devr->c0);
3112 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3113
3114 /* Make sure no change P_Key work items are still executing */
3115 for (port = 0; port < dev->num_ports; ++port)
3116 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3117}
3118
e53505a8
AS		 3119static u32 get_core_cap_flags(struct ib_device *ibdev)
3120{
3121 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3122 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3123 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3124 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3125 u32 ret = 0;
3126
3127 if (ll == IB_LINK_LAYER_INFINIBAND)
3128 return RDMA_CORE_PORT_IBA_IB;
3129
72cd5717
OG		 3130 ret = RDMA_CORE_PORT_RAW_PACKET;
3131
e53505a8 3132 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3133 return ret;
e53505a8
AS		 3134
3135 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3136 return ret;
e53505a8
AS		 3137
3138 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3139 ret |= RDMA_CORE_PORT_IBA_ROCE;
3140
3141 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3142 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3143
3144 return ret;
3145}
3146
7738613e
IW		 3147static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3148 struct ib_port_immutable *immutable)
3149{
3150 struct ib_port_attr attr;
ca5b91d6
OG		 3151 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3152 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3153 int err;
3154
c4550c63
OG		 3155 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3156
3157 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3158 if (err)
3159 return err;
3160
3161 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3162 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3163 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3164 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3165 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3166
3167 return 0;
3168}
3169
c7342823
IW		 3170static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3171 size_t str_len)
3172{
3173 struct mlx5_ib_dev *dev =
3174 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3175 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3176 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3177}
3178
45f95acd 3179static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3180{
3181 struct mlx5_core_dev *mdev = dev->mdev;
3182 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3183 MLX5_FLOW_NAMESPACE_LAG);
3184 struct mlx5_flow_table *ft;
3185 int err;
3186
3187 if (!ns || !mlx5_lag_is_active(mdev))
3188 return 0;
3189
3190 err = mlx5_cmd_create_vport_lag(mdev);
3191 if (err)
3192 return err;
3193
3194 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3195 if (IS_ERR(ft)) {
3196 err = PTR_ERR(ft);
3197 goto err_destroy_vport_lag;
3198 }
3199
3200 dev->flow_db.lag_demux_ft = ft;
3201 return 0;
3202
3203err_destroy_vport_lag:
3204 mlx5_cmd_destroy_vport_lag(mdev);
3205 return err;
3206}
3207
45f95acd 3208static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3209{
3210 struct mlx5_core_dev *mdev = dev->mdev;
3211
3212 if (dev->flow_db.lag_demux_ft) {
3213 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3214 dev->flow_db.lag_demux_ft = NULL;
3215
3216 mlx5_cmd_destroy_vport_lag(mdev);
3217 }
3218}
3219
d012f5d6
OG		 3220static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3221{
3222 int err;
3223
3224 dev->roce.nb.notifier_call = mlx5_netdev_event;
3225 err = register_netdevice_notifier(&dev->roce.nb);
3226 if (err) {
3227 dev->roce.nb.notifier_call = NULL;
3228 return err;
3229 }
3230
3231 return 0;
3232}
3233
3234static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3235{
3236 if (dev->roce.nb.notifier_call) {
3237 unregister_netdevice_notifier(&dev->roce.nb);
3238 dev->roce.nb.notifier_call = NULL;
3239 }
3240}
3241
45f95acd 3242static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3243{
e53505a8
AS		 3244 int err;
3245
d012f5d6
OG		 3246 err = mlx5_add_netdev_notifier(dev);
3247 if (err)
e53505a8
AS		 3248 return err;
3249
ca5b91d6
OG		 3250 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3251 err = mlx5_nic_vport_enable_roce(dev->mdev);
3252 if (err)
3253 goto err_unregister_netdevice_notifier;
3254 }
e53505a8 3255
45f95acd 3256 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3257 if (err)
3258 goto err_disable_roce;
3259
e53505a8
AS		 3260 return 0;
3261
9ef9c640 3262err_disable_roce:
ca5b91d6
OG		 3263 if (MLX5_CAP_GEN(dev->mdev, roce))
3264 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3265
e53505a8 3266err_unregister_netdevice_notifier:
d012f5d6 3267 mlx5_remove_netdev_notifier(dev);
e53505a8 3268 return err;
fc24fc5e
AS		 3269}
3270
45f95acd 3271static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3272{
45f95acd 3273 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3274 if (MLX5_CAP_GEN(dev->mdev, roce))
3275 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3276}
3277
e1f24a79 3278struct mlx5_ib_counter {
7c16f477
KH		 3279 const char *name;
3280 size_t offset;
3281};
3282
3283#define INIT_Q_COUNTER(_name) \
3284 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3285
e1f24a79 3286static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3287 INIT_Q_COUNTER(rx_write_requests),
3288 INIT_Q_COUNTER(rx_read_requests),
3289 INIT_Q_COUNTER(rx_atomic_requests),
3290 INIT_Q_COUNTER(out_of_buffer),
3291};
3292
e1f24a79 3293static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3294 INIT_Q_COUNTER(out_of_sequence),
3295};
3296
e1f24a79 3297static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3298 INIT_Q_COUNTER(duplicate_request),
3299 INIT_Q_COUNTER(rnr_nak_retry_err),
3300 INIT_Q_COUNTER(packet_seq_err),
3301 INIT_Q_COUNTER(implied_nak_seq_err),
3302 INIT_Q_COUNTER(local_ack_timeout_err),
3303};
3304
e1f24a79
PP		 3305#define INIT_CONG_COUNTER(_name) \
3306 { .name = #_name, .offset = \
3307 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3308
3309static const struct mlx5_ib_counter cong_cnts[] = {
3310 INIT_CONG_COUNTER(rp_cnp_ignored),
3311 INIT_CONG_COUNTER(rp_cnp_handled),
3312 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3313 INIT_CONG_COUNTER(np_cnp_sent),
3314};
3315
3316static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3317{
3318 unsigned int i;
3319
7c16f477 3320 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3321 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3322 dev->port[i].cnts.set_id);
3323 kfree(dev->port[i].cnts.names);
3324 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3325 }
3326}
3327
e1f24a79
PP		 3328static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3329 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3330{
3331 u32 num_counters;
3332
3333 num_counters = ARRAY_SIZE(basic_q_cnts);
3334
3335 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3336 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3337
3338 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3339 num_counters += ARRAY_SIZE(retrans_q_cnts);
e1f24a79 3340 cnts->num_q_counters = num_counters;
7c16f477 3341
e1f24a79
PP		 3342 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3343 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3344 num_counters += ARRAY_SIZE(cong_cnts);
3345 }
3346
3347 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3348 if (!cnts->names)
7c16f477
KH		 3349 return -ENOMEM;
3350
e1f24a79
PP		 3351 cnts->offsets = kcalloc(num_counters,
3352 sizeof(cnts->offsets), GFP_KERNEL);
3353 if (!cnts->offsets)
7c16f477
KH		 3354 goto err_names;
3355
7c16f477
KH		 3356 return 0;
3357
3358err_names:
e1f24a79 3359 kfree(cnts->names);
7c16f477
KH		 3360 return -ENOMEM;
3361}
3362
e1f24a79
PP		 3363static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3364 const char **names,
3365 size_t *offsets)
7c16f477
KH		 3366{
3367 int i;
3368 int j = 0;
3369
3370 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3371 names[j] = basic_q_cnts[i].name;
3372 offsets[j] = basic_q_cnts[i].offset;
3373 }
3374
3375 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3376 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3377 names[j] = out_of_seq_q_cnts[i].name;
3378 offsets[j] = out_of_seq_q_cnts[i].offset;
3379 }
3380 }
3381
3382 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3383 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3384 names[j] = retrans_q_cnts[i].name;
3385 offsets[j] = retrans_q_cnts[i].offset;
3386 }
3387 }
e1f24a79
PP		 3388
3389 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3390 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3391 names[j] = cong_cnts[i].name;
3392 offsets[j] = cong_cnts[i].offset;
3393 }
3394 }
0837e86a
MB		 3395}
3396
e1f24a79 3397static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3398{
3399 int i;
3400 int ret;
3401
3402 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3403 struct mlx5_ib_port *port = &dev->port[i];
3404
0837e86a 3405 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3406 &port->cnts.set_id);
0837e86a
MB		 3407 if (ret) {
3408 mlx5_ib_warn(dev,
3409 "couldn't allocate queue counter for port %d, err %d\n",
3410 i + 1, ret);
3411 goto dealloc_counters;
3412 }
7c16f477 3413
e1f24a79 3414 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3415 if (ret)
3416 goto dealloc_counters;
3417
e1f24a79
PP		 3418 mlx5_ib_fill_counters(dev, port->cnts.names,
3419 port->cnts.offsets);
0837e86a
MB		 3420 }
3421
3422 return 0;
3423
3424dealloc_counters:
3425 while (--i >= 0)
3426 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3427 dev->port[i].cnts.set_id);
0837e86a
MB		 3428
3429 return ret;
3430}
3431
0ad17a8f
MB		 3432static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3433 u8 port_num)
3434{
7c16f477
KH		 3435 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3436 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3437
3438 /* We support only per port stats */
3439 if (port_num == 0)
3440 return NULL;
3441
e1f24a79
PP		 3442 return rdma_alloc_hw_stats_struct(port->cnts.names,
3443 port->cnts.num_q_counters +
3444 port->cnts.num_cong_counters,
0ad17a8f
MB		 3445 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3446}
3447
e1f24a79
PP		 3448static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3449 struct mlx5_ib_port *port,
3450 struct rdma_hw_stats *stats)
0ad17a8f 3451{
0ad17a8f
MB		 3452 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3453 void *out;
3454 __be32 val;
e1f24a79 3455 int ret, i;
0ad17a8f 3456
1b9a07ee 3457 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3458 if (!out)
3459 return -ENOMEM;
3460
3461 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3462 port->cnts.set_id, 0,
0ad17a8f
MB		 3463 out, outlen);
3464 if (ret)
3465 goto free;
3466
e1f24a79
PP		 3467 for (i = 0; i < port->cnts.num_q_counters; i++) {
3468 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3469 stats->value[i] = (u64)be32_to_cpu(val);
3470 }
7c16f477 3471
0ad17a8f
MB		 3472free:
3473 kvfree(out);
e1f24a79
PP		 3474 return ret;
3475}
3476
3477static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3478 struct mlx5_ib_port *port,
3479 struct rdma_hw_stats *stats)
3480{
3481 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3482 void *out;
3483 int ret, i;
3484 int offset = port->cnts.num_q_counters;
3485
1b9a07ee 3486 out = kvzalloc(outlen, GFP_KERNEL);
e1f24a79
PP		 3487 if (!out)
3488 return -ENOMEM;
3489
3490 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3491 if (ret)
3492 goto free;
3493
3494 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3495 stats->value[i + offset] =
3496 be64_to_cpup((__be64 *)(out +
3497 port->cnts.offsets[i + offset]));
3498 }
3499
3500free:
3501 kvfree(out);
3502 return ret;
3503}
3504
3505static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3506 struct rdma_hw_stats *stats,
3507 u8 port_num, int index)
3508{
3509 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3510 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3511 int ret, num_counters;
3512
3513 if (!stats)
3514 return -EINVAL;
3515
3516 ret = mlx5_ib_query_q_counters(dev, port, stats);
3517 if (ret)
3518 return ret;
3519 num_counters = port->cnts.num_q_counters;
3520
3521 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3522 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3523 if (ret)
3524 return ret;
3525 num_counters += port->cnts.num_cong_counters;
3526 }
3527
3528 return num_counters;
0ad17a8f
MB		 3529}
3530
8e959601
NV		 3531static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3532{
3533 return mlx5_rdma_netdev_free(netdev);
3534}
3535
693dfd5a
ES		 3536static struct net_device*
3537mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3538 u8 port_num,
3539 enum rdma_netdev_t type,
3540 const char *name,
3541 unsigned char name_assign_type,
3542 void (*setup)(struct net_device *))
3543{
8e959601
NV		 3544 struct net_device *netdev;
3545 struct rdma_netdev *rn;
3546
693dfd5a
ES		 3547 if (type != RDMA_NETDEV_IPOIB)
3548 return ERR_PTR(-EOPNOTSUPP);
3549
8e959601
NV		 3550 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3551 name, setup);
3552 if (likely(!IS_ERR_OR_NULL(netdev))) {
3553 rn = netdev_priv(netdev);
3554 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3555 }
3556 return netdev;
693dfd5a
ES		 3557}
3558
9603b61d 3559static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3560{
e126ba97 3561 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3562 enum rdma_link_layer ll;
3563 int port_type_cap;
4babcf97 3564 const char *name;
e126ba97
EC		 3565 int err;
3566 int i;
3567
ebd61f68
AS		 3568 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3569 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3570
e126ba97
EC		 3571 printk_once(KERN_INFO "%s", mlx5_version);
3572
3573 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3574 if (!dev)
9603b61d 3575 return NULL;
e126ba97 3576
9603b61d 3577 dev->mdev = mdev;
e126ba97 3578
0837e86a
MB		 3579 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3580 GFP_KERNEL);
3581 if (!dev->port)
3582 goto err_dealloc;
3583
fc24fc5e 3584 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3585 err = get_port_caps(dev);
3586 if (err)
0837e86a 3587 goto err_free_port;
e126ba97 3588
1b5daf11
MD		 3589 if (mlx5_use_mad_ifc(dev))
3590 get_ext_port_caps(dev);
e126ba97 3591
4babcf97
AH		 3592 if (!mlx5_lag_is_active(mdev))
3593 name = "mlx5_%d";
3594 else
3595 name = "mlx5_bond_%d";
3596
3597 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3598 dev->ib_dev.owner = THIS_MODULE;
3599 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3600 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3601 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3602 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3603 dev->ib_dev.num_comp_vectors =
3604 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3605 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3606
3607 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3608 dev->ib_dev.uverbs_cmd_mask =
3609 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3610 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3611 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3612 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3613 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3614 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3615 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3616 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3617 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3618 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3619 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3620 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3621 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3622 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3623 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3624 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3625 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3626 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3627 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3628 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3629 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3630 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3631 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3632 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3633 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3634 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3635 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3636 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3637 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 3638 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3639 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 3640
3641 dev->ib_dev.query_device = mlx5_ib_query_device;
3642 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3643 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3644 if (ll == IB_LINK_LAYER_ETHERNET)
3645 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3646 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3647 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3648 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3649 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3650 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3651 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3652 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3653 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3654 dev->ib_dev.mmap = mlx5_ib_mmap;
3655 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3656 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3657 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3658 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3659 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3660 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3661 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3662 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3663 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3664 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3665 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3666 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3667 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3668 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3669 dev->ib_dev.post_send = mlx5_ib_post_send;
3670 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3671 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3672 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3673 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3674 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3675 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3676 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3677 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3678 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 3679 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 3680 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3681 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3682 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3683 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 3684 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 3685 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 3686 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 3687 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 3688 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
8e959601 3689 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 3690 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 3691
eff901d3
EC		 3692 if (mlx5_core_is_pf(mdev)) {
3693 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3694 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3695 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3696 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3697 }
e126ba97 3698
7c2344c3
MG		 3699 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3700
938fe83c 3701 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 3702
6e8484c5
MG		 3703 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3704
d2370e0a
MB		 3705 if (MLX5_CAP_GEN(mdev, imaicl)) {
3706 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3707 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3708 dev->ib_dev.uverbs_cmd_mask |=
3709 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3710 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3711 }
3712
7c16f477 3713 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 3714 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3715 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3716 }
3717
938fe83c 3718 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 3719 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3720 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3721 dev->ib_dev.uverbs_cmd_mask |=
3722 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3723 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3724 }
3725
048ccca8 3726 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 3727 IB_LINK_LAYER_ETHERNET) {
3728 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3729 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 3730 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3731 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3732 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 3733 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3734 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 3735 dev->ib_dev.uverbs_ex_cmd_mask |=
3736 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 3737 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3738 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3739 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 3740 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3741 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3742 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 3743 }
e126ba97
EC		 3744 err = init_node_data(dev);
3745 if (err)
90be7c8a 3746 goto err_free_port;
e126ba97 3747
038d2ef8 3748 mutex_init(&dev->flow_db.lock);
e126ba97 3749 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 3750 INIT_LIST_HEAD(&dev->qp_list);
3751 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 3752
fc24fc5e 3753 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 3754 err = mlx5_enable_eth(dev);
fc24fc5e 3755 if (err)
90be7c8a 3756 goto err_free_port;
fc24fc5e
AS		 3757 }
3758
e126ba97
EC		 3759 err = create_dev_resources(&dev->devr);
3760 if (err)
45f95acd 3761 goto err_disable_eth;
e126ba97 3762
6aec21f6 3763 err = mlx5_ib_odp_init_one(dev);
281d1a92 3764 if (err)
e126ba97
EC		 3765 goto err_rsrc;
3766
45bded2c 3767 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 3768 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 3769 if (err)
3770 goto err_odp;
3771 }
6aec21f6 3772
5fe9dec0
EC		 3773 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3774 if (!dev->mdev->priv.uar)
e1f24a79 3775 goto err_cnt;
5fe9dec0
EC		 3776
3777 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3778 if (err)
3779 goto err_uar_page;
3780
3781 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3782 if (err)
3783 goto err_bfreg;
3784
0837e86a
MB		 3785 err = ib_register_device(&dev->ib_dev, NULL);
3786 if (err)
5fe9dec0 3787 goto err_fp_bfreg;
0837e86a 3788
e126ba97
EC		 3789 err = create_umr_res(dev);
3790 if (err)
3791 goto err_dev;
3792
3793 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 3794 err = device_create_file(&dev->ib_dev.dev,
3795 mlx5_class_attributes[i]);
3796 if (err)
e126ba97
EC		 3797 goto err_umrc;
3798 }
3799
3800 dev->ib_active = true;
3801
9603b61d 3802 return dev;
e126ba97
EC		 3803
3804err_umrc:
3805 destroy_umrc_res(dev);
3806
3807err_dev:
3808 ib_unregister_device(&dev->ib_dev);
3809
5fe9dec0
EC		 3810err_fp_bfreg:
3811 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3812
3813err_bfreg:
3814 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3815
3816err_uar_page:
3817 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3818
e1f24a79 3819err_cnt:
45bded2c 3820 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 3821 mlx5_ib_dealloc_counters(dev);
0837e86a 3822
6aec21f6
HE		 3823err_odp:
3824 mlx5_ib_odp_remove_one(dev);
3825
e126ba97
EC		 3826err_rsrc:
3827 destroy_dev_resources(&dev->devr);
3828
45f95acd 3829err_disable_eth:
5ec8c83e 3830 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 3831 mlx5_disable_eth(dev);
d012f5d6 3832 mlx5_remove_netdev_notifier(dev);
5ec8c83e 3833 }
fc24fc5e 3834
0837e86a
MB		 3835err_free_port:
3836 kfree(dev->port);
3837
9603b61d 3838err_dealloc:
e126ba97
EC		 3839 ib_dealloc_device((struct ib_device *)dev);
3840
9603b61d 3841 return NULL;
e126ba97
EC		 3842}
3843
9603b61d 3844static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 3845{
9603b61d 3846 struct mlx5_ib_dev *dev = context;
fc24fc5e 3847 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 3848
d012f5d6 3849 mlx5_remove_netdev_notifier(dev);
e126ba97 3850 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 3851 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3852 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3853 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
45bded2c 3854 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 3855 mlx5_ib_dealloc_counters(dev);
eefd56e5 3856 destroy_umrc_res(dev);
6aec21f6 3857 mlx5_ib_odp_remove_one(dev);
e126ba97 3858 destroy_dev_resources(&dev->devr);
fc24fc5e 3859 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 3860 mlx5_disable_eth(dev);
0837e86a 3861 kfree(dev->port);
e126ba97
EC		 3862 ib_dealloc_device(&dev->ib_dev);
3863}
3864
9603b61d
JM		 3865static struct mlx5_interface mlx5_ib_interface = {
3866 .add = mlx5_ib_add,
3867 .remove = mlx5_ib_remove,
3868 .event = mlx5_ib_event,
d9aaed83
AK		 3869#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3870 .pfault = mlx5_ib_pfault,
3871#endif
64613d94 3872 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 3873};
3874
3875static int __init mlx5_ib_init(void)
3876{
6aec21f6
HE		 3877 int err;
3878
81713d37 3879 mlx5_ib_odp_init();
9603b61d 3880
6aec21f6 3881 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 3882
6aec21f6 3883 return err;
e126ba97
EC		 3884}
3885
3886static void __exit mlx5_ib_cleanup(void)
3887{
9603b61d 3888 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 3889}
3890
3891module_init(mlx5_ib_init);
3892module_exit(mlx5_ib_cleanup);
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