]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/infiniband/hw/mlx5/main.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IB/mlx5: Add information for querying IPsec capabilities
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
72c7fe90 53#include <linux/mlx5/fs.h>
802c2125 54#include <linux/mlx5/fs_helpers.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
da7525d2
EBE		 91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
d69a24e0 95static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
c44ef998
IL		 103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
32f69e4b
DJ		 109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
1b5daf11 119static enum rdma_link_layer
ebd61f68 120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 121{
ebd61f68 122 switch (port_type_cap) {
1b5daf11
MD		 123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
ebd61f68
AS		 132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
fd65f1b8
MS		 141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
8e6efa3a 149 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
fc24fc5e
AS		 155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
7fd8aefb 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
32f69e4b
DJ		 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
fc24fc5e 168
5ec8c83e
AH		 169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
7fd8aefb 172 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 181 NULL : ndev;
bcf87f1d
MB		 182 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) {
183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
fd65f1b8 189 case NETDEV_CHANGE:
5ec8c83e 190 case NETDEV_UP:
88621dfe 191 case NETDEV_DOWN: {
7fd8aefb 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
7fd8aefb 200 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 201 && ibdev->ib_active) {
626bc02d 202 struct ib_event ibev = { };
fd65f1b8 203 enum ib_port_state port_state;
5ec8c83e 204
7fd8aefb
DJ		 205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
fd65f1b8 208
7fd8aefb
DJ		 209 if (roce->last_port_state == port_state)
210 goto done;
fd65f1b8 211
7fd8aefb 212 roce->last_port_state = port_state;
5ec8c83e 213 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
7fd8aefb 219 goto done;
fd65f1b8 220
7fd8aefb 221 ibev.element.port_num = port_num;
5ec8c83e
AH		 222 ib_dispatch_event(&ibev);
223 }
224 break;
88621dfe 225 }
fc24fc5e 226
5ec8c83e
AH		 227 default:
228 break;
229 }
7fd8aefb 230done:
32f69e4b 231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
32f69e4b
DJ		 240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
fc24fc5e 245
32f69e4b 246 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 247 if (ndev)
32f69e4b 248 goto out;
88621dfe 249
fc24fc5e
AS		 250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
7fd8aefb
DJ		 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 254 if (ndev)
255 dev_hold(ndev);
7fd8aefb 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 257
32f69e4b
DJ		 258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 260 return ndev;
261}
262
32f69e4b
DJ		 263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
210b1f78
MB		 273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
32f69e4b
DJ		 280 if (native_port_num)
281 *native_port_num = 1;
282
32f69e4b
DJ		 283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
f1b65df5
NO		 326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
095b0927
IT		 384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
3f89a643
AS		 386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 388 struct mlx5_core_dev *mdev;
88621dfe 389 struct net_device *ndev, *upper;
3f89a643 390 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 391 bool put_mdev = true;
c876a1b7 392 u16 qkey_viol_cntr;
f1b65df5 393 u32 eth_prot_oper;
b3cbd6f0 394 u8 mdev_port_num;
095b0927 395 int err;
3f89a643 396
b3cbd6f0
DJ		 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
f1b65df5
NO		 408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
50f22fd8 410 */
b3cbd6f0
DJ		 411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
095b0927 413 if (err)
b3cbd6f0 414 goto out;
f1b65df5 415
7672ed33
HL		 416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
f1b65df5
NO		 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
3f89a643
AS		 421
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
b3cbd6f0 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 434 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 435
b3cbd6f0
DJ		 436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
3f89a643
AS		 440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
b3cbd6f0 442 goto out;
3f89a643 443
88621dfe
AH		 444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
3f89a643
AS		 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
3f89a643
AS		 469}
470
095b0927
IT		 471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
3cca2606 474{
095b0927
IT		 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
3cca2606
AS		 490 }
491
095b0927 492 switch (gid_type) {
3cca2606 493 case IB_GID_TYPE_IB:
095b0927 494 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 502 break;
503
504 default:
095b0927 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 506 }
507
095b0927
IT		 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 510 vlan_id, port_num);
3cca2606
AS		 511}
512
414448d2 513static int mlx5_ib_add_gid(const union ib_gid *gid,
3cca2606
AS		 514 const struct ib_gid_attr *attr,
515 __always_unused void **context)
516{
414448d2
PP		 517 return set_roce_addr(to_mdev(attr->device), attr->port_num,
518 attr->index, gid, attr);
3cca2606
AS		 519}
520
414448d2
PP		 521static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
522 __always_unused void **context)
3cca2606 523{
414448d2
PP		 524 return set_roce_addr(to_mdev(attr->device), attr->port_num,
525 attr->index, NULL, NULL);
3cca2606
AS		 526}
527
2811ba51
AS		 528__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
529 int index)
530{
531 struct ib_gid_attr attr;
532 union ib_gid gid;
533
534 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
535 return 0;
536
2811ba51
AS		 537 dev_put(attr.ndev);
538
539 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
540 return 0;
541
542 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
543}
544
ed88451e
MD		 545int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
546 int index, enum ib_gid_type *gid_type)
547{
548 struct ib_gid_attr attr;
549 union ib_gid gid;
550 int ret;
551
552 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
553 if (ret)
554 return ret;
555
ed88451e
MD		 556 dev_put(attr.ndev);
557
558 *gid_type = attr.gid_type;
559
560 return 0;
561}
562
1b5daf11
MD		 563static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
564{
7fae6655
NO		 565 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
566 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
567 return 0;
1b5daf11
MD		 568}
569
570enum {
571 MLX5_VPORT_ACCESS_METHOD_MAD,
572 MLX5_VPORT_ACCESS_METHOD_HCA,
573 MLX5_VPORT_ACCESS_METHOD_NIC,
574};
575
576static int mlx5_get_vport_access_method(struct ib_device *ibdev)
577{
578 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
579 return MLX5_VPORT_ACCESS_METHOD_MAD;
580
ebd61f68 581 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 582 IB_LINK_LAYER_ETHERNET)
583 return MLX5_VPORT_ACCESS_METHOD_NIC;
584
585 return MLX5_VPORT_ACCESS_METHOD_HCA;
586}
587
da7525d2 588static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 589 u8 atomic_size_qp,
da7525d2
EBE		 590 struct ib_device_attr *props)
591{
592 u8 tmp;
593 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 594 u8 atomic_req_8B_endianness_mode =
bd10838a 595 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 596
597 /* Check if HW supports 8 bytes standard atomic operations and capable
598 * of host endianness respond
599 */
600 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
601 if (((atomic_operations & tmp) == tmp) &&
602 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
603 (atomic_req_8B_endianness_mode)) {
604 props->atomic_cap = IB_ATOMIC_HCA;
605 } else {
606 props->atomic_cap = IB_ATOMIC_NONE;
607 }
608}
609
776a3906
MS		 610static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
611 struct ib_device_attr *props)
612{
613 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
614
615 get_atomic_caps(dev, atomic_size_qp, props);
616}
617
618static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
619 struct ib_device_attr *props)
620{
621 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
622
623 get_atomic_caps(dev, atomic_size_qp, props);
624}
625
626bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
627{
628 struct ib_device_attr props = {};
629
630 get_atomic_caps_dc(dev, &props);
631 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
632}
1b5daf11
MD		 633static int mlx5_query_system_image_guid(struct ib_device *ibdev,
634 __be64 *sys_image_guid)
635{
636 struct mlx5_ib_dev *dev = to_mdev(ibdev);
637 struct mlx5_core_dev *mdev = dev->mdev;
638 u64 tmp;
639 int err;
640
641 switch (mlx5_get_vport_access_method(ibdev)) {
642 case MLX5_VPORT_ACCESS_METHOD_MAD:
643 return mlx5_query_mad_ifc_system_image_guid(ibdev,
644 sys_image_guid);
645
646 case MLX5_VPORT_ACCESS_METHOD_HCA:
647 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 648 break;
649
650 case MLX5_VPORT_ACCESS_METHOD_NIC:
651 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
652 break;
1b5daf11
MD		 653
654 default:
655 return -EINVAL;
656 }
3f89a643
AS		 657
658 if (!err)
659 *sys_image_guid = cpu_to_be64(tmp);
660
661 return err;
662
1b5daf11
MD		 663}
664
665static int mlx5_query_max_pkeys(struct ib_device *ibdev,
666 u16 *max_pkeys)
667{
668 struct mlx5_ib_dev *dev = to_mdev(ibdev);
669 struct mlx5_core_dev *mdev = dev->mdev;
670
671 switch (mlx5_get_vport_access_method(ibdev)) {
672 case MLX5_VPORT_ACCESS_METHOD_MAD:
673 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
674
675 case MLX5_VPORT_ACCESS_METHOD_HCA:
676 case MLX5_VPORT_ACCESS_METHOD_NIC:
677 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
678 pkey_table_size));
679 return 0;
680
681 default:
682 return -EINVAL;
683 }
684}
685
686static int mlx5_query_vendor_id(struct ib_device *ibdev,
687 u32 *vendor_id)
688{
689 struct mlx5_ib_dev *dev = to_mdev(ibdev);
690
691 switch (mlx5_get_vport_access_method(ibdev)) {
692 case MLX5_VPORT_ACCESS_METHOD_MAD:
693 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
694
695 case MLX5_VPORT_ACCESS_METHOD_HCA:
696 case MLX5_VPORT_ACCESS_METHOD_NIC:
697 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
698
699 default:
700 return -EINVAL;
701 }
702}
703
704static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
705 __be64 *node_guid)
706{
707 u64 tmp;
708 int err;
709
710 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
711 case MLX5_VPORT_ACCESS_METHOD_MAD:
712 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
713
714 case MLX5_VPORT_ACCESS_METHOD_HCA:
715 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 716 break;
717
718 case MLX5_VPORT_ACCESS_METHOD_NIC:
719 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
720 break;
1b5daf11
MD		 721
722 default:
723 return -EINVAL;
724 }
3f89a643
AS		 725
726 if (!err)
727 *node_guid = cpu_to_be64(tmp);
728
729 return err;
1b5daf11
MD		 730}
731
732struct mlx5_reg_node_desc {
bd99fdea 733 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 734};
735
736static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
737{
738 struct mlx5_reg_node_desc in;
739
740 if (mlx5_use_mad_ifc(dev))
741 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
742
743 memset(&in, 0, sizeof(in));
744
745 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
746 sizeof(struct mlx5_reg_node_desc),
747 MLX5_REG_NODE_DESC, 0, 0);
748}
749
e126ba97 750static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 751 struct ib_device_attr *props,
752 struct ib_udata *uhw)
e126ba97
EC		 753{
754 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 755 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 756 int err = -ENOMEM;
288c01b7 757 int max_sq_desc;
e126ba97
EC		 758 int max_rq_sg;
759 int max_sq_sg;
e0238a6a 760 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 761 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 762 struct mlx5_ib_query_device_resp resp = {};
763 size_t resp_len;
764 u64 max_tso;
e126ba97 765
402ca536
BW		 766 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
767 if (uhw->outlen && uhw->outlen < resp_len)
768 return -EINVAL;
769 else
770 resp.response_length = resp_len;
771
772 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 773 return -EINVAL;
774
1b5daf11
MD		 775 memset(props, 0, sizeof(*props));
776 err = mlx5_query_system_image_guid(ibdev,
777 &props->sys_image_guid);
778 if (err)
779 return err;
e126ba97 780
1b5daf11 781 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 782 if (err)
1b5daf11 783 return err;
e126ba97 784
1b5daf11
MD		 785 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
786 if (err)
787 return err;
e126ba97 788
9603b61d
JM		 789 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
790 (fw_rev_min(dev->mdev) << 16) |
791 fw_rev_sub(dev->mdev);
e126ba97
EC		 792 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
793 IB_DEVICE_PORT_ACTIVE_EVENT |
794 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 795 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 796
797 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 798 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 799 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 800 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 801 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 802 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 803 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 804 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 805 if (MLX5_CAP_GEN(mdev, imaicl)) {
806 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
807 IB_DEVICE_MEM_WINDOW_TYPE_2B;
808 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 809 /* We support 'Gappy' memory registration too */
810 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 811 }
e126ba97 812 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 813 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 814 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
815 /* At this stage no support for signature handover */
816 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
817 IB_PROT_T10DIF_TYPE_2 |
818 IB_PROT_T10DIF_TYPE_3;
819 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
820 IB_GUARD_T10DIF_CSUM;
821 }
938fe83c 822 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 823 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 824
85c7c014 825 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 826 if (MLX5_CAP_ETH(mdev, csum_cap)) {
827 /* Legacy bit to support old userspace libraries */
88115fe7 828 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 829 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
830 }
831
832 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
833 props->raw_packet_caps |=
834 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 835
402ca536
BW		 836 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
837 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
838 if (max_tso) {
839 resp.tso_caps.max_tso = 1 << max_tso;
840 resp.tso_caps.supported_qpts |=
841 1 << IB_QPT_RAW_PACKET;
842 resp.response_length += sizeof(resp.tso_caps);
843 }
844 }
31f69a82
YH		 845
846 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
847 resp.rss_caps.rx_hash_function =
848 MLX5_RX_HASH_FUNC_TOEPLITZ;
849 resp.rss_caps.rx_hash_fields_mask =
850 MLX5_RX_HASH_SRC_IPV4 |
851 MLX5_RX_HASH_DST_IPV4 |
852 MLX5_RX_HASH_SRC_IPV6 |
853 MLX5_RX_HASH_DST_IPV6 |
854 MLX5_RX_HASH_SRC_PORT_TCP |
855 MLX5_RX_HASH_DST_PORT_TCP |
856 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 857 MLX5_RX_HASH_DST_PORT_UDP |
858 MLX5_RX_HASH_INNER;
31f69a82
YH		 859 resp.response_length += sizeof(resp.rss_caps);
860 }
861 } else {
862 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
863 resp.response_length += sizeof(resp.tso_caps);
864 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
865 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 866 }
867
f0313965
ES		 868 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
869 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
870 props->device_cap_flags |= IB_DEVICE_UD_TSO;
871 }
872
03404e8a 873 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 874 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
875 raw_support)
03404e8a
MG		 876 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
877
1d54f890
YH		 878 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
879 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
880 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
881
cff5a0f3 882 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 883 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
884 raw_support) {
e8161334 885 /* Legacy bit to support old userspace libraries */
cff5a0f3 886 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 887 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
888 }
cff5a0f3 889
da6d6ba3
MG		 890 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
891 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
892
b1383aa6
NO		 893 if (MLX5_CAP_GEN(mdev, end_pad))
894 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
895
1b5daf11
MD		 896 props->vendor_part_id = mdev->pdev->device;
897 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 898
899 props->max_mr_size = ~0ull;
e0238a6a 900 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 901 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
902 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
903 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
904 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 905 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
906 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
907 sizeof(struct mlx5_wqe_raddr_seg)) /
908 sizeof(struct mlx5_wqe_data_seg);
e126ba97 909 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 910 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 911 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 912 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 913 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
914 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
915 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
916 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
917 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
918 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
919 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 920 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 921 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 922 props->max_fast_reg_page_list_len =
923 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 924 get_atomic_caps_qp(dev, props);
81bea28f 925 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 926 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
927 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 928 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
929 props->max_mcast_grp;
930 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 931 props->max_ah = INT_MAX;
7c60bcbb
MB		 932 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
933 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 934
8cdd312c 935#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 936 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 937 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
938 props->odp_caps = dev->odp_caps;
939#endif
940
051f2630
LR		 941 if (MLX5_CAP_GEN(mdev, cd))
942 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
943
eff901d3
EC		 944 if (!mlx5_core_is_pf(mdev))
945 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
946
31f69a82 947 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 948 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 949 props->rss_caps.max_rwq_indirection_tables =
950 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
951 props->rss_caps.max_rwq_indirection_table_size =
952 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
953 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
954 props->max_wq_type_rq =
955 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
956 }
957
eb761894 958 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 959 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
960 props->tm_caps.max_num_tags =
eb761894 961 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 962 props->tm_caps.flags = IB_TM_CAP_RC;
963 props->tm_caps.max_ops =
eb761894 964 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 965 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 966 }
967
87ab3f52
YC		 968 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
969 props->cq_caps.max_cq_moderation_count =
970 MLX5_MAX_CQ_COUNT;
971 props->cq_caps.max_cq_moderation_period =
972 MLX5_MAX_CQ_PERIOD;
973 }
974
7e43a2a5
BW		 975 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
976 resp.cqe_comp_caps.max_num =
977 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
978 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
979 resp.cqe_comp_caps.supported_format =
980 MLX5_IB_CQE_RES_FORMAT_HASH |
981 MLX5_IB_CQE_RES_FORMAT_CSUM;
982 resp.response_length += sizeof(resp.cqe_comp_caps);
983 }
984
85c7c014
DJ		 985 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
986 raw_support) {
d949167d
BW		 987 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
988 MLX5_CAP_GEN(mdev, qos)) {
989 resp.packet_pacing_caps.qp_rate_limit_max =
990 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
991 resp.packet_pacing_caps.qp_rate_limit_min =
992 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
993 resp.packet_pacing_caps.supported_qpts |=
994 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 995 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
996 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
997 resp.packet_pacing_caps.cap_flags |=
998 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 999 }
1000 resp.response_length += sizeof(resp.packet_pacing_caps);
1001 }
1002
9f885201
LR		 1003 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1004 uhw->outlen)) {
795b609c
BW		 1005 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1006 resp.mlx5_ib_support_multi_pkt_send_wqes =
1007 MLX5_IB_ALLOW_MPW;
050da902
BW		 1008
1009 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1010 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1011 MLX5_IB_SUPPORT_EMPW;
1012
9f885201
LR		 1013 resp.response_length +=
1014 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1015 }
1016
de57f2ad
GL		 1017 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1018 resp.response_length += sizeof(resp.flags);
7a0c8f42 1019
de57f2ad
GL		 1020 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1021 resp.flags |=
1022 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1023
1024 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1025 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1026 }
9f885201 1027
96dc3fc5
NO		 1028 if (field_avail(typeof(resp), sw_parsing_caps,
1029 uhw->outlen)) {
1030 resp.response_length += sizeof(resp.sw_parsing_caps);
1031 if (MLX5_CAP_ETH(mdev, swp)) {
1032 resp.sw_parsing_caps.sw_parsing_offloads |=
1033 MLX5_IB_SW_PARSING;
1034
1035 if (MLX5_CAP_ETH(mdev, swp_csum))
1036 resp.sw_parsing_caps.sw_parsing_offloads |=
1037 MLX5_IB_SW_PARSING_CSUM;
1038
1039 if (MLX5_CAP_ETH(mdev, swp_lso))
1040 resp.sw_parsing_caps.sw_parsing_offloads |=
1041 MLX5_IB_SW_PARSING_LSO;
1042
1043 if (resp.sw_parsing_caps.sw_parsing_offloads)
1044 resp.sw_parsing_caps.supported_qpts =
1045 BIT(IB_QPT_RAW_PACKET);
1046 }
1047 }
1048
85c7c014
DJ		 1049 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1050 raw_support) {
b4f34597
NO		 1051 resp.response_length += sizeof(resp.striding_rq_caps);
1052 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1053 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1054 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1055 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1056 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1057 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1058 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1059 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1060 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1061 resp.striding_rq_caps.supported_qpts =
1062 BIT(IB_QPT_RAW_PACKET);
1063 }
1064 }
1065
f95ef6cb
MG		 1066 if (field_avail(typeof(resp), tunnel_offloads_caps,
1067 uhw->outlen)) {
1068 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1069 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1070 resp.tunnel_offloads_caps |=
1071 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1072 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1073 resp.tunnel_offloads_caps |=
1074 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1075 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1076 resp.tunnel_offloads_caps |=
1077 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1078 }
1079
402ca536
BW		 1080 if (uhw->outlen) {
1081 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1082
1083 if (err)
1084 return err;
1085 }
1086
1b5daf11 1087 return 0;
e126ba97
EC		 1088}
1089
1b5daf11
MD		 1090enum mlx5_ib_width {
1091 MLX5_IB_WIDTH_1X = 1 << 0,
1092 MLX5_IB_WIDTH_2X = 1 << 1,
1093 MLX5_IB_WIDTH_4X = 1 << 2,
1094 MLX5_IB_WIDTH_8X = 1 << 3,
1095 MLX5_IB_WIDTH_12X = 1 << 4
1096};
1097
1098static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1099 u8 *ib_width)
e126ba97
EC		 1100{
1101 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1102 int err = 0;
1103
1104 if (active_width & MLX5_IB_WIDTH_1X) {
1105 *ib_width = IB_WIDTH_1X;
1106 } else if (active_width & MLX5_IB_WIDTH_2X) {
1107 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1108 (int)active_width);
1109 err = -EINVAL;
1110 } else if (active_width & MLX5_IB_WIDTH_4X) {
1111 *ib_width = IB_WIDTH_4X;
1112 } else if (active_width & MLX5_IB_WIDTH_8X) {
1113 *ib_width = IB_WIDTH_8X;
1114 } else if (active_width & MLX5_IB_WIDTH_12X) {
1115 *ib_width = IB_WIDTH_12X;
1116 } else {
1117 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1118 (int)active_width);
1119 err = -EINVAL;
e126ba97
EC		 1120 }
1121
1b5daf11
MD		 1122 return err;
1123}
e126ba97 1124
1b5daf11
MD		 1125static int mlx5_mtu_to_ib_mtu(int mtu)
1126{
1127 switch (mtu) {
1128 case 256: return 1;
1129 case 512: return 2;
1130 case 1024: return 3;
1131 case 2048: return 4;
1132 case 4096: return 5;
1133 default:
1134 pr_warn("invalid mtu\n");
1135 return -1;
e126ba97 1136 }
1b5daf11 1137}
e126ba97 1138
1b5daf11
MD		 1139enum ib_max_vl_num {
1140 __IB_MAX_VL_0 = 1,
1141 __IB_MAX_VL_0_1 = 2,
1142 __IB_MAX_VL_0_3 = 3,
1143 __IB_MAX_VL_0_7 = 4,
1144 __IB_MAX_VL_0_14 = 5,
1145};
e126ba97 1146
1b5daf11
MD		 1147enum mlx5_vl_hw_cap {
1148 MLX5_VL_HW_0 = 1,
1149 MLX5_VL_HW_0_1 = 2,
1150 MLX5_VL_HW_0_2 = 3,
1151 MLX5_VL_HW_0_3 = 4,
1152 MLX5_VL_HW_0_4 = 5,
1153 MLX5_VL_HW_0_5 = 6,
1154 MLX5_VL_HW_0_6 = 7,
1155 MLX5_VL_HW_0_7 = 8,
1156 MLX5_VL_HW_0_14 = 15
1157};
e126ba97 1158
1b5daf11
MD		 1159static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1160 u8 *max_vl_num)
1161{
1162 switch (vl_hw_cap) {
1163 case MLX5_VL_HW_0:
1164 *max_vl_num = __IB_MAX_VL_0;
1165 break;
1166 case MLX5_VL_HW_0_1:
1167 *max_vl_num = __IB_MAX_VL_0_1;
1168 break;
1169 case MLX5_VL_HW_0_3:
1170 *max_vl_num = __IB_MAX_VL_0_3;
1171 break;
1172 case MLX5_VL_HW_0_7:
1173 *max_vl_num = __IB_MAX_VL_0_7;
1174 break;
1175 case MLX5_VL_HW_0_14:
1176 *max_vl_num = __IB_MAX_VL_0_14;
1177 break;
e126ba97 1178
1b5daf11
MD		 1179 default:
1180 return -EINVAL;
e126ba97 1181 }
e126ba97 1182
1b5daf11 1183 return 0;
e126ba97
EC		 1184}
1185
1b5daf11
MD		 1186static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1187 struct ib_port_attr *props)
e126ba97 1188{
1b5daf11
MD		 1189 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1190 struct mlx5_core_dev *mdev = dev->mdev;
1191 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1192 u16 max_mtu;
1193 u16 oper_mtu;
1b5daf11
MD		 1194 int err;
1195 u8 ib_link_width_oper;
1196 u8 vl_hw_cap;
e126ba97 1197
1b5daf11
MD		 1198 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1199 if (!rep) {
1200 err = -ENOMEM;
e126ba97 1201 goto out;
e126ba97 1202 }
e126ba97 1203
c4550c63 1204 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1205
1b5daf11 1206 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1207 if (err)
1208 goto out;
1209
1b5daf11
MD		 1210 props->lid = rep->lid;
1211 props->lmc = rep->lmc;
1212 props->sm_lid = rep->sm_lid;
1213 props->sm_sl = rep->sm_sl;
1214 props->state = rep->vport_state;
1215 props->phys_state = rep->port_physical_state;
1216 props->port_cap_flags = rep->cap_mask1;
1217 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1218 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1219 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1220 props->bad_pkey_cntr = rep->pkey_violation_counter;
1221 props->qkey_viol_cntr = rep->qkey_violation_counter;
1222 props->subnet_timeout = rep->subnet_timeout;
1223 props->init_type_reply = rep->init_type_reply;
eff901d3 1224 props->grh_required = rep->grh_required;
e126ba97 1225
1b5daf11
MD		 1226 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1227 if (err)
e126ba97 1228 goto out;
e126ba97 1229
1b5daf11
MD		 1230 err = translate_active_width(ibdev, ib_link_width_oper,
1231 &props->active_width);
1232 if (err)
1233 goto out;
d5beb7f2 1234 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1235 if (err)
1236 goto out;
1237
facc9699 1238 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1239
1b5daf11 1240 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1241
facc9699 1242 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1243
1b5daf11 1244 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1245
1b5daf11
MD		 1246 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1247 if (err)
1248 goto out;
e126ba97 1249
1b5daf11
MD		 1250 err = translate_max_vl_num(ibdev, vl_hw_cap,
1251 &props->max_vl_num);
e126ba97 1252out:
1b5daf11 1253 kfree(rep);
e126ba97
EC		 1254 return err;
1255}
1256
1b5daf11
MD		 1257int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1258 struct ib_port_attr *props)
e126ba97 1259{
095b0927
IT		 1260 unsigned int count;
1261 int ret;
1262
1b5daf11
MD		 1263 switch (mlx5_get_vport_access_method(ibdev)) {
1264 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1265 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1266 break;
e126ba97 1267
1b5daf11 1268 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1269 ret = mlx5_query_hca_port(ibdev, port, props);
1270 break;
e126ba97 1271
3f89a643 1272 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1273 ret = mlx5_query_port_roce(ibdev, port, props);
1274 break;
3f89a643 1275
1b5daf11 1276 default:
095b0927
IT		 1277 ret = -EINVAL;
1278 }
1279
1280 if (!ret && props) {
b3cbd6f0
DJ		 1281 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1282 struct mlx5_core_dev *mdev;
1283 bool put_mdev = true;
1284
1285 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1286 if (!mdev) {
1287 /* If the port isn't affiliated yet query the master.
1288 * The master and slave will have the same values.
1289 */
1290 mdev = dev->mdev;
1291 port = 1;
1292 put_mdev = false;
1293 }
1294 count = mlx5_core_reserved_gids_count(mdev);
1295 if (put_mdev)
1296 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1297 props->gid_tbl_len -= count;
1b5daf11 1298 }
095b0927 1299 return ret;
1b5daf11 1300}
e126ba97 1301
8e6efa3a
MB		 1302static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1303 struct ib_port_attr *props)
1304{
1305 int ret;
1306
1307 /* Only link layer == ethernet is valid for representors */
1308 ret = mlx5_query_port_roce(ibdev, port, props);
1309 if (ret || !props)
1310 return ret;
1311
1312 /* We don't support GIDS */
1313 props->gid_tbl_len = 0;
1314
1315 return ret;
1316}
1317
1b5daf11
MD		 1318static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1319 union ib_gid *gid)
1320{
1321 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1322 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1323
1b5daf11
MD		 1324 switch (mlx5_get_vport_access_method(ibdev)) {
1325 case MLX5_VPORT_ACCESS_METHOD_MAD:
1326 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1327
1b5daf11
MD		 1328 case MLX5_VPORT_ACCESS_METHOD_HCA:
1329 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1330
1331 default:
1332 return -EINVAL;
1333 }
e126ba97 1334
e126ba97
EC		 1335}
1336
b3cbd6f0
DJ		 1337static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1338 u16 index, u16 *pkey)
1b5daf11
MD		 1339{
1340 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1341 struct mlx5_core_dev *mdev;
1342 bool put_mdev = true;
1343 u8 mdev_port_num;
1344 int err;
1b5daf11 1345
b3cbd6f0
DJ		 1346 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1347 if (!mdev) {
1348 /* The port isn't affiliated yet, get the PKey from the master
1349 * port. For RoCE the PKey tables will be the same.
1350 */
1351 put_mdev = false;
1352 mdev = dev->mdev;
1353 mdev_port_num = 1;
1354 }
1355
1356 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1357 index, pkey);
1358 if (put_mdev)
1359 mlx5_ib_put_native_port_mdev(dev, port);
1360
1361 return err;
1362}
1363
1364static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1365 u16 *pkey)
1366{
1b5daf11
MD		 1367 switch (mlx5_get_vport_access_method(ibdev)) {
1368 case MLX5_VPORT_ACCESS_METHOD_MAD:
1369 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1370
1371 case MLX5_VPORT_ACCESS_METHOD_HCA:
1372 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1373 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1374 default:
1375 return -EINVAL;
1376 }
1377}
e126ba97
EC		 1378
1379static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1380 struct ib_device_modify *props)
1381{
1382 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1383 struct mlx5_reg_node_desc in;
1384 struct mlx5_reg_node_desc out;
1385 int err;
1386
1387 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1388 return -EOPNOTSUPP;
1389
1390 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1391 return 0;
1392
1393 /*
1394 * If possible, pass node desc to FW, so it can generate
1395 * a 144 trap. If cmd fails, just ignore.
1396 */
bd99fdea 1397 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1398 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1399 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1400 if (err)
1401 return err;
1402
bd99fdea 1403 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1404
1405 return err;
1406}
1407
cdbe33d0
EC		 1408static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1409 u32 value)
1410{
1411 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1412 struct mlx5_core_dev *mdev;
1413 u8 mdev_port_num;
cdbe33d0
EC		 1414 int err;
1415
b3cbd6f0
DJ		 1416 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1417 if (!mdev)
1418 return -ENODEV;
1419
1420 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1421 if (err)
b3cbd6f0 1422 goto out;
cdbe33d0
EC		 1423
1424 if (~ctx.cap_mask1_perm & mask) {
1425 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1426 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1427 err = -EINVAL;
1428 goto out;
cdbe33d0
EC		 1429 }
1430
1431 ctx.cap_mask1 = value;
1432 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1433 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1434 0, &ctx);
1435
1436out:
1437 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1438
1439 return err;
1440}
1441
e126ba97
EC		 1442static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1443 struct ib_port_modify *props)
1444{
1445 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1446 struct ib_port_attr attr;
1447 u32 tmp;
1448 int err;
cdbe33d0
EC		 1449 u32 change_mask;
1450 u32 value;
1451 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1452 IB_LINK_LAYER_INFINIBAND);
1453
ec255879
MD		 1454 /* CM layer calls ib_modify_port() regardless of the link layer. For
1455 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1456 */
1457 if (!is_ib)
1458 return 0;
1459
cdbe33d0
EC		 1460 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1461 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1462 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1463 return set_port_caps_atomic(dev, port, change_mask, value);
1464 }
e126ba97
EC		 1465
1466 mutex_lock(&dev->cap_mask_mutex);
1467
c4550c63 1468 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1469 if (err)
1470 goto out;
1471
1472 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1473 ~props->clr_port_cap_mask;
1474
9603b61d 1475 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1476
1477out:
1478 mutex_unlock(&dev->cap_mask_mutex);
1479 return err;
1480}
1481
30aa60b3
EC		 1482static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1483{
1484 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1485 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1486}
1487
31a78a5a
YH		 1488static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1489{
1490 /* Large page with non 4k uar support might limit the dynamic size */
1491 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1492 return MLX5_MIN_DYN_BFREGS;
1493
1494 return MLX5_MAX_DYN_BFREGS;
1495}
1496
b037c29a
EC		 1497static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1498 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1499 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1500{
1501 int uars_per_sys_page;
1502 int bfregs_per_sys_page;
1503 int ref_bfregs = req->total_num_bfregs;
1504
1505 if (req->total_num_bfregs == 0)
1506 return -EINVAL;
1507
1508 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1509 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1510
1511 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1512 return -ENOMEM;
1513
1514 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1515 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1516 /* This holds the required static allocation asked by the user */
b037c29a 1517 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1518 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1519 return -EINVAL;
1520
31a78a5a
YH		 1521 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1522 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1523 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1524 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1525
1526 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1527 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1528 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1529 req->total_num_bfregs, bfregi->total_num_bfregs,
1530 bfregi->num_sys_pages);
b037c29a
EC		 1531
1532 return 0;
1533}
1534
1535static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1536{
1537 struct mlx5_bfreg_info *bfregi;
1538 int err;
1539 int i;
1540
1541 bfregi = &context->bfregi;
31a78a5a 1542 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1543 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1544 if (err)
1545 goto error;
1546
1547 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1548 }
4ed131d0
YH		 1549
1550 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1551 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1552
b037c29a
EC		 1553 return 0;
1554
1555error:
1556 for (--i; i >= 0; i--)
1557 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1558 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1559
1560 return err;
1561}
1562
1563static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1564{
1565 struct mlx5_bfreg_info *bfregi;
1566 int err;
1567 int i;
1568
1569 bfregi = &context->bfregi;
4ed131d0
YH		 1570 for (i = 0; i < bfregi->num_sys_pages; i++) {
1571 if (i < bfregi->num_static_sys_pages ||
1572 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1573 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1574 if (err) {
1575 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1576 return err;
1577 }
b037c29a
EC		 1578 }
1579 }
4ed131d0 1580
b037c29a
EC		 1581 return 0;
1582}
1583
c85023e1
HN		 1584static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1585{
1586 int err;
1587
1588 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1589 if (err)
1590 return err;
1591
1592 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1593 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1594 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1595 return err;
1596
1597 mutex_lock(&dev->lb_mutex);
1598 dev->user_td++;
1599
1600 if (dev->user_td == 2)
1601 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1602
1603 mutex_unlock(&dev->lb_mutex);
1604 return err;
1605}
1606
1607static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1608{
1609 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1610
1611 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1612 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1613 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1614 return;
1615
1616 mutex_lock(&dev->lb_mutex);
1617 dev->user_td--;
1618
1619 if (dev->user_td < 2)
1620 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1621
1622 mutex_unlock(&dev->lb_mutex);
1623}
1624
e126ba97
EC		 1625static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1626 struct ib_udata *udata)
1627{
1628 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1629 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1630 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1631 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1632 struct mlx5_ib_ucontext *context;
2f5ff264 1633 struct mlx5_bfreg_info *bfregi;
78c0f98c 1634 int ver;
e126ba97 1635 int err;
a168a41c
MD		 1636 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1637 max_cqe_version);
b037c29a 1638 bool lib_uar_4k;
e126ba97
EC		 1639
1640 if (!dev->ib_active)
1641 return ERR_PTR(-EAGAIN);
1642
e093111d 1643 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1644 ver = 0;
e093111d 1645 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1646 ver = 2;
1647 else
1648 return ERR_PTR(-EINVAL);
1649
e093111d 1650 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1651 if (err)
1652 return ERR_PTR(err);
1653
b368d7cb 1654 if (req.flags)
78c0f98c
EC		 1655 return ERR_PTR(-EINVAL);
1656
f72300c5 1657 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1658 return ERR_PTR(-EOPNOTSUPP);
1659
2f5ff264
EC		 1660 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1661 MLX5_NON_FP_BFREGS_PER_UAR);
1662 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1663 return ERR_PTR(-EINVAL);
1664
938fe83c 1665 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1666 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1667 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1668 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1669 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1670 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1671 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1672 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1673 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1674 resp.cqe_version = min_t(__u8,
1675 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1676 req.max_cqe_version);
30aa60b3
EC		 1677 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1678 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1679 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1680 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1681 resp.response_length = min(offsetof(typeof(resp), response_length) +
1682 sizeof(resp.response_length), udata->outlen);
e126ba97 1683
c03faa56
MB		 1684 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1685 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1686 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1687 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1688 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1689 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1690 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1691 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1692 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1693 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1694 }
1695
e126ba97
EC		 1696 context = kzalloc(sizeof(*context), GFP_KERNEL);
1697 if (!context)
1698 return ERR_PTR(-ENOMEM);
1699
30aa60b3 1700 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1701 bfregi = &context->bfregi;
b037c29a
EC		 1702
1703 /* updates req->total_num_bfregs */
31a78a5a 1704 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1705 if (err)
e126ba97 1706 goto out_ctx;
e126ba97 1707
b037c29a
EC		 1708 mutex_init(&bfregi->lock);
1709 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1710 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1711 GFP_KERNEL);
b037c29a 1712 if (!bfregi->count) {
e126ba97 1713 err = -ENOMEM;
b037c29a 1714 goto out_ctx;
e126ba97
EC		 1715 }
1716
b037c29a
EC		 1717 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1718 sizeof(*bfregi->sys_pages),
1719 GFP_KERNEL);
1720 if (!bfregi->sys_pages) {
e126ba97 1721 err = -ENOMEM;
b037c29a 1722 goto out_count;
e126ba97
EC		 1723 }
1724
b037c29a
EC		 1725 err = allocate_uars(dev, context);
1726 if (err)
1727 goto out_sys_pages;
e126ba97 1728
b4cfe447
HE		 1729#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1730 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1731#endif
1732
146d2f1a 1733 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1734 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1735 if (err)
c44ef998 1736 goto out_uars;
146d2f1a 1737 }
1738
7c2344c3 1739 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1740 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1741 INIT_LIST_HEAD(&context->db_page_list);
1742 mutex_init(&context->db_page_mutex);
1743
2f5ff264 1744 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1745 resp.num_ports = dev->num_ports;
b368d7cb 1746
f72300c5
HA		 1747 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1748 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1749
402ca536 1750 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1751 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1752 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1753 resp.response_length += sizeof(resp.cmds_supp_uhw);
1754 }
1755
78984898
OG		 1756 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1757 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1758 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1759 resp.eth_min_inline++;
1760 }
1761 resp.response_length += sizeof(resp.eth_min_inline);
1762 }
1763
5c99eaec
FD		 1764 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1765 if (mdev->clock_info)
1766 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1767 resp.response_length += sizeof(resp.clock_info_versions);
1768 }
1769
bc5c6eed
NO		 1770 /*
1771 * We don't want to expose information from the PCI bar that is located
1772 * after 4096 bytes, so if the arch only supports larger pages, let's
1773 * pretend we don't support reading the HCA's core clock. This is also
1774 * forced by mmap function.
1775 */
de8d6e02
EC		 1776 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1777 if (PAGE_SIZE <= 4096) {
1778 resp.comp_mask |=
1779 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1780 resp.hca_core_clock_offset =
1781 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1782 }
5c99eaec 1783 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1784 }
1785
30aa60b3
EC		 1786 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1787 resp.response_length += sizeof(resp.log_uar_size);
1788
1789 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1790 resp.response_length += sizeof(resp.num_uars_per_page);
1791
31a78a5a
YH		 1792 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1793 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1794 resp.response_length += sizeof(resp.num_dyn_bfregs);
1795 }
1796
b368d7cb 1797 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1798 if (err)
146d2f1a 1799 goto out_td;
e126ba97 1800
2f5ff264
EC		 1801 bfregi->ver = ver;
1802 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1803 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1804 context->lib_caps = req.lib_caps;
1805 print_lib_caps(dev, context->lib_caps);
f72300c5 1806
e126ba97
EC		 1807 return &context->ibucontext;
1808
146d2f1a 1809out_td:
1810 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1811 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1812
e126ba97 1813out_uars:
b037c29a 1814 deallocate_uars(dev, context);
e126ba97 1815
b037c29a
EC		 1816out_sys_pages:
1817 kfree(bfregi->sys_pages);
e126ba97 1818
b037c29a
EC		 1819out_count:
1820 kfree(bfregi->count);
e126ba97
EC		 1821
1822out_ctx:
1823 kfree(context);
b037c29a 1824
e126ba97
EC		 1825 return ERR_PTR(err);
1826}
1827
1828static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1829{
1830 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1831 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1832 struct mlx5_bfreg_info *bfregi;
e126ba97 1833
b037c29a 1834 bfregi = &context->bfregi;
146d2f1a 1835 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1836 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1837
b037c29a
EC		 1838 deallocate_uars(dev, context);
1839 kfree(bfregi->sys_pages);
2f5ff264 1840 kfree(bfregi->count);
e126ba97
EC		 1841 kfree(context);
1842
1843 return 0;
1844}
1845
b037c29a 1846static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1847 int uar_idx)
e126ba97 1848{
b037c29a
EC		 1849 int fw_uars_per_page;
1850
1851 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1852
4ed131d0 1853 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1854}
1855
1856static int get_command(unsigned long offset)
1857{
1858 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1859}
1860
1861static int get_arg(unsigned long offset)
1862{
1863 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1864}
1865
1866static int get_index(unsigned long offset)
1867{
1868 return get_arg(offset);
1869}
1870
4ed131d0
YH		 1871/* Index resides in an extra byte to enable larger values than 255 */
1872static int get_extended_index(unsigned long offset)
1873{
1874 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1875}
1876
7c2344c3
MG		 1877static void mlx5_ib_vma_open(struct vm_area_struct *area)
1878{
1879 /* vma_open is called when a new VMA is created on top of our VMA. This
1880 * is done through either mremap flow or split_vma (usually due to
1881 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1882 * as this VMA is strongly hardware related. Therefore we set the
1883 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1884 * calling us again and trying to do incorrect actions. We assume that
1885 * the original VMA size is exactly a single page, and therefore all
1886 * "splitting" operation will not happen to it.
1887 */
1888 area->vm_ops = NULL;
1889}
1890
1891static void mlx5_ib_vma_close(struct vm_area_struct *area)
1892{
1893 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1894
1895 /* It's guaranteed that all VMAs opened on a FD are closed before the
1896 * file itself is closed, therefore no sync is needed with the regular
1897 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1898 * However need a sync with accessing the vma as part of
1899 * mlx5_ib_disassociate_ucontext.
1900 * The close operation is usually called under mm->mmap_sem except when
1901 * process is exiting.
1902 * The exiting case is handled explicitly as part of
1903 * mlx5_ib_disassociate_ucontext.
1904 */
1905 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1906
1907 /* setting the vma context pointer to null in the mlx5_ib driver's
1908 * private data, to protect a race condition in
1909 * mlx5_ib_disassociate_ucontext().
1910 */
1911 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1912 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1913 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1914 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1915 kfree(mlx5_ib_vma_priv_data);
1916}
1917
1918static const struct vm_operations_struct mlx5_ib_vm_ops = {
1919 .open = mlx5_ib_vma_open,
1920 .close = mlx5_ib_vma_close
1921};
1922
1923static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1924 struct mlx5_ib_ucontext *ctx)
1925{
1926 struct mlx5_ib_vma_private_data *vma_prv;
1927 struct list_head *vma_head = &ctx->vma_private_list;
1928
1929 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1930 if (!vma_prv)
1931 return -ENOMEM;
1932
1933 vma_prv->vma = vma;
ad9a3668 1934 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1935 vma->vm_private_data = vma_prv;
1936 vma->vm_ops = &mlx5_ib_vm_ops;
1937
ad9a3668 1938 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1939 list_add(&vma_prv->list, vma_head);
ad9a3668 1940 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1941
1942 return 0;
1943}
1944
1945static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1946{
1947 int ret;
1948 struct vm_area_struct *vma;
1949 struct mlx5_ib_vma_private_data *vma_private, *n;
1950 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1951 struct task_struct *owning_process = NULL;
1952 struct mm_struct *owning_mm = NULL;
1953
1954 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1955 if (!owning_process)
1956 return;
1957
1958 owning_mm = get_task_mm(owning_process);
1959 if (!owning_mm) {
1960 pr_info("no mm, disassociate ucontext is pending task termination\n");
1961 while (1) {
1962 put_task_struct(owning_process);
1963 usleep_range(1000, 2000);
1964 owning_process = get_pid_task(ibcontext->tgid,
1965 PIDTYPE_PID);
1966 if (!owning_process ||
1967 owning_process->state == TASK_DEAD) {
1968 pr_info("disassociate ucontext done, task was terminated\n");
1969 /* in case task was dead need to release the
1970 * task struct.
1971 */
1972 if (owning_process)
1973 put_task_struct(owning_process);
1974 return;
1975 }
1976 }
1977 }
1978
1979 /* need to protect from a race on closing the vma as part of
1980 * mlx5_ib_vma_close.
1981 */
ecc7d83b 1982 down_write(&owning_mm->mmap_sem);
ad9a3668 1983 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1984 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1985 list) {
1986 vma = vma_private->vma;
1987 ret = zap_vma_ptes(vma, vma->vm_start,
1988 PAGE_SIZE);
1989 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1990 /* context going to be destroyed, should
1991 * not access ops any more.
1992 */
13776612 1993 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1994 vma->vm_ops = NULL;
1995 list_del(&vma_private->list);
1996 kfree(vma_private);
1997 }
ad9a3668 1998 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 1999 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 2000 mmput(owning_mm);
2001 put_task_struct(owning_process);
2002}
2003
37aa5c36
GL		 2004static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2005{
2006 switch (cmd) {
2007 case MLX5_IB_MMAP_WC_PAGE:
2008 return "WC";
2009 case MLX5_IB_MMAP_REGULAR_PAGE:
2010 return "best effort WC";
2011 case MLX5_IB_MMAP_NC_PAGE:
2012 return "NC";
2013 default:
2014 return NULL;
2015 }
2016}
2017
5c99eaec
FD		 2018static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2019 struct vm_area_struct *vma,
2020 struct mlx5_ib_ucontext *context)
2021{
2022 phys_addr_t pfn;
2023 int err;
2024
2025 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2026 return -EINVAL;
2027
2028 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2029 return -EOPNOTSUPP;
2030
2031 if (vma->vm_flags & VM_WRITE)
2032 return -EPERM;
2033
2034 if (!dev->mdev->clock_info_page)
2035 return -EOPNOTSUPP;
2036
2037 pfn = page_to_pfn(dev->mdev->clock_info_page);
2038 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2039 vma->vm_page_prot);
2040 if (err)
2041 return err;
2042
2043 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2044 vma->vm_start,
2045 (unsigned long long)pfn << PAGE_SHIFT);
2046
2047 return mlx5_ib_set_vma_data(vma, context);
2048}
2049
37aa5c36 2050static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2051 struct vm_area_struct *vma,
2052 struct mlx5_ib_ucontext *context)
37aa5c36 2053{
2f5ff264 2054 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2055 int err;
2056 unsigned long idx;
2057 phys_addr_t pfn, pa;
2058 pgprot_t prot;
4ed131d0
YH		 2059 u32 bfreg_dyn_idx = 0;
2060 u32 uar_index;
2061 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2062 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2063 bfregi->num_static_sys_pages;
b037c29a
EC		 2064
2065 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2066 return -EINVAL;
2067
4ed131d0
YH		 2068 if (dyn_uar)
2069 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2070 else
2071 idx = get_index(vma->vm_pgoff);
2072
2073 if (idx >= max_valid_idx) {
2074 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2075 idx, max_valid_idx);
b037c29a
EC		 2076 return -EINVAL;
2077 }
37aa5c36
GL		 2078
2079 switch (cmd) {
2080 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2081 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2082/* Some architectures don't support WC memory */
2083#if defined(CONFIG_X86)
2084 if (!pat_enabled())
2085 return -EPERM;
2086#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2087 return -EPERM;
2088#endif
2089 /* fall through */
2090 case MLX5_IB_MMAP_REGULAR_PAGE:
2091 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2092 prot = pgprot_writecombine(vma->vm_page_prot);
2093 break;
2094 case MLX5_IB_MMAP_NC_PAGE:
2095 prot = pgprot_noncached(vma->vm_page_prot);
2096 break;
2097 default:
2098 return -EINVAL;
2099 }
2100
4ed131d0
YH		 2101 if (dyn_uar) {
2102 int uars_per_page;
2103
2104 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2105 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2106 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2107 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2108 bfreg_dyn_idx, bfregi->total_num_bfregs);
2109 return -EINVAL;
2110 }
2111
2112 mutex_lock(&bfregi->lock);
2113 /* Fail if uar already allocated, first bfreg index of each
2114 * page holds its count.
2115 */
2116 if (bfregi->count[bfreg_dyn_idx]) {
2117 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2118 mutex_unlock(&bfregi->lock);
2119 return -EINVAL;
2120 }
2121
2122 bfregi->count[bfreg_dyn_idx]++;
2123 mutex_unlock(&bfregi->lock);
2124
2125 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2126 if (err) {
2127 mlx5_ib_warn(dev, "UAR alloc failed\n");
2128 goto free_bfreg;
2129 }
2130 } else {
2131 uar_index = bfregi->sys_pages[idx];
2132 }
2133
2134 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2135 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2136
2137 vma->vm_page_prot = prot;
2138 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2139 PAGE_SIZE, vma->vm_page_prot);
2140 if (err) {
2141 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2142 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
4ed131d0
YH		 2143 err = -EAGAIN;
2144 goto err;
37aa5c36
GL		 2145 }
2146
2147 pa = pfn << PAGE_SHIFT;
2148 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2149 vma->vm_start, &pa);
2150
4ed131d0
YH		 2151 err = mlx5_ib_set_vma_data(vma, context);
2152 if (err)
2153 goto err;
2154
2155 if (dyn_uar)
2156 bfregi->sys_pages[idx] = uar_index;
2157 return 0;
2158
2159err:
2160 if (!dyn_uar)
2161 return err;
2162
2163 mlx5_cmd_free_uar(dev->mdev, idx);
2164
2165free_bfreg:
2166 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2167
2168 return err;
37aa5c36
GL		 2169}
2170
e126ba97
EC		 2171static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2172{
2173 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2174 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2175 unsigned long command;
e126ba97
EC		 2176 phys_addr_t pfn;
2177
2178 command = get_command(vma->vm_pgoff);
2179 switch (command) {
37aa5c36
GL		 2180 case MLX5_IB_MMAP_WC_PAGE:
2181 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2182 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2183 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2184 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2185
2186 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2187 return -ENOSYS;
2188
d69e3bcf 2189 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2190 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2191 return -EINVAL;
2192
6cbac1e4 2193 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2194 return -EPERM;
2195
2196 /* Don't expose to user-space information it shouldn't have */
2197 if (PAGE_SIZE > 4096)
2198 return -EOPNOTSUPP;
2199
2200 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2201 pfn = (dev->mdev->iseg_base +
2202 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2203 PAGE_SHIFT;
2204 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2205 PAGE_SIZE, vma->vm_page_prot))
2206 return -EAGAIN;
2207
2208 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2209 vma->vm_start,
2210 (unsigned long long)pfn << PAGE_SHIFT);
2211 break;
5c99eaec
FD		 2212 case MLX5_IB_MMAP_CLOCK_INFO:
2213 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2214
e126ba97
EC		 2215 default:
2216 return -EINVAL;
2217 }
2218
2219 return 0;
2220}
2221
e126ba97
EC		 2222static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2223 struct ib_ucontext *context,
2224 struct ib_udata *udata)
2225{
2226 struct mlx5_ib_alloc_pd_resp resp;
2227 struct mlx5_ib_pd *pd;
2228 int err;
2229
2230 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2231 if (!pd)
2232 return ERR_PTR(-ENOMEM);
2233
9603b61d 2234 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2235 if (err) {
2236 kfree(pd);
2237 return ERR_PTR(err);
2238 }
2239
2240 if (context) {
2241 resp.pdn = pd->pdn;
2242 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2243 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2244 kfree(pd);
2245 return ERR_PTR(-EFAULT);
2246 }
e126ba97
EC		 2247 }
2248
2249 return &pd->ibpd;
2250}
2251
2252static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2253{
2254 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2255 struct mlx5_ib_pd *mpd = to_mpd(pd);
2256
9603b61d 2257 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2258 kfree(mpd);
2259
2260 return 0;
2261}
2262
466fa6d2
MG		 2263enum {
2264 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2265 MATCH_CRITERIA_ENABLE_MISC_BIT,
2266 MATCH_CRITERIA_ENABLE_INNER_BIT
2267};
2268
2269#define HEADER_IS_ZERO(match_criteria, headers) \
2270 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2271 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2272
466fa6d2 2273static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2274{
466fa6d2 2275 u8 match_criteria_enable;
038d2ef8 2276
466fa6d2
MG		 2277 match_criteria_enable =
2278 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2279 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2280 match_criteria_enable |=
2281 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2282 MATCH_CRITERIA_ENABLE_MISC_BIT;
2283 match_criteria_enable |=
2284 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2285 MATCH_CRITERIA_ENABLE_INNER_BIT;
2286
2287 return match_criteria_enable;
038d2ef8
MG		 2288}
2289
ca0d4753
MG		 2290static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2291{
2292 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2293 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2294}
2295
2d1e697e
MR		 2296static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2297 bool inner)
2298{
2299 if (inner) {
2300 MLX5_SET(fte_match_set_misc,
2301 misc_c, inner_ipv6_flow_label, mask);
2302 MLX5_SET(fte_match_set_misc,
2303 misc_v, inner_ipv6_flow_label, val);
2304 } else {
2305 MLX5_SET(fte_match_set_misc,
2306 misc_c, outer_ipv6_flow_label, mask);
2307 MLX5_SET(fte_match_set_misc,
2308 misc_v, outer_ipv6_flow_label, val);
2309 }
2310}
2311
ca0d4753
MG		 2312static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2313{
2314 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2315 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2316 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2317 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2318}
2319
c47ac6ae
MG		 2320#define LAST_ETH_FIELD vlan_tag
2321#define LAST_IB_FIELD sl
ca0d4753 2322#define LAST_IPV4_FIELD tos
466fa6d2 2323#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2324#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2325#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2326#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2327#define LAST_DROP_FIELD size
c47ac6ae
MG		 2328
2329/* Field is the last supported field */
2330#define FIELDS_NOT_SUPPORTED(filter, field)\
2331 memchr_inv((void *)&filter.field +\
2332 sizeof(filter.field), 0,\
2333 sizeof(filter) -\
2334 offsetof(typeof(filter), field) -\
2335 sizeof(filter.field))
2336
802c2125
AY		 2337static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2338 const struct ib_flow_attr *flow_attr,
2339 struct mlx5_flow_act *action)
2340{
2341 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2342
2343 switch (maction->ib_action.type) {
2344 case IB_FLOW_ACTION_ESP:
2345 /* Currently only AES_GCM keymat is supported by the driver */
2346 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2347 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2348 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2349 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2350 return 0;
2351 default:
2352 return -EOPNOTSUPP;
2353 }
2354}
2355
19cc7524
AL		 2356static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2357 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2358 const struct ib_flow_attr *flow_attr,
075572d4 2359 struct mlx5_flow_act *action)
038d2ef8 2360{
466fa6d2
MG		 2361 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2362 misc_parameters);
2363 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2364 misc_parameters);
2d1e697e
MR		 2365 void *headers_c;
2366 void *headers_v;
19cc7524 2367 int match_ipv;
802c2125 2368 int ret;
2d1e697e
MR		 2369
2370 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2371 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2372 inner_headers);
2373 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2374 inner_headers);
19cc7524
AL		 2375 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2376 ft_field_support.inner_ip_version);
2d1e697e
MR		 2377 } else {
2378 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2379 outer_headers);
2380 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2381 outer_headers);
19cc7524
AL		 2382 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2383 ft_field_support.outer_ip_version);
2d1e697e 2384 }
466fa6d2 2385
2d1e697e 2386 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2387 case IB_FLOW_SPEC_ETH:
c47ac6ae 2388 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2389 return -EOPNOTSUPP;
038d2ef8 2390
2d1e697e 2391 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2392 dmac_47_16),
2393 ib_spec->eth.mask.dst_mac);
2d1e697e 2394 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2395 dmac_47_16),
2396 ib_spec->eth.val.dst_mac);
2397
2d1e697e 2398 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2399 smac_47_16),
2400 ib_spec->eth.mask.src_mac);
2d1e697e 2401 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2402 smac_47_16),
2403 ib_spec->eth.val.src_mac);
2404
038d2ef8 2405 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2406 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2407 cvlan_tag, 1);
2d1e697e 2408 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2409 cvlan_tag, 1);
038d2ef8 2410
2d1e697e 2411 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2412 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2413 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2414 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2415
2d1e697e 2416 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2417 first_cfi,
2418 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2419 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2420 first_cfi,
2421 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2422
2d1e697e 2423 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2424 first_prio,
2425 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2426 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2427 first_prio,
2428 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2429 }
2d1e697e 2430 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2431 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2432 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2433 ethertype, ntohs(ib_spec->eth.val.ether_type));
2434 break;
2435 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2436 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2437 return -EOPNOTSUPP;
038d2ef8 2438
19cc7524
AL		 2439 if (match_ipv) {
2440 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2441 ip_version, 0xf);
2442 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2443 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2444 } else {
2445 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2446 ethertype, 0xffff);
2447 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2448 ethertype, ETH_P_IP);
2449 }
038d2ef8 2450
2d1e697e 2451 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2452 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2453 &ib_spec->ipv4.mask.src_ip,
2454 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2455 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2456 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2457 &ib_spec->ipv4.val.src_ip,
2458 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2459 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2460 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2461 &ib_spec->ipv4.mask.dst_ip,
2462 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2463 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2464 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2465 &ib_spec->ipv4.val.dst_ip,
2466 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2467
2d1e697e 2468 set_tos(headers_c, headers_v,
ca0d4753
MG		 2469 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2470
2d1e697e 2471 set_proto(headers_c, headers_v,
ca0d4753 2472 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2473 break;
026bae0c 2474 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2475 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2476 return -EOPNOTSUPP;
026bae0c 2477
19cc7524
AL		 2478 if (match_ipv) {
2479 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2480 ip_version, 0xf);
2481 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2482 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2483 } else {
2484 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2485 ethertype, 0xffff);
2486 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2487 ethertype, ETH_P_IPV6);
2488 }
026bae0c 2489
2d1e697e 2490 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2491 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2492 &ib_spec->ipv6.mask.src_ip,
2493 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2494 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2495 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2496 &ib_spec->ipv6.val.src_ip,
2497 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2498 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2499 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2500 &ib_spec->ipv6.mask.dst_ip,
2501 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2502 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2503 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2504 &ib_spec->ipv6.val.dst_ip,
2505 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2506
2d1e697e 2507 set_tos(headers_c, headers_v,
466fa6d2
MG		 2508 ib_spec->ipv6.mask.traffic_class,
2509 ib_spec->ipv6.val.traffic_class);
2510
2d1e697e 2511 set_proto(headers_c, headers_v,
466fa6d2
MG		 2512 ib_spec->ipv6.mask.next_hdr,
2513 ib_spec->ipv6.val.next_hdr);
2514
2d1e697e
MR		 2515 set_flow_label(misc_params_c, misc_params_v,
2516 ntohl(ib_spec->ipv6.mask.flow_label),
2517 ntohl(ib_spec->ipv6.val.flow_label),
2518 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2519 break;
2520 case IB_FLOW_SPEC_ESP:
2521 if (ib_spec->esp.mask.seq)
2522 return -EOPNOTSUPP;
2d1e697e 2523
802c2125
AY		 2524 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2525 ntohl(ib_spec->esp.mask.spi));
2526 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2527 ntohl(ib_spec->esp.val.spi));
026bae0c 2528 break;
038d2ef8 2529 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2530 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2531 LAST_TCP_UDP_FIELD))
1ffd3a26 2532 return -EOPNOTSUPP;
038d2ef8 2533
2d1e697e 2534 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2535 0xff);
2d1e697e 2536 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2537 IPPROTO_TCP);
2538
2d1e697e 2539 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2540 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2541 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2542 ntohs(ib_spec->tcp_udp.val.src_port));
2543
2d1e697e 2544 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2545 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2546 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2547 ntohs(ib_spec->tcp_udp.val.dst_port));
2548 break;
2549 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2550 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2551 LAST_TCP_UDP_FIELD))
1ffd3a26 2552 return -EOPNOTSUPP;
038d2ef8 2553
2d1e697e 2554 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2555 0xff);
2d1e697e 2556 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2557 IPPROTO_UDP);
2558
2d1e697e 2559 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2560 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2561 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2562 ntohs(ib_spec->tcp_udp.val.src_port));
2563
2d1e697e 2564 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2565 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2566 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2567 ntohs(ib_spec->tcp_udp.val.dst_port));
2568 break;
ffb30d8f
MR		 2569 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2570 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2571 LAST_TUNNEL_FIELD))
1ffd3a26 2572 return -EOPNOTSUPP;
ffb30d8f
MR		 2573
2574 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2575 ntohl(ib_spec->tunnel.mask.tunnel_id));
2576 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2577 ntohl(ib_spec->tunnel.val.tunnel_id));
2578 break;
2ac693f9
MR		 2579 case IB_FLOW_SPEC_ACTION_TAG:
2580 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2581 LAST_FLOW_TAG_FIELD))
2582 return -EOPNOTSUPP;
2583 if (ib_spec->flow_tag.tag_id >= BIT(24))
2584 return -EINVAL;
2585
075572d4 2586 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2587 action->has_flow_tag = true;
2ac693f9 2588 break;
a22ed86c
SS		 2589 case IB_FLOW_SPEC_ACTION_DROP:
2590 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2591 LAST_DROP_FIELD))
2592 return -EOPNOTSUPP;
075572d4 2593 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2594 break;
802c2125
AY		 2595 case IB_FLOW_SPEC_ACTION_HANDLE:
2596 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2597 if (ret)
2598 return ret;
2599 break;
038d2ef8
MG		 2600 default:
2601 return -EINVAL;
2602 }
2603
2604 return 0;
2605}
2606
2607/* If a flow could catch both multicast and unicast packets,
2608 * it won't fall into the multicast flow steering table and this rule
2609 * could steal other multicast packets.
2610 */
a550ddfc 2611static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2612{
81e30880 2613 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2614
2615 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2616 ib_attr->num_of_specs < 1)
2617 return false;
2618
81e30880
YH		 2619 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2620 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2621 struct ib_flow_spec_ipv4 *ipv4_spec;
2622
2623 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2624 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2625 return true;
2626
038d2ef8 2627 return false;
81e30880
YH		 2628 }
2629
2630 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2631 struct ib_flow_spec_eth *eth_spec;
2632
2633 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2634 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2635 is_multicast_ether_addr(eth_spec->val.dst_mac);
2636 }
038d2ef8 2637
81e30880 2638 return false;
038d2ef8
MG		 2639}
2640
802c2125
AY		 2641enum valid_spec {
2642 VALID_SPEC_INVALID,
2643 VALID_SPEC_VALID,
2644 VALID_SPEC_NA,
2645};
2646
2647static enum valid_spec
2648is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2649 const struct mlx5_flow_spec *spec,
2650 const struct mlx5_flow_act *flow_act,
2651 bool egress)
2652{
2653 const u32 *match_c = spec->match_criteria;
2654 bool is_crypto =
2655 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2656 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2657 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2658 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2659
2660 /*
2661 * Currently only crypto is supported in egress, when regular egress
2662 * rules would be supported, always return VALID_SPEC_NA.
2663 */
2664 if (!is_crypto)
2665 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2666
2667 return is_crypto && is_ipsec &&
2668 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2669 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2670}
2671
2672static bool is_valid_spec(struct mlx5_core_dev *mdev,
2673 const struct mlx5_flow_spec *spec,
2674 const struct mlx5_flow_act *flow_act,
2675 bool egress)
2676{
2677 /* We curretly only support ipsec egress flow */
2678 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2679}
2680
19cc7524
AL		 2681static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2682 const struct ib_flow_attr *flow_attr,
0f750966 2683 bool check_inner)
038d2ef8
MG		 2684{
2685 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2686 int match_ipv = check_inner ?
2687 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2688 ft_field_support.inner_ip_version) :
2689 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2690 ft_field_support.outer_ip_version);
0f750966
AL		 2691 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2692 bool ipv4_spec_valid, ipv6_spec_valid;
2693 unsigned int ip_spec_type = 0;
2694 bool has_ethertype = false;
038d2ef8 2695 unsigned int spec_index;
0f750966
AL		 2696 bool mask_valid = true;
2697 u16 eth_type = 0;
2698 bool type_valid;
038d2ef8
MG		 2699
2700 /* Validate that ethertype is correct */
2701 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2702 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2703 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2704 mask_valid = (ib_spec->eth.mask.ether_type ==
2705 htons(0xffff));
2706 has_ethertype = true;
2707 eth_type = ntohs(ib_spec->eth.val.ether_type);
2708 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2709 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2710 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2711 }
2712 ib_spec = (void *)ib_spec + ib_spec->size;
2713 }
0f750966
AL		 2714
2715 type_valid = (!has_ethertype) || (!ip_spec_type);
2716 if (!type_valid && mask_valid) {
2717 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2718 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2719 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2720 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2721
2722 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2723 (((eth_type == ETH_P_MPLS_UC) ||
2724 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2725 }
2726
2727 return type_valid;
2728}
2729
19cc7524
AL		 2730static bool is_valid_attr(struct mlx5_core_dev *mdev,
2731 const struct ib_flow_attr *flow_attr)
0f750966 2732{
19cc7524
AL		 2733 return is_valid_ethertype(mdev, flow_attr, false) &&
2734 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2735}
2736
2737static void put_flow_table(struct mlx5_ib_dev *dev,
2738 struct mlx5_ib_flow_prio *prio, bool ft_added)
2739{
2740 prio->refcount -= !!ft_added;
2741 if (!prio->refcount) {
2742 mlx5_destroy_flow_table(prio->flow_table);
2743 prio->flow_table = NULL;
2744 }
2745}
2746
2747static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2748{
2749 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2750 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2751 struct mlx5_ib_flow_handler,
2752 ibflow);
2753 struct mlx5_ib_flow_handler *iter, *tmp;
2754
9a4ca38d 2755 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2756
2757 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2758 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2759 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2760 list_del(&iter->list);
2761 kfree(iter);
2762 }
2763
74491de9 2764 mlx5_del_flow_rules(handler->rule);
5497adc6 2765 put_flow_table(dev, handler->prio, true);
9a4ca38d 2766 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 2767
2768 kfree(handler);
2769
2770 return 0;
2771}
2772
35d19011
MG		 2773static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2774{
2775 priority *= 2;
2776 if (!dont_trap)
2777 priority++;
2778 return priority;
2779}
2780
cc0e5d42
MG		 2781enum flow_table_type {
2782 MLX5_IB_FT_RX,
2783 MLX5_IB_FT_TX
2784};
2785
00b7c2ab
MG		 2786#define MLX5_FS_MAX_TYPES 6
2787#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2788static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2789 struct ib_flow_attr *flow_attr,
2790 enum flow_table_type ft_type)
038d2ef8 2791{
35d19011 2792 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2793 struct mlx5_flow_namespace *ns = NULL;
2794 struct mlx5_ib_flow_prio *prio;
2795 struct mlx5_flow_table *ft;
dac388ef 2796 int max_table_size;
038d2ef8
MG		 2797 int num_entries;
2798 int num_groups;
2799 int priority;
2800 int err = 0;
2801
dac388ef
MG		 2802 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2803 log_max_ft_size));
038d2ef8 2804 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
802c2125
AY		 2805 if (ft_type == MLX5_IB_FT_TX)
2806 priority = 0;
2807 else if (flow_is_multicast_only(flow_attr) &&
2808 !dont_trap)
038d2ef8
MG		 2809 priority = MLX5_IB_FLOW_MCAST_PRIO;
2810 else
35d19011
MG		 2811 priority = ib_prio_to_core_prio(flow_attr->priority,
2812 dont_trap);
038d2ef8 2813 ns = mlx5_get_flow_namespace(dev->mdev,
802c2125
AY		 2814 ft_type == MLX5_IB_FT_TX ?
2815 MLX5_FLOW_NAMESPACE_EGRESS :
038d2ef8
MG		 2816 MLX5_FLOW_NAMESPACE_BYPASS);
2817 num_entries = MLX5_FS_MAX_ENTRIES;
2818 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 2819 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 2820 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2821 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2822 ns = mlx5_get_flow_namespace(dev->mdev,
2823 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2824 build_leftovers_ft_param(&priority,
2825 &num_entries,
2826 &num_groups);
9a4ca38d 2827 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2828 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2829 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2830 allow_sniffer_and_nic_rx_shared_tir))
2831 return ERR_PTR(-ENOTSUPP);
2832
2833 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2834 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2835 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2836
9a4ca38d 2837 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 2838 priority = 0;
2839 num_entries = 1;
2840 num_groups = 1;
038d2ef8
MG		 2841 }
2842
2843 if (!ns)
2844 return ERR_PTR(-ENOTSUPP);
2845
dac388ef
MG		 2846 if (num_entries > max_table_size)
2847 return ERR_PTR(-ENOMEM);
2848
038d2ef8
MG		 2849 ft = prio->flow_table;
2850 if (!ft) {
2851 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2852 num_entries,
d63cd286 2853 num_groups,
c9f1b073 2854 0, 0);
038d2ef8
MG		 2855
2856 if (!IS_ERR(ft)) {
2857 prio->refcount = 0;
2858 prio->flow_table = ft;
2859 } else {
2860 err = PTR_ERR(ft);
2861 }
2862 }
2863
2864 return err ? ERR_PTR(err) : prio;
2865}
2866
a550ddfc
YH		 2867static void set_underlay_qp(struct mlx5_ib_dev *dev,
2868 struct mlx5_flow_spec *spec,
2869 u32 underlay_qpn)
2870{
2871 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2872 spec->match_criteria,
2873 misc_parameters);
2874 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2875 misc_parameters);
2876
2877 if (underlay_qpn &&
2878 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2879 ft_field_support.bth_dst_qp)) {
2880 MLX5_SET(fte_match_set_misc,
2881 misc_params_v, bth_dst_qp, underlay_qpn);
2882 MLX5_SET(fte_match_set_misc,
2883 misc_params_c, bth_dst_qp, 0xffffff);
2884 }
2885}
2886
2887static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2888 struct mlx5_ib_flow_prio *ft_prio,
2889 const struct ib_flow_attr *flow_attr,
2890 struct mlx5_flow_destination *dst,
2891 u32 underlay_qpn)
038d2ef8
MG		 2892{
2893 struct mlx5_flow_table *ft = ft_prio->flow_table;
2894 struct mlx5_ib_flow_handler *handler;
075572d4 2895 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 2896 struct mlx5_flow_spec *spec;
a22ed86c 2897 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2898 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2899 unsigned int spec_index;
038d2ef8 2900 int err = 0;
a22ed86c 2901 int dest_num = 1;
802c2125 2902 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 2903
19cc7524 2904 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2905 return ERR_PTR(-EINVAL);
2906
1b9a07ee 2907 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2908 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2909 if (!handler || !spec) {
038d2ef8
MG		 2910 err = -ENOMEM;
2911 goto free;
2912 }
2913
2914 INIT_LIST_HEAD(&handler->list);
2915
2916 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2917 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 2918 spec->match_value,
802c2125 2919 ib_flow, flow_attr, &flow_act);
038d2ef8
MG		 2920 if (err < 0)
2921 goto free;
2922
2923 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2924 }
2925
a550ddfc
YH		 2926 if (!flow_is_multicast_only(flow_attr))
2927 set_underlay_qp(dev, spec, underlay_qpn);
2928
018a94ee
MB		 2929 if (dev->rep) {
2930 void *misc;
2931
2932 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2933 misc_parameters);
2934 MLX5_SET(fte_match_set_misc, misc, source_port,
2935 dev->rep->vport);
2936 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2937 misc_parameters);
2938 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2939 }
2940
466fa6d2 2941 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 2942
2943 if (is_egress &&
2944 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
2945 err = -EINVAL;
2946 goto free;
2947 }
2948
075572d4 2949 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
a22ed86c
SS		 2950 rule_dst = NULL;
2951 dest_num = 0;
2952 } else {
802c2125
AY		 2953 if (is_egress)
2954 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
2955 else
2956 flow_act.action |=
2957 dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2958 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 2959 }
2ac693f9 2960
a9db0ecf 2961 if (flow_act.has_flow_tag &&
2ac693f9
MR		 2962 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2963 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2964 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 2965 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 2966 err = -EINVAL;
2967 goto free;
2968 }
74491de9 2969 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2970 &flow_act,
a22ed86c 2971 rule_dst, dest_num);
038d2ef8
MG		 2972
2973 if (IS_ERR(handler->rule)) {
2974 err = PTR_ERR(handler->rule);
2975 goto free;
2976 }
2977
d9d4980a 2978 ft_prio->refcount++;
5497adc6 2979 handler->prio = ft_prio;
038d2ef8
MG		 2980
2981 ft_prio->flow_table = ft;
2982free:
2983 if (err)
2984 kfree(handler);
c5bb1730 2985 kvfree(spec);
038d2ef8
MG		 2986 return err ? ERR_PTR(err) : handler;
2987}
2988
a550ddfc
YH		 2989static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2990 struct mlx5_ib_flow_prio *ft_prio,
2991 const struct ib_flow_attr *flow_attr,
2992 struct mlx5_flow_destination *dst)
2993{
2994 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2995}
2996
35d19011
MG		 2997static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2998 struct mlx5_ib_flow_prio *ft_prio,
2999 struct ib_flow_attr *flow_attr,
3000 struct mlx5_flow_destination *dst)
3001{
3002 struct mlx5_ib_flow_handler *handler_dst = NULL;
3003 struct mlx5_ib_flow_handler *handler = NULL;
3004
3005 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3006 if (!IS_ERR(handler)) {
3007 handler_dst = create_flow_rule(dev, ft_prio,
3008 flow_attr, dst);
3009 if (IS_ERR(handler_dst)) {
74491de9 3010 mlx5_del_flow_rules(handler->rule);
d9d4980a 3011 ft_prio->refcount--;
35d19011
MG		 3012 kfree(handler);
3013 handler = handler_dst;
3014 } else {
3015 list_add(&handler_dst->list, &handler->list);
3016 }
3017 }
3018
3019 return handler;
3020}
038d2ef8
MG		 3021enum {
3022 LEFTOVERS_MC,
3023 LEFTOVERS_UC,
3024};
3025
3026static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3027 struct mlx5_ib_flow_prio *ft_prio,
3028 struct ib_flow_attr *flow_attr,
3029 struct mlx5_flow_destination *dst)
3030{
3031 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3032 struct mlx5_ib_flow_handler *handler = NULL;
3033
3034 static struct {
3035 struct ib_flow_attr flow_attr;
3036 struct ib_flow_spec_eth eth_flow;
3037 } leftovers_specs[] = {
3038 [LEFTOVERS_MC] = {
3039 .flow_attr = {
3040 .num_of_specs = 1,
3041 .size = sizeof(leftovers_specs[0])
3042 },
3043 .eth_flow = {
3044 .type = IB_FLOW_SPEC_ETH,
3045 .size = sizeof(struct ib_flow_spec_eth),
3046 .mask = {.dst_mac = {0x1} },
3047 .val = {.dst_mac = {0x1} }
3048 }
3049 },
3050 [LEFTOVERS_UC] = {
3051 .flow_attr = {
3052 .num_of_specs = 1,
3053 .size = sizeof(leftovers_specs[0])
3054 },
3055 .eth_flow = {
3056 .type = IB_FLOW_SPEC_ETH,
3057 .size = sizeof(struct ib_flow_spec_eth),
3058 .mask = {.dst_mac = {0x1} },
3059 .val = {.dst_mac = {} }
3060 }
3061 }
3062 };
3063
3064 handler = create_flow_rule(dev, ft_prio,
3065 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3066 dst);
3067 if (!IS_ERR(handler) &&
3068 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3069 handler_ucast = create_flow_rule(dev, ft_prio,
3070 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3071 dst);
3072 if (IS_ERR(handler_ucast)) {
74491de9 3073 mlx5_del_flow_rules(handler->rule);
d9d4980a 3074 ft_prio->refcount--;
038d2ef8
MG		 3075 kfree(handler);
3076 handler = handler_ucast;
3077 } else {
3078 list_add(&handler_ucast->list, &handler->list);
3079 }
3080 }
3081
3082 return handler;
3083}
3084
cc0e5d42
MG		 3085static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3086 struct mlx5_ib_flow_prio *ft_rx,
3087 struct mlx5_ib_flow_prio *ft_tx,
3088 struct mlx5_flow_destination *dst)
3089{
3090 struct mlx5_ib_flow_handler *handler_rx;
3091 struct mlx5_ib_flow_handler *handler_tx;
3092 int err;
3093 static const struct ib_flow_attr flow_attr = {
3094 .num_of_specs = 0,
3095 .size = sizeof(flow_attr)
3096 };
3097
3098 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3099 if (IS_ERR(handler_rx)) {
3100 err = PTR_ERR(handler_rx);
3101 goto err;
3102 }
3103
3104 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3105 if (IS_ERR(handler_tx)) {
3106 err = PTR_ERR(handler_tx);
3107 goto err_tx;
3108 }
3109
3110 list_add(&handler_tx->list, &handler_rx->list);
3111
3112 return handler_rx;
3113
3114err_tx:
74491de9 3115 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3116 ft_rx->refcount--;
3117 kfree(handler_rx);
3118err:
3119 return ERR_PTR(err);
3120}
3121
038d2ef8
MG		 3122static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3123 struct ib_flow_attr *flow_attr,
3124 int domain)
3125{
3126 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3127 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3128 struct mlx5_ib_flow_handler *handler = NULL;
3129 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3130 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3131 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3132 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3133 int err;
a550ddfc 3134 int underlay_qpn;
038d2ef8
MG		 3135
3136 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 3137 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 3138
3139 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3140 flow_attr->port > dev->num_ports ||
802c2125
AY		 3141 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3142 IB_FLOW_ATTR_FLAGS_EGRESS)))
3143 return ERR_PTR(-EINVAL);
3144
3145 if (is_egress &&
3146 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3147 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
038d2ef8
MG		 3148 return ERR_PTR(-EINVAL);
3149
3150 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3151 if (!dst)
3152 return ERR_PTR(-ENOMEM);
3153
9a4ca38d 3154 mutex_lock(&dev->flow_db->lock);
038d2ef8 3155
802c2125
AY		 3156 ft_prio = get_flow_table(dev, flow_attr,
3157 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3158 if (IS_ERR(ft_prio)) {
3159 err = PTR_ERR(ft_prio);
3160 goto unlock;
3161 }
cc0e5d42
MG		 3162 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3163 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3164 if (IS_ERR(ft_prio_tx)) {
3165 err = PTR_ERR(ft_prio_tx);
3166 ft_prio_tx = NULL;
3167 goto destroy_ft;
3168 }
3169 }
038d2ef8 3170
802c2125
AY		 3171 if (is_egress) {
3172 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3173 } else {
3174 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3175 if (mqp->flags & MLX5_IB_QP_RSS)
3176 dst->tir_num = mqp->rss_qp.tirn;
3177 else
3178 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3179 }
038d2ef8
MG		 3180
3181 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3182 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3183 handler = create_dont_trap_rule(dev, ft_prio,
3184 flow_attr, dst);
3185 } else {
a550ddfc
YH		 3186 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3187 mqp->underlay_qpn : 0;
3188 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3189 dst, underlay_qpn);
35d19011 3190 }
038d2ef8
MG		 3191 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3192 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3193 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3194 dst);
cc0e5d42
MG		 3195 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3196 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3197 } else {
3198 err = -EINVAL;
3199 goto destroy_ft;
3200 }
3201
3202 if (IS_ERR(handler)) {
3203 err = PTR_ERR(handler);
3204 handler = NULL;
3205 goto destroy_ft;
3206 }
3207
9a4ca38d 3208 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3209 kfree(dst);
3210
3211 return &handler->ibflow;
3212
3213destroy_ft:
3214 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3215 if (ft_prio_tx)
3216 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3217unlock:
9a4ca38d 3218 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3219 kfree(dst);
3220 kfree(handler);
3221 return ERR_PTR(err);
3222}
3223
c6475a0b
AY		 3224static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3225{
3226 u32 flags = 0;
3227
3228 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3229 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3230
3231 return flags;
3232}
3233
3234#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3235static struct ib_flow_action *
3236mlx5_ib_create_flow_action_esp(struct ib_device *device,
3237 const struct ib_flow_action_attrs_esp *attr,
3238 struct uverbs_attr_bundle *attrs)
3239{
3240 struct mlx5_ib_dev *mdev = to_mdev(device);
3241 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3242 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3243 struct mlx5_ib_flow_action *action;
3244 u64 action_flags;
3245 u64 flags;
3246 int err = 0;
3247
3248 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3249 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3250 return ERR_PTR(-EFAULT);
3251
3252 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3253 return ERR_PTR(-EOPNOTSUPP);
3254
3255 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3256
3257 /* We current only support a subset of the standard features. Only a
3258 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3259 * (with overlap). Full offload mode isn't supported.
3260 */
3261 if (!attr->keymat || attr->replay || attr->encap ||
3262 attr->spi || attr->seq || attr->tfc_pad ||
3263 attr->hard_limit_pkts ||
3264 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3265 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3266 return ERR_PTR(-EOPNOTSUPP);
3267
3268 if (attr->keymat->protocol !=
3269 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3270 return ERR_PTR(-EOPNOTSUPP);
3271
3272 aes_gcm = &attr->keymat->keymat.aes_gcm;
3273
3274 if (aes_gcm->icv_len != 16 ||
3275 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3276 return ERR_PTR(-EOPNOTSUPP);
3277
3278 action = kmalloc(sizeof(*action), GFP_KERNEL);
3279 if (!action)
3280 return ERR_PTR(-ENOMEM);
3281
3282 action->esp_aes_gcm.ib_flags = attr->flags;
3283 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3284 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3285 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3286 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3287 sizeof(accel_attrs.keymat.aes_gcm.salt));
3288 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3289 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3290 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3291 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3292 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3293
3294 accel_attrs.esn = attr->esn;
3295 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3296 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3297 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3298 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3299
3300 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3301 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3302
3303 action->esp_aes_gcm.ctx =
3304 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3305 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3306 err = PTR_ERR(action->esp_aes_gcm.ctx);
3307 goto err_parse;
3308 }
3309
3310 action->esp_aes_gcm.ib_flags = attr->flags;
3311
3312 return &action->ib_action;
3313
3314err_parse:
3315 kfree(action);
3316 return ERR_PTR(err);
3317}
3318
349705c1
MB		 3319static int
3320mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3321 const struct ib_flow_action_attrs_esp *attr,
3322 struct uverbs_attr_bundle *attrs)
3323{
3324 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3325 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3326 int err = 0;
3327
3328 if (attr->keymat || attr->replay || attr->encap ||
3329 attr->spi || attr->seq || attr->tfc_pad ||
3330 attr->hard_limit_pkts ||
3331 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3332 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3333 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3334 return -EOPNOTSUPP;
3335
3336 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3337 * be modified.
3338 */
3339 if (!(maction->esp_aes_gcm.ib_flags &
3340 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3341 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3342 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3343 return -EINVAL;
3344
3345 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3346 sizeof(accel_attrs));
3347
3348 accel_attrs.esn = attr->esn;
3349 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3350 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3351 else
3352 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3353
3354 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3355 &accel_attrs);
3356 if (err)
3357 return err;
3358
3359 maction->esp_aes_gcm.ib_flags &=
3360 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3361 maction->esp_aes_gcm.ib_flags |=
3362 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3363
3364 return 0;
3365}
3366
c6475a0b
AY		 3367static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3368{
3369 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3370
3371 switch (action->type) {
3372 case IB_FLOW_ACTION_ESP:
3373 /*
3374 * We only support aes_gcm by now, so we implicitly know this is
3375 * the underline crypto.
3376 */
3377 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3378 break;
3379 default:
3380 WARN_ON(true);
3381 break;
3382 }
3383
3384 kfree(maction);
3385 return 0;
3386}
3387
e126ba97
EC		 3388static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3389{
3390 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 3391 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 3392 int err;
3393
81e30880
YH		 3394 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3395 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3396 return -EOPNOTSUPP;
3397 }
3398
9603b61d 3399 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3400 if (err)
3401 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3402 ibqp->qp_num, gid->raw);
3403
3404 return err;
3405}
3406
3407static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3408{
3409 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3410 int err;
3411
9603b61d 3412 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3413 if (err)
3414 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3415 ibqp->qp_num, gid->raw);
3416
3417 return err;
3418}
3419
3420static int init_node_data(struct mlx5_ib_dev *dev)
3421{
1b5daf11 3422 int err;
e126ba97 3423
1b5daf11 3424 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 3425 if (err)
1b5daf11 3426 return err;
e126ba97 3427
1b5daf11 3428 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 3429
1b5daf11 3430 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 3431}
3432
3433static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3434 char *buf)
3435{
3436 struct mlx5_ib_dev *dev =
3437 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3438
9603b61d 3439 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 3440}
3441
3442static ssize_t show_reg_pages(struct device *device,
3443 struct device_attribute *attr, char *buf)
3444{
3445 struct mlx5_ib_dev *dev =
3446 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3447
6aec21f6 3448 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3449}
3450
3451static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3452 char *buf)
3453{
3454 struct mlx5_ib_dev *dev =
3455 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3456 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3457}
3458
e126ba97
EC		 3459static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3460 char *buf)
3461{
3462 struct mlx5_ib_dev *dev =
3463 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3464 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3465}
3466
3467static ssize_t show_board(struct device *device, struct device_attribute *attr,
3468 char *buf)
3469{
3470 struct mlx5_ib_dev *dev =
3471 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3472 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3473 dev->mdev->board_id);
e126ba97
EC		 3474}
3475
3476static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3477static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3478static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3479static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3480static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3481
3482static struct device_attribute *mlx5_class_attributes[] = {
3483 &dev_attr_hw_rev,
e126ba97
EC		 3484 &dev_attr_hca_type,
3485 &dev_attr_board_id,
3486 &dev_attr_fw_pages,
3487 &dev_attr_reg_pages,
3488};
3489
7722f47e
HE		 3490static void pkey_change_handler(struct work_struct *work)
3491{
3492 struct mlx5_ib_port_resources *ports =
3493 container_of(work, struct mlx5_ib_port_resources,
3494 pkey_change_work);
3495
3496 mutex_lock(&ports->devr->mutex);
3497 mlx5_ib_gsi_pkey_change(ports->gsi);
3498 mutex_unlock(&ports->devr->mutex);
3499}
3500
89ea94a7
MG		 3501static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3502{
3503 struct mlx5_ib_qp *mqp;
3504 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3505 struct mlx5_core_cq *mcq;
3506 struct list_head cq_armed_list;
3507 unsigned long flags_qp;
3508 unsigned long flags_cq;
3509 unsigned long flags;
3510
3511 INIT_LIST_HEAD(&cq_armed_list);
3512
3513 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3514 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3515 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3516 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3517 if (mqp->sq.tail != mqp->sq.head) {
3518 send_mcq = to_mcq(mqp->ibqp.send_cq);
3519 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3520 if (send_mcq->mcq.comp &&
3521 mqp->ibqp.send_cq->comp_handler) {
3522 if (!send_mcq->mcq.reset_notify_added) {
3523 send_mcq->mcq.reset_notify_added = 1;
3524 list_add_tail(&send_mcq->mcq.reset_notify,
3525 &cq_armed_list);
3526 }
3527 }
3528 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3529 }
3530 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3531 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3532 /* no handling is needed for SRQ */
3533 if (!mqp->ibqp.srq) {
3534 if (mqp->rq.tail != mqp->rq.head) {
3535 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3536 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3537 if (recv_mcq->mcq.comp &&
3538 mqp->ibqp.recv_cq->comp_handler) {
3539 if (!recv_mcq->mcq.reset_notify_added) {
3540 recv_mcq->mcq.reset_notify_added = 1;
3541 list_add_tail(&recv_mcq->mcq.reset_notify,
3542 &cq_armed_list);
3543 }
3544 }
3545 spin_unlock_irqrestore(&recv_mcq->lock,
3546 flags_cq);
3547 }
3548 }
3549 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3550 }
3551 /*At that point all inflight post send were put to be executed as of we
3552 * lock/unlock above locks Now need to arm all involved CQs.
3553 */
3554 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3555 mcq->comp(mcq);
3556 }
3557 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3558}
3559
03404e8a
MG		 3560static void delay_drop_handler(struct work_struct *work)
3561{
3562 int err;
3563 struct mlx5_ib_delay_drop *delay_drop =
3564 container_of(work, struct mlx5_ib_delay_drop,
3565 delay_drop_work);
3566
fe248c3a
MG		 3567 atomic_inc(&delay_drop->events_cnt);
3568
03404e8a
MG		 3569 mutex_lock(&delay_drop->lock);
3570 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3571 delay_drop->timeout);
3572 if (err) {
3573 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3574 delay_drop->timeout);
3575 delay_drop->activate = false;
3576 }
3577 mutex_unlock(&delay_drop->lock);
3578}
3579
d69a24e0 3580static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 3581{
d69a24e0
DJ		 3582 struct mlx5_ib_event_work *work =
3583 container_of(_work, struct mlx5_ib_event_work, work);
3584 struct mlx5_ib_dev *ibdev;
e126ba97 3585 struct ib_event ibev;
dbaaff2a 3586 bool fatal = false;
aba46213 3587 u8 port = (u8)work->param;
e126ba97 3588
d69a24e0
DJ		 3589 if (mlx5_core_is_mp_slave(work->dev)) {
3590 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3591 if (!ibdev)
3592 goto out;
3593 } else {
3594 ibdev = work->context;
3595 }
3596
3597 switch (work->event) {
e126ba97 3598 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 3599 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 3600 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 3601 fatal = true;
e126ba97
EC		 3602 break;
3603
3604 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 3605 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 3606 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 3607 /* In RoCE, port up/down events are handled in
3608 * mlx5_netdev_event().
3609 */
3610 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3611 IB_LINK_LAYER_ETHERNET)
d69a24e0 3612 goto out;
5ec8c83e 3613
d69a24e0 3614 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 3615 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 3616 break;
3617
e126ba97
EC		 3618 case MLX5_DEV_EVENT_LID_CHANGE:
3619 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 3620 break;
3621
3622 case MLX5_DEV_EVENT_PKEY_CHANGE:
3623 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 3624 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 3625 break;
3626
3627 case MLX5_DEV_EVENT_GUID_CHANGE:
3628 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 3629 break;
3630
3631 case MLX5_DEV_EVENT_CLIENT_REREG:
3632 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 3633 break;
03404e8a
MG		 3634 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3635 schedule_work(&ibdev->delay_drop.delay_drop_work);
3636 goto out;
bdc37924 3637 default:
03404e8a 3638 goto out;
e126ba97
EC		 3639 }
3640
3641 ibev.device = &ibdev->ib_dev;
3642 ibev.element.port_num = port;
3643
aba46213 3644 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 3645 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 3646 goto out;
a0c84c32
EC		 3647 }
3648
e126ba97
EC		 3649 if (ibdev->ib_active)
3650 ib_dispatch_event(&ibev);
dbaaff2a
EC		 3651
3652 if (fatal)
3653 ibdev->ib_active = false;
03404e8a 3654out:
d69a24e0
DJ		 3655 kfree(work);
3656}
3657
3658static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3659 enum mlx5_dev_event event, unsigned long param)
3660{
3661 struct mlx5_ib_event_work *work;
3662
3663 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 3664 if (!work)
d69a24e0 3665 return;
d69a24e0 3666
10bea9c8
LR		 3667 INIT_WORK(&work->work, mlx5_ib_handle_event);
3668 work->dev = dev;
3669 work->param = param;
3670 work->context = context;
3671 work->event = event;
3672
3673 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 3674}
3675
c43f1112
MG		 3676static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3677{
3678 struct mlx5_hca_vport_context vport_ctx;
3679 int err;
3680 int port;
3681
508562d6 3682 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 3683 dev->mdev->port_caps[port - 1].has_smi = false;
3684 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3685 MLX5_CAP_PORT_TYPE_IB) {
3686 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3687 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3688 port, 0,
3689 &vport_ctx);
3690 if (err) {
3691 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3692 port, err);
3693 return err;
3694 }
3695 dev->mdev->port_caps[port - 1].has_smi =
3696 vport_ctx.has_smi;
3697 } else {
3698 dev->mdev->port_caps[port - 1].has_smi = true;
3699 }
3700 }
3701 }
3702 return 0;
3703}
3704
e126ba97
EC		 3705static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3706{
3707 int port;
3708
508562d6 3709 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 3710 mlx5_query_ext_port_caps(dev, port);
3711}
3712
32f69e4b 3713static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 3714{
3715 struct ib_device_attr *dprops = NULL;
3716 struct ib_port_attr *pprops = NULL;
f614fc15 3717 int err = -ENOMEM;
2528e33e 3718 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3719
3720 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3721 if (!pprops)
3722 goto out;
3723
3724 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3725 if (!dprops)
3726 goto out;
3727
c43f1112
MG		 3728 err = set_has_smi_cap(dev);
3729 if (err)
3730 goto out;
3731
2528e33e 3732 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3733 if (err) {
3734 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3735 goto out;
3736 }
3737
32f69e4b
DJ		 3738 memset(pprops, 0, sizeof(*pprops));
3739 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3740 if (err) {
3741 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3742 port, err);
3743 goto out;
e126ba97
EC		 3744 }
3745
32f69e4b
DJ		 3746 dev->mdev->port_caps[port - 1].pkey_table_len =
3747 dprops->max_pkeys;
3748 dev->mdev->port_caps[port - 1].gid_table_len =
3749 pprops->gid_tbl_len;
3750 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3751 port, dprops->max_pkeys, pprops->gid_tbl_len);
3752
e126ba97
EC		 3753out:
3754 kfree(pprops);
3755 kfree(dprops);
3756
3757 return err;
3758}
3759
3760static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3761{
3762 int err;
3763
3764 err = mlx5_mr_cache_cleanup(dev);
3765 if (err)
3766 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3767
3768 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3769 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3770 ib_dealloc_pd(dev->umrc.pd);
3771}
3772
3773enum {
3774 MAX_UMR_WR = 128,
3775};
3776
3777static int create_umr_res(struct mlx5_ib_dev *dev)
3778{
3779 struct ib_qp_init_attr *init_attr = NULL;
3780 struct ib_qp_attr *attr = NULL;
3781 struct ib_pd *pd;
3782 struct ib_cq *cq;
3783 struct ib_qp *qp;
e126ba97
EC		 3784 int ret;
3785
3786 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3787 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3788 if (!attr || !init_attr) {
3789 ret = -ENOMEM;
3790 goto error_0;
3791 }
3792
ed082d36 3793 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3794 if (IS_ERR(pd)) {
3795 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3796 ret = PTR_ERR(pd);
3797 goto error_0;
3798 }
3799
add08d76 3800 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3801 if (IS_ERR(cq)) {
3802 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3803 ret = PTR_ERR(cq);
3804 goto error_2;
3805 }
e126ba97
EC		 3806
3807 init_attr->send_cq = cq;
3808 init_attr->recv_cq = cq;
3809 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3810 init_attr->cap.max_send_wr = MAX_UMR_WR;
3811 init_attr->cap.max_send_sge = 1;
3812 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3813 init_attr->port_num = 1;
3814 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3815 if (IS_ERR(qp)) {
3816 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3817 ret = PTR_ERR(qp);
3818 goto error_3;
3819 }
3820 qp->device = &dev->ib_dev;
3821 qp->real_qp = qp;
3822 qp->uobject = NULL;
3823 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3824 qp->send_cq = init_attr->send_cq;
3825 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3826
3827 attr->qp_state = IB_QPS_INIT;
3828 attr->port_num = 1;
3829 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3830 IB_QP_PORT, NULL);
3831 if (ret) {
3832 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3833 goto error_4;
3834 }
3835
3836 memset(attr, 0, sizeof(*attr));
3837 attr->qp_state = IB_QPS_RTR;
3838 attr->path_mtu = IB_MTU_256;
3839
3840 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3841 if (ret) {
3842 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3843 goto error_4;
3844 }
3845
3846 memset(attr, 0, sizeof(*attr));
3847 attr->qp_state = IB_QPS_RTS;
3848 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3849 if (ret) {
3850 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3851 goto error_4;
3852 }
3853
3854 dev->umrc.qp = qp;
3855 dev->umrc.cq = cq;
e126ba97
EC		 3856 dev->umrc.pd = pd;
3857
3858 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3859 ret = mlx5_mr_cache_init(dev);
3860 if (ret) {
3861 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3862 goto error_4;
3863 }
3864
3865 kfree(attr);
3866 kfree(init_attr);
3867
3868 return 0;
3869
3870error_4:
3871 mlx5_ib_destroy_qp(qp);
3872
3873error_3:
add08d76 3874 ib_free_cq(cq);
e126ba97
EC		 3875
3876error_2:
e126ba97
EC		 3877 ib_dealloc_pd(pd);
3878
3879error_0:
3880 kfree(attr);
3881 kfree(init_attr);
3882 return ret;
3883}
3884
6e8484c5
MG		 3885static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3886{
3887 switch (umr_fence_cap) {
3888 case MLX5_CAP_UMR_FENCE_NONE:
3889 return MLX5_FENCE_MODE_NONE;
3890 case MLX5_CAP_UMR_FENCE_SMALL:
3891 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3892 default:
3893 return MLX5_FENCE_MODE_STRONG_ORDERING;
3894 }
3895}
3896
e126ba97
EC		 3897static int create_dev_resources(struct mlx5_ib_resources *devr)
3898{
3899 struct ib_srq_init_attr attr;
3900 struct mlx5_ib_dev *dev;
bcf4c1ea 3901 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3902 int port;
e126ba97
EC		 3903 int ret = 0;
3904
3905 dev = container_of(devr, struct mlx5_ib_dev, devr);
3906
d16e91da
HE		 3907 mutex_init(&devr->mutex);
3908
e126ba97
EC		 3909 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3910 if (IS_ERR(devr->p0)) {
3911 ret = PTR_ERR(devr->p0);
3912 goto error0;
3913 }
3914 devr->p0->device = &dev->ib_dev;
3915 devr->p0->uobject = NULL;
3916 atomic_set(&devr->p0->usecnt, 0);
3917
bcf4c1ea 3918 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3919 if (IS_ERR(devr->c0)) {
3920 ret = PTR_ERR(devr->c0);
3921 goto error1;
3922 }
3923 devr->c0->device = &dev->ib_dev;
3924 devr->c0->uobject = NULL;
3925 devr->c0->comp_handler = NULL;
3926 devr->c0->event_handler = NULL;
3927 devr->c0->cq_context = NULL;
3928 atomic_set(&devr->c0->usecnt, 0);
3929
3930 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3931 if (IS_ERR(devr->x0)) {
3932 ret = PTR_ERR(devr->x0);
3933 goto error2;
3934 }
3935 devr->x0->device = &dev->ib_dev;
3936 devr->x0->inode = NULL;
3937 atomic_set(&devr->x0->usecnt, 0);
3938 mutex_init(&devr->x0->tgt_qp_mutex);
3939 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3940
3941 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3942 if (IS_ERR(devr->x1)) {
3943 ret = PTR_ERR(devr->x1);
3944 goto error3;
3945 }
3946 devr->x1->device = &dev->ib_dev;
3947 devr->x1->inode = NULL;
3948 atomic_set(&devr->x1->usecnt, 0);
3949 mutex_init(&devr->x1->tgt_qp_mutex);
3950 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3951
3952 memset(&attr, 0, sizeof(attr));
3953 attr.attr.max_sge = 1;
3954 attr.attr.max_wr = 1;
3955 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3956 attr.ext.cq = devr->c0;
e126ba97
EC		 3957 attr.ext.xrc.xrcd = devr->x0;
3958
3959 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3960 if (IS_ERR(devr->s0)) {
3961 ret = PTR_ERR(devr->s0);
3962 goto error4;
3963 }
3964 devr->s0->device = &dev->ib_dev;
3965 devr->s0->pd = devr->p0;
3966 devr->s0->uobject = NULL;
3967 devr->s0->event_handler = NULL;
3968 devr->s0->srq_context = NULL;
3969 devr->s0->srq_type = IB_SRQT_XRC;
3970 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3971 devr->s0->ext.cq = devr->c0;
e126ba97 3972 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3973 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3974 atomic_inc(&devr->p0->usecnt);
3975 atomic_set(&devr->s0->usecnt, 0);
3976
4aa17b28
HA		 3977 memset(&attr, 0, sizeof(attr));
3978 attr.attr.max_sge = 1;
3979 attr.attr.max_wr = 1;
3980 attr.srq_type = IB_SRQT_BASIC;
3981 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3982 if (IS_ERR(devr->s1)) {
3983 ret = PTR_ERR(devr->s1);
3984 goto error5;
3985 }
3986 devr->s1->device = &dev->ib_dev;
3987 devr->s1->pd = devr->p0;
3988 devr->s1->uobject = NULL;
3989 devr->s1->event_handler = NULL;
3990 devr->s1->srq_context = NULL;
3991 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3992 devr->s1->ext.cq = devr->c0;
4aa17b28 3993 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3994 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3995
7722f47e
HE		 3996 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3997 INIT_WORK(&devr->ports[port].pkey_change_work,
3998 pkey_change_handler);
3999 devr->ports[port].devr = devr;
4000 }
4001
e126ba97
EC		 4002 return 0;
4003
4aa17b28
HA		 4004error5:
4005 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4006error4:
4007 mlx5_ib_dealloc_xrcd(devr->x1);
4008error3:
4009 mlx5_ib_dealloc_xrcd(devr->x0);
4010error2:
4011 mlx5_ib_destroy_cq(devr->c0);
4012error1:
4013 mlx5_ib_dealloc_pd(devr->p0);
4014error0:
4015 return ret;
4016}
4017
4018static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4019{
7722f47e
HE		 4020 struct mlx5_ib_dev *dev =
4021 container_of(devr, struct mlx5_ib_dev, devr);
4022 int port;
4023
4aa17b28 4024 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4025 mlx5_ib_destroy_srq(devr->s0);
4026 mlx5_ib_dealloc_xrcd(devr->x0);
4027 mlx5_ib_dealloc_xrcd(devr->x1);
4028 mlx5_ib_destroy_cq(devr->c0);
4029 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4030
4031 /* Make sure no change P_Key work items are still executing */
4032 for (port = 0; port < dev->num_ports; ++port)
4033 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4034}
4035
e53505a8
AS		 4036static u32 get_core_cap_flags(struct ib_device *ibdev)
4037{
4038 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4039 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4040 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4041 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4042 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4043 u32 ret = 0;
4044
4045 if (ll == IB_LINK_LAYER_INFINIBAND)
4046 return RDMA_CORE_PORT_IBA_IB;
4047
85c7c014
DJ		 4048 if (raw_support)
4049 ret = RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4050
e53505a8 4051 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4052 return ret;
e53505a8
AS		 4053
4054 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4055 return ret;
e53505a8
AS		 4056
4057 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4058 ret |= RDMA_CORE_PORT_IBA_ROCE;
4059
4060 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4061 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4062
4063 return ret;
4064}
4065
7738613e
IW		 4066static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4067 struct ib_port_immutable *immutable)
4068{
4069 struct ib_port_attr attr;
ca5b91d6
OG		 4070 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4071 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 4072 int err;
4073
c4550c63
OG		 4074 immutable->core_cap_flags = get_core_cap_flags(ibdev);
4075
4076 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4077 if (err)
4078 return err;
4079
4080 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4081 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 4082 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 4083 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4084 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4085
4086 return 0;
4087}
4088
8e6efa3a
MB		 4089static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4090 struct ib_port_immutable *immutable)
4091{
4092 struct ib_port_attr attr;
4093 int err;
4094
4095 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4096
4097 err = ib_query_port(ibdev, port_num, &attr);
4098 if (err)
4099 return err;
4100
4101 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4102 immutable->gid_tbl_len = attr.gid_tbl_len;
4103 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4104
4105 return 0;
4106}
4107
9abb0d1b 4108static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4109{
4110 struct mlx5_ib_dev *dev =
4111 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4112 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4113 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4114 fw_rev_sub(dev->mdev));
c7342823
IW		 4115}
4116
45f95acd 4117static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4118{
4119 struct mlx5_core_dev *mdev = dev->mdev;
4120 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4121 MLX5_FLOW_NAMESPACE_LAG);
4122 struct mlx5_flow_table *ft;
4123 int err;
4124
4125 if (!ns || !mlx5_lag_is_active(mdev))
4126 return 0;
4127
4128 err = mlx5_cmd_create_vport_lag(mdev);
4129 if (err)
4130 return err;
4131
4132 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4133 if (IS_ERR(ft)) {
4134 err = PTR_ERR(ft);
4135 goto err_destroy_vport_lag;
4136 }
4137
9a4ca38d 4138 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4139 return 0;
4140
4141err_destroy_vport_lag:
4142 mlx5_cmd_destroy_vport_lag(mdev);
4143 return err;
4144}
4145
45f95acd 4146static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4147{
4148 struct mlx5_core_dev *mdev = dev->mdev;
4149
9a4ca38d
MB		 4150 if (dev->flow_db->lag_demux_ft) {
4151 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4152 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4153
4154 mlx5_cmd_destroy_vport_lag(mdev);
4155 }
4156}
4157
7fd8aefb 4158static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4159{
4160 int err;
4161
7fd8aefb
DJ		 4162 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4163 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4164 if (err) {
7fd8aefb 4165 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4166 return err;
4167 }
4168
4169 return 0;
4170}
4171
7fd8aefb 4172static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4173{
7fd8aefb
DJ		 4174 if (dev->roce[port_num].nb.notifier_call) {
4175 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4176 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4177 }
4178}
4179
7fd8aefb 4180static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
fc24fc5e 4181{
e53505a8
AS		 4182 int err;
4183
ca5b91d6
OG		 4184 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4185 err = mlx5_nic_vport_enable_roce(dev->mdev);
4186 if (err)
8e6efa3a 4187 return err;
ca5b91d6 4188 }
e53505a8 4189
45f95acd 4190 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4191 if (err)
4192 goto err_disable_roce;
4193
e53505a8
AS		 4194 return 0;
4195
9ef9c640 4196err_disable_roce:
ca5b91d6
OG		 4197 if (MLX5_CAP_GEN(dev->mdev, roce))
4198 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4199
e53505a8 4200 return err;
fc24fc5e
AS		 4201}
4202
45f95acd 4203static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4204{
45f95acd 4205 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4206 if (MLX5_CAP_GEN(dev->mdev, roce))
4207 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4208}
4209
e1f24a79 4210struct mlx5_ib_counter {
7c16f477
KH		 4211 const char *name;
4212 size_t offset;
4213};
4214
4215#define INIT_Q_COUNTER(_name) \
4216 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4217
e1f24a79 4218static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4219 INIT_Q_COUNTER(rx_write_requests),
4220 INIT_Q_COUNTER(rx_read_requests),
4221 INIT_Q_COUNTER(rx_atomic_requests),
4222 INIT_Q_COUNTER(out_of_buffer),
4223};
4224
e1f24a79 4225static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4226 INIT_Q_COUNTER(out_of_sequence),
4227};
4228
e1f24a79 4229static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4230 INIT_Q_COUNTER(duplicate_request),
4231 INIT_Q_COUNTER(rnr_nak_retry_err),
4232 INIT_Q_COUNTER(packet_seq_err),
4233 INIT_Q_COUNTER(implied_nak_seq_err),
4234 INIT_Q_COUNTER(local_ack_timeout_err),
4235};
4236
e1f24a79
PP		 4237#define INIT_CONG_COUNTER(_name) \
4238 { .name = #_name, .offset = \
4239 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4240
4241static const struct mlx5_ib_counter cong_cnts[] = {
4242 INIT_CONG_COUNTER(rp_cnp_ignored),
4243 INIT_CONG_COUNTER(rp_cnp_handled),
4244 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4245 INIT_CONG_COUNTER(np_cnp_sent),
4246};
4247
58dcb60a
PP		 4248static const struct mlx5_ib_counter extended_err_cnts[] = {
4249 INIT_Q_COUNTER(resp_local_length_error),
4250 INIT_Q_COUNTER(resp_cqe_error),
4251 INIT_Q_COUNTER(req_cqe_error),
4252 INIT_Q_COUNTER(req_remote_invalid_request),
4253 INIT_Q_COUNTER(req_remote_access_errors),
4254 INIT_Q_COUNTER(resp_remote_access_errors),
4255 INIT_Q_COUNTER(resp_cqe_flush_error),
4256 INIT_Q_COUNTER(req_cqe_flush_error),
4257};
4258
e1f24a79 4259static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4260{
aac4492e 4261 int i;
0837e86a 4262
7c16f477 4263 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4264 if (dev->port[i].cnts.set_id)
4265 mlx5_core_dealloc_q_counter(dev->mdev,
4266 dev->port[i].cnts.set_id);
e1f24a79
PP		 4267 kfree(dev->port[i].cnts.names);
4268 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4269 }
4270}
4271
e1f24a79
PP		 4272static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4273 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4274{
4275 u32 num_counters;
4276
4277 num_counters = ARRAY_SIZE(basic_q_cnts);
4278
4279 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4280 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4281
4282 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4283 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4284
4285 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4286 num_counters += ARRAY_SIZE(extended_err_cnts);
4287
e1f24a79 4288 cnts->num_q_counters = num_counters;
7c16f477 4289
e1f24a79
PP		 4290 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4291 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4292 num_counters += ARRAY_SIZE(cong_cnts);
4293 }
4294
4295 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4296 if (!cnts->names)
7c16f477
KH		 4297 return -ENOMEM;
4298
e1f24a79
PP		 4299 cnts->offsets = kcalloc(num_counters,
4300 sizeof(cnts->offsets), GFP_KERNEL);
4301 if (!cnts->offsets)
7c16f477
KH		 4302 goto err_names;
4303
7c16f477
KH		 4304 return 0;
4305
4306err_names:
e1f24a79 4307 kfree(cnts->names);
aac4492e 4308 cnts->names = NULL;
7c16f477
KH		 4309 return -ENOMEM;
4310}
4311
e1f24a79
PP		 4312static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4313 const char **names,
4314 size_t *offsets)
7c16f477
KH		 4315{
4316 int i;
4317 int j = 0;
4318
4319 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4320 names[j] = basic_q_cnts[i].name;
4321 offsets[j] = basic_q_cnts[i].offset;
4322 }
4323
4324 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4325 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4326 names[j] = out_of_seq_q_cnts[i].name;
4327 offsets[j] = out_of_seq_q_cnts[i].offset;
4328 }
4329 }
4330
4331 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4332 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4333 names[j] = retrans_q_cnts[i].name;
4334 offsets[j] = retrans_q_cnts[i].offset;
4335 }
4336 }
e1f24a79 4337
58dcb60a
PP		 4338 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4339 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4340 names[j] = extended_err_cnts[i].name;
4341 offsets[j] = extended_err_cnts[i].offset;
4342 }
4343 }
4344
e1f24a79
PP		 4345 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4346 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4347 names[j] = cong_cnts[i].name;
4348 offsets[j] = cong_cnts[i].offset;
4349 }
4350 }
0837e86a
MB		 4351}
4352
e1f24a79 4353static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4354{
aac4492e 4355 int err = 0;
0837e86a 4356 int i;
0837e86a
MB		 4357
4358 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4359 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4360 if (err)
4361 goto err_alloc;
4362
4363 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4364 dev->port[i].cnts.offsets);
7c16f477 4365
aac4492e
DJ		 4366 err = mlx5_core_alloc_q_counter(dev->mdev,
4367 &dev->port[i].cnts.set_id);
4368 if (err) {
0837e86a
MB		 4369 mlx5_ib_warn(dev,
4370 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 4371 i + 1, err);
4372 goto err_alloc;
0837e86a 4373 }
aac4492e 4374 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 4375 }
4376
4377 return 0;
4378
aac4492e
DJ		 4379err_alloc:
4380 mlx5_ib_dealloc_counters(dev);
4381 return err;
0837e86a
MB		 4382}
4383
0ad17a8f
MB		 4384static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4385 u8 port_num)
4386{
7c16f477
KH		 4387 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4388 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 4389
4390 /* We support only per port stats */
4391 if (port_num == 0)
4392 return NULL;
4393
e1f24a79
PP		 4394 return rdma_alloc_hw_stats_struct(port->cnts.names,
4395 port->cnts.num_q_counters +
4396 port->cnts.num_cong_counters,
0ad17a8f
MB		 4397 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4398}
4399
aac4492e 4400static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 4401 struct mlx5_ib_port *port,
4402 struct rdma_hw_stats *stats)
0ad17a8f 4403{
0ad17a8f
MB		 4404 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4405 void *out;
4406 __be32 val;
e1f24a79 4407 int ret, i;
0ad17a8f 4408
1b9a07ee 4409 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 4410 if (!out)
4411 return -ENOMEM;
4412
aac4492e 4413 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 4414 port->cnts.set_id, 0,
0ad17a8f
MB		 4415 out, outlen);
4416 if (ret)
4417 goto free;
4418
e1f24a79
PP		 4419 for (i = 0; i < port->cnts.num_q_counters; i++) {
4420 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 4421 stats->value[i] = (u64)be32_to_cpu(val);
4422 }
7c16f477 4423
0ad17a8f
MB		 4424free:
4425 kvfree(out);
e1f24a79
PP		 4426 return ret;
4427}
4428
e1f24a79
PP		 4429static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4430 struct rdma_hw_stats *stats,
4431 u8 port_num, int index)
4432{
4433 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4434 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 4435 struct mlx5_core_dev *mdev;
e1f24a79 4436 int ret, num_counters;
aac4492e 4437 u8 mdev_port_num;
e1f24a79
PP		 4438
4439 if (!stats)
4440 return -EINVAL;
4441
aac4492e
DJ		 4442 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4443
4444 /* q_counters are per IB device, query the master mdev */
4445 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 4446 if (ret)
4447 return ret;
e1f24a79
PP		 4448
4449 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 4450 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4451 &mdev_port_num);
4452 if (!mdev) {
4453 /* If port is not affiliated yet, its in down state
4454 * which doesn't have any counters yet, so it would be
4455 * zero. So no need to read from the HCA.
4456 */
4457 goto done;
4458 }
71a0ff65
MD		 4459 ret = mlx5_lag_query_cong_counters(dev->mdev,
4460 stats->value +
4461 port->cnts.num_q_counters,
4462 port->cnts.num_cong_counters,
4463 port->cnts.offsets +
4464 port->cnts.num_q_counters);
aac4492e
DJ		 4465
4466 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 4467 if (ret)
4468 return ret;
e1f24a79
PP		 4469 }
4470
aac4492e 4471done:
e1f24a79 4472 return num_counters;
0ad17a8f
MB		 4473}
4474
8e959601
NV		 4475static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4476{
4477 return mlx5_rdma_netdev_free(netdev);
4478}
4479
693dfd5a
ES		 4480static struct net_device*
4481mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4482 u8 port_num,
4483 enum rdma_netdev_t type,
4484 const char *name,
4485 unsigned char name_assign_type,
4486 void (*setup)(struct net_device *))
4487{
8e959601
NV		 4488 struct net_device *netdev;
4489 struct rdma_netdev *rn;
4490
693dfd5a
ES		 4491 if (type != RDMA_NETDEV_IPOIB)
4492 return ERR_PTR(-EOPNOTSUPP);
4493
8e959601
NV		 4494 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4495 name, setup);
4496 if (likely(!IS_ERR_OR_NULL(netdev))) {
4497 rn = netdev_priv(netdev);
4498 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4499 }
4500 return netdev;
693dfd5a
ES		 4501}
4502
fe248c3a
MG		 4503static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4504{
4505 if (!dev->delay_drop.dbg)
4506 return;
4507 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4508 kfree(dev->delay_drop.dbg);
4509 dev->delay_drop.dbg = NULL;
4510}
4511
03404e8a
MG		 4512static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4513{
4514 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4515 return;
4516
4517 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 4518 delay_drop_debugfs_cleanup(dev);
4519}
4520
4521static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4522 size_t count, loff_t *pos)
4523{
4524 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4525 char lbuf[20];
4526 int len;
4527
4528 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4529 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4530}
4531
4532static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4533 size_t count, loff_t *pos)
4534{
4535 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4536 u32 timeout;
4537 u32 var;
4538
4539 if (kstrtouint_from_user(buf, count, 0, &var))
4540 return -EFAULT;
4541
4542 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4543 1000);
4544 if (timeout != var)
4545 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4546 timeout);
4547
4548 delay_drop->timeout = timeout;
4549
4550 return count;
4551}
4552
4553static const struct file_operations fops_delay_drop_timeout = {
4554 .owner = THIS_MODULE,
4555 .open = simple_open,
4556 .write = delay_drop_timeout_write,
4557 .read = delay_drop_timeout_read,
4558};
4559
4560static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4561{
4562 struct mlx5_ib_dbg_delay_drop *dbg;
4563
4564 if (!mlx5_debugfs_root)
4565 return 0;
4566
4567 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4568 if (!dbg)
4569 return -ENOMEM;
4570
cbafad87
SM		 4571 dev->delay_drop.dbg = dbg;
4572
fe248c3a
MG		 4573 dbg->dir_debugfs =
4574 debugfs_create_dir("delay_drop",
4575 dev->mdev->priv.dbg_root);
4576 if (!dbg->dir_debugfs)
cbafad87 4577 goto out_debugfs;
fe248c3a
MG		 4578
4579 dbg->events_cnt_debugfs =
4580 debugfs_create_atomic_t("num_timeout_events", 0400,
4581 dbg->dir_debugfs,
4582 &dev->delay_drop.events_cnt);
4583 if (!dbg->events_cnt_debugfs)
4584 goto out_debugfs;
4585
4586 dbg->rqs_cnt_debugfs =
4587 debugfs_create_atomic_t("num_rqs", 0400,
4588 dbg->dir_debugfs,
4589 &dev->delay_drop.rqs_cnt);
4590 if (!dbg->rqs_cnt_debugfs)
4591 goto out_debugfs;
4592
4593 dbg->timeout_debugfs =
4594 debugfs_create_file("timeout", 0600,
4595 dbg->dir_debugfs,
4596 &dev->delay_drop,
4597 &fops_delay_drop_timeout);
4598 if (!dbg->timeout_debugfs)
4599 goto out_debugfs;
4600
4601 return 0;
4602
4603out_debugfs:
4604 delay_drop_debugfs_cleanup(dev);
4605 return -ENOMEM;
03404e8a
MG		 4606}
4607
4608static void init_delay_drop(struct mlx5_ib_dev *dev)
4609{
4610 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4611 return;
4612
4613 mutex_init(&dev->delay_drop.lock);
4614 dev->delay_drop.dev = dev;
4615 dev->delay_drop.activate = false;
4616 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4617 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 4618 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4619 atomic_set(&dev->delay_drop.events_cnt, 0);
4620
4621 if (delay_drop_debugfs_init(dev))
4622 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 4623}
4624
84305d71
LR		 4625static const struct cpumask *
4626mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 4627{
4628 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4629
4630 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4631}
4632
32f69e4b
DJ		 4633/* The mlx5_ib_multiport_mutex should be held when calling this function */
4634static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4635 struct mlx5_ib_multiport_info *mpi)
4636{
4637 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4638 struct mlx5_ib_port *port = &ibdev->port[port_num];
4639 int comps;
4640 int err;
4641 int i;
4642
a9e546e7
PP		 4643 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4644
32f69e4b
DJ		 4645 spin_lock(&port->mp.mpi_lock);
4646 if (!mpi->ibdev) {
4647 spin_unlock(&port->mp.mpi_lock);
4648 return;
4649 }
4650 mpi->ibdev = NULL;
4651
4652 spin_unlock(&port->mp.mpi_lock);
4653 mlx5_remove_netdev_notifier(ibdev, port_num);
4654 spin_lock(&port->mp.mpi_lock);
4655
4656 comps = mpi->mdev_refcnt;
4657 if (comps) {
4658 mpi->unaffiliate = true;
4659 init_completion(&mpi->unref_comp);
4660 spin_unlock(&port->mp.mpi_lock);
4661
4662 for (i = 0; i < comps; i++)
4663 wait_for_completion(&mpi->unref_comp);
4664
4665 spin_lock(&port->mp.mpi_lock);
4666 mpi->unaffiliate = false;
4667 }
4668
4669 port->mp.mpi = NULL;
4670
4671 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4672
4673 spin_unlock(&port->mp.mpi_lock);
4674
4675 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4676
4677 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4678 /* Log an error, still needed to cleanup the pointers and add
4679 * it back to the list.
4680 */
4681 if (err)
4682 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4683 port_num + 1);
4684
4685 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4686}
4687
4688/* The mlx5_ib_multiport_mutex should be held when calling this function */
4689static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4690 struct mlx5_ib_multiport_info *mpi)
4691{
4692 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4693 int err;
4694
4695 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4696 if (ibdev->port[port_num].mp.mpi) {
4697 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4698 port_num + 1);
4699 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4700 return false;
4701 }
4702
4703 ibdev->port[port_num].mp.mpi = mpi;
4704 mpi->ibdev = ibdev;
4705 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4706
4707 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4708 if (err)
4709 goto unbind;
4710
4711 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4712 if (err)
4713 goto unbind;
4714
4715 err = mlx5_add_netdev_notifier(ibdev, port_num);
4716 if (err) {
4717 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4718 port_num + 1);
4719 goto unbind;
4720 }
4721
a9e546e7
PP		 4722 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4723 if (err)
4724 goto unbind;
4725
32f69e4b
DJ		 4726 return true;
4727
4728unbind:
4729 mlx5_ib_unbind_slave_port(ibdev, mpi);
4730 return false;
4731}
4732
4733static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4734{
4735 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4736 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4737 port_num + 1);
4738 struct mlx5_ib_multiport_info *mpi;
4739 int err;
4740 int i;
4741
4742 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4743 return 0;
4744
4745 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4746 &dev->sys_image_guid);
4747 if (err)
4748 return err;
4749
4750 err = mlx5_nic_vport_enable_roce(dev->mdev);
4751 if (err)
4752 return err;
4753
4754 mutex_lock(&mlx5_ib_multiport_mutex);
4755 for (i = 0; i < dev->num_ports; i++) {
4756 bool bound = false;
4757
4758 /* build a stub multiport info struct for the native port. */
4759 if (i == port_num) {
4760 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4761 if (!mpi) {
4762 mutex_unlock(&mlx5_ib_multiport_mutex);
4763 mlx5_nic_vport_disable_roce(dev->mdev);
4764 return -ENOMEM;
4765 }
4766
4767 mpi->is_master = true;
4768 mpi->mdev = dev->mdev;
4769 mpi->sys_image_guid = dev->sys_image_guid;
4770 dev->port[i].mp.mpi = mpi;
4771 mpi->ibdev = dev;
4772 mpi = NULL;
4773 continue;
4774 }
4775
4776 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4777 list) {
4778 if (dev->sys_image_guid == mpi->sys_image_guid &&
4779 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4780 bound = mlx5_ib_bind_slave_port(dev, mpi);
4781 }
4782
4783 if (bound) {
4784 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4785 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4786 list_del(&mpi->list);
4787 break;
4788 }
4789 }
4790 if (!bound) {
4791 get_port_caps(dev, i + 1);
4792 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4793 i + 1);
4794 }
4795 }
4796
4797 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4798 mutex_unlock(&mlx5_ib_multiport_mutex);
4799 return err;
4800}
4801
4802static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4803{
4804 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4805 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4806 port_num + 1);
4807 int i;
4808
4809 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4810 return;
4811
4812 mutex_lock(&mlx5_ib_multiport_mutex);
4813 for (i = 0; i < dev->num_ports; i++) {
4814 if (dev->port[i].mp.mpi) {
4815 /* Destroy the native port stub */
4816 if (i == port_num) {
4817 kfree(dev->port[i].mp.mpi);
4818 dev->port[i].mp.mpi = NULL;
4819 } else {
4820 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4821 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4822 }
4823 }
4824 }
4825
4826 mlx5_ib_dbg(dev, "removing from devlist\n");
4827 list_del(&dev->ib_dev_list);
4828 mutex_unlock(&mlx5_ib_multiport_mutex);
4829
4830 mlx5_nic_vport_disable_roce(dev->mdev);
4831}
4832
c6475a0b
AY		 4833ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
4834 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
4835 &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4836 UVERBS_ATTR_TYPE(u64),
4837 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4838
4839#define NUM_TREES 1
8c84660b
MB		 4840static int populate_specs_root(struct mlx5_ib_dev *dev)
4841{
4842 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
4843 uverbs_default_get_objects()};
4844 size_t num_trees = 1;
4845
c6475a0b
AY		 4846 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
4847 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4848 default_root[num_trees++] = &mlx5_ib_flow_action;
4849
8c84660b
MB		 4850 dev->ib_dev.specs_root =
4851 uverbs_alloc_spec_tree(num_trees, default_root);
4852
4853 return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
4854}
4855
4856static void depopulate_specs_root(struct mlx5_ib_dev *dev)
4857{
4858 uverbs_free_spec_tree(dev->ib_dev.specs_root);
4859}
4860
b5ca15ad 4861void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 4862{
32f69e4b 4863 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 4864#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4865 cleanup_srcu_struct(&dev->mr_srcu);
4866#endif
16c1975f
MB		 4867 kfree(dev->port);
4868}
4869
b5ca15ad 4870int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4871{
4872 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 4873 const char *name;
e126ba97 4874 int err;
32f69e4b 4875 int i;
e126ba97 4876
508562d6 4877 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 4878 GFP_KERNEL);
4879 if (!dev->port)
16c1975f 4880 return -ENOMEM;
0837e86a 4881
32f69e4b
DJ		 4882 for (i = 0; i < dev->num_ports; i++) {
4883 spin_lock_init(&dev->port[i].mp.mpi_lock);
4884 rwlock_init(&dev->roce[i].netdev_lock);
4885 }
4886
4887 err = mlx5_ib_init_multiport_master(dev);
e126ba97 4888 if (err)
0837e86a 4889 goto err_free_port;
e126ba97 4890
32f69e4b 4891 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 4892 for (i = 1; i <= dev->num_ports; i++) {
4893 err = get_port_caps(dev, i);
4894 if (err)
4895 break;
4896 }
4897 } else {
4898 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4899 }
4900 if (err)
4901 goto err_mp;
4902
1b5daf11
MD		 4903 if (mlx5_use_mad_ifc(dev))
4904 get_ext_port_caps(dev);
e126ba97 4905
4babcf97
AH		 4906 if (!mlx5_lag_is_active(mdev))
4907 name = "mlx5_%d";
4908 else
4909 name = "mlx5_bond_%d";
4910
4911 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 4912 dev->ib_dev.owner = THIS_MODULE;
4913 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 4914 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 4915 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 4916 dev->ib_dev.num_comp_vectors =
4917 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 4918 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 4919
3cc297db
MB		 4920 mutex_init(&dev->cap_mask_mutex);
4921 INIT_LIST_HEAD(&dev->qp_list);
4922 spin_lock_init(&dev->reset_flow_resource_lock);
4923
4924#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4925 err = init_srcu_struct(&dev->mr_srcu);
4926 if (err)
4927 goto err_free_port;
4928#endif
4929
16c1975f 4930 return 0;
32f69e4b
DJ		 4931err_mp:
4932 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 4933
4934err_free_port:
4935 kfree(dev->port);
4936
4937 return -ENOMEM;
4938}
4939
9a4ca38d
MB		 4940static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
4941{
4942 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
4943
4944 if (!dev->flow_db)
4945 return -ENOMEM;
4946
4947 mutex_init(&dev->flow_db->lock);
4948
4949 return 0;
4950}
4951
b5ca15ad
MB		 4952int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
4953{
4954 struct mlx5_ib_dev *nic_dev;
4955
4956 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
4957
4958 if (!nic_dev)
4959 return -EINVAL;
4960
4961 dev->flow_db = nic_dev->flow_db;
4962
4963 return 0;
4964}
4965
9a4ca38d
MB		 4966static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
4967{
4968 kfree(dev->flow_db);
4969}
4970
b5ca15ad 4971int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 4972{
4973 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 4974 int err;
4975
e126ba97
EC		 4976 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
4977 dev->ib_dev.uverbs_cmd_mask =
4978 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
4979 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
4980 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
4981 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
4982 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 4983 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
4984 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 4985 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 4986 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 4987 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4988 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4989 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4990 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4991 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4992 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4993 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4994 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4995 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4996 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4997 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4998 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4999 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5000 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5001 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5002 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5003 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5004 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5005 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5006 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5007 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5008 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5009 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5010
5011 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5012 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5013 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5014 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5015 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5016 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5017 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5018 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5019 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5020 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5021 dev->ib_dev.mmap = mlx5_ib_mmap;
5022 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5023 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5024 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5025 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5026 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5027 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5028 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5029 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5030 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5031 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5032 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5033 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5034 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5035 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5036 dev->ib_dev.post_send = mlx5_ib_post_send;
5037 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5038 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5039 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5040 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5041 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5042 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5043 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5044 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5045 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5046 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5047 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5048 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5049 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5050 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5051 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5052 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5053 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5054 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5055 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5056 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5057 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5058
eff901d3
EC		 5059 if (mlx5_core_is_pf(mdev)) {
5060 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5061 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5062 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5063 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5064 }
e126ba97 5065
7c2344c3
MG		 5066 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5067
6e8484c5
MG		 5068 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5069
d2370e0a
MB		 5070 if (MLX5_CAP_GEN(mdev, imaicl)) {
5071 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5072 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5073 dev->ib_dev.uverbs_cmd_mask |=
5074 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5075 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5076 }
5077
938fe83c 5078 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5079 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5080 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5081 dev->ib_dev.uverbs_cmd_mask |=
5082 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5083 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5084 }
5085
81e30880
YH		 5086 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5087 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5088 dev->ib_dev.uverbs_ex_cmd_mask |=
5089 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5090 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5091 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5092 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5093 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5094 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
81e30880 5095
e126ba97
EC		 5096 err = init_node_data(dev);
5097 if (err)
16c1975f 5098 return err;
e126ba97 5099
c8b89924 5100 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5101 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5102 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 5103 mutex_init(&dev->lb_mutex);
5104
16c1975f
MB		 5105 return 0;
5106}
5107
8e6efa3a
MB		 5108static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5109{
5110 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5111 dev->ib_dev.query_port = mlx5_ib_query_port;
5112
5113 return 0;
5114}
5115
b5ca15ad 5116int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5117{
5118 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5119 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5120
5121 return 0;
5122}
5123
5124static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5125 u8 port_num)
5126{
5127 int i;
5128
5129 for (i = 0; i < dev->num_ports; i++) {
5130 dev->roce[i].dev = dev;
5131 dev->roce[i].native_port_num = i + 1;
5132 dev->roce[i].last_port_state = IB_PORT_DOWN;
5133 }
5134
5135 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5136 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5137 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5138 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5139 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5140 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5141
5142 dev->ib_dev.uverbs_ex_cmd_mask |=
5143 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5144 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5145 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5146 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5147 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5148
5149 return mlx5_add_netdev_notifier(dev, port_num);
5150}
5151
5152static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5153{
5154 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5155
5156 mlx5_remove_netdev_notifier(dev, port_num);
5157}
5158
5159int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5160{
5161 struct mlx5_core_dev *mdev = dev->mdev;
5162 enum rdma_link_layer ll;
5163 int port_type_cap;
5164 int err = 0;
5165 u8 port_num;
5166
5167 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5168 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5169 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5170
5171 if (ll == IB_LINK_LAYER_ETHERNET)
5172 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5173
5174 return err;
5175}
5176
5177void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5178{
5179 mlx5_ib_stage_common_roce_cleanup(dev);
5180}
5181
16c1975f
MB		 5182static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5183{
5184 struct mlx5_core_dev *mdev = dev->mdev;
5185 enum rdma_link_layer ll;
5186 int port_type_cap;
32f69e4b 5187 u8 port_num;
16c1975f
MB		 5188 int err;
5189
32f69e4b 5190 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 5191 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5192 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5193
fc24fc5e 5194 if (ll == IB_LINK_LAYER_ETHERNET) {
8e6efa3a
MB		 5195 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5196 if (err)
5197 return err;
7fd8aefb 5198
7fd8aefb 5199 err = mlx5_enable_eth(dev, port_num);
fc24fc5e 5200 if (err)
8e6efa3a 5201 goto cleanup;
fc24fc5e
AS		 5202 }
5203
16c1975f 5204 return 0;
8e6efa3a
MB		 5205cleanup:
5206 mlx5_ib_stage_common_roce_cleanup(dev);
5207
5208 return err;
16c1975f 5209}
e126ba97 5210
16c1975f
MB		 5211static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5212{
5213 struct mlx5_core_dev *mdev = dev->mdev;
5214 enum rdma_link_layer ll;
5215 int port_type_cap;
32f69e4b 5216 u8 port_num;
e126ba97 5217
32f69e4b 5218 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 5219 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5220 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5221
5222 if (ll == IB_LINK_LAYER_ETHERNET) {
5223 mlx5_disable_eth(dev);
8e6efa3a 5224 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 5225 }
16c1975f 5226}
6aec21f6 5227
b5ca15ad 5228int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5229{
5230 return create_dev_resources(&dev->devr);
5231}
5232
b5ca15ad 5233void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5234{
5235 destroy_dev_resources(&dev->devr);
5236}
5237
5238static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5239{
07321b3c
MB		 5240 mlx5_ib_internal_fill_odp_caps(dev);
5241
16c1975f
MB		 5242 return mlx5_ib_odp_init_one(dev);
5243}
4a2da0b8 5244
b5ca15ad 5245int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 5246{
5e1e7612
MB		 5247 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5248 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
5249 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
5250
5251 return mlx5_ib_alloc_counters(dev);
5252 }
16c1975f
MB		 5253
5254 return 0;
5255}
5256
b5ca15ad 5257void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5258{
5259 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5260 mlx5_ib_dealloc_counters(dev);
5261}
5262
5263static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5264{
a9e546e7
PP		 5265 return mlx5_ib_init_cong_debugfs(dev,
5266 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5267}
5268
5269static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5270{
a9e546e7
PP		 5271 mlx5_ib_cleanup_cong_debugfs(dev,
5272 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5273}
5274
5275static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5276{
5fe9dec0
EC		 5277 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
5278 if (!dev->mdev->priv.uar)
16c1975f
MB		 5279 return -ENOMEM;
5280 return 0;
5281}
5282
5283static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5284{
5285 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5286}
5287
b5ca15ad 5288int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5289{
5290 int err;
5fe9dec0
EC		 5291
5292 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5293 if (err)
16c1975f 5294 return err;
5fe9dec0
EC		 5295
5296 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5297 if (err)
16c1975f 5298 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 5299
16c1975f
MB		 5300 return err;
5301}
0837e86a 5302
b5ca15ad 5303void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5304{
5305 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5306 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5307}
e126ba97 5308
8c84660b
MB		 5309static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5310{
5311 return populate_specs_root(dev);
5312}
5313
b5ca15ad 5314int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5315{
5316 return ib_register_device(&dev->ib_dev, NULL);
5317}
5318
8c84660b
MB		 5319static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5320{
5321 depopulate_specs_root(dev);
5322}
5323
2d873449 5324void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5325{
42cea83f 5326 destroy_umrc_res(dev);
16c1975f
MB		 5327}
5328
2d873449 5329void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5330{
42cea83f 5331 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 5332}
5333
2d873449 5334int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 5335{
42cea83f 5336 return create_umr_res(dev);
16c1975f
MB		 5337}
5338
5339static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5340{
03404e8a
MG		 5341 init_delay_drop(dev);
5342
16c1975f
MB		 5343 return 0;
5344}
5345
5346static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5347{
5348 cancel_delay_drop(dev);
5349}
5350
b5ca15ad 5351int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5352{
5353 int err;
5354 int i;
5355
e126ba97 5356 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 5357 err = device_create_file(&dev->ib_dev.dev,
5358 mlx5_class_attributes[i]);
5359 if (err)
16c1975f 5360 return err;
e126ba97
EC		 5361 }
5362
16c1975f
MB		 5363 return 0;
5364}
5365
fc385b7a
MB		 5366static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5367{
5368 mlx5_ib_register_vport_reps(dev);
5369
5370 return 0;
5371}
5372
5373static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5374{
5375 mlx5_ib_unregister_vport_reps(dev);
5376}
5377
b5ca15ad
MB		 5378void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5379 const struct mlx5_ib_profile *profile,
5380 int stage)
16c1975f
MB		 5381{
5382 /* Number of stages to cleanup */
5383 while (stage) {
5384 stage--;
5385 if (profile->stage[stage].cleanup)
5386 profile->stage[stage].cleanup(dev);
5387 }
e126ba97 5388
16c1975f
MB		 5389 ib_dealloc_device((struct ib_device *)dev);
5390}
e126ba97 5391
32f69e4b
DJ		 5392static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5393
b5ca15ad
MB		 5394void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5395 const struct mlx5_ib_profile *profile)
16c1975f 5396{
16c1975f
MB		 5397 int err;
5398 int i;
e126ba97 5399
16c1975f 5400 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 5401
16c1975f
MB		 5402 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5403 if (profile->stage[i].init) {
5404 err = profile->stage[i].init(dev);
5405 if (err)
5406 goto err_out;
5407 }
5408 }
0837e86a 5409
16c1975f
MB		 5410 dev->profile = profile;
5411 dev->ib_active = true;
6aec21f6 5412
16c1975f 5413 return dev;
e126ba97 5414
16c1975f
MB		 5415err_out:
5416 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 5417
16c1975f
MB		 5418 return NULL;
5419}
0837e86a 5420
16c1975f
MB		 5421static const struct mlx5_ib_profile pf_profile = {
5422 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5423 mlx5_ib_stage_init_init,
5424 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 5425 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5426 mlx5_ib_stage_flow_db_init,
5427 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 5428 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5429 mlx5_ib_stage_caps_init,
5430 NULL),
8e6efa3a
MB		 5431 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5432 mlx5_ib_stage_non_default_cb,
5433 NULL),
16c1975f
MB		 5434 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5435 mlx5_ib_stage_roce_init,
5436 mlx5_ib_stage_roce_cleanup),
5437 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5438 mlx5_ib_stage_dev_res_init,
5439 mlx5_ib_stage_dev_res_cleanup),
5440 STAGE_CREATE(MLX5_IB_STAGE_ODP,
5441 mlx5_ib_stage_odp_init,
3cc297db 5442 NULL),
16c1975f
MB		 5443 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5444 mlx5_ib_stage_counters_init,
5445 mlx5_ib_stage_counters_cleanup),
5446 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5447 mlx5_ib_stage_cong_debugfs_init,
5448 mlx5_ib_stage_cong_debugfs_cleanup),
5449 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5450 mlx5_ib_stage_uar_init,
5451 mlx5_ib_stage_uar_cleanup),
5452 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5453 mlx5_ib_stage_bfrag_init,
5454 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 5455 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5456 NULL,
5457 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 5458 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5459 mlx5_ib_stage_populate_specs,
5460 mlx5_ib_stage_depopulate_specs),
16c1975f
MB		 5461 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5462 mlx5_ib_stage_ib_reg_init,
5463 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 5464 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5465 mlx5_ib_stage_post_ib_reg_umr_init,
5466 NULL),
16c1975f
MB		 5467 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5468 mlx5_ib_stage_delay_drop_init,
5469 mlx5_ib_stage_delay_drop_cleanup),
5470 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5471 mlx5_ib_stage_class_attr_init,
5472 NULL),
16c1975f 5473};
e126ba97 5474
b5ca15ad
MB		 5475static const struct mlx5_ib_profile nic_rep_profile = {
5476 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5477 mlx5_ib_stage_init_init,
5478 mlx5_ib_stage_init_cleanup),
5479 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5480 mlx5_ib_stage_flow_db_init,
5481 mlx5_ib_stage_flow_db_cleanup),
5482 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5483 mlx5_ib_stage_caps_init,
5484 NULL),
5485 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5486 mlx5_ib_stage_rep_non_default_cb,
5487 NULL),
5488 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5489 mlx5_ib_stage_rep_roce_init,
5490 mlx5_ib_stage_rep_roce_cleanup),
5491 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5492 mlx5_ib_stage_dev_res_init,
5493 mlx5_ib_stage_dev_res_cleanup),
5494 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5495 mlx5_ib_stage_counters_init,
5496 mlx5_ib_stage_counters_cleanup),
5497 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5498 mlx5_ib_stage_uar_init,
5499 mlx5_ib_stage_uar_cleanup),
5500 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5501 mlx5_ib_stage_bfrag_init,
5502 mlx5_ib_stage_bfrag_cleanup),
2d873449
DL		 5503 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5504 NULL,
5505 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 5506 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5507 mlx5_ib_stage_populate_specs,
5508 mlx5_ib_stage_depopulate_specs),
b5ca15ad
MB		 5509 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5510 mlx5_ib_stage_ib_reg_init,
5511 mlx5_ib_stage_ib_reg_cleanup),
2d873449
DL		 5512 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5513 mlx5_ib_stage_post_ib_reg_umr_init,
5514 NULL),
b5ca15ad
MB		 5515 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5516 mlx5_ib_stage_class_attr_init,
5517 NULL),
5518 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
5519 mlx5_ib_stage_rep_reg_init,
5520 mlx5_ib_stage_rep_reg_cleanup),
5521};
5522
32f69e4b
DJ		 5523static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5524{
5525 struct mlx5_ib_multiport_info *mpi;
5526 struct mlx5_ib_dev *dev;
5527 bool bound = false;
5528 int err;
5529
5530 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5531 if (!mpi)
5532 return NULL;
5533
5534 mpi->mdev = mdev;
5535
5536 err = mlx5_query_nic_vport_system_image_guid(mdev,
5537 &mpi->sys_image_guid);
5538 if (err) {
5539 kfree(mpi);
5540 return NULL;
5541 }
5542
5543 mutex_lock(&mlx5_ib_multiport_mutex);
5544 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5545 if (dev->sys_image_guid == mpi->sys_image_guid)
5546 bound = mlx5_ib_bind_slave_port(dev, mpi);
5547
5548 if (bound) {
5549 rdma_roce_rescan_device(&dev->ib_dev);
5550 break;
5551 }
5552 }
5553
5554 if (!bound) {
5555 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5556 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5557 } else {
5558 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5559 }
5560 mutex_unlock(&mlx5_ib_multiport_mutex);
5561
5562 return mpi;
5563}
5564
16c1975f
MB		 5565static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5566{
32f69e4b 5567 enum rdma_link_layer ll;
b5ca15ad 5568 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 5569 int port_type_cap;
5570
b5ca15ad
MB		 5571 printk_once(KERN_INFO "%s", mlx5_version);
5572
32f69e4b
DJ		 5573 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5574 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5575
5576 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5577 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5578
5579 return mlx5_ib_add_slave_port(mdev, port_num);
5580 }
5581
b5ca15ad
MB		 5582 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
5583 if (!dev)
5584 return NULL;
5585
5586 dev->mdev = mdev;
5587 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5588 MLX5_CAP_GEN(mdev, num_vhca_ports));
5589
5590 if (MLX5_VPORT_MANAGER(mdev) &&
5591 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5592 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
5593
5594 return __mlx5_ib_add(dev, &nic_rep_profile);
5595 }
5596
5597 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 5598}
5599
9603b61d 5600static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 5601{
32f69e4b
DJ		 5602 struct mlx5_ib_multiport_info *mpi;
5603 struct mlx5_ib_dev *dev;
5604
5605 if (mlx5_core_is_mp_slave(mdev)) {
5606 mpi = context;
5607 mutex_lock(&mlx5_ib_multiport_mutex);
5608 if (mpi->ibdev)
5609 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5610 list_del(&mpi->list);
5611 mutex_unlock(&mlx5_ib_multiport_mutex);
5612 return;
5613 }
6aec21f6 5614
32f69e4b 5615 dev = context;
16c1975f 5616 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 5617}
5618
9603b61d
JM		 5619static struct mlx5_interface mlx5_ib_interface = {
5620 .add = mlx5_ib_add,
5621 .remove = mlx5_ib_remove,
5622 .event = mlx5_ib_event,
d9aaed83
AK		 5623#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5624 .pfault = mlx5_ib_pfault,
5625#endif
64613d94 5626 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 5627};
5628
c44ef998
IL		 5629unsigned long mlx5_ib_get_xlt_emergency_page(void)
5630{
5631 mutex_lock(&xlt_emergency_page_mutex);
5632 return xlt_emergency_page;
5633}
5634
5635void mlx5_ib_put_xlt_emergency_page(void)
5636{
5637 mutex_unlock(&xlt_emergency_page_mutex);
5638}
5639
e126ba97
EC		 5640static int __init mlx5_ib_init(void)
5641{
6aec21f6
HE		 5642 int err;
5643
c44ef998
IL		 5644 xlt_emergency_page = __get_free_page(GFP_KERNEL);
5645 if (!xlt_emergency_page)
5646 return -ENOMEM;
5647
5648 mutex_init(&xlt_emergency_page_mutex);
5649
d69a24e0 5650 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 5651 if (!mlx5_ib_event_wq) {
5652 free_page(xlt_emergency_page);
d69a24e0 5653 return -ENOMEM;
c44ef998 5654 }
d69a24e0 5655
81713d37 5656 mlx5_ib_odp_init();
9603b61d 5657
6aec21f6 5658 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 5659
6aec21f6 5660 return err;
e126ba97
EC		 5661}
5662
5663static void __exit mlx5_ib_cleanup(void)
5664{
9603b61d 5665 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 5666 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 5667 mutex_destroy(&xlt_emergency_page_mutex);
5668 free_page(xlt_emergency_page);
e126ba97
EC		 5669}
5670
5671module_init(mlx5_ib_init);
5672module_exit(mlx5_ib_cleanup);
Ubuntu Hirsute Linux kernel mirror