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RDMA/bnxt_re: Fix a bunch of off by one bugs in qplib_fp.c
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
da7525d2
EBE		 91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
d69a24e0 95static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
c44ef998
IL		 103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
32f69e4b
DJ		 109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
1b5daf11 119static enum rdma_link_layer
ebd61f68 120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 121{
ebd61f68 122 switch (port_type_cap) {
1b5daf11
MD		 123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
ebd61f68
AS		 132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
fd65f1b8
MS		 141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
8e6efa3a 149 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
fc24fc5e
AS		 155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
7fd8aefb 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
32f69e4b
DJ		 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
fc24fc5e 168
5ec8c83e
AH		 169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
7fd8aefb 172 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 181 NULL : ndev;
84a6a7a9 182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
bcf87f1d
MB		 183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
fd65f1b8 189 case NETDEV_CHANGE:
5ec8c83e 190 case NETDEV_UP:
88621dfe 191 case NETDEV_DOWN: {
7fd8aefb 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
7fd8aefb 200 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 201 && ibdev->ib_active) {
626bc02d 202 struct ib_event ibev = { };
fd65f1b8 203 enum ib_port_state port_state;
5ec8c83e 204
7fd8aefb
DJ		 205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
fd65f1b8 208
7fd8aefb
DJ		 209 if (roce->last_port_state == port_state)
210 goto done;
fd65f1b8 211
7fd8aefb 212 roce->last_port_state = port_state;
5ec8c83e 213 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
7fd8aefb 219 goto done;
fd65f1b8 220
7fd8aefb 221 ibev.element.port_num = port_num;
5ec8c83e
AH		 222 ib_dispatch_event(&ibev);
223 }
224 break;
88621dfe 225 }
fc24fc5e 226
5ec8c83e
AH		 227 default:
228 break;
229 }
7fd8aefb 230done:
32f69e4b 231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
32f69e4b
DJ		 240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
fc24fc5e 245
32f69e4b 246 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 247 if (ndev)
32f69e4b 248 goto out;
88621dfe 249
fc24fc5e
AS		 250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
7fd8aefb
DJ		 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 254 if (ndev)
255 dev_hold(ndev);
7fd8aefb 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 257
32f69e4b
DJ		 258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 260 return ndev;
261}
262
32f69e4b
DJ		 263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
210b1f78
MB		 273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
32f69e4b
DJ		 280 if (native_port_num)
281 *native_port_num = 1;
282
32f69e4b
DJ		 283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
f1b65df5
NO		 326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
095b0927
IT		 384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
3f89a643
AS		 386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 388 struct mlx5_core_dev *mdev;
88621dfe 389 struct net_device *ndev, *upper;
3f89a643 390 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 391 bool put_mdev = true;
c876a1b7 392 u16 qkey_viol_cntr;
f1b65df5 393 u32 eth_prot_oper;
b3cbd6f0 394 u8 mdev_port_num;
095b0927 395 int err;
3f89a643 396
b3cbd6f0
DJ		 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
f1b65df5
NO		 408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
50f22fd8 410 */
b3cbd6f0
DJ		 411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
095b0927 413 if (err)
b3cbd6f0 414 goto out;
f1b65df5 415
7672ed33
HL		 416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
f1b65df5
NO		 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
3f89a643
AS		 421
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
b3cbd6f0 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 434 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 435
b3cbd6f0
DJ		 436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
3f89a643
AS		 440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
b3cbd6f0 442 goto out;
3f89a643 443
88621dfe
AH		 444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
3f89a643
AS		 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
3f89a643
AS		 469}
470
095b0927
IT		 471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
3cca2606 474{
095b0927
IT		 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
3cca2606
AS		 490 }
491
095b0927 492 switch (gid_type) {
3cca2606 493 case IB_GID_TYPE_IB:
095b0927 494 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 502 break;
503
504 default:
095b0927 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 506 }
507
095b0927
IT		 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 510 vlan_id, port_num);
3cca2606
AS		 511}
512
f4df9a7c 513static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 514 __always_unused void **context)
515{
414448d2 516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 517 attr->index, &attr->gid, attr);
3cca2606
AS		 518}
519
414448d2
PP		 520static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
3cca2606 522{
414448d2
PP		 523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
3cca2606
AS		 525}
526
47ec3866
PP		 527__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
2811ba51 529{
47ec3866 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534}
535
1b5daf11
MD		 536static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537{
7fae6655
NO		 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
1b5daf11
MD		 541}
542
543enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547};
548
549static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550{
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
ebd61f68 554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559}
560
da7525d2 561static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 562 u8 atomic_size_qp,
da7525d2
EBE		 563 struct ib_device_attr *props)
564{
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 567 u8 atomic_req_8B_endianness_mode =
bd10838a 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581}
582
776a3906
MS		 583static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585{
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589}
590
591static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600{
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605}
1b5daf11
MD		 606static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608{
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
1b5daf11
MD		 626
627 default:
628 return -EINVAL;
629 }
3f89a643
AS		 630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
1b5daf11
MD		 636}
637
638static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640{
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657}
658
659static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661{
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675}
676
677static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679{
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
1b5daf11
MD		 694
695 default:
696 return -EINVAL;
697 }
3f89a643
AS		 698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
1b5daf11
MD		 703}
704
705struct mlx5_reg_node_desc {
bd99fdea 706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 707};
708
709static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710{
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721}
722
e126ba97 723static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
e126ba97
EC		 726{
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 728 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 729 int err = -ENOMEM;
288c01b7 730 int max_sq_desc;
e126ba97
EC		 731 int max_rq_sg;
732 int max_sq_sg;
e0238a6a 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 734 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
e126ba97 738
402ca536
BW		 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 746 return -EINVAL;
747
1b5daf11
MD		 748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
e126ba97 753
1b5daf11 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 755 if (err)
1b5daf11 756 return err;
e126ba97 757
1b5daf11
MD		 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
e126ba97 761
9603b61d
JM		 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
e126ba97
EC		 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 768 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 769
770 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 772 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 774 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 776 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 777 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 784 }
e126ba97 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 786 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
938fe83c 795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 797
85c7c014 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
88115fe7 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 808
402ca536
BW		 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
31f69a82
YH		 818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
2d93fc85
MB		 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 843 }
844
f0313965
ES		 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
03404e8a 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
03404e8a
MG		 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
1d54f890
YH		 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
cff5a0f3 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
e8161334 862 /* Legacy bit to support old userspace libraries */
cff5a0f3 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
cff5a0f3 866
24da0016
AL		 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
da6d6ba3
MG		 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
b1383aa6
NO		 875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
1b5daf11
MD		 878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 880
881 props->max_mr_size = ~0ull;
e0238a6a 882 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
986ef95e 893 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 904 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 907 get_atomic_caps_qp(dev, props);
81bea28f 908 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 914 props->max_ah = INT_MAX;
7c60bcbb
MB		 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 917
8cdd312c 918#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 919 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922#endif
923
051f2630
LR		 924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
eff901d3
EC		 927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
31f69a82 930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 931 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
eb761894 941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
eb761894 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
eb761894 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 949 }
950
87ab3f52
YC		 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
7e43a2a5 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 959 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 973 }
7e43a2a5
BW		 974 }
975
85c7c014
DJ		 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
d949167d
BW		 978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
9f885201
LR		 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
795b609c
BW		 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
050da902
BW		 999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
9f885201
LR		 1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
de57f2ad
GL		 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
7a0c8f42 1010
de57f2ad
GL		 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1017 }
9f885201 1018
96dc3fc5
NO		 1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
85c7c014
DJ		 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
b4f34597
NO		 1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
f95ef6cb
MG		 1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1077 }
1078
402ca536
BW		 1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1b5daf11 1086 return 0;
e126ba97
EC		 1087}
1088
1b5daf11
MD		 1089enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095};
1096
1097static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
e126ba97
EC		 1099{
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1101 int err = 0;
1102
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1107 (int)active_width);
1108 err = -EINVAL;
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1115 } else {
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1117 (int)active_width);
1118 err = -EINVAL;
e126ba97
EC		 1119 }
1120
1b5daf11
MD		 1121 return err;
1122}
e126ba97 1123
1b5daf11
MD		 1124static int mlx5_mtu_to_ib_mtu(int mtu)
1125{
1126 switch (mtu) {
1127 case 256: return 1;
1128 case 512: return 2;
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1132 default:
1133 pr_warn("invalid mtu\n");
1134 return -1;
e126ba97 1135 }
1b5daf11 1136}
e126ba97 1137
1b5daf11
MD		 1138enum ib_max_vl_num {
1139 __IB_MAX_VL_0 = 1,
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1144};
e126ba97 1145
1b5daf11
MD		 1146enum mlx5_vl_hw_cap {
1147 MLX5_VL_HW_0 = 1,
1148 MLX5_VL_HW_0_1 = 2,
1149 MLX5_VL_HW_0_2 = 3,
1150 MLX5_VL_HW_0_3 = 4,
1151 MLX5_VL_HW_0_4 = 5,
1152 MLX5_VL_HW_0_5 = 6,
1153 MLX5_VL_HW_0_6 = 7,
1154 MLX5_VL_HW_0_7 = 8,
1155 MLX5_VL_HW_0_14 = 15
1156};
e126ba97 1157
1b5daf11
MD		 1158static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1159 u8 *max_vl_num)
1160{
1161 switch (vl_hw_cap) {
1162 case MLX5_VL_HW_0:
1163 *max_vl_num = __IB_MAX_VL_0;
1164 break;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1167 break;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1170 break;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1173 break;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1176 break;
e126ba97 1177
1b5daf11
MD		 1178 default:
1179 return -EINVAL;
e126ba97 1180 }
e126ba97 1181
1b5daf11 1182 return 0;
e126ba97
EC		 1183}
1184
1b5daf11
MD		 1185static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
e126ba97 1187{
1b5daf11
MD		 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1191 u16 max_mtu;
1192 u16 oper_mtu;
1b5daf11
MD		 1193 int err;
1194 u8 ib_link_width_oper;
1195 u8 vl_hw_cap;
e126ba97 1196
1b5daf11
MD		 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1198 if (!rep) {
1199 err = -ENOMEM;
e126ba97 1200 goto out;
e126ba97 1201 }
e126ba97 1202
c4550c63 1203 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1204
1b5daf11 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1206 if (err)
1207 goto out;
1208
1b5daf11
MD		 1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
eff901d3 1223 props->grh_required = rep->grh_required;
e126ba97 1224
1b5daf11
MD		 1225 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1226 if (err)
e126ba97 1227 goto out;
e126ba97 1228
1b5daf11
MD		 1229 err = translate_active_width(ibdev, ib_link_width_oper,
1230 &props->active_width);
1231 if (err)
1232 goto out;
d5beb7f2 1233 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1234 if (err)
1235 goto out;
1236
facc9699 1237 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1238
1b5daf11 1239 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1240
facc9699 1241 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1242
1b5daf11 1243 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1244
1b5daf11
MD		 1245 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1246 if (err)
1247 goto out;
e126ba97 1248
1b5daf11
MD		 1249 err = translate_max_vl_num(ibdev, vl_hw_cap,
1250 &props->max_vl_num);
e126ba97 1251out:
1b5daf11 1252 kfree(rep);
e126ba97
EC		 1253 return err;
1254}
1255
1b5daf11
MD		 1256int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1257 struct ib_port_attr *props)
e126ba97 1258{
095b0927
IT		 1259 unsigned int count;
1260 int ret;
1261
1b5daf11
MD		 1262 switch (mlx5_get_vport_access_method(ibdev)) {
1263 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1264 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1265 break;
e126ba97 1266
1b5daf11 1267 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1268 ret = mlx5_query_hca_port(ibdev, port, props);
1269 break;
e126ba97 1270
3f89a643 1271 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1272 ret = mlx5_query_port_roce(ibdev, port, props);
1273 break;
3f89a643 1274
1b5daf11 1275 default:
095b0927
IT		 1276 ret = -EINVAL;
1277 }
1278
1279 if (!ret && props) {
b3cbd6f0
DJ		 1280 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1281 struct mlx5_core_dev *mdev;
1282 bool put_mdev = true;
1283
1284 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1285 if (!mdev) {
1286 /* If the port isn't affiliated yet query the master.
1287 * The master and slave will have the same values.
1288 */
1289 mdev = dev->mdev;
1290 port = 1;
1291 put_mdev = false;
1292 }
1293 count = mlx5_core_reserved_gids_count(mdev);
1294 if (put_mdev)
1295 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1296 props->gid_tbl_len -= count;
1b5daf11 1297 }
095b0927 1298 return ret;
1b5daf11 1299}
e126ba97 1300
8e6efa3a
MB		 1301static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1302 struct ib_port_attr *props)
1303{
1304 int ret;
1305
1306 /* Only link layer == ethernet is valid for representors */
1307 ret = mlx5_query_port_roce(ibdev, port, props);
1308 if (ret || !props)
1309 return ret;
1310
1311 /* We don't support GIDS */
1312 props->gid_tbl_len = 0;
1313
1314 return ret;
1315}
1316
1b5daf11
MD		 1317static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1318 union ib_gid *gid)
1319{
1320 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1321 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1322
1b5daf11
MD		 1323 switch (mlx5_get_vport_access_method(ibdev)) {
1324 case MLX5_VPORT_ACCESS_METHOD_MAD:
1325 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1326
1b5daf11
MD		 1327 case MLX5_VPORT_ACCESS_METHOD_HCA:
1328 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1329
1330 default:
1331 return -EINVAL;
1332 }
e126ba97 1333
e126ba97
EC		 1334}
1335
b3cbd6f0
DJ		 1336static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1337 u16 index, u16 *pkey)
1b5daf11
MD		 1338{
1339 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1340 struct mlx5_core_dev *mdev;
1341 bool put_mdev = true;
1342 u8 mdev_port_num;
1343 int err;
1b5daf11 1344
b3cbd6f0
DJ		 1345 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1346 if (!mdev) {
1347 /* The port isn't affiliated yet, get the PKey from the master
1348 * port. For RoCE the PKey tables will be the same.
1349 */
1350 put_mdev = false;
1351 mdev = dev->mdev;
1352 mdev_port_num = 1;
1353 }
1354
1355 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1356 index, pkey);
1357 if (put_mdev)
1358 mlx5_ib_put_native_port_mdev(dev, port);
1359
1360 return err;
1361}
1362
1363static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1364 u16 *pkey)
1365{
1b5daf11
MD		 1366 switch (mlx5_get_vport_access_method(ibdev)) {
1367 case MLX5_VPORT_ACCESS_METHOD_MAD:
1368 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1369
1370 case MLX5_VPORT_ACCESS_METHOD_HCA:
1371 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1372 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1373 default:
1374 return -EINVAL;
1375 }
1376}
e126ba97
EC		 1377
1378static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1379 struct ib_device_modify *props)
1380{
1381 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1382 struct mlx5_reg_node_desc in;
1383 struct mlx5_reg_node_desc out;
1384 int err;
1385
1386 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1387 return -EOPNOTSUPP;
1388
1389 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1390 return 0;
1391
1392 /*
1393 * If possible, pass node desc to FW, so it can generate
1394 * a 144 trap. If cmd fails, just ignore.
1395 */
bd99fdea 1396 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1397 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1398 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1399 if (err)
1400 return err;
1401
bd99fdea 1402 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1403
1404 return err;
1405}
1406
cdbe33d0
EC		 1407static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1408 u32 value)
1409{
1410 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1411 struct mlx5_core_dev *mdev;
1412 u8 mdev_port_num;
cdbe33d0
EC		 1413 int err;
1414
b3cbd6f0
DJ		 1415 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1416 if (!mdev)
1417 return -ENODEV;
1418
1419 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1420 if (err)
b3cbd6f0 1421 goto out;
cdbe33d0
EC		 1422
1423 if (~ctx.cap_mask1_perm & mask) {
1424 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1425 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1426 err = -EINVAL;
1427 goto out;
cdbe33d0
EC		 1428 }
1429
1430 ctx.cap_mask1 = value;
1431 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1432 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1433 0, &ctx);
1434
1435out:
1436 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1437
1438 return err;
1439}
1440
e126ba97
EC		 1441static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1442 struct ib_port_modify *props)
1443{
1444 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1445 struct ib_port_attr attr;
1446 u32 tmp;
1447 int err;
cdbe33d0
EC		 1448 u32 change_mask;
1449 u32 value;
1450 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1451 IB_LINK_LAYER_INFINIBAND);
1452
ec255879
MD		 1453 /* CM layer calls ib_modify_port() regardless of the link layer. For
1454 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1455 */
1456 if (!is_ib)
1457 return 0;
1458
cdbe33d0
EC		 1459 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1460 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1461 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1462 return set_port_caps_atomic(dev, port, change_mask, value);
1463 }
e126ba97
EC		 1464
1465 mutex_lock(&dev->cap_mask_mutex);
1466
c4550c63 1467 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1468 if (err)
1469 goto out;
1470
1471 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1472 ~props->clr_port_cap_mask;
1473
9603b61d 1474 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1475
1476out:
1477 mutex_unlock(&dev->cap_mask_mutex);
1478 return err;
1479}
1480
30aa60b3
EC		 1481static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1482{
1483 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1484 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1485}
1486
31a78a5a
YH		 1487static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1488{
1489 /* Large page with non 4k uar support might limit the dynamic size */
1490 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1491 return MLX5_MIN_DYN_BFREGS;
1492
1493 return MLX5_MAX_DYN_BFREGS;
1494}
1495
b037c29a
EC		 1496static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1497 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1498 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1499{
1500 int uars_per_sys_page;
1501 int bfregs_per_sys_page;
1502 int ref_bfregs = req->total_num_bfregs;
1503
1504 if (req->total_num_bfregs == 0)
1505 return -EINVAL;
1506
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1508 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1509
1510 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1511 return -ENOMEM;
1512
1513 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1514 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1515 /* This holds the required static allocation asked by the user */
b037c29a 1516 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1517 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1518 return -EINVAL;
1519
31a78a5a
YH		 1520 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1521 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1522 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1523 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1524
1525 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1526 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1527 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1528 req->total_num_bfregs, bfregi->total_num_bfregs,
1529 bfregi->num_sys_pages);
b037c29a
EC		 1530
1531 return 0;
1532}
1533
1534static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1535{
1536 struct mlx5_bfreg_info *bfregi;
1537 int err;
1538 int i;
1539
1540 bfregi = &context->bfregi;
31a78a5a 1541 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1542 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1543 if (err)
1544 goto error;
1545
1546 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1547 }
4ed131d0
YH		 1548
1549 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1550 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1551
b037c29a
EC		 1552 return 0;
1553
1554error:
1555 for (--i; i >= 0; i--)
1556 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1557 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1558
1559 return err;
1560}
1561
15177999
LR		 1562static void deallocate_uars(struct mlx5_ib_dev *dev,
1563 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1564{
1565 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1566 int i;
1567
1568 bfregi = &context->bfregi;
15177999 1569 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1570 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1571 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1572 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1573}
1574
c85023e1
HN		 1575static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1576{
1577 int err;
1578
cfdeb893
LR		 1579 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1580 return 0;
1581
c85023e1
HN		 1582 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1583 if (err)
1584 return err;
1585
1586 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1587 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1588 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1589 return err;
1590
1591 mutex_lock(&dev->lb_mutex);
1592 dev->user_td++;
1593
1594 if (dev->user_td == 2)
1595 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1596
1597 mutex_unlock(&dev->lb_mutex);
1598 return err;
1599}
1600
1601static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1602{
cfdeb893
LR		 1603 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1604 return;
1605
c85023e1
HN		 1606 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1607
1608 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1609 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1610 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1611 return;
1612
1613 mutex_lock(&dev->lb_mutex);
1614 dev->user_td--;
1615
1616 if (dev->user_td < 2)
1617 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1618
1619 mutex_unlock(&dev->lb_mutex);
1620}
1621
e126ba97
EC		 1622static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1623 struct ib_udata *udata)
1624{
1625 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1626 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1627 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1628 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1629 struct mlx5_ib_ucontext *context;
2f5ff264 1630 struct mlx5_bfreg_info *bfregi;
78c0f98c 1631 int ver;
e126ba97 1632 int err;
a168a41c
MD		 1633 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1634 max_cqe_version);
b037c29a 1635 bool lib_uar_4k;
e126ba97
EC		 1636
1637 if (!dev->ib_active)
1638 return ERR_PTR(-EAGAIN);
1639
e093111d 1640 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1641 ver = 0;
e093111d 1642 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1643 ver = 2;
1644 else
1645 return ERR_PTR(-EINVAL);
1646
e093111d 1647 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1648 if (err)
1649 return ERR_PTR(err);
1650
a8b92ca1
YH		 1651 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1652 return ERR_PTR(-EOPNOTSUPP);
78c0f98c 1653
f72300c5 1654 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1655 return ERR_PTR(-EOPNOTSUPP);
1656
2f5ff264
EC		 1657 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1658 MLX5_NON_FP_BFREGS_PER_UAR);
1659 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1660 return ERR_PTR(-EINVAL);
1661
938fe83c 1662 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1663 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1664 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1665 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1666 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1667 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1668 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1669 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1670 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1671 resp.cqe_version = min_t(__u8,
1672 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1673 req.max_cqe_version);
30aa60b3
EC		 1674 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1675 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1676 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1677 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1678 resp.response_length = min(offsetof(typeof(resp), response_length) +
1679 sizeof(resp.response_length), udata->outlen);
e126ba97 1680
c03faa56
MB		 1681 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1682 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1683 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1684 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1685 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1686 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1687 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1688 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1689 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1690 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1691 }
1692
e126ba97
EC		 1693 context = kzalloc(sizeof(*context), GFP_KERNEL);
1694 if (!context)
1695 return ERR_PTR(-ENOMEM);
1696
30aa60b3 1697 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1698 bfregi = &context->bfregi;
b037c29a
EC		 1699
1700 /* updates req->total_num_bfregs */
31a78a5a 1701 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1702 if (err)
e126ba97 1703 goto out_ctx;
e126ba97 1704
b037c29a
EC		 1705 mutex_init(&bfregi->lock);
1706 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1707 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1708 GFP_KERNEL);
b037c29a 1709 if (!bfregi->count) {
e126ba97 1710 err = -ENOMEM;
b037c29a 1711 goto out_ctx;
e126ba97
EC		 1712 }
1713
b037c29a
EC		 1714 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1715 sizeof(*bfregi->sys_pages),
1716 GFP_KERNEL);
1717 if (!bfregi->sys_pages) {
e126ba97 1718 err = -ENOMEM;
b037c29a 1719 goto out_count;
e126ba97
EC		 1720 }
1721
b037c29a
EC		 1722 err = allocate_uars(dev, context);
1723 if (err)
1724 goto out_sys_pages;
e126ba97 1725
b4cfe447
HE		 1726#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1727 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1728#endif
1729
cfdeb893
LR		 1730 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1731 if (err)
1732 goto out_uars;
146d2f1a 1733
a8b92ca1
YH		 1734 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1735 /* Block DEVX on Infiniband as of SELinux */
1736 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1737 err = -EPERM;
1738 goto out_td;
1739 }
1740
1741 err = mlx5_ib_devx_create(dev, context);
1742 if (err)
1743 goto out_td;
1744 }
1745
7c2344c3 1746 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1747 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1748 INIT_LIST_HEAD(&context->db_page_list);
1749 mutex_init(&context->db_page_mutex);
1750
2f5ff264 1751 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1752 resp.num_ports = dev->num_ports;
b368d7cb 1753
f72300c5
HA		 1754 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1755 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1756
402ca536 1757 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1758 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1759 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1760 resp.response_length += sizeof(resp.cmds_supp_uhw);
1761 }
1762
78984898
OG		 1763 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1764 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1765 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1766 resp.eth_min_inline++;
1767 }
1768 resp.response_length += sizeof(resp.eth_min_inline);
1769 }
1770
5c99eaec
FD		 1771 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1772 if (mdev->clock_info)
1773 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1774 resp.response_length += sizeof(resp.clock_info_versions);
1775 }
1776
bc5c6eed
NO		 1777 /*
1778 * We don't want to expose information from the PCI bar that is located
1779 * after 4096 bytes, so if the arch only supports larger pages, let's
1780 * pretend we don't support reading the HCA's core clock. This is also
1781 * forced by mmap function.
1782 */
de8d6e02
EC		 1783 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1784 if (PAGE_SIZE <= 4096) {
1785 resp.comp_mask |=
1786 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1787 resp.hca_core_clock_offset =
1788 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1789 }
5c99eaec 1790 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1791 }
1792
30aa60b3
EC		 1793 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1794 resp.response_length += sizeof(resp.log_uar_size);
1795
1796 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1797 resp.response_length += sizeof(resp.num_uars_per_page);
1798
31a78a5a
YH		 1799 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1800 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1801 resp.response_length += sizeof(resp.num_dyn_bfregs);
1802 }
1803
b368d7cb 1804 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1805 if (err)
a8b92ca1 1806 goto out_mdev;
e126ba97 1807
2f5ff264
EC		 1808 bfregi->ver = ver;
1809 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1810 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1811 context->lib_caps = req.lib_caps;
1812 print_lib_caps(dev, context->lib_caps);
f72300c5 1813
e126ba97
EC		 1814 return &context->ibucontext;
1815
a8b92ca1
YH		 1816out_mdev:
1817 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1818 mlx5_ib_devx_destroy(dev, context);
146d2f1a 1819out_td:
cfdeb893 1820 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1821
e126ba97 1822out_uars:
b037c29a 1823 deallocate_uars(dev, context);
e126ba97 1824
b037c29a
EC		 1825out_sys_pages:
1826 kfree(bfregi->sys_pages);
e126ba97 1827
b037c29a
EC		 1828out_count:
1829 kfree(bfregi->count);
e126ba97
EC		 1830
1831out_ctx:
1832 kfree(context);
b037c29a 1833
e126ba97
EC		 1834 return ERR_PTR(err);
1835}
1836
1837static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1838{
1839 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1840 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1841 struct mlx5_bfreg_info *bfregi;
e126ba97 1842
a8b92ca1
YH		 1843 if (context->devx_uid)
1844 mlx5_ib_devx_destroy(dev, context);
1845
b037c29a 1846 bfregi = &context->bfregi;
cfdeb893 1847 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1848
b037c29a
EC		 1849 deallocate_uars(dev, context);
1850 kfree(bfregi->sys_pages);
2f5ff264 1851 kfree(bfregi->count);
e126ba97
EC		 1852 kfree(context);
1853
1854 return 0;
1855}
1856
b037c29a 1857static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1858 int uar_idx)
e126ba97 1859{
b037c29a
EC		 1860 int fw_uars_per_page;
1861
1862 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1863
4ed131d0 1864 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1865}
1866
1867static int get_command(unsigned long offset)
1868{
1869 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1870}
1871
1872static int get_arg(unsigned long offset)
1873{
1874 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1875}
1876
1877static int get_index(unsigned long offset)
1878{
1879 return get_arg(offset);
1880}
1881
4ed131d0
YH		 1882/* Index resides in an extra byte to enable larger values than 255 */
1883static int get_extended_index(unsigned long offset)
1884{
1885 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1886}
1887
7c2344c3
MG		 1888static void mlx5_ib_vma_open(struct vm_area_struct *area)
1889{
1890 /* vma_open is called when a new VMA is created on top of our VMA. This
1891 * is done through either mremap flow or split_vma (usually due to
1892 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1893 * as this VMA is strongly hardware related. Therefore we set the
1894 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1895 * calling us again and trying to do incorrect actions. We assume that
1896 * the original VMA size is exactly a single page, and therefore all
1897 * "splitting" operation will not happen to it.
1898 */
1899 area->vm_ops = NULL;
1900}
1901
1902static void mlx5_ib_vma_close(struct vm_area_struct *area)
1903{
1904 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1905
1906 /* It's guaranteed that all VMAs opened on a FD are closed before the
1907 * file itself is closed, therefore no sync is needed with the regular
1908 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1909 * However need a sync with accessing the vma as part of
1910 * mlx5_ib_disassociate_ucontext.
1911 * The close operation is usually called under mm->mmap_sem except when
1912 * process is exiting.
1913 * The exiting case is handled explicitly as part of
1914 * mlx5_ib_disassociate_ucontext.
1915 */
1916 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1917
1918 /* setting the vma context pointer to null in the mlx5_ib driver's
1919 * private data, to protect a race condition in
1920 * mlx5_ib_disassociate_ucontext().
1921 */
1922 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1923 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1924 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1925 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1926 kfree(mlx5_ib_vma_priv_data);
1927}
1928
1929static const struct vm_operations_struct mlx5_ib_vm_ops = {
1930 .open = mlx5_ib_vma_open,
1931 .close = mlx5_ib_vma_close
1932};
1933
1934static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1935 struct mlx5_ib_ucontext *ctx)
1936{
1937 struct mlx5_ib_vma_private_data *vma_prv;
1938 struct list_head *vma_head = &ctx->vma_private_list;
1939
1940 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1941 if (!vma_prv)
1942 return -ENOMEM;
1943
1944 vma_prv->vma = vma;
ad9a3668 1945 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1946 vma->vm_private_data = vma_prv;
1947 vma->vm_ops = &mlx5_ib_vm_ops;
1948
ad9a3668 1949 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1950 list_add(&vma_prv->list, vma_head);
ad9a3668 1951 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1952
1953 return 0;
1954}
1955
1956static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1957{
7c2344c3
MG		 1958 struct vm_area_struct *vma;
1959 struct mlx5_ib_vma_private_data *vma_private, *n;
1960 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
7c2344c3 1961
ad9a3668 1962 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1963 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1964 list) {
1965 vma = vma_private->vma;
2cb40791 1966 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
7c2344c3
MG		 1967 /* context going to be destroyed, should
1968 * not access ops any more.
1969 */
13776612 1970 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1971 vma->vm_ops = NULL;
1972 list_del(&vma_private->list);
1973 kfree(vma_private);
1974 }
ad9a3668 1975 mutex_unlock(&context->vma_private_list_mutex);
7c2344c3
MG		 1976}
1977
37aa5c36
GL		 1978static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1979{
1980 switch (cmd) {
1981 case MLX5_IB_MMAP_WC_PAGE:
1982 return "WC";
1983 case MLX5_IB_MMAP_REGULAR_PAGE:
1984 return "best effort WC";
1985 case MLX5_IB_MMAP_NC_PAGE:
1986 return "NC";
24da0016
AL		 1987 case MLX5_IB_MMAP_DEVICE_MEM:
1988 return "Device Memory";
37aa5c36
GL		 1989 default:
1990 return NULL;
1991 }
1992}
1993
5c99eaec
FD		 1994static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1995 struct vm_area_struct *vma,
1996 struct mlx5_ib_ucontext *context)
1997{
1998 phys_addr_t pfn;
1999 int err;
2000
2001 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2002 return -EINVAL;
2003
2004 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2005 return -EOPNOTSUPP;
2006
2007 if (vma->vm_flags & VM_WRITE)
2008 return -EPERM;
2009
2010 if (!dev->mdev->clock_info_page)
2011 return -EOPNOTSUPP;
2012
2013 pfn = page_to_pfn(dev->mdev->clock_info_page);
2014 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2015 vma->vm_page_prot);
2016 if (err)
2017 return err;
2018
5c99eaec
FD		 2019 return mlx5_ib_set_vma_data(vma, context);
2020}
2021
37aa5c36 2022static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2023 struct vm_area_struct *vma,
2024 struct mlx5_ib_ucontext *context)
37aa5c36 2025{
2f5ff264 2026 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2027 int err;
2028 unsigned long idx;
2029 phys_addr_t pfn, pa;
2030 pgprot_t prot;
4ed131d0
YH		 2031 u32 bfreg_dyn_idx = 0;
2032 u32 uar_index;
2033 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2034 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2035 bfregi->num_static_sys_pages;
b037c29a
EC		 2036
2037 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2038 return -EINVAL;
2039
4ed131d0
YH		 2040 if (dyn_uar)
2041 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2042 else
2043 idx = get_index(vma->vm_pgoff);
2044
2045 if (idx >= max_valid_idx) {
2046 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2047 idx, max_valid_idx);
b037c29a
EC		 2048 return -EINVAL;
2049 }
37aa5c36
GL		 2050
2051 switch (cmd) {
2052 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2053 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2054/* Some architectures don't support WC memory */
2055#if defined(CONFIG_X86)
2056 if (!pat_enabled())
2057 return -EPERM;
2058#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2059 return -EPERM;
2060#endif
2061 /* fall through */
2062 case MLX5_IB_MMAP_REGULAR_PAGE:
2063 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2064 prot = pgprot_writecombine(vma->vm_page_prot);
2065 break;
2066 case MLX5_IB_MMAP_NC_PAGE:
2067 prot = pgprot_noncached(vma->vm_page_prot);
2068 break;
2069 default:
2070 return -EINVAL;
2071 }
2072
4ed131d0
YH		 2073 if (dyn_uar) {
2074 int uars_per_page;
2075
2076 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2077 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2078 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2079 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2080 bfreg_dyn_idx, bfregi->total_num_bfregs);
2081 return -EINVAL;
2082 }
2083
2084 mutex_lock(&bfregi->lock);
2085 /* Fail if uar already allocated, first bfreg index of each
2086 * page holds its count.
2087 */
2088 if (bfregi->count[bfreg_dyn_idx]) {
2089 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2090 mutex_unlock(&bfregi->lock);
2091 return -EINVAL;
2092 }
2093
2094 bfregi->count[bfreg_dyn_idx]++;
2095 mutex_unlock(&bfregi->lock);
2096
2097 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2098 if (err) {
2099 mlx5_ib_warn(dev, "UAR alloc failed\n");
2100 goto free_bfreg;
2101 }
2102 } else {
2103 uar_index = bfregi->sys_pages[idx];
2104 }
2105
2106 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2107 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2108
2109 vma->vm_page_prot = prot;
2110 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2111 PAGE_SIZE, vma->vm_page_prot);
2112 if (err) {
8f062287
LR		 2113 mlx5_ib_err(dev,
2114 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2115 err, mmap_cmd2str(cmd));
4ed131d0
YH		 2116 err = -EAGAIN;
2117 goto err;
37aa5c36
GL		 2118 }
2119
2120 pa = pfn << PAGE_SHIFT;
37aa5c36 2121
4ed131d0
YH		 2122 err = mlx5_ib_set_vma_data(vma, context);
2123 if (err)
2124 goto err;
2125
2126 if (dyn_uar)
2127 bfregi->sys_pages[idx] = uar_index;
2128 return 0;
2129
2130err:
2131 if (!dyn_uar)
2132 return err;
2133
2134 mlx5_cmd_free_uar(dev->mdev, idx);
2135
2136free_bfreg:
2137 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2138
2139 return err;
37aa5c36
GL		 2140}
2141
24da0016
AL		 2142static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2143{
2144 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2145 struct mlx5_ib_dev *dev = to_mdev(context->device);
2146 u16 page_idx = get_extended_index(vma->vm_pgoff);
2147 size_t map_size = vma->vm_end - vma->vm_start;
2148 u32 npages = map_size >> PAGE_SHIFT;
2149 phys_addr_t pfn;
2150 pgprot_t prot;
2151
2152 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2153 page_idx + npages)
2154 return -EINVAL;
2155
2156 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2157 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2158 PAGE_SHIFT) +
2159 page_idx;
2160 prot = pgprot_writecombine(vma->vm_page_prot);
2161 vma->vm_page_prot = prot;
2162
2163 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2164 vma->vm_page_prot))
2165 return -EAGAIN;
2166
2167 return mlx5_ib_set_vma_data(vma, mctx);
2168}
2169
e126ba97
EC		 2170static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2171{
2172 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2173 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2174 unsigned long command;
e126ba97
EC		 2175 phys_addr_t pfn;
2176
2177 command = get_command(vma->vm_pgoff);
2178 switch (command) {
37aa5c36
GL		 2179 case MLX5_IB_MMAP_WC_PAGE:
2180 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2181 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2182 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2183 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2184
2185 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2186 return -ENOSYS;
2187
d69e3bcf 2188 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2189 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2190 return -EINVAL;
2191
6cbac1e4 2192 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2193 return -EPERM;
2194
2195 /* Don't expose to user-space information it shouldn't have */
2196 if (PAGE_SIZE > 4096)
2197 return -EOPNOTSUPP;
2198
2199 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2200 pfn = (dev->mdev->iseg_base +
2201 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2202 PAGE_SHIFT;
2203 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2204 PAGE_SIZE, vma->vm_page_prot))
2205 return -EAGAIN;
d69e3bcf 2206 break;
5c99eaec
FD		 2207 case MLX5_IB_MMAP_CLOCK_INFO:
2208 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2209
24da0016
AL		 2210 case MLX5_IB_MMAP_DEVICE_MEM:
2211 return dm_mmap(ibcontext, vma);
2212
e126ba97
EC		 2213 default:
2214 return -EINVAL;
2215 }
2216
2217 return 0;
2218}
2219
24da0016
AL		 2220struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2221 struct ib_ucontext *context,
2222 struct ib_dm_alloc_attr *attr,
2223 struct uverbs_attr_bundle *attrs)
2224{
2225 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2226 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2227 phys_addr_t memic_addr;
2228 struct mlx5_ib_dm *dm;
2229 u64 start_offset;
2230 u32 page_idx;
2231 int err;
2232
2233 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2234 if (!dm)
2235 return ERR_PTR(-ENOMEM);
2236
2237 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2238 attr->length, act_size, attr->alignment);
2239
2240 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2241 act_size, attr->alignment);
2242 if (err)
2243 goto err_free;
2244
2245 start_offset = memic_addr & ~PAGE_MASK;
2246 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2247 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2248 PAGE_SHIFT;
2249
2250 err = uverbs_copy_to(attrs,
2251 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2252 &start_offset, sizeof(start_offset));
2253 if (err)
2254 goto err_dealloc;
2255
2256 err = uverbs_copy_to(attrs,
2257 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2258 &page_idx, sizeof(page_idx));
2259 if (err)
2260 goto err_dealloc;
2261
2262 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2263 DIV_ROUND_UP(act_size, PAGE_SIZE));
2264
2265 dm->dev_addr = memic_addr;
2266
2267 return &dm->ibdm;
2268
2269err_dealloc:
2270 mlx5_cmd_dealloc_memic(memic, memic_addr,
2271 act_size);
2272err_free:
2273 kfree(dm);
2274 return ERR_PTR(err);
2275}
2276
2277int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2278{
2279 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2280 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2281 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2282 u32 page_idx;
2283 int ret;
2284
2285 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2286 if (ret)
2287 return ret;
2288
2289 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2290 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2291 PAGE_SHIFT;
2292 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2293 page_idx,
2294 DIV_ROUND_UP(act_size, PAGE_SIZE));
2295
2296 kfree(dm);
2297
2298 return 0;
2299}
2300
e126ba97
EC		 2301static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2302 struct ib_ucontext *context,
2303 struct ib_udata *udata)
2304{
2305 struct mlx5_ib_alloc_pd_resp resp;
2306 struct mlx5_ib_pd *pd;
2307 int err;
2308
2309 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2310 if (!pd)
2311 return ERR_PTR(-ENOMEM);
2312
9603b61d 2313 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2314 if (err) {
2315 kfree(pd);
2316 return ERR_PTR(err);
2317 }
2318
2319 if (context) {
2320 resp.pdn = pd->pdn;
2321 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2322 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2323 kfree(pd);
2324 return ERR_PTR(-EFAULT);
2325 }
e126ba97
EC		 2326 }
2327
2328 return &pd->ibpd;
2329}
2330
2331static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2332{
2333 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2334 struct mlx5_ib_pd *mpd = to_mpd(pd);
2335
9603b61d 2336 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2337 kfree(mpd);
2338
2339 return 0;
2340}
2341
466fa6d2
MG		 2342enum {
2343 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2344 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2345 MATCH_CRITERIA_ENABLE_INNER_BIT,
2346 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2347};
2348
2349#define HEADER_IS_ZERO(match_criteria, headers) \
2350 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2351 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2352
466fa6d2 2353static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2354{
466fa6d2 2355 u8 match_criteria_enable;
038d2ef8 2356
466fa6d2
MG		 2357 match_criteria_enable =
2358 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2359 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2360 match_criteria_enable |=
2361 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2362 MATCH_CRITERIA_ENABLE_MISC_BIT;
2363 match_criteria_enable |=
2364 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2365 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2366 match_criteria_enable |=
2367 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2368 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2369
2370 return match_criteria_enable;
038d2ef8
MG		 2371}
2372
ca0d4753
MG		 2373static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2374{
2375 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2376 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2377}
2378
37da2a03 2379static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2380 bool inner)
2381{
2382 if (inner) {
2383 MLX5_SET(fte_match_set_misc,
2384 misc_c, inner_ipv6_flow_label, mask);
2385 MLX5_SET(fte_match_set_misc,
2386 misc_v, inner_ipv6_flow_label, val);
2387 } else {
2388 MLX5_SET(fte_match_set_misc,
2389 misc_c, outer_ipv6_flow_label, mask);
2390 MLX5_SET(fte_match_set_misc,
2391 misc_v, outer_ipv6_flow_label, val);
2392 }
2393}
2394
ca0d4753
MG		 2395static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2396{
2397 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2398 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2399 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2400 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2401}
2402
71c6e863
AL		 2403static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2404{
2405 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2406 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2407 return -EOPNOTSUPP;
2408
2409 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2410 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2411 return -EOPNOTSUPP;
2412
2413 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2414 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2415 return -EOPNOTSUPP;
2416
2417 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2418 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2419 return -EOPNOTSUPP;
2420
2421 return 0;
2422}
2423
c47ac6ae
MG		 2424#define LAST_ETH_FIELD vlan_tag
2425#define LAST_IB_FIELD sl
ca0d4753 2426#define LAST_IPV4_FIELD tos
466fa6d2 2427#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2428#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2429#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2430#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2431#define LAST_DROP_FIELD size
3b3233fb 2432#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2433
2434/* Field is the last supported field */
2435#define FIELDS_NOT_SUPPORTED(filter, field)\
2436 memchr_inv((void *)&filter.field +\
2437 sizeof(filter.field), 0,\
2438 sizeof(filter) -\
2439 offsetof(typeof(filter), field) -\
2440 sizeof(filter.field))
2441
802c2125
AY		 2442static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2443 const struct ib_flow_attr *flow_attr,
2444 struct mlx5_flow_act *action)
2445{
2446 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2447
2448 switch (maction->ib_action.type) {
2449 case IB_FLOW_ACTION_ESP:
2450 /* Currently only AES_GCM keymat is supported by the driver */
2451 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2452 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2453 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2454 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2455 return 0;
2456 default:
2457 return -EOPNOTSUPP;
2458 }
2459}
2460
19cc7524
AL		 2461static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2462 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2463 const struct ib_flow_attr *flow_attr,
71c6e863 2464 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2465{
466fa6d2
MG		 2466 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2467 misc_parameters);
2468 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2469 misc_parameters);
71c6e863
AL		 2470 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2471 misc_parameters_2);
2472 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2473 misc_parameters_2);
2d1e697e
MR		 2474 void *headers_c;
2475 void *headers_v;
19cc7524 2476 int match_ipv;
802c2125 2477 int ret;
2d1e697e
MR		 2478
2479 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2480 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2481 inner_headers);
2482 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2483 inner_headers);
19cc7524
AL		 2484 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2485 ft_field_support.inner_ip_version);
2d1e697e
MR		 2486 } else {
2487 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2488 outer_headers);
2489 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2490 outer_headers);
19cc7524
AL		 2491 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2492 ft_field_support.outer_ip_version);
2d1e697e 2493 }
466fa6d2 2494
2d1e697e 2495 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2496 case IB_FLOW_SPEC_ETH:
c47ac6ae 2497 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2498 return -EOPNOTSUPP;
038d2ef8 2499
2d1e697e 2500 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2501 dmac_47_16),
2502 ib_spec->eth.mask.dst_mac);
2d1e697e 2503 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2504 dmac_47_16),
2505 ib_spec->eth.val.dst_mac);
2506
2d1e697e 2507 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2508 smac_47_16),
2509 ib_spec->eth.mask.src_mac);
2d1e697e 2510 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2511 smac_47_16),
2512 ib_spec->eth.val.src_mac);
2513
038d2ef8 2514 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2515 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2516 cvlan_tag, 1);
2d1e697e 2517 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2518 cvlan_tag, 1);
038d2ef8 2519
2d1e697e 2520 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2521 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2522 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2523 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2524
2d1e697e 2525 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2526 first_cfi,
2527 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2528 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2529 first_cfi,
2530 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2531
2d1e697e 2532 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2533 first_prio,
2534 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2535 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2536 first_prio,
2537 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2538 }
2d1e697e 2539 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2540 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2541 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2542 ethertype, ntohs(ib_spec->eth.val.ether_type));
2543 break;
2544 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2545 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2546 return -EOPNOTSUPP;
038d2ef8 2547
19cc7524
AL		 2548 if (match_ipv) {
2549 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2550 ip_version, 0xf);
2551 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2552 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2553 } else {
2554 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2555 ethertype, 0xffff);
2556 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2557 ethertype, ETH_P_IP);
2558 }
038d2ef8 2559
2d1e697e 2560 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2561 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2562 &ib_spec->ipv4.mask.src_ip,
2563 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2564 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2565 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2566 &ib_spec->ipv4.val.src_ip,
2567 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2568 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2569 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2570 &ib_spec->ipv4.mask.dst_ip,
2571 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2572 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2573 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2574 &ib_spec->ipv4.val.dst_ip,
2575 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2576
2d1e697e 2577 set_tos(headers_c, headers_v,
ca0d4753
MG		 2578 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2579
2d1e697e 2580 set_proto(headers_c, headers_v,
ca0d4753 2581 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2582 break;
026bae0c 2583 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2584 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2585 return -EOPNOTSUPP;
026bae0c 2586
19cc7524
AL		 2587 if (match_ipv) {
2588 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2589 ip_version, 0xf);
2590 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2591 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2592 } else {
2593 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2594 ethertype, 0xffff);
2595 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2596 ethertype, ETH_P_IPV6);
2597 }
026bae0c 2598
2d1e697e 2599 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2600 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2601 &ib_spec->ipv6.mask.src_ip,
2602 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2603 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2604 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2605 &ib_spec->ipv6.val.src_ip,
2606 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2607 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2608 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2609 &ib_spec->ipv6.mask.dst_ip,
2610 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2611 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2612 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2613 &ib_spec->ipv6.val.dst_ip,
2614 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2615
2d1e697e 2616 set_tos(headers_c, headers_v,
466fa6d2
MG		 2617 ib_spec->ipv6.mask.traffic_class,
2618 ib_spec->ipv6.val.traffic_class);
2619
2d1e697e 2620 set_proto(headers_c, headers_v,
466fa6d2
MG		 2621 ib_spec->ipv6.mask.next_hdr,
2622 ib_spec->ipv6.val.next_hdr);
2623
2d1e697e
MR		 2624 set_flow_label(misc_params_c, misc_params_v,
2625 ntohl(ib_spec->ipv6.mask.flow_label),
2626 ntohl(ib_spec->ipv6.val.flow_label),
2627 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2628 break;
2629 case IB_FLOW_SPEC_ESP:
2630 if (ib_spec->esp.mask.seq)
2631 return -EOPNOTSUPP;
2d1e697e 2632
802c2125
AY		 2633 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2634 ntohl(ib_spec->esp.mask.spi));
2635 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2636 ntohl(ib_spec->esp.val.spi));
026bae0c 2637 break;
038d2ef8 2638 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2639 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2640 LAST_TCP_UDP_FIELD))
1ffd3a26 2641 return -EOPNOTSUPP;
038d2ef8 2642
2d1e697e 2643 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2644 0xff);
2d1e697e 2645 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2646 IPPROTO_TCP);
2647
2d1e697e 2648 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2649 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2650 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2651 ntohs(ib_spec->tcp_udp.val.src_port));
2652
2d1e697e 2653 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2654 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2655 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2656 ntohs(ib_spec->tcp_udp.val.dst_port));
2657 break;
2658 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2659 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2660 LAST_TCP_UDP_FIELD))
1ffd3a26 2661 return -EOPNOTSUPP;
038d2ef8 2662
2d1e697e 2663 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2664 0xff);
2d1e697e 2665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2666 IPPROTO_UDP);
2667
2d1e697e 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2669 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2671 ntohs(ib_spec->tcp_udp.val.src_port));
2672
2d1e697e 2673 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2674 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2675 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2676 ntohs(ib_spec->tcp_udp.val.dst_port));
2677 break;
da2f22ae
AL		 2678 case IB_FLOW_SPEC_GRE:
2679 if (ib_spec->gre.mask.c_ks_res0_ver)
2680 return -EOPNOTSUPP;
2681
2682 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2683 0xff);
2684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2685 IPPROTO_GRE);
2686
2687 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2688 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2689 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2690 ntohs(ib_spec->gre.val.protocol));
2691
2692 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2693 gre_key_h),
2694 &ib_spec->gre.mask.key,
2695 sizeof(ib_spec->gre.mask.key));
2696 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2697 gre_key_h),
2698 &ib_spec->gre.val.key,
2699 sizeof(ib_spec->gre.val.key));
2700 break;
71c6e863
AL		 2701 case IB_FLOW_SPEC_MPLS:
2702 switch (prev_type) {
2703 case IB_FLOW_SPEC_UDP:
2704 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2705 ft_field_support.outer_first_mpls_over_udp),
2706 &ib_spec->mpls.mask.tag))
2707 return -EOPNOTSUPP;
2708
2709 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2710 outer_first_mpls_over_udp),
2711 &ib_spec->mpls.val.tag,
2712 sizeof(ib_spec->mpls.val.tag));
2713 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2714 outer_first_mpls_over_udp),
2715 &ib_spec->mpls.mask.tag,
2716 sizeof(ib_spec->mpls.mask.tag));
2717 break;
2718 case IB_FLOW_SPEC_GRE:
2719 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2720 ft_field_support.outer_first_mpls_over_gre),
2721 &ib_spec->mpls.mask.tag))
2722 return -EOPNOTSUPP;
2723
2724 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2725 outer_first_mpls_over_gre),
2726 &ib_spec->mpls.val.tag,
2727 sizeof(ib_spec->mpls.val.tag));
2728 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2729 outer_first_mpls_over_gre),
2730 &ib_spec->mpls.mask.tag,
2731 sizeof(ib_spec->mpls.mask.tag));
2732 break;
2733 default:
2734 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2735 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2736 ft_field_support.inner_first_mpls),
2737 &ib_spec->mpls.mask.tag))
2738 return -EOPNOTSUPP;
2739
2740 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2741 inner_first_mpls),
2742 &ib_spec->mpls.val.tag,
2743 sizeof(ib_spec->mpls.val.tag));
2744 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2745 inner_first_mpls),
2746 &ib_spec->mpls.mask.tag,
2747 sizeof(ib_spec->mpls.mask.tag));
2748 } else {
2749 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2750 ft_field_support.outer_first_mpls),
2751 &ib_spec->mpls.mask.tag))
2752 return -EOPNOTSUPP;
2753
2754 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2755 outer_first_mpls),
2756 &ib_spec->mpls.val.tag,
2757 sizeof(ib_spec->mpls.val.tag));
2758 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2759 outer_first_mpls),
2760 &ib_spec->mpls.mask.tag,
2761 sizeof(ib_spec->mpls.mask.tag));
2762 }
2763 }
2764 break;
ffb30d8f
MR		 2765 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2766 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2767 LAST_TUNNEL_FIELD))
1ffd3a26 2768 return -EOPNOTSUPP;
ffb30d8f
MR		 2769
2770 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2771 ntohl(ib_spec->tunnel.mask.tunnel_id));
2772 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2773 ntohl(ib_spec->tunnel.val.tunnel_id));
2774 break;
2ac693f9
MR		 2775 case IB_FLOW_SPEC_ACTION_TAG:
2776 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2777 LAST_FLOW_TAG_FIELD))
2778 return -EOPNOTSUPP;
2779 if (ib_spec->flow_tag.tag_id >= BIT(24))
2780 return -EINVAL;
2781
075572d4 2782 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2783 action->has_flow_tag = true;
2ac693f9 2784 break;
a22ed86c
SS		 2785 case IB_FLOW_SPEC_ACTION_DROP:
2786 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2787 LAST_DROP_FIELD))
2788 return -EOPNOTSUPP;
075572d4 2789 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2790 break;
802c2125
AY		 2791 case IB_FLOW_SPEC_ACTION_HANDLE:
2792 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2793 if (ret)
2794 return ret;
2795 break;
3b3233fb
RS		 2796 case IB_FLOW_SPEC_ACTION_COUNT:
2797 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2798 LAST_COUNTERS_FIELD))
2799 return -EOPNOTSUPP;
2800
2801 /* for now support only one counters spec per flow */
2802 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2803 return -EINVAL;
2804
2805 action->counters = ib_spec->flow_count.counters;
2806 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2807 break;
038d2ef8
MG		 2808 default:
2809 return -EINVAL;
2810 }
2811
2812 return 0;
2813}
2814
2815/* If a flow could catch both multicast and unicast packets,
2816 * it won't fall into the multicast flow steering table and this rule
2817 * could steal other multicast packets.
2818 */
a550ddfc 2819static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2820{
81e30880 2821 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2822
2823 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2824 ib_attr->num_of_specs < 1)
2825 return false;
2826
81e30880
YH		 2827 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2828 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2829 struct ib_flow_spec_ipv4 *ipv4_spec;
2830
2831 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2832 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2833 return true;
2834
038d2ef8 2835 return false;
81e30880
YH		 2836 }
2837
2838 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2839 struct ib_flow_spec_eth *eth_spec;
2840
2841 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2842 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2843 is_multicast_ether_addr(eth_spec->val.dst_mac);
2844 }
038d2ef8 2845
81e30880 2846 return false;
038d2ef8
MG		 2847}
2848
802c2125
AY		 2849enum valid_spec {
2850 VALID_SPEC_INVALID,
2851 VALID_SPEC_VALID,
2852 VALID_SPEC_NA,
2853};
2854
2855static enum valid_spec
2856is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2857 const struct mlx5_flow_spec *spec,
2858 const struct mlx5_flow_act *flow_act,
2859 bool egress)
2860{
2861 const u32 *match_c = spec->match_criteria;
2862 bool is_crypto =
2863 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2864 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2865 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2866 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2867
2868 /*
2869 * Currently only crypto is supported in egress, when regular egress
2870 * rules would be supported, always return VALID_SPEC_NA.
2871 */
2872 if (!is_crypto)
2873 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2874
2875 return is_crypto && is_ipsec &&
2876 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2877 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2878}
2879
2880static bool is_valid_spec(struct mlx5_core_dev *mdev,
2881 const struct mlx5_flow_spec *spec,
2882 const struct mlx5_flow_act *flow_act,
2883 bool egress)
2884{
2885 /* We curretly only support ipsec egress flow */
2886 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2887}
2888
19cc7524
AL		 2889static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2890 const struct ib_flow_attr *flow_attr,
0f750966 2891 bool check_inner)
038d2ef8
MG		 2892{
2893 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2894 int match_ipv = check_inner ?
2895 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2896 ft_field_support.inner_ip_version) :
2897 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2898 ft_field_support.outer_ip_version);
0f750966
AL		 2899 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2900 bool ipv4_spec_valid, ipv6_spec_valid;
2901 unsigned int ip_spec_type = 0;
2902 bool has_ethertype = false;
038d2ef8 2903 unsigned int spec_index;
0f750966
AL		 2904 bool mask_valid = true;
2905 u16 eth_type = 0;
2906 bool type_valid;
038d2ef8
MG		 2907
2908 /* Validate that ethertype is correct */
2909 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2910 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2911 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2912 mask_valid = (ib_spec->eth.mask.ether_type ==
2913 htons(0xffff));
2914 has_ethertype = true;
2915 eth_type = ntohs(ib_spec->eth.val.ether_type);
2916 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2917 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2918 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2919 }
2920 ib_spec = (void *)ib_spec + ib_spec->size;
2921 }
0f750966
AL		 2922
2923 type_valid = (!has_ethertype) || (!ip_spec_type);
2924 if (!type_valid && mask_valid) {
2925 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2926 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2927 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2928 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2929
2930 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2931 (((eth_type == ETH_P_MPLS_UC) ||
2932 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2933 }
2934
2935 return type_valid;
2936}
2937
19cc7524
AL		 2938static bool is_valid_attr(struct mlx5_core_dev *mdev,
2939 const struct ib_flow_attr *flow_attr)
0f750966 2940{
19cc7524
AL		 2941 return is_valid_ethertype(mdev, flow_attr, false) &&
2942 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2943}
2944
2945static void put_flow_table(struct mlx5_ib_dev *dev,
2946 struct mlx5_ib_flow_prio *prio, bool ft_added)
2947{
2948 prio->refcount -= !!ft_added;
2949 if (!prio->refcount) {
2950 mlx5_destroy_flow_table(prio->flow_table);
2951 prio->flow_table = NULL;
2952 }
2953}
2954
3b3233fb
RS		 2955static void counters_clear_description(struct ib_counters *counters)
2956{
2957 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2958
2959 mutex_lock(&mcounters->mcntrs_mutex);
2960 kfree(mcounters->counters_data);
2961 mcounters->counters_data = NULL;
2962 mcounters->cntrs_max_index = 0;
2963 mutex_unlock(&mcounters->mcntrs_mutex);
2964}
2965
038d2ef8
MG		 2966static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2967{
2968 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2969 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2970 struct mlx5_ib_flow_handler,
2971 ibflow);
2972 struct mlx5_ib_flow_handler *iter, *tmp;
2973
9a4ca38d 2974 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2975
2976 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2977 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2978 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2979 list_del(&iter->list);
2980 kfree(iter);
2981 }
2982
74491de9 2983 mlx5_del_flow_rules(handler->rule);
5497adc6 2984 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 2985 if (handler->ibcounters &&
2986 atomic_read(&handler->ibcounters->usecnt) == 1)
2987 counters_clear_description(handler->ibcounters);
038d2ef8 2988
3b3233fb 2989 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 2990 kfree(handler);
2991
2992 return 0;
2993}
2994
35d19011
MG		 2995static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2996{
2997 priority *= 2;
2998 if (!dont_trap)
2999 priority++;
3000 return priority;
3001}
3002
cc0e5d42
MG		 3003enum flow_table_type {
3004 MLX5_IB_FT_RX,
3005 MLX5_IB_FT_TX
3006};
3007
00b7c2ab
MG		 3008#define MLX5_FS_MAX_TYPES 6
3009#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 3010static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3011 struct ib_flow_attr *flow_attr,
3012 enum flow_table_type ft_type)
038d2ef8 3013{
35d19011 3014 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3015 struct mlx5_flow_namespace *ns = NULL;
3016 struct mlx5_ib_flow_prio *prio;
3017 struct mlx5_flow_table *ft;
dac388ef 3018 int max_table_size;
038d2ef8
MG		 3019 int num_entries;
3020 int num_groups;
3021 int priority;
3022 int err = 0;
3023
dac388ef
MG		 3024 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3025 log_max_ft_size));
038d2ef8 3026 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
802c2125
AY		 3027 if (ft_type == MLX5_IB_FT_TX)
3028 priority = 0;
3029 else if (flow_is_multicast_only(flow_attr) &&
3030 !dont_trap)
038d2ef8
MG		 3031 priority = MLX5_IB_FLOW_MCAST_PRIO;
3032 else
35d19011
MG		 3033 priority = ib_prio_to_core_prio(flow_attr->priority,
3034 dont_trap);
038d2ef8 3035 ns = mlx5_get_flow_namespace(dev->mdev,
802c2125
AY		 3036 ft_type == MLX5_IB_FT_TX ?
3037 MLX5_FLOW_NAMESPACE_EGRESS :
038d2ef8
MG		 3038 MLX5_FLOW_NAMESPACE_BYPASS);
3039 num_entries = MLX5_FS_MAX_ENTRIES;
3040 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 3041 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 3042 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3043 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3044 ns = mlx5_get_flow_namespace(dev->mdev,
3045 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3046 build_leftovers_ft_param(&priority,
3047 &num_entries,
3048 &num_groups);
9a4ca38d 3049 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3050 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3051 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3052 allow_sniffer_and_nic_rx_shared_tir))
3053 return ERR_PTR(-ENOTSUPP);
3054
3055 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3056 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3057 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3058
9a4ca38d 3059 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3060 priority = 0;
3061 num_entries = 1;
3062 num_groups = 1;
038d2ef8
MG		 3063 }
3064
3065 if (!ns)
3066 return ERR_PTR(-ENOTSUPP);
3067
dac388ef
MG		 3068 if (num_entries > max_table_size)
3069 return ERR_PTR(-ENOMEM);
3070
038d2ef8
MG		 3071 ft = prio->flow_table;
3072 if (!ft) {
3073 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3074 num_entries,
d63cd286 3075 num_groups,
c9f1b073 3076 0, 0);
038d2ef8
MG		 3077
3078 if (!IS_ERR(ft)) {
3079 prio->refcount = 0;
3080 prio->flow_table = ft;
3081 } else {
3082 err = PTR_ERR(ft);
3083 }
3084 }
3085
3086 return err ? ERR_PTR(err) : prio;
3087}
3088
a550ddfc
YH		 3089static void set_underlay_qp(struct mlx5_ib_dev *dev,
3090 struct mlx5_flow_spec *spec,
3091 u32 underlay_qpn)
3092{
3093 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3094 spec->match_criteria,
3095 misc_parameters);
3096 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3097 misc_parameters);
3098
3099 if (underlay_qpn &&
3100 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3101 ft_field_support.bth_dst_qp)) {
3102 MLX5_SET(fte_match_set_misc,
3103 misc_params_v, bth_dst_qp, underlay_qpn);
3104 MLX5_SET(fte_match_set_misc,
3105 misc_params_c, bth_dst_qp, 0xffffff);
3106 }
3107}
3108
5e95af5f
RS		 3109static int read_flow_counters(struct ib_device *ibdev,
3110 struct mlx5_read_counters_attr *read_attr)
3111{
3112 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3113 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3114
3115 return mlx5_fc_query(dev->mdev, fc,
3116 &read_attr->out[IB_COUNTER_PACKETS],
3117 &read_attr->out[IB_COUNTER_BYTES]);
3118}
3119
3120/* flow counters currently expose two counters packets and bytes */
3121#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3122static int counters_set_description(struct ib_counters *counters,
3123 enum mlx5_ib_counters_type counters_type,
3124 struct mlx5_ib_flow_counters_desc *desc_data,
3125 u32 ncounters)
3126{
3127 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3128 u32 cntrs_max_index = 0;
3129 int i;
3130
3131 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3132 return -EINVAL;
3133
3134 /* init the fields for the object */
3135 mcounters->type = counters_type;
5e95af5f
RS		 3136 mcounters->read_counters = read_flow_counters;
3137 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3138 mcounters->ncounters = ncounters;
3139 /* each counter entry have both description and index pair */
3140 for (i = 0; i < ncounters; i++) {
3141 if (desc_data[i].description > IB_COUNTER_BYTES)
3142 return -EINVAL;
3143
3144 if (cntrs_max_index <= desc_data[i].index)
3145 cntrs_max_index = desc_data[i].index + 1;
3146 }
3147
3148 mutex_lock(&mcounters->mcntrs_mutex);
3149 mcounters->counters_data = desc_data;
3150 mcounters->cntrs_max_index = cntrs_max_index;
3151 mutex_unlock(&mcounters->mcntrs_mutex);
3152
3153 return 0;
3154}
3155
3156#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3157static int flow_counters_set_data(struct ib_counters *ibcounters,
3158 struct mlx5_ib_create_flow *ucmd)
3159{
3160 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3161 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3162 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3163 bool hw_hndl = false;
3164 int ret = 0;
3165
3166 if (ucmd && ucmd->ncounters_data != 0) {
3167 cntrs_data = ucmd->data;
3168 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3169 return -EINVAL;
3170
3171 desc_data = kcalloc(cntrs_data->ncounters,
3172 sizeof(*desc_data),
3173 GFP_KERNEL);
3174 if (!desc_data)
3175 return -ENOMEM;
3176
3177 if (copy_from_user(desc_data,
3178 u64_to_user_ptr(cntrs_data->counters_data),
3179 sizeof(*desc_data) * cntrs_data->ncounters)) {
3180 ret = -EFAULT;
3181 goto free;
3182 }
3183 }
3184
3185 if (!mcounters->hw_cntrs_hndl) {
3186 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3187 to_mdev(ibcounters->device)->mdev, false);
3188 if (!mcounters->hw_cntrs_hndl) {
3189 ret = -ENOMEM;
3190 goto free;
3191 }
3192 hw_hndl = true;
3193 }
3194
3195 if (desc_data) {
3196 /* counters already bound to at least one flow */
3197 if (mcounters->cntrs_max_index) {
3198 ret = -EINVAL;
3199 goto free_hndl;
3200 }
3201
3202 ret = counters_set_description(ibcounters,
3203 MLX5_IB_COUNTERS_FLOW,
3204 desc_data,
3205 cntrs_data->ncounters);
3206 if (ret)
3207 goto free_hndl;
3208
3209 } else if (!mcounters->cntrs_max_index) {
3210 /* counters not bound yet, must have udata passed */
3211 ret = -EINVAL;
3212 goto free_hndl;
3213 }
3214
3215 return 0;
3216
3217free_hndl:
3218 if (hw_hndl) {
3219 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3220 mcounters->hw_cntrs_hndl);
3221 mcounters->hw_cntrs_hndl = NULL;
3222 }
3223free:
3224 kfree(desc_data);
3225 return ret;
3226}
3227
a550ddfc
YH		 3228static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3229 struct mlx5_ib_flow_prio *ft_prio,
3230 const struct ib_flow_attr *flow_attr,
3231 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3232 u32 underlay_qpn,
3233 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3234{
3235 struct mlx5_flow_table *ft = ft_prio->flow_table;
3236 struct mlx5_ib_flow_handler *handler;
075572d4 3237 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3238 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3239 struct mlx5_flow_destination dest_arr[2] = {};
3240 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3241 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3242 unsigned int spec_index;
71c6e863 3243 u32 prev_type = 0;
038d2ef8 3244 int err = 0;
3b3233fb 3245 int dest_num = 0;
802c2125 3246 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3247
19cc7524 3248 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3249 return ERR_PTR(-EINVAL);
3250
1b9a07ee 3251 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3252 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3253 if (!handler || !spec) {
038d2ef8
MG		 3254 err = -ENOMEM;
3255 goto free;
3256 }
3257
3258 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3259 if (dst) {
3260 memcpy(&dest_arr[0], dst, sizeof(*dst));
3261 dest_num++;
3262 }
038d2ef8
MG		 3263
3264 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3265 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3266 spec->match_value,
71c6e863
AL		 3267 ib_flow, flow_attr, &flow_act,
3268 prev_type);
038d2ef8
MG		 3269 if (err < 0)
3270 goto free;
3271
71c6e863 3272 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3273 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3274 }
3275
a550ddfc
YH		 3276 if (!flow_is_multicast_only(flow_attr))
3277 set_underlay_qp(dev, spec, underlay_qpn);
3278
018a94ee
MB		 3279 if (dev->rep) {
3280 void *misc;
3281
3282 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3283 misc_parameters);
3284 MLX5_SET(fte_match_set_misc, misc, source_port,
3285 dev->rep->vport);
3286 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3287 misc_parameters);
3288 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3289 }
3290
466fa6d2 3291 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3292
3293 if (is_egress &&
3294 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3295 err = -EINVAL;
3296 goto free;
3297 }
3298
3b3233fb
RS		 3299 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3300 err = flow_counters_set_data(flow_act.counters, ucmd);
3301 if (err)
3302 goto free;
3303
3304 handler->ibcounters = flow_act.counters;
3305 dest_arr[dest_num].type =
3306 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3307 dest_arr[dest_num].counter =
3308 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3309 dest_num++;
3310 }
3311
075572d4 3312 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3313 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3314 rule_dst = NULL;
3315 dest_num = 0;
3316 }
a22ed86c 3317 } else {
802c2125
AY		 3318 if (is_egress)
3319 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3320 else
3321 flow_act.action |=
3b3233fb 3322 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3323 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3324 }
2ac693f9 3325
a9db0ecf 3326 if (flow_act.has_flow_tag &&
2ac693f9
MR		 3327 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3328 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3329 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3330 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3331 err = -EINVAL;
3332 goto free;
3333 }
74491de9 3334 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3335 &flow_act,
a22ed86c 3336 rule_dst, dest_num);
038d2ef8
MG		 3337
3338 if (IS_ERR(handler->rule)) {
3339 err = PTR_ERR(handler->rule);
3340 goto free;
3341 }
3342
d9d4980a 3343 ft_prio->refcount++;
5497adc6 3344 handler->prio = ft_prio;
038d2ef8
MG		 3345
3346 ft_prio->flow_table = ft;
3347free:
3b3233fb
RS		 3348 if (err && handler) {
3349 if (handler->ibcounters &&
3350 atomic_read(&handler->ibcounters->usecnt) == 1)
3351 counters_clear_description(handler->ibcounters);
038d2ef8 3352 kfree(handler);
3b3233fb 3353 }
c5bb1730 3354 kvfree(spec);
038d2ef8
MG		 3355 return err ? ERR_PTR(err) : handler;
3356}
3357
a550ddfc
YH		 3358static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3359 struct mlx5_ib_flow_prio *ft_prio,
3360 const struct ib_flow_attr *flow_attr,
3361 struct mlx5_flow_destination *dst)
3362{
3b3233fb 3363 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3364}
3365
35d19011
MG		 3366static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3367 struct mlx5_ib_flow_prio *ft_prio,
3368 struct ib_flow_attr *flow_attr,
3369 struct mlx5_flow_destination *dst)
3370{
3371 struct mlx5_ib_flow_handler *handler_dst = NULL;
3372 struct mlx5_ib_flow_handler *handler = NULL;
3373
3374 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3375 if (!IS_ERR(handler)) {
3376 handler_dst = create_flow_rule(dev, ft_prio,
3377 flow_attr, dst);
3378 if (IS_ERR(handler_dst)) {
74491de9 3379 mlx5_del_flow_rules(handler->rule);
d9d4980a 3380 ft_prio->refcount--;
35d19011
MG		 3381 kfree(handler);
3382 handler = handler_dst;
3383 } else {
3384 list_add(&handler_dst->list, &handler->list);
3385 }
3386 }
3387
3388 return handler;
3389}
038d2ef8
MG		 3390enum {
3391 LEFTOVERS_MC,
3392 LEFTOVERS_UC,
3393};
3394
3395static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3396 struct mlx5_ib_flow_prio *ft_prio,
3397 struct ib_flow_attr *flow_attr,
3398 struct mlx5_flow_destination *dst)
3399{
3400 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3401 struct mlx5_ib_flow_handler *handler = NULL;
3402
3403 static struct {
3404 struct ib_flow_attr flow_attr;
3405 struct ib_flow_spec_eth eth_flow;
3406 } leftovers_specs[] = {
3407 [LEFTOVERS_MC] = {
3408 .flow_attr = {
3409 .num_of_specs = 1,
3410 .size = sizeof(leftovers_specs[0])
3411 },
3412 .eth_flow = {
3413 .type = IB_FLOW_SPEC_ETH,
3414 .size = sizeof(struct ib_flow_spec_eth),
3415 .mask = {.dst_mac = {0x1} },
3416 .val = {.dst_mac = {0x1} }
3417 }
3418 },
3419 [LEFTOVERS_UC] = {
3420 .flow_attr = {
3421 .num_of_specs = 1,
3422 .size = sizeof(leftovers_specs[0])
3423 },
3424 .eth_flow = {
3425 .type = IB_FLOW_SPEC_ETH,
3426 .size = sizeof(struct ib_flow_spec_eth),
3427 .mask = {.dst_mac = {0x1} },
3428 .val = {.dst_mac = {} }
3429 }
3430 }
3431 };
3432
3433 handler = create_flow_rule(dev, ft_prio,
3434 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3435 dst);
3436 if (!IS_ERR(handler) &&
3437 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3438 handler_ucast = create_flow_rule(dev, ft_prio,
3439 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3440 dst);
3441 if (IS_ERR(handler_ucast)) {
74491de9 3442 mlx5_del_flow_rules(handler->rule);
d9d4980a 3443 ft_prio->refcount--;
038d2ef8
MG		 3444 kfree(handler);
3445 handler = handler_ucast;
3446 } else {
3447 list_add(&handler_ucast->list, &handler->list);
3448 }
3449 }
3450
3451 return handler;
3452}
3453
cc0e5d42
MG		 3454static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3455 struct mlx5_ib_flow_prio *ft_rx,
3456 struct mlx5_ib_flow_prio *ft_tx,
3457 struct mlx5_flow_destination *dst)
3458{
3459 struct mlx5_ib_flow_handler *handler_rx;
3460 struct mlx5_ib_flow_handler *handler_tx;
3461 int err;
3462 static const struct ib_flow_attr flow_attr = {
3463 .num_of_specs = 0,
3464 .size = sizeof(flow_attr)
3465 };
3466
3467 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3468 if (IS_ERR(handler_rx)) {
3469 err = PTR_ERR(handler_rx);
3470 goto err;
3471 }
3472
3473 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3474 if (IS_ERR(handler_tx)) {
3475 err = PTR_ERR(handler_tx);
3476 goto err_tx;
3477 }
3478
3479 list_add(&handler_tx->list, &handler_rx->list);
3480
3481 return handler_rx;
3482
3483err_tx:
74491de9 3484 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3485 ft_rx->refcount--;
3486 kfree(handler_rx);
3487err:
3488 return ERR_PTR(err);
3489}
3490
038d2ef8
MG		 3491static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3492 struct ib_flow_attr *flow_attr,
59082a32
MB		 3493 int domain,
3494 struct ib_udata *udata)
038d2ef8
MG		 3495{
3496 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3497 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3498 struct mlx5_ib_flow_handler *handler = NULL;
3499 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3500 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3501 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3502 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3503 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3504 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3505 int err;
a550ddfc 3506 int underlay_qpn;
038d2ef8 3507
3b3233fb
RS		 3508 if (udata && udata->inlen) {
3509 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3510 sizeof(ucmd_hdr.reserved);
3511 if (udata->inlen < min_ucmd_sz)
3512 return ERR_PTR(-EOPNOTSUPP);
3513
3514 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3515 if (err)
3516 return ERR_PTR(err);
3517
3518 /* currently supports only one counters data */
3519 if (ucmd_hdr.ncounters_data > 1)
3520 return ERR_PTR(-EINVAL);
3521
3522 required_ucmd_sz = min_ucmd_sz +
3523 sizeof(struct mlx5_ib_flow_counters_data) *
3524 ucmd_hdr.ncounters_data;
3525 if (udata->inlen > required_ucmd_sz &&
3526 !ib_is_udata_cleared(udata, required_ucmd_sz,
3527 udata->inlen - required_ucmd_sz))
3528 return ERR_PTR(-EOPNOTSUPP);
3529
3530 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3531 if (!ucmd)
3532 return ERR_PTR(-ENOMEM);
3533
3534 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3535 if (err) {
3536 kfree(ucmd);
3537 return ERR_PTR(err);
3538 }
3539 }
59082a32 3540
038d2ef8 3541 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 3542 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 3543
3544 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3545 flow_attr->port > dev->num_ports ||
802c2125
AY		 3546 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3547 IB_FLOW_ATTR_FLAGS_EGRESS)))
3548 return ERR_PTR(-EINVAL);
3549
3550 if (is_egress &&
3551 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3552 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
038d2ef8
MG		 3553 return ERR_PTR(-EINVAL);
3554
3555 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3556 if (!dst)
3557 return ERR_PTR(-ENOMEM);
3558
9a4ca38d 3559 mutex_lock(&dev->flow_db->lock);
038d2ef8 3560
802c2125
AY		 3561 ft_prio = get_flow_table(dev, flow_attr,
3562 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3563 if (IS_ERR(ft_prio)) {
3564 err = PTR_ERR(ft_prio);
3565 goto unlock;
3566 }
cc0e5d42
MG		 3567 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3568 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3569 if (IS_ERR(ft_prio_tx)) {
3570 err = PTR_ERR(ft_prio_tx);
3571 ft_prio_tx = NULL;
3572 goto destroy_ft;
3573 }
3574 }
038d2ef8 3575
802c2125
AY		 3576 if (is_egress) {
3577 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3578 } else {
3579 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3580 if (mqp->flags & MLX5_IB_QP_RSS)
3581 dst->tir_num = mqp->rss_qp.tirn;
3582 else
3583 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3584 }
038d2ef8
MG		 3585
3586 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3587 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3588 handler = create_dont_trap_rule(dev, ft_prio,
3589 flow_attr, dst);
3590 } else {
a550ddfc
YH		 3591 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3592 mqp->underlay_qpn : 0;
3593 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3594 dst, underlay_qpn, ucmd);
35d19011 3595 }
038d2ef8
MG		 3596 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3597 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3598 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3599 dst);
cc0e5d42
MG		 3600 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3601 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3602 } else {
3603 err = -EINVAL;
3604 goto destroy_ft;
3605 }
3606
3607 if (IS_ERR(handler)) {
3608 err = PTR_ERR(handler);
3609 handler = NULL;
3610 goto destroy_ft;
3611 }
3612
9a4ca38d 3613 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3614 kfree(dst);
3b3233fb 3615 kfree(ucmd);
038d2ef8
MG		 3616
3617 return &handler->ibflow;
3618
3619destroy_ft:
3620 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3621 if (ft_prio_tx)
3622 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3623unlock:
9a4ca38d 3624 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3625 kfree(dst);
3b3233fb 3626 kfree(ucmd);
038d2ef8
MG		 3627 kfree(handler);
3628 return ERR_PTR(err);
3629}
3630
c6475a0b
AY		 3631static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3632{
3633 u32 flags = 0;
3634
3635 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3636 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3637
3638 return flags;
3639}
3640
3641#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3642static struct ib_flow_action *
3643mlx5_ib_create_flow_action_esp(struct ib_device *device,
3644 const struct ib_flow_action_attrs_esp *attr,
3645 struct uverbs_attr_bundle *attrs)
3646{
3647 struct mlx5_ib_dev *mdev = to_mdev(device);
3648 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3649 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3650 struct mlx5_ib_flow_action *action;
3651 u64 action_flags;
3652 u64 flags;
3653 int err = 0;
3654
3655 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3656 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3657 return ERR_PTR(-EFAULT);
3658
3659 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3660 return ERR_PTR(-EOPNOTSUPP);
3661
3662 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3663
3664 /* We current only support a subset of the standard features. Only a
3665 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3666 * (with overlap). Full offload mode isn't supported.
3667 */
3668 if (!attr->keymat || attr->replay || attr->encap ||
3669 attr->spi || attr->seq || attr->tfc_pad ||
3670 attr->hard_limit_pkts ||
3671 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3672 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3673 return ERR_PTR(-EOPNOTSUPP);
3674
3675 if (attr->keymat->protocol !=
3676 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3677 return ERR_PTR(-EOPNOTSUPP);
3678
3679 aes_gcm = &attr->keymat->keymat.aes_gcm;
3680
3681 if (aes_gcm->icv_len != 16 ||
3682 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3683 return ERR_PTR(-EOPNOTSUPP);
3684
3685 action = kmalloc(sizeof(*action), GFP_KERNEL);
3686 if (!action)
3687 return ERR_PTR(-ENOMEM);
3688
3689 action->esp_aes_gcm.ib_flags = attr->flags;
3690 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3691 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3692 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3693 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3694 sizeof(accel_attrs.keymat.aes_gcm.salt));
3695 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3696 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3697 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3698 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3699 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3700
3701 accel_attrs.esn = attr->esn;
3702 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3703 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3704 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3705 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3706
3707 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3708 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3709
3710 action->esp_aes_gcm.ctx =
3711 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3712 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3713 err = PTR_ERR(action->esp_aes_gcm.ctx);
3714 goto err_parse;
3715 }
3716
3717 action->esp_aes_gcm.ib_flags = attr->flags;
3718
3719 return &action->ib_action;
3720
3721err_parse:
3722 kfree(action);
3723 return ERR_PTR(err);
3724}
3725
349705c1
MB		 3726static int
3727mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3728 const struct ib_flow_action_attrs_esp *attr,
3729 struct uverbs_attr_bundle *attrs)
3730{
3731 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3732 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3733 int err = 0;
3734
3735 if (attr->keymat || attr->replay || attr->encap ||
3736 attr->spi || attr->seq || attr->tfc_pad ||
3737 attr->hard_limit_pkts ||
3738 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3739 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3740 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3741 return -EOPNOTSUPP;
3742
3743 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3744 * be modified.
3745 */
3746 if (!(maction->esp_aes_gcm.ib_flags &
3747 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3748 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3749 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3750 return -EINVAL;
3751
3752 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3753 sizeof(accel_attrs));
3754
3755 accel_attrs.esn = attr->esn;
3756 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3757 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3758 else
3759 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3760
3761 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3762 &accel_attrs);
3763 if (err)
3764 return err;
3765
3766 maction->esp_aes_gcm.ib_flags &=
3767 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3768 maction->esp_aes_gcm.ib_flags |=
3769 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3770
3771 return 0;
3772}
3773
c6475a0b
AY		 3774static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3775{
3776 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3777
3778 switch (action->type) {
3779 case IB_FLOW_ACTION_ESP:
3780 /*
3781 * We only support aes_gcm by now, so we implicitly know this is
3782 * the underline crypto.
3783 */
3784 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3785 break;
3786 default:
3787 WARN_ON(true);
3788 break;
3789 }
3790
3791 kfree(maction);
3792 return 0;
3793}
3794
e126ba97
EC		 3795static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3796{
3797 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 3798 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 3799 int err;
3800
81e30880
YH		 3801 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3802 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3803 return -EOPNOTSUPP;
3804 }
3805
9603b61d 3806 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3807 if (err)
3808 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3809 ibqp->qp_num, gid->raw);
3810
3811 return err;
3812}
3813
3814static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3815{
3816 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3817 int err;
3818
9603b61d 3819 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3820 if (err)
3821 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3822 ibqp->qp_num, gid->raw);
3823
3824 return err;
3825}
3826
3827static int init_node_data(struct mlx5_ib_dev *dev)
3828{
1b5daf11 3829 int err;
e126ba97 3830
1b5daf11 3831 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 3832 if (err)
1b5daf11 3833 return err;
e126ba97 3834
1b5daf11 3835 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 3836
1b5daf11 3837 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 3838}
3839
3840static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3841 char *buf)
3842{
3843 struct mlx5_ib_dev *dev =
3844 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3845
9603b61d 3846 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 3847}
3848
3849static ssize_t show_reg_pages(struct device *device,
3850 struct device_attribute *attr, char *buf)
3851{
3852 struct mlx5_ib_dev *dev =
3853 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3854
6aec21f6 3855 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3856}
3857
3858static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3859 char *buf)
3860{
3861 struct mlx5_ib_dev *dev =
3862 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3863 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3864}
3865
e126ba97
EC		 3866static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3867 char *buf)
3868{
3869 struct mlx5_ib_dev *dev =
3870 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3871 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3872}
3873
3874static ssize_t show_board(struct device *device, struct device_attribute *attr,
3875 char *buf)
3876{
3877 struct mlx5_ib_dev *dev =
3878 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3879 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3880 dev->mdev->board_id);
e126ba97
EC		 3881}
3882
3883static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3884static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3885static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3886static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3887static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3888
3889static struct device_attribute *mlx5_class_attributes[] = {
3890 &dev_attr_hw_rev,
e126ba97
EC		 3891 &dev_attr_hca_type,
3892 &dev_attr_board_id,
3893 &dev_attr_fw_pages,
3894 &dev_attr_reg_pages,
3895};
3896
7722f47e
HE		 3897static void pkey_change_handler(struct work_struct *work)
3898{
3899 struct mlx5_ib_port_resources *ports =
3900 container_of(work, struct mlx5_ib_port_resources,
3901 pkey_change_work);
3902
3903 mutex_lock(&ports->devr->mutex);
3904 mlx5_ib_gsi_pkey_change(ports->gsi);
3905 mutex_unlock(&ports->devr->mutex);
3906}
3907
89ea94a7
MG		 3908static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3909{
3910 struct mlx5_ib_qp *mqp;
3911 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3912 struct mlx5_core_cq *mcq;
3913 struct list_head cq_armed_list;
3914 unsigned long flags_qp;
3915 unsigned long flags_cq;
3916 unsigned long flags;
3917
3918 INIT_LIST_HEAD(&cq_armed_list);
3919
3920 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3921 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3922 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3923 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3924 if (mqp->sq.tail != mqp->sq.head) {
3925 send_mcq = to_mcq(mqp->ibqp.send_cq);
3926 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3927 if (send_mcq->mcq.comp &&
3928 mqp->ibqp.send_cq->comp_handler) {
3929 if (!send_mcq->mcq.reset_notify_added) {
3930 send_mcq->mcq.reset_notify_added = 1;
3931 list_add_tail(&send_mcq->mcq.reset_notify,
3932 &cq_armed_list);
3933 }
3934 }
3935 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3936 }
3937 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3938 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3939 /* no handling is needed for SRQ */
3940 if (!mqp->ibqp.srq) {
3941 if (mqp->rq.tail != mqp->rq.head) {
3942 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3943 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3944 if (recv_mcq->mcq.comp &&
3945 mqp->ibqp.recv_cq->comp_handler) {
3946 if (!recv_mcq->mcq.reset_notify_added) {
3947 recv_mcq->mcq.reset_notify_added = 1;
3948 list_add_tail(&recv_mcq->mcq.reset_notify,
3949 &cq_armed_list);
3950 }
3951 }
3952 spin_unlock_irqrestore(&recv_mcq->lock,
3953 flags_cq);
3954 }
3955 }
3956 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3957 }
3958 /*At that point all inflight post send were put to be executed as of we
3959 * lock/unlock above locks Now need to arm all involved CQs.
3960 */
3961 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3962 mcq->comp(mcq);
3963 }
3964 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3965}
3966
03404e8a
MG		 3967static void delay_drop_handler(struct work_struct *work)
3968{
3969 int err;
3970 struct mlx5_ib_delay_drop *delay_drop =
3971 container_of(work, struct mlx5_ib_delay_drop,
3972 delay_drop_work);
3973
fe248c3a
MG		 3974 atomic_inc(&delay_drop->events_cnt);
3975
03404e8a
MG		 3976 mutex_lock(&delay_drop->lock);
3977 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3978 delay_drop->timeout);
3979 if (err) {
3980 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3981 delay_drop->timeout);
3982 delay_drop->activate = false;
3983 }
3984 mutex_unlock(&delay_drop->lock);
3985}
3986
d69a24e0 3987static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 3988{
d69a24e0
DJ		 3989 struct mlx5_ib_event_work *work =
3990 container_of(_work, struct mlx5_ib_event_work, work);
3991 struct mlx5_ib_dev *ibdev;
e126ba97 3992 struct ib_event ibev;
dbaaff2a 3993 bool fatal = false;
aba46213 3994 u8 port = (u8)work->param;
e126ba97 3995
d69a24e0
DJ		 3996 if (mlx5_core_is_mp_slave(work->dev)) {
3997 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3998 if (!ibdev)
3999 goto out;
4000 } else {
4001 ibdev = work->context;
4002 }
4003
4004 switch (work->event) {
e126ba97 4005 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4006 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4007 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 4008 fatal = true;
e126ba97
EC		 4009 break;
4010
4011 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 4012 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 4013 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 4014 /* In RoCE, port up/down events are handled in
4015 * mlx5_netdev_event().
4016 */
4017 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4018 IB_LINK_LAYER_ETHERNET)
d69a24e0 4019 goto out;
5ec8c83e 4020
d69a24e0 4021 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 4022 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 4023 break;
4024
e126ba97
EC		 4025 case MLX5_DEV_EVENT_LID_CHANGE:
4026 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 4027 break;
4028
4029 case MLX5_DEV_EVENT_PKEY_CHANGE:
4030 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 4031 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 4032 break;
4033
4034 case MLX5_DEV_EVENT_GUID_CHANGE:
4035 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 4036 break;
4037
4038 case MLX5_DEV_EVENT_CLIENT_REREG:
4039 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 4040 break;
03404e8a
MG		 4041 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4042 schedule_work(&ibdev->delay_drop.delay_drop_work);
4043 goto out;
bdc37924 4044 default:
03404e8a 4045 goto out;
e126ba97
EC		 4046 }
4047
4048 ibev.device = &ibdev->ib_dev;
4049 ibev.element.port_num = port;
4050
aba46213 4051 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 4052 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 4053 goto out;
a0c84c32
EC		 4054 }
4055
e126ba97
EC		 4056 if (ibdev->ib_active)
4057 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4058
4059 if (fatal)
4060 ibdev->ib_active = false;
03404e8a 4061out:
d69a24e0
DJ		 4062 kfree(work);
4063}
4064
4065static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4066 enum mlx5_dev_event event, unsigned long param)
4067{
4068 struct mlx5_ib_event_work *work;
4069
4070 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4071 if (!work)
d69a24e0 4072 return;
d69a24e0 4073
10bea9c8
LR		 4074 INIT_WORK(&work->work, mlx5_ib_handle_event);
4075 work->dev = dev;
4076 work->param = param;
4077 work->context = context;
4078 work->event = event;
4079
4080 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 4081}
4082
c43f1112
MG		 4083static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4084{
4085 struct mlx5_hca_vport_context vport_ctx;
4086 int err;
4087 int port;
4088
508562d6 4089 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 4090 dev->mdev->port_caps[port - 1].has_smi = false;
4091 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4092 MLX5_CAP_PORT_TYPE_IB) {
4093 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4094 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4095 port, 0,
4096 &vport_ctx);
4097 if (err) {
4098 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4099 port, err);
4100 return err;
4101 }
4102 dev->mdev->port_caps[port - 1].has_smi =
4103 vport_ctx.has_smi;
4104 } else {
4105 dev->mdev->port_caps[port - 1].has_smi = true;
4106 }
4107 }
4108 }
4109 return 0;
4110}
4111
e126ba97
EC		 4112static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4113{
4114 int port;
4115
508562d6 4116 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4117 mlx5_query_ext_port_caps(dev, port);
4118}
4119
32f69e4b 4120static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4121{
4122 struct ib_device_attr *dprops = NULL;
4123 struct ib_port_attr *pprops = NULL;
f614fc15 4124 int err = -ENOMEM;
2528e33e 4125 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4126
4127 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4128 if (!pprops)
4129 goto out;
4130
4131 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4132 if (!dprops)
4133 goto out;
4134
c43f1112
MG		 4135 err = set_has_smi_cap(dev);
4136 if (err)
4137 goto out;
4138
2528e33e 4139 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4140 if (err) {
4141 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4142 goto out;
4143 }
4144
32f69e4b
DJ		 4145 memset(pprops, 0, sizeof(*pprops));
4146 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4147 if (err) {
4148 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4149 port, err);
4150 goto out;
e126ba97
EC		 4151 }
4152
32f69e4b
DJ		 4153 dev->mdev->port_caps[port - 1].pkey_table_len =
4154 dprops->max_pkeys;
4155 dev->mdev->port_caps[port - 1].gid_table_len =
4156 pprops->gid_tbl_len;
4157 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4158 port, dprops->max_pkeys, pprops->gid_tbl_len);
4159
e126ba97
EC		 4160out:
4161 kfree(pprops);
4162 kfree(dprops);
4163
4164 return err;
4165}
4166
4167static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4168{
4169 int err;
4170
4171 err = mlx5_mr_cache_cleanup(dev);
4172 if (err)
4173 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4174
32927e28
MB		 4175 if (dev->umrc.qp)
4176 mlx5_ib_destroy_qp(dev->umrc.qp);
4177 if (dev->umrc.cq)
4178 ib_free_cq(dev->umrc.cq);
4179 if (dev->umrc.pd)
4180 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4181}
4182
4183enum {
4184 MAX_UMR_WR = 128,
4185};
4186
4187static int create_umr_res(struct mlx5_ib_dev *dev)
4188{
4189 struct ib_qp_init_attr *init_attr = NULL;
4190 struct ib_qp_attr *attr = NULL;
4191 struct ib_pd *pd;
4192 struct ib_cq *cq;
4193 struct ib_qp *qp;
e126ba97
EC		 4194 int ret;
4195
4196 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4197 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4198 if (!attr || !init_attr) {
4199 ret = -ENOMEM;
4200 goto error_0;
4201 }
4202
ed082d36 4203 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4204 if (IS_ERR(pd)) {
4205 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4206 ret = PTR_ERR(pd);
4207 goto error_0;
4208 }
4209
add08d76 4210 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4211 if (IS_ERR(cq)) {
4212 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4213 ret = PTR_ERR(cq);
4214 goto error_2;
4215 }
e126ba97
EC		 4216
4217 init_attr->send_cq = cq;
4218 init_attr->recv_cq = cq;
4219 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4220 init_attr->cap.max_send_wr = MAX_UMR_WR;
4221 init_attr->cap.max_send_sge = 1;
4222 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4223 init_attr->port_num = 1;
4224 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4225 if (IS_ERR(qp)) {
4226 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4227 ret = PTR_ERR(qp);
4228 goto error_3;
4229 }
4230 qp->device = &dev->ib_dev;
4231 qp->real_qp = qp;
4232 qp->uobject = NULL;
4233 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4234 qp->send_cq = init_attr->send_cq;
4235 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4236
4237 attr->qp_state = IB_QPS_INIT;
4238 attr->port_num = 1;
4239 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4240 IB_QP_PORT, NULL);
4241 if (ret) {
4242 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4243 goto error_4;
4244 }
4245
4246 memset(attr, 0, sizeof(*attr));
4247 attr->qp_state = IB_QPS_RTR;
4248 attr->path_mtu = IB_MTU_256;
4249
4250 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4251 if (ret) {
4252 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4253 goto error_4;
4254 }
4255
4256 memset(attr, 0, sizeof(*attr));
4257 attr->qp_state = IB_QPS_RTS;
4258 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4259 if (ret) {
4260 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4261 goto error_4;
4262 }
4263
4264 dev->umrc.qp = qp;
4265 dev->umrc.cq = cq;
e126ba97
EC		 4266 dev->umrc.pd = pd;
4267
4268 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4269 ret = mlx5_mr_cache_init(dev);
4270 if (ret) {
4271 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4272 goto error_4;
4273 }
4274
4275 kfree(attr);
4276 kfree(init_attr);
4277
4278 return 0;
4279
4280error_4:
4281 mlx5_ib_destroy_qp(qp);
32927e28 4282 dev->umrc.qp = NULL;
e126ba97
EC		 4283
4284error_3:
add08d76 4285 ib_free_cq(cq);
32927e28 4286 dev->umrc.cq = NULL;
e126ba97
EC		 4287
4288error_2:
e126ba97 4289 ib_dealloc_pd(pd);
32927e28 4290 dev->umrc.pd = NULL;
e126ba97
EC		 4291
4292error_0:
4293 kfree(attr);
4294 kfree(init_attr);
4295 return ret;
4296}
4297
6e8484c5
MG		 4298static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4299{
4300 switch (umr_fence_cap) {
4301 case MLX5_CAP_UMR_FENCE_NONE:
4302 return MLX5_FENCE_MODE_NONE;
4303 case MLX5_CAP_UMR_FENCE_SMALL:
4304 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4305 default:
4306 return MLX5_FENCE_MODE_STRONG_ORDERING;
4307 }
4308}
4309
e126ba97
EC		 4310static int create_dev_resources(struct mlx5_ib_resources *devr)
4311{
4312 struct ib_srq_init_attr attr;
4313 struct mlx5_ib_dev *dev;
bcf4c1ea 4314 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4315 int port;
e126ba97
EC		 4316 int ret = 0;
4317
4318 dev = container_of(devr, struct mlx5_ib_dev, devr);
4319
d16e91da
HE		 4320 mutex_init(&devr->mutex);
4321
e126ba97
EC		 4322 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4323 if (IS_ERR(devr->p0)) {
4324 ret = PTR_ERR(devr->p0);
4325 goto error0;
4326 }
4327 devr->p0->device = &dev->ib_dev;
4328 devr->p0->uobject = NULL;
4329 atomic_set(&devr->p0->usecnt, 0);
4330
bcf4c1ea 4331 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4332 if (IS_ERR(devr->c0)) {
4333 ret = PTR_ERR(devr->c0);
4334 goto error1;
4335 }
4336 devr->c0->device = &dev->ib_dev;
4337 devr->c0->uobject = NULL;
4338 devr->c0->comp_handler = NULL;
4339 devr->c0->event_handler = NULL;
4340 devr->c0->cq_context = NULL;
4341 atomic_set(&devr->c0->usecnt, 0);
4342
4343 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4344 if (IS_ERR(devr->x0)) {
4345 ret = PTR_ERR(devr->x0);
4346 goto error2;
4347 }
4348 devr->x0->device = &dev->ib_dev;
4349 devr->x0->inode = NULL;
4350 atomic_set(&devr->x0->usecnt, 0);
4351 mutex_init(&devr->x0->tgt_qp_mutex);
4352 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4353
4354 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4355 if (IS_ERR(devr->x1)) {
4356 ret = PTR_ERR(devr->x1);
4357 goto error3;
4358 }
4359 devr->x1->device = &dev->ib_dev;
4360 devr->x1->inode = NULL;
4361 atomic_set(&devr->x1->usecnt, 0);
4362 mutex_init(&devr->x1->tgt_qp_mutex);
4363 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4364
4365 memset(&attr, 0, sizeof(attr));
4366 attr.attr.max_sge = 1;
4367 attr.attr.max_wr = 1;
4368 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4369 attr.ext.cq = devr->c0;
e126ba97
EC		 4370 attr.ext.xrc.xrcd = devr->x0;
4371
4372 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4373 if (IS_ERR(devr->s0)) {
4374 ret = PTR_ERR(devr->s0);
4375 goto error4;
4376 }
4377 devr->s0->device = &dev->ib_dev;
4378 devr->s0->pd = devr->p0;
4379 devr->s0->uobject = NULL;
4380 devr->s0->event_handler = NULL;
4381 devr->s0->srq_context = NULL;
4382 devr->s0->srq_type = IB_SRQT_XRC;
4383 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4384 devr->s0->ext.cq = devr->c0;
e126ba97 4385 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4386 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4387 atomic_inc(&devr->p0->usecnt);
4388 atomic_set(&devr->s0->usecnt, 0);
4389
4aa17b28
HA		 4390 memset(&attr, 0, sizeof(attr));
4391 attr.attr.max_sge = 1;
4392 attr.attr.max_wr = 1;
4393 attr.srq_type = IB_SRQT_BASIC;
4394 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4395 if (IS_ERR(devr->s1)) {
4396 ret = PTR_ERR(devr->s1);
4397 goto error5;
4398 }
4399 devr->s1->device = &dev->ib_dev;
4400 devr->s1->pd = devr->p0;
4401 devr->s1->uobject = NULL;
4402 devr->s1->event_handler = NULL;
4403 devr->s1->srq_context = NULL;
4404 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4405 devr->s1->ext.cq = devr->c0;
4aa17b28 4406 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4407 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4408
7722f47e
HE		 4409 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4410 INIT_WORK(&devr->ports[port].pkey_change_work,
4411 pkey_change_handler);
4412 devr->ports[port].devr = devr;
4413 }
4414
e126ba97
EC		 4415 return 0;
4416
4aa17b28
HA		 4417error5:
4418 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4419error4:
4420 mlx5_ib_dealloc_xrcd(devr->x1);
4421error3:
4422 mlx5_ib_dealloc_xrcd(devr->x0);
4423error2:
4424 mlx5_ib_destroy_cq(devr->c0);
4425error1:
4426 mlx5_ib_dealloc_pd(devr->p0);
4427error0:
4428 return ret;
4429}
4430
4431static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4432{
7722f47e
HE		 4433 struct mlx5_ib_dev *dev =
4434 container_of(devr, struct mlx5_ib_dev, devr);
4435 int port;
4436
4aa17b28 4437 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4438 mlx5_ib_destroy_srq(devr->s0);
4439 mlx5_ib_dealloc_xrcd(devr->x0);
4440 mlx5_ib_dealloc_xrcd(devr->x1);
4441 mlx5_ib_destroy_cq(devr->c0);
4442 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4443
4444 /* Make sure no change P_Key work items are still executing */
4445 for (port = 0; port < dev->num_ports; ++port)
4446 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4447}
4448
e53505a8
AS		 4449static u32 get_core_cap_flags(struct ib_device *ibdev)
4450{
4451 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4452 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4453 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4454 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4455 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4456 u32 ret = 0;
4457
4458 if (ll == IB_LINK_LAYER_INFINIBAND)
4459 return RDMA_CORE_PORT_IBA_IB;
4460
85c7c014
DJ		 4461 if (raw_support)
4462 ret = RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4463
e53505a8 4464 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4465 return ret;
e53505a8
AS		 4466
4467 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4468 return ret;
e53505a8
AS		 4469
4470 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4471 ret |= RDMA_CORE_PORT_IBA_ROCE;
4472
4473 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4474 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4475
4476 return ret;
4477}
4478
7738613e
IW		 4479static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4480 struct ib_port_immutable *immutable)
4481{
4482 struct ib_port_attr attr;
ca5b91d6
OG		 4483 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4484 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 4485 int err;
4486
c4550c63
OG		 4487 immutable->core_cap_flags = get_core_cap_flags(ibdev);
4488
4489 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4490 if (err)
4491 return err;
4492
4493 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4494 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 4495 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 4496 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4497 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4498
4499 return 0;
4500}
4501
8e6efa3a
MB		 4502static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4503 struct ib_port_immutable *immutable)
4504{
4505 struct ib_port_attr attr;
4506 int err;
4507
4508 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4509
4510 err = ib_query_port(ibdev, port_num, &attr);
4511 if (err)
4512 return err;
4513
4514 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4515 immutable->gid_tbl_len = attr.gid_tbl_len;
4516 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4517
4518 return 0;
4519}
4520
9abb0d1b 4521static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4522{
4523 struct mlx5_ib_dev *dev =
4524 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4525 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4526 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4527 fw_rev_sub(dev->mdev));
c7342823
IW		 4528}
4529
45f95acd 4530static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4531{
4532 struct mlx5_core_dev *mdev = dev->mdev;
4533 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4534 MLX5_FLOW_NAMESPACE_LAG);
4535 struct mlx5_flow_table *ft;
4536 int err;
4537
4538 if (!ns || !mlx5_lag_is_active(mdev))
4539 return 0;
4540
4541 err = mlx5_cmd_create_vport_lag(mdev);
4542 if (err)
4543 return err;
4544
4545 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4546 if (IS_ERR(ft)) {
4547 err = PTR_ERR(ft);
4548 goto err_destroy_vport_lag;
4549 }
4550
9a4ca38d 4551 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4552 return 0;
4553
4554err_destroy_vport_lag:
4555 mlx5_cmd_destroy_vport_lag(mdev);
4556 return err;
4557}
4558
45f95acd 4559static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4560{
4561 struct mlx5_core_dev *mdev = dev->mdev;
4562
9a4ca38d
MB		 4563 if (dev->flow_db->lag_demux_ft) {
4564 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4565 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4566
4567 mlx5_cmd_destroy_vport_lag(mdev);
4568 }
4569}
4570
7fd8aefb 4571static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4572{
4573 int err;
4574
7fd8aefb
DJ		 4575 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4576 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4577 if (err) {
7fd8aefb 4578 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4579 return err;
4580 }
4581
4582 return 0;
4583}
4584
7fd8aefb 4585static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4586{
7fd8aefb
DJ		 4587 if (dev->roce[port_num].nb.notifier_call) {
4588 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4589 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4590 }
4591}
4592
7fd8aefb 4593static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
fc24fc5e 4594{
e53505a8
AS		 4595 int err;
4596
ca5b91d6
OG		 4597 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4598 err = mlx5_nic_vport_enable_roce(dev->mdev);
4599 if (err)
8e6efa3a 4600 return err;
ca5b91d6 4601 }
e53505a8 4602
45f95acd 4603 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4604 if (err)
4605 goto err_disable_roce;
4606
e53505a8
AS		 4607 return 0;
4608
9ef9c640 4609err_disable_roce:
ca5b91d6
OG		 4610 if (MLX5_CAP_GEN(dev->mdev, roce))
4611 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4612
e53505a8 4613 return err;
fc24fc5e
AS		 4614}
4615
45f95acd 4616static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4617{
45f95acd 4618 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4619 if (MLX5_CAP_GEN(dev->mdev, roce))
4620 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4621}
4622
e1f24a79 4623struct mlx5_ib_counter {
7c16f477
KH		 4624 const char *name;
4625 size_t offset;
4626};
4627
4628#define INIT_Q_COUNTER(_name) \
4629 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4630
e1f24a79 4631static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4632 INIT_Q_COUNTER(rx_write_requests),
4633 INIT_Q_COUNTER(rx_read_requests),
4634 INIT_Q_COUNTER(rx_atomic_requests),
4635 INIT_Q_COUNTER(out_of_buffer),
4636};
4637
e1f24a79 4638static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4639 INIT_Q_COUNTER(out_of_sequence),
4640};
4641
e1f24a79 4642static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4643 INIT_Q_COUNTER(duplicate_request),
4644 INIT_Q_COUNTER(rnr_nak_retry_err),
4645 INIT_Q_COUNTER(packet_seq_err),
4646 INIT_Q_COUNTER(implied_nak_seq_err),
4647 INIT_Q_COUNTER(local_ack_timeout_err),
4648};
4649
e1f24a79
PP		 4650#define INIT_CONG_COUNTER(_name) \
4651 { .name = #_name, .offset = \
4652 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4653
4654static const struct mlx5_ib_counter cong_cnts[] = {
4655 INIT_CONG_COUNTER(rp_cnp_ignored),
4656 INIT_CONG_COUNTER(rp_cnp_handled),
4657 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4658 INIT_CONG_COUNTER(np_cnp_sent),
4659};
4660
58dcb60a
PP		 4661static const struct mlx5_ib_counter extended_err_cnts[] = {
4662 INIT_Q_COUNTER(resp_local_length_error),
4663 INIT_Q_COUNTER(resp_cqe_error),
4664 INIT_Q_COUNTER(req_cqe_error),
4665 INIT_Q_COUNTER(req_remote_invalid_request),
4666 INIT_Q_COUNTER(req_remote_access_errors),
4667 INIT_Q_COUNTER(resp_remote_access_errors),
4668 INIT_Q_COUNTER(resp_cqe_flush_error),
4669 INIT_Q_COUNTER(req_cqe_flush_error),
4670};
4671
9f876f3d
TB		 4672#define INIT_EXT_PPCNT_COUNTER(_name) \
4673 { .name = #_name, .offset = \
4674 MLX5_BYTE_OFF(ppcnt_reg, \
4675 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4676
4677static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4678 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4679};
4680
e1f24a79 4681static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4682{
aac4492e 4683 int i;
0837e86a 4684
7c16f477 4685 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4686 if (dev->port[i].cnts.set_id)
4687 mlx5_core_dealloc_q_counter(dev->mdev,
4688 dev->port[i].cnts.set_id);
e1f24a79
PP		 4689 kfree(dev->port[i].cnts.names);
4690 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4691 }
4692}
4693
e1f24a79
PP		 4694static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4695 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4696{
4697 u32 num_counters;
4698
4699 num_counters = ARRAY_SIZE(basic_q_cnts);
4700
4701 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4702 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4703
4704 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4705 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4706
4707 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4708 num_counters += ARRAY_SIZE(extended_err_cnts);
4709
e1f24a79 4710 cnts->num_q_counters = num_counters;
7c16f477 4711
e1f24a79
PP		 4712 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4713 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4714 num_counters += ARRAY_SIZE(cong_cnts);
4715 }
9f876f3d
TB		 4716 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4717 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4718 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4719 }
e1f24a79
PP		 4720 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4721 if (!cnts->names)
7c16f477
KH		 4722 return -ENOMEM;
4723
e1f24a79
PP		 4724 cnts->offsets = kcalloc(num_counters,
4725 sizeof(cnts->offsets), GFP_KERNEL);
4726 if (!cnts->offsets)
7c16f477
KH		 4727 goto err_names;
4728
7c16f477
KH		 4729 return 0;
4730
4731err_names:
e1f24a79 4732 kfree(cnts->names);
aac4492e 4733 cnts->names = NULL;
7c16f477
KH		 4734 return -ENOMEM;
4735}
4736
e1f24a79
PP		 4737static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4738 const char **names,
4739 size_t *offsets)
7c16f477
KH		 4740{
4741 int i;
4742 int j = 0;
4743
4744 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4745 names[j] = basic_q_cnts[i].name;
4746 offsets[j] = basic_q_cnts[i].offset;
4747 }
4748
4749 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4750 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4751 names[j] = out_of_seq_q_cnts[i].name;
4752 offsets[j] = out_of_seq_q_cnts[i].offset;
4753 }
4754 }
4755
4756 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4757 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4758 names[j] = retrans_q_cnts[i].name;
4759 offsets[j] = retrans_q_cnts[i].offset;
4760 }
4761 }
e1f24a79 4762
58dcb60a
PP		 4763 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4764 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4765 names[j] = extended_err_cnts[i].name;
4766 offsets[j] = extended_err_cnts[i].offset;
4767 }
4768 }
4769
e1f24a79
PP		 4770 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4771 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4772 names[j] = cong_cnts[i].name;
4773 offsets[j] = cong_cnts[i].offset;
4774 }
4775 }
9f876f3d
TB		 4776
4777 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4778 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
4779 names[j] = ext_ppcnt_cnts[i].name;
4780 offsets[j] = ext_ppcnt_cnts[i].offset;
4781 }
4782 }
0837e86a
MB		 4783}
4784
e1f24a79 4785static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4786{
aac4492e 4787 int err = 0;
0837e86a 4788 int i;
0837e86a
MB		 4789
4790 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4791 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4792 if (err)
4793 goto err_alloc;
4794
4795 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4796 dev->port[i].cnts.offsets);
7c16f477 4797
aac4492e
DJ		 4798 err = mlx5_core_alloc_q_counter(dev->mdev,
4799 &dev->port[i].cnts.set_id);
4800 if (err) {
0837e86a
MB		 4801 mlx5_ib_warn(dev,
4802 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 4803 i + 1, err);
4804 goto err_alloc;
0837e86a 4805 }
aac4492e 4806 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 4807 }
4808
4809 return 0;
4810
aac4492e
DJ		 4811err_alloc:
4812 mlx5_ib_dealloc_counters(dev);
4813 return err;
0837e86a
MB		 4814}
4815
0ad17a8f
MB		 4816static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4817 u8 port_num)
4818{
7c16f477
KH		 4819 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4820 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 4821
4822 /* We support only per port stats */
4823 if (port_num == 0)
4824 return NULL;
4825
e1f24a79
PP		 4826 return rdma_alloc_hw_stats_struct(port->cnts.names,
4827 port->cnts.num_q_counters +
9f876f3d
TB		 4828 port->cnts.num_cong_counters +
4829 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 4830 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4831}
4832
aac4492e 4833static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 4834 struct mlx5_ib_port *port,
4835 struct rdma_hw_stats *stats)
0ad17a8f 4836{
0ad17a8f
MB		 4837 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4838 void *out;
4839 __be32 val;
e1f24a79 4840 int ret, i;
0ad17a8f 4841
1b9a07ee 4842 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 4843 if (!out)
4844 return -ENOMEM;
4845
aac4492e 4846 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 4847 port->cnts.set_id, 0,
0ad17a8f
MB		 4848 out, outlen);
4849 if (ret)
4850 goto free;
4851
e1f24a79
PP		 4852 for (i = 0; i < port->cnts.num_q_counters; i++) {
4853 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 4854 stats->value[i] = (u64)be32_to_cpu(val);
4855 }
7c16f477 4856
0ad17a8f
MB		 4857free:
4858 kvfree(out);
e1f24a79
PP		 4859 return ret;
4860}
4861
9f876f3d
TB		 4862static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
4863 struct mlx5_ib_port *port,
4864 struct rdma_hw_stats *stats)
4865{
4866 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4867 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
4868 int ret, i;
4869 void *out;
4870
4871 out = kvzalloc(sz, GFP_KERNEL);
4872 if (!out)
4873 return -ENOMEM;
4874
4875 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
4876 if (ret)
4877 goto free;
4878
4879 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
4880 stats->value[i + offset] =
4881 be64_to_cpup((__be64 *)(out +
4882 port->cnts.offsets[i + offset]));
4883 }
4884
4885free:
4886 kvfree(out);
4887 return ret;
4888}
4889
e1f24a79
PP		 4890static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4891 struct rdma_hw_stats *stats,
4892 u8 port_num, int index)
4893{
4894 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4895 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 4896 struct mlx5_core_dev *mdev;
e1f24a79 4897 int ret, num_counters;
aac4492e 4898 u8 mdev_port_num;
e1f24a79
PP		 4899
4900 if (!stats)
4901 return -EINVAL;
4902
9f876f3d
TB		 4903 num_counters = port->cnts.num_q_counters +
4904 port->cnts.num_cong_counters +
4905 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 4906
4907 /* q_counters are per IB device, query the master mdev */
4908 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 4909 if (ret)
4910 return ret;
e1f24a79 4911
9f876f3d
TB		 4912 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4913 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
4914 if (ret)
4915 return ret;
4916 }
4917
e1f24a79 4918 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 4919 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4920 &mdev_port_num);
4921 if (!mdev) {
4922 /* If port is not affiliated yet, its in down state
4923 * which doesn't have any counters yet, so it would be
4924 * zero. So no need to read from the HCA.
4925 */
4926 goto done;
4927 }
71a0ff65
MD		 4928 ret = mlx5_lag_query_cong_counters(dev->mdev,
4929 stats->value +
4930 port->cnts.num_q_counters,
4931 port->cnts.num_cong_counters,
4932 port->cnts.offsets +
4933 port->cnts.num_q_counters);
aac4492e
DJ		 4934
4935 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 4936 if (ret)
4937 return ret;
e1f24a79
PP		 4938 }
4939
aac4492e 4940done:
e1f24a79 4941 return num_counters;
0ad17a8f
MB		 4942}
4943
8e959601
NV		 4944static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4945{
4946 return mlx5_rdma_netdev_free(netdev);
4947}
4948
693dfd5a
ES		 4949static struct net_device*
4950mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4951 u8 port_num,
4952 enum rdma_netdev_t type,
4953 const char *name,
4954 unsigned char name_assign_type,
4955 void (*setup)(struct net_device *))
4956{
8e959601
NV		 4957 struct net_device *netdev;
4958 struct rdma_netdev *rn;
4959
693dfd5a
ES		 4960 if (type != RDMA_NETDEV_IPOIB)
4961 return ERR_PTR(-EOPNOTSUPP);
4962
8e959601
NV		 4963 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4964 name, setup);
4965 if (likely(!IS_ERR_OR_NULL(netdev))) {
4966 rn = netdev_priv(netdev);
4967 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4968 }
4969 return netdev;
693dfd5a
ES		 4970}
4971
fe248c3a
MG		 4972static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4973{
4974 if (!dev->delay_drop.dbg)
4975 return;
4976 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4977 kfree(dev->delay_drop.dbg);
4978 dev->delay_drop.dbg = NULL;
4979}
4980
03404e8a
MG		 4981static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4982{
4983 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4984 return;
4985
4986 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 4987 delay_drop_debugfs_cleanup(dev);
4988}
4989
4990static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4991 size_t count, loff_t *pos)
4992{
4993 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4994 char lbuf[20];
4995 int len;
4996
4997 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4998 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4999}
5000
5001static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5002 size_t count, loff_t *pos)
5003{
5004 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5005 u32 timeout;
5006 u32 var;
5007
5008 if (kstrtouint_from_user(buf, count, 0, &var))
5009 return -EFAULT;
5010
5011 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5012 1000);
5013 if (timeout != var)
5014 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5015 timeout);
5016
5017 delay_drop->timeout = timeout;
5018
5019 return count;
5020}
5021
5022static const struct file_operations fops_delay_drop_timeout = {
5023 .owner = THIS_MODULE,
5024 .open = simple_open,
5025 .write = delay_drop_timeout_write,
5026 .read = delay_drop_timeout_read,
5027};
5028
5029static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5030{
5031 struct mlx5_ib_dbg_delay_drop *dbg;
5032
5033 if (!mlx5_debugfs_root)
5034 return 0;
5035
5036 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5037 if (!dbg)
5038 return -ENOMEM;
5039
cbafad87
SM		 5040 dev->delay_drop.dbg = dbg;
5041
fe248c3a
MG		 5042 dbg->dir_debugfs =
5043 debugfs_create_dir("delay_drop",
5044 dev->mdev->priv.dbg_root);
5045 if (!dbg->dir_debugfs)
cbafad87 5046 goto out_debugfs;
fe248c3a
MG		 5047
5048 dbg->events_cnt_debugfs =
5049 debugfs_create_atomic_t("num_timeout_events", 0400,
5050 dbg->dir_debugfs,
5051 &dev->delay_drop.events_cnt);
5052 if (!dbg->events_cnt_debugfs)
5053 goto out_debugfs;
5054
5055 dbg->rqs_cnt_debugfs =
5056 debugfs_create_atomic_t("num_rqs", 0400,
5057 dbg->dir_debugfs,
5058 &dev->delay_drop.rqs_cnt);
5059 if (!dbg->rqs_cnt_debugfs)
5060 goto out_debugfs;
5061
5062 dbg->timeout_debugfs =
5063 debugfs_create_file("timeout", 0600,
5064 dbg->dir_debugfs,
5065 &dev->delay_drop,
5066 &fops_delay_drop_timeout);
5067 if (!dbg->timeout_debugfs)
5068 goto out_debugfs;
5069
5070 return 0;
5071
5072out_debugfs:
5073 delay_drop_debugfs_cleanup(dev);
5074 return -ENOMEM;
03404e8a
MG		 5075}
5076
5077static void init_delay_drop(struct mlx5_ib_dev *dev)
5078{
5079 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5080 return;
5081
5082 mutex_init(&dev->delay_drop.lock);
5083 dev->delay_drop.dev = dev;
5084 dev->delay_drop.activate = false;
5085 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5086 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5087 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5088 atomic_set(&dev->delay_drop.events_cnt, 0);
5089
5090 if (delay_drop_debugfs_init(dev))
5091 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5092}
5093
84305d71
LR		 5094static const struct cpumask *
5095mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 5096{
5097 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5098
6082d9c9 5099 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
40b24403
SG		 5100}
5101
32f69e4b
DJ		 5102/* The mlx5_ib_multiport_mutex should be held when calling this function */
5103static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5104 struct mlx5_ib_multiport_info *mpi)
5105{
5106 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5107 struct mlx5_ib_port *port = &ibdev->port[port_num];
5108 int comps;
5109 int err;
5110 int i;
5111
a9e546e7
PP		 5112 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5113
32f69e4b
DJ		 5114 spin_lock(&port->mp.mpi_lock);
5115 if (!mpi->ibdev) {
5116 spin_unlock(&port->mp.mpi_lock);
5117 return;
5118 }
5119 mpi->ibdev = NULL;
5120
5121 spin_unlock(&port->mp.mpi_lock);
5122 mlx5_remove_netdev_notifier(ibdev, port_num);
5123 spin_lock(&port->mp.mpi_lock);
5124
5125 comps = mpi->mdev_refcnt;
5126 if (comps) {
5127 mpi->unaffiliate = true;
5128 init_completion(&mpi->unref_comp);
5129 spin_unlock(&port->mp.mpi_lock);
5130
5131 for (i = 0; i < comps; i++)
5132 wait_for_completion(&mpi->unref_comp);
5133
5134 spin_lock(&port->mp.mpi_lock);
5135 mpi->unaffiliate = false;
5136 }
5137
5138 port->mp.mpi = NULL;
5139
5140 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5141
5142 spin_unlock(&port->mp.mpi_lock);
5143
5144 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5145
5146 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5147 /* Log an error, still needed to cleanup the pointers and add
5148 * it back to the list.
5149 */
5150 if (err)
5151 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5152 port_num + 1);
5153
5154 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5155}
5156
5157/* The mlx5_ib_multiport_mutex should be held when calling this function */
5158static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5159 struct mlx5_ib_multiport_info *mpi)
5160{
5161 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5162 int err;
5163
5164 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5165 if (ibdev->port[port_num].mp.mpi) {
5166 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
5167 port_num + 1);
5168 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5169 return false;
5170 }
5171
5172 ibdev->port[port_num].mp.mpi = mpi;
5173 mpi->ibdev = ibdev;
5174 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5175
5176 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5177 if (err)
5178 goto unbind;
5179
5180 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5181 if (err)
5182 goto unbind;
5183
5184 err = mlx5_add_netdev_notifier(ibdev, port_num);
5185 if (err) {
5186 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5187 port_num + 1);
5188 goto unbind;
5189 }
5190
a9e546e7
PP		 5191 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5192 if (err)
5193 goto unbind;
5194
32f69e4b
DJ		 5195 return true;
5196
5197unbind:
5198 mlx5_ib_unbind_slave_port(ibdev, mpi);
5199 return false;
5200}
5201
5202static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5203{
5204 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5205 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5206 port_num + 1);
5207 struct mlx5_ib_multiport_info *mpi;
5208 int err;
5209 int i;
5210
5211 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5212 return 0;
5213
5214 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5215 &dev->sys_image_guid);
5216 if (err)
5217 return err;
5218
5219 err = mlx5_nic_vport_enable_roce(dev->mdev);
5220 if (err)
5221 return err;
5222
5223 mutex_lock(&mlx5_ib_multiport_mutex);
5224 for (i = 0; i < dev->num_ports; i++) {
5225 bool bound = false;
5226
5227 /* build a stub multiport info struct for the native port. */
5228 if (i == port_num) {
5229 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5230 if (!mpi) {
5231 mutex_unlock(&mlx5_ib_multiport_mutex);
5232 mlx5_nic_vport_disable_roce(dev->mdev);
5233 return -ENOMEM;
5234 }
5235
5236 mpi->is_master = true;
5237 mpi->mdev = dev->mdev;
5238 mpi->sys_image_guid = dev->sys_image_guid;
5239 dev->port[i].mp.mpi = mpi;
5240 mpi->ibdev = dev;
5241 mpi = NULL;
5242 continue;
5243 }
5244
5245 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5246 list) {
5247 if (dev->sys_image_guid == mpi->sys_image_guid &&
5248 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5249 bound = mlx5_ib_bind_slave_port(dev, mpi);
5250 }
5251
5252 if (bound) {
5253 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5254 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5255 list_del(&mpi->list);
5256 break;
5257 }
5258 }
5259 if (!bound) {
5260 get_port_caps(dev, i + 1);
5261 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5262 i + 1);
5263 }
5264 }
5265
5266 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5267 mutex_unlock(&mlx5_ib_multiport_mutex);
5268 return err;
5269}
5270
5271static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5272{
5273 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5274 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5275 port_num + 1);
5276 int i;
5277
5278 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5279 return;
5280
5281 mutex_lock(&mlx5_ib_multiport_mutex);
5282 for (i = 0; i < dev->num_ports; i++) {
5283 if (dev->port[i].mp.mpi) {
5284 /* Destroy the native port stub */
5285 if (i == port_num) {
5286 kfree(dev->port[i].mp.mpi);
5287 dev->port[i].mp.mpi = NULL;
5288 } else {
5289 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5290 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5291 }
5292 }
5293 }
5294
5295 mlx5_ib_dbg(dev, "removing from devlist\n");
5296 list_del(&dev->ib_dev_list);
5297 mutex_unlock(&mlx5_ib_multiport_mutex);
5298
5299 mlx5_nic_vport_disable_roce(dev->mdev);
5300}
5301
24da0016
AL		 5302ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
5303 UVERBS_METHOD_DM_ALLOC,
5304 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5305 UVERBS_ATTR_TYPE(u64),
5306 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
5307 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5308 UVERBS_ATTR_TYPE(u16),
5309 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
5310
c6475a0b
AY		 5311ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
5312 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5313 &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5314 UVERBS_ATTR_TYPE(u64),
5315 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
5316
c59450c4 5317#define NUM_TREES 3
8c84660b
MB		 5318static int populate_specs_root(struct mlx5_ib_dev *dev)
5319{
5320 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
5321 uverbs_default_get_objects()};
5322 size_t num_trees = 1;
5323
c6475a0b
AY		 5324 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
5325 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5326 default_root[num_trees++] = &mlx5_ib_flow_action;
5327
24da0016
AL		 5328 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
5329 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5330 default_root[num_trees++] = &mlx5_ib_dm;
5331
c59450c4
YH		 5332 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5333 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX &&
5334 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5335 default_root[num_trees++] = mlx5_ib_get_devx_tree();
5336
8c84660b
MB		 5337 dev->ib_dev.specs_root =
5338 uverbs_alloc_spec_tree(num_trees, default_root);
5339
5340 return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
5341}
5342
5343static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5344{
5345 uverbs_free_spec_tree(dev->ib_dev.specs_root);
5346}
5347
1a1e03dc
RS		 5348static int mlx5_ib_read_counters(struct ib_counters *counters,
5349 struct ib_counters_read_attr *read_attr,
5350 struct uverbs_attr_bundle *attrs)
5351{
5352 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5353 struct mlx5_read_counters_attr mread_attr = {};
5354 struct mlx5_ib_flow_counters_desc *desc;
5355 int ret, i;
5356
5357 mutex_lock(&mcounters->mcntrs_mutex);
5358 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5359 ret = -EINVAL;
5360 goto err_bound;
5361 }
5362
5363 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5364 GFP_KERNEL);
5365 if (!mread_attr.out) {
5366 ret = -ENOMEM;
5367 goto err_bound;
5368 }
5369
5370 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5371 mread_attr.flags = read_attr->flags;
5372 ret = mcounters->read_counters(counters->device, &mread_attr);
5373 if (ret)
5374 goto err_read;
5375
5376 /* do the pass over the counters data array to assign according to the
5377 * descriptions and indexing pairs
5378 */
5379 desc = mcounters->counters_data;
5380 for (i = 0; i < mcounters->ncounters; i++)
5381 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5382
5383err_read:
5384 kfree(mread_attr.out);
5385err_bound:
5386 mutex_unlock(&mcounters->mcntrs_mutex);
5387 return ret;
5388}
5389
b29e2a13
RS		 5390static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5391{
5392 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5393
3b3233fb
RS		 5394 counters_clear_description(counters);
5395 if (mcounters->hw_cntrs_hndl)
5396 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5397 mcounters->hw_cntrs_hndl);
5398
b29e2a13
RS		 5399 kfree(mcounters);
5400
5401 return 0;
5402}
5403
5404static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5405 struct uverbs_attr_bundle *attrs)
5406{
5407 struct mlx5_ib_mcounters *mcounters;
5408
5409 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5410 if (!mcounters)
5411 return ERR_PTR(-ENOMEM);
5412
3b3233fb
RS		 5413 mutex_init(&mcounters->mcntrs_mutex);
5414
b29e2a13
RS		 5415 return &mcounters->ibcntrs;
5416}
5417
b5ca15ad 5418void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5419{
32f69e4b 5420 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 5421#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5422 cleanup_srcu_struct(&dev->mr_srcu);
5423#endif
16c1975f
MB		 5424 kfree(dev->port);
5425}
5426
b5ca15ad 5427int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5428{
5429 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 5430 const char *name;
e126ba97 5431 int err;
32f69e4b 5432 int i;
e126ba97 5433
508562d6 5434 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5435 GFP_KERNEL);
5436 if (!dev->port)
16c1975f 5437 return -ENOMEM;
0837e86a 5438
32f69e4b
DJ		 5439 for (i = 0; i < dev->num_ports; i++) {
5440 spin_lock_init(&dev->port[i].mp.mpi_lock);
5441 rwlock_init(&dev->roce[i].netdev_lock);
5442 }
5443
5444 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5445 if (err)
0837e86a 5446 goto err_free_port;
e126ba97 5447
32f69e4b 5448 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5449 for (i = 1; i <= dev->num_ports; i++) {
5450 err = get_port_caps(dev, i);
5451 if (err)
5452 break;
5453 }
5454 } else {
5455 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5456 }
5457 if (err)
5458 goto err_mp;
5459
1b5daf11
MD		 5460 if (mlx5_use_mad_ifc(dev))
5461 get_ext_port_caps(dev);
e126ba97 5462
4babcf97
AH		 5463 if (!mlx5_lag_is_active(mdev))
5464 name = "mlx5_%d";
5465 else
5466 name = "mlx5_bond_%d";
5467
5468 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 5469 dev->ib_dev.owner = THIS_MODULE;
5470 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5471 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5472 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 5473 dev->ib_dev.num_comp_vectors =
5474 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 5475 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5476
3cc297db
MB		 5477 mutex_init(&dev->cap_mask_mutex);
5478 INIT_LIST_HEAD(&dev->qp_list);
5479 spin_lock_init(&dev->reset_flow_resource_lock);
5480
24da0016
AL		 5481 spin_lock_init(&dev->memic.memic_lock);
5482 dev->memic.dev = mdev;
5483
3cc297db
MB		 5484#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5485 err = init_srcu_struct(&dev->mr_srcu);
5486 if (err)
5487 goto err_free_port;
5488#endif
5489
16c1975f 5490 return 0;
32f69e4b
DJ		 5491err_mp:
5492 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5493
5494err_free_port:
5495 kfree(dev->port);
5496
5497 return -ENOMEM;
5498}
5499
9a4ca38d
MB		 5500static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5501{
5502 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5503
5504 if (!dev->flow_db)
5505 return -ENOMEM;
5506
5507 mutex_init(&dev->flow_db->lock);
5508
5509 return 0;
5510}
5511
b5ca15ad
MB		 5512int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5513{
5514 struct mlx5_ib_dev *nic_dev;
5515
5516 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5517
5518 if (!nic_dev)
5519 return -EINVAL;
5520
5521 dev->flow_db = nic_dev->flow_db;
5522
5523 return 0;
5524}
5525
9a4ca38d
MB		 5526static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5527{
5528 kfree(dev->flow_db);
5529}
5530
b5ca15ad 5531int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5532{
5533 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5534 int err;
5535
e126ba97
EC		 5536 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5537 dev->ib_dev.uverbs_cmd_mask =
5538 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5539 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5540 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5541 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5542 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5543 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5544 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5545 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5546 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5547 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5548 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5549 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5550 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5551 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5552 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5553 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5554 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5555 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5556 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5557 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5558 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5559 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5560 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5561 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5562 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5563 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5564 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5565 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5566 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5567 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5568 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5569 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5570
5571 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5572 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5573 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5574 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5575 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5576 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5577 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5578 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5579 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5580 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5581 dev->ib_dev.mmap = mlx5_ib_mmap;
5582 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5583 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5584 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5585 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5586 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5587 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5588 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5589 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5590 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5591 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5592 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5593 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5594 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5595 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
d0e84c0a
YH		 5596 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5597 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
e126ba97
EC		 5598 dev->ib_dev.post_send = mlx5_ib_post_send;
5599 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5600 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5601 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5602 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5603 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5604 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5605 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5606 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5607 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5608 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5609 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5610 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5611 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5612 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5613 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5614 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5615 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5616 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5617 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5618 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5619 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5620
eff901d3
EC		 5621 if (mlx5_core_is_pf(mdev)) {
5622 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5623 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5624 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5625 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5626 }
e126ba97 5627
7c2344c3
MG		 5628 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5629
6e8484c5
MG		 5630 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5631
d2370e0a
MB		 5632 if (MLX5_CAP_GEN(mdev, imaicl)) {
5633 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5634 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5635 dev->ib_dev.uverbs_cmd_mask |=
5636 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5637 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5638 }
5639
938fe83c 5640 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5641 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5642 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5643 dev->ib_dev.uverbs_cmd_mask |=
5644 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5645 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5646 }
5647
24da0016
AL		 5648 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5649 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5650 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
6c29f57e 5651 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
24da0016
AL		 5652 }
5653
81e30880
YH		 5654 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5655 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5656 dev->ib_dev.uverbs_ex_cmd_mask |=
5657 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5658 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5659 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5660 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5661 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5662 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
b29e2a13
RS		 5663 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5664 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
1a1e03dc 5665 dev->ib_dev.read_counters = mlx5_ib_read_counters;
81e30880 5666
e126ba97
EC		 5667 err = init_node_data(dev);
5668 if (err)
16c1975f 5669 return err;
e126ba97 5670
c8b89924 5671 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5672 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5673 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 5674 mutex_init(&dev->lb_mutex);
5675
16c1975f
MB		 5676 return 0;
5677}
5678
8e6efa3a
MB		 5679static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5680{
5681 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5682 dev->ib_dev.query_port = mlx5_ib_query_port;
5683
5684 return 0;
5685}
5686
b5ca15ad 5687int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5688{
5689 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5690 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5691
5692 return 0;
5693}
5694
5695static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5696 u8 port_num)
5697{
5698 int i;
5699
5700 for (i = 0; i < dev->num_ports; i++) {
5701 dev->roce[i].dev = dev;
5702 dev->roce[i].native_port_num = i + 1;
5703 dev->roce[i].last_port_state = IB_PORT_DOWN;
5704 }
5705
5706 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5707 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5708 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5709 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5710 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5711 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5712
5713 dev->ib_dev.uverbs_ex_cmd_mask |=
5714 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5715 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5716 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5717 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5718 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5719
5720 return mlx5_add_netdev_notifier(dev, port_num);
5721}
5722
5723static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5724{
5725 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5726
5727 mlx5_remove_netdev_notifier(dev, port_num);
5728}
5729
5730int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5731{
5732 struct mlx5_core_dev *mdev = dev->mdev;
5733 enum rdma_link_layer ll;
5734 int port_type_cap;
5735 int err = 0;
5736 u8 port_num;
5737
5738 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5739 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5740 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5741
5742 if (ll == IB_LINK_LAYER_ETHERNET)
5743 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5744
5745 return err;
5746}
5747
5748void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5749{
5750 mlx5_ib_stage_common_roce_cleanup(dev);
5751}
5752
16c1975f
MB		 5753static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5754{
5755 struct mlx5_core_dev *mdev = dev->mdev;
5756 enum rdma_link_layer ll;
5757 int port_type_cap;
32f69e4b 5758 u8 port_num;
16c1975f
MB		 5759 int err;
5760
32f69e4b 5761 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 5762 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5763 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5764
fc24fc5e 5765 if (ll == IB_LINK_LAYER_ETHERNET) {
8e6efa3a
MB		 5766 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5767 if (err)
5768 return err;
7fd8aefb 5769
7fd8aefb 5770 err = mlx5_enable_eth(dev, port_num);
fc24fc5e 5771 if (err)
8e6efa3a 5772 goto cleanup;
fc24fc5e
AS		 5773 }
5774
16c1975f 5775 return 0;
8e6efa3a
MB		 5776cleanup:
5777 mlx5_ib_stage_common_roce_cleanup(dev);
5778
5779 return err;
16c1975f 5780}
e126ba97 5781
16c1975f
MB		 5782static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5783{
5784 struct mlx5_core_dev *mdev = dev->mdev;
5785 enum rdma_link_layer ll;
5786 int port_type_cap;
e126ba97 5787
16c1975f
MB		 5788 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5789 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5790
5791 if (ll == IB_LINK_LAYER_ETHERNET) {
5792 mlx5_disable_eth(dev);
8e6efa3a 5793 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 5794 }
16c1975f 5795}
6aec21f6 5796
b5ca15ad 5797int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5798{
5799 return create_dev_resources(&dev->devr);
5800}
5801
b5ca15ad 5802void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5803{
5804 destroy_dev_resources(&dev->devr);
5805}
5806
5807static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5808{
07321b3c
MB		 5809 mlx5_ib_internal_fill_odp_caps(dev);
5810
16c1975f
MB		 5811 return mlx5_ib_odp_init_one(dev);
5812}
4a2da0b8 5813
b5ca15ad 5814int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 5815{
5e1e7612
MB		 5816 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5817 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
5818 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
5819
5820 return mlx5_ib_alloc_counters(dev);
5821 }
16c1975f
MB		 5822
5823 return 0;
5824}
5825
b5ca15ad 5826void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5827{
5828 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5829 mlx5_ib_dealloc_counters(dev);
5830}
5831
5832static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5833{
a9e546e7
PP		 5834 return mlx5_ib_init_cong_debugfs(dev,
5835 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5836}
5837
5838static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5839{
a9e546e7
PP		 5840 mlx5_ib_cleanup_cong_debugfs(dev,
5841 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5842}
5843
5844static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5845{
5fe9dec0 5846 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 5847 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 5848}
5849
5850static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5851{
5852 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5853}
5854
b5ca15ad 5855int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5856{
5857 int err;
5fe9dec0
EC		 5858
5859 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5860 if (err)
16c1975f 5861 return err;
5fe9dec0
EC		 5862
5863 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5864 if (err)
16c1975f 5865 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 5866
16c1975f
MB		 5867 return err;
5868}
0837e86a 5869
b5ca15ad 5870void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5871{
5872 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5873 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5874}
e126ba97 5875
8c84660b
MB		 5876static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5877{
5878 return populate_specs_root(dev);
5879}
5880
b5ca15ad 5881int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5882{
5883 return ib_register_device(&dev->ib_dev, NULL);
5884}
5885
8c84660b
MB		 5886static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5887{
5888 depopulate_specs_root(dev);
5889}
5890
03fe2deb 5891void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5892{
42cea83f 5893 destroy_umrc_res(dev);
16c1975f
MB		 5894}
5895
03fe2deb 5896void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5897{
42cea83f 5898 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 5899}
5900
03fe2deb 5901int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 5902{
42cea83f 5903 return create_umr_res(dev);
16c1975f
MB		 5904}
5905
5906static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5907{
03404e8a
MG		 5908 init_delay_drop(dev);
5909
16c1975f
MB		 5910 return 0;
5911}
5912
5913static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5914{
5915 cancel_delay_drop(dev);
5916}
5917
b5ca15ad 5918int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5919{
5920 int err;
5921 int i;
5922
e126ba97 5923 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 5924 err = device_create_file(&dev->ib_dev.dev,
5925 mlx5_class_attributes[i]);
5926 if (err)
16c1975f 5927 return err;
e126ba97
EC		 5928 }
5929
16c1975f
MB		 5930 return 0;
5931}
5932
fc385b7a
MB		 5933static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5934{
5935 mlx5_ib_register_vport_reps(dev);
5936
5937 return 0;
5938}
5939
5940static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5941{
5942 mlx5_ib_unregister_vport_reps(dev);
5943}
5944
b5ca15ad
MB		 5945void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5946 const struct mlx5_ib_profile *profile,
5947 int stage)
16c1975f
MB		 5948{
5949 /* Number of stages to cleanup */
5950 while (stage) {
5951 stage--;
5952 if (profile->stage[stage].cleanup)
5953 profile->stage[stage].cleanup(dev);
5954 }
e126ba97 5955
16c1975f
MB		 5956 ib_dealloc_device((struct ib_device *)dev);
5957}
e126ba97 5958
32f69e4b
DJ		 5959static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5960
b5ca15ad
MB		 5961void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5962 const struct mlx5_ib_profile *profile)
16c1975f 5963{
16c1975f
MB		 5964 int err;
5965 int i;
e126ba97 5966
16c1975f 5967 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 5968
16c1975f
MB		 5969 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5970 if (profile->stage[i].init) {
5971 err = profile->stage[i].init(dev);
5972 if (err)
5973 goto err_out;
5974 }
5975 }
0837e86a 5976
16c1975f
MB		 5977 dev->profile = profile;
5978 dev->ib_active = true;
6aec21f6 5979
16c1975f 5980 return dev;
e126ba97 5981
16c1975f
MB		 5982err_out:
5983 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 5984
16c1975f
MB		 5985 return NULL;
5986}
0837e86a 5987
16c1975f
MB		 5988static const struct mlx5_ib_profile pf_profile = {
5989 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5990 mlx5_ib_stage_init_init,
5991 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 5992 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5993 mlx5_ib_stage_flow_db_init,
5994 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 5995 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5996 mlx5_ib_stage_caps_init,
5997 NULL),
8e6efa3a
MB		 5998 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5999 mlx5_ib_stage_non_default_cb,
6000 NULL),
16c1975f
MB		 6001 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6002 mlx5_ib_stage_roce_init,
6003 mlx5_ib_stage_roce_cleanup),
6004 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6005 mlx5_ib_stage_dev_res_init,
6006 mlx5_ib_stage_dev_res_cleanup),
6007 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6008 mlx5_ib_stage_odp_init,
3cc297db 6009 NULL),
16c1975f
MB		 6010 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6011 mlx5_ib_stage_counters_init,
6012 mlx5_ib_stage_counters_cleanup),
6013 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6014 mlx5_ib_stage_cong_debugfs_init,
6015 mlx5_ib_stage_cong_debugfs_cleanup),
6016 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6017 mlx5_ib_stage_uar_init,
6018 mlx5_ib_stage_uar_cleanup),
6019 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6020 mlx5_ib_stage_bfrag_init,
6021 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6022 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6023 NULL,
6024 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6025 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6026 mlx5_ib_stage_populate_specs,
6027 mlx5_ib_stage_depopulate_specs),
16c1975f
MB		 6028 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6029 mlx5_ib_stage_ib_reg_init,
6030 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6031 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6032 mlx5_ib_stage_post_ib_reg_umr_init,
6033 NULL),
16c1975f
MB		 6034 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6035 mlx5_ib_stage_delay_drop_init,
6036 mlx5_ib_stage_delay_drop_cleanup),
6037 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6038 mlx5_ib_stage_class_attr_init,
6039 NULL),
16c1975f 6040};
e126ba97 6041
b5ca15ad
MB		 6042static const struct mlx5_ib_profile nic_rep_profile = {
6043 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6044 mlx5_ib_stage_init_init,
6045 mlx5_ib_stage_init_cleanup),
6046 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6047 mlx5_ib_stage_flow_db_init,
6048 mlx5_ib_stage_flow_db_cleanup),
6049 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6050 mlx5_ib_stage_caps_init,
6051 NULL),
6052 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6053 mlx5_ib_stage_rep_non_default_cb,
6054 NULL),
6055 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6056 mlx5_ib_stage_rep_roce_init,
6057 mlx5_ib_stage_rep_roce_cleanup),
6058 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6059 mlx5_ib_stage_dev_res_init,
6060 mlx5_ib_stage_dev_res_cleanup),
6061 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6062 mlx5_ib_stage_counters_init,
6063 mlx5_ib_stage_counters_cleanup),
6064 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6065 mlx5_ib_stage_uar_init,
6066 mlx5_ib_stage_uar_cleanup),
6067 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6068 mlx5_ib_stage_bfrag_init,
6069 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6070 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6071 NULL,
6072 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6073 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6074 mlx5_ib_stage_populate_specs,
6075 mlx5_ib_stage_depopulate_specs),
b5ca15ad
MB		 6076 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6077 mlx5_ib_stage_ib_reg_init,
6078 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6079 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6080 mlx5_ib_stage_post_ib_reg_umr_init,
6081 NULL),
b5ca15ad
MB		 6082 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6083 mlx5_ib_stage_class_attr_init,
6084 NULL),
6085 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6086 mlx5_ib_stage_rep_reg_init,
6087 mlx5_ib_stage_rep_reg_cleanup),
6088};
6089
32f69e4b
DJ		 6090static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
6091{
6092 struct mlx5_ib_multiport_info *mpi;
6093 struct mlx5_ib_dev *dev;
6094 bool bound = false;
6095 int err;
6096
6097 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6098 if (!mpi)
6099 return NULL;
6100
6101 mpi->mdev = mdev;
6102
6103 err = mlx5_query_nic_vport_system_image_guid(mdev,
6104 &mpi->sys_image_guid);
6105 if (err) {
6106 kfree(mpi);
6107 return NULL;
6108 }
6109
6110 mutex_lock(&mlx5_ib_multiport_mutex);
6111 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6112 if (dev->sys_image_guid == mpi->sys_image_guid)
6113 bound = mlx5_ib_bind_slave_port(dev, mpi);
6114
6115 if (bound) {
6116 rdma_roce_rescan_device(&dev->ib_dev);
6117 break;
6118 }
6119 }
6120
6121 if (!bound) {
6122 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6123 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6124 } else {
6125 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
6126 }
6127 mutex_unlock(&mlx5_ib_multiport_mutex);
6128
6129 return mpi;
6130}
6131
16c1975f
MB		 6132static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6133{
32f69e4b 6134 enum rdma_link_layer ll;
b5ca15ad 6135 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 6136 int port_type_cap;
6137
b5ca15ad
MB		 6138 printk_once(KERN_INFO "%s", mlx5_version);
6139
32f69e4b
DJ		 6140 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6141 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6142
6143 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
6144 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
6145
6146 return mlx5_ib_add_slave_port(mdev, port_num);
6147 }
6148
b5ca15ad
MB		 6149 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6150 if (!dev)
6151 return NULL;
6152
6153 dev->mdev = mdev;
6154 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6155 MLX5_CAP_GEN(mdev, num_vhca_ports));
6156
6157 if (MLX5_VPORT_MANAGER(mdev) &&
6158 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6159 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6160
6161 return __mlx5_ib_add(dev, &nic_rep_profile);
6162 }
6163
6164 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6165}
6166
9603b61d 6167static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6168{
32f69e4b
DJ		 6169 struct mlx5_ib_multiport_info *mpi;
6170 struct mlx5_ib_dev *dev;
6171
6172 if (mlx5_core_is_mp_slave(mdev)) {
6173 mpi = context;
6174 mutex_lock(&mlx5_ib_multiport_mutex);
6175 if (mpi->ibdev)
6176 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6177 list_del(&mpi->list);
6178 mutex_unlock(&mlx5_ib_multiport_mutex);
6179 return;
6180 }
6aec21f6 6181
32f69e4b 6182 dev = context;
16c1975f 6183 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6184}
6185
9603b61d
JM		 6186static struct mlx5_interface mlx5_ib_interface = {
6187 .add = mlx5_ib_add,
6188 .remove = mlx5_ib_remove,
6189 .event = mlx5_ib_event,
d9aaed83
AK		 6190#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6191 .pfault = mlx5_ib_pfault,
6192#endif
64613d94 6193 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6194};
6195
c44ef998
IL		 6196unsigned long mlx5_ib_get_xlt_emergency_page(void)
6197{
6198 mutex_lock(&xlt_emergency_page_mutex);
6199 return xlt_emergency_page;
6200}
6201
6202void mlx5_ib_put_xlt_emergency_page(void)
6203{
6204 mutex_unlock(&xlt_emergency_page_mutex);
6205}
6206
e126ba97
EC		 6207static int __init mlx5_ib_init(void)
6208{
6aec21f6
HE		 6209 int err;
6210
c44ef998
IL		 6211 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6212 if (!xlt_emergency_page)
6213 return -ENOMEM;
6214
6215 mutex_init(&xlt_emergency_page_mutex);
6216
d69a24e0 6217 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6218 if (!mlx5_ib_event_wq) {
6219 free_page(xlt_emergency_page);
d69a24e0 6220 return -ENOMEM;
c44ef998 6221 }
d69a24e0 6222
81713d37 6223 mlx5_ib_odp_init();
9603b61d 6224
6aec21f6 6225 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6226
6aec21f6 6227 return err;
e126ba97
EC		 6228}
6229
6230static void __exit mlx5_ib_cleanup(void)
6231{
9603b61d 6232 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6233 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6234 mutex_destroy(&xlt_emergency_page_mutex);
6235 free_page(xlt_emergency_page);
e126ba97
EC		 6236}
6237
6238module_init(mlx5_ib_init);
6239module_exit(mlx5_ib_cleanup);
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