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RDMA/mlx5: Consider eswitch encap mode
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
cecae747 55#include <linux/mlx5/eswitch.h>
7c2344c3 56#include <linux/list.h>
e126ba97
EC		 57#include <rdma/ib_smi.h>
58#include <rdma/ib_umem.h>
038d2ef8
MG		 59#include <linux/in.h>
60#include <linux/etherdevice.h>
e126ba97 61#include "mlx5_ib.h"
fc385b7a 62#include "ib_rep.h"
e1f24a79 63#include "cmd.h"
f3da6577 64#include "srq.h"
3346c487 65#include <linux/mlx5/fs_helpers.h>
c6475a0b 66#include <linux/mlx5/accel.h>
8c84660b 67#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 68#include <rdma/mlx5_user_ioctl_verbs.h>
69#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 70
71#define UVERBS_MODULE_NAME mlx5_ib
72#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 73
74#define DRIVER_NAME "mlx5_ib"
b359911d 75#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 76
77MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
79MODULE_LICENSE("Dual BSD/GPL");
e126ba97 80
e126ba97
EC		 81static char mlx5_version[] =
82 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 83 DRIVER_VERSION "\n";
e126ba97 84
d69a24e0
DJ		 85struct mlx5_ib_event_work {
86 struct work_struct work;
df097a27
SM		 87 union {
88 struct mlx5_ib_dev *dev;
89 struct mlx5_ib_multiport_info *mpi;
90 };
91 bool is_slave;
134e9349 92 unsigned int event;
df097a27 93 void *param;
d69a24e0
DJ		 94};
95
da7525d2
EBE		 96enum {
97 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
98};
99
d69a24e0 100static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 101static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
102static LIST_HEAD(mlx5_ib_dev_list);
103/*
104 * This mutex should be held when accessing either of the above lists
105 */
106static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
107
c44ef998
IL		 108/* We can't use an array for xlt_emergency_page because dma_map_single
109 * doesn't work on kernel modules memory
110 */
111static unsigned long xlt_emergency_page;
112static struct mutex xlt_emergency_page_mutex;
113
32f69e4b
DJ		 114struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
115{
116 struct mlx5_ib_dev *dev;
117
118 mutex_lock(&mlx5_ib_multiport_mutex);
119 dev = mpi->ibdev;
120 mutex_unlock(&mlx5_ib_multiport_mutex);
121 return dev;
122}
123
1b5daf11 124static enum rdma_link_layer
ebd61f68 125mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 126{
ebd61f68 127 switch (port_type_cap) {
1b5daf11
MD		 128 case MLX5_CAP_PORT_TYPE_IB:
129 return IB_LINK_LAYER_INFINIBAND;
130 case MLX5_CAP_PORT_TYPE_ETH:
131 return IB_LINK_LAYER_ETHERNET;
132 default:
133 return IB_LINK_LAYER_UNSPECIFIED;
134 }
135}
136
ebd61f68
AS		 137static enum rdma_link_layer
138mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
139{
140 struct mlx5_ib_dev *dev = to_mdev(device);
141 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
142
143 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
144}
145
fd65f1b8
MS		 146static int get_port_state(struct ib_device *ibdev,
147 u8 port_num,
148 enum ib_port_state *state)
149{
150 struct ib_port_attr attr;
151 int ret;
152
153 memset(&attr, 0, sizeof(attr));
3023a1e9 154 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 155 if (!ret)
156 *state = attr.state;
157 return ret;
158}
159
35b0aa67
MB		 160static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
161 struct net_device *ndev,
162 u8 *port_num)
163{
164 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
165 struct net_device *rep_ndev;
166 struct mlx5_ib_port *port;
167 int i;
168
169 for (i = 0; i < dev->num_ports; i++) {
170 port = &dev->port[i];
171 if (!port->rep)
172 continue;
173
174 read_lock(&port->roce.netdev_lock);
175 rep_ndev = mlx5_ib_get_rep_netdev(esw,
176 port->rep->vport);
177 if (rep_ndev == ndev) {
178 read_unlock(&port->roce.netdev_lock);
179 *port_num = i + 1;
180 return &port->roce;
181 }
182 read_unlock(&port->roce.netdev_lock);
183 }
184
185 return NULL;
186}
187
fc24fc5e
AS		 188static int mlx5_netdev_event(struct notifier_block *this,
189 unsigned long event, void *ptr)
190{
7fd8aefb 191 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 192 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 193 u8 port_num = roce->native_port_num;
194 struct mlx5_core_dev *mdev;
195 struct mlx5_ib_dev *ibdev;
196
197 ibdev = roce->dev;
32f69e4b
DJ		 198 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
199 if (!mdev)
200 return NOTIFY_DONE;
fc24fc5e 201
5ec8c83e
AH		 202 switch (event) {
203 case NETDEV_REGISTER:
35b0aa67
MB		 204 /* Should already be registered during the load */
205 if (ibdev->is_rep)
206 break;
7fd8aefb 207 write_lock(&roce->netdev_lock);
dce45af5 208 if (ndev->dev.parent == mdev->device)
842a9c83 209 roce->netdev = ndev;
7fd8aefb 210 write_unlock(&roce->netdev_lock);
5ec8c83e 211 break;
fc24fc5e 212
842a9c83 213 case NETDEV_UNREGISTER:
35b0aa67 214 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 215 write_lock(&roce->netdev_lock);
216 if (roce->netdev == ndev)
217 roce->netdev = NULL;
218 write_unlock(&roce->netdev_lock);
219 break;
220
fd65f1b8 221 case NETDEV_CHANGE:
5ec8c83e 222 case NETDEV_UP:
88621dfe 223 case NETDEV_DOWN: {
7fd8aefb 224 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 225 struct net_device *upper = NULL;
226
227 if (lag_ndev) {
228 upper = netdev_master_upper_dev_get(lag_ndev);
229 dev_put(lag_ndev);
230 }
231
35b0aa67
MB		 232 if (ibdev->is_rep)
233 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
234 if (!roce)
235 return NOTIFY_DONE;
7fd8aefb 236 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 237 && ibdev->ib_active) {
626bc02d 238 struct ib_event ibev = { };
fd65f1b8 239 enum ib_port_state port_state;
5ec8c83e 240
7fd8aefb
DJ		 241 if (get_port_state(&ibdev->ib_dev, port_num,
242 &port_state))
243 goto done;
fd65f1b8 244
7fd8aefb
DJ		 245 if (roce->last_port_state == port_state)
246 goto done;
fd65f1b8 247
7fd8aefb 248 roce->last_port_state = port_state;
5ec8c83e 249 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 250 if (port_state == IB_PORT_DOWN)
251 ibev.event = IB_EVENT_PORT_ERR;
252 else if (port_state == IB_PORT_ACTIVE)
253 ibev.event = IB_EVENT_PORT_ACTIVE;
254 else
7fd8aefb 255 goto done;
fd65f1b8 256
7fd8aefb 257 ibev.element.port_num = port_num;
5ec8c83e
AH		 258 ib_dispatch_event(&ibev);
259 }
260 break;
88621dfe 261 }
fc24fc5e 262
5ec8c83e
AH		 263 default:
264 break;
265 }
7fd8aefb 266done:
32f69e4b 267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return NOTIFY_DONE;
269}
270
271static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
272 u8 port_num)
273{
274 struct mlx5_ib_dev *ibdev = to_mdev(device);
275 struct net_device *ndev;
32f69e4b
DJ		 276 struct mlx5_core_dev *mdev;
277
278 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
279 if (!mdev)
280 return NULL;
fc24fc5e 281
32f69e4b 282 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 283 if (ndev)
32f69e4b 284 goto out;
88621dfe 285
fc24fc5e
AS		 286 /* Ensure ndev does not disappear before we invoke dev_hold()
287 */
95579e78
MB		 288 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
289 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 290 if (ndev)
291 dev_hold(ndev);
95579e78 292 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 293
32f69e4b
DJ		 294out:
295 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 296 return ndev;
297}
298
32f69e4b
DJ		 299struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
300 u8 ib_port_num,
301 u8 *native_port_num)
302{
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 ib_port_num);
305 struct mlx5_core_dev *mdev = NULL;
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
210b1f78
MB		 309 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
310 ll != IB_LINK_LAYER_ETHERNET) {
311 if (native_port_num)
312 *native_port_num = ib_port_num;
313 return ibdev->mdev;
314 }
315
32f69e4b
DJ		 316 if (native_port_num)
317 *native_port_num = 1;
318
32f69e4b
DJ		 319 port = &ibdev->port[ib_port_num - 1];
320 if (!port)
321 return NULL;
322
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
325 if (mpi && !mpi->unaffiliate) {
326 mdev = mpi->mdev;
327 /* If it's the master no need to refcount, it'll exist
328 * as long as the ib_dev exists.
329 */
330 if (!mpi->is_master)
331 mpi->mdev_refcnt++;
332 }
333 spin_unlock(&port->mp.mpi_lock);
334
335 return mdev;
336}
337
338void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
339{
340 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
341 port_num);
342 struct mlx5_ib_multiport_info *mpi;
343 struct mlx5_ib_port *port;
344
345 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
346 return;
347
348 port = &ibdev->port[port_num - 1];
349
350 spin_lock(&port->mp.mpi_lock);
351 mpi = ibdev->port[port_num - 1].mp.mpi;
352 if (mpi->is_master)
353 goto out;
354
355 mpi->mdev_refcnt--;
356 if (mpi->unaffiliate)
357 complete(&mpi->unref_comp);
358out:
359 spin_unlock(&port->mp.mpi_lock);
360}
361
08e8676f
AL		 362static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
363 u8 *active_width)
f1b65df5
NO		 364{
365 switch (eth_proto_oper) {
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
368 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
369 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
370 *active_width = IB_WIDTH_1X;
371 *active_speed = IB_SPEED_SDR;
372 break;
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_QDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
386 *active_width = IB_WIDTH_1X;
387 *active_speed = IB_SPEED_EDR;
388 break;
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
393 *active_width = IB_WIDTH_4X;
394 *active_speed = IB_SPEED_QDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_HDR;
401 break;
402 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
403 *active_width = IB_WIDTH_4X;
404 *active_speed = IB_SPEED_FDR;
405 break;
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
410 *active_width = IB_WIDTH_4X;
411 *active_speed = IB_SPEED_EDR;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
08e8676f
AL		 420static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
421 u8 *active_width)
422{
423 switch (eth_proto_oper) {
424 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
425 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
426 *active_width = IB_WIDTH_1X;
427 *active_speed = IB_SPEED_SDR;
428 break;
429 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
430 *active_width = IB_WIDTH_1X;
431 *active_speed = IB_SPEED_DDR;
432 break;
433 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
434 *active_width = IB_WIDTH_1X;
435 *active_speed = IB_SPEED_QDR;
436 break;
437 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
438 *active_width = IB_WIDTH_4X;
439 *active_speed = IB_SPEED_QDR;
440 break;
441 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
442 *active_width = IB_WIDTH_1X;
443 *active_speed = IB_SPEED_EDR;
444 break;
445 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 446 *active_width = IB_WIDTH_2X;
447 *active_speed = IB_SPEED_EDR;
448 break;
08e8676f
AL		 449 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
450 *active_width = IB_WIDTH_1X;
451 *active_speed = IB_SPEED_HDR;
452 break;
cd272875
AL		 453 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
454 *active_width = IB_WIDTH_4X;
455 *active_speed = IB_SPEED_EDR;
456 break;
08e8676f
AL		 457 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
458 *active_width = IB_WIDTH_2X;
459 *active_speed = IB_SPEED_HDR;
460 break;
461 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
462 *active_width = IB_WIDTH_4X;
463 *active_speed = IB_SPEED_HDR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470}
471
472static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
473 u8 *active_width, bool ext)
474{
475 return ext ?
476 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
477 active_width) :
478 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
479 active_width);
480}
481
095b0927
IT		 482static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
483 struct ib_port_attr *props)
3f89a643
AS		 484{
485 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 486 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 487 struct mlx5_core_dev *mdev;
88621dfe 488 struct net_device *ndev, *upper;
3f89a643 489 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 490 bool put_mdev = true;
c876a1b7 491 u16 qkey_viol_cntr;
f1b65df5 492 u32 eth_prot_oper;
b3cbd6f0 493 u8 mdev_port_num;
08e8676f 494 bool ext;
095b0927 495 int err;
3f89a643 496
b3cbd6f0
DJ		 497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499 /* This means the port isn't affiliated yet. Get the
500 * info for the master port instead.
501 */
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
f1b65df5
NO		 508 /* Possible bad flows are checked before filling out props so in case
509 * of an error it will still be zeroed out.
26628e2d 510 * Use native port in case of reps
50f22fd8 511 */
26628e2d
MB		 512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514 1);
515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 mdev_port_num);
095b0927 518 if (err)
b3cbd6f0 519 goto out;
08e8676f
AL		 520 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 522
7672ed33
HL		 523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
f1b65df5 526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 527 &props->active_width, ext);
3f89a643 528
2f944c0f
JG		 529 props->port_cap_flags |= IB_PORT_CM_SUP;
530 props->ip_gids = true;
3f89a643
AS		 531
532 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
533 roce_address_table_size);
534 props->max_mtu = IB_MTU_4096;
535 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
536 props->pkey_tbl_len = 1;
537 props->state = IB_PORT_DOWN;
538 props->phys_state = 3;
539
b3cbd6f0 540 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 541 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 542
b3cbd6f0
DJ		 543 /* If this is a stub query for an unaffiliated port stop here */
544 if (!put_mdev)
545 goto out;
546
3f89a643
AS		 547 ndev = mlx5_ib_get_netdev(device, port_num);
548 if (!ndev)
b3cbd6f0 549 goto out;
3f89a643 550
7c34ec19 551 if (dev->lag_active) {
88621dfe
AH		 552 rcu_read_lock();
553 upper = netdev_master_upper_dev_get_rcu(ndev);
554 if (upper) {
555 dev_put(ndev);
556 ndev = upper;
557 dev_hold(ndev);
558 }
559 rcu_read_unlock();
560 }
561
3f89a643
AS		 562 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
563 props->state = IB_PORT_ACTIVE;
564 props->phys_state = 5;
565 }
566
567 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
568
569 dev_put(ndev);
570
571 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 572out:
573 if (put_mdev)
574 mlx5_ib_put_native_port_mdev(dev, port_num);
575 return err;
3f89a643
AS		 576}
577
095b0927
IT		 578static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
579 unsigned int index, const union ib_gid *gid,
580 const struct ib_gid_attr *attr)
3cca2606 581{
095b0927 582 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 583 u16 vlan_id = 0xffff;
095b0927
IT		 584 u8 roce_version = 0;
585 u8 roce_l3_type = 0;
095b0927 586 u8 mac[ETH_ALEN];
a70c0739 587 int ret;
095b0927
IT		 588
589 if (gid) {
590 gid_type = attr->gid_type;
a70c0739
PP		 591 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
592 if (ret)
593 return ret;
3cca2606
AS		 594 }
595
095b0927 596 switch (gid_type) {
3cca2606 597 case IB_GID_TYPE_IB:
095b0927 598 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 599 break;
600 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 601 roce_version = MLX5_ROCE_VERSION_2;
602 if (ipv6_addr_v4mapped((void *)gid))
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
604 else
605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 606 break;
607
608 default:
095b0927 609 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 610 }
611
095b0927 612 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 613 roce_l3_type, gid->raw, mac,
a70c0739 614 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 615 port_num);
3cca2606
AS		 616}
617
f4df9a7c 618static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 619 __always_unused void **context)
620{
414448d2 621 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 622 attr->index, &attr->gid, attr);
3cca2606
AS		 623}
624
414448d2
PP		 625static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
626 __always_unused void **context)
3cca2606 627{
414448d2
PP		 628 return set_roce_addr(to_mdev(attr->device), attr->port_num,
629 attr->index, NULL, NULL);
3cca2606
AS		 630}
631
47ec3866
PP		 632__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
633 const struct ib_gid_attr *attr)
2811ba51 634{
47ec3866 635 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 636 return 0;
637
638 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
639}
640
1b5daf11
MD		 641static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
642{
7fae6655
NO		 643 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
644 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
645 return 0;
1b5daf11
MD		 646}
647
648enum {
649 MLX5_VPORT_ACCESS_METHOD_MAD,
650 MLX5_VPORT_ACCESS_METHOD_HCA,
651 MLX5_VPORT_ACCESS_METHOD_NIC,
652};
653
654static int mlx5_get_vport_access_method(struct ib_device *ibdev)
655{
656 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
657 return MLX5_VPORT_ACCESS_METHOD_MAD;
658
ebd61f68 659 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 660 IB_LINK_LAYER_ETHERNET)
661 return MLX5_VPORT_ACCESS_METHOD_NIC;
662
663 return MLX5_VPORT_ACCESS_METHOD_HCA;
664}
665
da7525d2 666static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 667 u8 atomic_size_qp,
da7525d2
EBE		 668 struct ib_device_attr *props)
669{
670 u8 tmp;
671 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 672 u8 atomic_req_8B_endianness_mode =
bd10838a 673 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 674
675 /* Check if HW supports 8 bytes standard atomic operations and capable
676 * of host endianness respond
677 */
678 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
679 if (((atomic_operations & tmp) == tmp) &&
680 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
681 (atomic_req_8B_endianness_mode)) {
682 props->atomic_cap = IB_ATOMIC_HCA;
683 } else {
684 props->atomic_cap = IB_ATOMIC_NONE;
685 }
686}
687
776a3906
MS		 688static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
689 struct ib_device_attr *props)
690{
691 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
692
693 get_atomic_caps(dev, atomic_size_qp, props);
694}
695
696static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
697 struct ib_device_attr *props)
698{
699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
700
701 get_atomic_caps(dev, atomic_size_qp, props);
702}
703
704bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
705{
706 struct ib_device_attr props = {};
707
708 get_atomic_caps_dc(dev, &props);
709 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
710}
1b5daf11
MD		 711static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713{
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
1b5daf11
MD		 731
732 default:
733 return -EINVAL;
734 }
3f89a643
AS		 735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
1b5daf11
MD		 741}
742
743static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745{
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762}
763
764static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766{
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780}
781
782static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784{
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
1b5daf11
MD		 799
800 default:
801 return -EINVAL;
802 }
3f89a643
AS		 803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
1b5daf11
MD		 808}
809
810struct mlx5_reg_node_desc {
bd99fdea 811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 812};
813
814static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815{
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826}
827
e126ba97 828static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 829 struct ib_device_attr *props,
830 struct ib_udata *uhw)
e126ba97
EC		 831{
832 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 833 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 834 int err = -ENOMEM;
288c01b7 835 int max_sq_desc;
e126ba97
EC		 836 int max_rq_sg;
837 int max_sq_sg;
e0238a6a 838 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 839 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 840 struct mlx5_ib_query_device_resp resp = {};
841 size_t resp_len;
842 u64 max_tso;
e126ba97 843
402ca536
BW		 844 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
845 if (uhw->outlen && uhw->outlen < resp_len)
846 return -EINVAL;
847 else
848 resp.response_length = resp_len;
849
850 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 851 return -EINVAL;
852
1b5daf11
MD		 853 memset(props, 0, sizeof(*props));
854 err = mlx5_query_system_image_guid(ibdev,
855 &props->sys_image_guid);
856 if (err)
857 return err;
e126ba97 858
1b5daf11 859 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 860 if (err)
1b5daf11 861 return err;
e126ba97 862
1b5daf11
MD		 863 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
864 if (err)
865 return err;
e126ba97 866
9603b61d
JM		 867 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
868 (fw_rev_min(dev->mdev) << 16) |
869 fw_rev_sub(dev->mdev);
e126ba97
EC		 870 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
871 IB_DEVICE_PORT_ACTIVE_EVENT |
872 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 873 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 874
875 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 876 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 877 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 878 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 879 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 880 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 881 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 882 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 883 if (MLX5_CAP_GEN(mdev, imaicl)) {
884 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
885 IB_DEVICE_MEM_WINDOW_TYPE_2B;
886 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 887 /* We support 'Gappy' memory registration too */
888 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 889 }
e126ba97 890 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 891 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 892 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
893 /* At this stage no support for signature handover */
894 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
895 IB_PROT_T10DIF_TYPE_2 |
896 IB_PROT_T10DIF_TYPE_3;
897 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
898 IB_GUARD_T10DIF_CSUM;
899 }
938fe83c 900 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 901 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 902
85c7c014 903 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 904 if (MLX5_CAP_ETH(mdev, csum_cap)) {
905 /* Legacy bit to support old userspace libraries */
88115fe7 906 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 907 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
908 }
909
910 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
911 props->raw_packet_caps |=
912 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 913
402ca536
BW		 914 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
915 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
916 if (max_tso) {
917 resp.tso_caps.max_tso = 1 << max_tso;
918 resp.tso_caps.supported_qpts |=
919 1 << IB_QPT_RAW_PACKET;
920 resp.response_length += sizeof(resp.tso_caps);
921 }
922 }
31f69a82
YH		 923
924 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
925 resp.rss_caps.rx_hash_function =
926 MLX5_RX_HASH_FUNC_TOEPLITZ;
927 resp.rss_caps.rx_hash_fields_mask =
928 MLX5_RX_HASH_SRC_IPV4 |
929 MLX5_RX_HASH_DST_IPV4 |
930 MLX5_RX_HASH_SRC_IPV6 |
931 MLX5_RX_HASH_DST_IPV6 |
932 MLX5_RX_HASH_SRC_PORT_TCP |
933 MLX5_RX_HASH_DST_PORT_TCP |
934 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 935 MLX5_RX_HASH_DST_PORT_UDP |
936 MLX5_RX_HASH_INNER;
2d93fc85
MB		 937 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
938 MLX5_ACCEL_IPSEC_CAP_DEVICE)
939 resp.rss_caps.rx_hash_fields_mask |=
940 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 941 resp.response_length += sizeof(resp.rss_caps);
942 }
943 } else {
944 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
945 resp.response_length += sizeof(resp.tso_caps);
946 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
947 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 948 }
949
f0313965
ES		 950 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
951 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
952 props->device_cap_flags |= IB_DEVICE_UD_TSO;
953 }
954
03404e8a 955 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 956 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
957 raw_support)
03404e8a
MG		 958 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
959
1d54f890
YH		 960 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
961 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
962 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
963
cff5a0f3 964 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 965 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
966 raw_support) {
e8161334 967 /* Legacy bit to support old userspace libraries */
cff5a0f3 968 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 969 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
970 }
cff5a0f3 971
24da0016
AL		 972 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
973 props->max_dm_size =
974 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
975 }
976
da6d6ba3
MG		 977 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
978 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
979
b1383aa6
NO		 980 if (MLX5_CAP_GEN(mdev, end_pad))
981 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
982
1b5daf11
MD		 983 props->vendor_part_id = mdev->pdev->device;
984 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 985
986 props->max_mr_size = ~0ull;
e0238a6a 987 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 988 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
989 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
990 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
991 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 992 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
993 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
994 sizeof(struct mlx5_wqe_raddr_seg)) /
995 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 996 props->max_send_sge = max_sq_sg;
997 props->max_recv_sge = max_rq_sg;
986ef95e 998 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 999 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 1000 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 1001 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 1008 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 1009 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 1010 props->max_fast_reg_page_list_len =
1011 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 1012 get_atomic_caps_qp(dev, props);
81bea28f 1013 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1014 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1015 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1016 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1017 props->max_mcast_grp;
1018 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1019 props->max_ah = INT_MAX;
7c60bcbb
MB		 1020 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1021 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1022
e502b8b0
LR		 1023 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1024 if (MLX5_CAP_GEN(mdev, pg))
1025 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1026 props->odp_caps = dev->odp_caps;
1027 }
8cdd312c 1028
051f2630
LR		 1029 if (MLX5_CAP_GEN(mdev, cd))
1030 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1031
eff901d3
EC		 1032 if (!mlx5_core_is_pf(mdev))
1033 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1034
31f69a82 1035 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1036 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1037 props->rss_caps.max_rwq_indirection_tables =
1038 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1039 props->rss_caps.max_rwq_indirection_table_size =
1040 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1041 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1042 props->max_wq_type_rq =
1043 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1044 }
1045
eb761894 1046 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 1047 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1048 props->tm_caps.max_num_tags =
eb761894 1049 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 1050 props->tm_caps.flags = IB_TM_CAP_RC;
1051 props->tm_caps.max_ops =
eb761894 1052 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1053 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1054 }
1055
87ab3f52
YC		 1056 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1057 props->cq_caps.max_cq_moderation_count =
1058 MLX5_MAX_CQ_COUNT;
1059 props->cq_caps.max_cq_moderation_period =
1060 MLX5_MAX_CQ_PERIOD;
1061 }
1062
7e43a2a5 1063 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 1064 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1065
1066 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1067 resp.cqe_comp_caps.max_num =
1068 MLX5_CAP_GEN(dev->mdev,
1069 cqe_compression_max_num);
1070
1071 resp.cqe_comp_caps.supported_format =
1072 MLX5_IB_CQE_RES_FORMAT_HASH |
1073 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1074
1075 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1076 resp.cqe_comp_caps.supported_format |=
1077 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1078 }
7e43a2a5
BW		 1079 }
1080
85c7c014
DJ		 1081 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1082 raw_support) {
d949167d
BW		 1083 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1084 MLX5_CAP_GEN(mdev, qos)) {
1085 resp.packet_pacing_caps.qp_rate_limit_max =
1086 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1087 resp.packet_pacing_caps.qp_rate_limit_min =
1088 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1089 resp.packet_pacing_caps.supported_qpts |=
1090 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1091 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1092 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1093 resp.packet_pacing_caps.cap_flags |=
1094 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1095 }
1096 resp.response_length += sizeof(resp.packet_pacing_caps);
1097 }
1098
9f885201
LR		 1099 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1100 uhw->outlen)) {
795b609c
BW		 1101 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1102 resp.mlx5_ib_support_multi_pkt_send_wqes =
1103 MLX5_IB_ALLOW_MPW;
050da902
BW		 1104
1105 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1106 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1107 MLX5_IB_SUPPORT_EMPW;
1108
9f885201
LR		 1109 resp.response_length +=
1110 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1111 }
1112
de57f2ad
GL		 1113 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1114 resp.response_length += sizeof(resp.flags);
7a0c8f42 1115
de57f2ad
GL		 1116 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1117 resp.flags |=
1118 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1119
1120 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1121 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1122 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1123 resp.flags |=
1124 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1125
1126 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1127 }
9f885201 1128
96dc3fc5
NO		 1129 if (field_avail(typeof(resp), sw_parsing_caps,
1130 uhw->outlen)) {
1131 resp.response_length += sizeof(resp.sw_parsing_caps);
1132 if (MLX5_CAP_ETH(mdev, swp)) {
1133 resp.sw_parsing_caps.sw_parsing_offloads |=
1134 MLX5_IB_SW_PARSING;
1135
1136 if (MLX5_CAP_ETH(mdev, swp_csum))
1137 resp.sw_parsing_caps.sw_parsing_offloads |=
1138 MLX5_IB_SW_PARSING_CSUM;
1139
1140 if (MLX5_CAP_ETH(mdev, swp_lso))
1141 resp.sw_parsing_caps.sw_parsing_offloads |=
1142 MLX5_IB_SW_PARSING_LSO;
1143
1144 if (resp.sw_parsing_caps.sw_parsing_offloads)
1145 resp.sw_parsing_caps.supported_qpts =
1146 BIT(IB_QPT_RAW_PACKET);
1147 }
1148 }
1149
85c7c014
DJ		 1150 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1151 raw_support) {
b4f34597
NO		 1152 resp.response_length += sizeof(resp.striding_rq_caps);
1153 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1154 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1155 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1156 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1157 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1158 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1159 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1160 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1161 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1162 resp.striding_rq_caps.supported_qpts =
1163 BIT(IB_QPT_RAW_PACKET);
1164 }
1165 }
1166
f95ef6cb
MG		 1167 if (field_avail(typeof(resp), tunnel_offloads_caps,
1168 uhw->outlen)) {
1169 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1170 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1171 resp.tunnel_offloads_caps |=
1172 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1173 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1174 resp.tunnel_offloads_caps |=
1175 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1176 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1177 resp.tunnel_offloads_caps |=
1178 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1179 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1180 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1181 resp.tunnel_offloads_caps |=
1182 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1183 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1184 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1185 resp.tunnel_offloads_caps |=
1186 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1187 }
1188
402ca536
BW		 1189 if (uhw->outlen) {
1190 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1191
1192 if (err)
1193 return err;
1194 }
1195
1b5daf11 1196 return 0;
e126ba97
EC		 1197}
1198
1b5daf11
MD		 1199enum mlx5_ib_width {
1200 MLX5_IB_WIDTH_1X = 1 << 0,
1201 MLX5_IB_WIDTH_2X = 1 << 1,
1202 MLX5_IB_WIDTH_4X = 1 << 2,
1203 MLX5_IB_WIDTH_8X = 1 << 3,
1204 MLX5_IB_WIDTH_12X = 1 << 4
1205};
1206
db7a691a 1207static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1208 u8 *ib_width)
e126ba97
EC		 1209{
1210 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1211
db7a691a 1212 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1213 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1214 else if (active_width & MLX5_IB_WIDTH_2X)
1215 *ib_width = IB_WIDTH_2X;
db7a691a 1216 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1217 *ib_width = IB_WIDTH_4X;
db7a691a 1218 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1219 *ib_width = IB_WIDTH_8X;
db7a691a 1220 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1221 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1222 else {
1223 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1224 (int)active_width);
db7a691a 1225 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1226 }
1227
db7a691a 1228 return;
1b5daf11 1229}
e126ba97 1230
1b5daf11
MD		 1231static int mlx5_mtu_to_ib_mtu(int mtu)
1232{
1233 switch (mtu) {
1234 case 256: return 1;
1235 case 512: return 2;
1236 case 1024: return 3;
1237 case 2048: return 4;
1238 case 4096: return 5;
1239 default:
1240 pr_warn("invalid mtu\n");
1241 return -1;
e126ba97 1242 }
1b5daf11 1243}
e126ba97 1244
1b5daf11
MD		 1245enum ib_max_vl_num {
1246 __IB_MAX_VL_0 = 1,
1247 __IB_MAX_VL_0_1 = 2,
1248 __IB_MAX_VL_0_3 = 3,
1249 __IB_MAX_VL_0_7 = 4,
1250 __IB_MAX_VL_0_14 = 5,
1251};
e126ba97 1252
1b5daf11
MD		 1253enum mlx5_vl_hw_cap {
1254 MLX5_VL_HW_0 = 1,
1255 MLX5_VL_HW_0_1 = 2,
1256 MLX5_VL_HW_0_2 = 3,
1257 MLX5_VL_HW_0_3 = 4,
1258 MLX5_VL_HW_0_4 = 5,
1259 MLX5_VL_HW_0_5 = 6,
1260 MLX5_VL_HW_0_6 = 7,
1261 MLX5_VL_HW_0_7 = 8,
1262 MLX5_VL_HW_0_14 = 15
1263};
e126ba97 1264
1b5daf11
MD		 1265static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1266 u8 *max_vl_num)
1267{
1268 switch (vl_hw_cap) {
1269 case MLX5_VL_HW_0:
1270 *max_vl_num = __IB_MAX_VL_0;
1271 break;
1272 case MLX5_VL_HW_0_1:
1273 *max_vl_num = __IB_MAX_VL_0_1;
1274 break;
1275 case MLX5_VL_HW_0_3:
1276 *max_vl_num = __IB_MAX_VL_0_3;
1277 break;
1278 case MLX5_VL_HW_0_7:
1279 *max_vl_num = __IB_MAX_VL_0_7;
1280 break;
1281 case MLX5_VL_HW_0_14:
1282 *max_vl_num = __IB_MAX_VL_0_14;
1283 break;
e126ba97 1284
1b5daf11
MD		 1285 default:
1286 return -EINVAL;
e126ba97 1287 }
e126ba97 1288
1b5daf11 1289 return 0;
e126ba97
EC		 1290}
1291
1b5daf11
MD		 1292static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1293 struct ib_port_attr *props)
e126ba97 1294{
1b5daf11
MD		 1295 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1296 struct mlx5_core_dev *mdev = dev->mdev;
1297 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1298 u16 max_mtu;
1299 u16 oper_mtu;
1b5daf11
MD		 1300 int err;
1301 u8 ib_link_width_oper;
1302 u8 vl_hw_cap;
e126ba97 1303
1b5daf11
MD		 1304 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1305 if (!rep) {
1306 err = -ENOMEM;
e126ba97 1307 goto out;
e126ba97 1308 }
e126ba97 1309
c4550c63 1310 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1311
1b5daf11 1312 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1313 if (err)
1314 goto out;
1315
1b5daf11
MD		 1316 props->lid = rep->lid;
1317 props->lmc = rep->lmc;
1318 props->sm_lid = rep->sm_lid;
1319 props->sm_sl = rep->sm_sl;
1320 props->state = rep->vport_state;
1321 props->phys_state = rep->port_physical_state;
1322 props->port_cap_flags = rep->cap_mask1;
1323 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1324 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1325 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1326 props->bad_pkey_cntr = rep->pkey_violation_counter;
1327 props->qkey_viol_cntr = rep->qkey_violation_counter;
1328 props->subnet_timeout = rep->subnet_timeout;
1329 props->init_type_reply = rep->init_type_reply;
e126ba97 1330
4106a758
MG		 1331 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1332 props->port_cap_flags2 = rep->cap_mask2;
1333
1b5daf11
MD		 1334 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1335 if (err)
e126ba97 1336 goto out;
e126ba97 1337
db7a691a
MG		 1338 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1339
d5beb7f2 1340 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1341 if (err)
1342 goto out;
1343
facc9699 1344 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1345
1b5daf11 1346 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1347
facc9699 1348 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1349
1b5daf11 1350 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1351
1b5daf11
MD		 1352 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1353 if (err)
1354 goto out;
e126ba97 1355
1b5daf11
MD		 1356 err = translate_max_vl_num(ibdev, vl_hw_cap,
1357 &props->max_vl_num);
e126ba97 1358out:
1b5daf11 1359 kfree(rep);
e126ba97
EC		 1360 return err;
1361}
1362
1b5daf11
MD		 1363int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1364 struct ib_port_attr *props)
e126ba97 1365{
095b0927
IT		 1366 unsigned int count;
1367 int ret;
1368
1b5daf11
MD		 1369 switch (mlx5_get_vport_access_method(ibdev)) {
1370 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1371 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1372 break;
e126ba97 1373
1b5daf11 1374 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1375 ret = mlx5_query_hca_port(ibdev, port, props);
1376 break;
e126ba97 1377
3f89a643 1378 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1379 ret = mlx5_query_port_roce(ibdev, port, props);
1380 break;
3f89a643 1381
1b5daf11 1382 default:
095b0927
IT		 1383 ret = -EINVAL;
1384 }
1385
1386 if (!ret && props) {
b3cbd6f0
DJ		 1387 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1388 struct mlx5_core_dev *mdev;
1389 bool put_mdev = true;
1390
1391 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1392 if (!mdev) {
1393 /* If the port isn't affiliated yet query the master.
1394 * The master and slave will have the same values.
1395 */
1396 mdev = dev->mdev;
1397 port = 1;
1398 put_mdev = false;
1399 }
1400 count = mlx5_core_reserved_gids_count(mdev);
1401 if (put_mdev)
1402 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1403 props->gid_tbl_len -= count;
1b5daf11 1404 }
095b0927 1405 return ret;
1b5daf11 1406}
e126ba97 1407
8e6efa3a
MB		 1408static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1409 struct ib_port_attr *props)
1410{
1411 int ret;
1412
26628e2d
MB		 1413 /* Only link layer == ethernet is valid for representors
1414 * and we always use port 1
1415 */
8e6efa3a
MB		 1416 ret = mlx5_query_port_roce(ibdev, port, props);
1417 if (ret || !props)
1418 return ret;
1419
1420 /* We don't support GIDS */
1421 props->gid_tbl_len = 0;
1422
1423 return ret;
1424}
1425
1b5daf11
MD		 1426static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1427 union ib_gid *gid)
1428{
1429 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1430 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1431
1b5daf11
MD		 1432 switch (mlx5_get_vport_access_method(ibdev)) {
1433 case MLX5_VPORT_ACCESS_METHOD_MAD:
1434 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1435
1b5daf11
MD		 1436 case MLX5_VPORT_ACCESS_METHOD_HCA:
1437 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1438
1439 default:
1440 return -EINVAL;
1441 }
e126ba97 1442
e126ba97
EC		 1443}
1444
b3cbd6f0
DJ		 1445static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1446 u16 index, u16 *pkey)
1b5daf11
MD		 1447{
1448 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1449 struct mlx5_core_dev *mdev;
1450 bool put_mdev = true;
1451 u8 mdev_port_num;
1452 int err;
1b5daf11 1453
b3cbd6f0
DJ		 1454 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1455 if (!mdev) {
1456 /* The port isn't affiliated yet, get the PKey from the master
1457 * port. For RoCE the PKey tables will be the same.
1458 */
1459 put_mdev = false;
1460 mdev = dev->mdev;
1461 mdev_port_num = 1;
1462 }
1463
1464 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1465 index, pkey);
1466 if (put_mdev)
1467 mlx5_ib_put_native_port_mdev(dev, port);
1468
1469 return err;
1470}
1471
1472static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1473 u16 *pkey)
1474{
1b5daf11
MD		 1475 switch (mlx5_get_vport_access_method(ibdev)) {
1476 case MLX5_VPORT_ACCESS_METHOD_MAD:
1477 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1478
1479 case MLX5_VPORT_ACCESS_METHOD_HCA:
1480 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1481 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1482 default:
1483 return -EINVAL;
1484 }
1485}
e126ba97
EC		 1486
1487static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1488 struct ib_device_modify *props)
1489{
1490 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1491 struct mlx5_reg_node_desc in;
1492 struct mlx5_reg_node_desc out;
1493 int err;
1494
1495 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1496 return -EOPNOTSUPP;
1497
1498 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1499 return 0;
1500
1501 /*
1502 * If possible, pass node desc to FW, so it can generate
1503 * a 144 trap. If cmd fails, just ignore.
1504 */
bd99fdea 1505 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1506 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1507 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1508 if (err)
1509 return err;
1510
bd99fdea 1511 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1512
1513 return err;
1514}
1515
cdbe33d0
EC		 1516static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1517 u32 value)
1518{
1519 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1520 struct mlx5_core_dev *mdev;
1521 u8 mdev_port_num;
cdbe33d0
EC		 1522 int err;
1523
b3cbd6f0
DJ		 1524 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1525 if (!mdev)
1526 return -ENODEV;
1527
1528 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1529 if (err)
b3cbd6f0 1530 goto out;
cdbe33d0
EC		 1531
1532 if (~ctx.cap_mask1_perm & mask) {
1533 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1534 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1535 err = -EINVAL;
1536 goto out;
cdbe33d0
EC		 1537 }
1538
1539 ctx.cap_mask1 = value;
1540 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1541 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1542 0, &ctx);
1543
1544out:
1545 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1546
1547 return err;
1548}
1549
e126ba97
EC		 1550static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1551 struct ib_port_modify *props)
1552{
1553 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1554 struct ib_port_attr attr;
1555 u32 tmp;
1556 int err;
cdbe33d0
EC		 1557 u32 change_mask;
1558 u32 value;
1559 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1560 IB_LINK_LAYER_INFINIBAND);
1561
ec255879
MD		 1562 /* CM layer calls ib_modify_port() regardless of the link layer. For
1563 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1564 */
1565 if (!is_ib)
1566 return 0;
1567
cdbe33d0
EC		 1568 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1569 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1570 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1571 return set_port_caps_atomic(dev, port, change_mask, value);
1572 }
e126ba97
EC		 1573
1574 mutex_lock(&dev->cap_mask_mutex);
1575
c4550c63 1576 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1577 if (err)
1578 goto out;
1579
1580 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1581 ~props->clr_port_cap_mask;
1582
9603b61d 1583 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1584
1585out:
1586 mutex_unlock(&dev->cap_mask_mutex);
1587 return err;
1588}
1589
30aa60b3
EC		 1590static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1591{
1592 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1593 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1594}
1595
31a78a5a
YH		 1596static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1597{
1598 /* Large page with non 4k uar support might limit the dynamic size */
1599 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1600 return MLX5_MIN_DYN_BFREGS;
1601
1602 return MLX5_MAX_DYN_BFREGS;
1603}
1604
b037c29a
EC		 1605static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1606 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1607 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1608{
1609 int uars_per_sys_page;
1610 int bfregs_per_sys_page;
1611 int ref_bfregs = req->total_num_bfregs;
1612
1613 if (req->total_num_bfregs == 0)
1614 return -EINVAL;
1615
1616 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1617 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1618
1619 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1620 return -ENOMEM;
1621
1622 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1623 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1624 /* This holds the required static allocation asked by the user */
b037c29a 1625 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1626 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1627 return -EINVAL;
1628
31a78a5a
YH		 1629 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1630 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1631 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1632 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1633
1634 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1635 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1636 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1637 req->total_num_bfregs, bfregi->total_num_bfregs,
1638 bfregi->num_sys_pages);
b037c29a
EC		 1639
1640 return 0;
1641}
1642
1643static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1644{
1645 struct mlx5_bfreg_info *bfregi;
1646 int err;
1647 int i;
1648
1649 bfregi = &context->bfregi;
31a78a5a 1650 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1651 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1652 if (err)
1653 goto error;
1654
1655 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1656 }
4ed131d0
YH		 1657
1658 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1659 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1660
b037c29a
EC		 1661 return 0;
1662
1663error:
1664 for (--i; i >= 0; i--)
1665 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1666 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1667
1668 return err;
1669}
1670
15177999
LR		 1671static void deallocate_uars(struct mlx5_ib_dev *dev,
1672 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1673{
1674 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1675 int i;
1676
1677 bfregi = &context->bfregi;
15177999 1678 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1679 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1680 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1681 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1682}
1683
0042f9e4 1684int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1685{
1686 int err = 0;
1687
1688 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1689 if (td)
1690 dev->lb.user_td++;
1691 if (qp)
1692 dev->lb.qps++;
1693
1694 if (dev->lb.user_td == 2 ||
1695 dev->lb.qps == 1) {
1696 if (!dev->lb.enabled) {
1697 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1698 dev->lb.enabled = true;
1699 }
1700 }
a560f1d9
MB		 1701
1702 mutex_unlock(&dev->lb.mutex);
1703
1704 return err;
1705}
1706
0042f9e4 1707void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1708{
1709 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1710 if (td)
1711 dev->lb.user_td--;
1712 if (qp)
1713 dev->lb.qps--;
1714
1715 if (dev->lb.user_td == 1 &&
1716 dev->lb.qps == 0) {
1717 if (dev->lb.enabled) {
1718 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1719 dev->lb.enabled = false;
1720 }
1721 }
a560f1d9
MB		 1722
1723 mutex_unlock(&dev->lb.mutex);
1724}
1725
d2d19121
YH		 1726static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1727 u16 uid)
c85023e1
HN		 1728{
1729 int err;
1730
cfdeb893
LR		 1731 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1732 return 0;
1733
d2d19121 1734 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1735 if (err)
1736 return err;
1737
1738 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1739 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1740 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1741 return err;
1742
0042f9e4 1743 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1744}
1745
d2d19121
YH		 1746static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1747 u16 uid)
c85023e1 1748{
cfdeb893
LR		 1749 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1750 return;
1751
d2d19121 1752 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1753
1754 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1755 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1756 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1757 return;
1758
0042f9e4 1759 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1760}
1761
a2a074ef
LR		 1762static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1763 struct ib_udata *udata)
e126ba97 1764{
a2a074ef 1765 struct ib_device *ibdev = uctx->device;
e126ba97 1766 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1767 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1768 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1769 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1770 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1771 struct mlx5_bfreg_info *bfregi;
78c0f98c 1772 int ver;
e126ba97 1773 int err;
a168a41c
MD		 1774 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1775 max_cqe_version);
25bb36e7 1776 u32 dump_fill_mkey;
b037c29a 1777 bool lib_uar_4k;
e126ba97
EC		 1778
1779 if (!dev->ib_active)
a2a074ef 1780 return -EAGAIN;
e126ba97 1781
e093111d 1782 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1783 ver = 0;
e093111d 1784 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1785 ver = 2;
1786 else
a2a074ef 1787 return -EINVAL;
78c0f98c 1788
e093111d 1789 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1790 if (err)
a2a074ef 1791 return err;
e126ba97 1792
a8b92ca1 1793 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1794 return -EOPNOTSUPP;
78c0f98c 1795
f72300c5 1796 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1797 return -EOPNOTSUPP;
b368d7cb 1798
2f5ff264
EC		 1799 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1800 MLX5_NON_FP_BFREGS_PER_UAR);
1801 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1802 return -EINVAL;
e126ba97 1803
938fe83c 1804 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1805 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1806 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1807 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1808 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1809 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1810 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1811 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1812 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1813 resp.cqe_version = min_t(__u8,
1814 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1815 req.max_cqe_version);
30aa60b3
EC		 1816 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1817 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1818 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1819 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1820 resp.response_length = min(offsetof(typeof(resp), response_length) +
1821 sizeof(resp.response_length), udata->outlen);
e126ba97 1822
c03faa56
MB		 1823 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1824 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1825 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1826 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1827 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1828 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1829 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1830 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1831 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1832 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1833 }
1834
30aa60b3 1835 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1836 bfregi = &context->bfregi;
b037c29a
EC		 1837
1838 /* updates req->total_num_bfregs */
31a78a5a 1839 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1840 if (err)
e126ba97 1841 goto out_ctx;
e126ba97 1842
b037c29a
EC		 1843 mutex_init(&bfregi->lock);
1844 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1845 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1846 GFP_KERNEL);
b037c29a 1847 if (!bfregi->count) {
e126ba97 1848 err = -ENOMEM;
b037c29a 1849 goto out_ctx;
e126ba97
EC		 1850 }
1851
b037c29a
EC		 1852 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1853 sizeof(*bfregi->sys_pages),
1854 GFP_KERNEL);
1855 if (!bfregi->sys_pages) {
e126ba97 1856 err = -ENOMEM;
b037c29a 1857 goto out_count;
e126ba97
EC		 1858 }
1859
b037c29a
EC		 1860 err = allocate_uars(dev, context);
1861 if (err)
1862 goto out_sys_pages;
e126ba97 1863
13859d5d
LR		 1864 if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1865 context->ibucontext.invalidate_range =
1866 &mlx5_ib_invalidate_range;
b4cfe447 1867
a8b92ca1 1868 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1869 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1870 if (err < 0)
d2d19121 1871 goto out_uars;
76dc5a84 1872 context->devx_uid = err;
a8b92ca1
YH		 1873 }
1874
d2d19121
YH		 1875 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1876 context->devx_uid);
1877 if (err)
1878 goto out_devx;
1879
25bb36e7
YC		 1880 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1881 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1882 if (err)
8193abb6 1883 goto out_mdev;
25bb36e7
YC		 1884 }
1885
e126ba97
EC		 1886 INIT_LIST_HEAD(&context->db_page_list);
1887 mutex_init(&context->db_page_mutex);
1888
2f5ff264 1889 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1890 resp.num_ports = dev->num_ports;
b368d7cb 1891
f72300c5
HA		 1892 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1893 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1894
402ca536 1895 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1896 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1897 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1898 resp.response_length += sizeof(resp.cmds_supp_uhw);
1899 }
1900
78984898
OG		 1901 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1902 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1903 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1904 resp.eth_min_inline++;
1905 }
1906 resp.response_length += sizeof(resp.eth_min_inline);
1907 }
1908
5c99eaec
FD		 1909 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1910 if (mdev->clock_info)
1911 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1912 resp.response_length += sizeof(resp.clock_info_versions);
1913 }
1914
bc5c6eed
NO		 1915 /*
1916 * We don't want to expose information from the PCI bar that is located
1917 * after 4096 bytes, so if the arch only supports larger pages, let's
1918 * pretend we don't support reading the HCA's core clock. This is also
1919 * forced by mmap function.
1920 */
de8d6e02
EC		 1921 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1922 if (PAGE_SIZE <= 4096) {
1923 resp.comp_mask |=
1924 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1925 resp.hca_core_clock_offset =
1926 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1927 }
5c99eaec 1928 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1929 }
1930
30aa60b3
EC		 1931 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1932 resp.response_length += sizeof(resp.log_uar_size);
1933
1934 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1935 resp.response_length += sizeof(resp.num_uars_per_page);
1936
31a78a5a
YH		 1937 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1938 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1939 resp.response_length += sizeof(resp.num_dyn_bfregs);
1940 }
1941
25bb36e7
YC		 1942 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1943 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1944 resp.dump_fill_mkey = dump_fill_mkey;
1945 resp.comp_mask |=
1946 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1947 }
1948 resp.response_length += sizeof(resp.dump_fill_mkey);
1949 }
1950
b368d7cb 1951 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1952 if (err)
a8b92ca1 1953 goto out_mdev;
e126ba97 1954
2f5ff264
EC		 1955 bfregi->ver = ver;
1956 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1957 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1958 context->lib_caps = req.lib_caps;
1959 print_lib_caps(dev, context->lib_caps);
f72300c5 1960
7c34ec19 1961 if (dev->lag_active) {
95579e78 1962 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1963
1964 atomic_set(&context->tx_port_affinity,
1965 atomic_add_return(
95579e78 1966 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1967 }
1968
a2a074ef 1969 return 0;
e126ba97 1970
a8b92ca1 1971out_mdev:
d2d19121
YH		 1972 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1973out_devx:
a8b92ca1 1974 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1975 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1976
e126ba97 1977out_uars:
b037c29a 1978 deallocate_uars(dev, context);
e126ba97 1979
b037c29a
EC		 1980out_sys_pages:
1981 kfree(bfregi->sys_pages);
e126ba97 1982
b037c29a
EC		 1983out_count:
1984 kfree(bfregi->count);
e126ba97
EC		 1985
1986out_ctx:
a2a074ef 1987 return err;
e126ba97
EC		 1988}
1989
a2a074ef 1990static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 1991{
1992 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1993 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1994 struct mlx5_bfreg_info *bfregi;
e126ba97 1995
f27a0d50
JG		 1996 /* All umem's must be destroyed before destroying the ucontext. */
1997 mutex_lock(&ibcontext->per_mm_list_lock);
1998 WARN_ON(!list_empty(&ibcontext->per_mm_list));
1999 mutex_unlock(&ibcontext->per_mm_list_lock);
a8b92ca1 2000
b037c29a 2001 bfregi = &context->bfregi;
d2d19121
YH		 2002 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2003
a8b92ca1 2004 if (context->devx_uid)
76dc5a84 2005 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2006
b037c29a
EC		 2007 deallocate_uars(dev, context);
2008 kfree(bfregi->sys_pages);
2f5ff264 2009 kfree(bfregi->count);
e126ba97
EC		 2010}
2011
b037c29a 2012static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2013 int uar_idx)
e126ba97 2014{
b037c29a
EC		 2015 int fw_uars_per_page;
2016
2017 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2018
aa8106f1 2019 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2020}
2021
2022static int get_command(unsigned long offset)
2023{
2024 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2025}
2026
2027static int get_arg(unsigned long offset)
2028{
2029 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2030}
2031
2032static int get_index(unsigned long offset)
2033{
2034 return get_arg(offset);
2035}
2036
4ed131d0
YH		 2037/* Index resides in an extra byte to enable larger values than 255 */
2038static int get_extended_index(unsigned long offset)
2039{
2040 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2041}
2042
7c2344c3
MG		 2043
2044static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2045{
7c2344c3
MG		 2046}
2047
37aa5c36
GL		 2048static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2049{
2050 switch (cmd) {
2051 case MLX5_IB_MMAP_WC_PAGE:
2052 return "WC";
2053 case MLX5_IB_MMAP_REGULAR_PAGE:
2054 return "best effort WC";
2055 case MLX5_IB_MMAP_NC_PAGE:
2056 return "NC";
24da0016
AL		 2057 case MLX5_IB_MMAP_DEVICE_MEM:
2058 return "Device Memory";
37aa5c36
GL		 2059 default:
2060 return NULL;
2061 }
2062}
2063
5c99eaec
FD		 2064static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2065 struct vm_area_struct *vma,
2066 struct mlx5_ib_ucontext *context)
2067{
4eb6ab13
JG		 2068 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2069 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2070 return -EINVAL;
2071
2072 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2073 return -EOPNOTSUPP;
2074
4eb6ab13 2075 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2076 return -EPERM;
c660133c 2077 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2078
ddcdc368 2079 if (!dev->mdev->clock_info)
5c99eaec
FD		 2080 return -EOPNOTSUPP;
2081
4eb6ab13
JG		 2082 return vm_insert_page(vma, vma->vm_start,
2083 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2084}
2085
37aa5c36 2086static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2087 struct vm_area_struct *vma,
2088 struct mlx5_ib_ucontext *context)
37aa5c36 2089{
2f5ff264 2090 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2091 int err;
2092 unsigned long idx;
aa09ea6e 2093 phys_addr_t pfn;
37aa5c36 2094 pgprot_t prot;
4ed131d0
YH		 2095 u32 bfreg_dyn_idx = 0;
2096 u32 uar_index;
2097 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2098 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2099 bfregi->num_static_sys_pages;
b037c29a
EC		 2100
2101 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2102 return -EINVAL;
2103
4ed131d0
YH		 2104 if (dyn_uar)
2105 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2106 else
2107 idx = get_index(vma->vm_pgoff);
2108
2109 if (idx >= max_valid_idx) {
2110 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2111 idx, max_valid_idx);
b037c29a
EC		 2112 return -EINVAL;
2113 }
37aa5c36
GL		 2114
2115 switch (cmd) {
2116 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2117 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2118/* Some architectures don't support WC memory */
2119#if defined(CONFIG_X86)
2120 if (!pat_enabled())
2121 return -EPERM;
2122#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2123 return -EPERM;
2124#endif
2125 /* fall through */
2126 case MLX5_IB_MMAP_REGULAR_PAGE:
2127 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2128 prot = pgprot_writecombine(vma->vm_page_prot);
2129 break;
2130 case MLX5_IB_MMAP_NC_PAGE:
2131 prot = pgprot_noncached(vma->vm_page_prot);
2132 break;
2133 default:
2134 return -EINVAL;
2135 }
2136
4ed131d0
YH		 2137 if (dyn_uar) {
2138 int uars_per_page;
2139
2140 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2141 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2142 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2143 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2144 bfreg_dyn_idx, bfregi->total_num_bfregs);
2145 return -EINVAL;
2146 }
2147
2148 mutex_lock(&bfregi->lock);
2149 /* Fail if uar already allocated, first bfreg index of each
2150 * page holds its count.
2151 */
2152 if (bfregi->count[bfreg_dyn_idx]) {
2153 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2154 mutex_unlock(&bfregi->lock);
2155 return -EINVAL;
2156 }
2157
2158 bfregi->count[bfreg_dyn_idx]++;
2159 mutex_unlock(&bfregi->lock);
2160
2161 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2162 if (err) {
2163 mlx5_ib_warn(dev, "UAR alloc failed\n");
2164 goto free_bfreg;
2165 }
2166 } else {
2167 uar_index = bfregi->sys_pages[idx];
2168 }
2169
2170 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2171 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2172
e2cd1d1a
JG		 2173 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2174 prot);
37aa5c36 2175 if (err) {
8f062287 2176 mlx5_ib_err(dev,
e2cd1d1a 2177 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2178 err, mmap_cmd2str(cmd));
4ed131d0 2179 goto err;
37aa5c36
GL		 2180 }
2181
4ed131d0
YH		 2182 if (dyn_uar)
2183 bfregi->sys_pages[idx] = uar_index;
2184 return 0;
2185
2186err:
2187 if (!dyn_uar)
2188 return err;
2189
2190 mlx5_cmd_free_uar(dev->mdev, idx);
2191
2192free_bfreg:
2193 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2194
2195 return err;
37aa5c36
GL		 2196}
2197
24da0016
AL		 2198static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2199{
2200 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2201 struct mlx5_ib_dev *dev = to_mdev(context->device);
2202 u16 page_idx = get_extended_index(vma->vm_pgoff);
2203 size_t map_size = vma->vm_end - vma->vm_start;
2204 u32 npages = map_size >> PAGE_SHIFT;
2205 phys_addr_t pfn;
24da0016
AL		 2206
2207 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2208 page_idx + npages)
2209 return -EINVAL;
2210
aa8106f1 2211 pfn = ((dev->mdev->bar_addr +
24da0016
AL		 2212 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2213 PAGE_SHIFT) +
2214 page_idx;
e2cd1d1a
JG		 2215 return rdma_user_mmap_io(context, vma, pfn, map_size,
2216 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2217}
2218
e126ba97
EC		 2219static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2220{
2221 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2222 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2223 unsigned long command;
e126ba97
EC		 2224 phys_addr_t pfn;
2225
2226 command = get_command(vma->vm_pgoff);
2227 switch (command) {
37aa5c36
GL		 2228 case MLX5_IB_MMAP_WC_PAGE:
2229 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2230 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2231 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2232 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2233
2234 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2235 return -ENOSYS;
2236
d69e3bcf 2237 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2238 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2239 return -EINVAL;
2240
6cbac1e4 2241 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2242 return -EPERM;
c660133c 2243 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2244
2245 /* Don't expose to user-space information it shouldn't have */
2246 if (PAGE_SIZE > 4096)
2247 return -EOPNOTSUPP;
2248
d69e3bcf
MB		 2249 pfn = (dev->mdev->iseg_base +
2250 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2251 PAGE_SHIFT;
d5e560d3
JG		 2252 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2253 PAGE_SIZE,
2254 pgprot_noncached(vma->vm_page_prot));
5c99eaec
FD		 2255 case MLX5_IB_MMAP_CLOCK_INFO:
2256 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2257
24da0016
AL		 2258 case MLX5_IB_MMAP_DEVICE_MEM:
2259 return dm_mmap(ibcontext, vma);
2260
e126ba97
EC		 2261 default:
2262 return -EINVAL;
2263 }
2264
2265 return 0;
2266}
2267
25c13324
AL		 2268static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2269 u32 type)
24da0016 2270{
25c13324
AL		 2271 switch (type) {
2272 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2273 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2274 return -EOPNOTSUPP;
2275 break;
2276 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2277 if (!capable(CAP_SYS_RAWIO) ||
2278 !capable(CAP_NET_RAW))
2279 return -EPERM;
2280
2281 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2282 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2283 return -EOPNOTSUPP;
2284 break;
2285 }
2286
2287 return 0;
2288}
2289
3b113a1e
AL		 2290static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2291 struct mlx5_ib_dm *dm,
2292 struct ib_dm_alloc_attr *attr,
2293 struct uverbs_attr_bundle *attrs)
24da0016 2294{
3b113a1e 2295 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016
AL		 2296 u64 start_offset;
2297 u32 page_idx;
2298 int err;
2299
3b113a1e 2300 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2301
3b113a1e
AL		 2302 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2303 dm->size, attr->alignment);
24da0016 2304 if (err)
3b113a1e 2305 return err;
24da0016 2306
3b113a1e
AL		 2307 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2308 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
24da0016
AL		 2309 PAGE_SHIFT;
2310
2311 err = uverbs_copy_to(attrs,
3b113a1e
AL		 2312 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2313 &page_idx, sizeof(page_idx));
24da0016
AL		 2314 if (err)
2315 goto err_dealloc;
2316
3b113a1e 2317 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2318 err = uverbs_copy_to(attrs,
2319 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2320 &start_offset, sizeof(start_offset));
2321 if (err)
2322 goto err_dealloc;
2323
3b113a1e
AL		 2324 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2325 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2326
2327 return 0;
2328
2329err_dealloc:
2330 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2331
2332 return err;
2333}
2334
25c13324
AL		 2335static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2336 struct mlx5_ib_dm *dm,
2337 struct ib_dm_alloc_attr *attr,
2338 struct uverbs_attr_bundle *attrs,
2339 int type)
2340{
2341 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2342 u64 act_size;
2343 int err;
2344
2345 /* Allocation size must a multiple of the basic block size
2346 * and a power of 2.
2347 */
2348 act_size = roundup(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dm_db->dev));
2349 act_size = roundup_pow_of_two(act_size);
2350
2351 dm->size = act_size;
2352 err = mlx5_cmd_alloc_sw_icm(dm_db, type, act_size,
2353 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2354 &dm->icm_dm.obj_id);
2355 if (err)
2356 return err;
2357
24da0016 2358 err = uverbs_copy_to(attrs,
25c13324
AL		 2359 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2360 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2361 if (err)
25c13324
AL		 2362 mlx5_cmd_dealloc_sw_icm(dm_db, type, dm->size,
2363 to_mucontext(ctx)->devx_uid,
2364 dm->dev_addr, dm->icm_dm.obj_id);
2365
2366 return err;
2367}
2368
3b113a1e
AL		 2369struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2370 struct ib_ucontext *context,
2371 struct ib_dm_alloc_attr *attr,
2372 struct uverbs_attr_bundle *attrs)
2373{
2374 struct mlx5_ib_dm *dm;
2375 enum mlx5_ib_uapi_dm_type type;
2376 int err;
24da0016 2377
3b113a1e
AL		 2378 err = uverbs_get_const_default(&type, attrs,
2379 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2380 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2381 if (err)
2382 return ERR_PTR(err);
24da0016 2383
3b113a1e
AL		 2384 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2385 type, attr->length, attr->alignment);
2386
25c13324
AL		 2387 err = check_dm_type_support(to_mdev(ibdev), type);
2388 if (err)
2389 return ERR_PTR(err);
2390
3b113a1e
AL		 2391 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2392 if (!dm)
2393 return ERR_PTR(-ENOMEM);
2394
2395 dm->type = type;
2396
2397 switch (type) {
2398 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2399 err = handle_alloc_dm_memic(context, dm,
2400 attr,
2401 attrs);
2402 break;
25c13324
AL		 2403 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2404 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2405 err = handle_alloc_dm_sw_icm(context, dm, attr, attrs, type);
2406 break;
3b113a1e
AL		 2407 default:
2408 err = -EOPNOTSUPP;
2409 }
24da0016 2410
3b113a1e
AL		 2411 if (err)
2412 goto err_free;
24da0016
AL		 2413
2414 return &dm->ibdm;
2415
24da0016
AL		 2416err_free:
2417 kfree(dm);
2418 return ERR_PTR(err);
2419}
2420
c4367a26 2421int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2422{
25c13324
AL		 2423 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2424 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
3b113a1e 2425 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
24da0016 2426 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2427 u32 page_idx;
2428 int ret;
2429
3b113a1e
AL		 2430 switch (dm->type) {
2431 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2432 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2433 if (ret)
2434 return ret;
24da0016 2435
3b113a1e
AL		 2436 page_idx = (dm->dev_addr -
2437 pci_resource_start(dm_db->dev->pdev, 0) -
2438 MLX5_CAP64_DEV_MEM(dm_db->dev,
2439 memic_bar_start_addr)) >>
2440 PAGE_SHIFT;
25c13324
AL		 2441 bitmap_clear(ctx->dm_pages, page_idx,
2442 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2443 break;
2444 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2445 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2446 ret = mlx5_cmd_dealloc_sw_icm(dm_db, dm->type, dm->size,
2447 ctx->devx_uid, dm->dev_addr,
2448 dm->icm_dm.obj_id);
2449 if (ret)
2450 return ret;
3b113a1e
AL		 2451 break;
2452 default:
2453 return -EOPNOTSUPP;
2454 }
24da0016
AL		 2455
2456 kfree(dm);
2457
2458 return 0;
2459}
2460
ff23dfa1 2461static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2462{
21a428a0
LR		 2463 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2464 struct ib_device *ibdev = ibpd->device;
e126ba97 2465 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2466 int err;
a1069c1c
YH		 2467 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2468 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2469 u16 uid = 0;
ff23dfa1
SR		 2470 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2471 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2472
ff23dfa1 2473 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2474 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2475 MLX5_SET(alloc_pd_in, in, uid, uid);
2476 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2477 out, sizeof(out));
21a428a0
LR		 2478 if (err)
2479 return err;
e126ba97 2480
a1069c1c
YH		 2481 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2482 pd->uid = uid;
ff23dfa1 2483 if (udata) {
e126ba97
EC		 2484 resp.pdn = pd->pdn;
2485 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2486 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2487 return -EFAULT;
e126ba97 2488 }
e126ba97
EC		 2489 }
2490
21a428a0 2491 return 0;
e126ba97
EC		 2492}
2493
c4367a26 2494static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2495{
2496 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2497 struct mlx5_ib_pd *mpd = to_mpd(pd);
2498
a1069c1c 2499 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2500}
2501
466fa6d2
MG		 2502enum {
2503 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2504 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2505 MATCH_CRITERIA_ENABLE_INNER_BIT,
2506 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2507};
2508
2509#define HEADER_IS_ZERO(match_criteria, headers) \
2510 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2511 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2512
466fa6d2 2513static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2514{
466fa6d2 2515 u8 match_criteria_enable;
038d2ef8 2516
466fa6d2
MG		 2517 match_criteria_enable =
2518 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2519 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2520 match_criteria_enable |=
2521 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2522 MATCH_CRITERIA_ENABLE_MISC_BIT;
2523 match_criteria_enable |=
2524 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2525 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2526 match_criteria_enable |=
2527 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2528 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2529
2530 return match_criteria_enable;
038d2ef8
MG		 2531}
2532
6113cc44 2533static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2534{
6113cc44
MG		 2535 u8 entry_mask;
2536 u8 entry_val;
2537 int err = 0;
2538
2539 if (!mask)
2540 goto out;
2541
2542 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2543 ip_protocol);
2544 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2545 ip_protocol);
2546 if (!entry_mask) {
2547 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2548 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2549 goto out;
2550 }
2551 /* Don't override existing ip protocol */
2552 if (mask != entry_mask || val != entry_val)
2553 err = -EINVAL;
2554out:
2555 return err;
038d2ef8
MG		 2556}
2557
37da2a03 2558static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2559 bool inner)
2560{
2561 if (inner) {
2562 MLX5_SET(fte_match_set_misc,
2563 misc_c, inner_ipv6_flow_label, mask);
2564 MLX5_SET(fte_match_set_misc,
2565 misc_v, inner_ipv6_flow_label, val);
2566 } else {
2567 MLX5_SET(fte_match_set_misc,
2568 misc_c, outer_ipv6_flow_label, mask);
2569 MLX5_SET(fte_match_set_misc,
2570 misc_v, outer_ipv6_flow_label, val);
2571 }
2572}
2573
ca0d4753
MG		 2574static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2575{
2576 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2577 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2578 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2579 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2580}
2581
71c6e863
AL		 2582static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2583{
2584 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2585 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2586 return -EOPNOTSUPP;
2587
2588 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2589 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2590 return -EOPNOTSUPP;
2591
2592 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2593 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2594 return -EOPNOTSUPP;
2595
2596 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2597 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2598 return -EOPNOTSUPP;
2599
2600 return 0;
2601}
2602
c47ac6ae
MG		 2603#define LAST_ETH_FIELD vlan_tag
2604#define LAST_IB_FIELD sl
ca0d4753 2605#define LAST_IPV4_FIELD tos
466fa6d2 2606#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2607#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2608#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2609#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2610#define LAST_DROP_FIELD size
3b3233fb 2611#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2612
2613/* Field is the last supported field */
2614#define FIELDS_NOT_SUPPORTED(filter, field)\
2615 memchr_inv((void *)&filter.field +\
2616 sizeof(filter.field), 0,\
2617 sizeof(filter) -\
2618 offsetof(typeof(filter), field) -\
2619 sizeof(filter.field))
2620
2ea26203
MB		 2621int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2622 bool is_egress,
2623 struct mlx5_flow_act *action)
802c2125 2624{
802c2125
AY		 2625
2626 switch (maction->ib_action.type) {
2627 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2628 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2629 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2630 return -EINVAL;
802c2125
AY		 2631 /* Currently only AES_GCM keymat is supported by the driver */
2632 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2633 action->action |= is_egress ?
802c2125
AY		 2634 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2635 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2636 return 0;
b1085be3
MB		 2637 case IB_FLOW_ACTION_UNSPECIFIED:
2638 if (maction->flow_action_raw.sub_type ==
2639 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2640 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2641 return -EINVAL;
b1085be3
MB		 2642 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2643 action->modify_id = maction->flow_action_raw.action_id;
2644 return 0;
2645 }
10a30896
MB		 2646 if (maction->flow_action_raw.sub_type ==
2647 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2648 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2649 return -EINVAL;
10a30896
MB		 2650 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2651 return 0;
2652 }
e806f932
MB		 2653 if (maction->flow_action_raw.sub_type ==
2654 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2655 if (action->action &
2656 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2657 return -EINVAL;
e806f932
MB		 2658 action->action |=
2659 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2660 action->reformat_id =
2661 maction->flow_action_raw.action_id;
2662 return 0;
2663 }
b1085be3 2664 /* fall through */
802c2125
AY		 2665 default:
2666 return -EOPNOTSUPP;
2667 }
2668}
2669
19cc7524
AL		 2670static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2671 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2672 const struct ib_flow_attr *flow_attr,
71c6e863 2673 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2674{
466fa6d2
MG		 2675 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2676 misc_parameters);
2677 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2678 misc_parameters);
71c6e863
AL		 2679 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2680 misc_parameters_2);
2681 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2682 misc_parameters_2);
2d1e697e
MR		 2683 void *headers_c;
2684 void *headers_v;
19cc7524 2685 int match_ipv;
802c2125 2686 int ret;
2d1e697e
MR		 2687
2688 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2689 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2690 inner_headers);
2691 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2692 inner_headers);
19cc7524
AL		 2693 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2694 ft_field_support.inner_ip_version);
2d1e697e
MR		 2695 } else {
2696 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2697 outer_headers);
2698 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2699 outer_headers);
19cc7524
AL		 2700 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2701 ft_field_support.outer_ip_version);
2d1e697e 2702 }
466fa6d2 2703
2d1e697e 2704 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2705 case IB_FLOW_SPEC_ETH:
c47ac6ae 2706 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2707 return -EOPNOTSUPP;
038d2ef8 2708
2d1e697e 2709 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2710 dmac_47_16),
2711 ib_spec->eth.mask.dst_mac);
2d1e697e 2712 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2713 dmac_47_16),
2714 ib_spec->eth.val.dst_mac);
2715
2d1e697e 2716 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2717 smac_47_16),
2718 ib_spec->eth.mask.src_mac);
2d1e697e 2719 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2720 smac_47_16),
2721 ib_spec->eth.val.src_mac);
2722
038d2ef8 2723 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2724 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2725 cvlan_tag, 1);
2d1e697e 2726 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2727 cvlan_tag, 1);
038d2ef8 2728
2d1e697e 2729 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2730 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2731 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2732 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2733
2d1e697e 2734 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2735 first_cfi,
2736 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2737 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2738 first_cfi,
2739 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2740
2d1e697e 2741 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2742 first_prio,
2743 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2744 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2745 first_prio,
2746 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2747 }
2d1e697e 2748 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2749 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2750 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2751 ethertype, ntohs(ib_spec->eth.val.ether_type));
2752 break;
2753 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2754 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2755 return -EOPNOTSUPP;
038d2ef8 2756
19cc7524
AL		 2757 if (match_ipv) {
2758 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2759 ip_version, 0xf);
2760 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2761 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2762 } else {
2763 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2764 ethertype, 0xffff);
2765 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2766 ethertype, ETH_P_IP);
2767 }
038d2ef8 2768
2d1e697e 2769 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2770 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2771 &ib_spec->ipv4.mask.src_ip,
2772 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2773 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2774 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2775 &ib_spec->ipv4.val.src_ip,
2776 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2777 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2778 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2779 &ib_spec->ipv4.mask.dst_ip,
2780 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2781 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2782 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2783 &ib_spec->ipv4.val.dst_ip,
2784 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2785
2d1e697e 2786 set_tos(headers_c, headers_v,
ca0d4753
MG		 2787 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2788
6113cc44
MG		 2789 if (set_proto(headers_c, headers_v,
2790 ib_spec->ipv4.mask.proto,
2791 ib_spec->ipv4.val.proto))
2792 return -EINVAL;
038d2ef8 2793 break;
026bae0c 2794 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2795 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2796 return -EOPNOTSUPP;
026bae0c 2797
19cc7524
AL		 2798 if (match_ipv) {
2799 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2800 ip_version, 0xf);
2801 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2802 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2803 } else {
2804 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2805 ethertype, 0xffff);
2806 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2807 ethertype, ETH_P_IPV6);
2808 }
026bae0c 2809
2d1e697e 2810 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2811 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2812 &ib_spec->ipv6.mask.src_ip,
2813 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2814 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2815 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2816 &ib_spec->ipv6.val.src_ip,
2817 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2818 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2819 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2820 &ib_spec->ipv6.mask.dst_ip,
2821 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2822 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2823 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2824 &ib_spec->ipv6.val.dst_ip,
2825 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2826
2d1e697e 2827 set_tos(headers_c, headers_v,
466fa6d2
MG		 2828 ib_spec->ipv6.mask.traffic_class,
2829 ib_spec->ipv6.val.traffic_class);
2830
6113cc44
MG		 2831 if (set_proto(headers_c, headers_v,
2832 ib_spec->ipv6.mask.next_hdr,
2833 ib_spec->ipv6.val.next_hdr))
2834 return -EINVAL;
466fa6d2 2835
2d1e697e
MR		 2836 set_flow_label(misc_params_c, misc_params_v,
2837 ntohl(ib_spec->ipv6.mask.flow_label),
2838 ntohl(ib_spec->ipv6.val.flow_label),
2839 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2840 break;
2841 case IB_FLOW_SPEC_ESP:
2842 if (ib_spec->esp.mask.seq)
2843 return -EOPNOTSUPP;
2d1e697e 2844
802c2125
AY		 2845 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2846 ntohl(ib_spec->esp.mask.spi));
2847 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2848 ntohl(ib_spec->esp.val.spi));
026bae0c 2849 break;
038d2ef8 2850 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2851 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2852 LAST_TCP_UDP_FIELD))
1ffd3a26 2853 return -EOPNOTSUPP;
038d2ef8 2854
6113cc44
MG		 2855 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2856 return -EINVAL;
038d2ef8 2857
2d1e697e 2858 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2859 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2860 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2861 ntohs(ib_spec->tcp_udp.val.src_port));
2862
2d1e697e 2863 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2864 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2865 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2866 ntohs(ib_spec->tcp_udp.val.dst_port));
2867 break;
2868 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2869 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2870 LAST_TCP_UDP_FIELD))
1ffd3a26 2871 return -EOPNOTSUPP;
038d2ef8 2872
6113cc44
MG		 2873 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2874 return -EINVAL;
038d2ef8 2875
2d1e697e 2876 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2877 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2878 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2879 ntohs(ib_spec->tcp_udp.val.src_port));
2880
2d1e697e 2881 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2882 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2883 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2884 ntohs(ib_spec->tcp_udp.val.dst_port));
2885 break;
da2f22ae
AL		 2886 case IB_FLOW_SPEC_GRE:
2887 if (ib_spec->gre.mask.c_ks_res0_ver)
2888 return -EOPNOTSUPP;
2889
6113cc44
MG		 2890 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2891 return -EINVAL;
2892
da2f22ae
AL		 2893 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2894 0xff);
2895 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2896 IPPROTO_GRE);
2897
2898 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2899 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2900 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2901 ntohs(ib_spec->gre.val.protocol));
2902
2903 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2904 gre_key.nvgre.hi),
da2f22ae
AL		 2905 &ib_spec->gre.mask.key,
2906 sizeof(ib_spec->gre.mask.key));
2907 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2908 gre_key.nvgre.hi),
da2f22ae
AL		 2909 &ib_spec->gre.val.key,
2910 sizeof(ib_spec->gre.val.key));
2911 break;
71c6e863
AL		 2912 case IB_FLOW_SPEC_MPLS:
2913 switch (prev_type) {
2914 case IB_FLOW_SPEC_UDP:
2915 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2916 ft_field_support.outer_first_mpls_over_udp),
2917 &ib_spec->mpls.mask.tag))
2918 return -EOPNOTSUPP;
2919
2920 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2921 outer_first_mpls_over_udp),
2922 &ib_spec->mpls.val.tag,
2923 sizeof(ib_spec->mpls.val.tag));
2924 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2925 outer_first_mpls_over_udp),
2926 &ib_spec->mpls.mask.tag,
2927 sizeof(ib_spec->mpls.mask.tag));
2928 break;
2929 case IB_FLOW_SPEC_GRE:
2930 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2931 ft_field_support.outer_first_mpls_over_gre),
2932 &ib_spec->mpls.mask.tag))
2933 return -EOPNOTSUPP;
2934
2935 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2936 outer_first_mpls_over_gre),
2937 &ib_spec->mpls.val.tag,
2938 sizeof(ib_spec->mpls.val.tag));
2939 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2940 outer_first_mpls_over_gre),
2941 &ib_spec->mpls.mask.tag,
2942 sizeof(ib_spec->mpls.mask.tag));
2943 break;
2944 default:
2945 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2946 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2947 ft_field_support.inner_first_mpls),
2948 &ib_spec->mpls.mask.tag))
2949 return -EOPNOTSUPP;
2950
2951 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2952 inner_first_mpls),
2953 &ib_spec->mpls.val.tag,
2954 sizeof(ib_spec->mpls.val.tag));
2955 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2956 inner_first_mpls),
2957 &ib_spec->mpls.mask.tag,
2958 sizeof(ib_spec->mpls.mask.tag));
2959 } else {
2960 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2961 ft_field_support.outer_first_mpls),
2962 &ib_spec->mpls.mask.tag))
2963 return -EOPNOTSUPP;
2964
2965 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2966 outer_first_mpls),
2967 &ib_spec->mpls.val.tag,
2968 sizeof(ib_spec->mpls.val.tag));
2969 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2970 outer_first_mpls),
2971 &ib_spec->mpls.mask.tag,
2972 sizeof(ib_spec->mpls.mask.tag));
2973 }
2974 }
2975 break;
ffb30d8f
MR		 2976 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2977 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2978 LAST_TUNNEL_FIELD))
1ffd3a26 2979 return -EOPNOTSUPP;
ffb30d8f
MR		 2980
2981 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2982 ntohl(ib_spec->tunnel.mask.tunnel_id));
2983 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2984 ntohl(ib_spec->tunnel.val.tunnel_id));
2985 break;
2ac693f9
MR		 2986 case IB_FLOW_SPEC_ACTION_TAG:
2987 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2988 LAST_FLOW_TAG_FIELD))
2989 return -EOPNOTSUPP;
2990 if (ib_spec->flow_tag.tag_id >= BIT(24))
2991 return -EINVAL;
2992
075572d4 2993 action->flow_tag = ib_spec->flow_tag.tag_id;
d5634fee 2994 action->flags |= FLOW_ACT_HAS_TAG;
2ac693f9 2995 break;
a22ed86c
SS		 2996 case IB_FLOW_SPEC_ACTION_DROP:
2997 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2998 LAST_DROP_FIELD))
2999 return -EOPNOTSUPP;
075572d4 3000 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3001 break;
802c2125 3002 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3003 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3004 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3005 if (ret)
3006 return ret;
3007 break;
3b3233fb
RS		 3008 case IB_FLOW_SPEC_ACTION_COUNT:
3009 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3010 LAST_COUNTERS_FIELD))
3011 return -EOPNOTSUPP;
3012
3013 /* for now support only one counters spec per flow */
3014 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3015 return -EINVAL;
3016
3017 action->counters = ib_spec->flow_count.counters;
3018 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3019 break;
038d2ef8
MG		 3020 default:
3021 return -EINVAL;
3022 }
3023
3024 return 0;
3025}
3026
3027/* If a flow could catch both multicast and unicast packets,
3028 * it won't fall into the multicast flow steering table and this rule
3029 * could steal other multicast packets.
3030 */
a550ddfc 3031static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3032{
81e30880 3033 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3034
3035 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3036 ib_attr->num_of_specs < 1)
3037 return false;
3038
81e30880
YH		 3039 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3040 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3041 struct ib_flow_spec_ipv4 *ipv4_spec;
3042
3043 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3044 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3045 return true;
3046
038d2ef8 3047 return false;
81e30880
YH		 3048 }
3049
3050 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3051 struct ib_flow_spec_eth *eth_spec;
3052
3053 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3054 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3055 is_multicast_ether_addr(eth_spec->val.dst_mac);
3056 }
038d2ef8 3057
81e30880 3058 return false;
038d2ef8
MG		 3059}
3060
802c2125
AY		 3061enum valid_spec {
3062 VALID_SPEC_INVALID,
3063 VALID_SPEC_VALID,
3064 VALID_SPEC_NA,
3065};
3066
3067static enum valid_spec
3068is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3069 const struct mlx5_flow_spec *spec,
3070 const struct mlx5_flow_act *flow_act,
3071 bool egress)
3072{
3073 const u32 *match_c = spec->match_criteria;
3074 bool is_crypto =
3075 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3076 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3077 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3078 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3079
3080 /*
3081 * Currently only crypto is supported in egress, when regular egress
3082 * rules would be supported, always return VALID_SPEC_NA.
3083 */
3084 if (!is_crypto)
78dd0c43 3085 return VALID_SPEC_NA;
802c2125
AY		 3086
3087 return is_crypto && is_ipsec &&
d5634fee 3088 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
802c2125
AY		 3089 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3090}
3091
3092static bool is_valid_spec(struct mlx5_core_dev *mdev,
3093 const struct mlx5_flow_spec *spec,
3094 const struct mlx5_flow_act *flow_act,
3095 bool egress)
3096{
3097 /* We curretly only support ipsec egress flow */
3098 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3099}
3100
19cc7524
AL		 3101static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3102 const struct ib_flow_attr *flow_attr,
0f750966 3103 bool check_inner)
038d2ef8
MG		 3104{
3105 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3106 int match_ipv = check_inner ?
3107 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3108 ft_field_support.inner_ip_version) :
3109 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3110 ft_field_support.outer_ip_version);
0f750966
AL		 3111 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3112 bool ipv4_spec_valid, ipv6_spec_valid;
3113 unsigned int ip_spec_type = 0;
3114 bool has_ethertype = false;
038d2ef8 3115 unsigned int spec_index;
0f750966
AL		 3116 bool mask_valid = true;
3117 u16 eth_type = 0;
3118 bool type_valid;
038d2ef8
MG		 3119
3120 /* Validate that ethertype is correct */
3121 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3122 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3123 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3124 mask_valid = (ib_spec->eth.mask.ether_type ==
3125 htons(0xffff));
3126 has_ethertype = true;
3127 eth_type = ntohs(ib_spec->eth.val.ether_type);
3128 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3129 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3130 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3131 }
3132 ib_spec = (void *)ib_spec + ib_spec->size;
3133 }
0f750966
AL		 3134
3135 type_valid = (!has_ethertype) || (!ip_spec_type);
3136 if (!type_valid && mask_valid) {
3137 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3138 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3139 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3140 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3141
3142 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3143 (((eth_type == ETH_P_MPLS_UC) ||
3144 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3145 }
3146
3147 return type_valid;
3148}
3149
19cc7524
AL		 3150static bool is_valid_attr(struct mlx5_core_dev *mdev,
3151 const struct ib_flow_attr *flow_attr)
0f750966 3152{
19cc7524
AL		 3153 return is_valid_ethertype(mdev, flow_attr, false) &&
3154 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3155}
3156
3157static void put_flow_table(struct mlx5_ib_dev *dev,
3158 struct mlx5_ib_flow_prio *prio, bool ft_added)
3159{
3160 prio->refcount -= !!ft_added;
3161 if (!prio->refcount) {
3162 mlx5_destroy_flow_table(prio->flow_table);
3163 prio->flow_table = NULL;
3164 }
3165}
3166
3b3233fb
RS		 3167static void counters_clear_description(struct ib_counters *counters)
3168{
3169 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3170
3171 mutex_lock(&mcounters->mcntrs_mutex);
3172 kfree(mcounters->counters_data);
3173 mcounters->counters_data = NULL;
3174 mcounters->cntrs_max_index = 0;
3175 mutex_unlock(&mcounters->mcntrs_mutex);
3176}
3177
038d2ef8
MG		 3178static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3179{
038d2ef8
MG		 3180 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3181 struct mlx5_ib_flow_handler,
3182 ibflow);
3183 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3184 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3185
9a4ca38d 3186 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3187
3188 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3189 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3190 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3191 list_del(&iter->list);
3192 kfree(iter);
3193 }
3194
74491de9 3195 mlx5_del_flow_rules(handler->rule);
5497adc6 3196 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3197 if (handler->ibcounters &&
3198 atomic_read(&handler->ibcounters->usecnt) == 1)
3199 counters_clear_description(handler->ibcounters);
038d2ef8 3200
3b3233fb 3201 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3202 if (handler->flow_matcher)
3203 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3204 kfree(handler);
3205
3206 return 0;
3207}
3208
35d19011
MG		 3209static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3210{
3211 priority *= 2;
3212 if (!dont_trap)
3213 priority++;
3214 return priority;
3215}
3216
cc0e5d42
MG		 3217enum flow_table_type {
3218 MLX5_IB_FT_RX,
3219 MLX5_IB_FT_TX
3220};
3221
00b7c2ab
MG		 3222#define MLX5_FS_MAX_TYPES 6
3223#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3224
3225static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3226 struct mlx5_ib_flow_prio *prio,
3227 int priority,
4adda112
MB		 3228 int num_entries, int num_groups,
3229 u32 flags)
d4be3f44
YH		 3230{
3231 struct mlx5_flow_table *ft;
3232
3233 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3234 num_entries,
3235 num_groups,
4adda112 3236 0, flags);
d4be3f44
YH		 3237 if (IS_ERR(ft))
3238 return ERR_CAST(ft);
3239
3240 prio->flow_table = ft;
3241 prio->refcount = 0;
3242 return prio;
3243}
3244
038d2ef8 3245static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3246 struct ib_flow_attr *flow_attr,
3247 enum flow_table_type ft_type)
038d2ef8 3248{
35d19011 3249 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3250 struct mlx5_flow_namespace *ns = NULL;
3251 struct mlx5_ib_flow_prio *prio;
3252 struct mlx5_flow_table *ft;
dac388ef 3253 int max_table_size;
038d2ef8
MG		 3254 int num_entries;
3255 int num_groups;
cecae747 3256 bool esw_encap;
4adda112 3257 u32 flags = 0;
038d2ef8 3258 int priority;
038d2ef8 3259
dac388ef
MG		 3260 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3261 log_max_ft_size));
cecae747
MG		 3262 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3263 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3264 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3265 enum mlx5_flow_namespace_type fn_type;
3266
3267 if (flow_is_multicast_only(flow_attr) &&
3268 !dont_trap)
038d2ef8
MG		 3269 priority = MLX5_IB_FLOW_MCAST_PRIO;
3270 else
35d19011
MG		 3271 priority = ib_prio_to_core_prio(flow_attr->priority,
3272 dont_trap);
78dd0c43
MB		 3273 if (ft_type == MLX5_IB_FT_RX) {
3274 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3275 prio = &dev->flow_db->prios[priority];
cecae747 3276 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3277 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3278 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3279 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3280 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3281 reformat_l3_tunnel_to_l2))
3282 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3283 } else {
3284 max_table_size =
3285 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3286 log_max_ft_size));
3287 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3288 prio = &dev->flow_db->egress_prios[priority];
cecae747 3289 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3290 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3291 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3292 }
3293 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3294 num_entries = MLX5_FS_MAX_ENTRIES;
3295 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3296 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3297 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3298 ns = mlx5_get_flow_namespace(dev->mdev,
3299 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3300 build_leftovers_ft_param(&priority,
3301 &num_entries,
3302 &num_groups);
9a4ca38d 3303 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3304 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3305 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3306 allow_sniffer_and_nic_rx_shared_tir))
3307 return ERR_PTR(-ENOTSUPP);
3308
3309 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3310 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3311 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3312
9a4ca38d 3313 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3314 priority = 0;
3315 num_entries = 1;
3316 num_groups = 1;
038d2ef8
MG		 3317 }
3318
3319 if (!ns)
3320 return ERR_PTR(-ENOTSUPP);
3321
3b70508a 3322 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3323
038d2ef8 3324 ft = prio->flow_table;
d4be3f44 3325 if (!ft)
3b70508a 3326 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3327 flags);
038d2ef8 3328
d4be3f44 3329 return prio;
038d2ef8
MG		 3330}
3331
a550ddfc
YH		 3332static void set_underlay_qp(struct mlx5_ib_dev *dev,
3333 struct mlx5_flow_spec *spec,
3334 u32 underlay_qpn)
3335{
3336 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3337 spec->match_criteria,
3338 misc_parameters);
3339 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3340 misc_parameters);
3341
3342 if (underlay_qpn &&
3343 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3344 ft_field_support.bth_dst_qp)) {
3345 MLX5_SET(fte_match_set_misc,
3346 misc_params_v, bth_dst_qp, underlay_qpn);
3347 MLX5_SET(fte_match_set_misc,
3348 misc_params_c, bth_dst_qp, 0xffffff);
3349 }
3350}
3351
5e95af5f
RS		 3352static int read_flow_counters(struct ib_device *ibdev,
3353 struct mlx5_read_counters_attr *read_attr)
3354{
3355 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3356 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3357
3358 return mlx5_fc_query(dev->mdev, fc,
3359 &read_attr->out[IB_COUNTER_PACKETS],
3360 &read_attr->out[IB_COUNTER_BYTES]);
3361}
3362
3363/* flow counters currently expose two counters packets and bytes */
3364#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3365static int counters_set_description(struct ib_counters *counters,
3366 enum mlx5_ib_counters_type counters_type,
3367 struct mlx5_ib_flow_counters_desc *desc_data,
3368 u32 ncounters)
3369{
3370 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3371 u32 cntrs_max_index = 0;
3372 int i;
3373
3374 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3375 return -EINVAL;
3376
3377 /* init the fields for the object */
3378 mcounters->type = counters_type;
5e95af5f
RS		 3379 mcounters->read_counters = read_flow_counters;
3380 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3381 mcounters->ncounters = ncounters;
3382 /* each counter entry have both description and index pair */
3383 for (i = 0; i < ncounters; i++) {
3384 if (desc_data[i].description > IB_COUNTER_BYTES)
3385 return -EINVAL;
3386
3387 if (cntrs_max_index <= desc_data[i].index)
3388 cntrs_max_index = desc_data[i].index + 1;
3389 }
3390
3391 mutex_lock(&mcounters->mcntrs_mutex);
3392 mcounters->counters_data = desc_data;
3393 mcounters->cntrs_max_index = cntrs_max_index;
3394 mutex_unlock(&mcounters->mcntrs_mutex);
3395
3396 return 0;
3397}
3398
3399#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3400static int flow_counters_set_data(struct ib_counters *ibcounters,
3401 struct mlx5_ib_create_flow *ucmd)
3402{
3403 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3404 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3405 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3406 bool hw_hndl = false;
3407 int ret = 0;
3408
3409 if (ucmd && ucmd->ncounters_data != 0) {
3410 cntrs_data = ucmd->data;
3411 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3412 return -EINVAL;
3413
3414 desc_data = kcalloc(cntrs_data->ncounters,
3415 sizeof(*desc_data),
3416 GFP_KERNEL);
3417 if (!desc_data)
3418 return -ENOMEM;
3419
3420 if (copy_from_user(desc_data,
3421 u64_to_user_ptr(cntrs_data->counters_data),
3422 sizeof(*desc_data) * cntrs_data->ncounters)) {
3423 ret = -EFAULT;
3424 goto free;
3425 }
3426 }
3427
3428 if (!mcounters->hw_cntrs_hndl) {
3429 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3430 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3431 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3432 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3433 goto free;
3434 }
3435 hw_hndl = true;
3436 }
3437
3438 if (desc_data) {
3439 /* counters already bound to at least one flow */
3440 if (mcounters->cntrs_max_index) {
3441 ret = -EINVAL;
3442 goto free_hndl;
3443 }
3444
3445 ret = counters_set_description(ibcounters,
3446 MLX5_IB_COUNTERS_FLOW,
3447 desc_data,
3448 cntrs_data->ncounters);
3449 if (ret)
3450 goto free_hndl;
3451
3452 } else if (!mcounters->cntrs_max_index) {
3453 /* counters not bound yet, must have udata passed */
3454 ret = -EINVAL;
3455 goto free_hndl;
3456 }
3457
3458 return 0;
3459
3460free_hndl:
3461 if (hw_hndl) {
3462 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3463 mcounters->hw_cntrs_hndl);
3464 mcounters->hw_cntrs_hndl = NULL;
3465 }
3466free:
3467 kfree(desc_data);
3468 return ret;
3469}
3470
a550ddfc
YH		 3471static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3472 struct mlx5_ib_flow_prio *ft_prio,
3473 const struct ib_flow_attr *flow_attr,
3474 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3475 u32 underlay_qpn,
3476 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3477{
3478 struct mlx5_flow_table *ft = ft_prio->flow_table;
3479 struct mlx5_ib_flow_handler *handler;
075572d4 3480 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3481 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3482 struct mlx5_flow_destination dest_arr[2] = {};
3483 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3484 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3485 unsigned int spec_index;
71c6e863 3486 u32 prev_type = 0;
038d2ef8 3487 int err = 0;
3b3233fb 3488 int dest_num = 0;
802c2125 3489 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3490
19cc7524 3491 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3492 return ERR_PTR(-EINVAL);
3493
6a4d00be 3494 if (dev->is_rep && is_egress)
78dd0c43
MB		 3495 return ERR_PTR(-EINVAL);
3496
1b9a07ee 3497 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3498 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3499 if (!handler || !spec) {
038d2ef8
MG		 3500 err = -ENOMEM;
3501 goto free;
3502 }
3503
3504 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3505 if (dst) {
3506 memcpy(&dest_arr[0], dst, sizeof(*dst));
3507 dest_num++;
3508 }
038d2ef8
MG		 3509
3510 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3511 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3512 spec->match_value,
71c6e863
AL		 3513 ib_flow, flow_attr, &flow_act,
3514 prev_type);
038d2ef8
MG		 3515 if (err < 0)
3516 goto free;
3517
71c6e863 3518 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3519 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3520 }
3521
a550ddfc
YH		 3522 if (!flow_is_multicast_only(flow_attr))
3523 set_underlay_qp(dev, spec, underlay_qpn);
3524
6a4d00be 3525 if (dev->is_rep) {
018a94ee
MB		 3526 void *misc;
3527
6a4d00be
MB		 3528 if (!dev->port[flow_attr->port - 1].rep) {
3529 err = -EINVAL;
3530 goto free;
3531 }
018a94ee
MB		 3532 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3533 misc_parameters);
3534 MLX5_SET(fte_match_set_misc, misc, source_port,
6a4d00be 3535 dev->port[flow_attr->port - 1].rep->vport);
018a94ee
MB		 3536 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3537 misc_parameters);
3538 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3539 }
3540
466fa6d2 3541 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3542
3543 if (is_egress &&
3544 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3545 err = -EINVAL;
3546 goto free;
3547 }
3548
3b3233fb 3549 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3550 struct mlx5_ib_mcounters *mcounters;
3551
3b3233fb
RS		 3552 err = flow_counters_set_data(flow_act.counters, ucmd);
3553 if (err)
3554 goto free;
3555
171c7625 3556 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3557 handler->ibcounters = flow_act.counters;
3558 dest_arr[dest_num].type =
3559 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3560 dest_arr[dest_num].counter_id =
3561 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3562 dest_num++;
3563 }
3564
075572d4 3565 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3566 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3567 rule_dst = NULL;
3568 dest_num = 0;
3569 }
a22ed86c 3570 } else {
802c2125
AY		 3571 if (is_egress)
3572 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3573 else
3574 flow_act.action |=
3b3233fb 3575 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3576 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3577 }
2ac693f9 3578
d5634fee 3579 if ((flow_act.flags & FLOW_ACT_HAS_TAG) &&
2ac693f9
MR		 3580 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3581 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3582 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3583 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3584 err = -EINVAL;
3585 goto free;
3586 }
74491de9 3587 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3588 &flow_act,
a22ed86c 3589 rule_dst, dest_num);
038d2ef8
MG		 3590
3591 if (IS_ERR(handler->rule)) {
3592 err = PTR_ERR(handler->rule);
3593 goto free;
3594 }
3595
d9d4980a 3596 ft_prio->refcount++;
5497adc6 3597 handler->prio = ft_prio;
d4be3f44 3598 handler->dev = dev;
038d2ef8
MG		 3599
3600 ft_prio->flow_table = ft;
3601free:
3b3233fb
RS		 3602 if (err && handler) {
3603 if (handler->ibcounters &&
3604 atomic_read(&handler->ibcounters->usecnt) == 1)
3605 counters_clear_description(handler->ibcounters);
038d2ef8 3606 kfree(handler);
3b3233fb 3607 }
c5bb1730 3608 kvfree(spec);
038d2ef8
MG		 3609 return err ? ERR_PTR(err) : handler;
3610}
3611
a550ddfc
YH		 3612static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3613 struct mlx5_ib_flow_prio *ft_prio,
3614 const struct ib_flow_attr *flow_attr,
3615 struct mlx5_flow_destination *dst)
3616{
3b3233fb 3617 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3618}
3619
35d19011
MG		 3620static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3621 struct mlx5_ib_flow_prio *ft_prio,
3622 struct ib_flow_attr *flow_attr,
3623 struct mlx5_flow_destination *dst)
3624{
3625 struct mlx5_ib_flow_handler *handler_dst = NULL;
3626 struct mlx5_ib_flow_handler *handler = NULL;
3627
3628 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3629 if (!IS_ERR(handler)) {
3630 handler_dst = create_flow_rule(dev, ft_prio,
3631 flow_attr, dst);
3632 if (IS_ERR(handler_dst)) {
74491de9 3633 mlx5_del_flow_rules(handler->rule);
d9d4980a 3634 ft_prio->refcount--;
35d19011
MG		 3635 kfree(handler);
3636 handler = handler_dst;
3637 } else {
3638 list_add(&handler_dst->list, &handler->list);
3639 }
3640 }
3641
3642 return handler;
3643}
038d2ef8
MG		 3644enum {
3645 LEFTOVERS_MC,
3646 LEFTOVERS_UC,
3647};
3648
3649static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3650 struct mlx5_ib_flow_prio *ft_prio,
3651 struct ib_flow_attr *flow_attr,
3652 struct mlx5_flow_destination *dst)
3653{
3654 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3655 struct mlx5_ib_flow_handler *handler = NULL;
3656
3657 static struct {
3658 struct ib_flow_attr flow_attr;
3659 struct ib_flow_spec_eth eth_flow;
3660 } leftovers_specs[] = {
3661 [LEFTOVERS_MC] = {
3662 .flow_attr = {
3663 .num_of_specs = 1,
3664 .size = sizeof(leftovers_specs[0])
3665 },
3666 .eth_flow = {
3667 .type = IB_FLOW_SPEC_ETH,
3668 .size = sizeof(struct ib_flow_spec_eth),
3669 .mask = {.dst_mac = {0x1} },
3670 .val = {.dst_mac = {0x1} }
3671 }
3672 },
3673 [LEFTOVERS_UC] = {
3674 .flow_attr = {
3675 .num_of_specs = 1,
3676 .size = sizeof(leftovers_specs[0])
3677 },
3678 .eth_flow = {
3679 .type = IB_FLOW_SPEC_ETH,
3680 .size = sizeof(struct ib_flow_spec_eth),
3681 .mask = {.dst_mac = {0x1} },
3682 .val = {.dst_mac = {} }
3683 }
3684 }
3685 };
3686
3687 handler = create_flow_rule(dev, ft_prio,
3688 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3689 dst);
3690 if (!IS_ERR(handler) &&
3691 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3692 handler_ucast = create_flow_rule(dev, ft_prio,
3693 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3694 dst);
3695 if (IS_ERR(handler_ucast)) {
74491de9 3696 mlx5_del_flow_rules(handler->rule);
d9d4980a 3697 ft_prio->refcount--;
038d2ef8
MG		 3698 kfree(handler);
3699 handler = handler_ucast;
3700 } else {
3701 list_add(&handler_ucast->list, &handler->list);
3702 }
3703 }
3704
3705 return handler;
3706}
3707
cc0e5d42
MG		 3708static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3709 struct mlx5_ib_flow_prio *ft_rx,
3710 struct mlx5_ib_flow_prio *ft_tx,
3711 struct mlx5_flow_destination *dst)
3712{
3713 struct mlx5_ib_flow_handler *handler_rx;
3714 struct mlx5_ib_flow_handler *handler_tx;
3715 int err;
3716 static const struct ib_flow_attr flow_attr = {
3717 .num_of_specs = 0,
3718 .size = sizeof(flow_attr)
3719 };
3720
3721 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3722 if (IS_ERR(handler_rx)) {
3723 err = PTR_ERR(handler_rx);
3724 goto err;
3725 }
3726
3727 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3728 if (IS_ERR(handler_tx)) {
3729 err = PTR_ERR(handler_tx);
3730 goto err_tx;
3731 }
3732
3733 list_add(&handler_tx->list, &handler_rx->list);
3734
3735 return handler_rx;
3736
3737err_tx:
74491de9 3738 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3739 ft_rx->refcount--;
3740 kfree(handler_rx);
3741err:
3742 return ERR_PTR(err);
3743}
3744
038d2ef8
MG		 3745static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3746 struct ib_flow_attr *flow_attr,
59082a32
MB		 3747 int domain,
3748 struct ib_udata *udata)
038d2ef8
MG		 3749{
3750 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3751 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3752 struct mlx5_ib_flow_handler *handler = NULL;
3753 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3754 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3755 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3756 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3757 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3758 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3759 int err;
a550ddfc 3760 int underlay_qpn;
038d2ef8 3761
3b3233fb
RS		 3762 if (udata && udata->inlen) {
3763 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3764 sizeof(ucmd_hdr.reserved);
3765 if (udata->inlen < min_ucmd_sz)
3766 return ERR_PTR(-EOPNOTSUPP);
3767
3768 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3769 if (err)
3770 return ERR_PTR(err);
3771
3772 /* currently supports only one counters data */
3773 if (ucmd_hdr.ncounters_data > 1)
3774 return ERR_PTR(-EINVAL);
3775
3776 required_ucmd_sz = min_ucmd_sz +
3777 sizeof(struct mlx5_ib_flow_counters_data) *
3778 ucmd_hdr.ncounters_data;
3779 if (udata->inlen > required_ucmd_sz &&
3780 !ib_is_udata_cleared(udata, required_ucmd_sz,
3781 udata->inlen - required_ucmd_sz))
3782 return ERR_PTR(-EOPNOTSUPP);
3783
3784 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3785 if (!ucmd)
3786 return ERR_PTR(-ENOMEM);
3787
3788 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3789 if (err)
3790 goto free_ucmd;
3b3233fb 3791 }
59082a32 3792
299eafee
GS		 3793 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3794 err = -ENOMEM;
3795 goto free_ucmd;
3796 }
038d2ef8
MG		 3797
3798 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3799 flow_attr->port > dev->num_ports ||
802c2125 3800 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3801 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3802 err = -EINVAL;
3803 goto free_ucmd;
3804 }
802c2125
AY		 3805
3806 if (is_egress &&
3807 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3808 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3809 err = -EINVAL;
3810 goto free_ucmd;
3811 }
038d2ef8
MG		 3812
3813 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3814 if (!dst) {
3815 err = -ENOMEM;
3816 goto free_ucmd;
3817 }
038d2ef8 3818
9a4ca38d 3819 mutex_lock(&dev->flow_db->lock);
038d2ef8 3820
802c2125
AY		 3821 ft_prio = get_flow_table(dev, flow_attr,
3822 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3823 if (IS_ERR(ft_prio)) {
3824 err = PTR_ERR(ft_prio);
3825 goto unlock;
3826 }
cc0e5d42
MG		 3827 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3828 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3829 if (IS_ERR(ft_prio_tx)) {
3830 err = PTR_ERR(ft_prio_tx);
3831 ft_prio_tx = NULL;
3832 goto destroy_ft;
3833 }
3834 }
038d2ef8 3835
802c2125
AY		 3836 if (is_egress) {
3837 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3838 } else {
3839 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3840 if (mqp->flags & MLX5_IB_QP_RSS)
3841 dst->tir_num = mqp->rss_qp.tirn;
3842 else
3843 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3844 }
038d2ef8
MG		 3845
3846 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3847 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3848 handler = create_dont_trap_rule(dev, ft_prio,
3849 flow_attr, dst);
3850 } else {
a550ddfc
YH		 3851 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3852 mqp->underlay_qpn : 0;
3853 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3854 dst, underlay_qpn, ucmd);
35d19011 3855 }
038d2ef8
MG		 3856 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3857 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3858 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3859 dst);
cc0e5d42
MG		 3860 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3861 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3862 } else {
3863 err = -EINVAL;
3864 goto destroy_ft;
3865 }
3866
3867 if (IS_ERR(handler)) {
3868 err = PTR_ERR(handler);
3869 handler = NULL;
3870 goto destroy_ft;
3871 }
3872
9a4ca38d 3873 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3874 kfree(dst);
3b3233fb 3875 kfree(ucmd);
038d2ef8
MG		 3876
3877 return &handler->ibflow;
3878
3879destroy_ft:
3880 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3881 if (ft_prio_tx)
3882 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3883unlock:
9a4ca38d 3884 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3885 kfree(dst);
299eafee 3886free_ucmd:
3b3233fb 3887 kfree(ucmd);
038d2ef8
MG		 3888 return ERR_PTR(err);
3889}
3890
b47fd4ff
MB		 3891static struct mlx5_ib_flow_prio *
3892_get_flow_table(struct mlx5_ib_dev *dev,
3893 struct mlx5_ib_flow_matcher *fs_matcher,
3894 bool mcast)
d4be3f44 3895{
d4be3f44 3896 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 3897 struct mlx5_ib_flow_prio *prio = NULL;
3898 int max_table_size = 0;
cecae747 3899 bool esw_encap;
b47fd4ff
MB		 3900 u32 flags = 0;
3901 int priority;
3902
13a43765
MB		 3903 if (mcast)
3904 priority = MLX5_IB_FLOW_MCAST_PRIO;
3905 else
3906 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3907
cecae747
MG		 3908 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3909 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 3910 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3911 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3912 log_max_ft_size));
cecae747 3913 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 3914 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3915 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 3916 reformat_l3_tunnel_to_l2) &&
3917 !esw_encap)
b47fd4ff 3918 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3919 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3920 max_table_size = BIT(
3921 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 3922 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 3923 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3924 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3925 max_table_size = BIT(
3926 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
3927 priority = FDB_BYPASS_PATH;
b47fd4ff 3928 }
d4be3f44 3929
3b70508a 3930 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 3931
b47fd4ff 3932 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3933 if (!ns)
3934 return ERR_PTR(-ENOTSUPP);
3935
b47fd4ff
MB		 3936 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3937 prio = &dev->flow_db->prios[priority];
13a43765 3938 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 3939 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 3940 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3941 prio = &dev->flow_db->fdb;
3942
3943 if (!prio)
3944 return ERR_PTR(-EINVAL);
d4be3f44
YH		 3945
3946 if (prio->flow_table)
3947 return prio;
3948
3b70508a 3949 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 3950 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 3951}
3952
3953static struct mlx5_ib_flow_handler *
3954_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3955 struct mlx5_ib_flow_prio *ft_prio,
3956 struct mlx5_flow_destination *dst,
3957 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 3958 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 3959 void *cmd_in, int inlen,
3960 int dst_num)
d4be3f44
YH		 3961{
3962 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 3963 struct mlx5_flow_spec *spec;
3964 struct mlx5_flow_table *ft = ft_prio->flow_table;
3965 int err = 0;
3966
3967 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3968 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3969 if (!handler || !spec) {
3970 err = -ENOMEM;
3971 goto free;
3972 }
3973
3974 INIT_LIST_HEAD(&handler->list);
3975
3976 memcpy(spec->match_value, cmd_in, inlen);
3977 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3978 fs_matcher->mask_len);
3979 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3980
d4be3f44 3981 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 3982 flow_act, dst, dst_num);
d4be3f44
YH		 3983
3984 if (IS_ERR(handler->rule)) {
3985 err = PTR_ERR(handler->rule);
3986 goto free;
3987 }
3988
3989 ft_prio->refcount++;
3990 handler->prio = ft_prio;
3991 handler->dev = dev;
3992 ft_prio->flow_table = ft;
3993
3994free:
3995 if (err)
3996 kfree(handler);
3997 kvfree(spec);
3998 return err ? ERR_PTR(err) : handler;
3999}
4000
4001static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4002 void *match_v)
4003{
4004 void *match_c;
4005 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4006 void *dmac, *dmac_mask;
4007 void *ipv4, *ipv4_mask;
4008
4009 if (!(fs_matcher->match_criteria_enable &
4010 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4011 return false;
4012
4013 match_c = fs_matcher->matcher_mask.match_params;
4014 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4015 outer_headers);
4016 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4017 outer_headers);
4018
4019 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4020 dmac_47_16);
4021 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4022 dmac_47_16);
4023
4024 if (is_multicast_ether_addr(dmac) &&
4025 is_multicast_ether_addr(dmac_mask))
4026 return true;
4027
4028 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4029 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4030
4031 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4032 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4033
4034 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4035 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4036 return true;
4037
4038 return false;
4039}
4040
32269441
YH		 4041struct mlx5_ib_flow_handler *
4042mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4043 struct mlx5_ib_flow_matcher *fs_matcher,
b823dd6d 4044 struct mlx5_flow_act *flow_act,
bfc5d839 4045 u32 counter_id,
32269441
YH		 4046 void *cmd_in, int inlen, int dest_id,
4047 int dest_type)
4048{
d4be3f44
YH		 4049 struct mlx5_flow_destination *dst;
4050 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4051 struct mlx5_ib_flow_handler *handler;
bfc5d839 4052 int dst_num = 0;
d4be3f44
YH		 4053 bool mcast;
4054 int err;
4055
4056 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4057 return ERR_PTR(-EOPNOTSUPP);
4058
4059 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4060 return ERR_PTR(-ENOMEM);
4061
8e8aa145 4062 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4063 if (!dst)
4064 return ERR_PTR(-ENOMEM);
4065
4066 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4067 mutex_lock(&dev->flow_db->lock);
4068
b47fd4ff 4069 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4070 if (IS_ERR(ft_prio)) {
4071 err = PTR_ERR(ft_prio);
4072 goto unlock;
4073 }
4074
6346f0bf 4075 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4076 dst[dst_num].type = dest_type;
4077 dst[dst_num].tir_num = dest_id;
b823dd6d 4078 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4079 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4080 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4081 dst[dst_num].ft_num = dest_id;
b823dd6d 4082 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4083 } else {
bfc5d839 4084 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4085 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4086 }
4087
bfc5d839
MB		 4088 dst_num++;
4089
4090 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4091 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4092 dst[dst_num].counter_id = counter_id;
4093 dst_num++;
4094 }
4095
b823dd6d 4096 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
bfc5d839 4097 cmd_in, inlen, dst_num);
d4be3f44
YH		 4098
4099 if (IS_ERR(handler)) {
4100 err = PTR_ERR(handler);
4101 goto destroy_ft;
4102 }
4103
4104 mutex_unlock(&dev->flow_db->lock);
4105 atomic_inc(&fs_matcher->usecnt);
4106 handler->flow_matcher = fs_matcher;
4107
4108 kfree(dst);
4109
4110 return handler;
4111
4112destroy_ft:
4113 put_flow_table(dev, ft_prio, false);
4114unlock:
4115 mutex_unlock(&dev->flow_db->lock);
4116 kfree(dst);
4117
4118 return ERR_PTR(err);
32269441
YH		 4119}
4120
c6475a0b
AY		 4121static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4122{
4123 u32 flags = 0;
4124
4125 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4126 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4127
4128 return flags;
4129}
4130
4131#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4132static struct ib_flow_action *
4133mlx5_ib_create_flow_action_esp(struct ib_device *device,
4134 const struct ib_flow_action_attrs_esp *attr,
4135 struct uverbs_attr_bundle *attrs)
4136{
4137 struct mlx5_ib_dev *mdev = to_mdev(device);
4138 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4139 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4140 struct mlx5_ib_flow_action *action;
4141 u64 action_flags;
4142 u64 flags;
4143 int err = 0;
4144
bccd0622
JG		 4145 err = uverbs_get_flags64(
4146 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4147 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4148 if (err)
4149 return ERR_PTR(err);
c6475a0b
AY		 4150
4151 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4152
4153 /* We current only support a subset of the standard features. Only a
4154 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4155 * (with overlap). Full offload mode isn't supported.
4156 */
4157 if (!attr->keymat || attr->replay || attr->encap ||
4158 attr->spi || attr->seq || attr->tfc_pad ||
4159 attr->hard_limit_pkts ||
4160 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4161 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4162 return ERR_PTR(-EOPNOTSUPP);
4163
4164 if (attr->keymat->protocol !=
4165 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4166 return ERR_PTR(-EOPNOTSUPP);
4167
4168 aes_gcm = &attr->keymat->keymat.aes_gcm;
4169
4170 if (aes_gcm->icv_len != 16 ||
4171 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4172 return ERR_PTR(-EOPNOTSUPP);
4173
4174 action = kmalloc(sizeof(*action), GFP_KERNEL);
4175 if (!action)
4176 return ERR_PTR(-ENOMEM);
4177
4178 action->esp_aes_gcm.ib_flags = attr->flags;
4179 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4180 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4181 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4182 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4183 sizeof(accel_attrs.keymat.aes_gcm.salt));
4184 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4185 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4186 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4187 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4188 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4189
4190 accel_attrs.esn = attr->esn;
4191 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4192 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4193 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4194 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4195
4196 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4197 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4198
4199 action->esp_aes_gcm.ctx =
4200 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4201 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4202 err = PTR_ERR(action->esp_aes_gcm.ctx);
4203 goto err_parse;
4204 }
4205
4206 action->esp_aes_gcm.ib_flags = attr->flags;
4207
4208 return &action->ib_action;
4209
4210err_parse:
4211 kfree(action);
4212 return ERR_PTR(err);
4213}
4214
349705c1
MB		 4215static int
4216mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4217 const struct ib_flow_action_attrs_esp *attr,
4218 struct uverbs_attr_bundle *attrs)
4219{
4220 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4221 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4222 int err = 0;
4223
4224 if (attr->keymat || attr->replay || attr->encap ||
4225 attr->spi || attr->seq || attr->tfc_pad ||
4226 attr->hard_limit_pkts ||
4227 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4228 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4229 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4230 return -EOPNOTSUPP;
4231
4232 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4233 * be modified.
4234 */
4235 if (!(maction->esp_aes_gcm.ib_flags &
4236 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4237 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4238 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4239 return -EINVAL;
4240
4241 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4242 sizeof(accel_attrs));
4243
4244 accel_attrs.esn = attr->esn;
4245 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4246 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4247 else
4248 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4249
4250 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4251 &accel_attrs);
4252 if (err)
4253 return err;
4254
4255 maction->esp_aes_gcm.ib_flags &=
4256 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4257 maction->esp_aes_gcm.ib_flags |=
4258 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4259
4260 return 0;
4261}
4262
c6475a0b
AY		 4263static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4264{
4265 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4266
4267 switch (action->type) {
4268 case IB_FLOW_ACTION_ESP:
4269 /*
4270 * We only support aes_gcm by now, so we implicitly know this is
4271 * the underline crypto.
4272 */
4273 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4274 break;
b4749bf2
MB		 4275 case IB_FLOW_ACTION_UNSPECIFIED:
4276 mlx5_ib_destroy_flow_action_raw(maction);
4277 break;
c6475a0b
AY		 4278 default:
4279 WARN_ON(true);
4280 break;
4281 }
4282
4283 kfree(maction);
4284 return 0;
4285}
4286
e126ba97
EC		 4287static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4288{
4289 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4290 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4291 int err;
539ec982
YH		 4292 u16 uid;
4293
4294 uid = ibqp->pd ?
4295 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4296
81e30880
YH		 4297 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4298 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4299 return -EOPNOTSUPP;
4300 }
4301
539ec982 4302 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4303 if (err)
4304 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4305 ibqp->qp_num, gid->raw);
4306
4307 return err;
4308}
4309
4310static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4311{
4312 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4313 int err;
539ec982 4314 u16 uid;
e126ba97 4315
539ec982
YH		 4316 uid = ibqp->pd ?
4317 to_mpd(ibqp->pd)->uid : 0;
4318 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4319 if (err)
4320 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4321 ibqp->qp_num, gid->raw);
4322
4323 return err;
4324}
4325
4326static int init_node_data(struct mlx5_ib_dev *dev)
4327{
1b5daf11 4328 int err;
e126ba97 4329
1b5daf11 4330 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4331 if (err)
1b5daf11 4332 return err;
e126ba97 4333
1b5daf11 4334 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4335
1b5daf11 4336 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4337}
4338
508a523f
PP		 4339static ssize_t fw_pages_show(struct device *device,
4340 struct device_attribute *attr, char *buf)
e126ba97
EC		 4341{
4342 struct mlx5_ib_dev *dev =
54747231 4343 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4344
9603b61d 4345 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4346}
508a523f 4347static DEVICE_ATTR_RO(fw_pages);
e126ba97 4348
508a523f 4349static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4350 struct device_attribute *attr, char *buf)
4351{
4352 struct mlx5_ib_dev *dev =
54747231 4353 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4354
6aec21f6 4355 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4356}
508a523f 4357static DEVICE_ATTR_RO(reg_pages);
e126ba97 4358
508a523f
PP		 4359static ssize_t hca_type_show(struct device *device,
4360 struct device_attribute *attr, char *buf)
e126ba97
EC		 4361{
4362 struct mlx5_ib_dev *dev =
54747231
PP		 4363 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4364
9603b61d 4365 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4366}
508a523f 4367static DEVICE_ATTR_RO(hca_type);
e126ba97 4368
508a523f
PP		 4369static ssize_t hw_rev_show(struct device *device,
4370 struct device_attribute *attr, char *buf)
e126ba97
EC		 4371{
4372 struct mlx5_ib_dev *dev =
54747231
PP		 4373 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4374
9603b61d 4375 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4376}
508a523f 4377static DEVICE_ATTR_RO(hw_rev);
e126ba97 4378
508a523f
PP		 4379static ssize_t board_id_show(struct device *device,
4380 struct device_attribute *attr, char *buf)
e126ba97
EC		 4381{
4382 struct mlx5_ib_dev *dev =
54747231
PP		 4383 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4384
e126ba97 4385 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4386 dev->mdev->board_id);
e126ba97 4387}
508a523f 4388static DEVICE_ATTR_RO(board_id);
e126ba97 4389
508a523f
PP		 4390static struct attribute *mlx5_class_attributes[] = {
4391 &dev_attr_hw_rev.attr,
4392 &dev_attr_hca_type.attr,
4393 &dev_attr_board_id.attr,
4394 &dev_attr_fw_pages.attr,
4395 &dev_attr_reg_pages.attr,
4396 NULL,
4397};
e126ba97 4398
508a523f
PP		 4399static const struct attribute_group mlx5_attr_group = {
4400 .attrs = mlx5_class_attributes,
e126ba97
EC		 4401};
4402
7722f47e
HE		 4403static void pkey_change_handler(struct work_struct *work)
4404{
4405 struct mlx5_ib_port_resources *ports =
4406 container_of(work, struct mlx5_ib_port_resources,
4407 pkey_change_work);
4408
4409 mutex_lock(&ports->devr->mutex);
4410 mlx5_ib_gsi_pkey_change(ports->gsi);
4411 mutex_unlock(&ports->devr->mutex);
4412}
4413
89ea94a7
MG		 4414static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4415{
4416 struct mlx5_ib_qp *mqp;
4417 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4418 struct mlx5_core_cq *mcq;
4419 struct list_head cq_armed_list;
4420 unsigned long flags_qp;
4421 unsigned long flags_cq;
4422 unsigned long flags;
4423
4424 INIT_LIST_HEAD(&cq_armed_list);
4425
4426 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4427 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4428 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4429 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4430 if (mqp->sq.tail != mqp->sq.head) {
4431 send_mcq = to_mcq(mqp->ibqp.send_cq);
4432 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4433 if (send_mcq->mcq.comp &&
4434 mqp->ibqp.send_cq->comp_handler) {
4435 if (!send_mcq->mcq.reset_notify_added) {
4436 send_mcq->mcq.reset_notify_added = 1;
4437 list_add_tail(&send_mcq->mcq.reset_notify,
4438 &cq_armed_list);
4439 }
4440 }
4441 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4442 }
4443 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4444 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4445 /* no handling is needed for SRQ */
4446 if (!mqp->ibqp.srq) {
4447 if (mqp->rq.tail != mqp->rq.head) {
4448 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4449 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4450 if (recv_mcq->mcq.comp &&
4451 mqp->ibqp.recv_cq->comp_handler) {
4452 if (!recv_mcq->mcq.reset_notify_added) {
4453 recv_mcq->mcq.reset_notify_added = 1;
4454 list_add_tail(&recv_mcq->mcq.reset_notify,
4455 &cq_armed_list);
4456 }
4457 }
4458 spin_unlock_irqrestore(&recv_mcq->lock,
4459 flags_cq);
4460 }
4461 }
4462 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4463 }
4464 /*At that point all inflight post send were put to be executed as of we
4465 * lock/unlock above locks Now need to arm all involved CQs.
4466 */
4467 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4468 mcq->comp(mcq);
4469 }
4470 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4471}
4472
03404e8a
MG		 4473static void delay_drop_handler(struct work_struct *work)
4474{
4475 int err;
4476 struct mlx5_ib_delay_drop *delay_drop =
4477 container_of(work, struct mlx5_ib_delay_drop,
4478 delay_drop_work);
4479
fe248c3a
MG		 4480 atomic_inc(&delay_drop->events_cnt);
4481
03404e8a
MG		 4482 mutex_lock(&delay_drop->lock);
4483 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4484 delay_drop->timeout);
4485 if (err) {
4486 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4487 delay_drop->timeout);
4488 delay_drop->activate = false;
4489 }
4490 mutex_unlock(&delay_drop->lock);
4491}
4492
09e574fa
SM		 4493static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4494 struct ib_event *ibev)
4495{
6cfdc7e4
AL		 4496 u8 port = (eqe->data.port.port >> 4) & 0xf;
4497
09e574fa
SM		 4498 switch (eqe->sub_type) {
4499 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4500 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4501 IB_LINK_LAYER_ETHERNET)
4502 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4503 break;
4504 default: /* do nothing */
4505 return;
4506 }
4507}
4508
134e9349
SM		 4509static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4510 struct ib_event *ibev)
4511{
4512 u8 port = (eqe->data.port.port >> 4) & 0xf;
4513
4514 ibev->element.port_num = port;
4515
4516 switch (eqe->sub_type) {
4517 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4518 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4519 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4520 /* In RoCE, port up/down events are handled in
4521 * mlx5_netdev_event().
4522 */
4523 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4524 IB_LINK_LAYER_ETHERNET)
4525 return -EINVAL;
4526
4527 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4528 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4529 break;
4530
4531 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4532 ibev->event = IB_EVENT_LID_CHANGE;
4533 break;
4534
4535 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4536 ibev->event = IB_EVENT_PKEY_CHANGE;
4537 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4538 break;
4539
4540 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4541 ibev->event = IB_EVENT_GID_CHANGE;
4542 break;
4543
4544 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4545 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4546 break;
4547 default:
4548 return -EINVAL;
4549 }
4550
4551 return 0;
4552}
4553
d69a24e0 4554static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4555{
d69a24e0
DJ		 4556 struct mlx5_ib_event_work *work =
4557 container_of(_work, struct mlx5_ib_event_work, work);
4558 struct mlx5_ib_dev *ibdev;
e126ba97 4559 struct ib_event ibev;
dbaaff2a 4560 bool fatal = false;
e126ba97 4561
df097a27
SM		 4562 if (work->is_slave) {
4563 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4564 if (!ibdev)
4565 goto out;
4566 } else {
df097a27 4567 ibdev = work->dev;
d69a24e0
DJ		 4568 }
4569
4570 switch (work->event) {
e126ba97 4571 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4572 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4573 mlx5_ib_handle_internal_error(ibdev);
134e9349 4574 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4575 fatal = true;
e126ba97 4576 break;
134e9349
SM		 4577 case MLX5_EVENT_TYPE_PORT_CHANGE:
4578 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4579 goto out;
e126ba97 4580 break;
09e574fa
SM		 4581 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4582 handle_general_event(ibdev, work->param, &ibev);
4583 /* fall through */
bdc37924 4584 default:
03404e8a 4585 goto out;
e126ba97
EC		 4586 }
4587
134e9349 4588 ibev.device = &ibdev->ib_dev;
e126ba97 4589
134e9349
SM		 4590 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4591 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4592 goto out;
a0c84c32
EC		 4593 }
4594
e126ba97
EC		 4595 if (ibdev->ib_active)
4596 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4597
4598 if (fatal)
4599 ibdev->ib_active = false;
03404e8a 4600out:
d69a24e0
DJ		 4601 kfree(work);
4602}
4603
df097a27
SM		 4604static int mlx5_ib_event(struct notifier_block *nb,
4605 unsigned long event, void *param)
d69a24e0
DJ		 4606{
4607 struct mlx5_ib_event_work *work;
4608
4609 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4610 if (!work)
df097a27 4611 return NOTIFY_DONE;
d69a24e0 4612
10bea9c8 4613 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4614 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4615 work->is_slave = false;
10bea9c8 4616 work->param = param;
10bea9c8
LR		 4617 work->event = event;
4618
4619 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4620
4621 return NOTIFY_OK;
4622}
4623
4624static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4625 unsigned long event, void *param)
4626{
4627 struct mlx5_ib_event_work *work;
4628
4629 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4630 if (!work)
4631 return NOTIFY_DONE;
4632
4633 INIT_WORK(&work->work, mlx5_ib_handle_event);
4634 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4635 work->is_slave = true;
4636 work->param = param;
4637 work->event = event;
4638 queue_work(mlx5_ib_event_wq, &work->work);
4639
4640 return NOTIFY_OK;
e126ba97
EC		 4641}
4642
c43f1112
MG		 4643static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4644{
4645 struct mlx5_hca_vport_context vport_ctx;
4646 int err;
4647 int port;
4648
a989ea01 4649 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4650 dev->mdev->port_caps[port - 1].has_smi = false;
4651 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4652 MLX5_CAP_PORT_TYPE_IB) {
4653 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4654 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4655 port, 0,
4656 &vport_ctx);
4657 if (err) {
4658 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4659 port, err);
4660 return err;
4661 }
4662 dev->mdev->port_caps[port - 1].has_smi =
4663 vport_ctx.has_smi;
4664 } else {
4665 dev->mdev->port_caps[port - 1].has_smi = true;
4666 }
4667 }
4668 }
4669 return 0;
4670}
4671
e126ba97
EC		 4672static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4673{
4674 int port;
4675
508562d6 4676 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4677 mlx5_query_ext_port_caps(dev, port);
4678}
4679
26628e2d 4680static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4681{
4682 struct ib_device_attr *dprops = NULL;
4683 struct ib_port_attr *pprops = NULL;
f614fc15 4684 int err = -ENOMEM;
2528e33e 4685 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4686
4687 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4688 if (!pprops)
4689 goto out;
4690
4691 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4692 if (!dprops)
4693 goto out;
4694
2528e33e 4695 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4696 if (err) {
4697 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4698 goto out;
4699 }
4700
32f69e4b
DJ		 4701 memset(pprops, 0, sizeof(*pprops));
4702 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4703 if (err) {
4704 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4705 port, err);
4706 goto out;
e126ba97
EC		 4707 }
4708
32f69e4b
DJ		 4709 dev->mdev->port_caps[port - 1].pkey_table_len =
4710 dprops->max_pkeys;
4711 dev->mdev->port_caps[port - 1].gid_table_len =
4712 pprops->gid_tbl_len;
4713 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4714 port, dprops->max_pkeys, pprops->gid_tbl_len);
4715
e126ba97
EC		 4716out:
4717 kfree(pprops);
4718 kfree(dprops);
4719
4720 return err;
4721}
4722
26628e2d
MB		 4723static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4724{
4725 /* For representors use port 1, is this is the only native
4726 * port
4727 */
4728 if (dev->is_rep)
4729 return __get_port_caps(dev, 1);
4730 return __get_port_caps(dev, port);
4731}
4732
e126ba97
EC		 4733static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4734{
4735 int err;
4736
4737 err = mlx5_mr_cache_cleanup(dev);
4738 if (err)
4739 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4740
32927e28 4741 if (dev->umrc.qp)
c4367a26 4742 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4743 if (dev->umrc.cq)
4744 ib_free_cq(dev->umrc.cq);
4745 if (dev->umrc.pd)
4746 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4747}
4748
4749enum {
4750 MAX_UMR_WR = 128,
4751};
4752
4753static int create_umr_res(struct mlx5_ib_dev *dev)
4754{
4755 struct ib_qp_init_attr *init_attr = NULL;
4756 struct ib_qp_attr *attr = NULL;
4757 struct ib_pd *pd;
4758 struct ib_cq *cq;
4759 struct ib_qp *qp;
e126ba97
EC		 4760 int ret;
4761
4762 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4763 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4764 if (!attr || !init_attr) {
4765 ret = -ENOMEM;
4766 goto error_0;
4767 }
4768
ed082d36 4769 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4770 if (IS_ERR(pd)) {
4771 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4772 ret = PTR_ERR(pd);
4773 goto error_0;
4774 }
4775
add08d76 4776 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4777 if (IS_ERR(cq)) {
4778 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4779 ret = PTR_ERR(cq);
4780 goto error_2;
4781 }
e126ba97
EC		 4782
4783 init_attr->send_cq = cq;
4784 init_attr->recv_cq = cq;
4785 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4786 init_attr->cap.max_send_wr = MAX_UMR_WR;
4787 init_attr->cap.max_send_sge = 1;
4788 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4789 init_attr->port_num = 1;
4790 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4791 if (IS_ERR(qp)) {
4792 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4793 ret = PTR_ERR(qp);
4794 goto error_3;
4795 }
4796 qp->device = &dev->ib_dev;
4797 qp->real_qp = qp;
4798 qp->uobject = NULL;
4799 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4800 qp->send_cq = init_attr->send_cq;
4801 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4802
4803 attr->qp_state = IB_QPS_INIT;
4804 attr->port_num = 1;
4805 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4806 IB_QP_PORT, NULL);
4807 if (ret) {
4808 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4809 goto error_4;
4810 }
4811
4812 memset(attr, 0, sizeof(*attr));
4813 attr->qp_state = IB_QPS_RTR;
4814 attr->path_mtu = IB_MTU_256;
4815
4816 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4817 if (ret) {
4818 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4819 goto error_4;
4820 }
4821
4822 memset(attr, 0, sizeof(*attr));
4823 attr->qp_state = IB_QPS_RTS;
4824 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4825 if (ret) {
4826 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4827 goto error_4;
4828 }
4829
4830 dev->umrc.qp = qp;
4831 dev->umrc.cq = cq;
e126ba97
EC		 4832 dev->umrc.pd = pd;
4833
4834 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4835 ret = mlx5_mr_cache_init(dev);
4836 if (ret) {
4837 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4838 goto error_4;
4839 }
4840
4841 kfree(attr);
4842 kfree(init_attr);
4843
4844 return 0;
4845
4846error_4:
c4367a26 4847 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4848 dev->umrc.qp = NULL;
e126ba97
EC		 4849
4850error_3:
add08d76 4851 ib_free_cq(cq);
32927e28 4852 dev->umrc.cq = NULL;
e126ba97
EC		 4853
4854error_2:
e126ba97 4855 ib_dealloc_pd(pd);
32927e28 4856 dev->umrc.pd = NULL;
e126ba97
EC		 4857
4858error_0:
4859 kfree(attr);
4860 kfree(init_attr);
4861 return ret;
4862}
4863
6e8484c5
MG		 4864static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4865{
4866 switch (umr_fence_cap) {
4867 case MLX5_CAP_UMR_FENCE_NONE:
4868 return MLX5_FENCE_MODE_NONE;
4869 case MLX5_CAP_UMR_FENCE_SMALL:
4870 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4871 default:
4872 return MLX5_FENCE_MODE_STRONG_ORDERING;
4873 }
4874}
4875
e126ba97
EC		 4876static int create_dev_resources(struct mlx5_ib_resources *devr)
4877{
4878 struct ib_srq_init_attr attr;
4879 struct mlx5_ib_dev *dev;
21a428a0 4880 struct ib_device *ibdev;
bcf4c1ea 4881 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4882 int port;
e126ba97
EC		 4883 int ret = 0;
4884
4885 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 4886 ibdev = &dev->ib_dev;
e126ba97 4887
d16e91da
HE		 4888 mutex_init(&devr->mutex);
4889
21a428a0
LR		 4890 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4891 if (!devr->p0)
4892 return -ENOMEM;
4893
4894 devr->p0->device = ibdev;
e126ba97
EC		 4895 devr->p0->uobject = NULL;
4896 atomic_set(&devr->p0->usecnt, 0);
4897
ff23dfa1 4898 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 4899 if (ret)
4900 goto error0;
4901
e39afe3d
LR		 4902 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4903 if (!devr->c0) {
4904 ret = -ENOMEM;
e126ba97
EC		 4905 goto error1;
4906 }
e39afe3d
LR		 4907
4908 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 4909 atomic_set(&devr->c0->usecnt, 0);
4910
e39afe3d
LR		 4911 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4912 if (ret)
4913 goto err_create_cq;
4914
ff23dfa1 4915 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4916 if (IS_ERR(devr->x0)) {
4917 ret = PTR_ERR(devr->x0);
4918 goto error2;
4919 }
4920 devr->x0->device = &dev->ib_dev;
4921 devr->x0->inode = NULL;
4922 atomic_set(&devr->x0->usecnt, 0);
4923 mutex_init(&devr->x0->tgt_qp_mutex);
4924 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4925
ff23dfa1 4926 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4927 if (IS_ERR(devr->x1)) {
4928 ret = PTR_ERR(devr->x1);
4929 goto error3;
4930 }
4931 devr->x1->device = &dev->ib_dev;
4932 devr->x1->inode = NULL;
4933 atomic_set(&devr->x1->usecnt, 0);
4934 mutex_init(&devr->x1->tgt_qp_mutex);
4935 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4936
4937 memset(&attr, 0, sizeof(attr));
4938 attr.attr.max_sge = 1;
4939 attr.attr.max_wr = 1;
4940 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4941 attr.ext.cq = devr->c0;
e126ba97
EC		 4942 attr.ext.xrc.xrcd = devr->x0;
4943
68e326de
LR		 4944 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4945 if (!devr->s0) {
4946 ret = -ENOMEM;
e126ba97
EC		 4947 goto error4;
4948 }
68e326de 4949
e126ba97
EC		 4950 devr->s0->device = &dev->ib_dev;
4951 devr->s0->pd = devr->p0;
e126ba97
EC		 4952 devr->s0->srq_type = IB_SRQT_XRC;
4953 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4954 devr->s0->ext.cq = devr->c0;
68e326de
LR		 4955 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
4956 if (ret)
4957 goto err_create;
4958
e126ba97 4959 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4960 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4961 atomic_inc(&devr->p0->usecnt);
4962 atomic_set(&devr->s0->usecnt, 0);
4963
4aa17b28
HA		 4964 memset(&attr, 0, sizeof(attr));
4965 attr.attr.max_sge = 1;
4966 attr.attr.max_wr = 1;
4967 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 4968 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4969 if (!devr->s1) {
4970 ret = -ENOMEM;
4aa17b28
HA		 4971 goto error5;
4972 }
68e326de 4973
4aa17b28
HA		 4974 devr->s1->device = &dev->ib_dev;
4975 devr->s1->pd = devr->p0;
4aa17b28 4976 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4977 devr->s1->ext.cq = devr->c0;
68e326de
LR		 4978
4979 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
4980 if (ret)
4981 goto error6;
4982
4aa17b28 4983 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4984 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4985
7722f47e
HE		 4986 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4987 INIT_WORK(&devr->ports[port].pkey_change_work,
4988 pkey_change_handler);
4989 devr->ports[port].devr = devr;
4990 }
4991
e126ba97
EC		 4992 return 0;
4993
68e326de
LR		 4994error6:
4995 kfree(devr->s1);
4aa17b28 4996error5:
c4367a26 4997 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 4998err_create:
4999 kfree(devr->s0);
e126ba97 5000error4:
c4367a26 5001 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5002error3:
c4367a26 5003 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5004error2:
c4367a26 5005 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5006err_create_cq:
5007 kfree(devr->c0);
e126ba97 5008error1:
c4367a26 5009 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5010error0:
21a428a0 5011 kfree(devr->p0);
e126ba97
EC		 5012 return ret;
5013}
5014
5015static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5016{
7722f47e
HE		 5017 int port;
5018
c4367a26 5019 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5020 kfree(devr->s1);
c4367a26 5021 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5022 kfree(devr->s0);
c4367a26
SR		 5023 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5024 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5025 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5026 kfree(devr->c0);
c4367a26 5027 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5028 kfree(devr->p0);
7722f47e
HE		 5029
5030 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5031 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5032 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5033}
5034
b02289b3
AK		 5035static u32 get_core_cap_flags(struct ib_device *ibdev,
5036 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5037{
5038 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5039 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5040 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5041 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5042 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5043 u32 ret = 0;
5044
b02289b3
AK		 5045 if (rep->grh_required)
5046 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5047
e53505a8 5048 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5049 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5050
85c7c014 5051 if (raw_support)
b02289b3 5052 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5053
e53505a8 5054 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5055 return ret;
e53505a8
AS		 5056
5057 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5058 return ret;
e53505a8
AS		 5059
5060 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5061 ret |= RDMA_CORE_PORT_IBA_ROCE;
5062
5063 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5064 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5065
5066 return ret;
5067}
5068
7738613e
IW		 5069static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5070 struct ib_port_immutable *immutable)
5071{
5072 struct ib_port_attr attr;
ca5b91d6
OG		 5073 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5074 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5075 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5076 int err;
5077
c4550c63 5078 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5079 if (err)
5080 return err;
5081
b02289b3
AK		 5082 if (ll == IB_LINK_LAYER_INFINIBAND) {
5083 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5084 &rep);
5085 if (err)
5086 return err;
5087 }
5088
7738613e
IW		 5089 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5090 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5091 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 5092 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5093 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5094
5095 return 0;
5096}
5097
8e6efa3a
MB		 5098static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5099 struct ib_port_immutable *immutable)
5100{
5101 struct ib_port_attr attr;
5102 int err;
5103
5104 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5105
5106 err = ib_query_port(ibdev, port_num, &attr);
5107 if (err)
5108 return err;
5109
5110 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5111 immutable->gid_tbl_len = attr.gid_tbl_len;
5112 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5113
5114 return 0;
5115}
5116
9abb0d1b 5117static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5118{
5119 struct mlx5_ib_dev *dev =
5120 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5121 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5122 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5123 fw_rev_sub(dev->mdev));
c7342823
IW		 5124}
5125
45f95acd 5126static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5127{
5128 struct mlx5_core_dev *mdev = dev->mdev;
5129 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5130 MLX5_FLOW_NAMESPACE_LAG);
5131 struct mlx5_flow_table *ft;
5132 int err;
5133
7c34ec19 5134 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5135 return 0;
5136
5137 err = mlx5_cmd_create_vport_lag(mdev);
5138 if (err)
5139 return err;
5140
5141 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5142 if (IS_ERR(ft)) {
5143 err = PTR_ERR(ft);
5144 goto err_destroy_vport_lag;
5145 }
5146
9a4ca38d 5147 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5148 dev->lag_active = true;
9ef9c640
AH		 5149 return 0;
5150
5151err_destroy_vport_lag:
5152 mlx5_cmd_destroy_vport_lag(mdev);
5153 return err;
5154}
5155
45f95acd 5156static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5157{
5158 struct mlx5_core_dev *mdev = dev->mdev;
5159
7c34ec19
AH		 5160 if (dev->lag_active) {
5161 dev->lag_active = false;
5162
9a4ca38d
MB		 5163 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5164 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5165
5166 mlx5_cmd_destroy_vport_lag(mdev);
5167 }
5168}
5169
7fd8aefb 5170static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5171{
5172 int err;
5173
95579e78
MB		 5174 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5175 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5176 if (err) {
95579e78 5177 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5178 return err;
5179 }
5180
5181 return 0;
5182}
5183
7fd8aefb 5184static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5185{
95579e78
MB		 5186 if (dev->port[port_num].roce.nb.notifier_call) {
5187 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5188 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5189 }
5190}
5191
e3f1ed1f 5192static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5193{
e53505a8
AS		 5194 int err;
5195
ca5b91d6
OG		 5196 if (MLX5_CAP_GEN(dev->mdev, roce)) {
5197 err = mlx5_nic_vport_enable_roce(dev->mdev);
5198 if (err)
8e6efa3a 5199 return err;
ca5b91d6 5200 }
e53505a8 5201
45f95acd 5202 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5203 if (err)
5204 goto err_disable_roce;
5205
e53505a8
AS		 5206 return 0;
5207
9ef9c640 5208err_disable_roce:
ca5b91d6
OG		 5209 if (MLX5_CAP_GEN(dev->mdev, roce))
5210 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5211
e53505a8 5212 return err;
fc24fc5e
AS		 5213}
5214
45f95acd 5215static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5216{
45f95acd 5217 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 5218 if (MLX5_CAP_GEN(dev->mdev, roce))
5219 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5220}
5221
e1f24a79 5222struct mlx5_ib_counter {
7c16f477
KH		 5223 const char *name;
5224 size_t offset;
5225};
5226
5227#define INIT_Q_COUNTER(_name) \
5228 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5229
e1f24a79 5230static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5231 INIT_Q_COUNTER(rx_write_requests),
5232 INIT_Q_COUNTER(rx_read_requests),
5233 INIT_Q_COUNTER(rx_atomic_requests),
5234 INIT_Q_COUNTER(out_of_buffer),
5235};
5236
e1f24a79 5237static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5238 INIT_Q_COUNTER(out_of_sequence),
5239};
5240
e1f24a79 5241static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5242 INIT_Q_COUNTER(duplicate_request),
5243 INIT_Q_COUNTER(rnr_nak_retry_err),
5244 INIT_Q_COUNTER(packet_seq_err),
5245 INIT_Q_COUNTER(implied_nak_seq_err),
5246 INIT_Q_COUNTER(local_ack_timeout_err),
5247};
5248
e1f24a79
PP		 5249#define INIT_CONG_COUNTER(_name) \
5250 { .name = #_name, .offset = \
5251 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5252
5253static const struct mlx5_ib_counter cong_cnts[] = {
5254 INIT_CONG_COUNTER(rp_cnp_ignored),
5255 INIT_CONG_COUNTER(rp_cnp_handled),
5256 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5257 INIT_CONG_COUNTER(np_cnp_sent),
5258};
5259
58dcb60a
PP		 5260static const struct mlx5_ib_counter extended_err_cnts[] = {
5261 INIT_Q_COUNTER(resp_local_length_error),
5262 INIT_Q_COUNTER(resp_cqe_error),
5263 INIT_Q_COUNTER(req_cqe_error),
5264 INIT_Q_COUNTER(req_remote_invalid_request),
5265 INIT_Q_COUNTER(req_remote_access_errors),
5266 INIT_Q_COUNTER(resp_remote_access_errors),
5267 INIT_Q_COUNTER(resp_cqe_flush_error),
5268 INIT_Q_COUNTER(req_cqe_flush_error),
5269};
5270
9f876f3d
TB		 5271#define INIT_EXT_PPCNT_COUNTER(_name) \
5272 { .name = #_name, .offset = \
5273 MLX5_BYTE_OFF(ppcnt_reg, \
5274 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5275
5276static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5277 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5278};
5279
e1f24a79 5280static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5281{
aac4492e 5282 int i;
0837e86a 5283
7c16f477 5284 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 5285 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5286 mlx5_core_dealloc_q_counter(dev->mdev,
5287 dev->port[i].cnts.set_id);
e1f24a79
PP		 5288 kfree(dev->port[i].cnts.names);
5289 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5290 }
5291}
5292
e1f24a79
PP		 5293static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5294 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5295{
5296 u32 num_counters;
5297
5298 num_counters = ARRAY_SIZE(basic_q_cnts);
5299
5300 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5301 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5302
5303 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5304 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5305
5306 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5307 num_counters += ARRAY_SIZE(extended_err_cnts);
5308
e1f24a79 5309 cnts->num_q_counters = num_counters;
7c16f477 5310
e1f24a79
PP		 5311 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5312 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5313 num_counters += ARRAY_SIZE(cong_cnts);
5314 }
9f876f3d
TB		 5315 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5316 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5317 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5318 }
e1f24a79
PP		 5319 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5320 if (!cnts->names)
7c16f477
KH		 5321 return -ENOMEM;
5322
e1f24a79
PP		 5323 cnts->offsets = kcalloc(num_counters,
5324 sizeof(cnts->offsets), GFP_KERNEL);
5325 if (!cnts->offsets)
7c16f477
KH		 5326 goto err_names;
5327
7c16f477
KH		 5328 return 0;
5329
5330err_names:
e1f24a79 5331 kfree(cnts->names);
aac4492e 5332 cnts->names = NULL;
7c16f477
KH		 5333 return -ENOMEM;
5334}
5335
e1f24a79
PP		 5336static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5337 const char **names,
5338 size_t *offsets)
7c16f477
KH		 5339{
5340 int i;
5341 int j = 0;
5342
5343 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5344 names[j] = basic_q_cnts[i].name;
5345 offsets[j] = basic_q_cnts[i].offset;
5346 }
5347
5348 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5349 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5350 names[j] = out_of_seq_q_cnts[i].name;
5351 offsets[j] = out_of_seq_q_cnts[i].offset;
5352 }
5353 }
5354
5355 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5356 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5357 names[j] = retrans_q_cnts[i].name;
5358 offsets[j] = retrans_q_cnts[i].offset;
5359 }
5360 }
e1f24a79 5361
58dcb60a
PP		 5362 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5363 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5364 names[j] = extended_err_cnts[i].name;
5365 offsets[j] = extended_err_cnts[i].offset;
5366 }
5367 }
5368
e1f24a79
PP		 5369 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5370 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5371 names[j] = cong_cnts[i].name;
5372 offsets[j] = cong_cnts[i].offset;
5373 }
5374 }
9f876f3d
TB		 5375
5376 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5377 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5378 names[j] = ext_ppcnt_cnts[i].name;
5379 offsets[j] = ext_ppcnt_cnts[i].offset;
5380 }
5381 }
0837e86a
MB		 5382}
5383
e1f24a79 5384static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5385{
aac4492e 5386 int err = 0;
0837e86a 5387 int i;
aa74be6e
YH		 5388 bool is_shared;
5389
5390 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
0837e86a
MB		 5391
5392 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5393 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5394 if (err)
5395 goto err_alloc;
5396
5397 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5398 dev->port[i].cnts.offsets);
7c16f477 5399
aa74be6e
YH		 5400 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5401 &dev->port[i].cnts.set_id,
5402 is_shared ?
5403 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5404 if (err) {
0837e86a
MB		 5405 mlx5_ib_warn(dev,
5406 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5407 i + 1, err);
5408 goto err_alloc;
0837e86a 5409 }
aac4492e 5410 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5411 }
5412
5413 return 0;
5414
aac4492e
DJ		 5415err_alloc:
5416 mlx5_ib_dealloc_counters(dev);
5417 return err;
0837e86a
MB		 5418}
5419
0ad17a8f
MB		 5420static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5421 u8 port_num)
5422{
7c16f477
KH		 5423 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5424 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 5425
5426 /* We support only per port stats */
5427 if (port_num == 0)
5428 return NULL;
5429
e1f24a79
PP		 5430 return rdma_alloc_hw_stats_struct(port->cnts.names,
5431 port->cnts.num_q_counters +
9f876f3d
TB		 5432 port->cnts.num_cong_counters +
5433 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 5434 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5435}
5436
aac4492e 5437static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 5438 struct mlx5_ib_port *port,
5439 struct rdma_hw_stats *stats)
0ad17a8f 5440{
0ad17a8f
MB		 5441 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5442 void *out;
5443 __be32 val;
e1f24a79 5444 int ret, i;
0ad17a8f 5445
1b9a07ee 5446 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5447 if (!out)
5448 return -ENOMEM;
5449
aac4492e 5450 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 5451 port->cnts.set_id, 0,
0ad17a8f
MB		 5452 out, outlen);
5453 if (ret)
5454 goto free;
5455
e1f24a79
PP		 5456 for (i = 0; i < port->cnts.num_q_counters; i++) {
5457 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 5458 stats->value[i] = (u64)be32_to_cpu(val);
5459 }
7c16f477 5460
0ad17a8f
MB		 5461free:
5462 kvfree(out);
e1f24a79
PP		 5463 return ret;
5464}
5465
9f876f3d
TB		 5466static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5467 struct mlx5_ib_port *port,
5468 struct rdma_hw_stats *stats)
5469{
5470 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5471 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5472 int ret, i;
5473 void *out;
5474
5475 out = kvzalloc(sz, GFP_KERNEL);
5476 if (!out)
5477 return -ENOMEM;
5478
5479 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5480 if (ret)
5481 goto free;
5482
5483 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5484 stats->value[i + offset] =
5485 be64_to_cpup((__be64 *)(out +
5486 port->cnts.offsets[i + offset]));
5487 }
5488
5489free:
5490 kvfree(out);
5491 return ret;
5492}
5493
e1f24a79
PP		 5494static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5495 struct rdma_hw_stats *stats,
5496 u8 port_num, int index)
5497{
5498 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5499 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 5500 struct mlx5_core_dev *mdev;
e1f24a79 5501 int ret, num_counters;
aac4492e 5502 u8 mdev_port_num;
e1f24a79
PP		 5503
5504 if (!stats)
5505 return -EINVAL;
5506
9f876f3d
TB		 5507 num_counters = port->cnts.num_q_counters +
5508 port->cnts.num_cong_counters +
5509 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 5510
5511 /* q_counters are per IB device, query the master mdev */
5512 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 5513 if (ret)
5514 return ret;
e1f24a79 5515
9f876f3d
TB		 5516 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5517 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5518 if (ret)
5519 return ret;
5520 }
5521
e1f24a79 5522 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5523 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5524 &mdev_port_num);
5525 if (!mdev) {
5526 /* If port is not affiliated yet, its in down state
5527 * which doesn't have any counters yet, so it would be
5528 * zero. So no need to read from the HCA.
5529 */
5530 goto done;
5531 }
71a0ff65
MD		 5532 ret = mlx5_lag_query_cong_counters(dev->mdev,
5533 stats->value +
5534 port->cnts.num_q_counters,
5535 port->cnts.num_cong_counters,
5536 port->cnts.offsets +
5537 port->cnts.num_q_counters);
aac4492e
DJ		 5538
5539 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5540 if (ret)
5541 return ret;
e1f24a79
PP		 5542 }
5543
aac4492e 5544done:
e1f24a79 5545 return num_counters;
0ad17a8f
MB		 5546}
5547
f6a8a19b
DD		 5548static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5549 enum rdma_netdev_t type,
5550 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5551{
5552 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5553 return -EOPNOTSUPP;
693dfd5a 5554
f6a8a19b 5555 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5556}
5557
fe248c3a
MG		 5558static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5559{
5560 if (!dev->delay_drop.dbg)
5561 return;
5562 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5563 kfree(dev->delay_drop.dbg);
5564 dev->delay_drop.dbg = NULL;
5565}
5566
03404e8a
MG		 5567static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5568{
5569 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5570 return;
5571
5572 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5573 delay_drop_debugfs_cleanup(dev);
5574}
5575
5576static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5577 size_t count, loff_t *pos)
5578{
5579 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5580 char lbuf[20];
5581 int len;
5582
5583 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5584 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5585}
5586
5587static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5588 size_t count, loff_t *pos)
5589{
5590 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5591 u32 timeout;
5592 u32 var;
5593
5594 if (kstrtouint_from_user(buf, count, 0, &var))
5595 return -EFAULT;
5596
5597 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5598 1000);
5599 if (timeout != var)
5600 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5601 timeout);
5602
5603 delay_drop->timeout = timeout;
5604
5605 return count;
5606}
5607
5608static const struct file_operations fops_delay_drop_timeout = {
5609 .owner = THIS_MODULE,
5610 .open = simple_open,
5611 .write = delay_drop_timeout_write,
5612 .read = delay_drop_timeout_read,
5613};
5614
5615static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5616{
5617 struct mlx5_ib_dbg_delay_drop *dbg;
5618
5619 if (!mlx5_debugfs_root)
5620 return 0;
5621
5622 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5623 if (!dbg)
5624 return -ENOMEM;
5625
cbafad87
SM		 5626 dev->delay_drop.dbg = dbg;
5627
fe248c3a
MG		 5628 dbg->dir_debugfs =
5629 debugfs_create_dir("delay_drop",
5630 dev->mdev->priv.dbg_root);
5631 if (!dbg->dir_debugfs)
cbafad87 5632 goto out_debugfs;
fe248c3a
MG		 5633
5634 dbg->events_cnt_debugfs =
5635 debugfs_create_atomic_t("num_timeout_events", 0400,
5636 dbg->dir_debugfs,
5637 &dev->delay_drop.events_cnt);
5638 if (!dbg->events_cnt_debugfs)
5639 goto out_debugfs;
5640
5641 dbg->rqs_cnt_debugfs =
5642 debugfs_create_atomic_t("num_rqs", 0400,
5643 dbg->dir_debugfs,
5644 &dev->delay_drop.rqs_cnt);
5645 if (!dbg->rqs_cnt_debugfs)
5646 goto out_debugfs;
5647
5648 dbg->timeout_debugfs =
5649 debugfs_create_file("timeout", 0600,
5650 dbg->dir_debugfs,
5651 &dev->delay_drop,
5652 &fops_delay_drop_timeout);
5653 if (!dbg->timeout_debugfs)
5654 goto out_debugfs;
5655
5656 return 0;
5657
5658out_debugfs:
5659 delay_drop_debugfs_cleanup(dev);
5660 return -ENOMEM;
03404e8a
MG		 5661}
5662
5663static void init_delay_drop(struct mlx5_ib_dev *dev)
5664{
5665 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5666 return;
5667
5668 mutex_init(&dev->delay_drop.lock);
5669 dev->delay_drop.dev = dev;
5670 dev->delay_drop.activate = false;
5671 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5672 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5673 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5674 atomic_set(&dev->delay_drop.events_cnt, 0);
5675
5676 if (delay_drop_debugfs_init(dev))
5677 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5678}
5679
32f69e4b
DJ		 5680/* The mlx5_ib_multiport_mutex should be held when calling this function */
5681static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5682 struct mlx5_ib_multiport_info *mpi)
5683{
5684 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5685 struct mlx5_ib_port *port = &ibdev->port[port_num];
5686 int comps;
5687 int err;
5688 int i;
5689
a9e546e7
PP		 5690 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5691
32f69e4b
DJ		 5692 spin_lock(&port->mp.mpi_lock);
5693 if (!mpi->ibdev) {
5694 spin_unlock(&port->mp.mpi_lock);
5695 return;
5696 }
df097a27
SM		 5697
5698 if (mpi->mdev_events.notifier_call)
5699 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5700 mpi->mdev_events.notifier_call = NULL;
5701
32f69e4b
DJ		 5702 mpi->ibdev = NULL;
5703
5704 spin_unlock(&port->mp.mpi_lock);
5705 mlx5_remove_netdev_notifier(ibdev, port_num);
5706 spin_lock(&port->mp.mpi_lock);
5707
5708 comps = mpi->mdev_refcnt;
5709 if (comps) {
5710 mpi->unaffiliate = true;
5711 init_completion(&mpi->unref_comp);
5712 spin_unlock(&port->mp.mpi_lock);
5713
5714 for (i = 0; i < comps; i++)
5715 wait_for_completion(&mpi->unref_comp);
5716
5717 spin_lock(&port->mp.mpi_lock);
5718 mpi->unaffiliate = false;
5719 }
5720
5721 port->mp.mpi = NULL;
5722
5723 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5724
5725 spin_unlock(&port->mp.mpi_lock);
5726
5727 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5728
5729 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5730 /* Log an error, still needed to cleanup the pointers and add
5731 * it back to the list.
5732 */
5733 if (err)
5734 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5735 port_num + 1);
5736
95579e78 5737 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5738}
5739
5740/* The mlx5_ib_multiport_mutex should be held when calling this function */
5741static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5742 struct mlx5_ib_multiport_info *mpi)
5743{
5744 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5745 int err;
5746
5747 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5748 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5749 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5750 port_num + 1);
32f69e4b
DJ		 5751 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5752 return false;
5753 }
5754
5755 ibdev->port[port_num].mp.mpi = mpi;
5756 mpi->ibdev = ibdev;
df097a27 5757 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5758 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5759
5760 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5761 if (err)
5762 goto unbind;
5763
5764 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5765 if (err)
5766 goto unbind;
5767
5768 err = mlx5_add_netdev_notifier(ibdev, port_num);
5769 if (err) {
5770 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5771 port_num + 1);
5772 goto unbind;
5773 }
5774
df097a27
SM		 5775 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5776 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5777
73eb8f03 5778 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5779
32f69e4b
DJ		 5780 return true;
5781
5782unbind:
5783 mlx5_ib_unbind_slave_port(ibdev, mpi);
5784 return false;
5785}
5786
5787static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5788{
5789 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5790 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5791 port_num + 1);
5792 struct mlx5_ib_multiport_info *mpi;
5793 int err;
5794 int i;
5795
5796 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5797 return 0;
5798
5799 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5800 &dev->sys_image_guid);
5801 if (err)
5802 return err;
5803
5804 err = mlx5_nic_vport_enable_roce(dev->mdev);
5805 if (err)
5806 return err;
5807
5808 mutex_lock(&mlx5_ib_multiport_mutex);
5809 for (i = 0; i < dev->num_ports; i++) {
5810 bool bound = false;
5811
5812 /* build a stub multiport info struct for the native port. */
5813 if (i == port_num) {
5814 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5815 if (!mpi) {
5816 mutex_unlock(&mlx5_ib_multiport_mutex);
5817 mlx5_nic_vport_disable_roce(dev->mdev);
5818 return -ENOMEM;
5819 }
5820
5821 mpi->is_master = true;
5822 mpi->mdev = dev->mdev;
5823 mpi->sys_image_guid = dev->sys_image_guid;
5824 dev->port[i].mp.mpi = mpi;
5825 mpi->ibdev = dev;
5826 mpi = NULL;
5827 continue;
5828 }
5829
5830 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5831 list) {
5832 if (dev->sys_image_guid == mpi->sys_image_guid &&
5833 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5834 bound = mlx5_ib_bind_slave_port(dev, mpi);
5835 }
5836
5837 if (bound) {
c42260f1
VP		 5838 dev_dbg(mpi->mdev->device,
5839 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 5840 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5841 list_del(&mpi->list);
5842 break;
5843 }
5844 }
5845 if (!bound) {
5846 get_port_caps(dev, i + 1);
5847 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5848 i + 1);
5849 }
5850 }
5851
5852 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5853 mutex_unlock(&mlx5_ib_multiport_mutex);
5854 return err;
5855}
5856
5857static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5858{
5859 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5860 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5861 port_num + 1);
5862 int i;
5863
5864 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5865 return;
5866
5867 mutex_lock(&mlx5_ib_multiport_mutex);
5868 for (i = 0; i < dev->num_ports; i++) {
5869 if (dev->port[i].mp.mpi) {
5870 /* Destroy the native port stub */
5871 if (i == port_num) {
5872 kfree(dev->port[i].mp.mpi);
5873 dev->port[i].mp.mpi = NULL;
5874 } else {
5875 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5876 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5877 }
5878 }
5879 }
5880
5881 mlx5_ib_dbg(dev, "removing from devlist\n");
5882 list_del(&dev->ib_dev_list);
5883 mutex_unlock(&mlx5_ib_multiport_mutex);
5884
5885 mlx5_nic_vport_disable_roce(dev->mdev);
5886}
5887
9a119cd5
JG		 5888ADD_UVERBS_ATTRIBUTES_SIMPLE(
5889 mlx5_ib_dm,
5890 UVERBS_OBJECT_DM,
5891 UVERBS_METHOD_DM_ALLOC,
5892 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5893 UVERBS_ATTR_TYPE(u64),
83bb4442 5894 UA_MANDATORY),
9a119cd5
JG		 5895 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5896 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 5897 UA_OPTIONAL),
5898 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
5899 enum mlx5_ib_uapi_dm_type,
5900 UA_OPTIONAL));
9a119cd5
JG		 5901
5902ADD_UVERBS_ATTRIBUTES_SIMPLE(
5903 mlx5_ib_flow_action,
5904 UVERBS_OBJECT_FLOW_ACTION,
5905 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 5906 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5907 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 5908
0cbf432d
JG		 5909static const struct uapi_definition mlx5_ib_defs[] = {
5910#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 5911 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 5912 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
5913#endif
8c84660b 5914
0cbf432d
JG		 5915 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
5916 &mlx5_ib_flow_action),
5917 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
5918 {}
5919};
8c84660b 5920
1a1e03dc
RS		 5921static int mlx5_ib_read_counters(struct ib_counters *counters,
5922 struct ib_counters_read_attr *read_attr,
5923 struct uverbs_attr_bundle *attrs)
5924{
5925 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5926 struct mlx5_read_counters_attr mread_attr = {};
5927 struct mlx5_ib_flow_counters_desc *desc;
5928 int ret, i;
5929
5930 mutex_lock(&mcounters->mcntrs_mutex);
5931 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5932 ret = -EINVAL;
5933 goto err_bound;
5934 }
5935
5936 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5937 GFP_KERNEL);
5938 if (!mread_attr.out) {
5939 ret = -ENOMEM;
5940 goto err_bound;
5941 }
5942
5943 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5944 mread_attr.flags = read_attr->flags;
5945 ret = mcounters->read_counters(counters->device, &mread_attr);
5946 if (ret)
5947 goto err_read;
5948
5949 /* do the pass over the counters data array to assign according to the
5950 * descriptions and indexing pairs
5951 */
5952 desc = mcounters->counters_data;
5953 for (i = 0; i < mcounters->ncounters; i++)
5954 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5955
5956err_read:
5957 kfree(mread_attr.out);
5958err_bound:
5959 mutex_unlock(&mcounters->mcntrs_mutex);
5960 return ret;
5961}
5962
b29e2a13
RS		 5963static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5964{
5965 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5966
3b3233fb
RS		 5967 counters_clear_description(counters);
5968 if (mcounters->hw_cntrs_hndl)
5969 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5970 mcounters->hw_cntrs_hndl);
5971
b29e2a13
RS		 5972 kfree(mcounters);
5973
5974 return 0;
5975}
5976
5977static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5978 struct uverbs_attr_bundle *attrs)
5979{
5980 struct mlx5_ib_mcounters *mcounters;
5981
5982 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5983 if (!mcounters)
5984 return ERR_PTR(-ENOMEM);
5985
3b3233fb
RS		 5986 mutex_init(&mcounters->mcntrs_mutex);
5987
b29e2a13
RS		 5988 return &mcounters->ibcntrs;
5989}
5990
fb652d32 5991static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5992{
25c13324
AL		 5993 struct mlx5_core_dev *mdev = dev->mdev;
5994
32f69e4b 5995 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 5996 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 5997 srcu_barrier(&dev->mr_srcu);
13859d5d 5998 cleanup_srcu_struct(&dev->mr_srcu);
13859d5d 5999 }
4056b12e
AL		 6000
6001 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
25c13324
AL		 6002
6003 WARN_ON(dev->dm.steering_sw_icm_alloc_blocks &&
6004 !bitmap_empty(
6005 dev->dm.steering_sw_icm_alloc_blocks,
6006 BIT(MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size) -
6007 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6008
6009 kfree(dev->dm.steering_sw_icm_alloc_blocks);
6010
6011 WARN_ON(dev->dm.header_modify_sw_icm_alloc_blocks &&
6012 !bitmap_empty(dev->dm.header_modify_sw_icm_alloc_blocks,
6013 BIT(MLX5_CAP_DEV_MEM(
6014 mdev, log_header_modify_sw_icm_size) -
6015 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6016
6017 kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
16c1975f
MB		 6018}
6019
fb652d32 6020static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6021{
6022 struct mlx5_core_dev *mdev = dev->mdev;
25c13324
AL		 6023 u64 header_modify_icm_blocks = 0;
6024 u64 steering_icm_blocks = 0;
e126ba97 6025 int err;
32f69e4b 6026 int i;
e126ba97 6027
32f69e4b
DJ		 6028 for (i = 0; i < dev->num_ports; i++) {
6029 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6030 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6031 dev->port[i].roce.dev = dev;
6032 dev->port[i].roce.native_port_num = i + 1;
6033 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6034 }
6035
6036 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6037 if (err)
da796ccb 6038 return err;
e126ba97 6039
a989ea01
MB		 6040 err = set_has_smi_cap(dev);
6041 if (err)
6042 return err;
e126ba97 6043
32f69e4b 6044 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6045 for (i = 1; i <= dev->num_ports; i++) {
6046 err = get_port_caps(dev, i);
6047 if (err)
6048 break;
6049 }
6050 } else {
6051 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6052 }
6053 if (err)
6054 goto err_mp;
6055
1b5daf11
MD		 6056 if (mlx5_use_mad_ifc(dev))
6057 get_ext_port_caps(dev);
e126ba97 6058
e126ba97 6059 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6060 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6061 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6062 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6063 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6064
3cc297db
MB		 6065 mutex_init(&dev->cap_mask_mutex);
6066 INIT_LIST_HEAD(&dev->qp_list);
6067 spin_lock_init(&dev->reset_flow_resource_lock);
6068
25c13324
AL		 6069 if (MLX5_CAP_GEN_64(mdev, general_obj_types) &
6070 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) {
6071 if (MLX5_CAP64_DEV_MEM(mdev, steering_sw_icm_start_address)) {
6072 steering_icm_blocks =
6073 BIT(MLX5_CAP_DEV_MEM(mdev,
6074 log_steering_sw_icm_size) -
6075 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6076
6077 dev->dm.steering_sw_icm_alloc_blocks =
6078 kcalloc(BITS_TO_LONGS(steering_icm_blocks),
6079 sizeof(unsigned long), GFP_KERNEL);
6080 if (!dev->dm.steering_sw_icm_alloc_blocks)
6081 goto err_mp;
6082 }
6083
6084 if (MLX5_CAP64_DEV_MEM(mdev,
6085 header_modify_sw_icm_start_address)) {
6086 header_modify_icm_blocks = BIT(
6087 MLX5_CAP_DEV_MEM(
6088 mdev, log_header_modify_sw_icm_size) -
6089 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6090
6091 dev->dm.header_modify_sw_icm_alloc_blocks =
6092 kcalloc(BITS_TO_LONGS(header_modify_icm_blocks),
6093 sizeof(unsigned long), GFP_KERNEL);
6094 if (!dev->dm.header_modify_sw_icm_alloc_blocks)
6095 goto err_dm;
6096 }
6097 }
6098
3b113a1e
AL		 6099 spin_lock_init(&dev->dm.lock);
6100 dev->dm.dev = mdev;
24da0016 6101
13859d5d 6102 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
13859d5d 6103 err = init_srcu_struct(&dev->mr_srcu);
a6bc3875 6104 if (err)
25c13324 6105 goto err_dm;
623d1543 6106 }
3cc297db 6107
16c1975f 6108 return 0;
25c13324
AL		 6109
6110err_dm:
6111 kfree(dev->dm.steering_sw_icm_alloc_blocks);
6112 kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6113
32f69e4b
DJ		 6114err_mp:
6115 mlx5_ib_cleanup_multiport_master(dev);
16c1975f 6116
16c1975f
MB		 6117 return -ENOMEM;
6118}
6119
9a4ca38d
MB		 6120static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6121{
6122 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6123
6124 if (!dev->flow_db)
6125 return -ENOMEM;
6126
6127 mutex_init(&dev->flow_db->lock);
6128
6129 return 0;
6130}
6131
6132static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6133{
6134 kfree(dev->flow_db);
6135}
6136
96458233 6137static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6138 .owner = THIS_MODULE,
b9560a41 6139 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6140 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6141
96458233
KH		 6142 .add_gid = mlx5_ib_add_gid,
6143 .alloc_mr = mlx5_ib_alloc_mr,
6144 .alloc_pd = mlx5_ib_alloc_pd,
6145 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6146 .attach_mcast = mlx5_ib_mcg_attach,
6147 .check_mr_status = mlx5_ib_check_mr_status,
6148 .create_ah = mlx5_ib_create_ah,
6149 .create_counters = mlx5_ib_create_counters,
6150 .create_cq = mlx5_ib_create_cq,
6151 .create_flow = mlx5_ib_create_flow,
6152 .create_qp = mlx5_ib_create_qp,
6153 .create_srq = mlx5_ib_create_srq,
6154 .dealloc_pd = mlx5_ib_dealloc_pd,
6155 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6156 .del_gid = mlx5_ib_del_gid,
6157 .dereg_mr = mlx5_ib_dereg_mr,
6158 .destroy_ah = mlx5_ib_destroy_ah,
6159 .destroy_counters = mlx5_ib_destroy_counters,
6160 .destroy_cq = mlx5_ib_destroy_cq,
6161 .destroy_flow = mlx5_ib_destroy_flow,
6162 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6163 .destroy_qp = mlx5_ib_destroy_qp,
6164 .destroy_srq = mlx5_ib_destroy_srq,
6165 .detach_mcast = mlx5_ib_mcg_detach,
6166 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6167 .drain_rq = mlx5_ib_drain_rq,
6168 .drain_sq = mlx5_ib_drain_sq,
6169 .get_dev_fw_str = get_dev_fw_str,
6170 .get_dma_mr = mlx5_ib_get_dma_mr,
6171 .get_link_layer = mlx5_ib_port_link_layer,
6172 .map_mr_sg = mlx5_ib_map_mr_sg,
6173 .mmap = mlx5_ib_mmap,
6174 .modify_cq = mlx5_ib_modify_cq,
6175 .modify_device = mlx5_ib_modify_device,
6176 .modify_port = mlx5_ib_modify_port,
6177 .modify_qp = mlx5_ib_modify_qp,
6178 .modify_srq = mlx5_ib_modify_srq,
6179 .poll_cq = mlx5_ib_poll_cq,
6180 .post_recv = mlx5_ib_post_recv,
6181 .post_send = mlx5_ib_post_send,
6182 .post_srq_recv = mlx5_ib_post_srq_recv,
6183 .process_mad = mlx5_ib_process_mad,
6184 .query_ah = mlx5_ib_query_ah,
6185 .query_device = mlx5_ib_query_device,
6186 .query_gid = mlx5_ib_query_gid,
6187 .query_pkey = mlx5_ib_query_pkey,
6188 .query_qp = mlx5_ib_query_qp,
6189 .query_srq = mlx5_ib_query_srq,
6190 .read_counters = mlx5_ib_read_counters,
6191 .reg_user_mr = mlx5_ib_reg_user_mr,
6192 .req_notify_cq = mlx5_ib_arm_cq,
6193 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6194 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6195
6196 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6197 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6198 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6199 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6200 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6201};
6202
6203static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6204 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6205 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6206};
6207
6208static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6209 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6210};
6211
6212static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6213 .get_vf_config = mlx5_ib_get_vf_config,
6214 .get_vf_stats = mlx5_ib_get_vf_stats,
6215 .set_vf_guid = mlx5_ib_set_vf_guid,
6216 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6217};
6218
6219static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6220 .alloc_mw = mlx5_ib_alloc_mw,
6221 .dealloc_mw = mlx5_ib_dealloc_mw,
6222};
6223
6224static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6225 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6226 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6227};
6228
6229static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6230 .alloc_dm = mlx5_ib_alloc_dm,
6231 .dealloc_dm = mlx5_ib_dealloc_dm,
6232 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6233};
6234
fb652d32 6235static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6236{
6237 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6238 int err;
6239
e126ba97
EC		 6240 dev->ib_dev.uverbs_cmd_mask =
6241 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6242 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6243 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6244 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6245 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6246 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6247 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6248 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6249 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6250 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6251 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6252 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6253 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6254 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6255 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6256 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6257 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6258 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6259 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6260 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6261 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6262 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6263 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6264 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6265 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6266 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6267 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6268 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6269 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6270 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6271 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6272 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6273 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6274 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6275
f6a8a19b
DD		 6276 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6277 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6278 ib_set_device_ops(&dev->ib_dev,
6279 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6280
96458233
KH		 6281 if (mlx5_core_is_pf(mdev))
6282 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6283
6e8484c5
MG		 6284 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6285
d2370e0a 6286 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6287 dev->ib_dev.uverbs_cmd_mask |=
6288 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6289 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6290 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6291 }
6292
938fe83c 6293 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6294 dev->ib_dev.uverbs_cmd_mask |=
6295 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6296 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6297 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6298 }
6299
25c13324
AL		 6300 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6301 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6302 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6303 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6304
dfb631a1 6305 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6306 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6307 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6308 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6309
36e235c8
JG		 6310 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6311 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6312
e126ba97
EC		 6313 err = init_node_data(dev);
6314 if (err)
16c1975f 6315 return err;
e126ba97 6316
c8b89924 6317 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6318 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6319 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6320 mutex_init(&dev->lb.mutex);
c8b89924 6321
16c1975f
MB		 6322 return 0;
6323}
6324
96458233
KH		 6325static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6326 .get_port_immutable = mlx5_port_immutable,
6327 .query_port = mlx5_ib_query_port,
6328};
6329
8e6efa3a
MB		 6330static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6331{
96458233 6332 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6333 return 0;
6334}
6335
96458233
KH		 6336static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6337 .get_port_immutable = mlx5_port_rep_immutable,
6338 .query_port = mlx5_ib_rep_query_port,
6339};
6340
fb652d32 6341static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6342{
96458233 6343 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6344 return 0;
6345}
6346
96458233
KH		 6347static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6348 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6349 .create_wq = mlx5_ib_create_wq,
6350 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6351 .destroy_wq = mlx5_ib_destroy_wq,
6352 .get_netdev = mlx5_ib_get_netdev,
6353 .modify_wq = mlx5_ib_modify_wq,
6354};
6355
e3f1ed1f 6356static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6357{
e3f1ed1f 6358 u8 port_num;
8e6efa3a 6359
8e6efa3a
MB		 6360 dev->ib_dev.uverbs_ex_cmd_mask |=
6361 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6362 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6363 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6364 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6365 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6366 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6367
e3f1ed1f
LR		 6368 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6369
26628e2d 6370 /* Register only for native ports */
8e6efa3a
MB		 6371 return mlx5_add_netdev_notifier(dev, port_num);
6372}
6373
6374static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6375{
6376 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6377
6378 mlx5_remove_netdev_notifier(dev, port_num);
6379}
6380
fb652d32 6381static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6382{
6383 struct mlx5_core_dev *mdev = dev->mdev;
6384 enum rdma_link_layer ll;
6385 int port_type_cap;
6386 int err = 0;
8e6efa3a 6387
8e6efa3a
MB		 6388 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6389 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6390
6391 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6392 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6393
6394 return err;
6395}
6396
fb652d32 6397static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6398{
6399 mlx5_ib_stage_common_roce_cleanup(dev);
6400}
6401
16c1975f
MB		 6402static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6403{
6404 struct mlx5_core_dev *mdev = dev->mdev;
6405 enum rdma_link_layer ll;
6406 int port_type_cap;
6407 int err;
6408
6409 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6410 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6411
fc24fc5e 6412 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6413 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6414 if (err)
6415 return err;
7fd8aefb 6416
e3f1ed1f 6417 err = mlx5_enable_eth(dev);
fc24fc5e 6418 if (err)
8e6efa3a 6419 goto cleanup;
fc24fc5e
AS		 6420 }
6421
16c1975f 6422 return 0;
8e6efa3a
MB		 6423cleanup:
6424 mlx5_ib_stage_common_roce_cleanup(dev);
6425
6426 return err;
16c1975f 6427}
e126ba97 6428
16c1975f
MB		 6429static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6430{
6431 struct mlx5_core_dev *mdev = dev->mdev;
6432 enum rdma_link_layer ll;
6433 int port_type_cap;
e126ba97 6434
16c1975f
MB		 6435 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6436 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6437
6438 if (ll == IB_LINK_LAYER_ETHERNET) {
6439 mlx5_disable_eth(dev);
8e6efa3a 6440 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6441 }
16c1975f 6442}
6aec21f6 6443
fb652d32 6444static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6445{
6446 return create_dev_resources(&dev->devr);
6447}
6448
fb652d32 6449static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6450{
6451 destroy_dev_resources(&dev->devr);
6452}
6453
6454static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6455{
07321b3c
MB		 6456 mlx5_ib_internal_fill_odp_caps(dev);
6457
16c1975f
MB		 6458 return mlx5_ib_odp_init_one(dev);
6459}
4a2da0b8 6460
f3ffed0c 6461static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6462{
6463 mlx5_ib_odp_cleanup_one(dev);
6464}
6465
96458233
KH		 6466static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6467 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6468 .get_hw_stats = mlx5_ib_get_hw_stats,
6469};
6470
fb652d32 6471static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6472{
5e1e7612 6473 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6474 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6475
6476 return mlx5_ib_alloc_counters(dev);
6477 }
16c1975f
MB		 6478
6479 return 0;
6480}
6481
fb652d32 6482static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6483{
6484 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6485 mlx5_ib_dealloc_counters(dev);
6486}
6487
6488static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6489{
73eb8f03
GKH		 6490 mlx5_ib_init_cong_debugfs(dev,
6491 mlx5_core_native_port_num(dev->mdev) - 1);
6492 return 0;
16c1975f
MB		 6493}
6494
6495static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6496{
a9e546e7
PP		 6497 mlx5_ib_cleanup_cong_debugfs(dev,
6498 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6499}
6500
6501static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6502{
5fe9dec0 6503 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6504 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6505}
6506
6507static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6508{
6509 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6510}
6511
fb652d32 6512static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6513{
6514 int err;
5fe9dec0
EC		 6515
6516 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6517 if (err)
16c1975f 6518 return err;
5fe9dec0
EC		 6519
6520 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6521 if (err)
16c1975f 6522 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6523
16c1975f
MB		 6524 return err;
6525}
0837e86a 6526
fb652d32 6527static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6528{
6529 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6530 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6531}
e126ba97 6532
fb652d32 6533static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6534{
e349f858
JG		 6535 const char *name;
6536
508a523f 6537 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6538 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6539 name = "mlx5_%d";
6540 else
6541 name = "mlx5_bond_%d";
ea4baf7f 6542 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6543}
6544
fb652d32 6545static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6546{
42cea83f 6547 destroy_umrc_res(dev);
16c1975f
MB		 6548}
6549
fb652d32 6550static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6551{
42cea83f 6552 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6553}
6554
fb652d32 6555static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6556{
42cea83f 6557 return create_umr_res(dev);
16c1975f
MB		 6558}
6559
6560static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6561{
03404e8a
MG		 6562 init_delay_drop(dev);
6563
16c1975f
MB		 6564 return 0;
6565}
6566
6567static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6568{
6569 cancel_delay_drop(dev);
6570}
6571
df097a27
SM		 6572static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6573{
6574 dev->mdev_events.notifier_call = mlx5_ib_event;
6575 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6576 return 0;
6577}
6578
6579static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6580{
6581 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6582}
6583
81773ce5
LR		 6584static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6585{
6586 int uid;
6587
fb98153b 6588 uid = mlx5_ib_devx_create(dev, false);
81773ce5
LR		 6589 if (uid > 0)
6590 dev->devx_whitelist_uid = uid;
6591
6592 return 0;
6593}
6594static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6595{
6596 if (dev->devx_whitelist_uid)
6597 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6598}
6599
b5ca15ad
MB		 6600void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6601 const struct mlx5_ib_profile *profile,
6602 int stage)
16c1975f
MB		 6603{
6604 /* Number of stages to cleanup */
6605 while (stage) {
6606 stage--;
6607 if (profile->stage[stage].cleanup)
6608 profile->stage[stage].cleanup(dev);
6609 }
4a6dc855 6610
da796ccb 6611 kfree(dev->port);
4a6dc855 6612 ib_dealloc_device(&dev->ib_dev);
16c1975f 6613}
e126ba97 6614
b5ca15ad
MB		 6615void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6616 const struct mlx5_ib_profile *profile)
16c1975f 6617{
16c1975f
MB		 6618 int err;
6619 int i;
5fe9dec0 6620
16c1975f
MB		 6621 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6622 if (profile->stage[i].init) {
6623 err = profile->stage[i].init(dev);
6624 if (err)
6625 goto err_out;
6626 }
6627 }
0837e86a 6628
16c1975f
MB		 6629 dev->profile = profile;
6630 dev->ib_active = true;
6aec21f6 6631
16c1975f 6632 return dev;
e126ba97 6633
16c1975f
MB		 6634err_out:
6635 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6636
16c1975f
MB		 6637 return NULL;
6638}
0837e86a 6639
16c1975f
MB		 6640static const struct mlx5_ib_profile pf_profile = {
6641 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6642 mlx5_ib_stage_init_init,
6643 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6644 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6645 mlx5_ib_stage_flow_db_init,
6646 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6647 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6648 mlx5_ib_stage_caps_init,
6649 NULL),
8e6efa3a
MB		 6650 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6651 mlx5_ib_stage_non_default_cb,
6652 NULL),
16c1975f
MB		 6653 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6654 mlx5_ib_stage_roce_init,
6655 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6656 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6657 mlx5_init_srq_table,
6658 mlx5_cleanup_srq_table),
16c1975f
MB		 6659 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6660 mlx5_ib_stage_dev_res_init,
6661 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6662 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6663 mlx5_ib_stage_dev_notifier_init,
6664 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6665 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6666 mlx5_ib_stage_odp_init,
d5d284b8 6667 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6668 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6669 mlx5_ib_stage_counters_init,
6670 mlx5_ib_stage_counters_cleanup),
6671 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6672 mlx5_ib_stage_cong_debugfs_init,
6673 mlx5_ib_stage_cong_debugfs_cleanup),
6674 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6675 mlx5_ib_stage_uar_init,
6676 mlx5_ib_stage_uar_cleanup),
6677 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6678 mlx5_ib_stage_bfrag_init,
6679 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6680 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6681 NULL,
6682 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6683 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6684 mlx5_ib_stage_devx_init,
6685 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6686 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6687 mlx5_ib_stage_ib_reg_init,
6688 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6689 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6690 mlx5_ib_stage_post_ib_reg_umr_init,
6691 NULL),
16c1975f
MB		 6692 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6693 mlx5_ib_stage_delay_drop_init,
6694 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6695};
e126ba97 6696
f0666f1f 6697const struct mlx5_ib_profile uplink_rep_profile = {
b5ca15ad
MB		 6698 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6699 mlx5_ib_stage_init_init,
6700 mlx5_ib_stage_init_cleanup),
6701 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6702 mlx5_ib_stage_flow_db_init,
6703 mlx5_ib_stage_flow_db_cleanup),
6704 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6705 mlx5_ib_stage_caps_init,
6706 NULL),
6707 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6708 mlx5_ib_stage_rep_non_default_cb,
6709 NULL),
6710 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6711 mlx5_ib_stage_rep_roce_init,
6712 mlx5_ib_stage_rep_roce_cleanup),
f3da6577
LR		 6713 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6714 mlx5_init_srq_table,
6715 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6716 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6717 mlx5_ib_stage_dev_res_init,
6718 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6719 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6720 mlx5_ib_stage_dev_notifier_init,
6721 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6722 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6723 mlx5_ib_stage_counters_init,
6724 mlx5_ib_stage_counters_cleanup),
6725 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6726 mlx5_ib_stage_uar_init,
6727 mlx5_ib_stage_uar_cleanup),
6728 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6729 mlx5_ib_stage_bfrag_init,
6730 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6731 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6732 NULL,
6733 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 6734 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6735 mlx5_ib_stage_devx_init,
6736 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 6737 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6738 mlx5_ib_stage_ib_reg_init,
6739 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6740 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6741 mlx5_ib_stage_post_ib_reg_umr_init,
6742 NULL),
b5ca15ad
MB		 6743};
6744
e3f1ed1f 6745static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6746{
6747 struct mlx5_ib_multiport_info *mpi;
6748 struct mlx5_ib_dev *dev;
6749 bool bound = false;
6750 int err;
6751
6752 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6753 if (!mpi)
6754 return NULL;
6755
6756 mpi->mdev = mdev;
6757
6758 err = mlx5_query_nic_vport_system_image_guid(mdev,
6759 &mpi->sys_image_guid);
6760 if (err) {
6761 kfree(mpi);
6762 return NULL;
6763 }
6764
6765 mutex_lock(&mlx5_ib_multiport_mutex);
6766 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6767 if (dev->sys_image_guid == mpi->sys_image_guid)
6768 bound = mlx5_ib_bind_slave_port(dev, mpi);
6769
6770 if (bound) {
6771 rdma_roce_rescan_device(&dev->ib_dev);
6772 break;
6773 }
6774 }
6775
6776 if (!bound) {
6777 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 6778 dev_dbg(mdev->device,
6779 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6780 }
6781 mutex_unlock(&mlx5_ib_multiport_mutex);
6782
6783 return mpi;
6784}
6785
16c1975f
MB		 6786static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6787{
32f69e4b 6788 enum rdma_link_layer ll;
b5ca15ad 6789 struct mlx5_ib_dev *dev;
32f69e4b 6790 int port_type_cap;
da796ccb 6791 int num_ports;
32f69e4b 6792
b5ca15ad
MB		 6793 printk_once(KERN_INFO "%s", mlx5_version);
6794
f0666f1f
BW		 6795 if (MLX5_ESWITCH_MANAGER(mdev) &&
6796 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5fb58c9e
MB		 6797 if (!mlx5_core_mp_enabled(mdev))
6798 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 6799 return mdev;
6800 }
6801
32f69e4b
DJ		 6802 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6803 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6804
e3f1ed1f
LR		 6805 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6806 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6807
da796ccb
MB		 6808 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6809 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 6810 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 6811 if (!dev)
6812 return NULL;
da796ccb
MB		 6813 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6814 GFP_KERNEL);
6815 if (!dev->port) {
6816 ib_dealloc_device((struct ib_device *)dev);
6817 return NULL;
6818 }
b5ca15ad
MB		 6819
6820 dev->mdev = mdev;
da796ccb 6821 dev->num_ports = num_ports;
b5ca15ad 6822
b5ca15ad 6823 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6824}
6825
9603b61d 6826static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6827{
32f69e4b
DJ		 6828 struct mlx5_ib_multiport_info *mpi;
6829 struct mlx5_ib_dev *dev;
6830
f0666f1f
BW		 6831 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6832 mlx5_ib_unregister_vport_reps(mdev);
6833 return;
6834 }
6835
32f69e4b
DJ		 6836 if (mlx5_core_is_mp_slave(mdev)) {
6837 mpi = context;
6838 mutex_lock(&mlx5_ib_multiport_mutex);
6839 if (mpi->ibdev)
6840 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6841 list_del(&mpi->list);
6842 mutex_unlock(&mlx5_ib_multiport_mutex);
6843 return;
6844 }
6aec21f6 6845
32f69e4b 6846 dev = context;
f0666f1f 6847 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6848}
6849
9603b61d
JM		 6850static struct mlx5_interface mlx5_ib_interface = {
6851 .add = mlx5_ib_add,
6852 .remove = mlx5_ib_remove,
64613d94 6853 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6854};
6855
c44ef998
IL		 6856unsigned long mlx5_ib_get_xlt_emergency_page(void)
6857{
6858 mutex_lock(&xlt_emergency_page_mutex);
6859 return xlt_emergency_page;
6860}
6861
6862void mlx5_ib_put_xlt_emergency_page(void)
6863{
6864 mutex_unlock(&xlt_emergency_page_mutex);
6865}
6866
e126ba97
EC		 6867static int __init mlx5_ib_init(void)
6868{
6aec21f6
HE		 6869 int err;
6870
c44ef998
IL		 6871 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6872 if (!xlt_emergency_page)
6873 return -ENOMEM;
6874
6875 mutex_init(&xlt_emergency_page_mutex);
6876
d69a24e0 6877 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6878 if (!mlx5_ib_event_wq) {
6879 free_page(xlt_emergency_page);
d69a24e0 6880 return -ENOMEM;
c44ef998 6881 }
d69a24e0 6882
81713d37 6883 mlx5_ib_odp_init();
9603b61d 6884
6aec21f6 6885 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6886
6aec21f6 6887 return err;
e126ba97
EC		 6888}
6889
6890static void __exit mlx5_ib_cleanup(void)
6891{
9603b61d 6892 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6893 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6894 mutex_destroy(&xlt_emergency_page_mutex);
6895 free_page(xlt_emergency_page);
e126ba97
EC		 6896}
6897
6898module_init(mlx5_ib_init);
6899module_exit(mlx5_ib_cleanup);
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