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IB/mlx5: Support 128B CQE compression feature
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
7c2344c3 53#include <linux/list.h>
e126ba97
EC		 54#include <rdma/ib_smi.h>
55#include <rdma/ib_umem.h>
038d2ef8
MG		 56#include <linux/in.h>
57#include <linux/etherdevice.h>
58#include <linux/mlx5/fs.h>
78984898 59#include <linux/mlx5/vport.h>
e126ba97 60#include "mlx5_ib.h"
e1f24a79 61#include "cmd.h"
c85023e1 62#include <linux/mlx5/vport.h>
e126ba97
EC		 63
64#define DRIVER_NAME "mlx5_ib"
b359911d 65#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 66
67MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69MODULE_LICENSE("Dual BSD/GPL");
e126ba97 70
e126ba97
EC		 71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 73 DRIVER_VERSION "\n";
e126ba97 74
da7525d2
EBE		 75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
1b5daf11 79static enum rdma_link_layer
ebd61f68 80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 81{
ebd61f68 82 switch (port_type_cap) {
1b5daf11
MD		 83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
ebd61f68
AS		 92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
fd65f1b8
MS		 101static int get_port_state(struct ib_device *ibdev,
102 u8 port_num,
103 enum ib_port_state *state)
104{
105 struct ib_port_attr attr;
106 int ret;
107
108 memset(&attr, 0, sizeof(attr));
109 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
110 if (!ret)
111 *state = attr.state;
112 return ret;
113}
114
fc24fc5e
AS		 115static int mlx5_netdev_event(struct notifier_block *this,
116 unsigned long event, void *ptr)
117{
118 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
119 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
120 roce.nb);
121
5ec8c83e
AH		 122 switch (event) {
123 case NETDEV_REGISTER:
124 case NETDEV_UNREGISTER:
125 write_lock(&ibdev->roce.netdev_lock);
126 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
127 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
128 NULL : ndev;
129 write_unlock(&ibdev->roce.netdev_lock);
130 break;
fc24fc5e 131
fd65f1b8 132 case NETDEV_CHANGE:
5ec8c83e 133 case NETDEV_UP:
88621dfe
AH		 134 case NETDEV_DOWN: {
135 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
136 struct net_device *upper = NULL;
137
138 if (lag_ndev) {
139 upper = netdev_master_upper_dev_get(lag_ndev);
140 dev_put(lag_ndev);
141 }
142
143 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
144 && ibdev->ib_active) {
626bc02d 145 struct ib_event ibev = { };
fd65f1b8 146 enum ib_port_state port_state;
5ec8c83e 147
fd65f1b8
MS		 148 if (get_port_state(&ibdev->ib_dev, 1, &port_state))
149 return NOTIFY_DONE;
150
151 if (ibdev->roce.last_port_state == port_state)
152 return NOTIFY_DONE;
153
154 ibdev->roce.last_port_state = port_state;
5ec8c83e 155 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 156 if (port_state == IB_PORT_DOWN)
157 ibev.event = IB_EVENT_PORT_ERR;
158 else if (port_state == IB_PORT_ACTIVE)
159 ibev.event = IB_EVENT_PORT_ACTIVE;
160 else
161 return NOTIFY_DONE;
162
5ec8c83e
AH		 163 ibev.element.port_num = 1;
164 ib_dispatch_event(&ibev);
165 }
166 break;
88621dfe 167 }
fc24fc5e 168
5ec8c83e
AH		 169 default:
170 break;
171 }
fc24fc5e
AS		 172
173 return NOTIFY_DONE;
174}
175
176static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
177 u8 port_num)
178{
179 struct mlx5_ib_dev *ibdev = to_mdev(device);
180 struct net_device *ndev;
181
88621dfe
AH		 182 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
183 if (ndev)
184 return ndev;
185
fc24fc5e
AS		 186 /* Ensure ndev does not disappear before we invoke dev_hold()
187 */
188 read_lock(&ibdev->roce.netdev_lock);
189 ndev = ibdev->roce.netdev;
190 if (ndev)
191 dev_hold(ndev);
192 read_unlock(&ibdev->roce.netdev_lock);
193
194 return ndev;
195}
196
f1b65df5
NO		 197static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
198 u8 *active_width)
199{
200 switch (eth_proto_oper) {
201 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
202 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
203 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
204 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_SDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
209 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
210 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
211 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
212 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
213 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
214 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
215 *active_width = IB_WIDTH_1X;
216 *active_speed = IB_SPEED_QDR;
217 break;
218 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
219 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
220 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
221 *active_width = IB_WIDTH_1X;
222 *active_speed = IB_SPEED_EDR;
223 break;
224 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
225 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
226 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
227 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
228 *active_width = IB_WIDTH_4X;
229 *active_speed = IB_SPEED_QDR;
230 break;
231 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
232 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
233 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_HDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_FDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
242 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
243 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
244 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
245 *active_width = IB_WIDTH_4X;
246 *active_speed = IB_SPEED_EDR;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
095b0927
IT		 255static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
256 struct ib_port_attr *props)
3f89a643
AS		 257{
258 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 259 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 260 struct net_device *ndev, *upper;
3f89a643 261 enum ib_mtu ndev_ib_mtu;
c876a1b7 262 u16 qkey_viol_cntr;
f1b65df5 263 u32 eth_prot_oper;
095b0927 264 int err;
3f89a643 265
f1b65df5
NO		 266 /* Possible bad flows are checked before filling out props so in case
267 * of an error it will still be zeroed out.
50f22fd8 268 */
095b0927
IT		 269 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
270 if (err)
271 return err;
f1b65df5
NO		 272
273 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
274 &props->active_width);
3f89a643
AS		 275
276 props->port_cap_flags |= IB_PORT_CM_SUP;
277 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
278
279 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
280 roce_address_table_size);
281 props->max_mtu = IB_MTU_4096;
282 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
283 props->pkey_tbl_len = 1;
284 props->state = IB_PORT_DOWN;
285 props->phys_state = 3;
286
c876a1b7
LR		 287 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
288 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 289
290 ndev = mlx5_ib_get_netdev(device, port_num);
291 if (!ndev)
095b0927 292 return 0;
3f89a643 293
88621dfe
AH		 294 if (mlx5_lag_is_active(dev->mdev)) {
295 rcu_read_lock();
296 upper = netdev_master_upper_dev_get_rcu(ndev);
297 if (upper) {
298 dev_put(ndev);
299 ndev = upper;
300 dev_hold(ndev);
301 }
302 rcu_read_unlock();
303 }
304
3f89a643
AS		 305 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
306 props->state = IB_PORT_ACTIVE;
307 props->phys_state = 5;
308 }
309
310 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
311
312 dev_put(ndev);
313
314 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 315 return 0;
3f89a643
AS		 316}
317
095b0927
IT		 318static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
319 unsigned int index, const union ib_gid *gid,
320 const struct ib_gid_attr *attr)
3cca2606 321{
095b0927
IT		 322 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
323 u8 roce_version = 0;
324 u8 roce_l3_type = 0;
325 bool vlan = false;
326 u8 mac[ETH_ALEN];
327 u16 vlan_id = 0;
328
329 if (gid) {
330 gid_type = attr->gid_type;
331 ether_addr_copy(mac, attr->ndev->dev_addr);
332
333 if (is_vlan_dev(attr->ndev)) {
334 vlan = true;
335 vlan_id = vlan_dev_vlan_id(attr->ndev);
336 }
3cca2606
AS		 337 }
338
095b0927 339 switch (gid_type) {
3cca2606 340 case IB_GID_TYPE_IB:
095b0927 341 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 342 break;
343 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 344 roce_version = MLX5_ROCE_VERSION_2;
345 if (ipv6_addr_v4mapped((void *)gid))
346 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
347 else
348 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 349 break;
350
351 default:
095b0927 352 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 353 }
354
095b0927
IT		 355 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
356 roce_l3_type, gid->raw, mac, vlan,
357 vlan_id);
3cca2606
AS		 358}
359
360static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
361 unsigned int index, const union ib_gid *gid,
362 const struct ib_gid_attr *attr,
363 __always_unused void **context)
364{
095b0927 365 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 366}
367
368static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
369 unsigned int index, __always_unused void **context)
370{
095b0927 371 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 372}
373
2811ba51
AS		 374__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
375 int index)
376{
377 struct ib_gid_attr attr;
378 union ib_gid gid;
379
380 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
381 return 0;
382
383 if (!attr.ndev)
384 return 0;
385
386 dev_put(attr.ndev);
387
388 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
389 return 0;
390
391 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
392}
393
ed88451e
MD		 394int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
395 int index, enum ib_gid_type *gid_type)
396{
397 struct ib_gid_attr attr;
398 union ib_gid gid;
399 int ret;
400
401 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
402 if (ret)
403 return ret;
404
405 if (!attr.ndev)
406 return -ENODEV;
407
408 dev_put(attr.ndev);
409
410 *gid_type = attr.gid_type;
411
412 return 0;
413}
414
1b5daf11
MD		 415static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
416{
7fae6655
NO		 417 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
418 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
419 return 0;
1b5daf11
MD		 420}
421
422enum {
423 MLX5_VPORT_ACCESS_METHOD_MAD,
424 MLX5_VPORT_ACCESS_METHOD_HCA,
425 MLX5_VPORT_ACCESS_METHOD_NIC,
426};
427
428static int mlx5_get_vport_access_method(struct ib_device *ibdev)
429{
430 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
431 return MLX5_VPORT_ACCESS_METHOD_MAD;
432
ebd61f68 433 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 434 IB_LINK_LAYER_ETHERNET)
435 return MLX5_VPORT_ACCESS_METHOD_NIC;
436
437 return MLX5_VPORT_ACCESS_METHOD_HCA;
438}
439
da7525d2
EBE		 440static void get_atomic_caps(struct mlx5_ib_dev *dev,
441 struct ib_device_attr *props)
442{
443 u8 tmp;
444 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
445 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
446 u8 atomic_req_8B_endianness_mode =
bd10838a 447 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 448
449 /* Check if HW supports 8 bytes standard atomic operations and capable
450 * of host endianness respond
451 */
452 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
453 if (((atomic_operations & tmp) == tmp) &&
454 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
455 (atomic_req_8B_endianness_mode)) {
456 props->atomic_cap = IB_ATOMIC_HCA;
457 } else {
458 props->atomic_cap = IB_ATOMIC_NONE;
459 }
460}
461
1b5daf11
MD		 462static int mlx5_query_system_image_guid(struct ib_device *ibdev,
463 __be64 *sys_image_guid)
464{
465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
466 struct mlx5_core_dev *mdev = dev->mdev;
467 u64 tmp;
468 int err;
469
470 switch (mlx5_get_vport_access_method(ibdev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_system_image_guid(ibdev,
473 sys_image_guid);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 477 break;
478
479 case MLX5_VPORT_ACCESS_METHOD_NIC:
480 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
481 break;
1b5daf11
MD		 482
483 default:
484 return -EINVAL;
485 }
3f89a643
AS		 486
487 if (!err)
488 *sys_image_guid = cpu_to_be64(tmp);
489
490 return err;
491
1b5daf11
MD		 492}
493
494static int mlx5_query_max_pkeys(struct ib_device *ibdev,
495 u16 *max_pkeys)
496{
497 struct mlx5_ib_dev *dev = to_mdev(ibdev);
498 struct mlx5_core_dev *mdev = dev->mdev;
499
500 switch (mlx5_get_vport_access_method(ibdev)) {
501 case MLX5_VPORT_ACCESS_METHOD_MAD:
502 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
503
504 case MLX5_VPORT_ACCESS_METHOD_HCA:
505 case MLX5_VPORT_ACCESS_METHOD_NIC:
506 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
507 pkey_table_size));
508 return 0;
509
510 default:
511 return -EINVAL;
512 }
513}
514
515static int mlx5_query_vendor_id(struct ib_device *ibdev,
516 u32 *vendor_id)
517{
518 struct mlx5_ib_dev *dev = to_mdev(ibdev);
519
520 switch (mlx5_get_vport_access_method(ibdev)) {
521 case MLX5_VPORT_ACCESS_METHOD_MAD:
522 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
523
524 case MLX5_VPORT_ACCESS_METHOD_HCA:
525 case MLX5_VPORT_ACCESS_METHOD_NIC:
526 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
527
528 default:
529 return -EINVAL;
530 }
531}
532
533static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
534 __be64 *node_guid)
535{
536 u64 tmp;
537 int err;
538
539 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
540 case MLX5_VPORT_ACCESS_METHOD_MAD:
541 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
542
543 case MLX5_VPORT_ACCESS_METHOD_HCA:
544 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 545 break;
546
547 case MLX5_VPORT_ACCESS_METHOD_NIC:
548 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
549 break;
1b5daf11
MD		 550
551 default:
552 return -EINVAL;
553 }
3f89a643
AS		 554
555 if (!err)
556 *node_guid = cpu_to_be64(tmp);
557
558 return err;
1b5daf11
MD		 559}
560
561struct mlx5_reg_node_desc {
bd99fdea 562 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 563};
564
565static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
566{
567 struct mlx5_reg_node_desc in;
568
569 if (mlx5_use_mad_ifc(dev))
570 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
571
572 memset(&in, 0, sizeof(in));
573
574 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
575 sizeof(struct mlx5_reg_node_desc),
576 MLX5_REG_NODE_DESC, 0, 0);
577}
578
e126ba97 579static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 580 struct ib_device_attr *props,
581 struct ib_udata *uhw)
e126ba97
EC		 582{
583 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 584 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 585 int err = -ENOMEM;
288c01b7 586 int max_sq_desc;
e126ba97
EC		 587 int max_rq_sg;
588 int max_sq_sg;
e0238a6a 589 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 590 struct mlx5_ib_query_device_resp resp = {};
591 size_t resp_len;
592 u64 max_tso;
e126ba97 593
402ca536
BW		 594 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
595 if (uhw->outlen && uhw->outlen < resp_len)
596 return -EINVAL;
597 else
598 resp.response_length = resp_len;
599
600 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 601 return -EINVAL;
602
1b5daf11
MD		 603 memset(props, 0, sizeof(*props));
604 err = mlx5_query_system_image_guid(ibdev,
605 &props->sys_image_guid);
606 if (err)
607 return err;
e126ba97 608
1b5daf11 609 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 610 if (err)
1b5daf11 611 return err;
e126ba97 612
1b5daf11
MD		 613 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
614 if (err)
615 return err;
e126ba97 616
9603b61d
JM		 617 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
618 (fw_rev_min(dev->mdev) << 16) |
619 fw_rev_sub(dev->mdev);
e126ba97
EC		 620 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
621 IB_DEVICE_PORT_ACTIVE_EVENT |
622 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 623 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 624
625 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 626 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 627 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 628 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 629 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 630 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 631 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 632 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 633 if (MLX5_CAP_GEN(mdev, imaicl)) {
634 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
635 IB_DEVICE_MEM_WINDOW_TYPE_2B;
636 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 637 /* We support 'Gappy' memory registration too */
638 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 639 }
e126ba97 640 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 641 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 642 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
643 /* At this stage no support for signature handover */
644 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
645 IB_PROT_T10DIF_TYPE_2 |
646 IB_PROT_T10DIF_TYPE_3;
647 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
648 IB_GUARD_T10DIF_CSUM;
649 }
938fe83c 650 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 651 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 652
402ca536 653 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 654 if (MLX5_CAP_ETH(mdev, csum_cap)) {
655 /* Legacy bit to support old userspace libraries */
88115fe7 656 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 657 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
658 }
659
660 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
661 props->raw_packet_caps |=
662 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 663
402ca536
BW		 664 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
665 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
666 if (max_tso) {
667 resp.tso_caps.max_tso = 1 << max_tso;
668 resp.tso_caps.supported_qpts |=
669 1 << IB_QPT_RAW_PACKET;
670 resp.response_length += sizeof(resp.tso_caps);
671 }
672 }
31f69a82
YH		 673
674 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
675 resp.rss_caps.rx_hash_function =
676 MLX5_RX_HASH_FUNC_TOEPLITZ;
677 resp.rss_caps.rx_hash_fields_mask =
678 MLX5_RX_HASH_SRC_IPV4 |
679 MLX5_RX_HASH_DST_IPV4 |
680 MLX5_RX_HASH_SRC_IPV6 |
681 MLX5_RX_HASH_DST_IPV6 |
682 MLX5_RX_HASH_SRC_PORT_TCP |
683 MLX5_RX_HASH_DST_PORT_TCP |
684 MLX5_RX_HASH_SRC_PORT_UDP |
685 MLX5_RX_HASH_DST_PORT_UDP;
686 resp.response_length += sizeof(resp.rss_caps);
687 }
688 } else {
689 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
690 resp.response_length += sizeof(resp.tso_caps);
691 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
692 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 693 }
694
f0313965
ES		 695 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
696 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
697 props->device_cap_flags |= IB_DEVICE_UD_TSO;
698 }
699
03404e8a
MG		 700 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
701 MLX5_CAP_GEN(dev->mdev, general_notification_event))
702 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
703
1d54f890
YH		 704 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
705 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
706 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
707
cff5a0f3 708 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 709 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
710 /* Legacy bit to support old userspace libraries */
cff5a0f3 711 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 712 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
713 }
cff5a0f3 714
da6d6ba3
MG		 715 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
716 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
717
1b5daf11
MD		 718 props->vendor_part_id = mdev->pdev->device;
719 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 720
721 props->max_mr_size = ~0ull;
e0238a6a 722 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 723 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
724 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
725 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
726 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 727 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
728 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
729 sizeof(struct mlx5_wqe_raddr_seg)) /
730 sizeof(struct mlx5_wqe_data_seg);
e126ba97 731 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 732 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 733 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 734 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 735 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
736 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
737 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
738 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
739 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
740 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
741 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 742 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 743 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 744 props->max_fast_reg_page_list_len =
745 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 746 get_atomic_caps(dev, props);
81bea28f 747 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 748 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
749 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 750 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
751 props->max_mcast_grp;
752 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 753 props->max_ah = INT_MAX;
7c60bcbb
MB		 754 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
755 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 756
8cdd312c 757#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 758 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 759 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
760 props->odp_caps = dev->odp_caps;
761#endif
762
051f2630
LR		 763 if (MLX5_CAP_GEN(mdev, cd))
764 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
765
eff901d3
EC		 766 if (!mlx5_core_is_pf(mdev))
767 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
768
31f69a82
YH		 769 if (mlx5_ib_port_link_layer(ibdev, 1) ==
770 IB_LINK_LAYER_ETHERNET) {
771 props->rss_caps.max_rwq_indirection_tables =
772 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
773 props->rss_caps.max_rwq_indirection_table_size =
774 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
775 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
776 props->max_wq_type_rq =
777 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
778 }
779
eb761894 780 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 781 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
782 props->tm_caps.max_num_tags =
eb761894 783 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 784 props->tm_caps.flags = IB_TM_CAP_RC;
785 props->tm_caps.max_ops =
eb761894 786 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 787 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 788 }
789
7e43a2a5
BW		 790 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
791 resp.cqe_comp_caps.max_num =
792 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
793 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
794 resp.cqe_comp_caps.supported_format =
795 MLX5_IB_CQE_RES_FORMAT_HASH |
796 MLX5_IB_CQE_RES_FORMAT_CSUM;
797 resp.response_length += sizeof(resp.cqe_comp_caps);
798 }
799
d949167d
BW		 800 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
801 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
802 MLX5_CAP_GEN(mdev, qos)) {
803 resp.packet_pacing_caps.qp_rate_limit_max =
804 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
805 resp.packet_pacing_caps.qp_rate_limit_min =
806 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
807 resp.packet_pacing_caps.supported_qpts |=
808 1 << IB_QPT_RAW_PACKET;
809 }
810 resp.response_length += sizeof(resp.packet_pacing_caps);
811 }
812
9f885201
LR		 813 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
814 uhw->outlen)) {
795b609c
BW		 815 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
816 resp.mlx5_ib_support_multi_pkt_send_wqes =
817 MLX5_IB_ALLOW_MPW;
050da902
BW		 818
819 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
820 resp.mlx5_ib_support_multi_pkt_send_wqes |=
821 MLX5_IB_SUPPORT_EMPW;
822
9f885201
LR		 823 resp.response_length +=
824 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
825 }
826
de57f2ad
GL		 827 if (field_avail(typeof(resp), flags, uhw->outlen)) {
828 resp.response_length += sizeof(resp.flags);
829 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
830 resp.flags |=
831 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
832 }
9f885201 833
96dc3fc5
NO		 834 if (field_avail(typeof(resp), sw_parsing_caps,
835 uhw->outlen)) {
836 resp.response_length += sizeof(resp.sw_parsing_caps);
837 if (MLX5_CAP_ETH(mdev, swp)) {
838 resp.sw_parsing_caps.sw_parsing_offloads |=
839 MLX5_IB_SW_PARSING;
840
841 if (MLX5_CAP_ETH(mdev, swp_csum))
842 resp.sw_parsing_caps.sw_parsing_offloads |=
843 MLX5_IB_SW_PARSING_CSUM;
844
845 if (MLX5_CAP_ETH(mdev, swp_lso))
846 resp.sw_parsing_caps.sw_parsing_offloads |=
847 MLX5_IB_SW_PARSING_LSO;
848
849 if (resp.sw_parsing_caps.sw_parsing_offloads)
850 resp.sw_parsing_caps.supported_qpts =
851 BIT(IB_QPT_RAW_PACKET);
852 }
853 }
854
b4f34597
NO		 855 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
856 resp.response_length += sizeof(resp.striding_rq_caps);
857 if (MLX5_CAP_GEN(mdev, striding_rq)) {
858 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
859 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
860 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
861 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
862 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
863 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
864 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
865 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
866 resp.striding_rq_caps.supported_qpts =
867 BIT(IB_QPT_RAW_PACKET);
868 }
869 }
870
402ca536
BW		 871 if (uhw->outlen) {
872 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
873
874 if (err)
875 return err;
876 }
877
1b5daf11 878 return 0;
e126ba97
EC		 879}
880
1b5daf11
MD		 881enum mlx5_ib_width {
882 MLX5_IB_WIDTH_1X = 1 << 0,
883 MLX5_IB_WIDTH_2X = 1 << 1,
884 MLX5_IB_WIDTH_4X = 1 << 2,
885 MLX5_IB_WIDTH_8X = 1 << 3,
886 MLX5_IB_WIDTH_12X = 1 << 4
887};
888
889static int translate_active_width(struct ib_device *ibdev, u8 active_width,
890 u8 *ib_width)
e126ba97
EC		 891{
892 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 893 int err = 0;
894
895 if (active_width & MLX5_IB_WIDTH_1X) {
896 *ib_width = IB_WIDTH_1X;
897 } else if (active_width & MLX5_IB_WIDTH_2X) {
898 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
899 (int)active_width);
900 err = -EINVAL;
901 } else if (active_width & MLX5_IB_WIDTH_4X) {
902 *ib_width = IB_WIDTH_4X;
903 } else if (active_width & MLX5_IB_WIDTH_8X) {
904 *ib_width = IB_WIDTH_8X;
905 } else if (active_width & MLX5_IB_WIDTH_12X) {
906 *ib_width = IB_WIDTH_12X;
907 } else {
908 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
909 (int)active_width);
910 err = -EINVAL;
e126ba97
EC		 911 }
912
1b5daf11
MD		 913 return err;
914}
e126ba97 915
1b5daf11
MD		 916static int mlx5_mtu_to_ib_mtu(int mtu)
917{
918 switch (mtu) {
919 case 256: return 1;
920 case 512: return 2;
921 case 1024: return 3;
922 case 2048: return 4;
923 case 4096: return 5;
924 default:
925 pr_warn("invalid mtu\n");
926 return -1;
e126ba97 927 }
1b5daf11 928}
e126ba97 929
1b5daf11
MD		 930enum ib_max_vl_num {
931 __IB_MAX_VL_0 = 1,
932 __IB_MAX_VL_0_1 = 2,
933 __IB_MAX_VL_0_3 = 3,
934 __IB_MAX_VL_0_7 = 4,
935 __IB_MAX_VL_0_14 = 5,
936};
e126ba97 937
1b5daf11
MD		 938enum mlx5_vl_hw_cap {
939 MLX5_VL_HW_0 = 1,
940 MLX5_VL_HW_0_1 = 2,
941 MLX5_VL_HW_0_2 = 3,
942 MLX5_VL_HW_0_3 = 4,
943 MLX5_VL_HW_0_4 = 5,
944 MLX5_VL_HW_0_5 = 6,
945 MLX5_VL_HW_0_6 = 7,
946 MLX5_VL_HW_0_7 = 8,
947 MLX5_VL_HW_0_14 = 15
948};
e126ba97 949
1b5daf11
MD		 950static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
951 u8 *max_vl_num)
952{
953 switch (vl_hw_cap) {
954 case MLX5_VL_HW_0:
955 *max_vl_num = __IB_MAX_VL_0;
956 break;
957 case MLX5_VL_HW_0_1:
958 *max_vl_num = __IB_MAX_VL_0_1;
959 break;
960 case MLX5_VL_HW_0_3:
961 *max_vl_num = __IB_MAX_VL_0_3;
962 break;
963 case MLX5_VL_HW_0_7:
964 *max_vl_num = __IB_MAX_VL_0_7;
965 break;
966 case MLX5_VL_HW_0_14:
967 *max_vl_num = __IB_MAX_VL_0_14;
968 break;
e126ba97 969
1b5daf11
MD		 970 default:
971 return -EINVAL;
e126ba97 972 }
e126ba97 973
1b5daf11 974 return 0;
e126ba97
EC		 975}
976
1b5daf11
MD		 977static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
978 struct ib_port_attr *props)
e126ba97 979{
1b5daf11
MD		 980 struct mlx5_ib_dev *dev = to_mdev(ibdev);
981 struct mlx5_core_dev *mdev = dev->mdev;
982 struct mlx5_hca_vport_context *rep;
046339ea
SM		 983 u16 max_mtu;
984 u16 oper_mtu;
1b5daf11
MD		 985 int err;
986 u8 ib_link_width_oper;
987 u8 vl_hw_cap;
e126ba97 988
1b5daf11
MD		 989 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
990 if (!rep) {
991 err = -ENOMEM;
e126ba97 992 goto out;
e126ba97 993 }
e126ba97 994
c4550c63 995 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 996
1b5daf11 997 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 998 if (err)
999 goto out;
1000
1b5daf11
MD		 1001 props->lid = rep->lid;
1002 props->lmc = rep->lmc;
1003 props->sm_lid = rep->sm_lid;
1004 props->sm_sl = rep->sm_sl;
1005 props->state = rep->vport_state;
1006 props->phys_state = rep->port_physical_state;
1007 props->port_cap_flags = rep->cap_mask1;
1008 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1009 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1010 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1011 props->bad_pkey_cntr = rep->pkey_violation_counter;
1012 props->qkey_viol_cntr = rep->qkey_violation_counter;
1013 props->subnet_timeout = rep->subnet_timeout;
1014 props->init_type_reply = rep->init_type_reply;
eff901d3 1015 props->grh_required = rep->grh_required;
e126ba97 1016
1b5daf11
MD		 1017 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1018 if (err)
e126ba97 1019 goto out;
e126ba97 1020
1b5daf11
MD		 1021 err = translate_active_width(ibdev, ib_link_width_oper,
1022 &props->active_width);
1023 if (err)
1024 goto out;
d5beb7f2 1025 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1026 if (err)
1027 goto out;
1028
facc9699 1029 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1030
1b5daf11 1031 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1032
facc9699 1033 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1034
1b5daf11 1035 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1036
1b5daf11
MD		 1037 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1038 if (err)
1039 goto out;
e126ba97 1040
1b5daf11
MD		 1041 err = translate_max_vl_num(ibdev, vl_hw_cap,
1042 &props->max_vl_num);
e126ba97 1043out:
1b5daf11 1044 kfree(rep);
e126ba97
EC		 1045 return err;
1046}
1047
1b5daf11
MD		 1048int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1049 struct ib_port_attr *props)
e126ba97 1050{
095b0927
IT		 1051 unsigned int count;
1052 int ret;
1053
1b5daf11
MD		 1054 switch (mlx5_get_vport_access_method(ibdev)) {
1055 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1056 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1057 break;
e126ba97 1058
1b5daf11 1059 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1060 ret = mlx5_query_hca_port(ibdev, port, props);
1061 break;
e126ba97 1062
3f89a643 1063 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1064 ret = mlx5_query_port_roce(ibdev, port, props);
1065 break;
3f89a643 1066
1b5daf11 1067 default:
095b0927
IT		 1068 ret = -EINVAL;
1069 }
1070
1071 if (!ret && props) {
1072 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1073 props->gid_tbl_len -= count;
1b5daf11 1074 }
095b0927 1075 return ret;
1b5daf11 1076}
e126ba97 1077
1b5daf11
MD		 1078static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1079 union ib_gid *gid)
1080{
1081 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1082 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1083
1b5daf11
MD		 1084 switch (mlx5_get_vport_access_method(ibdev)) {
1085 case MLX5_VPORT_ACCESS_METHOD_MAD:
1086 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1087
1b5daf11
MD		 1088 case MLX5_VPORT_ACCESS_METHOD_HCA:
1089 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1090
1091 default:
1092 return -EINVAL;
1093 }
e126ba97 1094
e126ba97
EC		 1095}
1096
1b5daf11
MD		 1097static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1098 u16 *pkey)
1099{
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1101 struct mlx5_core_dev *mdev = dev->mdev;
1102
1103 switch (mlx5_get_vport_access_method(ibdev)) {
1104 case MLX5_VPORT_ACCESS_METHOD_MAD:
1105 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1106
1107 case MLX5_VPORT_ACCESS_METHOD_HCA:
1108 case MLX5_VPORT_ACCESS_METHOD_NIC:
1109 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1110 pkey);
1111 default:
1112 return -EINVAL;
1113 }
1114}
e126ba97
EC		 1115
1116static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1117 struct ib_device_modify *props)
1118{
1119 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1120 struct mlx5_reg_node_desc in;
1121 struct mlx5_reg_node_desc out;
1122 int err;
1123
1124 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1125 return -EOPNOTSUPP;
1126
1127 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1128 return 0;
1129
1130 /*
1131 * If possible, pass node desc to FW, so it can generate
1132 * a 144 trap. If cmd fails, just ignore.
1133 */
bd99fdea 1134 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1135 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1136 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1137 if (err)
1138 return err;
1139
bd99fdea 1140 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1141
1142 return err;
1143}
1144
cdbe33d0
EC		 1145static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1146 u32 value)
1147{
1148 struct mlx5_hca_vport_context ctx = {};
1149 int err;
1150
1151 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1152 port_num, 0, &ctx);
1153 if (err)
1154 return err;
1155
1156 if (~ctx.cap_mask1_perm & mask) {
1157 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1158 mask, ctx.cap_mask1_perm);
1159 return -EINVAL;
1160 }
1161
1162 ctx.cap_mask1 = value;
1163 ctx.cap_mask1_perm = mask;
1164 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1165 port_num, 0, &ctx);
1166
1167 return err;
1168}
1169
e126ba97
EC		 1170static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1171 struct ib_port_modify *props)
1172{
1173 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1174 struct ib_port_attr attr;
1175 u32 tmp;
1176 int err;
cdbe33d0
EC		 1177 u32 change_mask;
1178 u32 value;
1179 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1180 IB_LINK_LAYER_INFINIBAND);
1181
ec255879
MD		 1182 /* CM layer calls ib_modify_port() regardless of the link layer. For
1183 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1184 */
1185 if (!is_ib)
1186 return 0;
1187
cdbe33d0
EC		 1188 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1189 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1190 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1191 return set_port_caps_atomic(dev, port, change_mask, value);
1192 }
e126ba97
EC		 1193
1194 mutex_lock(&dev->cap_mask_mutex);
1195
c4550c63 1196 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1197 if (err)
1198 goto out;
1199
1200 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1201 ~props->clr_port_cap_mask;
1202
9603b61d 1203 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1204
1205out:
1206 mutex_unlock(&dev->cap_mask_mutex);
1207 return err;
1208}
1209
30aa60b3
EC		 1210static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1211{
1212 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1213 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1214}
1215
b037c29a
EC		 1216static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1217 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1218 u32 *num_sys_pages)
1219{
1220 int uars_per_sys_page;
1221 int bfregs_per_sys_page;
1222 int ref_bfregs = req->total_num_bfregs;
1223
1224 if (req->total_num_bfregs == 0)
1225 return -EINVAL;
1226
1227 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1228 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1229
1230 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1231 return -ENOMEM;
1232
1233 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1234 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1235 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1236 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1237
1238 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1239 return -EINVAL;
1240
9c2d33d4 1241 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, using %d sys pages\n",
b037c29a
EC		 1242 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1243 lib_uar_4k ? "yes" : "no", ref_bfregs,
1244 req->total_num_bfregs, *num_sys_pages);
1245
1246 return 0;
1247}
1248
1249static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1250{
1251 struct mlx5_bfreg_info *bfregi;
1252 int err;
1253 int i;
1254
1255 bfregi = &context->bfregi;
1256 for (i = 0; i < bfregi->num_sys_pages; i++) {
1257 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1258 if (err)
1259 goto error;
1260
1261 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1262 }
1263 return 0;
1264
1265error:
1266 for (--i; i >= 0; i--)
1267 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1268 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1269
1270 return err;
1271}
1272
1273static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1274{
1275 struct mlx5_bfreg_info *bfregi;
1276 int err;
1277 int i;
1278
1279 bfregi = &context->bfregi;
1280 for (i = 0; i < bfregi->num_sys_pages; i++) {
1281 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1282 if (err) {
1283 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1284 return err;
1285 }
1286 }
1287 return 0;
1288}
1289
c85023e1
HN		 1290static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1291{
1292 int err;
1293
1294 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1295 if (err)
1296 return err;
1297
1298 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1299 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1300 return err;
1301
1302 mutex_lock(&dev->lb_mutex);
1303 dev->user_td++;
1304
1305 if (dev->user_td == 2)
1306 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1307
1308 mutex_unlock(&dev->lb_mutex);
1309 return err;
1310}
1311
1312static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1313{
1314 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1315
1316 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1317 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1318 return;
1319
1320 mutex_lock(&dev->lb_mutex);
1321 dev->user_td--;
1322
1323 if (dev->user_td < 2)
1324 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1325
1326 mutex_unlock(&dev->lb_mutex);
1327}
1328
e126ba97
EC		 1329static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1330 struct ib_udata *udata)
1331{
1332 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1333 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1334 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1335 struct mlx5_ib_ucontext *context;
2f5ff264 1336 struct mlx5_bfreg_info *bfregi;
78c0f98c 1337 int ver;
e126ba97 1338 int err;
a168a41c
MD		 1339 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1340 max_cqe_version);
b037c29a 1341 bool lib_uar_4k;
e126ba97
EC		 1342
1343 if (!dev->ib_active)
1344 return ERR_PTR(-EAGAIN);
1345
e093111d 1346 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1347 ver = 0;
e093111d 1348 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1349 ver = 2;
1350 else
1351 return ERR_PTR(-EINVAL);
1352
e093111d 1353 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1354 if (err)
1355 return ERR_PTR(err);
1356
b368d7cb 1357 if (req.flags)
78c0f98c
EC		 1358 return ERR_PTR(-EINVAL);
1359
f72300c5 1360 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1361 return ERR_PTR(-EOPNOTSUPP);
1362
2f5ff264
EC		 1363 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1364 MLX5_NON_FP_BFREGS_PER_UAR);
1365 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1366 return ERR_PTR(-EINVAL);
1367
938fe83c 1368 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1369 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1370 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1371 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1372 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1373 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1374 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1375 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1376 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1377 resp.cqe_version = min_t(__u8,
1378 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1379 req.max_cqe_version);
30aa60b3
EC		 1380 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1381 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1382 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1383 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1384 resp.response_length = min(offsetof(typeof(resp), response_length) +
1385 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1386
1387 context = kzalloc(sizeof(*context), GFP_KERNEL);
1388 if (!context)
1389 return ERR_PTR(-ENOMEM);
1390
30aa60b3 1391 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1392 bfregi = &context->bfregi;
b037c29a
EC		 1393
1394 /* updates req->total_num_bfregs */
1395 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1396 if (err)
e126ba97 1397 goto out_ctx;
e126ba97 1398
b037c29a
EC		 1399 mutex_init(&bfregi->lock);
1400 bfregi->lib_uar_4k = lib_uar_4k;
1401 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1402 GFP_KERNEL);
b037c29a 1403 if (!bfregi->count) {
e126ba97 1404 err = -ENOMEM;
b037c29a 1405 goto out_ctx;
e126ba97
EC		 1406 }
1407
b037c29a
EC		 1408 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1409 sizeof(*bfregi->sys_pages),
1410 GFP_KERNEL);
1411 if (!bfregi->sys_pages) {
e126ba97 1412 err = -ENOMEM;
b037c29a 1413 goto out_count;
e126ba97
EC		 1414 }
1415
b037c29a
EC		 1416 err = allocate_uars(dev, context);
1417 if (err)
1418 goto out_sys_pages;
e126ba97 1419
b4cfe447
HE		 1420#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1421 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1422#endif
1423
7d0cc6ed
AK		 1424 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1425 if (!context->upd_xlt_page) {
1426 err = -ENOMEM;
1427 goto out_uars;
1428 }
1429 mutex_init(&context->upd_xlt_page_mutex);
1430
146d2f1a 1431 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1432 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1433 if (err)
7d0cc6ed 1434 goto out_page;
146d2f1a 1435 }
1436
7c2344c3 1437 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1438 INIT_LIST_HEAD(&context->db_page_list);
1439 mutex_init(&context->db_page_mutex);
1440
2f5ff264 1441 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1442 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1443
f72300c5
HA		 1444 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1445 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1446
402ca536 1447 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1448 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1449 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1450 resp.response_length += sizeof(resp.cmds_supp_uhw);
1451 }
1452
78984898
OG		 1453 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1454 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1455 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1456 resp.eth_min_inline++;
1457 }
1458 resp.response_length += sizeof(resp.eth_min_inline);
1459 }
1460
bc5c6eed
NO		 1461 /*
1462 * We don't want to expose information from the PCI bar that is located
1463 * after 4096 bytes, so if the arch only supports larger pages, let's
1464 * pretend we don't support reading the HCA's core clock. This is also
1465 * forced by mmap function.
1466 */
de8d6e02
EC		 1467 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1468 if (PAGE_SIZE <= 4096) {
1469 resp.comp_mask |=
1470 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1471 resp.hca_core_clock_offset =
1472 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1473 }
f72300c5 1474 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1475 sizeof(resp.reserved2);
b368d7cb
MB		 1476 }
1477
30aa60b3
EC		 1478 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1479 resp.response_length += sizeof(resp.log_uar_size);
1480
1481 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1482 resp.response_length += sizeof(resp.num_uars_per_page);
1483
b368d7cb 1484 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1485 if (err)
146d2f1a 1486 goto out_td;
e126ba97 1487
2f5ff264
EC		 1488 bfregi->ver = ver;
1489 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1490 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1491 context->lib_caps = req.lib_caps;
1492 print_lib_caps(dev, context->lib_caps);
f72300c5 1493
e126ba97
EC		 1494 return &context->ibucontext;
1495
146d2f1a 1496out_td:
1497 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1498 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1499
7d0cc6ed
AK		 1500out_page:
1501 free_page(context->upd_xlt_page);
1502
e126ba97 1503out_uars:
b037c29a 1504 deallocate_uars(dev, context);
e126ba97 1505
b037c29a
EC		 1506out_sys_pages:
1507 kfree(bfregi->sys_pages);
e126ba97 1508
b037c29a
EC		 1509out_count:
1510 kfree(bfregi->count);
e126ba97
EC		 1511
1512out_ctx:
1513 kfree(context);
b037c29a 1514
e126ba97
EC		 1515 return ERR_PTR(err);
1516}
1517
1518static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1519{
1520 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1521 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1522 struct mlx5_bfreg_info *bfregi;
e126ba97 1523
b037c29a 1524 bfregi = &context->bfregi;
146d2f1a 1525 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1526 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1527
7d0cc6ed 1528 free_page(context->upd_xlt_page);
b037c29a
EC		 1529 deallocate_uars(dev, context);
1530 kfree(bfregi->sys_pages);
2f5ff264 1531 kfree(bfregi->count);
e126ba97
EC		 1532 kfree(context);
1533
1534 return 0;
1535}
1536
b037c29a
EC		 1537static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1538 struct mlx5_bfreg_info *bfregi,
1539 int idx)
e126ba97 1540{
b037c29a
EC		 1541 int fw_uars_per_page;
1542
1543 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1544
1545 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1546 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1547}
1548
1549static int get_command(unsigned long offset)
1550{
1551 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1552}
1553
1554static int get_arg(unsigned long offset)
1555{
1556 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1557}
1558
1559static int get_index(unsigned long offset)
1560{
1561 return get_arg(offset);
1562}
1563
7c2344c3
MG		 1564static void mlx5_ib_vma_open(struct vm_area_struct *area)
1565{
1566 /* vma_open is called when a new VMA is created on top of our VMA. This
1567 * is done through either mremap flow or split_vma (usually due to
1568 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1569 * as this VMA is strongly hardware related. Therefore we set the
1570 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1571 * calling us again and trying to do incorrect actions. We assume that
1572 * the original VMA size is exactly a single page, and therefore all
1573 * "splitting" operation will not happen to it.
1574 */
1575 area->vm_ops = NULL;
1576}
1577
1578static void mlx5_ib_vma_close(struct vm_area_struct *area)
1579{
1580 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1581
1582 /* It's guaranteed that all VMAs opened on a FD are closed before the
1583 * file itself is closed, therefore no sync is needed with the regular
1584 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1585 * However need a sync with accessing the vma as part of
1586 * mlx5_ib_disassociate_ucontext.
1587 * The close operation is usually called under mm->mmap_sem except when
1588 * process is exiting.
1589 * The exiting case is handled explicitly as part of
1590 * mlx5_ib_disassociate_ucontext.
1591 */
1592 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1593
1594 /* setting the vma context pointer to null in the mlx5_ib driver's
1595 * private data, to protect a race condition in
1596 * mlx5_ib_disassociate_ucontext().
1597 */
1598 mlx5_ib_vma_priv_data->vma = NULL;
1599 list_del(&mlx5_ib_vma_priv_data->list);
1600 kfree(mlx5_ib_vma_priv_data);
1601}
1602
1603static const struct vm_operations_struct mlx5_ib_vm_ops = {
1604 .open = mlx5_ib_vma_open,
1605 .close = mlx5_ib_vma_close
1606};
1607
1608static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1609 struct mlx5_ib_ucontext *ctx)
1610{
1611 struct mlx5_ib_vma_private_data *vma_prv;
1612 struct list_head *vma_head = &ctx->vma_private_list;
1613
1614 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1615 if (!vma_prv)
1616 return -ENOMEM;
1617
1618 vma_prv->vma = vma;
1619 vma->vm_private_data = vma_prv;
1620 vma->vm_ops = &mlx5_ib_vm_ops;
1621
1622 list_add(&vma_prv->list, vma_head);
1623
1624 return 0;
1625}
1626
1627static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1628{
1629 int ret;
1630 struct vm_area_struct *vma;
1631 struct mlx5_ib_vma_private_data *vma_private, *n;
1632 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1633 struct task_struct *owning_process = NULL;
1634 struct mm_struct *owning_mm = NULL;
1635
1636 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1637 if (!owning_process)
1638 return;
1639
1640 owning_mm = get_task_mm(owning_process);
1641 if (!owning_mm) {
1642 pr_info("no mm, disassociate ucontext is pending task termination\n");
1643 while (1) {
1644 put_task_struct(owning_process);
1645 usleep_range(1000, 2000);
1646 owning_process = get_pid_task(ibcontext->tgid,
1647 PIDTYPE_PID);
1648 if (!owning_process ||
1649 owning_process->state == TASK_DEAD) {
1650 pr_info("disassociate ucontext done, task was terminated\n");
1651 /* in case task was dead need to release the
1652 * task struct.
1653 */
1654 if (owning_process)
1655 put_task_struct(owning_process);
1656 return;
1657 }
1658 }
1659 }
1660
1661 /* need to protect from a race on closing the vma as part of
1662 * mlx5_ib_vma_close.
1663 */
ecc7d83b 1664 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1665 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1666 list) {
1667 vma = vma_private->vma;
1668 ret = zap_vma_ptes(vma, vma->vm_start,
1669 PAGE_SIZE);
1670 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1671 /* context going to be destroyed, should
1672 * not access ops any more.
1673 */
13776612 1674 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1675 vma->vm_ops = NULL;
1676 list_del(&vma_private->list);
1677 kfree(vma_private);
1678 }
ecc7d83b 1679 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1680 mmput(owning_mm);
1681 put_task_struct(owning_process);
1682}
1683
37aa5c36
GL		 1684static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1685{
1686 switch (cmd) {
1687 case MLX5_IB_MMAP_WC_PAGE:
1688 return "WC";
1689 case MLX5_IB_MMAP_REGULAR_PAGE:
1690 return "best effort WC";
1691 case MLX5_IB_MMAP_NC_PAGE:
1692 return "NC";
1693 default:
1694 return NULL;
1695 }
1696}
1697
1698static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1699 struct vm_area_struct *vma,
1700 struct mlx5_ib_ucontext *context)
37aa5c36 1701{
2f5ff264 1702 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1703 int err;
1704 unsigned long idx;
1705 phys_addr_t pfn, pa;
1706 pgprot_t prot;
b037c29a
EC		 1707 int uars_per_page;
1708
1709 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1710 return -EINVAL;
1711
1712 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1713 idx = get_index(vma->vm_pgoff);
1714 if (idx % uars_per_page ||
1715 idx * uars_per_page >= bfregi->num_sys_pages) {
1716 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1717 return -EINVAL;
1718 }
37aa5c36
GL		 1719
1720 switch (cmd) {
1721 case MLX5_IB_MMAP_WC_PAGE:
1722/* Some architectures don't support WC memory */
1723#if defined(CONFIG_X86)
1724 if (!pat_enabled())
1725 return -EPERM;
1726#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1727 return -EPERM;
1728#endif
1729 /* fall through */
1730 case MLX5_IB_MMAP_REGULAR_PAGE:
1731 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1732 prot = pgprot_writecombine(vma->vm_page_prot);
1733 break;
1734 case MLX5_IB_MMAP_NC_PAGE:
1735 prot = pgprot_noncached(vma->vm_page_prot);
1736 break;
1737 default:
1738 return -EINVAL;
1739 }
1740
b037c29a 1741 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1742 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1743
1744 vma->vm_page_prot = prot;
1745 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1746 PAGE_SIZE, vma->vm_page_prot);
1747 if (err) {
1748 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1749 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1750 return -EAGAIN;
1751 }
1752
1753 pa = pfn << PAGE_SHIFT;
1754 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1755 vma->vm_start, &pa);
1756
7c2344c3 1757 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1758}
1759
e126ba97
EC		 1760static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1761{
1762 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1763 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1764 unsigned long command;
e126ba97
EC		 1765 phys_addr_t pfn;
1766
1767 command = get_command(vma->vm_pgoff);
1768 switch (command) {
37aa5c36
GL		 1769 case MLX5_IB_MMAP_WC_PAGE:
1770 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1771 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1772 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1773
1774 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1775 return -ENOSYS;
1776
d69e3bcf 1777 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1778 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1779 return -EINVAL;
1780
6cbac1e4 1781 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1782 return -EPERM;
1783
1784 /* Don't expose to user-space information it shouldn't have */
1785 if (PAGE_SIZE > 4096)
1786 return -EOPNOTSUPP;
1787
1788 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1789 pfn = (dev->mdev->iseg_base +
1790 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1791 PAGE_SHIFT;
1792 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1793 PAGE_SIZE, vma->vm_page_prot))
1794 return -EAGAIN;
1795
1796 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1797 vma->vm_start,
1798 (unsigned long long)pfn << PAGE_SHIFT);
1799 break;
d69e3bcf 1800
e126ba97
EC		 1801 default:
1802 return -EINVAL;
1803 }
1804
1805 return 0;
1806}
1807
e126ba97
EC		 1808static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1809 struct ib_ucontext *context,
1810 struct ib_udata *udata)
1811{
1812 struct mlx5_ib_alloc_pd_resp resp;
1813 struct mlx5_ib_pd *pd;
1814 int err;
1815
1816 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1817 if (!pd)
1818 return ERR_PTR(-ENOMEM);
1819
9603b61d 1820 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1821 if (err) {
1822 kfree(pd);
1823 return ERR_PTR(err);
1824 }
1825
1826 if (context) {
1827 resp.pdn = pd->pdn;
1828 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1829 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1830 kfree(pd);
1831 return ERR_PTR(-EFAULT);
1832 }
e126ba97
EC		 1833 }
1834
1835 return &pd->ibpd;
1836}
1837
1838static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1839{
1840 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1841 struct mlx5_ib_pd *mpd = to_mpd(pd);
1842
9603b61d 1843 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1844 kfree(mpd);
1845
1846 return 0;
1847}
1848
466fa6d2
MG		 1849enum {
1850 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1851 MATCH_CRITERIA_ENABLE_MISC_BIT,
1852 MATCH_CRITERIA_ENABLE_INNER_BIT
1853};
1854
1855#define HEADER_IS_ZERO(match_criteria, headers) \
1856 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1857 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1858
466fa6d2 1859static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1860{
466fa6d2 1861 u8 match_criteria_enable;
038d2ef8 1862
466fa6d2
MG		 1863 match_criteria_enable =
1864 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1865 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1866 match_criteria_enable |=
1867 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1868 MATCH_CRITERIA_ENABLE_MISC_BIT;
1869 match_criteria_enable |=
1870 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1871 MATCH_CRITERIA_ENABLE_INNER_BIT;
1872
1873 return match_criteria_enable;
038d2ef8
MG		 1874}
1875
ca0d4753
MG		 1876static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1877{
1878 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1879 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1880}
1881
2d1e697e
MR		 1882static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1883 bool inner)
1884{
1885 if (inner) {
1886 MLX5_SET(fte_match_set_misc,
1887 misc_c, inner_ipv6_flow_label, mask);
1888 MLX5_SET(fte_match_set_misc,
1889 misc_v, inner_ipv6_flow_label, val);
1890 } else {
1891 MLX5_SET(fte_match_set_misc,
1892 misc_c, outer_ipv6_flow_label, mask);
1893 MLX5_SET(fte_match_set_misc,
1894 misc_v, outer_ipv6_flow_label, val);
1895 }
1896}
1897
ca0d4753
MG		 1898static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1899{
1900 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1901 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1902 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1903 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1904}
1905
c47ac6ae
MG		 1906#define LAST_ETH_FIELD vlan_tag
1907#define LAST_IB_FIELD sl
ca0d4753 1908#define LAST_IPV4_FIELD tos
466fa6d2 1909#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1910#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1911#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1912#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1913#define LAST_DROP_FIELD size
c47ac6ae
MG		 1914
1915/* Field is the last supported field */
1916#define FIELDS_NOT_SUPPORTED(filter, field)\
1917 memchr_inv((void *)&filter.field +\
1918 sizeof(filter.field), 0,\
1919 sizeof(filter) -\
1920 offsetof(typeof(filter), field) -\
1921 sizeof(filter.field))
1922
19cc7524
AL		 1923#define IPV4_VERSION 4
1924#define IPV6_VERSION 6
1925static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1926 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1927 u32 *tag_id, bool *is_drop)
038d2ef8 1928{
466fa6d2
MG		 1929 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1930 misc_parameters);
1931 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1932 misc_parameters);
2d1e697e
MR		 1933 void *headers_c;
1934 void *headers_v;
19cc7524 1935 int match_ipv;
2d1e697e
MR		 1936
1937 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1938 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1939 inner_headers);
1940 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1941 inner_headers);
19cc7524
AL		 1942 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1943 ft_field_support.inner_ip_version);
2d1e697e
MR		 1944 } else {
1945 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1946 outer_headers);
1947 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1948 outer_headers);
19cc7524
AL		 1949 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1950 ft_field_support.outer_ip_version);
2d1e697e 1951 }
466fa6d2 1952
2d1e697e 1953 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1954 case IB_FLOW_SPEC_ETH:
c47ac6ae 1955 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1956 return -EOPNOTSUPP;
038d2ef8 1957
2d1e697e 1958 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1959 dmac_47_16),
1960 ib_spec->eth.mask.dst_mac);
2d1e697e 1961 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1962 dmac_47_16),
1963 ib_spec->eth.val.dst_mac);
1964
2d1e697e 1965 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1966 smac_47_16),
1967 ib_spec->eth.mask.src_mac);
2d1e697e 1968 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1969 smac_47_16),
1970 ib_spec->eth.val.src_mac);
1971
038d2ef8 1972 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1973 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1974 cvlan_tag, 1);
2d1e697e 1975 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1976 cvlan_tag, 1);
038d2ef8 1977
2d1e697e 1978 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1979 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1980 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1981 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1982
2d1e697e 1983 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1984 first_cfi,
1985 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1986 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1987 first_cfi,
1988 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1989
2d1e697e 1990 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1991 first_prio,
1992 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1993 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1994 first_prio,
1995 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1996 }
2d1e697e 1997 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1998 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1999 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2000 ethertype, ntohs(ib_spec->eth.val.ether_type));
2001 break;
2002 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2003 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2004 return -EOPNOTSUPP;
038d2ef8 2005
19cc7524
AL		 2006 if (match_ipv) {
2007 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2008 ip_version, 0xf);
2009 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2010 ip_version, IPV4_VERSION);
2011 } else {
2012 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2013 ethertype, 0xffff);
2014 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2015 ethertype, ETH_P_IP);
2016 }
038d2ef8 2017
2d1e697e 2018 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2019 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2020 &ib_spec->ipv4.mask.src_ip,
2021 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2022 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2023 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2024 &ib_spec->ipv4.val.src_ip,
2025 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2026 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2027 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2028 &ib_spec->ipv4.mask.dst_ip,
2029 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2030 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2031 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2032 &ib_spec->ipv4.val.dst_ip,
2033 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2034
2d1e697e 2035 set_tos(headers_c, headers_v,
ca0d4753
MG		 2036 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2037
2d1e697e 2038 set_proto(headers_c, headers_v,
ca0d4753 2039 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2040 break;
026bae0c 2041 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2042 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2043 return -EOPNOTSUPP;
026bae0c 2044
19cc7524
AL		 2045 if (match_ipv) {
2046 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2047 ip_version, 0xf);
2048 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2049 ip_version, IPV6_VERSION);
2050 } else {
2051 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2052 ethertype, 0xffff);
2053 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2054 ethertype, ETH_P_IPV6);
2055 }
026bae0c 2056
2d1e697e 2057 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2058 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2059 &ib_spec->ipv6.mask.src_ip,
2060 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2061 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2062 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2063 &ib_spec->ipv6.val.src_ip,
2064 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2065 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2066 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2067 &ib_spec->ipv6.mask.dst_ip,
2068 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2069 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2070 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2071 &ib_spec->ipv6.val.dst_ip,
2072 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2073
2d1e697e 2074 set_tos(headers_c, headers_v,
466fa6d2
MG		 2075 ib_spec->ipv6.mask.traffic_class,
2076 ib_spec->ipv6.val.traffic_class);
2077
2d1e697e 2078 set_proto(headers_c, headers_v,
466fa6d2
MG		 2079 ib_spec->ipv6.mask.next_hdr,
2080 ib_spec->ipv6.val.next_hdr);
2081
2d1e697e
MR		 2082 set_flow_label(misc_params_c, misc_params_v,
2083 ntohl(ib_spec->ipv6.mask.flow_label),
2084 ntohl(ib_spec->ipv6.val.flow_label),
2085 ib_spec->type & IB_FLOW_SPEC_INNER);
2086
026bae0c 2087 break;
038d2ef8 2088 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2089 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2090 LAST_TCP_UDP_FIELD))
1ffd3a26 2091 return -EOPNOTSUPP;
038d2ef8 2092
2d1e697e 2093 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2094 0xff);
2d1e697e 2095 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2096 IPPROTO_TCP);
2097
2d1e697e 2098 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2099 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2100 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2101 ntohs(ib_spec->tcp_udp.val.src_port));
2102
2d1e697e 2103 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2104 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2105 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2106 ntohs(ib_spec->tcp_udp.val.dst_port));
2107 break;
2108 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2109 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2110 LAST_TCP_UDP_FIELD))
1ffd3a26 2111 return -EOPNOTSUPP;
038d2ef8 2112
2d1e697e 2113 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2114 0xff);
2d1e697e 2115 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2116 IPPROTO_UDP);
2117
2d1e697e 2118 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2119 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2120 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2121 ntohs(ib_spec->tcp_udp.val.src_port));
2122
2d1e697e 2123 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2124 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2125 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2126 ntohs(ib_spec->tcp_udp.val.dst_port));
2127 break;
ffb30d8f
MR		 2128 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2129 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2130 LAST_TUNNEL_FIELD))
1ffd3a26 2131 return -EOPNOTSUPP;
ffb30d8f
MR		 2132
2133 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2134 ntohl(ib_spec->tunnel.mask.tunnel_id));
2135 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2136 ntohl(ib_spec->tunnel.val.tunnel_id));
2137 break;
2ac693f9
MR		 2138 case IB_FLOW_SPEC_ACTION_TAG:
2139 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2140 LAST_FLOW_TAG_FIELD))
2141 return -EOPNOTSUPP;
2142 if (ib_spec->flow_tag.tag_id >= BIT(24))
2143 return -EINVAL;
2144
2145 *tag_id = ib_spec->flow_tag.tag_id;
2146 break;
a22ed86c
SS		 2147 case IB_FLOW_SPEC_ACTION_DROP:
2148 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2149 LAST_DROP_FIELD))
2150 return -EOPNOTSUPP;
2151 *is_drop = true;
2152 break;
038d2ef8
MG		 2153 default:
2154 return -EINVAL;
2155 }
2156
2157 return 0;
2158}
2159
2160/* If a flow could catch both multicast and unicast packets,
2161 * it won't fall into the multicast flow steering table and this rule
2162 * could steal other multicast packets.
2163 */
a550ddfc 2164static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2165{
81e30880 2166 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2167
2168 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2169 ib_attr->num_of_specs < 1)
2170 return false;
2171
81e30880
YH		 2172 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2173 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2174 struct ib_flow_spec_ipv4 *ipv4_spec;
2175
2176 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2177 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2178 return true;
2179
038d2ef8 2180 return false;
81e30880
YH		 2181 }
2182
2183 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2184 struct ib_flow_spec_eth *eth_spec;
2185
2186 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2187 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2188 is_multicast_ether_addr(eth_spec->val.dst_mac);
2189 }
038d2ef8 2190
81e30880 2191 return false;
038d2ef8
MG		 2192}
2193
19cc7524
AL		 2194static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2195 const struct ib_flow_attr *flow_attr,
0f750966 2196 bool check_inner)
038d2ef8
MG		 2197{
2198 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2199 int match_ipv = check_inner ?
2200 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2201 ft_field_support.inner_ip_version) :
2202 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2203 ft_field_support.outer_ip_version);
0f750966
AL		 2204 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2205 bool ipv4_spec_valid, ipv6_spec_valid;
2206 unsigned int ip_spec_type = 0;
2207 bool has_ethertype = false;
038d2ef8 2208 unsigned int spec_index;
0f750966
AL		 2209 bool mask_valid = true;
2210 u16 eth_type = 0;
2211 bool type_valid;
038d2ef8
MG		 2212
2213 /* Validate that ethertype is correct */
2214 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2215 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2216 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2217 mask_valid = (ib_spec->eth.mask.ether_type ==
2218 htons(0xffff));
2219 has_ethertype = true;
2220 eth_type = ntohs(ib_spec->eth.val.ether_type);
2221 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2222 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2223 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2224 }
2225 ib_spec = (void *)ib_spec + ib_spec->size;
2226 }
0f750966
AL		 2227
2228 type_valid = (!has_ethertype) || (!ip_spec_type);
2229 if (!type_valid && mask_valid) {
2230 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2231 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2232 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2233 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2234
2235 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2236 (((eth_type == ETH_P_MPLS_UC) ||
2237 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2238 }
2239
2240 return type_valid;
2241}
2242
19cc7524
AL		 2243static bool is_valid_attr(struct mlx5_core_dev *mdev,
2244 const struct ib_flow_attr *flow_attr)
0f750966 2245{
19cc7524
AL		 2246 return is_valid_ethertype(mdev, flow_attr, false) &&
2247 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2248}
2249
2250static void put_flow_table(struct mlx5_ib_dev *dev,
2251 struct mlx5_ib_flow_prio *prio, bool ft_added)
2252{
2253 prio->refcount -= !!ft_added;
2254 if (!prio->refcount) {
2255 mlx5_destroy_flow_table(prio->flow_table);
2256 prio->flow_table = NULL;
2257 }
2258}
2259
2260static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2261{
2262 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2263 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2264 struct mlx5_ib_flow_handler,
2265 ibflow);
2266 struct mlx5_ib_flow_handler *iter, *tmp;
2267
2268 mutex_lock(&dev->flow_db.lock);
2269
2270 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2271 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2272 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2273 list_del(&iter->list);
2274 kfree(iter);
2275 }
2276
74491de9 2277 mlx5_del_flow_rules(handler->rule);
5497adc6 2278 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2279 mutex_unlock(&dev->flow_db.lock);
2280
2281 kfree(handler);
2282
2283 return 0;
2284}
2285
35d19011
MG		 2286static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2287{
2288 priority *= 2;
2289 if (!dont_trap)
2290 priority++;
2291 return priority;
2292}
2293
cc0e5d42
MG		 2294enum flow_table_type {
2295 MLX5_IB_FT_RX,
2296 MLX5_IB_FT_TX
2297};
2298
00b7c2ab
MG		 2299#define MLX5_FS_MAX_TYPES 6
2300#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2301static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2302 struct ib_flow_attr *flow_attr,
2303 enum flow_table_type ft_type)
038d2ef8 2304{
35d19011 2305 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2306 struct mlx5_flow_namespace *ns = NULL;
2307 struct mlx5_ib_flow_prio *prio;
2308 struct mlx5_flow_table *ft;
dac388ef 2309 int max_table_size;
038d2ef8
MG		 2310 int num_entries;
2311 int num_groups;
2312 int priority;
2313 int err = 0;
2314
dac388ef
MG		 2315 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2316 log_max_ft_size));
038d2ef8 2317 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2318 if (flow_is_multicast_only(flow_attr) &&
2319 !dont_trap)
038d2ef8
MG		 2320 priority = MLX5_IB_FLOW_MCAST_PRIO;
2321 else
35d19011
MG		 2322 priority = ib_prio_to_core_prio(flow_attr->priority,
2323 dont_trap);
038d2ef8
MG		 2324 ns = mlx5_get_flow_namespace(dev->mdev,
2325 MLX5_FLOW_NAMESPACE_BYPASS);
2326 num_entries = MLX5_FS_MAX_ENTRIES;
2327 num_groups = MLX5_FS_MAX_TYPES;
2328 prio = &dev->flow_db.prios[priority];
2329 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2330 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2331 ns = mlx5_get_flow_namespace(dev->mdev,
2332 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2333 build_leftovers_ft_param(&priority,
2334 &num_entries,
2335 &num_groups);
2336 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2337 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2338 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2339 allow_sniffer_and_nic_rx_shared_tir))
2340 return ERR_PTR(-ENOTSUPP);
2341
2342 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2343 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2344 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2345
2346 prio = &dev->flow_db.sniffer[ft_type];
2347 priority = 0;
2348 num_entries = 1;
2349 num_groups = 1;
038d2ef8
MG		 2350 }
2351
2352 if (!ns)
2353 return ERR_PTR(-ENOTSUPP);
2354
dac388ef
MG		 2355 if (num_entries > max_table_size)
2356 return ERR_PTR(-ENOMEM);
2357
038d2ef8
MG		 2358 ft = prio->flow_table;
2359 if (!ft) {
2360 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2361 num_entries,
d63cd286 2362 num_groups,
c9f1b073 2363 0, 0);
038d2ef8
MG		 2364
2365 if (!IS_ERR(ft)) {
2366 prio->refcount = 0;
2367 prio->flow_table = ft;
2368 } else {
2369 err = PTR_ERR(ft);
2370 }
2371 }
2372
2373 return err ? ERR_PTR(err) : prio;
2374}
2375
a550ddfc
YH		 2376static void set_underlay_qp(struct mlx5_ib_dev *dev,
2377 struct mlx5_flow_spec *spec,
2378 u32 underlay_qpn)
2379{
2380 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2381 spec->match_criteria,
2382 misc_parameters);
2383 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2384 misc_parameters);
2385
2386 if (underlay_qpn &&
2387 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2388 ft_field_support.bth_dst_qp)) {
2389 MLX5_SET(fte_match_set_misc,
2390 misc_params_v, bth_dst_qp, underlay_qpn);
2391 MLX5_SET(fte_match_set_misc,
2392 misc_params_c, bth_dst_qp, 0xffffff);
2393 }
2394}
2395
2396static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2397 struct mlx5_ib_flow_prio *ft_prio,
2398 const struct ib_flow_attr *flow_attr,
2399 struct mlx5_flow_destination *dst,
2400 u32 underlay_qpn)
038d2ef8
MG		 2401{
2402 struct mlx5_flow_table *ft = ft_prio->flow_table;
2403 struct mlx5_ib_flow_handler *handler;
66958ed9 2404 struct mlx5_flow_act flow_act = {0};
c5bb1730 2405 struct mlx5_flow_spec *spec;
a22ed86c 2406 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2407 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2408 unsigned int spec_index;
2ac693f9 2409 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2410 bool is_drop = false;
038d2ef8 2411 int err = 0;
a22ed86c 2412 int dest_num = 1;
038d2ef8 2413
19cc7524 2414 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2415 return ERR_PTR(-EINVAL);
2416
1b9a07ee 2417 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2418 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2419 if (!handler || !spec) {
038d2ef8
MG		 2420 err = -ENOMEM;
2421 goto free;
2422 }
2423
2424 INIT_LIST_HEAD(&handler->list);
2425
2426 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2427 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2428 spec->match_value,
2429 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2430 if (err < 0)
2431 goto free;
2432
2433 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2434 }
2435
a550ddfc
YH		 2436 if (!flow_is_multicast_only(flow_attr))
2437 set_underlay_qp(dev, spec, underlay_qpn);
2438
466fa6d2 2439 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2440 if (is_drop) {
2441 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2442 rule_dst = NULL;
2443 dest_num = 0;
2444 } else {
2445 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2446 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2447 }
2ac693f9
MR		 2448
2449 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2450 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2451 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2452 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2453 flow_tag, flow_attr->type);
2454 err = -EINVAL;
2455 goto free;
2456 }
2457 flow_act.flow_tag = flow_tag;
74491de9 2458 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2459 &flow_act,
a22ed86c 2460 rule_dst, dest_num);
038d2ef8
MG		 2461
2462 if (IS_ERR(handler->rule)) {
2463 err = PTR_ERR(handler->rule);
2464 goto free;
2465 }
2466
d9d4980a 2467 ft_prio->refcount++;
5497adc6 2468 handler->prio = ft_prio;
038d2ef8
MG		 2469
2470 ft_prio->flow_table = ft;
2471free:
2472 if (err)
2473 kfree(handler);
c5bb1730 2474 kvfree(spec);
038d2ef8
MG		 2475 return err ? ERR_PTR(err) : handler;
2476}
2477
a550ddfc
YH		 2478static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2479 struct mlx5_ib_flow_prio *ft_prio,
2480 const struct ib_flow_attr *flow_attr,
2481 struct mlx5_flow_destination *dst)
2482{
2483 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2484}
2485
35d19011
MG		 2486static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2487 struct mlx5_ib_flow_prio *ft_prio,
2488 struct ib_flow_attr *flow_attr,
2489 struct mlx5_flow_destination *dst)
2490{
2491 struct mlx5_ib_flow_handler *handler_dst = NULL;
2492 struct mlx5_ib_flow_handler *handler = NULL;
2493
2494 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2495 if (!IS_ERR(handler)) {
2496 handler_dst = create_flow_rule(dev, ft_prio,
2497 flow_attr, dst);
2498 if (IS_ERR(handler_dst)) {
74491de9 2499 mlx5_del_flow_rules(handler->rule);
d9d4980a 2500 ft_prio->refcount--;
35d19011
MG		 2501 kfree(handler);
2502 handler = handler_dst;
2503 } else {
2504 list_add(&handler_dst->list, &handler->list);
2505 }
2506 }
2507
2508 return handler;
2509}
038d2ef8
MG		 2510enum {
2511 LEFTOVERS_MC,
2512 LEFTOVERS_UC,
2513};
2514
2515static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2516 struct mlx5_ib_flow_prio *ft_prio,
2517 struct ib_flow_attr *flow_attr,
2518 struct mlx5_flow_destination *dst)
2519{
2520 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2521 struct mlx5_ib_flow_handler *handler = NULL;
2522
2523 static struct {
2524 struct ib_flow_attr flow_attr;
2525 struct ib_flow_spec_eth eth_flow;
2526 } leftovers_specs[] = {
2527 [LEFTOVERS_MC] = {
2528 .flow_attr = {
2529 .num_of_specs = 1,
2530 .size = sizeof(leftovers_specs[0])
2531 },
2532 .eth_flow = {
2533 .type = IB_FLOW_SPEC_ETH,
2534 .size = sizeof(struct ib_flow_spec_eth),
2535 .mask = {.dst_mac = {0x1} },
2536 .val = {.dst_mac = {0x1} }
2537 }
2538 },
2539 [LEFTOVERS_UC] = {
2540 .flow_attr = {
2541 .num_of_specs = 1,
2542 .size = sizeof(leftovers_specs[0])
2543 },
2544 .eth_flow = {
2545 .type = IB_FLOW_SPEC_ETH,
2546 .size = sizeof(struct ib_flow_spec_eth),
2547 .mask = {.dst_mac = {0x1} },
2548 .val = {.dst_mac = {} }
2549 }
2550 }
2551 };
2552
2553 handler = create_flow_rule(dev, ft_prio,
2554 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2555 dst);
2556 if (!IS_ERR(handler) &&
2557 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2558 handler_ucast = create_flow_rule(dev, ft_prio,
2559 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2560 dst);
2561 if (IS_ERR(handler_ucast)) {
74491de9 2562 mlx5_del_flow_rules(handler->rule);
d9d4980a 2563 ft_prio->refcount--;
038d2ef8
MG		 2564 kfree(handler);
2565 handler = handler_ucast;
2566 } else {
2567 list_add(&handler_ucast->list, &handler->list);
2568 }
2569 }
2570
2571 return handler;
2572}
2573
cc0e5d42
MG		 2574static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2575 struct mlx5_ib_flow_prio *ft_rx,
2576 struct mlx5_ib_flow_prio *ft_tx,
2577 struct mlx5_flow_destination *dst)
2578{
2579 struct mlx5_ib_flow_handler *handler_rx;
2580 struct mlx5_ib_flow_handler *handler_tx;
2581 int err;
2582 static const struct ib_flow_attr flow_attr = {
2583 .num_of_specs = 0,
2584 .size = sizeof(flow_attr)
2585 };
2586
2587 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2588 if (IS_ERR(handler_rx)) {
2589 err = PTR_ERR(handler_rx);
2590 goto err;
2591 }
2592
2593 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2594 if (IS_ERR(handler_tx)) {
2595 err = PTR_ERR(handler_tx);
2596 goto err_tx;
2597 }
2598
2599 list_add(&handler_tx->list, &handler_rx->list);
2600
2601 return handler_rx;
2602
2603err_tx:
74491de9 2604 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2605 ft_rx->refcount--;
2606 kfree(handler_rx);
2607err:
2608 return ERR_PTR(err);
2609}
2610
038d2ef8
MG		 2611static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2612 struct ib_flow_attr *flow_attr,
2613 int domain)
2614{
2615 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2616 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2617 struct mlx5_ib_flow_handler *handler = NULL;
2618 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2619 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2620 struct mlx5_ib_flow_prio *ft_prio;
2621 int err;
a550ddfc 2622 int underlay_qpn;
038d2ef8
MG		 2623
2624 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2625 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2626
2627 if (domain != IB_FLOW_DOMAIN_USER ||
2628 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2629 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2630 return ERR_PTR(-EINVAL);
2631
2632 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2633 if (!dst)
2634 return ERR_PTR(-ENOMEM);
2635
2636 mutex_lock(&dev->flow_db.lock);
2637
cc0e5d42 2638 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2639 if (IS_ERR(ft_prio)) {
2640 err = PTR_ERR(ft_prio);
2641 goto unlock;
2642 }
cc0e5d42
MG		 2643 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2644 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2645 if (IS_ERR(ft_prio_tx)) {
2646 err = PTR_ERR(ft_prio_tx);
2647 ft_prio_tx = NULL;
2648 goto destroy_ft;
2649 }
2650 }
038d2ef8
MG		 2651
2652 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2653 if (mqp->flags & MLX5_IB_QP_RSS)
2654 dst->tir_num = mqp->rss_qp.tirn;
2655 else
2656 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2657
2658 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2659 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2660 handler = create_dont_trap_rule(dev, ft_prio,
2661 flow_attr, dst);
2662 } else {
a550ddfc
YH		 2663 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2664 mqp->underlay_qpn : 0;
2665 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2666 dst, underlay_qpn);
35d19011 2667 }
038d2ef8
MG		 2668 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2669 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2670 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2671 dst);
cc0e5d42
MG		 2672 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2673 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2674 } else {
2675 err = -EINVAL;
2676 goto destroy_ft;
2677 }
2678
2679 if (IS_ERR(handler)) {
2680 err = PTR_ERR(handler);
2681 handler = NULL;
2682 goto destroy_ft;
2683 }
2684
038d2ef8
MG		 2685 mutex_unlock(&dev->flow_db.lock);
2686 kfree(dst);
2687
2688 return &handler->ibflow;
2689
2690destroy_ft:
2691 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2692 if (ft_prio_tx)
2693 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2694unlock:
2695 mutex_unlock(&dev->flow_db.lock);
2696 kfree(dst);
2697 kfree(handler);
2698 return ERR_PTR(err);
2699}
2700
e126ba97
EC		 2701static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2702{
2703 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2704 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2705 int err;
2706
81e30880
YH		 2707 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2708 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2709 return -EOPNOTSUPP;
2710 }
2711
9603b61d 2712 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2713 if (err)
2714 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2715 ibqp->qp_num, gid->raw);
2716
2717 return err;
2718}
2719
2720static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2721{
2722 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2723 int err;
2724
9603b61d 2725 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2726 if (err)
2727 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2728 ibqp->qp_num, gid->raw);
2729
2730 return err;
2731}
2732
2733static int init_node_data(struct mlx5_ib_dev *dev)
2734{
1b5daf11 2735 int err;
e126ba97 2736
1b5daf11 2737 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2738 if (err)
1b5daf11 2739 return err;
e126ba97 2740
1b5daf11 2741 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2742
1b5daf11 2743 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2744}
2745
2746static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2747 char *buf)
2748{
2749 struct mlx5_ib_dev *dev =
2750 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2751
9603b61d 2752 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2753}
2754
2755static ssize_t show_reg_pages(struct device *device,
2756 struct device_attribute *attr, char *buf)
2757{
2758 struct mlx5_ib_dev *dev =
2759 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2760
6aec21f6 2761 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2762}
2763
2764static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2765 char *buf)
2766{
2767 struct mlx5_ib_dev *dev =
2768 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2769 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2770}
2771
e126ba97
EC		 2772static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2773 char *buf)
2774{
2775 struct mlx5_ib_dev *dev =
2776 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2777 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2778}
2779
2780static ssize_t show_board(struct device *device, struct device_attribute *attr,
2781 char *buf)
2782{
2783 struct mlx5_ib_dev *dev =
2784 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2785 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2786 dev->mdev->board_id);
e126ba97
EC		 2787}
2788
2789static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2790static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2791static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2792static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2793static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2794
2795static struct device_attribute *mlx5_class_attributes[] = {
2796 &dev_attr_hw_rev,
e126ba97
EC		 2797 &dev_attr_hca_type,
2798 &dev_attr_board_id,
2799 &dev_attr_fw_pages,
2800 &dev_attr_reg_pages,
2801};
2802
7722f47e
HE		 2803static void pkey_change_handler(struct work_struct *work)
2804{
2805 struct mlx5_ib_port_resources *ports =
2806 container_of(work, struct mlx5_ib_port_resources,
2807 pkey_change_work);
2808
2809 mutex_lock(&ports->devr->mutex);
2810 mlx5_ib_gsi_pkey_change(ports->gsi);
2811 mutex_unlock(&ports->devr->mutex);
2812}
2813
89ea94a7
MG		 2814static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2815{
2816 struct mlx5_ib_qp *mqp;
2817 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2818 struct mlx5_core_cq *mcq;
2819 struct list_head cq_armed_list;
2820 unsigned long flags_qp;
2821 unsigned long flags_cq;
2822 unsigned long flags;
2823
2824 INIT_LIST_HEAD(&cq_armed_list);
2825
2826 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2827 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2828 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2829 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2830 if (mqp->sq.tail != mqp->sq.head) {
2831 send_mcq = to_mcq(mqp->ibqp.send_cq);
2832 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2833 if (send_mcq->mcq.comp &&
2834 mqp->ibqp.send_cq->comp_handler) {
2835 if (!send_mcq->mcq.reset_notify_added) {
2836 send_mcq->mcq.reset_notify_added = 1;
2837 list_add_tail(&send_mcq->mcq.reset_notify,
2838 &cq_armed_list);
2839 }
2840 }
2841 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2842 }
2843 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2844 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2845 /* no handling is needed for SRQ */
2846 if (!mqp->ibqp.srq) {
2847 if (mqp->rq.tail != mqp->rq.head) {
2848 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2849 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2850 if (recv_mcq->mcq.comp &&
2851 mqp->ibqp.recv_cq->comp_handler) {
2852 if (!recv_mcq->mcq.reset_notify_added) {
2853 recv_mcq->mcq.reset_notify_added = 1;
2854 list_add_tail(&recv_mcq->mcq.reset_notify,
2855 &cq_armed_list);
2856 }
2857 }
2858 spin_unlock_irqrestore(&recv_mcq->lock,
2859 flags_cq);
2860 }
2861 }
2862 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2863 }
2864 /*At that point all inflight post send were put to be executed as of we
2865 * lock/unlock above locks Now need to arm all involved CQs.
2866 */
2867 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2868 mcq->comp(mcq);
2869 }
2870 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2871}
2872
03404e8a
MG		 2873static void delay_drop_handler(struct work_struct *work)
2874{
2875 int err;
2876 struct mlx5_ib_delay_drop *delay_drop =
2877 container_of(work, struct mlx5_ib_delay_drop,
2878 delay_drop_work);
2879
fe248c3a
MG		 2880 atomic_inc(&delay_drop->events_cnt);
2881
03404e8a
MG		 2882 mutex_lock(&delay_drop->lock);
2883 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
2884 delay_drop->timeout);
2885 if (err) {
2886 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2887 delay_drop->timeout);
2888 delay_drop->activate = false;
2889 }
2890 mutex_unlock(&delay_drop->lock);
2891}
2892
9603b61d 2893static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2894 enum mlx5_dev_event event, unsigned long param)
e126ba97 2895{
9603b61d 2896 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2897 struct ib_event ibev;
dbaaff2a 2898 bool fatal = false;
e126ba97
EC		 2899 u8 port = 0;
2900
2901 switch (event) {
2902 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2903 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2904 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2905 fatal = true;
e126ba97
EC		 2906 break;
2907
2908 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2909 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2910 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2911 port = (u8)param;
5ec8c83e
AH		 2912
2913 /* In RoCE, port up/down events are handled in
2914 * mlx5_netdev_event().
2915 */
2916 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2917 IB_LINK_LAYER_ETHERNET)
2918 return;
2919
2920 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2921 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2922 break;
2923
e126ba97
EC		 2924 case MLX5_DEV_EVENT_LID_CHANGE:
2925 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2926 port = (u8)param;
e126ba97
EC		 2927 break;
2928
2929 case MLX5_DEV_EVENT_PKEY_CHANGE:
2930 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2931 port = (u8)param;
7722f47e
HE		 2932
2933 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2934 break;
2935
2936 case MLX5_DEV_EVENT_GUID_CHANGE:
2937 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2938 port = (u8)param;
e126ba97
EC		 2939 break;
2940
2941 case MLX5_DEV_EVENT_CLIENT_REREG:
2942 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2943 port = (u8)param;
e126ba97 2944 break;
03404e8a
MG		 2945 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
2946 schedule_work(&ibdev->delay_drop.delay_drop_work);
2947 goto out;
bdc37924 2948 default:
03404e8a 2949 goto out;
e126ba97
EC		 2950 }
2951
2952 ibev.device = &ibdev->ib_dev;
2953 ibev.element.port_num = port;
2954
a0c84c32
EC		 2955 if (port < 1 || port > ibdev->num_ports) {
2956 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 2957 goto out;
a0c84c32
EC		 2958 }
2959
e126ba97
EC		 2960 if (ibdev->ib_active)
2961 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2962
2963 if (fatal)
2964 ibdev->ib_active = false;
03404e8a
MG		 2965
2966out:
2967 return;
e126ba97
EC		 2968}
2969
c43f1112
MG		 2970static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2971{
2972 struct mlx5_hca_vport_context vport_ctx;
2973 int err;
2974 int port;
2975
2976 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2977 dev->mdev->port_caps[port - 1].has_smi = false;
2978 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2979 MLX5_CAP_PORT_TYPE_IB) {
2980 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2981 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2982 port, 0,
2983 &vport_ctx);
2984 if (err) {
2985 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2986 port, err);
2987 return err;
2988 }
2989 dev->mdev->port_caps[port - 1].has_smi =
2990 vport_ctx.has_smi;
2991 } else {
2992 dev->mdev->port_caps[port - 1].has_smi = true;
2993 }
2994 }
2995 }
2996 return 0;
2997}
2998
e126ba97
EC		 2999static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3000{
3001 int port;
3002
938fe83c 3003 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 3004 mlx5_query_ext_port_caps(dev, port);
3005}
3006
3007static int get_port_caps(struct mlx5_ib_dev *dev)
3008{
3009 struct ib_device_attr *dprops = NULL;
3010 struct ib_port_attr *pprops = NULL;
f614fc15 3011 int err = -ENOMEM;
e126ba97 3012 int port;
2528e33e 3013 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3014
3015 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3016 if (!pprops)
3017 goto out;
3018
3019 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3020 if (!dprops)
3021 goto out;
3022
c43f1112
MG		 3023 err = set_has_smi_cap(dev);
3024 if (err)
3025 goto out;
3026
2528e33e 3027 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3028 if (err) {
3029 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3030 goto out;
3031 }
3032
938fe83c 3033 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 3034 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 3035 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3036 if (err) {
938fe83c
SM		 3037 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3038 port, err);
e126ba97
EC		 3039 break;
3040 }
938fe83c
SM		 3041 dev->mdev->port_caps[port - 1].pkey_table_len =
3042 dprops->max_pkeys;
3043 dev->mdev->port_caps[port - 1].gid_table_len =
3044 pprops->gid_tbl_len;
e126ba97
EC		 3045 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
3046 dprops->max_pkeys, pprops->gid_tbl_len);
3047 }
3048
3049out:
3050 kfree(pprops);
3051 kfree(dprops);
3052
3053 return err;
3054}
3055
3056static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3057{
3058 int err;
3059
3060 err = mlx5_mr_cache_cleanup(dev);
3061 if (err)
3062 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3063
3064 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3065 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3066 ib_dealloc_pd(dev->umrc.pd);
3067}
3068
3069enum {
3070 MAX_UMR_WR = 128,
3071};
3072
3073static int create_umr_res(struct mlx5_ib_dev *dev)
3074{
3075 struct ib_qp_init_attr *init_attr = NULL;
3076 struct ib_qp_attr *attr = NULL;
3077 struct ib_pd *pd;
3078 struct ib_cq *cq;
3079 struct ib_qp *qp;
e126ba97
EC		 3080 int ret;
3081
3082 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3083 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3084 if (!attr || !init_attr) {
3085 ret = -ENOMEM;
3086 goto error_0;
3087 }
3088
ed082d36 3089 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3090 if (IS_ERR(pd)) {
3091 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3092 ret = PTR_ERR(pd);
3093 goto error_0;
3094 }
3095
add08d76 3096 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3097 if (IS_ERR(cq)) {
3098 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3099 ret = PTR_ERR(cq);
3100 goto error_2;
3101 }
e126ba97
EC		 3102
3103 init_attr->send_cq = cq;
3104 init_attr->recv_cq = cq;
3105 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3106 init_attr->cap.max_send_wr = MAX_UMR_WR;
3107 init_attr->cap.max_send_sge = 1;
3108 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3109 init_attr->port_num = 1;
3110 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3111 if (IS_ERR(qp)) {
3112 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3113 ret = PTR_ERR(qp);
3114 goto error_3;
3115 }
3116 qp->device = &dev->ib_dev;
3117 qp->real_qp = qp;
3118 qp->uobject = NULL;
3119 qp->qp_type = MLX5_IB_QPT_REG_UMR;
3120
3121 attr->qp_state = IB_QPS_INIT;
3122 attr->port_num = 1;
3123 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3124 IB_QP_PORT, NULL);
3125 if (ret) {
3126 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3127 goto error_4;
3128 }
3129
3130 memset(attr, 0, sizeof(*attr));
3131 attr->qp_state = IB_QPS_RTR;
3132 attr->path_mtu = IB_MTU_256;
3133
3134 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3135 if (ret) {
3136 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3137 goto error_4;
3138 }
3139
3140 memset(attr, 0, sizeof(*attr));
3141 attr->qp_state = IB_QPS_RTS;
3142 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3143 if (ret) {
3144 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3145 goto error_4;
3146 }
3147
3148 dev->umrc.qp = qp;
3149 dev->umrc.cq = cq;
e126ba97
EC		 3150 dev->umrc.pd = pd;
3151
3152 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3153 ret = mlx5_mr_cache_init(dev);
3154 if (ret) {
3155 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3156 goto error_4;
3157 }
3158
3159 kfree(attr);
3160 kfree(init_attr);
3161
3162 return 0;
3163
3164error_4:
3165 mlx5_ib_destroy_qp(qp);
3166
3167error_3:
add08d76 3168 ib_free_cq(cq);
e126ba97
EC		 3169
3170error_2:
e126ba97
EC		 3171 ib_dealloc_pd(pd);
3172
3173error_0:
3174 kfree(attr);
3175 kfree(init_attr);
3176 return ret;
3177}
3178
6e8484c5
MG		 3179static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3180{
3181 switch (umr_fence_cap) {
3182 case MLX5_CAP_UMR_FENCE_NONE:
3183 return MLX5_FENCE_MODE_NONE;
3184 case MLX5_CAP_UMR_FENCE_SMALL:
3185 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3186 default:
3187 return MLX5_FENCE_MODE_STRONG_ORDERING;
3188 }
3189}
3190
e126ba97
EC		 3191static int create_dev_resources(struct mlx5_ib_resources *devr)
3192{
3193 struct ib_srq_init_attr attr;
3194 struct mlx5_ib_dev *dev;
bcf4c1ea 3195 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3196 int port;
e126ba97
EC		 3197 int ret = 0;
3198
3199 dev = container_of(devr, struct mlx5_ib_dev, devr);
3200
d16e91da
HE		 3201 mutex_init(&devr->mutex);
3202
e126ba97
EC		 3203 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3204 if (IS_ERR(devr->p0)) {
3205 ret = PTR_ERR(devr->p0);
3206 goto error0;
3207 }
3208 devr->p0->device = &dev->ib_dev;
3209 devr->p0->uobject = NULL;
3210 atomic_set(&devr->p0->usecnt, 0);
3211
bcf4c1ea 3212 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3213 if (IS_ERR(devr->c0)) {
3214 ret = PTR_ERR(devr->c0);
3215 goto error1;
3216 }
3217 devr->c0->device = &dev->ib_dev;
3218 devr->c0->uobject = NULL;
3219 devr->c0->comp_handler = NULL;
3220 devr->c0->event_handler = NULL;
3221 devr->c0->cq_context = NULL;
3222 atomic_set(&devr->c0->usecnt, 0);
3223
3224 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3225 if (IS_ERR(devr->x0)) {
3226 ret = PTR_ERR(devr->x0);
3227 goto error2;
3228 }
3229 devr->x0->device = &dev->ib_dev;
3230 devr->x0->inode = NULL;
3231 atomic_set(&devr->x0->usecnt, 0);
3232 mutex_init(&devr->x0->tgt_qp_mutex);
3233 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3234
3235 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3236 if (IS_ERR(devr->x1)) {
3237 ret = PTR_ERR(devr->x1);
3238 goto error3;
3239 }
3240 devr->x1->device = &dev->ib_dev;
3241 devr->x1->inode = NULL;
3242 atomic_set(&devr->x1->usecnt, 0);
3243 mutex_init(&devr->x1->tgt_qp_mutex);
3244 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3245
3246 memset(&attr, 0, sizeof(attr));
3247 attr.attr.max_sge = 1;
3248 attr.attr.max_wr = 1;
3249 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3250 attr.ext.cq = devr->c0;
e126ba97
EC		 3251 attr.ext.xrc.xrcd = devr->x0;
3252
3253 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3254 if (IS_ERR(devr->s0)) {
3255 ret = PTR_ERR(devr->s0);
3256 goto error4;
3257 }
3258 devr->s0->device = &dev->ib_dev;
3259 devr->s0->pd = devr->p0;
3260 devr->s0->uobject = NULL;
3261 devr->s0->event_handler = NULL;
3262 devr->s0->srq_context = NULL;
3263 devr->s0->srq_type = IB_SRQT_XRC;
3264 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3265 devr->s0->ext.cq = devr->c0;
e126ba97 3266 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3267 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3268 atomic_inc(&devr->p0->usecnt);
3269 atomic_set(&devr->s0->usecnt, 0);
3270
4aa17b28
HA		 3271 memset(&attr, 0, sizeof(attr));
3272 attr.attr.max_sge = 1;
3273 attr.attr.max_wr = 1;
3274 attr.srq_type = IB_SRQT_BASIC;
3275 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3276 if (IS_ERR(devr->s1)) {
3277 ret = PTR_ERR(devr->s1);
3278 goto error5;
3279 }
3280 devr->s1->device = &dev->ib_dev;
3281 devr->s1->pd = devr->p0;
3282 devr->s1->uobject = NULL;
3283 devr->s1->event_handler = NULL;
3284 devr->s1->srq_context = NULL;
3285 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3286 devr->s1->ext.cq = devr->c0;
4aa17b28 3287 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3288 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3289
7722f47e
HE		 3290 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3291 INIT_WORK(&devr->ports[port].pkey_change_work,
3292 pkey_change_handler);
3293 devr->ports[port].devr = devr;
3294 }
3295
e126ba97
EC		 3296 return 0;
3297
4aa17b28
HA		 3298error5:
3299 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3300error4:
3301 mlx5_ib_dealloc_xrcd(devr->x1);
3302error3:
3303 mlx5_ib_dealloc_xrcd(devr->x0);
3304error2:
3305 mlx5_ib_destroy_cq(devr->c0);
3306error1:
3307 mlx5_ib_dealloc_pd(devr->p0);
3308error0:
3309 return ret;
3310}
3311
3312static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3313{
7722f47e
HE		 3314 struct mlx5_ib_dev *dev =
3315 container_of(devr, struct mlx5_ib_dev, devr);
3316 int port;
3317
4aa17b28 3318 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3319 mlx5_ib_destroy_srq(devr->s0);
3320 mlx5_ib_dealloc_xrcd(devr->x0);
3321 mlx5_ib_dealloc_xrcd(devr->x1);
3322 mlx5_ib_destroy_cq(devr->c0);
3323 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3324
3325 /* Make sure no change P_Key work items are still executing */
3326 for (port = 0; port < dev->num_ports; ++port)
3327 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3328}
3329
e53505a8
AS		 3330static u32 get_core_cap_flags(struct ib_device *ibdev)
3331{
3332 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3333 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3334 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3335 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3336 u32 ret = 0;
3337
3338 if (ll == IB_LINK_LAYER_INFINIBAND)
3339 return RDMA_CORE_PORT_IBA_IB;
3340
72cd5717
OG		 3341 ret = RDMA_CORE_PORT_RAW_PACKET;
3342
e53505a8 3343 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3344 return ret;
e53505a8
AS		 3345
3346 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3347 return ret;
e53505a8
AS		 3348
3349 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3350 ret |= RDMA_CORE_PORT_IBA_ROCE;
3351
3352 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3353 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3354
3355 return ret;
3356}
3357
7738613e
IW		 3358static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3359 struct ib_port_immutable *immutable)
3360{
3361 struct ib_port_attr attr;
ca5b91d6
OG		 3362 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3363 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3364 int err;
3365
c4550c63
OG		 3366 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3367
3368 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3369 if (err)
3370 return err;
3371
3372 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3373 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3374 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3375 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3376 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3377
3378 return 0;
3379}
3380
9abb0d1b 3381static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3382{
3383 struct mlx5_ib_dev *dev =
3384 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3385 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3386 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3387 fw_rev_sub(dev->mdev));
c7342823
IW		 3388}
3389
45f95acd 3390static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3391{
3392 struct mlx5_core_dev *mdev = dev->mdev;
3393 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3394 MLX5_FLOW_NAMESPACE_LAG);
3395 struct mlx5_flow_table *ft;
3396 int err;
3397
3398 if (!ns || !mlx5_lag_is_active(mdev))
3399 return 0;
3400
3401 err = mlx5_cmd_create_vport_lag(mdev);
3402 if (err)
3403 return err;
3404
3405 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3406 if (IS_ERR(ft)) {
3407 err = PTR_ERR(ft);
3408 goto err_destroy_vport_lag;
3409 }
3410
3411 dev->flow_db.lag_demux_ft = ft;
3412 return 0;
3413
3414err_destroy_vport_lag:
3415 mlx5_cmd_destroy_vport_lag(mdev);
3416 return err;
3417}
3418
45f95acd 3419static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3420{
3421 struct mlx5_core_dev *mdev = dev->mdev;
3422
3423 if (dev->flow_db.lag_demux_ft) {
3424 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3425 dev->flow_db.lag_demux_ft = NULL;
3426
3427 mlx5_cmd_destroy_vport_lag(mdev);
3428 }
3429}
3430
d012f5d6
OG		 3431static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3432{
3433 int err;
3434
3435 dev->roce.nb.notifier_call = mlx5_netdev_event;
3436 err = register_netdevice_notifier(&dev->roce.nb);
3437 if (err) {
3438 dev->roce.nb.notifier_call = NULL;
3439 return err;
3440 }
3441
3442 return 0;
3443}
3444
3445static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3446{
3447 if (dev->roce.nb.notifier_call) {
3448 unregister_netdevice_notifier(&dev->roce.nb);
3449 dev->roce.nb.notifier_call = NULL;
3450 }
3451}
3452
45f95acd 3453static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3454{
e53505a8
AS		 3455 int err;
3456
d012f5d6
OG		 3457 err = mlx5_add_netdev_notifier(dev);
3458 if (err)
e53505a8
AS		 3459 return err;
3460
ca5b91d6
OG		 3461 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3462 err = mlx5_nic_vport_enable_roce(dev->mdev);
3463 if (err)
3464 goto err_unregister_netdevice_notifier;
3465 }
e53505a8 3466
45f95acd 3467 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3468 if (err)
3469 goto err_disable_roce;
3470
e53505a8
AS		 3471 return 0;
3472
9ef9c640 3473err_disable_roce:
ca5b91d6
OG		 3474 if (MLX5_CAP_GEN(dev->mdev, roce))
3475 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3476
e53505a8 3477err_unregister_netdevice_notifier:
d012f5d6 3478 mlx5_remove_netdev_notifier(dev);
e53505a8 3479 return err;
fc24fc5e
AS		 3480}
3481
45f95acd 3482static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3483{
45f95acd 3484 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3485 if (MLX5_CAP_GEN(dev->mdev, roce))
3486 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3487}
3488
e1f24a79 3489struct mlx5_ib_counter {
7c16f477
KH		 3490 const char *name;
3491 size_t offset;
3492};
3493
3494#define INIT_Q_COUNTER(_name) \
3495 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3496
e1f24a79 3497static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3498 INIT_Q_COUNTER(rx_write_requests),
3499 INIT_Q_COUNTER(rx_read_requests),
3500 INIT_Q_COUNTER(rx_atomic_requests),
3501 INIT_Q_COUNTER(out_of_buffer),
3502};
3503
e1f24a79 3504static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3505 INIT_Q_COUNTER(out_of_sequence),
3506};
3507
e1f24a79 3508static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3509 INIT_Q_COUNTER(duplicate_request),
3510 INIT_Q_COUNTER(rnr_nak_retry_err),
3511 INIT_Q_COUNTER(packet_seq_err),
3512 INIT_Q_COUNTER(implied_nak_seq_err),
3513 INIT_Q_COUNTER(local_ack_timeout_err),
3514};
3515
e1f24a79
PP		 3516#define INIT_CONG_COUNTER(_name) \
3517 { .name = #_name, .offset = \
3518 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3519
3520static const struct mlx5_ib_counter cong_cnts[] = {
3521 INIT_CONG_COUNTER(rp_cnp_ignored),
3522 INIT_CONG_COUNTER(rp_cnp_handled),
3523 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3524 INIT_CONG_COUNTER(np_cnp_sent),
3525};
3526
58dcb60a
PP		 3527static const struct mlx5_ib_counter extended_err_cnts[] = {
3528 INIT_Q_COUNTER(resp_local_length_error),
3529 INIT_Q_COUNTER(resp_cqe_error),
3530 INIT_Q_COUNTER(req_cqe_error),
3531 INIT_Q_COUNTER(req_remote_invalid_request),
3532 INIT_Q_COUNTER(req_remote_access_errors),
3533 INIT_Q_COUNTER(resp_remote_access_errors),
3534 INIT_Q_COUNTER(resp_cqe_flush_error),
3535 INIT_Q_COUNTER(req_cqe_flush_error),
3536};
3537
e1f24a79 3538static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3539{
3540 unsigned int i;
3541
7c16f477 3542 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3543 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3544 dev->port[i].cnts.set_id);
3545 kfree(dev->port[i].cnts.names);
3546 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3547 }
3548}
3549
e1f24a79
PP		 3550static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3551 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3552{
3553 u32 num_counters;
3554
3555 num_counters = ARRAY_SIZE(basic_q_cnts);
3556
3557 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3558 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3559
3560 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3561 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3562
3563 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3564 num_counters += ARRAY_SIZE(extended_err_cnts);
3565
e1f24a79 3566 cnts->num_q_counters = num_counters;
7c16f477 3567
e1f24a79
PP		 3568 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3569 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3570 num_counters += ARRAY_SIZE(cong_cnts);
3571 }
3572
3573 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3574 if (!cnts->names)
7c16f477
KH		 3575 return -ENOMEM;
3576
e1f24a79
PP		 3577 cnts->offsets = kcalloc(num_counters,
3578 sizeof(cnts->offsets), GFP_KERNEL);
3579 if (!cnts->offsets)
7c16f477
KH		 3580 goto err_names;
3581
7c16f477
KH		 3582 return 0;
3583
3584err_names:
e1f24a79 3585 kfree(cnts->names);
7c16f477
KH		 3586 return -ENOMEM;
3587}
3588
e1f24a79
PP		 3589static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3590 const char **names,
3591 size_t *offsets)
7c16f477
KH		 3592{
3593 int i;
3594 int j = 0;
3595
3596 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3597 names[j] = basic_q_cnts[i].name;
3598 offsets[j] = basic_q_cnts[i].offset;
3599 }
3600
3601 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3602 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3603 names[j] = out_of_seq_q_cnts[i].name;
3604 offsets[j] = out_of_seq_q_cnts[i].offset;
3605 }
3606 }
3607
3608 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3609 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3610 names[j] = retrans_q_cnts[i].name;
3611 offsets[j] = retrans_q_cnts[i].offset;
3612 }
3613 }
e1f24a79 3614
58dcb60a
PP		 3615 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3616 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3617 names[j] = extended_err_cnts[i].name;
3618 offsets[j] = extended_err_cnts[i].offset;
3619 }
3620 }
3621
e1f24a79
PP		 3622 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3623 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3624 names[j] = cong_cnts[i].name;
3625 offsets[j] = cong_cnts[i].offset;
3626 }
3627 }
0837e86a
MB		 3628}
3629
e1f24a79 3630static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3631{
3632 int i;
3633 int ret;
3634
3635 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3636 struct mlx5_ib_port *port = &dev->port[i];
3637
0837e86a 3638 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3639 &port->cnts.set_id);
0837e86a
MB		 3640 if (ret) {
3641 mlx5_ib_warn(dev,
3642 "couldn't allocate queue counter for port %d, err %d\n",
3643 i + 1, ret);
3644 goto dealloc_counters;
3645 }
7c16f477 3646
e1f24a79 3647 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3648 if (ret)
3649 goto dealloc_counters;
3650
e1f24a79
PP		 3651 mlx5_ib_fill_counters(dev, port->cnts.names,
3652 port->cnts.offsets);
0837e86a
MB		 3653 }
3654
3655 return 0;
3656
3657dealloc_counters:
3658 while (--i >= 0)
3659 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3660 dev->port[i].cnts.set_id);
0837e86a
MB		 3661
3662 return ret;
3663}
3664
0ad17a8f
MB		 3665static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3666 u8 port_num)
3667{
7c16f477
KH		 3668 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3669 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3670
3671 /* We support only per port stats */
3672 if (port_num == 0)
3673 return NULL;
3674
e1f24a79
PP		 3675 return rdma_alloc_hw_stats_struct(port->cnts.names,
3676 port->cnts.num_q_counters +
3677 port->cnts.num_cong_counters,
0ad17a8f
MB		 3678 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3679}
3680
e1f24a79
PP		 3681static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3682 struct mlx5_ib_port *port,
3683 struct rdma_hw_stats *stats)
0ad17a8f 3684{
0ad17a8f
MB		 3685 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3686 void *out;
3687 __be32 val;
e1f24a79 3688 int ret, i;
0ad17a8f 3689
1b9a07ee 3690 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3691 if (!out)
3692 return -ENOMEM;
3693
3694 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3695 port->cnts.set_id, 0,
0ad17a8f
MB		 3696 out, outlen);
3697 if (ret)
3698 goto free;
3699
e1f24a79
PP		 3700 for (i = 0; i < port->cnts.num_q_counters; i++) {
3701 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3702 stats->value[i] = (u64)be32_to_cpu(val);
3703 }
7c16f477 3704
0ad17a8f
MB		 3705free:
3706 kvfree(out);
e1f24a79
PP		 3707 return ret;
3708}
3709
3710static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3711 struct mlx5_ib_port *port,
3712 struct rdma_hw_stats *stats)
3713{
3714 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3715 void *out;
3716 int ret, i;
3717 int offset = port->cnts.num_q_counters;
3718
1b9a07ee 3719 out = kvzalloc(outlen, GFP_KERNEL);
e1f24a79
PP		 3720 if (!out)
3721 return -ENOMEM;
3722
3723 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3724 if (ret)
3725 goto free;
3726
3727 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3728 stats->value[i + offset] =
3729 be64_to_cpup((__be64 *)(out +
3730 port->cnts.offsets[i + offset]));
3731 }
3732
3733free:
3734 kvfree(out);
3735 return ret;
3736}
3737
3738static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3739 struct rdma_hw_stats *stats,
3740 u8 port_num, int index)
3741{
3742 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3743 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3744 int ret, num_counters;
3745
3746 if (!stats)
3747 return -EINVAL;
3748
3749 ret = mlx5_ib_query_q_counters(dev, port, stats);
3750 if (ret)
3751 return ret;
3752 num_counters = port->cnts.num_q_counters;
3753
3754 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3755 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3756 if (ret)
3757 return ret;
3758 num_counters += port->cnts.num_cong_counters;
3759 }
3760
3761 return num_counters;
0ad17a8f
MB		 3762}
3763
8e959601
NV		 3764static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3765{
3766 return mlx5_rdma_netdev_free(netdev);
3767}
3768
693dfd5a
ES		 3769static struct net_device*
3770mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3771 u8 port_num,
3772 enum rdma_netdev_t type,
3773 const char *name,
3774 unsigned char name_assign_type,
3775 void (*setup)(struct net_device *))
3776{
8e959601
NV		 3777 struct net_device *netdev;
3778 struct rdma_netdev *rn;
3779
693dfd5a
ES		 3780 if (type != RDMA_NETDEV_IPOIB)
3781 return ERR_PTR(-EOPNOTSUPP);
3782
8e959601
NV		 3783 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3784 name, setup);
3785 if (likely(!IS_ERR_OR_NULL(netdev))) {
3786 rn = netdev_priv(netdev);
3787 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3788 }
3789 return netdev;
693dfd5a
ES		 3790}
3791
fe248c3a
MG		 3792static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
3793{
3794 if (!dev->delay_drop.dbg)
3795 return;
3796 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
3797 kfree(dev->delay_drop.dbg);
3798 dev->delay_drop.dbg = NULL;
3799}
3800
03404e8a
MG		 3801static void cancel_delay_drop(struct mlx5_ib_dev *dev)
3802{
3803 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3804 return;
3805
3806 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 3807 delay_drop_debugfs_cleanup(dev);
3808}
3809
3810static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3811 size_t count, loff_t *pos)
3812{
3813 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3814 char lbuf[20];
3815 int len;
3816
3817 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3818 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3819}
3820
3821static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3822 size_t count, loff_t *pos)
3823{
3824 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3825 u32 timeout;
3826 u32 var;
3827
3828 if (kstrtouint_from_user(buf, count, 0, &var))
3829 return -EFAULT;
3830
3831 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3832 1000);
3833 if (timeout != var)
3834 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3835 timeout);
3836
3837 delay_drop->timeout = timeout;
3838
3839 return count;
3840}
3841
3842static const struct file_operations fops_delay_drop_timeout = {
3843 .owner = THIS_MODULE,
3844 .open = simple_open,
3845 .write = delay_drop_timeout_write,
3846 .read = delay_drop_timeout_read,
3847};
3848
3849static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
3850{
3851 struct mlx5_ib_dbg_delay_drop *dbg;
3852
3853 if (!mlx5_debugfs_root)
3854 return 0;
3855
3856 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
3857 if (!dbg)
3858 return -ENOMEM;
3859
cbafad87
SM		 3860 dev->delay_drop.dbg = dbg;
3861
fe248c3a
MG		 3862 dbg->dir_debugfs =
3863 debugfs_create_dir("delay_drop",
3864 dev->mdev->priv.dbg_root);
3865 if (!dbg->dir_debugfs)
cbafad87 3866 goto out_debugfs;
fe248c3a
MG		 3867
3868 dbg->events_cnt_debugfs =
3869 debugfs_create_atomic_t("num_timeout_events", 0400,
3870 dbg->dir_debugfs,
3871 &dev->delay_drop.events_cnt);
3872 if (!dbg->events_cnt_debugfs)
3873 goto out_debugfs;
3874
3875 dbg->rqs_cnt_debugfs =
3876 debugfs_create_atomic_t("num_rqs", 0400,
3877 dbg->dir_debugfs,
3878 &dev->delay_drop.rqs_cnt);
3879 if (!dbg->rqs_cnt_debugfs)
3880 goto out_debugfs;
3881
3882 dbg->timeout_debugfs =
3883 debugfs_create_file("timeout", 0600,
3884 dbg->dir_debugfs,
3885 &dev->delay_drop,
3886 &fops_delay_drop_timeout);
3887 if (!dbg->timeout_debugfs)
3888 goto out_debugfs;
3889
3890 return 0;
3891
3892out_debugfs:
3893 delay_drop_debugfs_cleanup(dev);
3894 return -ENOMEM;
03404e8a
MG		 3895}
3896
3897static void init_delay_drop(struct mlx5_ib_dev *dev)
3898{
3899 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
3900 return;
3901
3902 mutex_init(&dev->delay_drop.lock);
3903 dev->delay_drop.dev = dev;
3904 dev->delay_drop.activate = false;
3905 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
3906 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 3907 atomic_set(&dev->delay_drop.rqs_cnt, 0);
3908 atomic_set(&dev->delay_drop.events_cnt, 0);
3909
3910 if (delay_drop_debugfs_init(dev))
3911 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 3912}
3913
84305d71
LR		 3914static const struct cpumask *
3915mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 3916{
3917 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3918
3919 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
3920}
3921
9603b61d 3922static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3923{
e126ba97 3924 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3925 enum rdma_link_layer ll;
3926 int port_type_cap;
4babcf97 3927 const char *name;
e126ba97
EC		 3928 int err;
3929 int i;
3930
ebd61f68
AS		 3931 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3932 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3933
e126ba97
EC		 3934 printk_once(KERN_INFO "%s", mlx5_version);
3935
3936 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3937 if (!dev)
9603b61d 3938 return NULL;
e126ba97 3939
9603b61d 3940 dev->mdev = mdev;
e126ba97 3941
0837e86a
MB		 3942 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3943 GFP_KERNEL);
3944 if (!dev->port)
3945 goto err_dealloc;
3946
fc24fc5e 3947 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3948 err = get_port_caps(dev);
3949 if (err)
0837e86a 3950 goto err_free_port;
e126ba97 3951
1b5daf11
MD		 3952 if (mlx5_use_mad_ifc(dev))
3953 get_ext_port_caps(dev);
e126ba97 3954
4babcf97
AH		 3955 if (!mlx5_lag_is_active(mdev))
3956 name = "mlx5_%d";
3957 else
3958 name = "mlx5_bond_%d";
3959
3960 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3961 dev->ib_dev.owner = THIS_MODULE;
3962 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3963 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3964 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3965 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3966 dev->ib_dev.num_comp_vectors =
3967 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3968 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3969
3970 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3971 dev->ib_dev.uverbs_cmd_mask =
3972 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3973 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3974 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3975 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3976 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3977 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3978 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3979 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3980 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3981 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3982 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3983 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3984 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3985 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3986 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3987 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3988 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3989 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3990 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3991 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3992 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3993 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3994 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3995 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3996 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3997 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3998 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3999 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4000 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 4001 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
4002 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 4003
4004 dev->ib_dev.query_device = mlx5_ib_query_device;
4005 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 4006 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 4007 if (ll == IB_LINK_LAYER_ETHERNET)
4008 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 4009 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 4010 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4011 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 4012 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4013 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4014 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4015 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4016 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4017 dev->ib_dev.mmap = mlx5_ib_mmap;
4018 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4019 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4020 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4021 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4022 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4023 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4024 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4025 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4026 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4027 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4028 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4029 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4030 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4031 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4032 dev->ib_dev.post_send = mlx5_ib_post_send;
4033 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4034 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4035 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4036 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4037 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4038 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4039 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4040 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4041 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4042 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4043 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4044 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4045 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4046 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4047 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4048 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4049 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 4050 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 4051 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4052 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4053 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4054 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4055
eff901d3
EC		 4056 if (mlx5_core_is_pf(mdev)) {
4057 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4058 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4059 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4060 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4061 }
e126ba97 4062
7c2344c3
MG		 4063 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4064
938fe83c 4065 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 4066
6e8484c5
MG		 4067 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4068
d2370e0a
MB		 4069 if (MLX5_CAP_GEN(mdev, imaicl)) {
4070 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4071 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4072 dev->ib_dev.uverbs_cmd_mask |=
4073 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4074 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4075 }
4076
7c16f477 4077 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 4078 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4079 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4080 }
4081
938fe83c 4082 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4083 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4084 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4085 dev->ib_dev.uverbs_cmd_mask |=
4086 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4087 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4088 }
4089
81e30880
YH		 4090 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4091 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4092 dev->ib_dev.uverbs_ex_cmd_mask |=
4093 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4094 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4095
048ccca8 4096 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8 4097 IB_LINK_LAYER_ETHERNET) {
79b20a6c
YH		 4098 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4099 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4100 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 4101 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4102 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8 4103 dev->ib_dev.uverbs_ex_cmd_mask |=
79b20a6c
YH		 4104 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4105 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 4106 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4107 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4108 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 4109 }
e126ba97
EC		 4110 err = init_node_data(dev);
4111 if (err)
90be7c8a 4112 goto err_free_port;
e126ba97 4113
038d2ef8 4114 mutex_init(&dev->flow_db.lock);
e126ba97 4115 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 4116 INIT_LIST_HEAD(&dev->qp_list);
4117 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 4118
fc24fc5e 4119 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4120 err = mlx5_enable_eth(dev);
fc24fc5e 4121 if (err)
90be7c8a 4122 goto err_free_port;
fd65f1b8 4123 dev->roce.last_port_state = IB_PORT_DOWN;
fc24fc5e
AS		 4124 }
4125
e126ba97
EC		 4126 err = create_dev_resources(&dev->devr);
4127 if (err)
45f95acd 4128 goto err_disable_eth;
e126ba97 4129
6aec21f6 4130 err = mlx5_ib_odp_init_one(dev);
281d1a92 4131 if (err)
e126ba97
EC		 4132 goto err_rsrc;
4133
45bded2c 4134 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 4135 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 4136 if (err)
4137 goto err_odp;
4138 }
6aec21f6 4139
4a2da0b8
PP		 4140 err = mlx5_ib_init_cong_debugfs(dev);
4141 if (err)
4142 goto err_cnt;
4143
5fe9dec0
EC		 4144 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4145 if (!dev->mdev->priv.uar)
4a2da0b8 4146 goto err_cong;
5fe9dec0
EC		 4147
4148 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4149 if (err)
4150 goto err_uar_page;
4151
4152 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4153 if (err)
4154 goto err_bfreg;
4155
0837e86a
MB		 4156 err = ib_register_device(&dev->ib_dev, NULL);
4157 if (err)
5fe9dec0 4158 goto err_fp_bfreg;
0837e86a 4159
e126ba97
EC		 4160 err = create_umr_res(dev);
4161 if (err)
4162 goto err_dev;
4163
03404e8a
MG		 4164 init_delay_drop(dev);
4165
e126ba97 4166 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4167 err = device_create_file(&dev->ib_dev.dev,
4168 mlx5_class_attributes[i]);
4169 if (err)
03404e8a 4170 goto err_delay_drop;
e126ba97
EC		 4171 }
4172
c85023e1
HN		 4173 if ((MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4174 MLX5_CAP_GEN(mdev, disable_local_lb))
4175 mutex_init(&dev->lb_mutex);
4176
e126ba97
EC		 4177 dev->ib_active = true;
4178
9603b61d 4179 return dev;
e126ba97 4180
03404e8a
MG		 4181err_delay_drop:
4182 cancel_delay_drop(dev);
e126ba97
EC		 4183 destroy_umrc_res(dev);
4184
4185err_dev:
4186 ib_unregister_device(&dev->ib_dev);
4187
5fe9dec0
EC		 4188err_fp_bfreg:
4189 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4190
4191err_bfreg:
4192 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4193
4194err_uar_page:
4195 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4196
4a2da0b8 4197err_cong:
e19cd282
PP		 4198 mlx5_ib_cleanup_cong_debugfs(dev);
4199err_cnt:
45bded2c 4200 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4201 mlx5_ib_dealloc_counters(dev);
0837e86a 4202
6aec21f6
HE		 4203err_odp:
4204 mlx5_ib_odp_remove_one(dev);
4205
e126ba97
EC		 4206err_rsrc:
4207 destroy_dev_resources(&dev->devr);
4208
45f95acd 4209err_disable_eth:
5ec8c83e 4210 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 4211 mlx5_disable_eth(dev);
d012f5d6 4212 mlx5_remove_netdev_notifier(dev);
5ec8c83e 4213 }
fc24fc5e 4214
0837e86a
MB		 4215err_free_port:
4216 kfree(dev->port);
4217
9603b61d 4218err_dealloc:
e126ba97
EC		 4219 ib_dealloc_device((struct ib_device *)dev);
4220
9603b61d 4221 return NULL;
e126ba97
EC		 4222}
4223
9603b61d 4224static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4225{
9603b61d 4226 struct mlx5_ib_dev *dev = context;
fc24fc5e 4227 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 4228
03404e8a 4229 cancel_delay_drop(dev);
d012f5d6 4230 mlx5_remove_netdev_notifier(dev);
e126ba97 4231 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 4232 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4233 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4234 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
4a2da0b8 4235 mlx5_ib_cleanup_cong_debugfs(dev);
45bded2c 4236 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 4237 mlx5_ib_dealloc_counters(dev);
eefd56e5 4238 destroy_umrc_res(dev);
6aec21f6 4239 mlx5_ib_odp_remove_one(dev);
e126ba97 4240 destroy_dev_resources(&dev->devr);
fc24fc5e 4241 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 4242 mlx5_disable_eth(dev);
0837e86a 4243 kfree(dev->port);
e126ba97
EC		 4244 ib_dealloc_device(&dev->ib_dev);
4245}
4246
9603b61d
JM		 4247static struct mlx5_interface mlx5_ib_interface = {
4248 .add = mlx5_ib_add,
4249 .remove = mlx5_ib_remove,
4250 .event = mlx5_ib_event,
d9aaed83
AK		 4251#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4252 .pfault = mlx5_ib_pfault,
4253#endif
64613d94 4254 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4255};
4256
4257static int __init mlx5_ib_init(void)
4258{
6aec21f6
HE		 4259 int err;
4260
81713d37 4261 mlx5_ib_odp_init();
9603b61d 4262
6aec21f6 4263 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4264
6aec21f6 4265 return err;
e126ba97
EC		 4266}
4267
4268static void __exit mlx5_ib_cleanup(void)
4269{
9603b61d 4270 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4271}
4272
4273module_init(mlx5_ib_init);
4274module_exit(mlx5_ib_cleanup);
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