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RDMA/mlx5: Remove unused port number parameter
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
da7525d2
EBE		 91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
d69a24e0 95static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
c44ef998
IL		 103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
32f69e4b
DJ		 109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
1b5daf11 119static enum rdma_link_layer
ebd61f68 120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 121{
ebd61f68 122 switch (port_type_cap) {
1b5daf11
MD		 123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
ebd61f68
AS		 132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
fd65f1b8
MS		 141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
8e6efa3a 149 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
fc24fc5e
AS		 155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
7fd8aefb 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
32f69e4b
DJ		 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
fc24fc5e 168
5ec8c83e
AH		 169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
7fd8aefb 172 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 181 NULL : ndev;
84a6a7a9 182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
bcf87f1d
MB		 183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
fd65f1b8 189 case NETDEV_CHANGE:
5ec8c83e 190 case NETDEV_UP:
88621dfe 191 case NETDEV_DOWN: {
7fd8aefb 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
7fd8aefb 200 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 201 && ibdev->ib_active) {
626bc02d 202 struct ib_event ibev = { };
fd65f1b8 203 enum ib_port_state port_state;
5ec8c83e 204
7fd8aefb
DJ		 205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
fd65f1b8 208
7fd8aefb
DJ		 209 if (roce->last_port_state == port_state)
210 goto done;
fd65f1b8 211
7fd8aefb 212 roce->last_port_state = port_state;
5ec8c83e 213 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
7fd8aefb 219 goto done;
fd65f1b8 220
7fd8aefb 221 ibev.element.port_num = port_num;
5ec8c83e
AH		 222 ib_dispatch_event(&ibev);
223 }
224 break;
88621dfe 225 }
fc24fc5e 226
5ec8c83e
AH		 227 default:
228 break;
229 }
7fd8aefb 230done:
32f69e4b 231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
32f69e4b
DJ		 240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
fc24fc5e 245
32f69e4b 246 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 247 if (ndev)
32f69e4b 248 goto out;
88621dfe 249
fc24fc5e
AS		 250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
7fd8aefb
DJ		 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 254 if (ndev)
255 dev_hold(ndev);
7fd8aefb 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 257
32f69e4b
DJ		 258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 260 return ndev;
261}
262
32f69e4b
DJ		 263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
210b1f78
MB		 273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
32f69e4b
DJ		 280 if (native_port_num)
281 *native_port_num = 1;
282
32f69e4b
DJ		 283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
f1b65df5
NO		 326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
095b0927
IT		 384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
3f89a643
AS		 386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 388 struct mlx5_core_dev *mdev;
88621dfe 389 struct net_device *ndev, *upper;
3f89a643 390 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 391 bool put_mdev = true;
c876a1b7 392 u16 qkey_viol_cntr;
f1b65df5 393 u32 eth_prot_oper;
b3cbd6f0 394 u8 mdev_port_num;
095b0927 395 int err;
3f89a643 396
b3cbd6f0
DJ		 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
f1b65df5
NO		 408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
50f22fd8 410 */
b3cbd6f0
DJ		 411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
095b0927 413 if (err)
b3cbd6f0 414 goto out;
f1b65df5 415
7672ed33
HL		 416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
f1b65df5
NO		 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
3f89a643
AS		 421
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
b3cbd6f0 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 434 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 435
b3cbd6f0
DJ		 436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
3f89a643
AS		 440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
b3cbd6f0 442 goto out;
3f89a643 443
88621dfe
AH		 444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
3f89a643
AS		 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
3f89a643
AS		 469}
470
095b0927
IT		 471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
3cca2606 474{
095b0927
IT		 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
3cca2606
AS		 490 }
491
095b0927 492 switch (gid_type) {
3cca2606 493 case IB_GID_TYPE_IB:
095b0927 494 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 502 break;
503
504 default:
095b0927 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 506 }
507
095b0927
IT		 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 510 vlan_id, port_num);
3cca2606
AS		 511}
512
f4df9a7c 513static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 514 __always_unused void **context)
515{
414448d2 516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 517 attr->index, &attr->gid, attr);
3cca2606
AS		 518}
519
414448d2
PP		 520static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
3cca2606 522{
414448d2
PP		 523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
3cca2606
AS		 525}
526
47ec3866
PP		 527__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
2811ba51 529{
47ec3866 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534}
535
1b5daf11
MD		 536static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537{
7fae6655
NO		 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
1b5daf11
MD		 541}
542
543enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547};
548
549static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550{
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
ebd61f68 554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559}
560
da7525d2 561static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 562 u8 atomic_size_qp,
da7525d2
EBE		 563 struct ib_device_attr *props)
564{
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 567 u8 atomic_req_8B_endianness_mode =
bd10838a 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581}
582
776a3906
MS		 583static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585{
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589}
590
591static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600{
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605}
1b5daf11
MD		 606static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608{
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
1b5daf11
MD		 626
627 default:
628 return -EINVAL;
629 }
3f89a643
AS		 630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
1b5daf11
MD		 636}
637
638static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640{
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657}
658
659static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661{
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675}
676
677static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679{
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
1b5daf11
MD		 694
695 default:
696 return -EINVAL;
697 }
3f89a643
AS		 698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
1b5daf11
MD		 703}
704
705struct mlx5_reg_node_desc {
bd99fdea 706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 707};
708
709static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710{
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721}
722
e126ba97 723static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
e126ba97
EC		 726{
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 728 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 729 int err = -ENOMEM;
288c01b7 730 int max_sq_desc;
e126ba97
EC		 731 int max_rq_sg;
732 int max_sq_sg;
e0238a6a 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 734 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
e126ba97 738
402ca536
BW		 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 746 return -EINVAL;
747
1b5daf11
MD		 748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
e126ba97 753
1b5daf11 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 755 if (err)
1b5daf11 756 return err;
e126ba97 757
1b5daf11
MD		 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
e126ba97 761
9603b61d
JM		 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
e126ba97
EC		 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 768 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 769
770 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 772 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 774 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 776 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 777 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 784 }
e126ba97 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 786 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
938fe83c 795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 797
85c7c014 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
88115fe7 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 808
402ca536
BW		 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
31f69a82
YH		 818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
2d93fc85
MB		 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 843 }
844
f0313965
ES		 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
03404e8a 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
03404e8a
MG		 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
1d54f890
YH		 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
cff5a0f3 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
e8161334 862 /* Legacy bit to support old userspace libraries */
cff5a0f3 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
cff5a0f3 866
24da0016
AL		 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
da6d6ba3
MG		 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
b1383aa6
NO		 875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
1b5daf11
MD		 878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 880
881 props->max_mr_size = ~0ull;
e0238a6a 882 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
986ef95e 893 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 904 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 907 get_atomic_caps_qp(dev, props);
81bea28f 908 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 914 props->max_ah = INT_MAX;
7c60bcbb
MB		 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 917
8cdd312c 918#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 919 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922#endif
923
051f2630
LR		 924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
eff901d3
EC		 927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
31f69a82 930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 931 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
eb761894 941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
eb761894 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
eb761894 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 949 }
950
87ab3f52
YC		 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
7e43a2a5 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 959 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 973 }
7e43a2a5
BW		 974 }
975
85c7c014
DJ		 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
d949167d
BW		 978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
9f885201
LR		 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
795b609c
BW		 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
050da902
BW		 999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
9f885201
LR		 1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
de57f2ad
GL		 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
7a0c8f42 1010
de57f2ad
GL		 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1017 }
9f885201 1018
96dc3fc5
NO		 1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
85c7c014
DJ		 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
b4f34597
NO		 1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
f95ef6cb
MG		 1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1077 }
1078
402ca536
BW		 1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1b5daf11 1086 return 0;
e126ba97
EC		 1087}
1088
1b5daf11
MD		 1089enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095};
1096
1097static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
e126ba97
EC		 1099{
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1101 int err = 0;
1102
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1107 (int)active_width);
1108 err = -EINVAL;
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1115 } else {
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1117 (int)active_width);
1118 err = -EINVAL;
e126ba97
EC		 1119 }
1120
1b5daf11
MD		 1121 return err;
1122}
e126ba97 1123
1b5daf11
MD		 1124static int mlx5_mtu_to_ib_mtu(int mtu)
1125{
1126 switch (mtu) {
1127 case 256: return 1;
1128 case 512: return 2;
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1132 default:
1133 pr_warn("invalid mtu\n");
1134 return -1;
e126ba97 1135 }
1b5daf11 1136}
e126ba97 1137
1b5daf11
MD		 1138enum ib_max_vl_num {
1139 __IB_MAX_VL_0 = 1,
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1144};
e126ba97 1145
1b5daf11
MD		 1146enum mlx5_vl_hw_cap {
1147 MLX5_VL_HW_0 = 1,
1148 MLX5_VL_HW_0_1 = 2,
1149 MLX5_VL_HW_0_2 = 3,
1150 MLX5_VL_HW_0_3 = 4,
1151 MLX5_VL_HW_0_4 = 5,
1152 MLX5_VL_HW_0_5 = 6,
1153 MLX5_VL_HW_0_6 = 7,
1154 MLX5_VL_HW_0_7 = 8,
1155 MLX5_VL_HW_0_14 = 15
1156};
e126ba97 1157
1b5daf11
MD		 1158static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1159 u8 *max_vl_num)
1160{
1161 switch (vl_hw_cap) {
1162 case MLX5_VL_HW_0:
1163 *max_vl_num = __IB_MAX_VL_0;
1164 break;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1167 break;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1170 break;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1173 break;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1176 break;
e126ba97 1177
1b5daf11
MD		 1178 default:
1179 return -EINVAL;
e126ba97 1180 }
e126ba97 1181
1b5daf11 1182 return 0;
e126ba97
EC		 1183}
1184
1b5daf11
MD		 1185static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
e126ba97 1187{
1b5daf11
MD		 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1191 u16 max_mtu;
1192 u16 oper_mtu;
1b5daf11
MD		 1193 int err;
1194 u8 ib_link_width_oper;
1195 u8 vl_hw_cap;
e126ba97 1196
1b5daf11
MD		 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1198 if (!rep) {
1199 err = -ENOMEM;
e126ba97 1200 goto out;
e126ba97 1201 }
e126ba97 1202
c4550c63 1203 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1204
1b5daf11 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1206 if (err)
1207 goto out;
1208
1b5daf11
MD		 1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
eff901d3 1223 props->grh_required = rep->grh_required;
e126ba97 1224
1b5daf11
MD		 1225 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1226 if (err)
e126ba97 1227 goto out;
e126ba97 1228
1b5daf11
MD		 1229 err = translate_active_width(ibdev, ib_link_width_oper,
1230 &props->active_width);
1231 if (err)
1232 goto out;
d5beb7f2 1233 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1234 if (err)
1235 goto out;
1236
facc9699 1237 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1238
1b5daf11 1239 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1240
facc9699 1241 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1242
1b5daf11 1243 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1244
1b5daf11
MD		 1245 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1246 if (err)
1247 goto out;
e126ba97 1248
1b5daf11
MD		 1249 err = translate_max_vl_num(ibdev, vl_hw_cap,
1250 &props->max_vl_num);
e126ba97 1251out:
1b5daf11 1252 kfree(rep);
e126ba97
EC		 1253 return err;
1254}
1255
1b5daf11
MD		 1256int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1257 struct ib_port_attr *props)
e126ba97 1258{
095b0927
IT		 1259 unsigned int count;
1260 int ret;
1261
1b5daf11
MD		 1262 switch (mlx5_get_vport_access_method(ibdev)) {
1263 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1264 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1265 break;
e126ba97 1266
1b5daf11 1267 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1268 ret = mlx5_query_hca_port(ibdev, port, props);
1269 break;
e126ba97 1270
3f89a643 1271 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1272 ret = mlx5_query_port_roce(ibdev, port, props);
1273 break;
3f89a643 1274
1b5daf11 1275 default:
095b0927
IT		 1276 ret = -EINVAL;
1277 }
1278
1279 if (!ret && props) {
b3cbd6f0
DJ		 1280 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1281 struct mlx5_core_dev *mdev;
1282 bool put_mdev = true;
1283
1284 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1285 if (!mdev) {
1286 /* If the port isn't affiliated yet query the master.
1287 * The master and slave will have the same values.
1288 */
1289 mdev = dev->mdev;
1290 port = 1;
1291 put_mdev = false;
1292 }
1293 count = mlx5_core_reserved_gids_count(mdev);
1294 if (put_mdev)
1295 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1296 props->gid_tbl_len -= count;
1b5daf11 1297 }
095b0927 1298 return ret;
1b5daf11 1299}
e126ba97 1300
8e6efa3a
MB		 1301static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1302 struct ib_port_attr *props)
1303{
1304 int ret;
1305
1306 /* Only link layer == ethernet is valid for representors */
1307 ret = mlx5_query_port_roce(ibdev, port, props);
1308 if (ret || !props)
1309 return ret;
1310
1311 /* We don't support GIDS */
1312 props->gid_tbl_len = 0;
1313
1314 return ret;
1315}
1316
1b5daf11
MD		 1317static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1318 union ib_gid *gid)
1319{
1320 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1321 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1322
1b5daf11
MD		 1323 switch (mlx5_get_vport_access_method(ibdev)) {
1324 case MLX5_VPORT_ACCESS_METHOD_MAD:
1325 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1326
1b5daf11
MD		 1327 case MLX5_VPORT_ACCESS_METHOD_HCA:
1328 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1329
1330 default:
1331 return -EINVAL;
1332 }
e126ba97 1333
e126ba97
EC		 1334}
1335
b3cbd6f0
DJ		 1336static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1337 u16 index, u16 *pkey)
1b5daf11
MD		 1338{
1339 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1340 struct mlx5_core_dev *mdev;
1341 bool put_mdev = true;
1342 u8 mdev_port_num;
1343 int err;
1b5daf11 1344
b3cbd6f0
DJ		 1345 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1346 if (!mdev) {
1347 /* The port isn't affiliated yet, get the PKey from the master
1348 * port. For RoCE the PKey tables will be the same.
1349 */
1350 put_mdev = false;
1351 mdev = dev->mdev;
1352 mdev_port_num = 1;
1353 }
1354
1355 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1356 index, pkey);
1357 if (put_mdev)
1358 mlx5_ib_put_native_port_mdev(dev, port);
1359
1360 return err;
1361}
1362
1363static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1364 u16 *pkey)
1365{
1b5daf11
MD		 1366 switch (mlx5_get_vport_access_method(ibdev)) {
1367 case MLX5_VPORT_ACCESS_METHOD_MAD:
1368 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1369
1370 case MLX5_VPORT_ACCESS_METHOD_HCA:
1371 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1372 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1373 default:
1374 return -EINVAL;
1375 }
1376}
e126ba97
EC		 1377
1378static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1379 struct ib_device_modify *props)
1380{
1381 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1382 struct mlx5_reg_node_desc in;
1383 struct mlx5_reg_node_desc out;
1384 int err;
1385
1386 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1387 return -EOPNOTSUPP;
1388
1389 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1390 return 0;
1391
1392 /*
1393 * If possible, pass node desc to FW, so it can generate
1394 * a 144 trap. If cmd fails, just ignore.
1395 */
bd99fdea 1396 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1397 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1398 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1399 if (err)
1400 return err;
1401
bd99fdea 1402 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1403
1404 return err;
1405}
1406
cdbe33d0
EC		 1407static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1408 u32 value)
1409{
1410 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1411 struct mlx5_core_dev *mdev;
1412 u8 mdev_port_num;
cdbe33d0
EC		 1413 int err;
1414
b3cbd6f0
DJ		 1415 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1416 if (!mdev)
1417 return -ENODEV;
1418
1419 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1420 if (err)
b3cbd6f0 1421 goto out;
cdbe33d0
EC		 1422
1423 if (~ctx.cap_mask1_perm & mask) {
1424 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1425 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1426 err = -EINVAL;
1427 goto out;
cdbe33d0
EC		 1428 }
1429
1430 ctx.cap_mask1 = value;
1431 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1432 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1433 0, &ctx);
1434
1435out:
1436 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1437
1438 return err;
1439}
1440
e126ba97
EC		 1441static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1442 struct ib_port_modify *props)
1443{
1444 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1445 struct ib_port_attr attr;
1446 u32 tmp;
1447 int err;
cdbe33d0
EC		 1448 u32 change_mask;
1449 u32 value;
1450 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1451 IB_LINK_LAYER_INFINIBAND);
1452
ec255879
MD		 1453 /* CM layer calls ib_modify_port() regardless of the link layer. For
1454 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1455 */
1456 if (!is_ib)
1457 return 0;
1458
cdbe33d0
EC		 1459 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1460 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1461 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1462 return set_port_caps_atomic(dev, port, change_mask, value);
1463 }
e126ba97
EC		 1464
1465 mutex_lock(&dev->cap_mask_mutex);
1466
c4550c63 1467 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1468 if (err)
1469 goto out;
1470
1471 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1472 ~props->clr_port_cap_mask;
1473
9603b61d 1474 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1475
1476out:
1477 mutex_unlock(&dev->cap_mask_mutex);
1478 return err;
1479}
1480
30aa60b3
EC		 1481static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1482{
1483 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1484 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1485}
1486
31a78a5a
YH		 1487static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1488{
1489 /* Large page with non 4k uar support might limit the dynamic size */
1490 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1491 return MLX5_MIN_DYN_BFREGS;
1492
1493 return MLX5_MAX_DYN_BFREGS;
1494}
1495
b037c29a
EC		 1496static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1497 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1498 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1499{
1500 int uars_per_sys_page;
1501 int bfregs_per_sys_page;
1502 int ref_bfregs = req->total_num_bfregs;
1503
1504 if (req->total_num_bfregs == 0)
1505 return -EINVAL;
1506
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1508 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1509
1510 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1511 return -ENOMEM;
1512
1513 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1514 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1515 /* This holds the required static allocation asked by the user */
b037c29a 1516 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1517 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1518 return -EINVAL;
1519
31a78a5a
YH		 1520 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1521 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1522 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1523 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1524
1525 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1526 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1527 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1528 req->total_num_bfregs, bfregi->total_num_bfregs,
1529 bfregi->num_sys_pages);
b037c29a
EC		 1530
1531 return 0;
1532}
1533
1534static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1535{
1536 struct mlx5_bfreg_info *bfregi;
1537 int err;
1538 int i;
1539
1540 bfregi = &context->bfregi;
31a78a5a 1541 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1542 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1543 if (err)
1544 goto error;
1545
1546 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1547 }
4ed131d0
YH		 1548
1549 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1550 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1551
b037c29a
EC		 1552 return 0;
1553
1554error:
1555 for (--i; i >= 0; i--)
1556 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1557 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1558
1559 return err;
1560}
1561
15177999
LR		 1562static void deallocate_uars(struct mlx5_ib_dev *dev,
1563 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1564{
1565 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1566 int i;
1567
1568 bfregi = &context->bfregi;
15177999 1569 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1570 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1571 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1572 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1573}
1574
c85023e1
HN		 1575static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1576{
1577 int err;
1578
cfdeb893
LR		 1579 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1580 return 0;
1581
c85023e1
HN		 1582 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1583 if (err)
1584 return err;
1585
1586 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1587 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1588 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1589 return err;
1590
1591 mutex_lock(&dev->lb_mutex);
1592 dev->user_td++;
1593
1594 if (dev->user_td == 2)
1595 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1596
1597 mutex_unlock(&dev->lb_mutex);
1598 return err;
1599}
1600
1601static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1602{
cfdeb893
LR		 1603 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1604 return;
1605
c85023e1
HN		 1606 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1607
1608 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1609 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1610 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1611 return;
1612
1613 mutex_lock(&dev->lb_mutex);
1614 dev->user_td--;
1615
1616 if (dev->user_td < 2)
1617 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1618
1619 mutex_unlock(&dev->lb_mutex);
1620}
1621
e126ba97
EC		 1622static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1623 struct ib_udata *udata)
1624{
1625 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1626 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1627 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1628 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1629 struct mlx5_ib_ucontext *context;
2f5ff264 1630 struct mlx5_bfreg_info *bfregi;
78c0f98c 1631 int ver;
e126ba97 1632 int err;
a168a41c
MD		 1633 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1634 max_cqe_version);
25bb36e7 1635 u32 dump_fill_mkey;
b037c29a 1636 bool lib_uar_4k;
e126ba97
EC		 1637
1638 if (!dev->ib_active)
1639 return ERR_PTR(-EAGAIN);
1640
e093111d 1641 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1642 ver = 0;
e093111d 1643 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1644 ver = 2;
1645 else
1646 return ERR_PTR(-EINVAL);
1647
e093111d 1648 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1649 if (err)
1650 return ERR_PTR(err);
1651
a8b92ca1
YH		 1652 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1653 return ERR_PTR(-EOPNOTSUPP);
78c0f98c 1654
f72300c5 1655 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1656 return ERR_PTR(-EOPNOTSUPP);
1657
2f5ff264
EC		 1658 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1659 MLX5_NON_FP_BFREGS_PER_UAR);
1660 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1661 return ERR_PTR(-EINVAL);
1662
938fe83c 1663 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1664 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1665 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1666 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1667 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1668 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1669 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1670 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1671 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1672 resp.cqe_version = min_t(__u8,
1673 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1674 req.max_cqe_version);
30aa60b3
EC		 1675 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1676 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1677 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1678 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1679 resp.response_length = min(offsetof(typeof(resp), response_length) +
1680 sizeof(resp.response_length), udata->outlen);
e126ba97 1681
c03faa56
MB		 1682 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1683 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1684 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1685 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1686 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1687 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1688 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1689 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1690 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1691 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1692 }
1693
e126ba97
EC		 1694 context = kzalloc(sizeof(*context), GFP_KERNEL);
1695 if (!context)
1696 return ERR_PTR(-ENOMEM);
1697
30aa60b3 1698 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1699 bfregi = &context->bfregi;
b037c29a
EC		 1700
1701 /* updates req->total_num_bfregs */
31a78a5a 1702 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1703 if (err)
e126ba97 1704 goto out_ctx;
e126ba97 1705
b037c29a
EC		 1706 mutex_init(&bfregi->lock);
1707 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1708 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1709 GFP_KERNEL);
b037c29a 1710 if (!bfregi->count) {
e126ba97 1711 err = -ENOMEM;
b037c29a 1712 goto out_ctx;
e126ba97
EC		 1713 }
1714
b037c29a
EC		 1715 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1716 sizeof(*bfregi->sys_pages),
1717 GFP_KERNEL);
1718 if (!bfregi->sys_pages) {
e126ba97 1719 err = -ENOMEM;
b037c29a 1720 goto out_count;
e126ba97
EC		 1721 }
1722
b037c29a
EC		 1723 err = allocate_uars(dev, context);
1724 if (err)
1725 goto out_sys_pages;
e126ba97 1726
b4cfe447
HE		 1727#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1728 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1729#endif
1730
cfdeb893
LR		 1731 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1732 if (err)
1733 goto out_uars;
146d2f1a 1734
a8b92ca1
YH		 1735 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1736 /* Block DEVX on Infiniband as of SELinux */
1737 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1738 err = -EPERM;
1739 goto out_td;
1740 }
1741
1742 err = mlx5_ib_devx_create(dev, context);
1743 if (err)
1744 goto out_td;
1745 }
1746
25bb36e7
YC		 1747 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1748 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1749 if (err)
8193abb6 1750 goto out_mdev;
25bb36e7
YC		 1751 }
1752
7c2344c3 1753 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1754 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1755 INIT_LIST_HEAD(&context->db_page_list);
1756 mutex_init(&context->db_page_mutex);
1757
2f5ff264 1758 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1759 resp.num_ports = dev->num_ports;
b368d7cb 1760
f72300c5
HA		 1761 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1762 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1763
402ca536 1764 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1765 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1766 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1767 resp.response_length += sizeof(resp.cmds_supp_uhw);
1768 }
1769
78984898
OG		 1770 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1771 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1772 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1773 resp.eth_min_inline++;
1774 }
1775 resp.response_length += sizeof(resp.eth_min_inline);
1776 }
1777
5c99eaec
FD		 1778 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1779 if (mdev->clock_info)
1780 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1781 resp.response_length += sizeof(resp.clock_info_versions);
1782 }
1783
bc5c6eed
NO		 1784 /*
1785 * We don't want to expose information from the PCI bar that is located
1786 * after 4096 bytes, so if the arch only supports larger pages, let's
1787 * pretend we don't support reading the HCA's core clock. This is also
1788 * forced by mmap function.
1789 */
de8d6e02
EC		 1790 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1791 if (PAGE_SIZE <= 4096) {
1792 resp.comp_mask |=
1793 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1794 resp.hca_core_clock_offset =
1795 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1796 }
5c99eaec 1797 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1798 }
1799
30aa60b3
EC		 1800 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1801 resp.response_length += sizeof(resp.log_uar_size);
1802
1803 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1804 resp.response_length += sizeof(resp.num_uars_per_page);
1805
31a78a5a
YH		 1806 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1807 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1808 resp.response_length += sizeof(resp.num_dyn_bfregs);
1809 }
1810
25bb36e7
YC		 1811 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1812 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1813 resp.dump_fill_mkey = dump_fill_mkey;
1814 resp.comp_mask |=
1815 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1816 }
1817 resp.response_length += sizeof(resp.dump_fill_mkey);
1818 }
1819
b368d7cb 1820 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1821 if (err)
a8b92ca1 1822 goto out_mdev;
e126ba97 1823
2f5ff264
EC		 1824 bfregi->ver = ver;
1825 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1826 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1827 context->lib_caps = req.lib_caps;
1828 print_lib_caps(dev, context->lib_caps);
f72300c5 1829
e126ba97
EC		 1830 return &context->ibucontext;
1831
a8b92ca1
YH		 1832out_mdev:
1833 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1834 mlx5_ib_devx_destroy(dev, context);
146d2f1a 1835out_td:
cfdeb893 1836 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1837
e126ba97 1838out_uars:
b037c29a 1839 deallocate_uars(dev, context);
e126ba97 1840
b037c29a
EC		 1841out_sys_pages:
1842 kfree(bfregi->sys_pages);
e126ba97 1843
b037c29a
EC		 1844out_count:
1845 kfree(bfregi->count);
e126ba97
EC		 1846
1847out_ctx:
1848 kfree(context);
b037c29a 1849
e126ba97
EC		 1850 return ERR_PTR(err);
1851}
1852
1853static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1854{
1855 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1856 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1857 struct mlx5_bfreg_info *bfregi;
e126ba97 1858
a8b92ca1
YH		 1859 if (context->devx_uid)
1860 mlx5_ib_devx_destroy(dev, context);
1861
b037c29a 1862 bfregi = &context->bfregi;
cfdeb893 1863 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1864
b037c29a
EC		 1865 deallocate_uars(dev, context);
1866 kfree(bfregi->sys_pages);
2f5ff264 1867 kfree(bfregi->count);
e126ba97
EC		 1868 kfree(context);
1869
1870 return 0;
1871}
1872
b037c29a 1873static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1874 int uar_idx)
e126ba97 1875{
b037c29a
EC		 1876 int fw_uars_per_page;
1877
1878 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1879
4ed131d0 1880 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1881}
1882
1883static int get_command(unsigned long offset)
1884{
1885 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1886}
1887
1888static int get_arg(unsigned long offset)
1889{
1890 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1891}
1892
1893static int get_index(unsigned long offset)
1894{
1895 return get_arg(offset);
1896}
1897
4ed131d0
YH		 1898/* Index resides in an extra byte to enable larger values than 255 */
1899static int get_extended_index(unsigned long offset)
1900{
1901 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1902}
1903
7c2344c3
MG		 1904static void mlx5_ib_vma_open(struct vm_area_struct *area)
1905{
1906 /* vma_open is called when a new VMA is created on top of our VMA. This
1907 * is done through either mremap flow or split_vma (usually due to
1908 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1909 * as this VMA is strongly hardware related. Therefore we set the
1910 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1911 * calling us again and trying to do incorrect actions. We assume that
1912 * the original VMA size is exactly a single page, and therefore all
1913 * "splitting" operation will not happen to it.
1914 */
1915 area->vm_ops = NULL;
1916}
1917
1918static void mlx5_ib_vma_close(struct vm_area_struct *area)
1919{
1920 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1921
1922 /* It's guaranteed that all VMAs opened on a FD are closed before the
1923 * file itself is closed, therefore no sync is needed with the regular
1924 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1925 * However need a sync with accessing the vma as part of
1926 * mlx5_ib_disassociate_ucontext.
1927 * The close operation is usually called under mm->mmap_sem except when
1928 * process is exiting.
1929 * The exiting case is handled explicitly as part of
1930 * mlx5_ib_disassociate_ucontext.
1931 */
1932 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1933
1934 /* setting the vma context pointer to null in the mlx5_ib driver's
1935 * private data, to protect a race condition in
1936 * mlx5_ib_disassociate_ucontext().
1937 */
1938 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1939 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1940 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1941 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1942 kfree(mlx5_ib_vma_priv_data);
1943}
1944
1945static const struct vm_operations_struct mlx5_ib_vm_ops = {
1946 .open = mlx5_ib_vma_open,
1947 .close = mlx5_ib_vma_close
1948};
1949
1950static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1951 struct mlx5_ib_ucontext *ctx)
1952{
1953 struct mlx5_ib_vma_private_data *vma_prv;
1954 struct list_head *vma_head = &ctx->vma_private_list;
1955
1956 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1957 if (!vma_prv)
1958 return -ENOMEM;
1959
1960 vma_prv->vma = vma;
ad9a3668 1961 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1962 vma->vm_private_data = vma_prv;
1963 vma->vm_ops = &mlx5_ib_vm_ops;
1964
ad9a3668 1965 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1966 list_add(&vma_prv->list, vma_head);
ad9a3668 1967 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1968
1969 return 0;
1970}
1971
1972static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1973{
7c2344c3
MG		 1974 struct vm_area_struct *vma;
1975 struct mlx5_ib_vma_private_data *vma_private, *n;
1976 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
7c2344c3 1977
ad9a3668 1978 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1979 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1980 list) {
1981 vma = vma_private->vma;
2cb40791 1982 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
7c2344c3
MG		 1983 /* context going to be destroyed, should
1984 * not access ops any more.
1985 */
13776612 1986 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1987 vma->vm_ops = NULL;
1988 list_del(&vma_private->list);
1989 kfree(vma_private);
1990 }
ad9a3668 1991 mutex_unlock(&context->vma_private_list_mutex);
7c2344c3
MG		 1992}
1993
37aa5c36
GL		 1994static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1995{
1996 switch (cmd) {
1997 case MLX5_IB_MMAP_WC_PAGE:
1998 return "WC";
1999 case MLX5_IB_MMAP_REGULAR_PAGE:
2000 return "best effort WC";
2001 case MLX5_IB_MMAP_NC_PAGE:
2002 return "NC";
24da0016
AL		 2003 case MLX5_IB_MMAP_DEVICE_MEM:
2004 return "Device Memory";
37aa5c36
GL		 2005 default:
2006 return NULL;
2007 }
2008}
2009
5c99eaec
FD		 2010static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2011 struct vm_area_struct *vma,
2012 struct mlx5_ib_ucontext *context)
2013{
2014 phys_addr_t pfn;
2015 int err;
2016
2017 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2018 return -EINVAL;
2019
2020 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2021 return -EOPNOTSUPP;
2022
2023 if (vma->vm_flags & VM_WRITE)
2024 return -EPERM;
2025
2026 if (!dev->mdev->clock_info_page)
2027 return -EOPNOTSUPP;
2028
2029 pfn = page_to_pfn(dev->mdev->clock_info_page);
2030 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2031 vma->vm_page_prot);
2032 if (err)
2033 return err;
2034
5c99eaec
FD		 2035 return mlx5_ib_set_vma_data(vma, context);
2036}
2037
37aa5c36 2038static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2039 struct vm_area_struct *vma,
2040 struct mlx5_ib_ucontext *context)
37aa5c36 2041{
2f5ff264 2042 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2043 int err;
2044 unsigned long idx;
2045 phys_addr_t pfn, pa;
2046 pgprot_t prot;
4ed131d0
YH		 2047 u32 bfreg_dyn_idx = 0;
2048 u32 uar_index;
2049 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2050 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2051 bfregi->num_static_sys_pages;
b037c29a
EC		 2052
2053 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2054 return -EINVAL;
2055
4ed131d0
YH		 2056 if (dyn_uar)
2057 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2058 else
2059 idx = get_index(vma->vm_pgoff);
2060
2061 if (idx >= max_valid_idx) {
2062 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2063 idx, max_valid_idx);
b037c29a
EC		 2064 return -EINVAL;
2065 }
37aa5c36
GL		 2066
2067 switch (cmd) {
2068 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2069 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2070/* Some architectures don't support WC memory */
2071#if defined(CONFIG_X86)
2072 if (!pat_enabled())
2073 return -EPERM;
2074#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2075 return -EPERM;
2076#endif
2077 /* fall through */
2078 case MLX5_IB_MMAP_REGULAR_PAGE:
2079 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2080 prot = pgprot_writecombine(vma->vm_page_prot);
2081 break;
2082 case MLX5_IB_MMAP_NC_PAGE:
2083 prot = pgprot_noncached(vma->vm_page_prot);
2084 break;
2085 default:
2086 return -EINVAL;
2087 }
2088
4ed131d0
YH		 2089 if (dyn_uar) {
2090 int uars_per_page;
2091
2092 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2093 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2094 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2095 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2096 bfreg_dyn_idx, bfregi->total_num_bfregs);
2097 return -EINVAL;
2098 }
2099
2100 mutex_lock(&bfregi->lock);
2101 /* Fail if uar already allocated, first bfreg index of each
2102 * page holds its count.
2103 */
2104 if (bfregi->count[bfreg_dyn_idx]) {
2105 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2106 mutex_unlock(&bfregi->lock);
2107 return -EINVAL;
2108 }
2109
2110 bfregi->count[bfreg_dyn_idx]++;
2111 mutex_unlock(&bfregi->lock);
2112
2113 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2114 if (err) {
2115 mlx5_ib_warn(dev, "UAR alloc failed\n");
2116 goto free_bfreg;
2117 }
2118 } else {
2119 uar_index = bfregi->sys_pages[idx];
2120 }
2121
2122 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2123 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2124
2125 vma->vm_page_prot = prot;
2126 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2127 PAGE_SIZE, vma->vm_page_prot);
2128 if (err) {
8f062287
LR		 2129 mlx5_ib_err(dev,
2130 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2131 err, mmap_cmd2str(cmd));
4ed131d0
YH		 2132 err = -EAGAIN;
2133 goto err;
37aa5c36
GL		 2134 }
2135
2136 pa = pfn << PAGE_SHIFT;
37aa5c36 2137
4ed131d0
YH		 2138 err = mlx5_ib_set_vma_data(vma, context);
2139 if (err)
2140 goto err;
2141
2142 if (dyn_uar)
2143 bfregi->sys_pages[idx] = uar_index;
2144 return 0;
2145
2146err:
2147 if (!dyn_uar)
2148 return err;
2149
2150 mlx5_cmd_free_uar(dev->mdev, idx);
2151
2152free_bfreg:
2153 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2154
2155 return err;
37aa5c36
GL		 2156}
2157
24da0016
AL		 2158static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2159{
2160 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2161 struct mlx5_ib_dev *dev = to_mdev(context->device);
2162 u16 page_idx = get_extended_index(vma->vm_pgoff);
2163 size_t map_size = vma->vm_end - vma->vm_start;
2164 u32 npages = map_size >> PAGE_SHIFT;
2165 phys_addr_t pfn;
2166 pgprot_t prot;
2167
2168 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2169 page_idx + npages)
2170 return -EINVAL;
2171
2172 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2173 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2174 PAGE_SHIFT) +
2175 page_idx;
2176 prot = pgprot_writecombine(vma->vm_page_prot);
2177 vma->vm_page_prot = prot;
2178
2179 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2180 vma->vm_page_prot))
2181 return -EAGAIN;
2182
2183 return mlx5_ib_set_vma_data(vma, mctx);
2184}
2185
e126ba97
EC		 2186static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2187{
2188 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2189 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2190 unsigned long command;
e126ba97
EC		 2191 phys_addr_t pfn;
2192
2193 command = get_command(vma->vm_pgoff);
2194 switch (command) {
37aa5c36
GL		 2195 case MLX5_IB_MMAP_WC_PAGE:
2196 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2197 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2198 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2199 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2200
2201 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2202 return -ENOSYS;
2203
d69e3bcf 2204 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2205 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2206 return -EINVAL;
2207
6cbac1e4 2208 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2209 return -EPERM;
2210
2211 /* Don't expose to user-space information it shouldn't have */
2212 if (PAGE_SIZE > 4096)
2213 return -EOPNOTSUPP;
2214
2215 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2216 pfn = (dev->mdev->iseg_base +
2217 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2218 PAGE_SHIFT;
2219 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2220 PAGE_SIZE, vma->vm_page_prot))
2221 return -EAGAIN;
d69e3bcf 2222 break;
5c99eaec
FD		 2223 case MLX5_IB_MMAP_CLOCK_INFO:
2224 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2225
24da0016
AL		 2226 case MLX5_IB_MMAP_DEVICE_MEM:
2227 return dm_mmap(ibcontext, vma);
2228
e126ba97
EC		 2229 default:
2230 return -EINVAL;
2231 }
2232
2233 return 0;
2234}
2235
24da0016
AL		 2236struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2237 struct ib_ucontext *context,
2238 struct ib_dm_alloc_attr *attr,
2239 struct uverbs_attr_bundle *attrs)
2240{
2241 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2242 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2243 phys_addr_t memic_addr;
2244 struct mlx5_ib_dm *dm;
2245 u64 start_offset;
2246 u32 page_idx;
2247 int err;
2248
2249 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2250 if (!dm)
2251 return ERR_PTR(-ENOMEM);
2252
2253 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2254 attr->length, act_size, attr->alignment);
2255
2256 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2257 act_size, attr->alignment);
2258 if (err)
2259 goto err_free;
2260
2261 start_offset = memic_addr & ~PAGE_MASK;
2262 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2263 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2264 PAGE_SHIFT;
2265
2266 err = uverbs_copy_to(attrs,
2267 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2268 &start_offset, sizeof(start_offset));
2269 if (err)
2270 goto err_dealloc;
2271
2272 err = uverbs_copy_to(attrs,
2273 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2274 &page_idx, sizeof(page_idx));
2275 if (err)
2276 goto err_dealloc;
2277
2278 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2279 DIV_ROUND_UP(act_size, PAGE_SIZE));
2280
2281 dm->dev_addr = memic_addr;
2282
2283 return &dm->ibdm;
2284
2285err_dealloc:
2286 mlx5_cmd_dealloc_memic(memic, memic_addr,
2287 act_size);
2288err_free:
2289 kfree(dm);
2290 return ERR_PTR(err);
2291}
2292
2293int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2294{
2295 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2296 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2297 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2298 u32 page_idx;
2299 int ret;
2300
2301 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2302 if (ret)
2303 return ret;
2304
2305 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2306 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2307 PAGE_SHIFT;
2308 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2309 page_idx,
2310 DIV_ROUND_UP(act_size, PAGE_SIZE));
2311
2312 kfree(dm);
2313
2314 return 0;
2315}
2316
e126ba97
EC		 2317static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2318 struct ib_ucontext *context,
2319 struct ib_udata *udata)
2320{
2321 struct mlx5_ib_alloc_pd_resp resp;
2322 struct mlx5_ib_pd *pd;
2323 int err;
2324
2325 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2326 if (!pd)
2327 return ERR_PTR(-ENOMEM);
2328
9603b61d 2329 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2330 if (err) {
2331 kfree(pd);
2332 return ERR_PTR(err);
2333 }
2334
2335 if (context) {
2336 resp.pdn = pd->pdn;
2337 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2338 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2339 kfree(pd);
2340 return ERR_PTR(-EFAULT);
2341 }
e126ba97
EC		 2342 }
2343
2344 return &pd->ibpd;
2345}
2346
2347static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2348{
2349 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2350 struct mlx5_ib_pd *mpd = to_mpd(pd);
2351
9603b61d 2352 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2353 kfree(mpd);
2354
2355 return 0;
2356}
2357
466fa6d2
MG		 2358enum {
2359 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2360 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2361 MATCH_CRITERIA_ENABLE_INNER_BIT,
2362 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2363};
2364
2365#define HEADER_IS_ZERO(match_criteria, headers) \
2366 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2367 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2368
466fa6d2 2369static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2370{
466fa6d2 2371 u8 match_criteria_enable;
038d2ef8 2372
466fa6d2
MG		 2373 match_criteria_enable =
2374 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2375 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2376 match_criteria_enable |=
2377 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2378 MATCH_CRITERIA_ENABLE_MISC_BIT;
2379 match_criteria_enable |=
2380 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2381 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2382 match_criteria_enable |=
2383 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2384 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2385
2386 return match_criteria_enable;
038d2ef8
MG		 2387}
2388
ca0d4753
MG		 2389static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2390{
2391 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2392 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2393}
2394
37da2a03 2395static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2396 bool inner)
2397{
2398 if (inner) {
2399 MLX5_SET(fte_match_set_misc,
2400 misc_c, inner_ipv6_flow_label, mask);
2401 MLX5_SET(fte_match_set_misc,
2402 misc_v, inner_ipv6_flow_label, val);
2403 } else {
2404 MLX5_SET(fte_match_set_misc,
2405 misc_c, outer_ipv6_flow_label, mask);
2406 MLX5_SET(fte_match_set_misc,
2407 misc_v, outer_ipv6_flow_label, val);
2408 }
2409}
2410
ca0d4753
MG		 2411static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2412{
2413 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2414 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2415 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2416 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2417}
2418
71c6e863
AL		 2419static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2420{
2421 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2422 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2423 return -EOPNOTSUPP;
2424
2425 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2426 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2427 return -EOPNOTSUPP;
2428
2429 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2430 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2431 return -EOPNOTSUPP;
2432
2433 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2434 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2435 return -EOPNOTSUPP;
2436
2437 return 0;
2438}
2439
c47ac6ae
MG		 2440#define LAST_ETH_FIELD vlan_tag
2441#define LAST_IB_FIELD sl
ca0d4753 2442#define LAST_IPV4_FIELD tos
466fa6d2 2443#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2444#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2445#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2446#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2447#define LAST_DROP_FIELD size
3b3233fb 2448#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2449
2450/* Field is the last supported field */
2451#define FIELDS_NOT_SUPPORTED(filter, field)\
2452 memchr_inv((void *)&filter.field +\
2453 sizeof(filter.field), 0,\
2454 sizeof(filter) -\
2455 offsetof(typeof(filter), field) -\
2456 sizeof(filter.field))
2457
802c2125
AY		 2458static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2459 const struct ib_flow_attr *flow_attr,
2460 struct mlx5_flow_act *action)
2461{
2462 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2463
2464 switch (maction->ib_action.type) {
2465 case IB_FLOW_ACTION_ESP:
2466 /* Currently only AES_GCM keymat is supported by the driver */
2467 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2468 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2469 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2470 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2471 return 0;
2472 default:
2473 return -EOPNOTSUPP;
2474 }
2475}
2476
19cc7524
AL		 2477static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2478 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2479 const struct ib_flow_attr *flow_attr,
71c6e863 2480 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2481{
466fa6d2
MG		 2482 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2483 misc_parameters);
2484 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2485 misc_parameters);
71c6e863
AL		 2486 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2487 misc_parameters_2);
2488 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2489 misc_parameters_2);
2d1e697e
MR		 2490 void *headers_c;
2491 void *headers_v;
19cc7524 2492 int match_ipv;
802c2125 2493 int ret;
2d1e697e
MR		 2494
2495 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2496 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2497 inner_headers);
2498 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2499 inner_headers);
19cc7524
AL		 2500 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2501 ft_field_support.inner_ip_version);
2d1e697e
MR		 2502 } else {
2503 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2504 outer_headers);
2505 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2506 outer_headers);
19cc7524
AL		 2507 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2508 ft_field_support.outer_ip_version);
2d1e697e 2509 }
466fa6d2 2510
2d1e697e 2511 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2512 case IB_FLOW_SPEC_ETH:
c47ac6ae 2513 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2514 return -EOPNOTSUPP;
038d2ef8 2515
2d1e697e 2516 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2517 dmac_47_16),
2518 ib_spec->eth.mask.dst_mac);
2d1e697e 2519 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2520 dmac_47_16),
2521 ib_spec->eth.val.dst_mac);
2522
2d1e697e 2523 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2524 smac_47_16),
2525 ib_spec->eth.mask.src_mac);
2d1e697e 2526 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2527 smac_47_16),
2528 ib_spec->eth.val.src_mac);
2529
038d2ef8 2530 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2531 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2532 cvlan_tag, 1);
2d1e697e 2533 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2534 cvlan_tag, 1);
038d2ef8 2535
2d1e697e 2536 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2537 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2538 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2539 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2540
2d1e697e 2541 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2542 first_cfi,
2543 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2544 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2545 first_cfi,
2546 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2547
2d1e697e 2548 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2549 first_prio,
2550 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2551 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2552 first_prio,
2553 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2554 }
2d1e697e 2555 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2556 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2557 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2558 ethertype, ntohs(ib_spec->eth.val.ether_type));
2559 break;
2560 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2561 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2562 return -EOPNOTSUPP;
038d2ef8 2563
19cc7524
AL		 2564 if (match_ipv) {
2565 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2566 ip_version, 0xf);
2567 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2568 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2569 } else {
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2571 ethertype, 0xffff);
2572 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2573 ethertype, ETH_P_IP);
2574 }
038d2ef8 2575
2d1e697e 2576 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2577 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2578 &ib_spec->ipv4.mask.src_ip,
2579 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2580 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2581 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2582 &ib_spec->ipv4.val.src_ip,
2583 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2584 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2585 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2586 &ib_spec->ipv4.mask.dst_ip,
2587 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2588 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2589 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2590 &ib_spec->ipv4.val.dst_ip,
2591 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2592
2d1e697e 2593 set_tos(headers_c, headers_v,
ca0d4753
MG		 2594 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2595
2d1e697e 2596 set_proto(headers_c, headers_v,
ca0d4753 2597 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2598 break;
026bae0c 2599 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2600 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2601 return -EOPNOTSUPP;
026bae0c 2602
19cc7524
AL		 2603 if (match_ipv) {
2604 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2605 ip_version, 0xf);
2606 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2607 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2608 } else {
2609 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2610 ethertype, 0xffff);
2611 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2612 ethertype, ETH_P_IPV6);
2613 }
026bae0c 2614
2d1e697e 2615 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2616 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2617 &ib_spec->ipv6.mask.src_ip,
2618 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2619 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2620 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2621 &ib_spec->ipv6.val.src_ip,
2622 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2623 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2624 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2625 &ib_spec->ipv6.mask.dst_ip,
2626 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2627 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2628 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2629 &ib_spec->ipv6.val.dst_ip,
2630 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2631
2d1e697e 2632 set_tos(headers_c, headers_v,
466fa6d2
MG		 2633 ib_spec->ipv6.mask.traffic_class,
2634 ib_spec->ipv6.val.traffic_class);
2635
2d1e697e 2636 set_proto(headers_c, headers_v,
466fa6d2
MG		 2637 ib_spec->ipv6.mask.next_hdr,
2638 ib_spec->ipv6.val.next_hdr);
2639
2d1e697e
MR		 2640 set_flow_label(misc_params_c, misc_params_v,
2641 ntohl(ib_spec->ipv6.mask.flow_label),
2642 ntohl(ib_spec->ipv6.val.flow_label),
2643 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2644 break;
2645 case IB_FLOW_SPEC_ESP:
2646 if (ib_spec->esp.mask.seq)
2647 return -EOPNOTSUPP;
2d1e697e 2648
802c2125
AY		 2649 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2650 ntohl(ib_spec->esp.mask.spi));
2651 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2652 ntohl(ib_spec->esp.val.spi));
026bae0c 2653 break;
038d2ef8 2654 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2655 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2656 LAST_TCP_UDP_FIELD))
1ffd3a26 2657 return -EOPNOTSUPP;
038d2ef8 2658
2d1e697e 2659 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2660 0xff);
2d1e697e 2661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2662 IPPROTO_TCP);
2663
2d1e697e 2664 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2665 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2666 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2667 ntohs(ib_spec->tcp_udp.val.src_port));
2668
2d1e697e 2669 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2670 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2672 ntohs(ib_spec->tcp_udp.val.dst_port));
2673 break;
2674 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2675 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2676 LAST_TCP_UDP_FIELD))
1ffd3a26 2677 return -EOPNOTSUPP;
038d2ef8 2678
2d1e697e 2679 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2680 0xff);
2d1e697e 2681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2682 IPPROTO_UDP);
2683
2d1e697e 2684 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2685 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2686 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2687 ntohs(ib_spec->tcp_udp.val.src_port));
2688
2d1e697e 2689 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2690 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2691 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2692 ntohs(ib_spec->tcp_udp.val.dst_port));
2693 break;
da2f22ae
AL		 2694 case IB_FLOW_SPEC_GRE:
2695 if (ib_spec->gre.mask.c_ks_res0_ver)
2696 return -EOPNOTSUPP;
2697
2698 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2699 0xff);
2700 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2701 IPPROTO_GRE);
2702
2703 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2704 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2705 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2706 ntohs(ib_spec->gre.val.protocol));
2707
2708 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2709 gre_key_h),
2710 &ib_spec->gre.mask.key,
2711 sizeof(ib_spec->gre.mask.key));
2712 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2713 gre_key_h),
2714 &ib_spec->gre.val.key,
2715 sizeof(ib_spec->gre.val.key));
2716 break;
71c6e863
AL		 2717 case IB_FLOW_SPEC_MPLS:
2718 switch (prev_type) {
2719 case IB_FLOW_SPEC_UDP:
2720 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2721 ft_field_support.outer_first_mpls_over_udp),
2722 &ib_spec->mpls.mask.tag))
2723 return -EOPNOTSUPP;
2724
2725 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2726 outer_first_mpls_over_udp),
2727 &ib_spec->mpls.val.tag,
2728 sizeof(ib_spec->mpls.val.tag));
2729 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2730 outer_first_mpls_over_udp),
2731 &ib_spec->mpls.mask.tag,
2732 sizeof(ib_spec->mpls.mask.tag));
2733 break;
2734 case IB_FLOW_SPEC_GRE:
2735 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2736 ft_field_support.outer_first_mpls_over_gre),
2737 &ib_spec->mpls.mask.tag))
2738 return -EOPNOTSUPP;
2739
2740 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2741 outer_first_mpls_over_gre),
2742 &ib_spec->mpls.val.tag,
2743 sizeof(ib_spec->mpls.val.tag));
2744 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2745 outer_first_mpls_over_gre),
2746 &ib_spec->mpls.mask.tag,
2747 sizeof(ib_spec->mpls.mask.tag));
2748 break;
2749 default:
2750 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2751 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2752 ft_field_support.inner_first_mpls),
2753 &ib_spec->mpls.mask.tag))
2754 return -EOPNOTSUPP;
2755
2756 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2757 inner_first_mpls),
2758 &ib_spec->mpls.val.tag,
2759 sizeof(ib_spec->mpls.val.tag));
2760 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2761 inner_first_mpls),
2762 &ib_spec->mpls.mask.tag,
2763 sizeof(ib_spec->mpls.mask.tag));
2764 } else {
2765 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2766 ft_field_support.outer_first_mpls),
2767 &ib_spec->mpls.mask.tag))
2768 return -EOPNOTSUPP;
2769
2770 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2771 outer_first_mpls),
2772 &ib_spec->mpls.val.tag,
2773 sizeof(ib_spec->mpls.val.tag));
2774 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2775 outer_first_mpls),
2776 &ib_spec->mpls.mask.tag,
2777 sizeof(ib_spec->mpls.mask.tag));
2778 }
2779 }
2780 break;
ffb30d8f
MR		 2781 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2782 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2783 LAST_TUNNEL_FIELD))
1ffd3a26 2784 return -EOPNOTSUPP;
ffb30d8f
MR		 2785
2786 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2787 ntohl(ib_spec->tunnel.mask.tunnel_id));
2788 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2789 ntohl(ib_spec->tunnel.val.tunnel_id));
2790 break;
2ac693f9
MR		 2791 case IB_FLOW_SPEC_ACTION_TAG:
2792 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2793 LAST_FLOW_TAG_FIELD))
2794 return -EOPNOTSUPP;
2795 if (ib_spec->flow_tag.tag_id >= BIT(24))
2796 return -EINVAL;
2797
075572d4 2798 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2799 action->has_flow_tag = true;
2ac693f9 2800 break;
a22ed86c
SS		 2801 case IB_FLOW_SPEC_ACTION_DROP:
2802 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2803 LAST_DROP_FIELD))
2804 return -EOPNOTSUPP;
075572d4 2805 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2806 break;
802c2125
AY		 2807 case IB_FLOW_SPEC_ACTION_HANDLE:
2808 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2809 if (ret)
2810 return ret;
2811 break;
3b3233fb
RS		 2812 case IB_FLOW_SPEC_ACTION_COUNT:
2813 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2814 LAST_COUNTERS_FIELD))
2815 return -EOPNOTSUPP;
2816
2817 /* for now support only one counters spec per flow */
2818 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2819 return -EINVAL;
2820
2821 action->counters = ib_spec->flow_count.counters;
2822 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2823 break;
038d2ef8
MG		 2824 default:
2825 return -EINVAL;
2826 }
2827
2828 return 0;
2829}
2830
2831/* If a flow could catch both multicast and unicast packets,
2832 * it won't fall into the multicast flow steering table and this rule
2833 * could steal other multicast packets.
2834 */
a550ddfc 2835static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2836{
81e30880 2837 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2838
2839 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2840 ib_attr->num_of_specs < 1)
2841 return false;
2842
81e30880
YH		 2843 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2844 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2845 struct ib_flow_spec_ipv4 *ipv4_spec;
2846
2847 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2848 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2849 return true;
2850
038d2ef8 2851 return false;
81e30880
YH		 2852 }
2853
2854 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2855 struct ib_flow_spec_eth *eth_spec;
2856
2857 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2858 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2859 is_multicast_ether_addr(eth_spec->val.dst_mac);
2860 }
038d2ef8 2861
81e30880 2862 return false;
038d2ef8
MG		 2863}
2864
802c2125
AY		 2865enum valid_spec {
2866 VALID_SPEC_INVALID,
2867 VALID_SPEC_VALID,
2868 VALID_SPEC_NA,
2869};
2870
2871static enum valid_spec
2872is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2873 const struct mlx5_flow_spec *spec,
2874 const struct mlx5_flow_act *flow_act,
2875 bool egress)
2876{
2877 const u32 *match_c = spec->match_criteria;
2878 bool is_crypto =
2879 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2880 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2881 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2882 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2883
2884 /*
2885 * Currently only crypto is supported in egress, when regular egress
2886 * rules would be supported, always return VALID_SPEC_NA.
2887 */
2888 if (!is_crypto)
2889 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2890
2891 return is_crypto && is_ipsec &&
2892 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2893 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2894}
2895
2896static bool is_valid_spec(struct mlx5_core_dev *mdev,
2897 const struct mlx5_flow_spec *spec,
2898 const struct mlx5_flow_act *flow_act,
2899 bool egress)
2900{
2901 /* We curretly only support ipsec egress flow */
2902 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2903}
2904
19cc7524
AL		 2905static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2906 const struct ib_flow_attr *flow_attr,
0f750966 2907 bool check_inner)
038d2ef8
MG		 2908{
2909 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2910 int match_ipv = check_inner ?
2911 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2912 ft_field_support.inner_ip_version) :
2913 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2914 ft_field_support.outer_ip_version);
0f750966
AL		 2915 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2916 bool ipv4_spec_valid, ipv6_spec_valid;
2917 unsigned int ip_spec_type = 0;
2918 bool has_ethertype = false;
038d2ef8 2919 unsigned int spec_index;
0f750966
AL		 2920 bool mask_valid = true;
2921 u16 eth_type = 0;
2922 bool type_valid;
038d2ef8
MG		 2923
2924 /* Validate that ethertype is correct */
2925 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2926 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2927 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2928 mask_valid = (ib_spec->eth.mask.ether_type ==
2929 htons(0xffff));
2930 has_ethertype = true;
2931 eth_type = ntohs(ib_spec->eth.val.ether_type);
2932 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2933 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2934 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2935 }
2936 ib_spec = (void *)ib_spec + ib_spec->size;
2937 }
0f750966
AL		 2938
2939 type_valid = (!has_ethertype) || (!ip_spec_type);
2940 if (!type_valid && mask_valid) {
2941 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2942 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2943 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2944 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2945
2946 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2947 (((eth_type == ETH_P_MPLS_UC) ||
2948 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2949 }
2950
2951 return type_valid;
2952}
2953
19cc7524
AL		 2954static bool is_valid_attr(struct mlx5_core_dev *mdev,
2955 const struct ib_flow_attr *flow_attr)
0f750966 2956{
19cc7524
AL		 2957 return is_valid_ethertype(mdev, flow_attr, false) &&
2958 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2959}
2960
2961static void put_flow_table(struct mlx5_ib_dev *dev,
2962 struct mlx5_ib_flow_prio *prio, bool ft_added)
2963{
2964 prio->refcount -= !!ft_added;
2965 if (!prio->refcount) {
2966 mlx5_destroy_flow_table(prio->flow_table);
2967 prio->flow_table = NULL;
2968 }
2969}
2970
3b3233fb
RS		 2971static void counters_clear_description(struct ib_counters *counters)
2972{
2973 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2974
2975 mutex_lock(&mcounters->mcntrs_mutex);
2976 kfree(mcounters->counters_data);
2977 mcounters->counters_data = NULL;
2978 mcounters->cntrs_max_index = 0;
2979 mutex_unlock(&mcounters->mcntrs_mutex);
2980}
2981
038d2ef8
MG		 2982static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2983{
2984 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2985 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2986 struct mlx5_ib_flow_handler,
2987 ibflow);
2988 struct mlx5_ib_flow_handler *iter, *tmp;
2989
9a4ca38d 2990 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2991
2992 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2993 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2994 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2995 list_del(&iter->list);
2996 kfree(iter);
2997 }
2998
74491de9 2999 mlx5_del_flow_rules(handler->rule);
5497adc6 3000 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3001 if (handler->ibcounters &&
3002 atomic_read(&handler->ibcounters->usecnt) == 1)
3003 counters_clear_description(handler->ibcounters);
038d2ef8 3004
3b3233fb 3005 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3006 kfree(handler);
3007
3008 return 0;
3009}
3010
35d19011
MG		 3011static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3012{
3013 priority *= 2;
3014 if (!dont_trap)
3015 priority++;
3016 return priority;
3017}
3018
cc0e5d42
MG		 3019enum flow_table_type {
3020 MLX5_IB_FT_RX,
3021 MLX5_IB_FT_TX
3022};
3023
00b7c2ab
MG		 3024#define MLX5_FS_MAX_TYPES 6
3025#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 3026static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3027 struct ib_flow_attr *flow_attr,
3028 enum flow_table_type ft_type)
038d2ef8 3029{
35d19011 3030 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3031 struct mlx5_flow_namespace *ns = NULL;
3032 struct mlx5_ib_flow_prio *prio;
3033 struct mlx5_flow_table *ft;
dac388ef 3034 int max_table_size;
038d2ef8
MG		 3035 int num_entries;
3036 int num_groups;
3037 int priority;
3038 int err = 0;
3039
dac388ef
MG		 3040 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3041 log_max_ft_size));
038d2ef8 3042 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
802c2125
AY		 3043 if (ft_type == MLX5_IB_FT_TX)
3044 priority = 0;
3045 else if (flow_is_multicast_only(flow_attr) &&
3046 !dont_trap)
038d2ef8
MG		 3047 priority = MLX5_IB_FLOW_MCAST_PRIO;
3048 else
35d19011
MG		 3049 priority = ib_prio_to_core_prio(flow_attr->priority,
3050 dont_trap);
038d2ef8 3051 ns = mlx5_get_flow_namespace(dev->mdev,
802c2125
AY		 3052 ft_type == MLX5_IB_FT_TX ?
3053 MLX5_FLOW_NAMESPACE_EGRESS :
038d2ef8
MG		 3054 MLX5_FLOW_NAMESPACE_BYPASS);
3055 num_entries = MLX5_FS_MAX_ENTRIES;
3056 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 3057 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 3058 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3059 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3060 ns = mlx5_get_flow_namespace(dev->mdev,
3061 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3062 build_leftovers_ft_param(&priority,
3063 &num_entries,
3064 &num_groups);
9a4ca38d 3065 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3066 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3067 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3068 allow_sniffer_and_nic_rx_shared_tir))
3069 return ERR_PTR(-ENOTSUPP);
3070
3071 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3072 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3073 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3074
9a4ca38d 3075 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3076 priority = 0;
3077 num_entries = 1;
3078 num_groups = 1;
038d2ef8
MG		 3079 }
3080
3081 if (!ns)
3082 return ERR_PTR(-ENOTSUPP);
3083
dac388ef
MG		 3084 if (num_entries > max_table_size)
3085 return ERR_PTR(-ENOMEM);
3086
038d2ef8
MG		 3087 ft = prio->flow_table;
3088 if (!ft) {
3089 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3090 num_entries,
d63cd286 3091 num_groups,
c9f1b073 3092 0, 0);
038d2ef8
MG		 3093
3094 if (!IS_ERR(ft)) {
3095 prio->refcount = 0;
3096 prio->flow_table = ft;
3097 } else {
3098 err = PTR_ERR(ft);
3099 }
3100 }
3101
3102 return err ? ERR_PTR(err) : prio;
3103}
3104
a550ddfc
YH		 3105static void set_underlay_qp(struct mlx5_ib_dev *dev,
3106 struct mlx5_flow_spec *spec,
3107 u32 underlay_qpn)
3108{
3109 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3110 spec->match_criteria,
3111 misc_parameters);
3112 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3113 misc_parameters);
3114
3115 if (underlay_qpn &&
3116 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3117 ft_field_support.bth_dst_qp)) {
3118 MLX5_SET(fte_match_set_misc,
3119 misc_params_v, bth_dst_qp, underlay_qpn);
3120 MLX5_SET(fte_match_set_misc,
3121 misc_params_c, bth_dst_qp, 0xffffff);
3122 }
3123}
3124
5e95af5f
RS		 3125static int read_flow_counters(struct ib_device *ibdev,
3126 struct mlx5_read_counters_attr *read_attr)
3127{
3128 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3129 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3130
3131 return mlx5_fc_query(dev->mdev, fc,
3132 &read_attr->out[IB_COUNTER_PACKETS],
3133 &read_attr->out[IB_COUNTER_BYTES]);
3134}
3135
3136/* flow counters currently expose two counters packets and bytes */
3137#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3138static int counters_set_description(struct ib_counters *counters,
3139 enum mlx5_ib_counters_type counters_type,
3140 struct mlx5_ib_flow_counters_desc *desc_data,
3141 u32 ncounters)
3142{
3143 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3144 u32 cntrs_max_index = 0;
3145 int i;
3146
3147 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3148 return -EINVAL;
3149
3150 /* init the fields for the object */
3151 mcounters->type = counters_type;
5e95af5f
RS		 3152 mcounters->read_counters = read_flow_counters;
3153 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3154 mcounters->ncounters = ncounters;
3155 /* each counter entry have both description and index pair */
3156 for (i = 0; i < ncounters; i++) {
3157 if (desc_data[i].description > IB_COUNTER_BYTES)
3158 return -EINVAL;
3159
3160 if (cntrs_max_index <= desc_data[i].index)
3161 cntrs_max_index = desc_data[i].index + 1;
3162 }
3163
3164 mutex_lock(&mcounters->mcntrs_mutex);
3165 mcounters->counters_data = desc_data;
3166 mcounters->cntrs_max_index = cntrs_max_index;
3167 mutex_unlock(&mcounters->mcntrs_mutex);
3168
3169 return 0;
3170}
3171
3172#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3173static int flow_counters_set_data(struct ib_counters *ibcounters,
3174 struct mlx5_ib_create_flow *ucmd)
3175{
3176 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3177 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3178 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3179 bool hw_hndl = false;
3180 int ret = 0;
3181
3182 if (ucmd && ucmd->ncounters_data != 0) {
3183 cntrs_data = ucmd->data;
3184 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3185 return -EINVAL;
3186
3187 desc_data = kcalloc(cntrs_data->ncounters,
3188 sizeof(*desc_data),
3189 GFP_KERNEL);
3190 if (!desc_data)
3191 return -ENOMEM;
3192
3193 if (copy_from_user(desc_data,
3194 u64_to_user_ptr(cntrs_data->counters_data),
3195 sizeof(*desc_data) * cntrs_data->ncounters)) {
3196 ret = -EFAULT;
3197 goto free;
3198 }
3199 }
3200
3201 if (!mcounters->hw_cntrs_hndl) {
3202 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3203 to_mdev(ibcounters->device)->mdev, false);
3204 if (!mcounters->hw_cntrs_hndl) {
3205 ret = -ENOMEM;
3206 goto free;
3207 }
3208 hw_hndl = true;
3209 }
3210
3211 if (desc_data) {
3212 /* counters already bound to at least one flow */
3213 if (mcounters->cntrs_max_index) {
3214 ret = -EINVAL;
3215 goto free_hndl;
3216 }
3217
3218 ret = counters_set_description(ibcounters,
3219 MLX5_IB_COUNTERS_FLOW,
3220 desc_data,
3221 cntrs_data->ncounters);
3222 if (ret)
3223 goto free_hndl;
3224
3225 } else if (!mcounters->cntrs_max_index) {
3226 /* counters not bound yet, must have udata passed */
3227 ret = -EINVAL;
3228 goto free_hndl;
3229 }
3230
3231 return 0;
3232
3233free_hndl:
3234 if (hw_hndl) {
3235 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3236 mcounters->hw_cntrs_hndl);
3237 mcounters->hw_cntrs_hndl = NULL;
3238 }
3239free:
3240 kfree(desc_data);
3241 return ret;
3242}
3243
a550ddfc
YH		 3244static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3245 struct mlx5_ib_flow_prio *ft_prio,
3246 const struct ib_flow_attr *flow_attr,
3247 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3248 u32 underlay_qpn,
3249 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3250{
3251 struct mlx5_flow_table *ft = ft_prio->flow_table;
3252 struct mlx5_ib_flow_handler *handler;
075572d4 3253 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3254 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3255 struct mlx5_flow_destination dest_arr[2] = {};
3256 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3257 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3258 unsigned int spec_index;
71c6e863 3259 u32 prev_type = 0;
038d2ef8 3260 int err = 0;
3b3233fb 3261 int dest_num = 0;
802c2125 3262 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3263
19cc7524 3264 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3265 return ERR_PTR(-EINVAL);
3266
1b9a07ee 3267 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3268 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3269 if (!handler || !spec) {
038d2ef8
MG		 3270 err = -ENOMEM;
3271 goto free;
3272 }
3273
3274 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3275 if (dst) {
3276 memcpy(&dest_arr[0], dst, sizeof(*dst));
3277 dest_num++;
3278 }
038d2ef8
MG		 3279
3280 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3281 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3282 spec->match_value,
71c6e863
AL		 3283 ib_flow, flow_attr, &flow_act,
3284 prev_type);
038d2ef8
MG		 3285 if (err < 0)
3286 goto free;
3287
71c6e863 3288 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3289 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3290 }
3291
a550ddfc
YH		 3292 if (!flow_is_multicast_only(flow_attr))
3293 set_underlay_qp(dev, spec, underlay_qpn);
3294
018a94ee
MB		 3295 if (dev->rep) {
3296 void *misc;
3297
3298 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3299 misc_parameters);
3300 MLX5_SET(fte_match_set_misc, misc, source_port,
3301 dev->rep->vport);
3302 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3303 misc_parameters);
3304 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3305 }
3306
466fa6d2 3307 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3308
3309 if (is_egress &&
3310 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3311 err = -EINVAL;
3312 goto free;
3313 }
3314
3b3233fb
RS		 3315 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3316 err = flow_counters_set_data(flow_act.counters, ucmd);
3317 if (err)
3318 goto free;
3319
3320 handler->ibcounters = flow_act.counters;
3321 dest_arr[dest_num].type =
3322 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3323 dest_arr[dest_num].counter =
3324 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3325 dest_num++;
3326 }
3327
075572d4 3328 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3329 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3330 rule_dst = NULL;
3331 dest_num = 0;
3332 }
a22ed86c 3333 } else {
802c2125
AY		 3334 if (is_egress)
3335 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3336 else
3337 flow_act.action |=
3b3233fb 3338 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3339 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3340 }
2ac693f9 3341
a9db0ecf 3342 if (flow_act.has_flow_tag &&
2ac693f9
MR		 3343 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3344 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3345 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3346 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3347 err = -EINVAL;
3348 goto free;
3349 }
74491de9 3350 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3351 &flow_act,
a22ed86c 3352 rule_dst, dest_num);
038d2ef8
MG		 3353
3354 if (IS_ERR(handler->rule)) {
3355 err = PTR_ERR(handler->rule);
3356 goto free;
3357 }
3358
d9d4980a 3359 ft_prio->refcount++;
5497adc6 3360 handler->prio = ft_prio;
038d2ef8
MG		 3361
3362 ft_prio->flow_table = ft;
3363free:
3b3233fb
RS		 3364 if (err && handler) {
3365 if (handler->ibcounters &&
3366 atomic_read(&handler->ibcounters->usecnt) == 1)
3367 counters_clear_description(handler->ibcounters);
038d2ef8 3368 kfree(handler);
3b3233fb 3369 }
c5bb1730 3370 kvfree(spec);
038d2ef8
MG		 3371 return err ? ERR_PTR(err) : handler;
3372}
3373
a550ddfc
YH		 3374static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3375 struct mlx5_ib_flow_prio *ft_prio,
3376 const struct ib_flow_attr *flow_attr,
3377 struct mlx5_flow_destination *dst)
3378{
3b3233fb 3379 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3380}
3381
35d19011
MG		 3382static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3383 struct mlx5_ib_flow_prio *ft_prio,
3384 struct ib_flow_attr *flow_attr,
3385 struct mlx5_flow_destination *dst)
3386{
3387 struct mlx5_ib_flow_handler *handler_dst = NULL;
3388 struct mlx5_ib_flow_handler *handler = NULL;
3389
3390 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3391 if (!IS_ERR(handler)) {
3392 handler_dst = create_flow_rule(dev, ft_prio,
3393 flow_attr, dst);
3394 if (IS_ERR(handler_dst)) {
74491de9 3395 mlx5_del_flow_rules(handler->rule);
d9d4980a 3396 ft_prio->refcount--;
35d19011
MG		 3397 kfree(handler);
3398 handler = handler_dst;
3399 } else {
3400 list_add(&handler_dst->list, &handler->list);
3401 }
3402 }
3403
3404 return handler;
3405}
038d2ef8
MG		 3406enum {
3407 LEFTOVERS_MC,
3408 LEFTOVERS_UC,
3409};
3410
3411static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3412 struct mlx5_ib_flow_prio *ft_prio,
3413 struct ib_flow_attr *flow_attr,
3414 struct mlx5_flow_destination *dst)
3415{
3416 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3417 struct mlx5_ib_flow_handler *handler = NULL;
3418
3419 static struct {
3420 struct ib_flow_attr flow_attr;
3421 struct ib_flow_spec_eth eth_flow;
3422 } leftovers_specs[] = {
3423 [LEFTOVERS_MC] = {
3424 .flow_attr = {
3425 .num_of_specs = 1,
3426 .size = sizeof(leftovers_specs[0])
3427 },
3428 .eth_flow = {
3429 .type = IB_FLOW_SPEC_ETH,
3430 .size = sizeof(struct ib_flow_spec_eth),
3431 .mask = {.dst_mac = {0x1} },
3432 .val = {.dst_mac = {0x1} }
3433 }
3434 },
3435 [LEFTOVERS_UC] = {
3436 .flow_attr = {
3437 .num_of_specs = 1,
3438 .size = sizeof(leftovers_specs[0])
3439 },
3440 .eth_flow = {
3441 .type = IB_FLOW_SPEC_ETH,
3442 .size = sizeof(struct ib_flow_spec_eth),
3443 .mask = {.dst_mac = {0x1} },
3444 .val = {.dst_mac = {} }
3445 }
3446 }
3447 };
3448
3449 handler = create_flow_rule(dev, ft_prio,
3450 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3451 dst);
3452 if (!IS_ERR(handler) &&
3453 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3454 handler_ucast = create_flow_rule(dev, ft_prio,
3455 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3456 dst);
3457 if (IS_ERR(handler_ucast)) {
74491de9 3458 mlx5_del_flow_rules(handler->rule);
d9d4980a 3459 ft_prio->refcount--;
038d2ef8
MG		 3460 kfree(handler);
3461 handler = handler_ucast;
3462 } else {
3463 list_add(&handler_ucast->list, &handler->list);
3464 }
3465 }
3466
3467 return handler;
3468}
3469
cc0e5d42
MG		 3470static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3471 struct mlx5_ib_flow_prio *ft_rx,
3472 struct mlx5_ib_flow_prio *ft_tx,
3473 struct mlx5_flow_destination *dst)
3474{
3475 struct mlx5_ib_flow_handler *handler_rx;
3476 struct mlx5_ib_flow_handler *handler_tx;
3477 int err;
3478 static const struct ib_flow_attr flow_attr = {
3479 .num_of_specs = 0,
3480 .size = sizeof(flow_attr)
3481 };
3482
3483 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3484 if (IS_ERR(handler_rx)) {
3485 err = PTR_ERR(handler_rx);
3486 goto err;
3487 }
3488
3489 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3490 if (IS_ERR(handler_tx)) {
3491 err = PTR_ERR(handler_tx);
3492 goto err_tx;
3493 }
3494
3495 list_add(&handler_tx->list, &handler_rx->list);
3496
3497 return handler_rx;
3498
3499err_tx:
74491de9 3500 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3501 ft_rx->refcount--;
3502 kfree(handler_rx);
3503err:
3504 return ERR_PTR(err);
3505}
3506
038d2ef8
MG		 3507static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3508 struct ib_flow_attr *flow_attr,
59082a32
MB		 3509 int domain,
3510 struct ib_udata *udata)
038d2ef8
MG		 3511{
3512 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3513 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3514 struct mlx5_ib_flow_handler *handler = NULL;
3515 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3516 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3517 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3518 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3519 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3520 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3521 int err;
a550ddfc 3522 int underlay_qpn;
038d2ef8 3523
3b3233fb
RS		 3524 if (udata && udata->inlen) {
3525 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3526 sizeof(ucmd_hdr.reserved);
3527 if (udata->inlen < min_ucmd_sz)
3528 return ERR_PTR(-EOPNOTSUPP);
3529
3530 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3531 if (err)
3532 return ERR_PTR(err);
3533
3534 /* currently supports only one counters data */
3535 if (ucmd_hdr.ncounters_data > 1)
3536 return ERR_PTR(-EINVAL);
3537
3538 required_ucmd_sz = min_ucmd_sz +
3539 sizeof(struct mlx5_ib_flow_counters_data) *
3540 ucmd_hdr.ncounters_data;
3541 if (udata->inlen > required_ucmd_sz &&
3542 !ib_is_udata_cleared(udata, required_ucmd_sz,
3543 udata->inlen - required_ucmd_sz))
3544 return ERR_PTR(-EOPNOTSUPP);
3545
3546 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3547 if (!ucmd)
3548 return ERR_PTR(-ENOMEM);
3549
3550 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3551 if (err) {
3552 kfree(ucmd);
3553 return ERR_PTR(err);
3554 }
3555 }
59082a32 3556
038d2ef8 3557 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 3558 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 3559
3560 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3561 flow_attr->port > dev->num_ports ||
802c2125
AY		 3562 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3563 IB_FLOW_ATTR_FLAGS_EGRESS)))
3564 return ERR_PTR(-EINVAL);
3565
3566 if (is_egress &&
3567 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3568 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
038d2ef8
MG		 3569 return ERR_PTR(-EINVAL);
3570
3571 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3572 if (!dst)
3573 return ERR_PTR(-ENOMEM);
3574
9a4ca38d 3575 mutex_lock(&dev->flow_db->lock);
038d2ef8 3576
802c2125
AY		 3577 ft_prio = get_flow_table(dev, flow_attr,
3578 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3579 if (IS_ERR(ft_prio)) {
3580 err = PTR_ERR(ft_prio);
3581 goto unlock;
3582 }
cc0e5d42
MG		 3583 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3584 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3585 if (IS_ERR(ft_prio_tx)) {
3586 err = PTR_ERR(ft_prio_tx);
3587 ft_prio_tx = NULL;
3588 goto destroy_ft;
3589 }
3590 }
038d2ef8 3591
802c2125
AY		 3592 if (is_egress) {
3593 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3594 } else {
3595 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3596 if (mqp->flags & MLX5_IB_QP_RSS)
3597 dst->tir_num = mqp->rss_qp.tirn;
3598 else
3599 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3600 }
038d2ef8
MG		 3601
3602 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3603 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3604 handler = create_dont_trap_rule(dev, ft_prio,
3605 flow_attr, dst);
3606 } else {
a550ddfc
YH		 3607 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3608 mqp->underlay_qpn : 0;
3609 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3610 dst, underlay_qpn, ucmd);
35d19011 3611 }
038d2ef8
MG		 3612 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3613 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3614 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3615 dst);
cc0e5d42
MG		 3616 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3617 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3618 } else {
3619 err = -EINVAL;
3620 goto destroy_ft;
3621 }
3622
3623 if (IS_ERR(handler)) {
3624 err = PTR_ERR(handler);
3625 handler = NULL;
3626 goto destroy_ft;
3627 }
3628
9a4ca38d 3629 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3630 kfree(dst);
3b3233fb 3631 kfree(ucmd);
038d2ef8
MG		 3632
3633 return &handler->ibflow;
3634
3635destroy_ft:
3636 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3637 if (ft_prio_tx)
3638 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3639unlock:
9a4ca38d 3640 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3641 kfree(dst);
3b3233fb 3642 kfree(ucmd);
038d2ef8
MG		 3643 kfree(handler);
3644 return ERR_PTR(err);
3645}
3646
c6475a0b
AY		 3647static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3648{
3649 u32 flags = 0;
3650
3651 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3652 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3653
3654 return flags;
3655}
3656
3657#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3658static struct ib_flow_action *
3659mlx5_ib_create_flow_action_esp(struct ib_device *device,
3660 const struct ib_flow_action_attrs_esp *attr,
3661 struct uverbs_attr_bundle *attrs)
3662{
3663 struct mlx5_ib_dev *mdev = to_mdev(device);
3664 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3665 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3666 struct mlx5_ib_flow_action *action;
3667 u64 action_flags;
3668 u64 flags;
3669 int err = 0;
3670
3671 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3672 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3673 return ERR_PTR(-EFAULT);
3674
3675 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3676 return ERR_PTR(-EOPNOTSUPP);
3677
3678 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3679
3680 /* We current only support a subset of the standard features. Only a
3681 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3682 * (with overlap). Full offload mode isn't supported.
3683 */
3684 if (!attr->keymat || attr->replay || attr->encap ||
3685 attr->spi || attr->seq || attr->tfc_pad ||
3686 attr->hard_limit_pkts ||
3687 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3688 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3689 return ERR_PTR(-EOPNOTSUPP);
3690
3691 if (attr->keymat->protocol !=
3692 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3693 return ERR_PTR(-EOPNOTSUPP);
3694
3695 aes_gcm = &attr->keymat->keymat.aes_gcm;
3696
3697 if (aes_gcm->icv_len != 16 ||
3698 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3699 return ERR_PTR(-EOPNOTSUPP);
3700
3701 action = kmalloc(sizeof(*action), GFP_KERNEL);
3702 if (!action)
3703 return ERR_PTR(-ENOMEM);
3704
3705 action->esp_aes_gcm.ib_flags = attr->flags;
3706 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3707 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3708 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3709 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3710 sizeof(accel_attrs.keymat.aes_gcm.salt));
3711 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3712 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3713 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3714 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3715 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3716
3717 accel_attrs.esn = attr->esn;
3718 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3719 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3720 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3721 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3722
3723 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3724 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3725
3726 action->esp_aes_gcm.ctx =
3727 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3728 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3729 err = PTR_ERR(action->esp_aes_gcm.ctx);
3730 goto err_parse;
3731 }
3732
3733 action->esp_aes_gcm.ib_flags = attr->flags;
3734
3735 return &action->ib_action;
3736
3737err_parse:
3738 kfree(action);
3739 return ERR_PTR(err);
3740}
3741
349705c1
MB		 3742static int
3743mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3744 const struct ib_flow_action_attrs_esp *attr,
3745 struct uverbs_attr_bundle *attrs)
3746{
3747 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3748 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3749 int err = 0;
3750
3751 if (attr->keymat || attr->replay || attr->encap ||
3752 attr->spi || attr->seq || attr->tfc_pad ||
3753 attr->hard_limit_pkts ||
3754 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3755 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3756 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3757 return -EOPNOTSUPP;
3758
3759 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3760 * be modified.
3761 */
3762 if (!(maction->esp_aes_gcm.ib_flags &
3763 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3764 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3765 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3766 return -EINVAL;
3767
3768 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3769 sizeof(accel_attrs));
3770
3771 accel_attrs.esn = attr->esn;
3772 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3773 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3774 else
3775 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3776
3777 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3778 &accel_attrs);
3779 if (err)
3780 return err;
3781
3782 maction->esp_aes_gcm.ib_flags &=
3783 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3784 maction->esp_aes_gcm.ib_flags |=
3785 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3786
3787 return 0;
3788}
3789
c6475a0b
AY		 3790static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3791{
3792 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3793
3794 switch (action->type) {
3795 case IB_FLOW_ACTION_ESP:
3796 /*
3797 * We only support aes_gcm by now, so we implicitly know this is
3798 * the underline crypto.
3799 */
3800 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3801 break;
3802 default:
3803 WARN_ON(true);
3804 break;
3805 }
3806
3807 kfree(maction);
3808 return 0;
3809}
3810
e126ba97
EC		 3811static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3812{
3813 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 3814 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 3815 int err;
3816
81e30880
YH		 3817 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3818 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3819 return -EOPNOTSUPP;
3820 }
3821
9603b61d 3822 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3823 if (err)
3824 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3825 ibqp->qp_num, gid->raw);
3826
3827 return err;
3828}
3829
3830static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3831{
3832 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3833 int err;
3834
9603b61d 3835 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3836 if (err)
3837 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3838 ibqp->qp_num, gid->raw);
3839
3840 return err;
3841}
3842
3843static int init_node_data(struct mlx5_ib_dev *dev)
3844{
1b5daf11 3845 int err;
e126ba97 3846
1b5daf11 3847 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 3848 if (err)
1b5daf11 3849 return err;
e126ba97 3850
1b5daf11 3851 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 3852
1b5daf11 3853 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 3854}
3855
3856static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3857 char *buf)
3858{
3859 struct mlx5_ib_dev *dev =
3860 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3861
9603b61d 3862 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 3863}
3864
3865static ssize_t show_reg_pages(struct device *device,
3866 struct device_attribute *attr, char *buf)
3867{
3868 struct mlx5_ib_dev *dev =
3869 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3870
6aec21f6 3871 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3872}
3873
3874static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3875 char *buf)
3876{
3877 struct mlx5_ib_dev *dev =
3878 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3879 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3880}
3881
e126ba97
EC		 3882static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3883 char *buf)
3884{
3885 struct mlx5_ib_dev *dev =
3886 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3887 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3888}
3889
3890static ssize_t show_board(struct device *device, struct device_attribute *attr,
3891 char *buf)
3892{
3893 struct mlx5_ib_dev *dev =
3894 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3895 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3896 dev->mdev->board_id);
e126ba97
EC		 3897}
3898
3899static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3900static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3901static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3902static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3903static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3904
3905static struct device_attribute *mlx5_class_attributes[] = {
3906 &dev_attr_hw_rev,
e126ba97
EC		 3907 &dev_attr_hca_type,
3908 &dev_attr_board_id,
3909 &dev_attr_fw_pages,
3910 &dev_attr_reg_pages,
3911};
3912
7722f47e
HE		 3913static void pkey_change_handler(struct work_struct *work)
3914{
3915 struct mlx5_ib_port_resources *ports =
3916 container_of(work, struct mlx5_ib_port_resources,
3917 pkey_change_work);
3918
3919 mutex_lock(&ports->devr->mutex);
3920 mlx5_ib_gsi_pkey_change(ports->gsi);
3921 mutex_unlock(&ports->devr->mutex);
3922}
3923
89ea94a7
MG		 3924static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3925{
3926 struct mlx5_ib_qp *mqp;
3927 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3928 struct mlx5_core_cq *mcq;
3929 struct list_head cq_armed_list;
3930 unsigned long flags_qp;
3931 unsigned long flags_cq;
3932 unsigned long flags;
3933
3934 INIT_LIST_HEAD(&cq_armed_list);
3935
3936 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3937 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3938 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3939 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3940 if (mqp->sq.tail != mqp->sq.head) {
3941 send_mcq = to_mcq(mqp->ibqp.send_cq);
3942 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3943 if (send_mcq->mcq.comp &&
3944 mqp->ibqp.send_cq->comp_handler) {
3945 if (!send_mcq->mcq.reset_notify_added) {
3946 send_mcq->mcq.reset_notify_added = 1;
3947 list_add_tail(&send_mcq->mcq.reset_notify,
3948 &cq_armed_list);
3949 }
3950 }
3951 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3952 }
3953 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3954 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3955 /* no handling is needed for SRQ */
3956 if (!mqp->ibqp.srq) {
3957 if (mqp->rq.tail != mqp->rq.head) {
3958 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3959 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3960 if (recv_mcq->mcq.comp &&
3961 mqp->ibqp.recv_cq->comp_handler) {
3962 if (!recv_mcq->mcq.reset_notify_added) {
3963 recv_mcq->mcq.reset_notify_added = 1;
3964 list_add_tail(&recv_mcq->mcq.reset_notify,
3965 &cq_armed_list);
3966 }
3967 }
3968 spin_unlock_irqrestore(&recv_mcq->lock,
3969 flags_cq);
3970 }
3971 }
3972 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3973 }
3974 /*At that point all inflight post send were put to be executed as of we
3975 * lock/unlock above locks Now need to arm all involved CQs.
3976 */
3977 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3978 mcq->comp(mcq);
3979 }
3980 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3981}
3982
03404e8a
MG		 3983static void delay_drop_handler(struct work_struct *work)
3984{
3985 int err;
3986 struct mlx5_ib_delay_drop *delay_drop =
3987 container_of(work, struct mlx5_ib_delay_drop,
3988 delay_drop_work);
3989
fe248c3a
MG		 3990 atomic_inc(&delay_drop->events_cnt);
3991
03404e8a
MG		 3992 mutex_lock(&delay_drop->lock);
3993 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3994 delay_drop->timeout);
3995 if (err) {
3996 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3997 delay_drop->timeout);
3998 delay_drop->activate = false;
3999 }
4000 mutex_unlock(&delay_drop->lock);
4001}
4002
d69a24e0 4003static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4004{
d69a24e0
DJ		 4005 struct mlx5_ib_event_work *work =
4006 container_of(_work, struct mlx5_ib_event_work, work);
4007 struct mlx5_ib_dev *ibdev;
e126ba97 4008 struct ib_event ibev;
dbaaff2a 4009 bool fatal = false;
aba46213 4010 u8 port = (u8)work->param;
e126ba97 4011
d69a24e0
DJ		 4012 if (mlx5_core_is_mp_slave(work->dev)) {
4013 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4014 if (!ibdev)
4015 goto out;
4016 } else {
4017 ibdev = work->context;
4018 }
4019
4020 switch (work->event) {
e126ba97 4021 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4022 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4023 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 4024 fatal = true;
e126ba97
EC		 4025 break;
4026
4027 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 4028 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 4029 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 4030 /* In RoCE, port up/down events are handled in
4031 * mlx5_netdev_event().
4032 */
4033 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4034 IB_LINK_LAYER_ETHERNET)
d69a24e0 4035 goto out;
5ec8c83e 4036
d69a24e0 4037 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 4038 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 4039 break;
4040
e126ba97
EC		 4041 case MLX5_DEV_EVENT_LID_CHANGE:
4042 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 4043 break;
4044
4045 case MLX5_DEV_EVENT_PKEY_CHANGE:
4046 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 4047 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 4048 break;
4049
4050 case MLX5_DEV_EVENT_GUID_CHANGE:
4051 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 4052 break;
4053
4054 case MLX5_DEV_EVENT_CLIENT_REREG:
4055 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 4056 break;
03404e8a
MG		 4057 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4058 schedule_work(&ibdev->delay_drop.delay_drop_work);
4059 goto out;
bdc37924 4060 default:
03404e8a 4061 goto out;
e126ba97
EC		 4062 }
4063
4064 ibev.device = &ibdev->ib_dev;
4065 ibev.element.port_num = port;
4066
aba46213 4067 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 4068 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 4069 goto out;
a0c84c32
EC		 4070 }
4071
e126ba97
EC		 4072 if (ibdev->ib_active)
4073 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4074
4075 if (fatal)
4076 ibdev->ib_active = false;
03404e8a 4077out:
d69a24e0
DJ		 4078 kfree(work);
4079}
4080
4081static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4082 enum mlx5_dev_event event, unsigned long param)
4083{
4084 struct mlx5_ib_event_work *work;
4085
4086 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4087 if (!work)
d69a24e0 4088 return;
d69a24e0 4089
10bea9c8
LR		 4090 INIT_WORK(&work->work, mlx5_ib_handle_event);
4091 work->dev = dev;
4092 work->param = param;
4093 work->context = context;
4094 work->event = event;
4095
4096 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 4097}
4098
c43f1112
MG		 4099static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4100{
4101 struct mlx5_hca_vport_context vport_ctx;
4102 int err;
4103 int port;
4104
508562d6 4105 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 4106 dev->mdev->port_caps[port - 1].has_smi = false;
4107 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4108 MLX5_CAP_PORT_TYPE_IB) {
4109 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4110 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4111 port, 0,
4112 &vport_ctx);
4113 if (err) {
4114 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4115 port, err);
4116 return err;
4117 }
4118 dev->mdev->port_caps[port - 1].has_smi =
4119 vport_ctx.has_smi;
4120 } else {
4121 dev->mdev->port_caps[port - 1].has_smi = true;
4122 }
4123 }
4124 }
4125 return 0;
4126}
4127
e126ba97
EC		 4128static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4129{
4130 int port;
4131
508562d6 4132 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4133 mlx5_query_ext_port_caps(dev, port);
4134}
4135
32f69e4b 4136static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4137{
4138 struct ib_device_attr *dprops = NULL;
4139 struct ib_port_attr *pprops = NULL;
f614fc15 4140 int err = -ENOMEM;
2528e33e 4141 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4142
4143 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4144 if (!pprops)
4145 goto out;
4146
4147 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4148 if (!dprops)
4149 goto out;
4150
c43f1112
MG		 4151 err = set_has_smi_cap(dev);
4152 if (err)
4153 goto out;
4154
2528e33e 4155 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4156 if (err) {
4157 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4158 goto out;
4159 }
4160
32f69e4b
DJ		 4161 memset(pprops, 0, sizeof(*pprops));
4162 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4163 if (err) {
4164 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4165 port, err);
4166 goto out;
e126ba97
EC		 4167 }
4168
32f69e4b
DJ		 4169 dev->mdev->port_caps[port - 1].pkey_table_len =
4170 dprops->max_pkeys;
4171 dev->mdev->port_caps[port - 1].gid_table_len =
4172 pprops->gid_tbl_len;
4173 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4174 port, dprops->max_pkeys, pprops->gid_tbl_len);
4175
e126ba97
EC		 4176out:
4177 kfree(pprops);
4178 kfree(dprops);
4179
4180 return err;
4181}
4182
4183static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4184{
4185 int err;
4186
4187 err = mlx5_mr_cache_cleanup(dev);
4188 if (err)
4189 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4190
32927e28
MB		 4191 if (dev->umrc.qp)
4192 mlx5_ib_destroy_qp(dev->umrc.qp);
4193 if (dev->umrc.cq)
4194 ib_free_cq(dev->umrc.cq);
4195 if (dev->umrc.pd)
4196 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4197}
4198
4199enum {
4200 MAX_UMR_WR = 128,
4201};
4202
4203static int create_umr_res(struct mlx5_ib_dev *dev)
4204{
4205 struct ib_qp_init_attr *init_attr = NULL;
4206 struct ib_qp_attr *attr = NULL;
4207 struct ib_pd *pd;
4208 struct ib_cq *cq;
4209 struct ib_qp *qp;
e126ba97
EC		 4210 int ret;
4211
4212 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4213 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4214 if (!attr || !init_attr) {
4215 ret = -ENOMEM;
4216 goto error_0;
4217 }
4218
ed082d36 4219 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4220 if (IS_ERR(pd)) {
4221 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4222 ret = PTR_ERR(pd);
4223 goto error_0;
4224 }
4225
add08d76 4226 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4227 if (IS_ERR(cq)) {
4228 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4229 ret = PTR_ERR(cq);
4230 goto error_2;
4231 }
e126ba97
EC		 4232
4233 init_attr->send_cq = cq;
4234 init_attr->recv_cq = cq;
4235 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4236 init_attr->cap.max_send_wr = MAX_UMR_WR;
4237 init_attr->cap.max_send_sge = 1;
4238 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4239 init_attr->port_num = 1;
4240 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4241 if (IS_ERR(qp)) {
4242 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4243 ret = PTR_ERR(qp);
4244 goto error_3;
4245 }
4246 qp->device = &dev->ib_dev;
4247 qp->real_qp = qp;
4248 qp->uobject = NULL;
4249 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4250 qp->send_cq = init_attr->send_cq;
4251 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4252
4253 attr->qp_state = IB_QPS_INIT;
4254 attr->port_num = 1;
4255 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4256 IB_QP_PORT, NULL);
4257 if (ret) {
4258 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4259 goto error_4;
4260 }
4261
4262 memset(attr, 0, sizeof(*attr));
4263 attr->qp_state = IB_QPS_RTR;
4264 attr->path_mtu = IB_MTU_256;
4265
4266 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4267 if (ret) {
4268 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4269 goto error_4;
4270 }
4271
4272 memset(attr, 0, sizeof(*attr));
4273 attr->qp_state = IB_QPS_RTS;
4274 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4275 if (ret) {
4276 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4277 goto error_4;
4278 }
4279
4280 dev->umrc.qp = qp;
4281 dev->umrc.cq = cq;
e126ba97
EC		 4282 dev->umrc.pd = pd;
4283
4284 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4285 ret = mlx5_mr_cache_init(dev);
4286 if (ret) {
4287 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4288 goto error_4;
4289 }
4290
4291 kfree(attr);
4292 kfree(init_attr);
4293
4294 return 0;
4295
4296error_4:
4297 mlx5_ib_destroy_qp(qp);
32927e28 4298 dev->umrc.qp = NULL;
e126ba97
EC		 4299
4300error_3:
add08d76 4301 ib_free_cq(cq);
32927e28 4302 dev->umrc.cq = NULL;
e126ba97
EC		 4303
4304error_2:
e126ba97 4305 ib_dealloc_pd(pd);
32927e28 4306 dev->umrc.pd = NULL;
e126ba97
EC		 4307
4308error_0:
4309 kfree(attr);
4310 kfree(init_attr);
4311 return ret;
4312}
4313
6e8484c5
MG		 4314static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4315{
4316 switch (umr_fence_cap) {
4317 case MLX5_CAP_UMR_FENCE_NONE:
4318 return MLX5_FENCE_MODE_NONE;
4319 case MLX5_CAP_UMR_FENCE_SMALL:
4320 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4321 default:
4322 return MLX5_FENCE_MODE_STRONG_ORDERING;
4323 }
4324}
4325
e126ba97
EC		 4326static int create_dev_resources(struct mlx5_ib_resources *devr)
4327{
4328 struct ib_srq_init_attr attr;
4329 struct mlx5_ib_dev *dev;
bcf4c1ea 4330 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4331 int port;
e126ba97
EC		 4332 int ret = 0;
4333
4334 dev = container_of(devr, struct mlx5_ib_dev, devr);
4335
d16e91da
HE		 4336 mutex_init(&devr->mutex);
4337
e126ba97
EC		 4338 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4339 if (IS_ERR(devr->p0)) {
4340 ret = PTR_ERR(devr->p0);
4341 goto error0;
4342 }
4343 devr->p0->device = &dev->ib_dev;
4344 devr->p0->uobject = NULL;
4345 atomic_set(&devr->p0->usecnt, 0);
4346
bcf4c1ea 4347 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4348 if (IS_ERR(devr->c0)) {
4349 ret = PTR_ERR(devr->c0);
4350 goto error1;
4351 }
4352 devr->c0->device = &dev->ib_dev;
4353 devr->c0->uobject = NULL;
4354 devr->c0->comp_handler = NULL;
4355 devr->c0->event_handler = NULL;
4356 devr->c0->cq_context = NULL;
4357 atomic_set(&devr->c0->usecnt, 0);
4358
4359 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4360 if (IS_ERR(devr->x0)) {
4361 ret = PTR_ERR(devr->x0);
4362 goto error2;
4363 }
4364 devr->x0->device = &dev->ib_dev;
4365 devr->x0->inode = NULL;
4366 atomic_set(&devr->x0->usecnt, 0);
4367 mutex_init(&devr->x0->tgt_qp_mutex);
4368 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4369
4370 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4371 if (IS_ERR(devr->x1)) {
4372 ret = PTR_ERR(devr->x1);
4373 goto error3;
4374 }
4375 devr->x1->device = &dev->ib_dev;
4376 devr->x1->inode = NULL;
4377 atomic_set(&devr->x1->usecnt, 0);
4378 mutex_init(&devr->x1->tgt_qp_mutex);
4379 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4380
4381 memset(&attr, 0, sizeof(attr));
4382 attr.attr.max_sge = 1;
4383 attr.attr.max_wr = 1;
4384 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4385 attr.ext.cq = devr->c0;
e126ba97
EC		 4386 attr.ext.xrc.xrcd = devr->x0;
4387
4388 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4389 if (IS_ERR(devr->s0)) {
4390 ret = PTR_ERR(devr->s0);
4391 goto error4;
4392 }
4393 devr->s0->device = &dev->ib_dev;
4394 devr->s0->pd = devr->p0;
4395 devr->s0->uobject = NULL;
4396 devr->s0->event_handler = NULL;
4397 devr->s0->srq_context = NULL;
4398 devr->s0->srq_type = IB_SRQT_XRC;
4399 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4400 devr->s0->ext.cq = devr->c0;
e126ba97 4401 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4402 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4403 atomic_inc(&devr->p0->usecnt);
4404 atomic_set(&devr->s0->usecnt, 0);
4405
4aa17b28
HA		 4406 memset(&attr, 0, sizeof(attr));
4407 attr.attr.max_sge = 1;
4408 attr.attr.max_wr = 1;
4409 attr.srq_type = IB_SRQT_BASIC;
4410 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4411 if (IS_ERR(devr->s1)) {
4412 ret = PTR_ERR(devr->s1);
4413 goto error5;
4414 }
4415 devr->s1->device = &dev->ib_dev;
4416 devr->s1->pd = devr->p0;
4417 devr->s1->uobject = NULL;
4418 devr->s1->event_handler = NULL;
4419 devr->s1->srq_context = NULL;
4420 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4421 devr->s1->ext.cq = devr->c0;
4aa17b28 4422 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4423 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4424
7722f47e
HE		 4425 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4426 INIT_WORK(&devr->ports[port].pkey_change_work,
4427 pkey_change_handler);
4428 devr->ports[port].devr = devr;
4429 }
4430
e126ba97
EC		 4431 return 0;
4432
4aa17b28
HA		 4433error5:
4434 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4435error4:
4436 mlx5_ib_dealloc_xrcd(devr->x1);
4437error3:
4438 mlx5_ib_dealloc_xrcd(devr->x0);
4439error2:
4440 mlx5_ib_destroy_cq(devr->c0);
4441error1:
4442 mlx5_ib_dealloc_pd(devr->p0);
4443error0:
4444 return ret;
4445}
4446
4447static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4448{
7722f47e
HE		 4449 struct mlx5_ib_dev *dev =
4450 container_of(devr, struct mlx5_ib_dev, devr);
4451 int port;
4452
4aa17b28 4453 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4454 mlx5_ib_destroy_srq(devr->s0);
4455 mlx5_ib_dealloc_xrcd(devr->x0);
4456 mlx5_ib_dealloc_xrcd(devr->x1);
4457 mlx5_ib_destroy_cq(devr->c0);
4458 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4459
4460 /* Make sure no change P_Key work items are still executing */
4461 for (port = 0; port < dev->num_ports; ++port)
4462 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4463}
4464
e53505a8
AS		 4465static u32 get_core_cap_flags(struct ib_device *ibdev)
4466{
4467 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4468 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4469 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4470 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4471 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4472 u32 ret = 0;
4473
4474 if (ll == IB_LINK_LAYER_INFINIBAND)
4475 return RDMA_CORE_PORT_IBA_IB;
4476
85c7c014
DJ		 4477 if (raw_support)
4478 ret = RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4479
e53505a8 4480 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4481 return ret;
e53505a8
AS		 4482
4483 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4484 return ret;
e53505a8
AS		 4485
4486 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4487 ret |= RDMA_CORE_PORT_IBA_ROCE;
4488
4489 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4490 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4491
4492 return ret;
4493}
4494
7738613e
IW		 4495static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4496 struct ib_port_immutable *immutable)
4497{
4498 struct ib_port_attr attr;
ca5b91d6
OG		 4499 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4500 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 4501 int err;
4502
c4550c63
OG		 4503 immutable->core_cap_flags = get_core_cap_flags(ibdev);
4504
4505 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4506 if (err)
4507 return err;
4508
4509 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4510 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 4511 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 4512 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4513 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4514
4515 return 0;
4516}
4517
8e6efa3a
MB		 4518static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4519 struct ib_port_immutable *immutable)
4520{
4521 struct ib_port_attr attr;
4522 int err;
4523
4524 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4525
4526 err = ib_query_port(ibdev, port_num, &attr);
4527 if (err)
4528 return err;
4529
4530 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4531 immutable->gid_tbl_len = attr.gid_tbl_len;
4532 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4533
4534 return 0;
4535}
4536
9abb0d1b 4537static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4538{
4539 struct mlx5_ib_dev *dev =
4540 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4541 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4542 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4543 fw_rev_sub(dev->mdev));
c7342823
IW		 4544}
4545
45f95acd 4546static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4547{
4548 struct mlx5_core_dev *mdev = dev->mdev;
4549 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4550 MLX5_FLOW_NAMESPACE_LAG);
4551 struct mlx5_flow_table *ft;
4552 int err;
4553
4554 if (!ns || !mlx5_lag_is_active(mdev))
4555 return 0;
4556
4557 err = mlx5_cmd_create_vport_lag(mdev);
4558 if (err)
4559 return err;
4560
4561 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4562 if (IS_ERR(ft)) {
4563 err = PTR_ERR(ft);
4564 goto err_destroy_vport_lag;
4565 }
4566
9a4ca38d 4567 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4568 return 0;
4569
4570err_destroy_vport_lag:
4571 mlx5_cmd_destroy_vport_lag(mdev);
4572 return err;
4573}
4574
45f95acd 4575static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4576{
4577 struct mlx5_core_dev *mdev = dev->mdev;
4578
9a4ca38d
MB		 4579 if (dev->flow_db->lag_demux_ft) {
4580 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4581 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4582
4583 mlx5_cmd_destroy_vport_lag(mdev);
4584 }
4585}
4586
7fd8aefb 4587static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4588{
4589 int err;
4590
7fd8aefb
DJ		 4591 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4592 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4593 if (err) {
7fd8aefb 4594 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4595 return err;
4596 }
4597
4598 return 0;
4599}
4600
7fd8aefb 4601static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4602{
7fd8aefb
DJ		 4603 if (dev->roce[port_num].nb.notifier_call) {
4604 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4605 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4606 }
4607}
4608
e3f1ed1f 4609static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4610{
e53505a8
AS		 4611 int err;
4612
ca5b91d6
OG		 4613 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4614 err = mlx5_nic_vport_enable_roce(dev->mdev);
4615 if (err)
8e6efa3a 4616 return err;
ca5b91d6 4617 }
e53505a8 4618
45f95acd 4619 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4620 if (err)
4621 goto err_disable_roce;
4622
e53505a8
AS		 4623 return 0;
4624
9ef9c640 4625err_disable_roce:
ca5b91d6
OG		 4626 if (MLX5_CAP_GEN(dev->mdev, roce))
4627 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4628
e53505a8 4629 return err;
fc24fc5e
AS		 4630}
4631
45f95acd 4632static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4633{
45f95acd 4634 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4635 if (MLX5_CAP_GEN(dev->mdev, roce))
4636 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4637}
4638
e1f24a79 4639struct mlx5_ib_counter {
7c16f477
KH		 4640 const char *name;
4641 size_t offset;
4642};
4643
4644#define INIT_Q_COUNTER(_name) \
4645 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4646
e1f24a79 4647static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4648 INIT_Q_COUNTER(rx_write_requests),
4649 INIT_Q_COUNTER(rx_read_requests),
4650 INIT_Q_COUNTER(rx_atomic_requests),
4651 INIT_Q_COUNTER(out_of_buffer),
4652};
4653
e1f24a79 4654static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4655 INIT_Q_COUNTER(out_of_sequence),
4656};
4657
e1f24a79 4658static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4659 INIT_Q_COUNTER(duplicate_request),
4660 INIT_Q_COUNTER(rnr_nak_retry_err),
4661 INIT_Q_COUNTER(packet_seq_err),
4662 INIT_Q_COUNTER(implied_nak_seq_err),
4663 INIT_Q_COUNTER(local_ack_timeout_err),
4664};
4665
e1f24a79
PP		 4666#define INIT_CONG_COUNTER(_name) \
4667 { .name = #_name, .offset = \
4668 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4669
4670static const struct mlx5_ib_counter cong_cnts[] = {
4671 INIT_CONG_COUNTER(rp_cnp_ignored),
4672 INIT_CONG_COUNTER(rp_cnp_handled),
4673 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4674 INIT_CONG_COUNTER(np_cnp_sent),
4675};
4676
58dcb60a
PP		 4677static const struct mlx5_ib_counter extended_err_cnts[] = {
4678 INIT_Q_COUNTER(resp_local_length_error),
4679 INIT_Q_COUNTER(resp_cqe_error),
4680 INIT_Q_COUNTER(req_cqe_error),
4681 INIT_Q_COUNTER(req_remote_invalid_request),
4682 INIT_Q_COUNTER(req_remote_access_errors),
4683 INIT_Q_COUNTER(resp_remote_access_errors),
4684 INIT_Q_COUNTER(resp_cqe_flush_error),
4685 INIT_Q_COUNTER(req_cqe_flush_error),
4686};
4687
9f876f3d
TB		 4688#define INIT_EXT_PPCNT_COUNTER(_name) \
4689 { .name = #_name, .offset = \
4690 MLX5_BYTE_OFF(ppcnt_reg, \
4691 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4692
4693static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4694 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4695};
4696
e1f24a79 4697static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4698{
aac4492e 4699 int i;
0837e86a 4700
7c16f477 4701 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4702 if (dev->port[i].cnts.set_id)
4703 mlx5_core_dealloc_q_counter(dev->mdev,
4704 dev->port[i].cnts.set_id);
e1f24a79
PP		 4705 kfree(dev->port[i].cnts.names);
4706 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4707 }
4708}
4709
e1f24a79
PP		 4710static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4711 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4712{
4713 u32 num_counters;
4714
4715 num_counters = ARRAY_SIZE(basic_q_cnts);
4716
4717 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4718 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4719
4720 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4721 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4722
4723 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4724 num_counters += ARRAY_SIZE(extended_err_cnts);
4725
e1f24a79 4726 cnts->num_q_counters = num_counters;
7c16f477 4727
e1f24a79
PP		 4728 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4729 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4730 num_counters += ARRAY_SIZE(cong_cnts);
4731 }
9f876f3d
TB		 4732 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4733 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4734 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4735 }
e1f24a79
PP		 4736 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4737 if (!cnts->names)
7c16f477
KH		 4738 return -ENOMEM;
4739
e1f24a79
PP		 4740 cnts->offsets = kcalloc(num_counters,
4741 sizeof(cnts->offsets), GFP_KERNEL);
4742 if (!cnts->offsets)
7c16f477
KH		 4743 goto err_names;
4744
7c16f477
KH		 4745 return 0;
4746
4747err_names:
e1f24a79 4748 kfree(cnts->names);
aac4492e 4749 cnts->names = NULL;
7c16f477
KH		 4750 return -ENOMEM;
4751}
4752
e1f24a79
PP		 4753static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4754 const char **names,
4755 size_t *offsets)
7c16f477
KH		 4756{
4757 int i;
4758 int j = 0;
4759
4760 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4761 names[j] = basic_q_cnts[i].name;
4762 offsets[j] = basic_q_cnts[i].offset;
4763 }
4764
4765 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4766 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4767 names[j] = out_of_seq_q_cnts[i].name;
4768 offsets[j] = out_of_seq_q_cnts[i].offset;
4769 }
4770 }
4771
4772 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4773 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4774 names[j] = retrans_q_cnts[i].name;
4775 offsets[j] = retrans_q_cnts[i].offset;
4776 }
4777 }
e1f24a79 4778
58dcb60a
PP		 4779 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4780 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4781 names[j] = extended_err_cnts[i].name;
4782 offsets[j] = extended_err_cnts[i].offset;
4783 }
4784 }
4785
e1f24a79
PP		 4786 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4787 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4788 names[j] = cong_cnts[i].name;
4789 offsets[j] = cong_cnts[i].offset;
4790 }
4791 }
9f876f3d
TB		 4792
4793 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4794 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
4795 names[j] = ext_ppcnt_cnts[i].name;
4796 offsets[j] = ext_ppcnt_cnts[i].offset;
4797 }
4798 }
0837e86a
MB		 4799}
4800
e1f24a79 4801static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4802{
aac4492e 4803 int err = 0;
0837e86a 4804 int i;
0837e86a
MB		 4805
4806 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4807 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4808 if (err)
4809 goto err_alloc;
4810
4811 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4812 dev->port[i].cnts.offsets);
7c16f477 4813
aac4492e
DJ		 4814 err = mlx5_core_alloc_q_counter(dev->mdev,
4815 &dev->port[i].cnts.set_id);
4816 if (err) {
0837e86a
MB		 4817 mlx5_ib_warn(dev,
4818 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 4819 i + 1, err);
4820 goto err_alloc;
0837e86a 4821 }
aac4492e 4822 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 4823 }
4824
4825 return 0;
4826
aac4492e
DJ		 4827err_alloc:
4828 mlx5_ib_dealloc_counters(dev);
4829 return err;
0837e86a
MB		 4830}
4831
0ad17a8f
MB		 4832static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4833 u8 port_num)
4834{
7c16f477
KH		 4835 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4836 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 4837
4838 /* We support only per port stats */
4839 if (port_num == 0)
4840 return NULL;
4841
e1f24a79
PP		 4842 return rdma_alloc_hw_stats_struct(port->cnts.names,
4843 port->cnts.num_q_counters +
9f876f3d
TB		 4844 port->cnts.num_cong_counters +
4845 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 4846 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4847}
4848
aac4492e 4849static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 4850 struct mlx5_ib_port *port,
4851 struct rdma_hw_stats *stats)
0ad17a8f 4852{
0ad17a8f
MB		 4853 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4854 void *out;
4855 __be32 val;
e1f24a79 4856 int ret, i;
0ad17a8f 4857
1b9a07ee 4858 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 4859 if (!out)
4860 return -ENOMEM;
4861
aac4492e 4862 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 4863 port->cnts.set_id, 0,
0ad17a8f
MB		 4864 out, outlen);
4865 if (ret)
4866 goto free;
4867
e1f24a79
PP		 4868 for (i = 0; i < port->cnts.num_q_counters; i++) {
4869 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 4870 stats->value[i] = (u64)be32_to_cpu(val);
4871 }
7c16f477 4872
0ad17a8f
MB		 4873free:
4874 kvfree(out);
e1f24a79
PP		 4875 return ret;
4876}
4877
9f876f3d
TB		 4878static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
4879 struct mlx5_ib_port *port,
4880 struct rdma_hw_stats *stats)
4881{
4882 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4883 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
4884 int ret, i;
4885 void *out;
4886
4887 out = kvzalloc(sz, GFP_KERNEL);
4888 if (!out)
4889 return -ENOMEM;
4890
4891 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
4892 if (ret)
4893 goto free;
4894
4895 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
4896 stats->value[i + offset] =
4897 be64_to_cpup((__be64 *)(out +
4898 port->cnts.offsets[i + offset]));
4899 }
4900
4901free:
4902 kvfree(out);
4903 return ret;
4904}
4905
e1f24a79
PP		 4906static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4907 struct rdma_hw_stats *stats,
4908 u8 port_num, int index)
4909{
4910 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4911 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 4912 struct mlx5_core_dev *mdev;
e1f24a79 4913 int ret, num_counters;
aac4492e 4914 u8 mdev_port_num;
e1f24a79
PP		 4915
4916 if (!stats)
4917 return -EINVAL;
4918
9f876f3d
TB		 4919 num_counters = port->cnts.num_q_counters +
4920 port->cnts.num_cong_counters +
4921 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 4922
4923 /* q_counters are per IB device, query the master mdev */
4924 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 4925 if (ret)
4926 return ret;
e1f24a79 4927
9f876f3d
TB		 4928 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4929 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
4930 if (ret)
4931 return ret;
4932 }
4933
e1f24a79 4934 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 4935 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4936 &mdev_port_num);
4937 if (!mdev) {
4938 /* If port is not affiliated yet, its in down state
4939 * which doesn't have any counters yet, so it would be
4940 * zero. So no need to read from the HCA.
4941 */
4942 goto done;
4943 }
71a0ff65
MD		 4944 ret = mlx5_lag_query_cong_counters(dev->mdev,
4945 stats->value +
4946 port->cnts.num_q_counters,
4947 port->cnts.num_cong_counters,
4948 port->cnts.offsets +
4949 port->cnts.num_q_counters);
aac4492e
DJ		 4950
4951 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 4952 if (ret)
4953 return ret;
e1f24a79
PP		 4954 }
4955
aac4492e 4956done:
e1f24a79 4957 return num_counters;
0ad17a8f
MB		 4958}
4959
8e959601
NV		 4960static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4961{
4962 return mlx5_rdma_netdev_free(netdev);
4963}
4964
693dfd5a
ES		 4965static struct net_device*
4966mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4967 u8 port_num,
4968 enum rdma_netdev_t type,
4969 const char *name,
4970 unsigned char name_assign_type,
4971 void (*setup)(struct net_device *))
4972{
8e959601
NV		 4973 struct net_device *netdev;
4974 struct rdma_netdev *rn;
4975
693dfd5a
ES		 4976 if (type != RDMA_NETDEV_IPOIB)
4977 return ERR_PTR(-EOPNOTSUPP);
4978
8e959601
NV		 4979 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4980 name, setup);
4981 if (likely(!IS_ERR_OR_NULL(netdev))) {
4982 rn = netdev_priv(netdev);
4983 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4984 }
4985 return netdev;
693dfd5a
ES		 4986}
4987
fe248c3a
MG		 4988static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4989{
4990 if (!dev->delay_drop.dbg)
4991 return;
4992 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4993 kfree(dev->delay_drop.dbg);
4994 dev->delay_drop.dbg = NULL;
4995}
4996
03404e8a
MG		 4997static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4998{
4999 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5000 return;
5001
5002 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5003 delay_drop_debugfs_cleanup(dev);
5004}
5005
5006static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5007 size_t count, loff_t *pos)
5008{
5009 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5010 char lbuf[20];
5011 int len;
5012
5013 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5014 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5015}
5016
5017static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5018 size_t count, loff_t *pos)
5019{
5020 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5021 u32 timeout;
5022 u32 var;
5023
5024 if (kstrtouint_from_user(buf, count, 0, &var))
5025 return -EFAULT;
5026
5027 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5028 1000);
5029 if (timeout != var)
5030 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5031 timeout);
5032
5033 delay_drop->timeout = timeout;
5034
5035 return count;
5036}
5037
5038static const struct file_operations fops_delay_drop_timeout = {
5039 .owner = THIS_MODULE,
5040 .open = simple_open,
5041 .write = delay_drop_timeout_write,
5042 .read = delay_drop_timeout_read,
5043};
5044
5045static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5046{
5047 struct mlx5_ib_dbg_delay_drop *dbg;
5048
5049 if (!mlx5_debugfs_root)
5050 return 0;
5051
5052 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5053 if (!dbg)
5054 return -ENOMEM;
5055
cbafad87
SM		 5056 dev->delay_drop.dbg = dbg;
5057
fe248c3a
MG		 5058 dbg->dir_debugfs =
5059 debugfs_create_dir("delay_drop",
5060 dev->mdev->priv.dbg_root);
5061 if (!dbg->dir_debugfs)
cbafad87 5062 goto out_debugfs;
fe248c3a
MG		 5063
5064 dbg->events_cnt_debugfs =
5065 debugfs_create_atomic_t("num_timeout_events", 0400,
5066 dbg->dir_debugfs,
5067 &dev->delay_drop.events_cnt);
5068 if (!dbg->events_cnt_debugfs)
5069 goto out_debugfs;
5070
5071 dbg->rqs_cnt_debugfs =
5072 debugfs_create_atomic_t("num_rqs", 0400,
5073 dbg->dir_debugfs,
5074 &dev->delay_drop.rqs_cnt);
5075 if (!dbg->rqs_cnt_debugfs)
5076 goto out_debugfs;
5077
5078 dbg->timeout_debugfs =
5079 debugfs_create_file("timeout", 0600,
5080 dbg->dir_debugfs,
5081 &dev->delay_drop,
5082 &fops_delay_drop_timeout);
5083 if (!dbg->timeout_debugfs)
5084 goto out_debugfs;
5085
5086 return 0;
5087
5088out_debugfs:
5089 delay_drop_debugfs_cleanup(dev);
5090 return -ENOMEM;
03404e8a
MG		 5091}
5092
5093static void init_delay_drop(struct mlx5_ib_dev *dev)
5094{
5095 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5096 return;
5097
5098 mutex_init(&dev->delay_drop.lock);
5099 dev->delay_drop.dev = dev;
5100 dev->delay_drop.activate = false;
5101 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5102 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5103 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5104 atomic_set(&dev->delay_drop.events_cnt, 0);
5105
5106 if (delay_drop_debugfs_init(dev))
5107 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5108}
5109
84305d71
LR		 5110static const struct cpumask *
5111mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 5112{
5113 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5114
6082d9c9 5115 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
40b24403
SG		 5116}
5117
32f69e4b
DJ		 5118/* The mlx5_ib_multiport_mutex should be held when calling this function */
5119static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5120 struct mlx5_ib_multiport_info *mpi)
5121{
5122 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5123 struct mlx5_ib_port *port = &ibdev->port[port_num];
5124 int comps;
5125 int err;
5126 int i;
5127
a9e546e7
PP		 5128 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5129
32f69e4b
DJ		 5130 spin_lock(&port->mp.mpi_lock);
5131 if (!mpi->ibdev) {
5132 spin_unlock(&port->mp.mpi_lock);
5133 return;
5134 }
5135 mpi->ibdev = NULL;
5136
5137 spin_unlock(&port->mp.mpi_lock);
5138 mlx5_remove_netdev_notifier(ibdev, port_num);
5139 spin_lock(&port->mp.mpi_lock);
5140
5141 comps = mpi->mdev_refcnt;
5142 if (comps) {
5143 mpi->unaffiliate = true;
5144 init_completion(&mpi->unref_comp);
5145 spin_unlock(&port->mp.mpi_lock);
5146
5147 for (i = 0; i < comps; i++)
5148 wait_for_completion(&mpi->unref_comp);
5149
5150 spin_lock(&port->mp.mpi_lock);
5151 mpi->unaffiliate = false;
5152 }
5153
5154 port->mp.mpi = NULL;
5155
5156 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5157
5158 spin_unlock(&port->mp.mpi_lock);
5159
5160 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5161
5162 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5163 /* Log an error, still needed to cleanup the pointers and add
5164 * it back to the list.
5165 */
5166 if (err)
5167 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5168 port_num + 1);
5169
5170 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5171}
5172
5173/* The mlx5_ib_multiport_mutex should be held when calling this function */
5174static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5175 struct mlx5_ib_multiport_info *mpi)
5176{
5177 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5178 int err;
5179
5180 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5181 if (ibdev->port[port_num].mp.mpi) {
5182 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
5183 port_num + 1);
5184 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5185 return false;
5186 }
5187
5188 ibdev->port[port_num].mp.mpi = mpi;
5189 mpi->ibdev = ibdev;
5190 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5191
5192 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5193 if (err)
5194 goto unbind;
5195
5196 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5197 if (err)
5198 goto unbind;
5199
5200 err = mlx5_add_netdev_notifier(ibdev, port_num);
5201 if (err) {
5202 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5203 port_num + 1);
5204 goto unbind;
5205 }
5206
a9e546e7
PP		 5207 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5208 if (err)
5209 goto unbind;
5210
32f69e4b
DJ		 5211 return true;
5212
5213unbind:
5214 mlx5_ib_unbind_slave_port(ibdev, mpi);
5215 return false;
5216}
5217
5218static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5219{
5220 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5221 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5222 port_num + 1);
5223 struct mlx5_ib_multiport_info *mpi;
5224 int err;
5225 int i;
5226
5227 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5228 return 0;
5229
5230 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5231 &dev->sys_image_guid);
5232 if (err)
5233 return err;
5234
5235 err = mlx5_nic_vport_enable_roce(dev->mdev);
5236 if (err)
5237 return err;
5238
5239 mutex_lock(&mlx5_ib_multiport_mutex);
5240 for (i = 0; i < dev->num_ports; i++) {
5241 bool bound = false;
5242
5243 /* build a stub multiport info struct for the native port. */
5244 if (i == port_num) {
5245 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5246 if (!mpi) {
5247 mutex_unlock(&mlx5_ib_multiport_mutex);
5248 mlx5_nic_vport_disable_roce(dev->mdev);
5249 return -ENOMEM;
5250 }
5251
5252 mpi->is_master = true;
5253 mpi->mdev = dev->mdev;
5254 mpi->sys_image_guid = dev->sys_image_guid;
5255 dev->port[i].mp.mpi = mpi;
5256 mpi->ibdev = dev;
5257 mpi = NULL;
5258 continue;
5259 }
5260
5261 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5262 list) {
5263 if (dev->sys_image_guid == mpi->sys_image_guid &&
5264 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5265 bound = mlx5_ib_bind_slave_port(dev, mpi);
5266 }
5267
5268 if (bound) {
5269 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5270 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5271 list_del(&mpi->list);
5272 break;
5273 }
5274 }
5275 if (!bound) {
5276 get_port_caps(dev, i + 1);
5277 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5278 i + 1);
5279 }
5280 }
5281
5282 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5283 mutex_unlock(&mlx5_ib_multiport_mutex);
5284 return err;
5285}
5286
5287static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5288{
5289 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5290 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5291 port_num + 1);
5292 int i;
5293
5294 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5295 return;
5296
5297 mutex_lock(&mlx5_ib_multiport_mutex);
5298 for (i = 0; i < dev->num_ports; i++) {
5299 if (dev->port[i].mp.mpi) {
5300 /* Destroy the native port stub */
5301 if (i == port_num) {
5302 kfree(dev->port[i].mp.mpi);
5303 dev->port[i].mp.mpi = NULL;
5304 } else {
5305 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5306 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5307 }
5308 }
5309 }
5310
5311 mlx5_ib_dbg(dev, "removing from devlist\n");
5312 list_del(&dev->ib_dev_list);
5313 mutex_unlock(&mlx5_ib_multiport_mutex);
5314
5315 mlx5_nic_vport_disable_roce(dev->mdev);
5316}
5317
9a119cd5
JG		 5318ADD_UVERBS_ATTRIBUTES_SIMPLE(
5319 mlx5_ib_dm,
5320 UVERBS_OBJECT_DM,
5321 UVERBS_METHOD_DM_ALLOC,
5322 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5323 UVERBS_ATTR_TYPE(u64),
83bb4442 5324 UA_MANDATORY),
9a119cd5
JG		 5325 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5326 UVERBS_ATTR_TYPE(u16),
83bb4442 5327 UA_MANDATORY));
9a119cd5
JG		 5328
5329ADD_UVERBS_ATTRIBUTES_SIMPLE(
5330 mlx5_ib_flow_action,
5331 UVERBS_OBJECT_FLOW_ACTION,
5332 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5333 UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5334 UVERBS_ATTR_TYPE(u64),
83bb4442 5335 UA_MANDATORY));
c6475a0b 5336
c59450c4 5337#define NUM_TREES 3
8c84660b
MB		 5338static int populate_specs_root(struct mlx5_ib_dev *dev)
5339{
5340 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
5341 uverbs_default_get_objects()};
5342 size_t num_trees = 1;
5343
c6475a0b
AY		 5344 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
5345 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5346 default_root[num_trees++] = &mlx5_ib_flow_action;
5347
24da0016
AL		 5348 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
5349 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5350 default_root[num_trees++] = &mlx5_ib_dm;
5351
c59450c4
YH		 5352 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5353 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX &&
5354 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5355 default_root[num_trees++] = mlx5_ib_get_devx_tree();
5356
87fc2a62 5357 dev->ib_dev.driver_specs_root =
8c84660b
MB		 5358 uverbs_alloc_spec_tree(num_trees, default_root);
5359
87fc2a62 5360 return PTR_ERR_OR_ZERO(dev->ib_dev.driver_specs_root);
8c84660b
MB		 5361}
5362
5363static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5364{
87fc2a62 5365 uverbs_free_spec_tree(dev->ib_dev.driver_specs_root);
8c84660b
MB		 5366}
5367
1a1e03dc
RS		 5368static int mlx5_ib_read_counters(struct ib_counters *counters,
5369 struct ib_counters_read_attr *read_attr,
5370 struct uverbs_attr_bundle *attrs)
5371{
5372 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5373 struct mlx5_read_counters_attr mread_attr = {};
5374 struct mlx5_ib_flow_counters_desc *desc;
5375 int ret, i;
5376
5377 mutex_lock(&mcounters->mcntrs_mutex);
5378 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5379 ret = -EINVAL;
5380 goto err_bound;
5381 }
5382
5383 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5384 GFP_KERNEL);
5385 if (!mread_attr.out) {
5386 ret = -ENOMEM;
5387 goto err_bound;
5388 }
5389
5390 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5391 mread_attr.flags = read_attr->flags;
5392 ret = mcounters->read_counters(counters->device, &mread_attr);
5393 if (ret)
5394 goto err_read;
5395
5396 /* do the pass over the counters data array to assign according to the
5397 * descriptions and indexing pairs
5398 */
5399 desc = mcounters->counters_data;
5400 for (i = 0; i < mcounters->ncounters; i++)
5401 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5402
5403err_read:
5404 kfree(mread_attr.out);
5405err_bound:
5406 mutex_unlock(&mcounters->mcntrs_mutex);
5407 return ret;
5408}
5409
b29e2a13
RS		 5410static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5411{
5412 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5413
3b3233fb
RS		 5414 counters_clear_description(counters);
5415 if (mcounters->hw_cntrs_hndl)
5416 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5417 mcounters->hw_cntrs_hndl);
5418
b29e2a13
RS		 5419 kfree(mcounters);
5420
5421 return 0;
5422}
5423
5424static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5425 struct uverbs_attr_bundle *attrs)
5426{
5427 struct mlx5_ib_mcounters *mcounters;
5428
5429 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5430 if (!mcounters)
5431 return ERR_PTR(-ENOMEM);
5432
3b3233fb
RS		 5433 mutex_init(&mcounters->mcntrs_mutex);
5434
b29e2a13
RS		 5435 return &mcounters->ibcntrs;
5436}
5437
b5ca15ad 5438void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5439{
32f69e4b 5440 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 5441#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5442 cleanup_srcu_struct(&dev->mr_srcu);
5443#endif
16c1975f
MB		 5444 kfree(dev->port);
5445}
5446
b5ca15ad 5447int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5448{
5449 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 5450 const char *name;
e126ba97 5451 int err;
32f69e4b 5452 int i;
e126ba97 5453
508562d6 5454 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5455 GFP_KERNEL);
5456 if (!dev->port)
16c1975f 5457 return -ENOMEM;
0837e86a 5458
32f69e4b
DJ		 5459 for (i = 0; i < dev->num_ports; i++) {
5460 spin_lock_init(&dev->port[i].mp.mpi_lock);
5461 rwlock_init(&dev->roce[i].netdev_lock);
5462 }
5463
5464 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5465 if (err)
0837e86a 5466 goto err_free_port;
e126ba97 5467
32f69e4b 5468 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5469 for (i = 1; i <= dev->num_ports; i++) {
5470 err = get_port_caps(dev, i);
5471 if (err)
5472 break;
5473 }
5474 } else {
5475 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5476 }
5477 if (err)
5478 goto err_mp;
5479
1b5daf11
MD		 5480 if (mlx5_use_mad_ifc(dev))
5481 get_ext_port_caps(dev);
e126ba97 5482
4babcf97
AH		 5483 if (!mlx5_lag_is_active(mdev))
5484 name = "mlx5_%d";
5485 else
5486 name = "mlx5_bond_%d";
5487
5488 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 5489 dev->ib_dev.owner = THIS_MODULE;
5490 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5491 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5492 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 5493 dev->ib_dev.num_comp_vectors =
5494 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 5495 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5496
3cc297db
MB		 5497 mutex_init(&dev->cap_mask_mutex);
5498 INIT_LIST_HEAD(&dev->qp_list);
5499 spin_lock_init(&dev->reset_flow_resource_lock);
5500
24da0016
AL		 5501 spin_lock_init(&dev->memic.memic_lock);
5502 dev->memic.dev = mdev;
5503
3cc297db
MB		 5504#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5505 err = init_srcu_struct(&dev->mr_srcu);
5506 if (err)
5507 goto err_free_port;
5508#endif
5509
16c1975f 5510 return 0;
32f69e4b
DJ		 5511err_mp:
5512 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5513
5514err_free_port:
5515 kfree(dev->port);
5516
5517 return -ENOMEM;
5518}
5519
9a4ca38d
MB		 5520static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5521{
5522 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5523
5524 if (!dev->flow_db)
5525 return -ENOMEM;
5526
5527 mutex_init(&dev->flow_db->lock);
5528
5529 return 0;
5530}
5531
b5ca15ad
MB		 5532int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5533{
5534 struct mlx5_ib_dev *nic_dev;
5535
5536 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5537
5538 if (!nic_dev)
5539 return -EINVAL;
5540
5541 dev->flow_db = nic_dev->flow_db;
5542
5543 return 0;
5544}
5545
9a4ca38d
MB		 5546static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5547{
5548 kfree(dev->flow_db);
5549}
5550
b5ca15ad 5551int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5552{
5553 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5554 int err;
5555
e126ba97
EC		 5556 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5557 dev->ib_dev.uverbs_cmd_mask =
5558 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5559 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5560 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5561 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5562 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5563 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5564 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5565 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5566 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5567 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5568 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5569 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5570 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5571 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5572 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5573 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5574 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5575 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5576 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5577 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5578 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5579 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5580 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5581 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5582 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5583 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5584 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5585 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5586 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5587 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5588 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5589 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5590
5591 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5592 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5593 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5594 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5595 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5596 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5597 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5598 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5599 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5600 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5601 dev->ib_dev.mmap = mlx5_ib_mmap;
5602 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5603 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5604 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5605 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5606 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5607 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5608 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5609 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5610 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5611 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5612 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5613 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5614 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5615 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
d0e84c0a
YH		 5616 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5617 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
e126ba97
EC		 5618 dev->ib_dev.post_send = mlx5_ib_post_send;
5619 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5620 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5621 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5622 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5623 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5624 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5625 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5626 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5627 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5628 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5629 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5630 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5631 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5632 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5633 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5634 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5635 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5636 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5637 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5638 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5639 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5640
eff901d3
EC		 5641 if (mlx5_core_is_pf(mdev)) {
5642 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5643 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5644 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5645 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5646 }
e126ba97 5647
7c2344c3
MG		 5648 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5649
6e8484c5
MG		 5650 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5651
d2370e0a
MB		 5652 if (MLX5_CAP_GEN(mdev, imaicl)) {
5653 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5654 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5655 dev->ib_dev.uverbs_cmd_mask |=
5656 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5657 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5658 }
5659
938fe83c 5660 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5661 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5662 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5663 dev->ib_dev.uverbs_cmd_mask |=
5664 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5665 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5666 }
5667
24da0016
AL		 5668 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5669 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5670 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
6c29f57e 5671 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
24da0016
AL		 5672 }
5673
81e30880
YH		 5674 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5675 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5676 dev->ib_dev.uverbs_ex_cmd_mask |=
5677 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5678 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5679 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5680 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5681 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5682 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
b29e2a13
RS		 5683 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5684 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
1a1e03dc 5685 dev->ib_dev.read_counters = mlx5_ib_read_counters;
81e30880 5686
e126ba97
EC		 5687 err = init_node_data(dev);
5688 if (err)
16c1975f 5689 return err;
e126ba97 5690
c8b89924 5691 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5692 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5693 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 5694 mutex_init(&dev->lb_mutex);
5695
16c1975f
MB		 5696 return 0;
5697}
5698
8e6efa3a
MB		 5699static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5700{
5701 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5702 dev->ib_dev.query_port = mlx5_ib_query_port;
5703
5704 return 0;
5705}
5706
b5ca15ad 5707int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5708{
5709 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5710 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5711
5712 return 0;
5713}
5714
e3f1ed1f 5715static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 5716{
e3f1ed1f 5717 u8 port_num;
8e6efa3a
MB		 5718 int i;
5719
5720 for (i = 0; i < dev->num_ports; i++) {
5721 dev->roce[i].dev = dev;
5722 dev->roce[i].native_port_num = i + 1;
5723 dev->roce[i].last_port_state = IB_PORT_DOWN;
5724 }
5725
5726 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5727 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5728 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5729 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5730 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5731 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5732
5733 dev->ib_dev.uverbs_ex_cmd_mask |=
5734 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5735 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5736 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5737 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5738 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5739
e3f1ed1f
LR		 5740 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5741
8e6efa3a
MB		 5742 return mlx5_add_netdev_notifier(dev, port_num);
5743}
5744
5745static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5746{
5747 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5748
5749 mlx5_remove_netdev_notifier(dev, port_num);
5750}
5751
5752int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5753{
5754 struct mlx5_core_dev *mdev = dev->mdev;
5755 enum rdma_link_layer ll;
5756 int port_type_cap;
5757 int err = 0;
8e6efa3a 5758
8e6efa3a
MB		 5759 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5760 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5761
5762 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 5763 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5764
5765 return err;
5766}
5767
5768void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5769{
5770 mlx5_ib_stage_common_roce_cleanup(dev);
5771}
5772
16c1975f
MB		 5773static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5774{
5775 struct mlx5_core_dev *mdev = dev->mdev;
5776 enum rdma_link_layer ll;
5777 int port_type_cap;
5778 int err;
5779
5780 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5781 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5782
fc24fc5e 5783 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 5784 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5785 if (err)
5786 return err;
7fd8aefb 5787
e3f1ed1f 5788 err = mlx5_enable_eth(dev);
fc24fc5e 5789 if (err)
8e6efa3a 5790 goto cleanup;
fc24fc5e
AS		 5791 }
5792
16c1975f 5793 return 0;
8e6efa3a
MB		 5794cleanup:
5795 mlx5_ib_stage_common_roce_cleanup(dev);
5796
5797 return err;
16c1975f 5798}
e126ba97 5799
16c1975f
MB		 5800static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5801{
5802 struct mlx5_core_dev *mdev = dev->mdev;
5803 enum rdma_link_layer ll;
5804 int port_type_cap;
e126ba97 5805
16c1975f
MB		 5806 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5807 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5808
5809 if (ll == IB_LINK_LAYER_ETHERNET) {
5810 mlx5_disable_eth(dev);
8e6efa3a 5811 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 5812 }
16c1975f 5813}
6aec21f6 5814
b5ca15ad 5815int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5816{
5817 return create_dev_resources(&dev->devr);
5818}
5819
b5ca15ad 5820void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5821{
5822 destroy_dev_resources(&dev->devr);
5823}
5824
5825static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5826{
07321b3c
MB		 5827 mlx5_ib_internal_fill_odp_caps(dev);
5828
16c1975f
MB		 5829 return mlx5_ib_odp_init_one(dev);
5830}
4a2da0b8 5831
b5ca15ad 5832int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 5833{
5e1e7612
MB		 5834 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5835 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
5836 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
5837
5838 return mlx5_ib_alloc_counters(dev);
5839 }
16c1975f
MB		 5840
5841 return 0;
5842}
5843
b5ca15ad 5844void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5845{
5846 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5847 mlx5_ib_dealloc_counters(dev);
5848}
5849
5850static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5851{
a9e546e7
PP		 5852 return mlx5_ib_init_cong_debugfs(dev,
5853 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5854}
5855
5856static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5857{
a9e546e7
PP		 5858 mlx5_ib_cleanup_cong_debugfs(dev,
5859 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5860}
5861
5862static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5863{
5fe9dec0 5864 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 5865 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 5866}
5867
5868static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5869{
5870 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5871}
5872
b5ca15ad 5873int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5874{
5875 int err;
5fe9dec0
EC		 5876
5877 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5878 if (err)
16c1975f 5879 return err;
5fe9dec0
EC		 5880
5881 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5882 if (err)
16c1975f 5883 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 5884
16c1975f
MB		 5885 return err;
5886}
0837e86a 5887
b5ca15ad 5888void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5889{
5890 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5891 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5892}
e126ba97 5893
8c84660b
MB		 5894static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5895{
5896 return populate_specs_root(dev);
5897}
5898
b5ca15ad 5899int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5900{
5901 return ib_register_device(&dev->ib_dev, NULL);
5902}
5903
8c84660b
MB		 5904static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5905{
5906 depopulate_specs_root(dev);
5907}
5908
03fe2deb 5909void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5910{
42cea83f 5911 destroy_umrc_res(dev);
16c1975f
MB		 5912}
5913
03fe2deb 5914void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5915{
42cea83f 5916 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 5917}
5918
03fe2deb 5919int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 5920{
42cea83f 5921 return create_umr_res(dev);
16c1975f
MB		 5922}
5923
5924static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5925{
03404e8a
MG		 5926 init_delay_drop(dev);
5927
16c1975f
MB		 5928 return 0;
5929}
5930
5931static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5932{
5933 cancel_delay_drop(dev);
5934}
5935
b5ca15ad 5936int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5937{
5938 int err;
5939 int i;
5940
e126ba97 5941 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 5942 err = device_create_file(&dev->ib_dev.dev,
5943 mlx5_class_attributes[i]);
5944 if (err)
16c1975f 5945 return err;
e126ba97
EC		 5946 }
5947
16c1975f
MB		 5948 return 0;
5949}
5950
fc385b7a
MB		 5951static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5952{
5953 mlx5_ib_register_vport_reps(dev);
5954
5955 return 0;
5956}
5957
5958static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5959{
5960 mlx5_ib_unregister_vport_reps(dev);
5961}
5962
b5ca15ad
MB		 5963void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5964 const struct mlx5_ib_profile *profile,
5965 int stage)
16c1975f
MB		 5966{
5967 /* Number of stages to cleanup */
5968 while (stage) {
5969 stage--;
5970 if (profile->stage[stage].cleanup)
5971 profile->stage[stage].cleanup(dev);
5972 }
e126ba97 5973
16c1975f
MB		 5974 ib_dealloc_device((struct ib_device *)dev);
5975}
e126ba97 5976
b5ca15ad
MB		 5977void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5978 const struct mlx5_ib_profile *profile)
16c1975f 5979{
16c1975f
MB		 5980 int err;
5981 int i;
e126ba97 5982
16c1975f 5983 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 5984
16c1975f
MB		 5985 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5986 if (profile->stage[i].init) {
5987 err = profile->stage[i].init(dev);
5988 if (err)
5989 goto err_out;
5990 }
5991 }
0837e86a 5992
16c1975f
MB		 5993 dev->profile = profile;
5994 dev->ib_active = true;
6aec21f6 5995
16c1975f 5996 return dev;
e126ba97 5997
16c1975f
MB		 5998err_out:
5999 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6000
16c1975f
MB		 6001 return NULL;
6002}
0837e86a 6003
16c1975f
MB		 6004static const struct mlx5_ib_profile pf_profile = {
6005 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6006 mlx5_ib_stage_init_init,
6007 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6008 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6009 mlx5_ib_stage_flow_db_init,
6010 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6011 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6012 mlx5_ib_stage_caps_init,
6013 NULL),
8e6efa3a
MB		 6014 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6015 mlx5_ib_stage_non_default_cb,
6016 NULL),
16c1975f
MB		 6017 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6018 mlx5_ib_stage_roce_init,
6019 mlx5_ib_stage_roce_cleanup),
6020 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6021 mlx5_ib_stage_dev_res_init,
6022 mlx5_ib_stage_dev_res_cleanup),
6023 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6024 mlx5_ib_stage_odp_init,
3cc297db 6025 NULL),
16c1975f
MB		 6026 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6027 mlx5_ib_stage_counters_init,
6028 mlx5_ib_stage_counters_cleanup),
6029 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6030 mlx5_ib_stage_cong_debugfs_init,
6031 mlx5_ib_stage_cong_debugfs_cleanup),
6032 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6033 mlx5_ib_stage_uar_init,
6034 mlx5_ib_stage_uar_cleanup),
6035 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6036 mlx5_ib_stage_bfrag_init,
6037 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6038 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6039 NULL,
6040 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6041 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6042 mlx5_ib_stage_populate_specs,
6043 mlx5_ib_stage_depopulate_specs),
16c1975f
MB		 6044 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6045 mlx5_ib_stage_ib_reg_init,
6046 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6047 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6048 mlx5_ib_stage_post_ib_reg_umr_init,
6049 NULL),
16c1975f
MB		 6050 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6051 mlx5_ib_stage_delay_drop_init,
6052 mlx5_ib_stage_delay_drop_cleanup),
6053 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6054 mlx5_ib_stage_class_attr_init,
6055 NULL),
16c1975f 6056};
e126ba97 6057
b5ca15ad
MB		 6058static const struct mlx5_ib_profile nic_rep_profile = {
6059 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6060 mlx5_ib_stage_init_init,
6061 mlx5_ib_stage_init_cleanup),
6062 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6063 mlx5_ib_stage_flow_db_init,
6064 mlx5_ib_stage_flow_db_cleanup),
6065 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6066 mlx5_ib_stage_caps_init,
6067 NULL),
6068 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6069 mlx5_ib_stage_rep_non_default_cb,
6070 NULL),
6071 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6072 mlx5_ib_stage_rep_roce_init,
6073 mlx5_ib_stage_rep_roce_cleanup),
6074 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6075 mlx5_ib_stage_dev_res_init,
6076 mlx5_ib_stage_dev_res_cleanup),
6077 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6078 mlx5_ib_stage_counters_init,
6079 mlx5_ib_stage_counters_cleanup),
6080 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6081 mlx5_ib_stage_uar_init,
6082 mlx5_ib_stage_uar_cleanup),
6083 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6084 mlx5_ib_stage_bfrag_init,
6085 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6086 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6087 NULL,
6088 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6089 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6090 mlx5_ib_stage_populate_specs,
6091 mlx5_ib_stage_depopulate_specs),
b5ca15ad
MB		 6092 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6093 mlx5_ib_stage_ib_reg_init,
6094 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6095 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6096 mlx5_ib_stage_post_ib_reg_umr_init,
6097 NULL),
b5ca15ad
MB		 6098 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6099 mlx5_ib_stage_class_attr_init,
6100 NULL),
6101 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6102 mlx5_ib_stage_rep_reg_init,
6103 mlx5_ib_stage_rep_reg_cleanup),
6104};
6105
e3f1ed1f 6106static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6107{
6108 struct mlx5_ib_multiport_info *mpi;
6109 struct mlx5_ib_dev *dev;
6110 bool bound = false;
6111 int err;
6112
6113 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6114 if (!mpi)
6115 return NULL;
6116
6117 mpi->mdev = mdev;
6118
6119 err = mlx5_query_nic_vport_system_image_guid(mdev,
6120 &mpi->sys_image_guid);
6121 if (err) {
6122 kfree(mpi);
6123 return NULL;
6124 }
6125
6126 mutex_lock(&mlx5_ib_multiport_mutex);
6127 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6128 if (dev->sys_image_guid == mpi->sys_image_guid)
6129 bound = mlx5_ib_bind_slave_port(dev, mpi);
6130
6131 if (bound) {
6132 rdma_roce_rescan_device(&dev->ib_dev);
6133 break;
6134 }
6135 }
6136
6137 if (!bound) {
6138 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6139 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6140 }
6141 mutex_unlock(&mlx5_ib_multiport_mutex);
6142
6143 return mpi;
6144}
6145
16c1975f
MB		 6146static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6147{
32f69e4b 6148 enum rdma_link_layer ll;
b5ca15ad 6149 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 6150 int port_type_cap;
6151
b5ca15ad
MB		 6152 printk_once(KERN_INFO "%s", mlx5_version);
6153
32f69e4b
DJ		 6154 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6155 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6156
e3f1ed1f
LR		 6157 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6158 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6159
b5ca15ad
MB		 6160 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6161 if (!dev)
6162 return NULL;
6163
6164 dev->mdev = mdev;
6165 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6166 MLX5_CAP_GEN(mdev, num_vhca_ports));
6167
6168 if (MLX5_VPORT_MANAGER(mdev) &&
6169 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6170 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6171
6172 return __mlx5_ib_add(dev, &nic_rep_profile);
6173 }
6174
6175 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6176}
6177
9603b61d 6178static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6179{
32f69e4b
DJ		 6180 struct mlx5_ib_multiport_info *mpi;
6181 struct mlx5_ib_dev *dev;
6182
6183 if (mlx5_core_is_mp_slave(mdev)) {
6184 mpi = context;
6185 mutex_lock(&mlx5_ib_multiport_mutex);
6186 if (mpi->ibdev)
6187 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6188 list_del(&mpi->list);
6189 mutex_unlock(&mlx5_ib_multiport_mutex);
6190 return;
6191 }
6aec21f6 6192
32f69e4b 6193 dev = context;
16c1975f 6194 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6195}
6196
9603b61d
JM		 6197static struct mlx5_interface mlx5_ib_interface = {
6198 .add = mlx5_ib_add,
6199 .remove = mlx5_ib_remove,
6200 .event = mlx5_ib_event,
d9aaed83
AK		 6201#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6202 .pfault = mlx5_ib_pfault,
6203#endif
64613d94 6204 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6205};
6206
c44ef998
IL		 6207unsigned long mlx5_ib_get_xlt_emergency_page(void)
6208{
6209 mutex_lock(&xlt_emergency_page_mutex);
6210 return xlt_emergency_page;
6211}
6212
6213void mlx5_ib_put_xlt_emergency_page(void)
6214{
6215 mutex_unlock(&xlt_emergency_page_mutex);
6216}
6217
e126ba97
EC		 6218static int __init mlx5_ib_init(void)
6219{
6aec21f6
HE		 6220 int err;
6221
c44ef998
IL		 6222 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6223 if (!xlt_emergency_page)
6224 return -ENOMEM;
6225
6226 mutex_init(&xlt_emergency_page_mutex);
6227
d69a24e0 6228 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6229 if (!mlx5_ib_event_wq) {
6230 free_page(xlt_emergency_page);
d69a24e0 6231 return -ENOMEM;
c44ef998 6232 }
d69a24e0 6233
81713d37 6234 mlx5_ib_odp_init();
9603b61d 6235
6aec21f6 6236 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6237
6aec21f6 6238 return err;
e126ba97
EC		 6239}
6240
6241static void __exit mlx5_ib_cleanup(void)
6242{
9603b61d 6243 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6244 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6245 mutex_destroy(&xlt_emergency_page_mutex);
6246 free_page(xlt_emergency_page);
e126ba97
EC		 6247}
6248
6249module_init(mlx5_ib_init);
6250module_exit(mlx5_ib_cleanup);
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