]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/infiniband/hw/mlx5/main.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RDMA/core: Document QP @event_handler function
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
7c2344c3 55#include <linux/list.h>
e126ba97
EC		 56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
038d2ef8
MG		 58#include <linux/in.h>
59#include <linux/etherdevice.h>
e126ba97 60#include "mlx5_ib.h"
fc385b7a 61#include "ib_rep.h"
e1f24a79 62#include "cmd.h"
3346c487 63#include <linux/mlx5/fs_helpers.h>
c6475a0b 64#include <linux/mlx5/accel.h>
8c84660b 65#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 71
72#define DRIVER_NAME "mlx5_ib"
b359911d 73#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
e126ba97 78
e126ba97
EC		 79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 81 DRIVER_VERSION "\n";
e126ba97 82
d69a24e0
DJ		 83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
da7525d2
EBE		 91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
d69a24e0 95static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
c44ef998
IL		 103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
32f69e4b
DJ		 109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
1b5daf11 119static enum rdma_link_layer
ebd61f68 120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 121{
ebd61f68 122 switch (port_type_cap) {
1b5daf11
MD		 123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
ebd61f68
AS		 132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
fd65f1b8
MS		 141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
8e6efa3a 149 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
fc24fc5e
AS		 155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
7fd8aefb 158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
32f69e4b
DJ		 165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
fc24fc5e 168
5ec8c83e
AH		 169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
7fd8aefb 172 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 181 NULL : ndev;
84a6a7a9 182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
bcf87f1d
MB		 183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
7fd8aefb 186 write_unlock(&roce->netdev_lock);
5ec8c83e 187 break;
fc24fc5e 188
fd65f1b8 189 case NETDEV_CHANGE:
5ec8c83e 190 case NETDEV_UP:
88621dfe 191 case NETDEV_DOWN: {
7fd8aefb 192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
7fd8aefb 200 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 201 && ibdev->ib_active) {
626bc02d 202 struct ib_event ibev = { };
fd65f1b8 203 enum ib_port_state port_state;
5ec8c83e 204
7fd8aefb
DJ		 205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
fd65f1b8 208
7fd8aefb
DJ		 209 if (roce->last_port_state == port_state)
210 goto done;
fd65f1b8 211
7fd8aefb 212 roce->last_port_state = port_state;
5ec8c83e 213 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
7fd8aefb 219 goto done;
fd65f1b8 220
7fd8aefb 221 ibev.element.port_num = port_num;
5ec8c83e
AH		 222 ib_dispatch_event(&ibev);
223 }
224 break;
88621dfe 225 }
fc24fc5e 226
5ec8c83e
AH		 227 default:
228 break;
229 }
7fd8aefb 230done:
32f69e4b 231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
32f69e4b
DJ		 240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
fc24fc5e 245
32f69e4b 246 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 247 if (ndev)
32f69e4b 248 goto out;
88621dfe 249
fc24fc5e
AS		 250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
7fd8aefb
DJ		 252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 254 if (ndev)
255 dev_hold(ndev);
7fd8aefb 256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 257
32f69e4b
DJ		 258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 260 return ndev;
261}
262
32f69e4b
DJ		 263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
210b1f78
MB		 273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
32f69e4b
DJ		 280 if (native_port_num)
281 *native_port_num = 1;
282
32f69e4b
DJ		 283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
f1b65df5
NO		 326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
095b0927
IT		 384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
3f89a643
AS		 386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 388 struct mlx5_core_dev *mdev;
88621dfe 389 struct net_device *ndev, *upper;
3f89a643 390 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 391 bool put_mdev = true;
c876a1b7 392 u16 qkey_viol_cntr;
f1b65df5 393 u32 eth_prot_oper;
b3cbd6f0 394 u8 mdev_port_num;
095b0927 395 int err;
3f89a643 396
b3cbd6f0
DJ		 397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
f1b65df5
NO		 408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
50f22fd8 410 */
b3cbd6f0
DJ		 411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
095b0927 413 if (err)
b3cbd6f0 414 goto out;
f1b65df5 415
7672ed33
HL		 416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
f1b65df5
NO		 419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
3f89a643 421
2f944c0f
JG		 422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->ip_gids = true;
3f89a643
AS		 424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
b3cbd6f0 433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 434 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 435
b3cbd6f0
DJ		 436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
3f89a643
AS		 440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
b3cbd6f0 442 goto out;
3f89a643 443
88621dfe
AH		 444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
3f89a643
AS		 455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
3f89a643
AS		 469}
470
095b0927
IT		 471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
3cca2606 474{
095b0927
IT		 475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
3cca2606
AS		 490 }
491
095b0927 492 switch (gid_type) {
3cca2606 493 case IB_GID_TYPE_IB:
095b0927 494 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 502 break;
503
504 default:
095b0927 505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 506 }
507
095b0927
IT		 508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 510 vlan_id, port_num);
3cca2606
AS		 511}
512
f4df9a7c 513static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 514 __always_unused void **context)
515{
414448d2 516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 517 attr->index, &attr->gid, attr);
3cca2606
AS		 518}
519
414448d2
PP		 520static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
3cca2606 522{
414448d2
PP		 523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
3cca2606
AS		 525}
526
47ec3866
PP		 527__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
2811ba51 529{
47ec3866 530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534}
535
1b5daf11
MD		 536static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537{
7fae6655
NO		 538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
1b5daf11
MD		 541}
542
543enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547};
548
549static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550{
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
ebd61f68 554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559}
560
da7525d2 561static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 562 u8 atomic_size_qp,
da7525d2
EBE		 563 struct ib_device_attr *props)
564{
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 567 u8 atomic_req_8B_endianness_mode =
bd10838a 568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581}
582
776a3906
MS		 583static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585{
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589}
590
591static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600{
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605}
1b5daf11
MD		 606static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608{
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
1b5daf11
MD		 626
627 default:
628 return -EINVAL;
629 }
3f89a643
AS		 630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
1b5daf11
MD		 636}
637
638static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640{
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657}
658
659static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661{
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675}
676
677static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679{
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
1b5daf11
MD		 694
695 default:
696 return -EINVAL;
697 }
3f89a643
AS		 698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
1b5daf11
MD		 703}
704
705struct mlx5_reg_node_desc {
bd99fdea 706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 707};
708
709static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710{
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721}
722
e126ba97 723static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
e126ba97
EC		 726{
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 728 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 729 int err = -ENOMEM;
288c01b7 730 int max_sq_desc;
e126ba97
EC		 731 int max_rq_sg;
732 int max_sq_sg;
e0238a6a 733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 734 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
e126ba97 738
402ca536
BW		 739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 746 return -EINVAL;
747
1b5daf11
MD		 748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
e126ba97 753
1b5daf11 754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 755 if (err)
1b5daf11 756 return err;
e126ba97 757
1b5daf11
MD		 758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
e126ba97 761
9603b61d
JM		 762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
e126ba97
EC		 765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 768 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 769
770 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 772 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 774 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 776 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 777 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 784 }
e126ba97 785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 786 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
938fe83c 795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 797
85c7c014 798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
88115fe7 801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 808
402ca536
BW		 809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
31f69a82
YH		 818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
2d93fc85
MB		 832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 843 }
844
f0313965
ES		 845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
03404e8a 850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
03404e8a
MG		 853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
1d54f890
YH		 855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
cff5a0f3 859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
e8161334 862 /* Legacy bit to support old userspace libraries */
cff5a0f3 863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
cff5a0f3 866
24da0016
AL		 867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
da6d6ba3
MG		 872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
b1383aa6
NO		 875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
1b5daf11
MD		 878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 880
881 props->max_mr_size = ~0ull;
e0238a6a 882 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
986ef95e 893 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 904 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 907 get_atomic_caps_qp(dev, props);
81bea28f 908 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 914 props->max_ah = INT_MAX;
7c60bcbb
MB		 915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 917
8cdd312c 918#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 919 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922#endif
923
051f2630
LR		 924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
eff901d3
EC		 927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
31f69a82 930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 931 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
eb761894 941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
eb761894 944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
eb761894 947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 949 }
950
87ab3f52
YC		 951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
7e43a2a5 958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 959 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 973 }
7e43a2a5
BW		 974 }
975
85c7c014
DJ		 976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
d949167d
BW		 978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
9f885201
LR		 994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
795b609c
BW		 996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
050da902
BW		 999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
9f885201
LR		 1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
de57f2ad
GL		 1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
7a0c8f42 1010
de57f2ad
GL		 1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1017 }
9f885201 1018
96dc3fc5
NO		 1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
85c7c014
DJ		 1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
b4f34597
NO		 1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
f95ef6cb
MG		 1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1077 }
1078
402ca536
BW		 1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1b5daf11 1086 return 0;
e126ba97
EC		 1087}
1088
1b5daf11
MD		 1089enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095};
1096
1097static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
e126ba97
EC		 1099{
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1101 int err = 0;
1102
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1107 (int)active_width);
1108 err = -EINVAL;
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1115 } else {
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1117 (int)active_width);
1118 err = -EINVAL;
e126ba97
EC		 1119 }
1120
1b5daf11
MD		 1121 return err;
1122}
e126ba97 1123
1b5daf11
MD		 1124static int mlx5_mtu_to_ib_mtu(int mtu)
1125{
1126 switch (mtu) {
1127 case 256: return 1;
1128 case 512: return 2;
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1132 default:
1133 pr_warn("invalid mtu\n");
1134 return -1;
e126ba97 1135 }
1b5daf11 1136}
e126ba97 1137
1b5daf11
MD		 1138enum ib_max_vl_num {
1139 __IB_MAX_VL_0 = 1,
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1144};
e126ba97 1145
1b5daf11
MD		 1146enum mlx5_vl_hw_cap {
1147 MLX5_VL_HW_0 = 1,
1148 MLX5_VL_HW_0_1 = 2,
1149 MLX5_VL_HW_0_2 = 3,
1150 MLX5_VL_HW_0_3 = 4,
1151 MLX5_VL_HW_0_4 = 5,
1152 MLX5_VL_HW_0_5 = 6,
1153 MLX5_VL_HW_0_6 = 7,
1154 MLX5_VL_HW_0_7 = 8,
1155 MLX5_VL_HW_0_14 = 15
1156};
e126ba97 1157
1b5daf11
MD		 1158static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1159 u8 *max_vl_num)
1160{
1161 switch (vl_hw_cap) {
1162 case MLX5_VL_HW_0:
1163 *max_vl_num = __IB_MAX_VL_0;
1164 break;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1167 break;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1170 break;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1173 break;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1176 break;
e126ba97 1177
1b5daf11
MD		 1178 default:
1179 return -EINVAL;
e126ba97 1180 }
e126ba97 1181
1b5daf11 1182 return 0;
e126ba97
EC		 1183}
1184
1b5daf11
MD		 1185static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
e126ba97 1187{
1b5daf11
MD		 1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1191 u16 max_mtu;
1192 u16 oper_mtu;
1b5daf11
MD		 1193 int err;
1194 u8 ib_link_width_oper;
1195 u8 vl_hw_cap;
e126ba97 1196
1b5daf11
MD		 1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1198 if (!rep) {
1199 err = -ENOMEM;
e126ba97 1200 goto out;
e126ba97 1201 }
e126ba97 1202
c4550c63 1203 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1204
1b5daf11 1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1206 if (err)
1207 goto out;
1208
1b5daf11
MD		 1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
e126ba97 1223
1b5daf11
MD		 1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1225 if (err)
e126ba97 1226 goto out;
e126ba97 1227
1b5daf11
MD		 1228 err = translate_active_width(ibdev, ib_link_width_oper,
1229 &props->active_width);
1230 if (err)
1231 goto out;
d5beb7f2 1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1233 if (err)
1234 goto out;
1235
facc9699 1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1237
1b5daf11 1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1239
facc9699 1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1241
1b5daf11 1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1243
1b5daf11
MD		 1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1245 if (err)
1246 goto out;
e126ba97 1247
1b5daf11
MD		 1248 err = translate_max_vl_num(ibdev, vl_hw_cap,
1249 &props->max_vl_num);
e126ba97 1250out:
1b5daf11 1251 kfree(rep);
e126ba97
EC		 1252 return err;
1253}
1254
1b5daf11
MD		 1255int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1256 struct ib_port_attr *props)
e126ba97 1257{
095b0927
IT		 1258 unsigned int count;
1259 int ret;
1260
1b5daf11
MD		 1261 switch (mlx5_get_vport_access_method(ibdev)) {
1262 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1264 break;
e126ba97 1265
1b5daf11 1266 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1267 ret = mlx5_query_hca_port(ibdev, port, props);
1268 break;
e126ba97 1269
3f89a643 1270 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1271 ret = mlx5_query_port_roce(ibdev, port, props);
1272 break;
3f89a643 1273
1b5daf11 1274 default:
095b0927
IT		 1275 ret = -EINVAL;
1276 }
1277
1278 if (!ret && props) {
b3cbd6f0
DJ		 1279 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1280 struct mlx5_core_dev *mdev;
1281 bool put_mdev = true;
1282
1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1284 if (!mdev) {
1285 /* If the port isn't affiliated yet query the master.
1286 * The master and slave will have the same values.
1287 */
1288 mdev = dev->mdev;
1289 port = 1;
1290 put_mdev = false;
1291 }
1292 count = mlx5_core_reserved_gids_count(mdev);
1293 if (put_mdev)
1294 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1295 props->gid_tbl_len -= count;
1b5daf11 1296 }
095b0927 1297 return ret;
1b5daf11 1298}
e126ba97 1299
8e6efa3a
MB		 1300static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1301 struct ib_port_attr *props)
1302{
1303 int ret;
1304
1305 /* Only link layer == ethernet is valid for representors */
1306 ret = mlx5_query_port_roce(ibdev, port, props);
1307 if (ret || !props)
1308 return ret;
1309
1310 /* We don't support GIDS */
1311 props->gid_tbl_len = 0;
1312
1313 return ret;
1314}
1315
1b5daf11
MD		 1316static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1317 union ib_gid *gid)
1318{
1319 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1320 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1321
1b5daf11
MD		 1322 switch (mlx5_get_vport_access_method(ibdev)) {
1323 case MLX5_VPORT_ACCESS_METHOD_MAD:
1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1325
1b5daf11
MD		 1326 case MLX5_VPORT_ACCESS_METHOD_HCA:
1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1328
1329 default:
1330 return -EINVAL;
1331 }
e126ba97 1332
e126ba97
EC		 1333}
1334
b3cbd6f0
DJ		 1335static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1336 u16 index, u16 *pkey)
1b5daf11
MD		 1337{
1338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1339 struct mlx5_core_dev *mdev;
1340 bool put_mdev = true;
1341 u8 mdev_port_num;
1342 int err;
1b5daf11 1343
b3cbd6f0
DJ		 1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1345 if (!mdev) {
1346 /* The port isn't affiliated yet, get the PKey from the master
1347 * port. For RoCE the PKey tables will be the same.
1348 */
1349 put_mdev = false;
1350 mdev = dev->mdev;
1351 mdev_port_num = 1;
1352 }
1353
1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1355 index, pkey);
1356 if (put_mdev)
1357 mlx5_ib_put_native_port_mdev(dev, port);
1358
1359 return err;
1360}
1361
1362static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1363 u16 *pkey)
1364{
1b5daf11
MD		 1365 switch (mlx5_get_vport_access_method(ibdev)) {
1366 case MLX5_VPORT_ACCESS_METHOD_MAD:
1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1368
1369 case MLX5_VPORT_ACCESS_METHOD_HCA:
1370 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1372 default:
1373 return -EINVAL;
1374 }
1375}
e126ba97
EC		 1376
1377static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1378 struct ib_device_modify *props)
1379{
1380 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1381 struct mlx5_reg_node_desc in;
1382 struct mlx5_reg_node_desc out;
1383 int err;
1384
1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1386 return -EOPNOTSUPP;
1387
1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1389 return 0;
1390
1391 /*
1392 * If possible, pass node desc to FW, so it can generate
1393 * a 144 trap. If cmd fails, just ignore.
1394 */
bd99fdea 1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1398 if (err)
1399 return err;
1400
bd99fdea 1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1402
1403 return err;
1404}
1405
cdbe33d0
EC		 1406static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1407 u32 value)
1408{
1409 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1410 struct mlx5_core_dev *mdev;
1411 u8 mdev_port_num;
cdbe33d0
EC		 1412 int err;
1413
b3cbd6f0
DJ		 1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1415 if (!mdev)
1416 return -ENODEV;
1417
1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1419 if (err)
b3cbd6f0 1420 goto out;
cdbe33d0
EC		 1421
1422 if (~ctx.cap_mask1_perm & mask) {
1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1424 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1425 err = -EINVAL;
1426 goto out;
cdbe33d0
EC		 1427 }
1428
1429 ctx.cap_mask1 = value;
1430 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1432 0, &ctx);
1433
1434out:
1435 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1436
1437 return err;
1438}
1439
e126ba97
EC		 1440static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1441 struct ib_port_modify *props)
1442{
1443 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1444 struct ib_port_attr attr;
1445 u32 tmp;
1446 int err;
cdbe33d0
EC		 1447 u32 change_mask;
1448 u32 value;
1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1450 IB_LINK_LAYER_INFINIBAND);
1451
ec255879
MD		 1452 /* CM layer calls ib_modify_port() regardless of the link layer. For
1453 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1454 */
1455 if (!is_ib)
1456 return 0;
1457
cdbe33d0
EC		 1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1461 return set_port_caps_atomic(dev, port, change_mask, value);
1462 }
e126ba97
EC		 1463
1464 mutex_lock(&dev->cap_mask_mutex);
1465
c4550c63 1466 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1467 if (err)
1468 goto out;
1469
1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1471 ~props->clr_port_cap_mask;
1472
9603b61d 1473 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1474
1475out:
1476 mutex_unlock(&dev->cap_mask_mutex);
1477 return err;
1478}
1479
30aa60b3
EC		 1480static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1481{
1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1484}
1485
31a78a5a
YH		 1486static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1487{
1488 /* Large page with non 4k uar support might limit the dynamic size */
1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1490 return MLX5_MIN_DYN_BFREGS;
1491
1492 return MLX5_MAX_DYN_BFREGS;
1493}
1494
b037c29a
EC		 1495static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1496 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1497 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1498{
1499 int uars_per_sys_page;
1500 int bfregs_per_sys_page;
1501 int ref_bfregs = req->total_num_bfregs;
1502
1503 if (req->total_num_bfregs == 0)
1504 return -EINVAL;
1505
1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1508
1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1510 return -ENOMEM;
1511
1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1514 /* This holds the required static allocation asked by the user */
b037c29a 1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1517 return -EINVAL;
1518
31a78a5a
YH		 1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1523
1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1526 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1527 req->total_num_bfregs, bfregi->total_num_bfregs,
1528 bfregi->num_sys_pages);
b037c29a
EC		 1529
1530 return 0;
1531}
1532
1533static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1534{
1535 struct mlx5_bfreg_info *bfregi;
1536 int err;
1537 int i;
1538
1539 bfregi = &context->bfregi;
31a78a5a 1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1542 if (err)
1543 goto error;
1544
1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1546 }
4ed131d0
YH		 1547
1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1550
b037c29a
EC		 1551 return 0;
1552
1553error:
1554 for (--i; i >= 0; i--)
1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1557
1558 return err;
1559}
1560
15177999
LR		 1561static void deallocate_uars(struct mlx5_ib_dev *dev,
1562 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1563{
1564 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1565 int i;
1566
1567 bfregi = &context->bfregi;
15177999 1568 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1569 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1572}
1573
c85023e1
HN		 1574static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1575{
1576 int err;
1577
cfdeb893
LR		 1578 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1579 return 0;
1580
c85023e1
HN		 1581 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1582 if (err)
1583 return err;
1584
1585 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1586 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1587 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1588 return err;
1589
1590 mutex_lock(&dev->lb_mutex);
1591 dev->user_td++;
1592
1593 if (dev->user_td == 2)
1594 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1595
1596 mutex_unlock(&dev->lb_mutex);
1597 return err;
1598}
1599
1600static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1601{
cfdeb893
LR		 1602 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1603 return;
1604
c85023e1
HN		 1605 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1606
1607 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1608 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1609 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1610 return;
1611
1612 mutex_lock(&dev->lb_mutex);
1613 dev->user_td--;
1614
1615 if (dev->user_td < 2)
1616 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1617
1618 mutex_unlock(&dev->lb_mutex);
1619}
1620
e126ba97
EC		 1621static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1622 struct ib_udata *udata)
1623{
1624 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1625 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1626 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1627 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1628 struct mlx5_ib_ucontext *context;
2f5ff264 1629 struct mlx5_bfreg_info *bfregi;
78c0f98c 1630 int ver;
e126ba97 1631 int err;
a168a41c
MD		 1632 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1633 max_cqe_version);
25bb36e7 1634 u32 dump_fill_mkey;
b037c29a 1635 bool lib_uar_4k;
e126ba97
EC		 1636
1637 if (!dev->ib_active)
1638 return ERR_PTR(-EAGAIN);
1639
e093111d 1640 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1641 ver = 0;
e093111d 1642 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1643 ver = 2;
1644 else
1645 return ERR_PTR(-EINVAL);
1646
e093111d 1647 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1648 if (err)
1649 return ERR_PTR(err);
1650
a8b92ca1
YH		 1651 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1652 return ERR_PTR(-EOPNOTSUPP);
78c0f98c 1653
f72300c5 1654 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1655 return ERR_PTR(-EOPNOTSUPP);
1656
2f5ff264
EC		 1657 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1658 MLX5_NON_FP_BFREGS_PER_UAR);
1659 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1660 return ERR_PTR(-EINVAL);
1661
938fe83c 1662 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1663 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1664 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1665 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1666 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1667 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1668 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1669 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1670 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1671 resp.cqe_version = min_t(__u8,
1672 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1673 req.max_cqe_version);
30aa60b3
EC		 1674 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1675 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1676 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1677 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1678 resp.response_length = min(offsetof(typeof(resp), response_length) +
1679 sizeof(resp.response_length), udata->outlen);
e126ba97 1680
c03faa56
MB		 1681 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1682 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1683 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1684 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1685 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1686 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1687 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1688 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1689 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1690 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1691 }
1692
e126ba97
EC		 1693 context = kzalloc(sizeof(*context), GFP_KERNEL);
1694 if (!context)
1695 return ERR_PTR(-ENOMEM);
1696
30aa60b3 1697 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1698 bfregi = &context->bfregi;
b037c29a
EC		 1699
1700 /* updates req->total_num_bfregs */
31a78a5a 1701 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1702 if (err)
e126ba97 1703 goto out_ctx;
e126ba97 1704
b037c29a
EC		 1705 mutex_init(&bfregi->lock);
1706 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1707 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1708 GFP_KERNEL);
b037c29a 1709 if (!bfregi->count) {
e126ba97 1710 err = -ENOMEM;
b037c29a 1711 goto out_ctx;
e126ba97
EC		 1712 }
1713
b037c29a
EC		 1714 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1715 sizeof(*bfregi->sys_pages),
1716 GFP_KERNEL);
1717 if (!bfregi->sys_pages) {
e126ba97 1718 err = -ENOMEM;
b037c29a 1719 goto out_count;
e126ba97
EC		 1720 }
1721
b037c29a
EC		 1722 err = allocate_uars(dev, context);
1723 if (err)
1724 goto out_sys_pages;
e126ba97 1725
b4cfe447
HE		 1726#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1727 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1728#endif
1729
cfdeb893
LR		 1730 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1731 if (err)
1732 goto out_uars;
146d2f1a 1733
a8b92ca1
YH		 1734 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1735 /* Block DEVX on Infiniband as of SELinux */
1736 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1737 err = -EPERM;
1738 goto out_td;
1739 }
1740
1741 err = mlx5_ib_devx_create(dev, context);
1742 if (err)
1743 goto out_td;
1744 }
1745
25bb36e7
YC		 1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1748 if (err)
8193abb6 1749 goto out_mdev;
25bb36e7
YC		 1750 }
1751
7c2344c3 1752 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1753 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1754 INIT_LIST_HEAD(&context->db_page_list);
1755 mutex_init(&context->db_page_mutex);
1756
2f5ff264 1757 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1758 resp.num_ports = dev->num_ports;
b368d7cb 1759
f72300c5
HA		 1760 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1761 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1762
402ca536 1763 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1764 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1765 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1766 resp.response_length += sizeof(resp.cmds_supp_uhw);
1767 }
1768
78984898
OG		 1769 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1770 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1771 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1772 resp.eth_min_inline++;
1773 }
1774 resp.response_length += sizeof(resp.eth_min_inline);
1775 }
1776
5c99eaec
FD		 1777 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1778 if (mdev->clock_info)
1779 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1780 resp.response_length += sizeof(resp.clock_info_versions);
1781 }
1782
bc5c6eed
NO		 1783 /*
1784 * We don't want to expose information from the PCI bar that is located
1785 * after 4096 bytes, so if the arch only supports larger pages, let's
1786 * pretend we don't support reading the HCA's core clock. This is also
1787 * forced by mmap function.
1788 */
de8d6e02
EC		 1789 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1790 if (PAGE_SIZE <= 4096) {
1791 resp.comp_mask |=
1792 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1793 resp.hca_core_clock_offset =
1794 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1795 }
5c99eaec 1796 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1797 }
1798
30aa60b3
EC		 1799 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1800 resp.response_length += sizeof(resp.log_uar_size);
1801
1802 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1803 resp.response_length += sizeof(resp.num_uars_per_page);
1804
31a78a5a
YH		 1805 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1806 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1807 resp.response_length += sizeof(resp.num_dyn_bfregs);
1808 }
1809
25bb36e7
YC		 1810 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1811 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1812 resp.dump_fill_mkey = dump_fill_mkey;
1813 resp.comp_mask |=
1814 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1815 }
1816 resp.response_length += sizeof(resp.dump_fill_mkey);
1817 }
1818
b368d7cb 1819 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1820 if (err)
a8b92ca1 1821 goto out_mdev;
e126ba97 1822
2f5ff264
EC		 1823 bfregi->ver = ver;
1824 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1825 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1826 context->lib_caps = req.lib_caps;
1827 print_lib_caps(dev, context->lib_caps);
f72300c5 1828
c6a21c38
MD		 1829 if (mlx5_lag_is_active(dev->mdev)) {
1830 u8 port = mlx5_core_native_port_num(dev->mdev);
1831
1832 atomic_set(&context->tx_port_affinity,
1833 atomic_add_return(
1834 1, &dev->roce[port].tx_port_affinity));
1835 }
1836
e126ba97
EC		 1837 return &context->ibucontext;
1838
a8b92ca1
YH		 1839out_mdev:
1840 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1841 mlx5_ib_devx_destroy(dev, context);
146d2f1a 1842out_td:
cfdeb893 1843 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1844
e126ba97 1845out_uars:
b037c29a 1846 deallocate_uars(dev, context);
e126ba97 1847
b037c29a
EC		 1848out_sys_pages:
1849 kfree(bfregi->sys_pages);
e126ba97 1850
b037c29a
EC		 1851out_count:
1852 kfree(bfregi->count);
e126ba97
EC		 1853
1854out_ctx:
1855 kfree(context);
b037c29a 1856
e126ba97
EC		 1857 return ERR_PTR(err);
1858}
1859
1860static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1861{
1862 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1863 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1864 struct mlx5_bfreg_info *bfregi;
e126ba97 1865
a8b92ca1
YH		 1866 if (context->devx_uid)
1867 mlx5_ib_devx_destroy(dev, context);
1868
b037c29a 1869 bfregi = &context->bfregi;
cfdeb893 1870 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1871
b037c29a
EC		 1872 deallocate_uars(dev, context);
1873 kfree(bfregi->sys_pages);
2f5ff264 1874 kfree(bfregi->count);
e126ba97
EC		 1875 kfree(context);
1876
1877 return 0;
1878}
1879
b037c29a 1880static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1881 int uar_idx)
e126ba97 1882{
b037c29a
EC		 1883 int fw_uars_per_page;
1884
1885 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1886
4ed131d0 1887 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1888}
1889
1890static int get_command(unsigned long offset)
1891{
1892 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1893}
1894
1895static int get_arg(unsigned long offset)
1896{
1897 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1898}
1899
1900static int get_index(unsigned long offset)
1901{
1902 return get_arg(offset);
1903}
1904
4ed131d0
YH		 1905/* Index resides in an extra byte to enable larger values than 255 */
1906static int get_extended_index(unsigned long offset)
1907{
1908 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1909}
1910
7c2344c3
MG		 1911static void mlx5_ib_vma_open(struct vm_area_struct *area)
1912{
1913 /* vma_open is called when a new VMA is created on top of our VMA. This
1914 * is done through either mremap flow or split_vma (usually due to
1915 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1916 * as this VMA is strongly hardware related. Therefore we set the
1917 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1918 * calling us again and trying to do incorrect actions. We assume that
1919 * the original VMA size is exactly a single page, and therefore all
1920 * "splitting" operation will not happen to it.
1921 */
1922 area->vm_ops = NULL;
1923}
1924
1925static void mlx5_ib_vma_close(struct vm_area_struct *area)
1926{
1927 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1928
1929 /* It's guaranteed that all VMAs opened on a FD are closed before the
1930 * file itself is closed, therefore no sync is needed with the regular
1931 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1932 * However need a sync with accessing the vma as part of
1933 * mlx5_ib_disassociate_ucontext.
1934 * The close operation is usually called under mm->mmap_sem except when
1935 * process is exiting.
1936 * The exiting case is handled explicitly as part of
1937 * mlx5_ib_disassociate_ucontext.
1938 */
1939 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1940
1941 /* setting the vma context pointer to null in the mlx5_ib driver's
1942 * private data, to protect a race condition in
1943 * mlx5_ib_disassociate_ucontext().
1944 */
1945 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1946 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1947 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1948 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1949 kfree(mlx5_ib_vma_priv_data);
1950}
1951
1952static const struct vm_operations_struct mlx5_ib_vm_ops = {
1953 .open = mlx5_ib_vma_open,
1954 .close = mlx5_ib_vma_close
1955};
1956
1957static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1958 struct mlx5_ib_ucontext *ctx)
1959{
1960 struct mlx5_ib_vma_private_data *vma_prv;
1961 struct list_head *vma_head = &ctx->vma_private_list;
1962
1963 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1964 if (!vma_prv)
1965 return -ENOMEM;
1966
1967 vma_prv->vma = vma;
ad9a3668 1968 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1969 vma->vm_private_data = vma_prv;
1970 vma->vm_ops = &mlx5_ib_vm_ops;
1971
ad9a3668 1972 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1973 list_add(&vma_prv->list, vma_head);
ad9a3668 1974 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1975
1976 return 0;
1977}
1978
1979static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1980{
7c2344c3
MG		 1981 struct vm_area_struct *vma;
1982 struct mlx5_ib_vma_private_data *vma_private, *n;
1983 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
7c2344c3 1984
ad9a3668 1985 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1986 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1987 list) {
1988 vma = vma_private->vma;
2cb40791 1989 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
7c2344c3
MG		 1990 /* context going to be destroyed, should
1991 * not access ops any more.
1992 */
13776612 1993 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1994 vma->vm_ops = NULL;
1995 list_del(&vma_private->list);
1996 kfree(vma_private);
1997 }
ad9a3668 1998 mutex_unlock(&context->vma_private_list_mutex);
7c2344c3
MG		 1999}
2000
37aa5c36
GL		 2001static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2002{
2003 switch (cmd) {
2004 case MLX5_IB_MMAP_WC_PAGE:
2005 return "WC";
2006 case MLX5_IB_MMAP_REGULAR_PAGE:
2007 return "best effort WC";
2008 case MLX5_IB_MMAP_NC_PAGE:
2009 return "NC";
24da0016
AL		 2010 case MLX5_IB_MMAP_DEVICE_MEM:
2011 return "Device Memory";
37aa5c36
GL		 2012 default:
2013 return NULL;
2014 }
2015}
2016
5c99eaec
FD		 2017static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2018 struct vm_area_struct *vma,
2019 struct mlx5_ib_ucontext *context)
2020{
2021 phys_addr_t pfn;
2022 int err;
2023
2024 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2025 return -EINVAL;
2026
2027 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2028 return -EOPNOTSUPP;
2029
2030 if (vma->vm_flags & VM_WRITE)
2031 return -EPERM;
2032
2033 if (!dev->mdev->clock_info_page)
2034 return -EOPNOTSUPP;
2035
2036 pfn = page_to_pfn(dev->mdev->clock_info_page);
2037 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2038 vma->vm_page_prot);
2039 if (err)
2040 return err;
2041
5c99eaec
FD		 2042 return mlx5_ib_set_vma_data(vma, context);
2043}
2044
37aa5c36 2045static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2046 struct vm_area_struct *vma,
2047 struct mlx5_ib_ucontext *context)
37aa5c36 2048{
2f5ff264 2049 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2050 int err;
2051 unsigned long idx;
aa09ea6e 2052 phys_addr_t pfn;
37aa5c36 2053 pgprot_t prot;
4ed131d0
YH		 2054 u32 bfreg_dyn_idx = 0;
2055 u32 uar_index;
2056 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2057 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2058 bfregi->num_static_sys_pages;
b037c29a
EC		 2059
2060 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2061 return -EINVAL;
2062
4ed131d0
YH		 2063 if (dyn_uar)
2064 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2065 else
2066 idx = get_index(vma->vm_pgoff);
2067
2068 if (idx >= max_valid_idx) {
2069 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2070 idx, max_valid_idx);
b037c29a
EC		 2071 return -EINVAL;
2072 }
37aa5c36
GL		 2073
2074 switch (cmd) {
2075 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2076 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2077/* Some architectures don't support WC memory */
2078#if defined(CONFIG_X86)
2079 if (!pat_enabled())
2080 return -EPERM;
2081#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2082 return -EPERM;
2083#endif
2084 /* fall through */
2085 case MLX5_IB_MMAP_REGULAR_PAGE:
2086 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2087 prot = pgprot_writecombine(vma->vm_page_prot);
2088 break;
2089 case MLX5_IB_MMAP_NC_PAGE:
2090 prot = pgprot_noncached(vma->vm_page_prot);
2091 break;
2092 default:
2093 return -EINVAL;
2094 }
2095
4ed131d0
YH		 2096 if (dyn_uar) {
2097 int uars_per_page;
2098
2099 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2100 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2101 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2102 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2103 bfreg_dyn_idx, bfregi->total_num_bfregs);
2104 return -EINVAL;
2105 }
2106
2107 mutex_lock(&bfregi->lock);
2108 /* Fail if uar already allocated, first bfreg index of each
2109 * page holds its count.
2110 */
2111 if (bfregi->count[bfreg_dyn_idx]) {
2112 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2113 mutex_unlock(&bfregi->lock);
2114 return -EINVAL;
2115 }
2116
2117 bfregi->count[bfreg_dyn_idx]++;
2118 mutex_unlock(&bfregi->lock);
2119
2120 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2121 if (err) {
2122 mlx5_ib_warn(dev, "UAR alloc failed\n");
2123 goto free_bfreg;
2124 }
2125 } else {
2126 uar_index = bfregi->sys_pages[idx];
2127 }
2128
2129 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2130 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2131
2132 vma->vm_page_prot = prot;
2133 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2134 PAGE_SIZE, vma->vm_page_prot);
2135 if (err) {
8f062287
LR		 2136 mlx5_ib_err(dev,
2137 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2138 err, mmap_cmd2str(cmd));
4ed131d0
YH		 2139 err = -EAGAIN;
2140 goto err;
37aa5c36
GL		 2141 }
2142
4ed131d0
YH		 2143 err = mlx5_ib_set_vma_data(vma, context);
2144 if (err)
2145 goto err;
2146
2147 if (dyn_uar)
2148 bfregi->sys_pages[idx] = uar_index;
2149 return 0;
2150
2151err:
2152 if (!dyn_uar)
2153 return err;
2154
2155 mlx5_cmd_free_uar(dev->mdev, idx);
2156
2157free_bfreg:
2158 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2159
2160 return err;
37aa5c36
GL		 2161}
2162
24da0016
AL		 2163static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2164{
2165 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2166 struct mlx5_ib_dev *dev = to_mdev(context->device);
2167 u16 page_idx = get_extended_index(vma->vm_pgoff);
2168 size_t map_size = vma->vm_end - vma->vm_start;
2169 u32 npages = map_size >> PAGE_SHIFT;
2170 phys_addr_t pfn;
2171 pgprot_t prot;
2172
2173 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2174 page_idx + npages)
2175 return -EINVAL;
2176
2177 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2178 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2179 PAGE_SHIFT) +
2180 page_idx;
2181 prot = pgprot_writecombine(vma->vm_page_prot);
2182 vma->vm_page_prot = prot;
2183
2184 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2185 vma->vm_page_prot))
2186 return -EAGAIN;
2187
2188 return mlx5_ib_set_vma_data(vma, mctx);
2189}
2190
e126ba97
EC		 2191static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2192{
2193 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2194 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2195 unsigned long command;
e126ba97
EC		 2196 phys_addr_t pfn;
2197
2198 command = get_command(vma->vm_pgoff);
2199 switch (command) {
37aa5c36
GL		 2200 case MLX5_IB_MMAP_WC_PAGE:
2201 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2202 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2203 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2204 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2205
2206 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2207 return -ENOSYS;
2208
d69e3bcf 2209 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2210 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2211 return -EINVAL;
2212
6cbac1e4 2213 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2214 return -EPERM;
2215
2216 /* Don't expose to user-space information it shouldn't have */
2217 if (PAGE_SIZE > 4096)
2218 return -EOPNOTSUPP;
2219
2220 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2221 pfn = (dev->mdev->iseg_base +
2222 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2223 PAGE_SHIFT;
2224 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2225 PAGE_SIZE, vma->vm_page_prot))
2226 return -EAGAIN;
d69e3bcf 2227 break;
5c99eaec
FD		 2228 case MLX5_IB_MMAP_CLOCK_INFO:
2229 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2230
24da0016
AL		 2231 case MLX5_IB_MMAP_DEVICE_MEM:
2232 return dm_mmap(ibcontext, vma);
2233
e126ba97
EC		 2234 default:
2235 return -EINVAL;
2236 }
2237
2238 return 0;
2239}
2240
24da0016
AL		 2241struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2242 struct ib_ucontext *context,
2243 struct ib_dm_alloc_attr *attr,
2244 struct uverbs_attr_bundle *attrs)
2245{
2246 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2247 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2248 phys_addr_t memic_addr;
2249 struct mlx5_ib_dm *dm;
2250 u64 start_offset;
2251 u32 page_idx;
2252 int err;
2253
2254 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2255 if (!dm)
2256 return ERR_PTR(-ENOMEM);
2257
2258 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2259 attr->length, act_size, attr->alignment);
2260
2261 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2262 act_size, attr->alignment);
2263 if (err)
2264 goto err_free;
2265
2266 start_offset = memic_addr & ~PAGE_MASK;
2267 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2268 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2269 PAGE_SHIFT;
2270
2271 err = uverbs_copy_to(attrs,
2272 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2273 &start_offset, sizeof(start_offset));
2274 if (err)
2275 goto err_dealloc;
2276
2277 err = uverbs_copy_to(attrs,
2278 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2279 &page_idx, sizeof(page_idx));
2280 if (err)
2281 goto err_dealloc;
2282
2283 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2284 DIV_ROUND_UP(act_size, PAGE_SIZE));
2285
2286 dm->dev_addr = memic_addr;
2287
2288 return &dm->ibdm;
2289
2290err_dealloc:
2291 mlx5_cmd_dealloc_memic(memic, memic_addr,
2292 act_size);
2293err_free:
2294 kfree(dm);
2295 return ERR_PTR(err);
2296}
2297
2298int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2299{
2300 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2301 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2302 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2303 u32 page_idx;
2304 int ret;
2305
2306 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2307 if (ret)
2308 return ret;
2309
2310 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2311 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2312 PAGE_SHIFT;
2313 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2314 page_idx,
2315 DIV_ROUND_UP(act_size, PAGE_SIZE));
2316
2317 kfree(dm);
2318
2319 return 0;
2320}
2321
e126ba97
EC		 2322static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2323 struct ib_ucontext *context,
2324 struct ib_udata *udata)
2325{
2326 struct mlx5_ib_alloc_pd_resp resp;
2327 struct mlx5_ib_pd *pd;
2328 int err;
2329
2330 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2331 if (!pd)
2332 return ERR_PTR(-ENOMEM);
2333
9603b61d 2334 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2335 if (err) {
2336 kfree(pd);
2337 return ERR_PTR(err);
2338 }
2339
2340 if (context) {
2341 resp.pdn = pd->pdn;
2342 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2343 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2344 kfree(pd);
2345 return ERR_PTR(-EFAULT);
2346 }
e126ba97
EC		 2347 }
2348
2349 return &pd->ibpd;
2350}
2351
2352static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2353{
2354 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2355 struct mlx5_ib_pd *mpd = to_mpd(pd);
2356
9603b61d 2357 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2358 kfree(mpd);
2359
2360 return 0;
2361}
2362
466fa6d2
MG		 2363enum {
2364 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2365 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2366 MATCH_CRITERIA_ENABLE_INNER_BIT,
2367 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2368};
2369
2370#define HEADER_IS_ZERO(match_criteria, headers) \
2371 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2372 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2373
466fa6d2 2374static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2375{
466fa6d2 2376 u8 match_criteria_enable;
038d2ef8 2377
466fa6d2
MG		 2378 match_criteria_enable =
2379 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2380 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2381 match_criteria_enable |=
2382 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2383 MATCH_CRITERIA_ENABLE_MISC_BIT;
2384 match_criteria_enable |=
2385 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2386 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2387 match_criteria_enable |=
2388 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2389 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2390
2391 return match_criteria_enable;
038d2ef8
MG		 2392}
2393
ca0d4753
MG		 2394static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2395{
2396 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2397 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2398}
2399
37da2a03 2400static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2401 bool inner)
2402{
2403 if (inner) {
2404 MLX5_SET(fte_match_set_misc,
2405 misc_c, inner_ipv6_flow_label, mask);
2406 MLX5_SET(fte_match_set_misc,
2407 misc_v, inner_ipv6_flow_label, val);
2408 } else {
2409 MLX5_SET(fte_match_set_misc,
2410 misc_c, outer_ipv6_flow_label, mask);
2411 MLX5_SET(fte_match_set_misc,
2412 misc_v, outer_ipv6_flow_label, val);
2413 }
2414}
2415
ca0d4753
MG		 2416static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2417{
2418 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2419 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2420 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2421 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2422}
2423
71c6e863
AL		 2424static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2425{
2426 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2427 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2428 return -EOPNOTSUPP;
2429
2430 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2431 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2432 return -EOPNOTSUPP;
2433
2434 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2435 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2436 return -EOPNOTSUPP;
2437
2438 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2439 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2440 return -EOPNOTSUPP;
2441
2442 return 0;
2443}
2444
c47ac6ae
MG		 2445#define LAST_ETH_FIELD vlan_tag
2446#define LAST_IB_FIELD sl
ca0d4753 2447#define LAST_IPV4_FIELD tos
466fa6d2 2448#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2449#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2450#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2451#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2452#define LAST_DROP_FIELD size
3b3233fb 2453#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2454
2455/* Field is the last supported field */
2456#define FIELDS_NOT_SUPPORTED(filter, field)\
2457 memchr_inv((void *)&filter.field +\
2458 sizeof(filter.field), 0,\
2459 sizeof(filter) -\
2460 offsetof(typeof(filter), field) -\
2461 sizeof(filter.field))
2462
802c2125
AY		 2463static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2464 const struct ib_flow_attr *flow_attr,
2465 struct mlx5_flow_act *action)
2466{
2467 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2468
2469 switch (maction->ib_action.type) {
2470 case IB_FLOW_ACTION_ESP:
2471 /* Currently only AES_GCM keymat is supported by the driver */
2472 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2473 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2474 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2475 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2476 return 0;
2477 default:
2478 return -EOPNOTSUPP;
2479 }
2480}
2481
19cc7524
AL		 2482static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2483 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2484 const struct ib_flow_attr *flow_attr,
71c6e863 2485 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2486{
466fa6d2
MG		 2487 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2488 misc_parameters);
2489 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2490 misc_parameters);
71c6e863
AL		 2491 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2492 misc_parameters_2);
2493 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2494 misc_parameters_2);
2d1e697e
MR		 2495 void *headers_c;
2496 void *headers_v;
19cc7524 2497 int match_ipv;
802c2125 2498 int ret;
2d1e697e
MR		 2499
2500 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2501 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2502 inner_headers);
2503 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2504 inner_headers);
19cc7524
AL		 2505 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2506 ft_field_support.inner_ip_version);
2d1e697e
MR		 2507 } else {
2508 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2509 outer_headers);
2510 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2511 outer_headers);
19cc7524
AL		 2512 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2513 ft_field_support.outer_ip_version);
2d1e697e 2514 }
466fa6d2 2515
2d1e697e 2516 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2517 case IB_FLOW_SPEC_ETH:
c47ac6ae 2518 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2519 return -EOPNOTSUPP;
038d2ef8 2520
2d1e697e 2521 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2522 dmac_47_16),
2523 ib_spec->eth.mask.dst_mac);
2d1e697e 2524 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2525 dmac_47_16),
2526 ib_spec->eth.val.dst_mac);
2527
2d1e697e 2528 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2529 smac_47_16),
2530 ib_spec->eth.mask.src_mac);
2d1e697e 2531 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2532 smac_47_16),
2533 ib_spec->eth.val.src_mac);
2534
038d2ef8 2535 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2536 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2537 cvlan_tag, 1);
2d1e697e 2538 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2539 cvlan_tag, 1);
038d2ef8 2540
2d1e697e 2541 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2542 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2543 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2544 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2545
2d1e697e 2546 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2547 first_cfi,
2548 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2549 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2550 first_cfi,
2551 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2552
2d1e697e 2553 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2554 first_prio,
2555 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2556 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2557 first_prio,
2558 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2559 }
2d1e697e 2560 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2561 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2562 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2563 ethertype, ntohs(ib_spec->eth.val.ether_type));
2564 break;
2565 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2566 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2567 return -EOPNOTSUPP;
038d2ef8 2568
19cc7524
AL		 2569 if (match_ipv) {
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2571 ip_version, 0xf);
2572 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2573 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2574 } else {
2575 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2576 ethertype, 0xffff);
2577 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2578 ethertype, ETH_P_IP);
2579 }
038d2ef8 2580
2d1e697e 2581 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2582 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2583 &ib_spec->ipv4.mask.src_ip,
2584 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2585 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2586 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2587 &ib_spec->ipv4.val.src_ip,
2588 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2589 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2590 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2591 &ib_spec->ipv4.mask.dst_ip,
2592 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2593 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2594 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2595 &ib_spec->ipv4.val.dst_ip,
2596 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2597
2d1e697e 2598 set_tos(headers_c, headers_v,
ca0d4753
MG		 2599 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2600
2d1e697e 2601 set_proto(headers_c, headers_v,
ca0d4753 2602 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2603 break;
026bae0c 2604 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2605 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2606 return -EOPNOTSUPP;
026bae0c 2607
19cc7524
AL		 2608 if (match_ipv) {
2609 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2610 ip_version, 0xf);
2611 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2612 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2613 } else {
2614 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2615 ethertype, 0xffff);
2616 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2617 ethertype, ETH_P_IPV6);
2618 }
026bae0c 2619
2d1e697e 2620 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2621 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2622 &ib_spec->ipv6.mask.src_ip,
2623 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2624 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2625 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2626 &ib_spec->ipv6.val.src_ip,
2627 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2628 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2629 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2630 &ib_spec->ipv6.mask.dst_ip,
2631 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2632 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2633 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2634 &ib_spec->ipv6.val.dst_ip,
2635 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2636
2d1e697e 2637 set_tos(headers_c, headers_v,
466fa6d2
MG		 2638 ib_spec->ipv6.mask.traffic_class,
2639 ib_spec->ipv6.val.traffic_class);
2640
2d1e697e 2641 set_proto(headers_c, headers_v,
466fa6d2
MG		 2642 ib_spec->ipv6.mask.next_hdr,
2643 ib_spec->ipv6.val.next_hdr);
2644
2d1e697e
MR		 2645 set_flow_label(misc_params_c, misc_params_v,
2646 ntohl(ib_spec->ipv6.mask.flow_label),
2647 ntohl(ib_spec->ipv6.val.flow_label),
2648 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2649 break;
2650 case IB_FLOW_SPEC_ESP:
2651 if (ib_spec->esp.mask.seq)
2652 return -EOPNOTSUPP;
2d1e697e 2653
802c2125
AY		 2654 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2655 ntohl(ib_spec->esp.mask.spi));
2656 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2657 ntohl(ib_spec->esp.val.spi));
026bae0c 2658 break;
038d2ef8 2659 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2660 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2661 LAST_TCP_UDP_FIELD))
1ffd3a26 2662 return -EOPNOTSUPP;
038d2ef8 2663
2d1e697e 2664 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2665 0xff);
2d1e697e 2666 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2667 IPPROTO_TCP);
2668
2d1e697e 2669 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2670 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2672 ntohs(ib_spec->tcp_udp.val.src_port));
2673
2d1e697e 2674 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2675 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2676 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2677 ntohs(ib_spec->tcp_udp.val.dst_port));
2678 break;
2679 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2680 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2681 LAST_TCP_UDP_FIELD))
1ffd3a26 2682 return -EOPNOTSUPP;
038d2ef8 2683
2d1e697e 2684 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2685 0xff);
2d1e697e 2686 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2687 IPPROTO_UDP);
2688
2d1e697e 2689 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2690 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2691 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2692 ntohs(ib_spec->tcp_udp.val.src_port));
2693
2d1e697e 2694 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2695 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2696 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2697 ntohs(ib_spec->tcp_udp.val.dst_port));
2698 break;
da2f22ae
AL		 2699 case IB_FLOW_SPEC_GRE:
2700 if (ib_spec->gre.mask.c_ks_res0_ver)
2701 return -EOPNOTSUPP;
2702
2703 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2704 0xff);
2705 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2706 IPPROTO_GRE);
2707
2708 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2709 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2710 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2711 ntohs(ib_spec->gre.val.protocol));
2712
2713 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2714 gre_key_h),
2715 &ib_spec->gre.mask.key,
2716 sizeof(ib_spec->gre.mask.key));
2717 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2718 gre_key_h),
2719 &ib_spec->gre.val.key,
2720 sizeof(ib_spec->gre.val.key));
2721 break;
71c6e863
AL		 2722 case IB_FLOW_SPEC_MPLS:
2723 switch (prev_type) {
2724 case IB_FLOW_SPEC_UDP:
2725 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2726 ft_field_support.outer_first_mpls_over_udp),
2727 &ib_spec->mpls.mask.tag))
2728 return -EOPNOTSUPP;
2729
2730 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2731 outer_first_mpls_over_udp),
2732 &ib_spec->mpls.val.tag,
2733 sizeof(ib_spec->mpls.val.tag));
2734 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2735 outer_first_mpls_over_udp),
2736 &ib_spec->mpls.mask.tag,
2737 sizeof(ib_spec->mpls.mask.tag));
2738 break;
2739 case IB_FLOW_SPEC_GRE:
2740 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2741 ft_field_support.outer_first_mpls_over_gre),
2742 &ib_spec->mpls.mask.tag))
2743 return -EOPNOTSUPP;
2744
2745 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2746 outer_first_mpls_over_gre),
2747 &ib_spec->mpls.val.tag,
2748 sizeof(ib_spec->mpls.val.tag));
2749 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2750 outer_first_mpls_over_gre),
2751 &ib_spec->mpls.mask.tag,
2752 sizeof(ib_spec->mpls.mask.tag));
2753 break;
2754 default:
2755 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2756 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2757 ft_field_support.inner_first_mpls),
2758 &ib_spec->mpls.mask.tag))
2759 return -EOPNOTSUPP;
2760
2761 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2762 inner_first_mpls),
2763 &ib_spec->mpls.val.tag,
2764 sizeof(ib_spec->mpls.val.tag));
2765 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2766 inner_first_mpls),
2767 &ib_spec->mpls.mask.tag,
2768 sizeof(ib_spec->mpls.mask.tag));
2769 } else {
2770 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2771 ft_field_support.outer_first_mpls),
2772 &ib_spec->mpls.mask.tag))
2773 return -EOPNOTSUPP;
2774
2775 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2776 outer_first_mpls),
2777 &ib_spec->mpls.val.tag,
2778 sizeof(ib_spec->mpls.val.tag));
2779 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2780 outer_first_mpls),
2781 &ib_spec->mpls.mask.tag,
2782 sizeof(ib_spec->mpls.mask.tag));
2783 }
2784 }
2785 break;
ffb30d8f
MR		 2786 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2787 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2788 LAST_TUNNEL_FIELD))
1ffd3a26 2789 return -EOPNOTSUPP;
ffb30d8f
MR		 2790
2791 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2792 ntohl(ib_spec->tunnel.mask.tunnel_id));
2793 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2794 ntohl(ib_spec->tunnel.val.tunnel_id));
2795 break;
2ac693f9
MR		 2796 case IB_FLOW_SPEC_ACTION_TAG:
2797 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2798 LAST_FLOW_TAG_FIELD))
2799 return -EOPNOTSUPP;
2800 if (ib_spec->flow_tag.tag_id >= BIT(24))
2801 return -EINVAL;
2802
075572d4 2803 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2804 action->has_flow_tag = true;
2ac693f9 2805 break;
a22ed86c
SS		 2806 case IB_FLOW_SPEC_ACTION_DROP:
2807 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2808 LAST_DROP_FIELD))
2809 return -EOPNOTSUPP;
075572d4 2810 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2811 break;
802c2125
AY		 2812 case IB_FLOW_SPEC_ACTION_HANDLE:
2813 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2814 if (ret)
2815 return ret;
2816 break;
3b3233fb
RS		 2817 case IB_FLOW_SPEC_ACTION_COUNT:
2818 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2819 LAST_COUNTERS_FIELD))
2820 return -EOPNOTSUPP;
2821
2822 /* for now support only one counters spec per flow */
2823 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2824 return -EINVAL;
2825
2826 action->counters = ib_spec->flow_count.counters;
2827 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2828 break;
038d2ef8
MG		 2829 default:
2830 return -EINVAL;
2831 }
2832
2833 return 0;
2834}
2835
2836/* If a flow could catch both multicast and unicast packets,
2837 * it won't fall into the multicast flow steering table and this rule
2838 * could steal other multicast packets.
2839 */
a550ddfc 2840static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2841{
81e30880 2842 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2843
2844 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2845 ib_attr->num_of_specs < 1)
2846 return false;
2847
81e30880
YH		 2848 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2849 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2850 struct ib_flow_spec_ipv4 *ipv4_spec;
2851
2852 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2853 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2854 return true;
2855
038d2ef8 2856 return false;
81e30880
YH		 2857 }
2858
2859 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2860 struct ib_flow_spec_eth *eth_spec;
2861
2862 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2863 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2864 is_multicast_ether_addr(eth_spec->val.dst_mac);
2865 }
038d2ef8 2866
81e30880 2867 return false;
038d2ef8
MG		 2868}
2869
802c2125
AY		 2870enum valid_spec {
2871 VALID_SPEC_INVALID,
2872 VALID_SPEC_VALID,
2873 VALID_SPEC_NA,
2874};
2875
2876static enum valid_spec
2877is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2878 const struct mlx5_flow_spec *spec,
2879 const struct mlx5_flow_act *flow_act,
2880 bool egress)
2881{
2882 const u32 *match_c = spec->match_criteria;
2883 bool is_crypto =
2884 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2885 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2886 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2887 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2888
2889 /*
2890 * Currently only crypto is supported in egress, when regular egress
2891 * rules would be supported, always return VALID_SPEC_NA.
2892 */
2893 if (!is_crypto)
2894 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2895
2896 return is_crypto && is_ipsec &&
2897 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2898 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2899}
2900
2901static bool is_valid_spec(struct mlx5_core_dev *mdev,
2902 const struct mlx5_flow_spec *spec,
2903 const struct mlx5_flow_act *flow_act,
2904 bool egress)
2905{
2906 /* We curretly only support ipsec egress flow */
2907 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2908}
2909
19cc7524
AL		 2910static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2911 const struct ib_flow_attr *flow_attr,
0f750966 2912 bool check_inner)
038d2ef8
MG		 2913{
2914 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2915 int match_ipv = check_inner ?
2916 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2917 ft_field_support.inner_ip_version) :
2918 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2919 ft_field_support.outer_ip_version);
0f750966
AL		 2920 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2921 bool ipv4_spec_valid, ipv6_spec_valid;
2922 unsigned int ip_spec_type = 0;
2923 bool has_ethertype = false;
038d2ef8 2924 unsigned int spec_index;
0f750966
AL		 2925 bool mask_valid = true;
2926 u16 eth_type = 0;
2927 bool type_valid;
038d2ef8
MG		 2928
2929 /* Validate that ethertype is correct */
2930 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2931 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2932 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2933 mask_valid = (ib_spec->eth.mask.ether_type ==
2934 htons(0xffff));
2935 has_ethertype = true;
2936 eth_type = ntohs(ib_spec->eth.val.ether_type);
2937 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2938 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2939 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2940 }
2941 ib_spec = (void *)ib_spec + ib_spec->size;
2942 }
0f750966
AL		 2943
2944 type_valid = (!has_ethertype) || (!ip_spec_type);
2945 if (!type_valid && mask_valid) {
2946 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2947 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2948 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2949 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2950
2951 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2952 (((eth_type == ETH_P_MPLS_UC) ||
2953 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2954 }
2955
2956 return type_valid;
2957}
2958
19cc7524
AL		 2959static bool is_valid_attr(struct mlx5_core_dev *mdev,
2960 const struct ib_flow_attr *flow_attr)
0f750966 2961{
19cc7524
AL		 2962 return is_valid_ethertype(mdev, flow_attr, false) &&
2963 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2964}
2965
2966static void put_flow_table(struct mlx5_ib_dev *dev,
2967 struct mlx5_ib_flow_prio *prio, bool ft_added)
2968{
2969 prio->refcount -= !!ft_added;
2970 if (!prio->refcount) {
2971 mlx5_destroy_flow_table(prio->flow_table);
2972 prio->flow_table = NULL;
2973 }
2974}
2975
3b3233fb
RS		 2976static void counters_clear_description(struct ib_counters *counters)
2977{
2978 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2979
2980 mutex_lock(&mcounters->mcntrs_mutex);
2981 kfree(mcounters->counters_data);
2982 mcounters->counters_data = NULL;
2983 mcounters->cntrs_max_index = 0;
2984 mutex_unlock(&mcounters->mcntrs_mutex);
2985}
2986
038d2ef8
MG		 2987static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2988{
038d2ef8
MG		 2989 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2990 struct mlx5_ib_flow_handler,
2991 ibflow);
2992 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 2993 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 2994
9a4ca38d 2995 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2996
2997 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2998 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2999 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3000 list_del(&iter->list);
3001 kfree(iter);
3002 }
3003
74491de9 3004 mlx5_del_flow_rules(handler->rule);
5497adc6 3005 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3006 if (handler->ibcounters &&
3007 atomic_read(&handler->ibcounters->usecnt) == 1)
3008 counters_clear_description(handler->ibcounters);
038d2ef8 3009
3b3233fb 3010 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3011 if (handler->flow_matcher)
3012 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3013 kfree(handler);
3014
3015 return 0;
3016}
3017
35d19011
MG		 3018static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3019{
3020 priority *= 2;
3021 if (!dont_trap)
3022 priority++;
3023 return priority;
3024}
3025
cc0e5d42
MG		 3026enum flow_table_type {
3027 MLX5_IB_FT_RX,
3028 MLX5_IB_FT_TX
3029};
3030
00b7c2ab
MG		 3031#define MLX5_FS_MAX_TYPES 6
3032#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3033
3034static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3035 struct mlx5_ib_flow_prio *prio,
3036 int priority,
3037 int num_entries, int num_groups)
3038{
3039 struct mlx5_flow_table *ft;
3040
3041 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3042 num_entries,
3043 num_groups,
3044 0, 0);
3045 if (IS_ERR(ft))
3046 return ERR_CAST(ft);
3047
3048 prio->flow_table = ft;
3049 prio->refcount = 0;
3050 return prio;
3051}
3052
038d2ef8 3053static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3054 struct ib_flow_attr *flow_attr,
3055 enum flow_table_type ft_type)
038d2ef8 3056{
35d19011 3057 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3058 struct mlx5_flow_namespace *ns = NULL;
3059 struct mlx5_ib_flow_prio *prio;
3060 struct mlx5_flow_table *ft;
dac388ef 3061 int max_table_size;
038d2ef8
MG		 3062 int num_entries;
3063 int num_groups;
3064 int priority;
038d2ef8 3065
dac388ef
MG		 3066 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3067 log_max_ft_size));
038d2ef8 3068 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
802c2125
AY		 3069 if (ft_type == MLX5_IB_FT_TX)
3070 priority = 0;
3071 else if (flow_is_multicast_only(flow_attr) &&
3072 !dont_trap)
038d2ef8
MG		 3073 priority = MLX5_IB_FLOW_MCAST_PRIO;
3074 else
35d19011
MG		 3075 priority = ib_prio_to_core_prio(flow_attr->priority,
3076 dont_trap);
038d2ef8 3077 ns = mlx5_get_flow_namespace(dev->mdev,
802c2125
AY		 3078 ft_type == MLX5_IB_FT_TX ?
3079 MLX5_FLOW_NAMESPACE_EGRESS :
038d2ef8
MG		 3080 MLX5_FLOW_NAMESPACE_BYPASS);
3081 num_entries = MLX5_FS_MAX_ENTRIES;
3082 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 3083 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 3084 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3085 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3086 ns = mlx5_get_flow_namespace(dev->mdev,
3087 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3088 build_leftovers_ft_param(&priority,
3089 &num_entries,
3090 &num_groups);
9a4ca38d 3091 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3092 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3093 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3094 allow_sniffer_and_nic_rx_shared_tir))
3095 return ERR_PTR(-ENOTSUPP);
3096
3097 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3098 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3099 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3100
9a4ca38d 3101 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3102 priority = 0;
3103 num_entries = 1;
3104 num_groups = 1;
038d2ef8
MG		 3105 }
3106
3107 if (!ns)
3108 return ERR_PTR(-ENOTSUPP);
3109
dac388ef
MG		 3110 if (num_entries > max_table_size)
3111 return ERR_PTR(-ENOMEM);
3112
038d2ef8 3113 ft = prio->flow_table;
d4be3f44
YH		 3114 if (!ft)
3115 return _get_prio(ns, prio, priority, num_entries, num_groups);
038d2ef8 3116
d4be3f44 3117 return prio;
038d2ef8
MG		 3118}
3119
a550ddfc
YH		 3120static void set_underlay_qp(struct mlx5_ib_dev *dev,
3121 struct mlx5_flow_spec *spec,
3122 u32 underlay_qpn)
3123{
3124 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3125 spec->match_criteria,
3126 misc_parameters);
3127 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3128 misc_parameters);
3129
3130 if (underlay_qpn &&
3131 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3132 ft_field_support.bth_dst_qp)) {
3133 MLX5_SET(fte_match_set_misc,
3134 misc_params_v, bth_dst_qp, underlay_qpn);
3135 MLX5_SET(fte_match_set_misc,
3136 misc_params_c, bth_dst_qp, 0xffffff);
3137 }
3138}
3139
5e95af5f
RS		 3140static int read_flow_counters(struct ib_device *ibdev,
3141 struct mlx5_read_counters_attr *read_attr)
3142{
3143 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3144 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3145
3146 return mlx5_fc_query(dev->mdev, fc,
3147 &read_attr->out[IB_COUNTER_PACKETS],
3148 &read_attr->out[IB_COUNTER_BYTES]);
3149}
3150
3151/* flow counters currently expose two counters packets and bytes */
3152#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3153static int counters_set_description(struct ib_counters *counters,
3154 enum mlx5_ib_counters_type counters_type,
3155 struct mlx5_ib_flow_counters_desc *desc_data,
3156 u32 ncounters)
3157{
3158 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3159 u32 cntrs_max_index = 0;
3160 int i;
3161
3162 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3163 return -EINVAL;
3164
3165 /* init the fields for the object */
3166 mcounters->type = counters_type;
5e95af5f
RS		 3167 mcounters->read_counters = read_flow_counters;
3168 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3169 mcounters->ncounters = ncounters;
3170 /* each counter entry have both description and index pair */
3171 for (i = 0; i < ncounters; i++) {
3172 if (desc_data[i].description > IB_COUNTER_BYTES)
3173 return -EINVAL;
3174
3175 if (cntrs_max_index <= desc_data[i].index)
3176 cntrs_max_index = desc_data[i].index + 1;
3177 }
3178
3179 mutex_lock(&mcounters->mcntrs_mutex);
3180 mcounters->counters_data = desc_data;
3181 mcounters->cntrs_max_index = cntrs_max_index;
3182 mutex_unlock(&mcounters->mcntrs_mutex);
3183
3184 return 0;
3185}
3186
3187#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3188static int flow_counters_set_data(struct ib_counters *ibcounters,
3189 struct mlx5_ib_create_flow *ucmd)
3190{
3191 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3192 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3193 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3194 bool hw_hndl = false;
3195 int ret = 0;
3196
3197 if (ucmd && ucmd->ncounters_data != 0) {
3198 cntrs_data = ucmd->data;
3199 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3200 return -EINVAL;
3201
3202 desc_data = kcalloc(cntrs_data->ncounters,
3203 sizeof(*desc_data),
3204 GFP_KERNEL);
3205 if (!desc_data)
3206 return -ENOMEM;
3207
3208 if (copy_from_user(desc_data,
3209 u64_to_user_ptr(cntrs_data->counters_data),
3210 sizeof(*desc_data) * cntrs_data->ncounters)) {
3211 ret = -EFAULT;
3212 goto free;
3213 }
3214 }
3215
3216 if (!mcounters->hw_cntrs_hndl) {
3217 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3218 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3219 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3220 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3221 goto free;
3222 }
3223 hw_hndl = true;
3224 }
3225
3226 if (desc_data) {
3227 /* counters already bound to at least one flow */
3228 if (mcounters->cntrs_max_index) {
3229 ret = -EINVAL;
3230 goto free_hndl;
3231 }
3232
3233 ret = counters_set_description(ibcounters,
3234 MLX5_IB_COUNTERS_FLOW,
3235 desc_data,
3236 cntrs_data->ncounters);
3237 if (ret)
3238 goto free_hndl;
3239
3240 } else if (!mcounters->cntrs_max_index) {
3241 /* counters not bound yet, must have udata passed */
3242 ret = -EINVAL;
3243 goto free_hndl;
3244 }
3245
3246 return 0;
3247
3248free_hndl:
3249 if (hw_hndl) {
3250 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3251 mcounters->hw_cntrs_hndl);
3252 mcounters->hw_cntrs_hndl = NULL;
3253 }
3254free:
3255 kfree(desc_data);
3256 return ret;
3257}
3258
a550ddfc
YH		 3259static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3260 struct mlx5_ib_flow_prio *ft_prio,
3261 const struct ib_flow_attr *flow_attr,
3262 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3263 u32 underlay_qpn,
3264 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3265{
3266 struct mlx5_flow_table *ft = ft_prio->flow_table;
3267 struct mlx5_ib_flow_handler *handler;
075572d4 3268 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3269 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3270 struct mlx5_flow_destination dest_arr[2] = {};
3271 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3272 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3273 unsigned int spec_index;
71c6e863 3274 u32 prev_type = 0;
038d2ef8 3275 int err = 0;
3b3233fb 3276 int dest_num = 0;
802c2125 3277 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3278
19cc7524 3279 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3280 return ERR_PTR(-EINVAL);
3281
1b9a07ee 3282 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3283 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3284 if (!handler || !spec) {
038d2ef8
MG		 3285 err = -ENOMEM;
3286 goto free;
3287 }
3288
3289 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3290 if (dst) {
3291 memcpy(&dest_arr[0], dst, sizeof(*dst));
3292 dest_num++;
3293 }
038d2ef8
MG		 3294
3295 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3296 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3297 spec->match_value,
71c6e863
AL		 3298 ib_flow, flow_attr, &flow_act,
3299 prev_type);
038d2ef8
MG		 3300 if (err < 0)
3301 goto free;
3302
71c6e863 3303 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3304 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3305 }
3306
a550ddfc
YH		 3307 if (!flow_is_multicast_only(flow_attr))
3308 set_underlay_qp(dev, spec, underlay_qpn);
3309
018a94ee
MB		 3310 if (dev->rep) {
3311 void *misc;
3312
3313 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3314 misc_parameters);
3315 MLX5_SET(fte_match_set_misc, misc, source_port,
3316 dev->rep->vport);
3317 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3318 misc_parameters);
3319 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3320 }
3321
466fa6d2 3322 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3323
3324 if (is_egress &&
3325 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3326 err = -EINVAL;
3327 goto free;
3328 }
3329
3b3233fb
RS		 3330 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3331 err = flow_counters_set_data(flow_act.counters, ucmd);
3332 if (err)
3333 goto free;
3334
3335 handler->ibcounters = flow_act.counters;
3336 dest_arr[dest_num].type =
3337 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3338 dest_arr[dest_num].counter =
3339 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3340 dest_num++;
3341 }
3342
075572d4 3343 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3344 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3345 rule_dst = NULL;
3346 dest_num = 0;
3347 }
a22ed86c 3348 } else {
802c2125
AY		 3349 if (is_egress)
3350 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3351 else
3352 flow_act.action |=
3b3233fb 3353 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3354 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3355 }
2ac693f9 3356
a9db0ecf 3357 if (flow_act.has_flow_tag &&
2ac693f9
MR		 3358 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3359 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3360 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3361 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3362 err = -EINVAL;
3363 goto free;
3364 }
74491de9 3365 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3366 &flow_act,
a22ed86c 3367 rule_dst, dest_num);
038d2ef8
MG		 3368
3369 if (IS_ERR(handler->rule)) {
3370 err = PTR_ERR(handler->rule);
3371 goto free;
3372 }
3373
d9d4980a 3374 ft_prio->refcount++;
5497adc6 3375 handler->prio = ft_prio;
d4be3f44 3376 handler->dev = dev;
038d2ef8
MG		 3377
3378 ft_prio->flow_table = ft;
3379free:
3b3233fb
RS		 3380 if (err && handler) {
3381 if (handler->ibcounters &&
3382 atomic_read(&handler->ibcounters->usecnt) == 1)
3383 counters_clear_description(handler->ibcounters);
038d2ef8 3384 kfree(handler);
3b3233fb 3385 }
c5bb1730 3386 kvfree(spec);
038d2ef8
MG		 3387 return err ? ERR_PTR(err) : handler;
3388}
3389
a550ddfc
YH		 3390static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3391 struct mlx5_ib_flow_prio *ft_prio,
3392 const struct ib_flow_attr *flow_attr,
3393 struct mlx5_flow_destination *dst)
3394{
3b3233fb 3395 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3396}
3397
35d19011
MG		 3398static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3399 struct mlx5_ib_flow_prio *ft_prio,
3400 struct ib_flow_attr *flow_attr,
3401 struct mlx5_flow_destination *dst)
3402{
3403 struct mlx5_ib_flow_handler *handler_dst = NULL;
3404 struct mlx5_ib_flow_handler *handler = NULL;
3405
3406 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3407 if (!IS_ERR(handler)) {
3408 handler_dst = create_flow_rule(dev, ft_prio,
3409 flow_attr, dst);
3410 if (IS_ERR(handler_dst)) {
74491de9 3411 mlx5_del_flow_rules(handler->rule);
d9d4980a 3412 ft_prio->refcount--;
35d19011
MG		 3413 kfree(handler);
3414 handler = handler_dst;
3415 } else {
3416 list_add(&handler_dst->list, &handler->list);
3417 }
3418 }
3419
3420 return handler;
3421}
038d2ef8
MG		 3422enum {
3423 LEFTOVERS_MC,
3424 LEFTOVERS_UC,
3425};
3426
3427static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3428 struct mlx5_ib_flow_prio *ft_prio,
3429 struct ib_flow_attr *flow_attr,
3430 struct mlx5_flow_destination *dst)
3431{
3432 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3433 struct mlx5_ib_flow_handler *handler = NULL;
3434
3435 static struct {
3436 struct ib_flow_attr flow_attr;
3437 struct ib_flow_spec_eth eth_flow;
3438 } leftovers_specs[] = {
3439 [LEFTOVERS_MC] = {
3440 .flow_attr = {
3441 .num_of_specs = 1,
3442 .size = sizeof(leftovers_specs[0])
3443 },
3444 .eth_flow = {
3445 .type = IB_FLOW_SPEC_ETH,
3446 .size = sizeof(struct ib_flow_spec_eth),
3447 .mask = {.dst_mac = {0x1} },
3448 .val = {.dst_mac = {0x1} }
3449 }
3450 },
3451 [LEFTOVERS_UC] = {
3452 .flow_attr = {
3453 .num_of_specs = 1,
3454 .size = sizeof(leftovers_specs[0])
3455 },
3456 .eth_flow = {
3457 .type = IB_FLOW_SPEC_ETH,
3458 .size = sizeof(struct ib_flow_spec_eth),
3459 .mask = {.dst_mac = {0x1} },
3460 .val = {.dst_mac = {} }
3461 }
3462 }
3463 };
3464
3465 handler = create_flow_rule(dev, ft_prio,
3466 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3467 dst);
3468 if (!IS_ERR(handler) &&
3469 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3470 handler_ucast = create_flow_rule(dev, ft_prio,
3471 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3472 dst);
3473 if (IS_ERR(handler_ucast)) {
74491de9 3474 mlx5_del_flow_rules(handler->rule);
d9d4980a 3475 ft_prio->refcount--;
038d2ef8
MG		 3476 kfree(handler);
3477 handler = handler_ucast;
3478 } else {
3479 list_add(&handler_ucast->list, &handler->list);
3480 }
3481 }
3482
3483 return handler;
3484}
3485
cc0e5d42
MG		 3486static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3487 struct mlx5_ib_flow_prio *ft_rx,
3488 struct mlx5_ib_flow_prio *ft_tx,
3489 struct mlx5_flow_destination *dst)
3490{
3491 struct mlx5_ib_flow_handler *handler_rx;
3492 struct mlx5_ib_flow_handler *handler_tx;
3493 int err;
3494 static const struct ib_flow_attr flow_attr = {
3495 .num_of_specs = 0,
3496 .size = sizeof(flow_attr)
3497 };
3498
3499 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3500 if (IS_ERR(handler_rx)) {
3501 err = PTR_ERR(handler_rx);
3502 goto err;
3503 }
3504
3505 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3506 if (IS_ERR(handler_tx)) {
3507 err = PTR_ERR(handler_tx);
3508 goto err_tx;
3509 }
3510
3511 list_add(&handler_tx->list, &handler_rx->list);
3512
3513 return handler_rx;
3514
3515err_tx:
74491de9 3516 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3517 ft_rx->refcount--;
3518 kfree(handler_rx);
3519err:
3520 return ERR_PTR(err);
3521}
3522
038d2ef8
MG		 3523static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3524 struct ib_flow_attr *flow_attr,
59082a32
MB		 3525 int domain,
3526 struct ib_udata *udata)
038d2ef8
MG		 3527{
3528 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3529 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3530 struct mlx5_ib_flow_handler *handler = NULL;
3531 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3532 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3533 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3534 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3535 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3536 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3537 int err;
a550ddfc 3538 int underlay_qpn;
038d2ef8 3539
3b3233fb
RS		 3540 if (udata && udata->inlen) {
3541 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3542 sizeof(ucmd_hdr.reserved);
3543 if (udata->inlen < min_ucmd_sz)
3544 return ERR_PTR(-EOPNOTSUPP);
3545
3546 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3547 if (err)
3548 return ERR_PTR(err);
3549
3550 /* currently supports only one counters data */
3551 if (ucmd_hdr.ncounters_data > 1)
3552 return ERR_PTR(-EINVAL);
3553
3554 required_ucmd_sz = min_ucmd_sz +
3555 sizeof(struct mlx5_ib_flow_counters_data) *
3556 ucmd_hdr.ncounters_data;
3557 if (udata->inlen > required_ucmd_sz &&
3558 !ib_is_udata_cleared(udata, required_ucmd_sz,
3559 udata->inlen - required_ucmd_sz))
3560 return ERR_PTR(-EOPNOTSUPP);
3561
3562 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3563 if (!ucmd)
3564 return ERR_PTR(-ENOMEM);
3565
3566 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3567 if (err)
3568 goto free_ucmd;
3b3233fb 3569 }
59082a32 3570
299eafee
GS		 3571 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3572 err = -ENOMEM;
3573 goto free_ucmd;
3574 }
038d2ef8
MG		 3575
3576 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3577 flow_attr->port > dev->num_ports ||
802c2125 3578 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3579 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3580 err = -EINVAL;
3581 goto free_ucmd;
3582 }
802c2125
AY		 3583
3584 if (is_egress &&
3585 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3586 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3587 err = -EINVAL;
3588 goto free_ucmd;
3589 }
038d2ef8
MG		 3590
3591 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3592 if (!dst) {
3593 err = -ENOMEM;
3594 goto free_ucmd;
3595 }
038d2ef8 3596
9a4ca38d 3597 mutex_lock(&dev->flow_db->lock);
038d2ef8 3598
802c2125
AY		 3599 ft_prio = get_flow_table(dev, flow_attr,
3600 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3601 if (IS_ERR(ft_prio)) {
3602 err = PTR_ERR(ft_prio);
3603 goto unlock;
3604 }
cc0e5d42
MG		 3605 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3606 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3607 if (IS_ERR(ft_prio_tx)) {
3608 err = PTR_ERR(ft_prio_tx);
3609 ft_prio_tx = NULL;
3610 goto destroy_ft;
3611 }
3612 }
038d2ef8 3613
802c2125
AY		 3614 if (is_egress) {
3615 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3616 } else {
3617 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3618 if (mqp->flags & MLX5_IB_QP_RSS)
3619 dst->tir_num = mqp->rss_qp.tirn;
3620 else
3621 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3622 }
038d2ef8
MG		 3623
3624 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3625 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3626 handler = create_dont_trap_rule(dev, ft_prio,
3627 flow_attr, dst);
3628 } else {
a550ddfc
YH		 3629 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3630 mqp->underlay_qpn : 0;
3631 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3632 dst, underlay_qpn, ucmd);
35d19011 3633 }
038d2ef8
MG		 3634 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3635 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3636 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3637 dst);
cc0e5d42
MG		 3638 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3639 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3640 } else {
3641 err = -EINVAL;
3642 goto destroy_ft;
3643 }
3644
3645 if (IS_ERR(handler)) {
3646 err = PTR_ERR(handler);
3647 handler = NULL;
3648 goto destroy_ft;
3649 }
3650
9a4ca38d 3651 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3652 kfree(dst);
3b3233fb 3653 kfree(ucmd);
038d2ef8
MG		 3654
3655 return &handler->ibflow;
3656
3657destroy_ft:
3658 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3659 if (ft_prio_tx)
3660 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3661unlock:
9a4ca38d 3662 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3663 kfree(dst);
299eafee 3664free_ucmd:
3b3233fb 3665 kfree(ucmd);
038d2ef8
MG		 3666 return ERR_PTR(err);
3667}
3668
d4be3f44
YH		 3669static struct mlx5_ib_flow_prio *_get_flow_table(struct mlx5_ib_dev *dev,
3670 int priority, bool mcast)
3671{
3672 int max_table_size;
3673 struct mlx5_flow_namespace *ns = NULL;
3674 struct mlx5_ib_flow_prio *prio;
3675
3676 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3677 log_max_ft_size));
3678 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3679 return ERR_PTR(-ENOMEM);
3680
3681 if (mcast)
3682 priority = MLX5_IB_FLOW_MCAST_PRIO;
3683 else
3684 priority = ib_prio_to_core_prio(priority, false);
3685
3686 ns = mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS);
3687 if (!ns)
3688 return ERR_PTR(-ENOTSUPP);
3689
3690 prio = &dev->flow_db->prios[priority];
3691
3692 if (prio->flow_table)
3693 return prio;
3694
3695 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3696 MLX5_FS_MAX_TYPES);
3697}
3698
3699static struct mlx5_ib_flow_handler *
3700_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3701 struct mlx5_ib_flow_prio *ft_prio,
3702 struct mlx5_flow_destination *dst,
3703 struct mlx5_ib_flow_matcher *fs_matcher,
3704 void *cmd_in, int inlen)
3705{
3706 struct mlx5_ib_flow_handler *handler;
3707 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3708 struct mlx5_flow_spec *spec;
3709 struct mlx5_flow_table *ft = ft_prio->flow_table;
3710 int err = 0;
3711
3712 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3713 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3714 if (!handler || !spec) {
3715 err = -ENOMEM;
3716 goto free;
3717 }
3718
3719 INIT_LIST_HEAD(&handler->list);
3720
3721 memcpy(spec->match_value, cmd_in, inlen);
3722 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3723 fs_matcher->mask_len);
3724 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3725
3726 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3727 handler->rule = mlx5_add_flow_rules(ft, spec,
3728 &flow_act, dst, 1);
3729
3730 if (IS_ERR(handler->rule)) {
3731 err = PTR_ERR(handler->rule);
3732 goto free;
3733 }
3734
3735 ft_prio->refcount++;
3736 handler->prio = ft_prio;
3737 handler->dev = dev;
3738 ft_prio->flow_table = ft;
3739
3740free:
3741 if (err)
3742 kfree(handler);
3743 kvfree(spec);
3744 return err ? ERR_PTR(err) : handler;
3745}
3746
3747static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3748 void *match_v)
3749{
3750 void *match_c;
3751 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3752 void *dmac, *dmac_mask;
3753 void *ipv4, *ipv4_mask;
3754
3755 if (!(fs_matcher->match_criteria_enable &
3756 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3757 return false;
3758
3759 match_c = fs_matcher->matcher_mask.match_params;
3760 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3761 outer_headers);
3762 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3763 outer_headers);
3764
3765 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3766 dmac_47_16);
3767 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3768 dmac_47_16);
3769
3770 if (is_multicast_ether_addr(dmac) &&
3771 is_multicast_ether_addr(dmac_mask))
3772 return true;
3773
3774 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3775 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3776
3777 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3778 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3779
3780 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3781 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3782 return true;
3783
3784 return false;
3785}
3786
32269441
YH		 3787struct mlx5_ib_flow_handler *
3788mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3789 struct mlx5_ib_flow_matcher *fs_matcher,
3790 void *cmd_in, int inlen, int dest_id,
3791 int dest_type)
3792{
d4be3f44
YH		 3793 struct mlx5_flow_destination *dst;
3794 struct mlx5_ib_flow_prio *ft_prio;
3795 int priority = fs_matcher->priority;
3796 struct mlx5_ib_flow_handler *handler;
3797 bool mcast;
3798 int err;
3799
3800 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3801 return ERR_PTR(-EOPNOTSUPP);
3802
3803 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3804 return ERR_PTR(-ENOMEM);
3805
d4be3f44
YH		 3806 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3807 if (!dst)
3808 return ERR_PTR(-ENOMEM);
3809
3810 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3811 mutex_lock(&dev->flow_db->lock);
3812
3813 ft_prio = _get_flow_table(dev, priority, mcast);
3814 if (IS_ERR(ft_prio)) {
3815 err = PTR_ERR(ft_prio);
3816 goto unlock;
3817 }
3818
6346f0bf
YH		 3819 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3820 dst->type = dest_type;
3821 dst->tir_num = dest_id;
3822 } else {
3823 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3824 dst->ft_num = dest_id;
3825 }
3826
d4be3f44
YH		 3827 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, cmd_in,
3828 inlen);
3829
3830 if (IS_ERR(handler)) {
3831 err = PTR_ERR(handler);
3832 goto destroy_ft;
3833 }
3834
3835 mutex_unlock(&dev->flow_db->lock);
3836 atomic_inc(&fs_matcher->usecnt);
3837 handler->flow_matcher = fs_matcher;
3838
3839 kfree(dst);
3840
3841 return handler;
3842
3843destroy_ft:
3844 put_flow_table(dev, ft_prio, false);
3845unlock:
3846 mutex_unlock(&dev->flow_db->lock);
3847 kfree(dst);
3848
3849 return ERR_PTR(err);
32269441
YH		 3850}
3851
c6475a0b
AY		 3852static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3853{
3854 u32 flags = 0;
3855
3856 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3857 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3858
3859 return flags;
3860}
3861
3862#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3863static struct ib_flow_action *
3864mlx5_ib_create_flow_action_esp(struct ib_device *device,
3865 const struct ib_flow_action_attrs_esp *attr,
3866 struct uverbs_attr_bundle *attrs)
3867{
3868 struct mlx5_ib_dev *mdev = to_mdev(device);
3869 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3870 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3871 struct mlx5_ib_flow_action *action;
3872 u64 action_flags;
3873 u64 flags;
3874 int err = 0;
3875
bccd0622
JG		 3876 err = uverbs_get_flags64(
3877 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3878 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3879 if (err)
3880 return ERR_PTR(err);
c6475a0b
AY		 3881
3882 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3883
3884 /* We current only support a subset of the standard features. Only a
3885 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3886 * (with overlap). Full offload mode isn't supported.
3887 */
3888 if (!attr->keymat || attr->replay || attr->encap ||
3889 attr->spi || attr->seq || attr->tfc_pad ||
3890 attr->hard_limit_pkts ||
3891 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3892 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3893 return ERR_PTR(-EOPNOTSUPP);
3894
3895 if (attr->keymat->protocol !=
3896 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3897 return ERR_PTR(-EOPNOTSUPP);
3898
3899 aes_gcm = &attr->keymat->keymat.aes_gcm;
3900
3901 if (aes_gcm->icv_len != 16 ||
3902 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3903 return ERR_PTR(-EOPNOTSUPP);
3904
3905 action = kmalloc(sizeof(*action), GFP_KERNEL);
3906 if (!action)
3907 return ERR_PTR(-ENOMEM);
3908
3909 action->esp_aes_gcm.ib_flags = attr->flags;
3910 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3911 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3912 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3913 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3914 sizeof(accel_attrs.keymat.aes_gcm.salt));
3915 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3916 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3917 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3918 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3919 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3920
3921 accel_attrs.esn = attr->esn;
3922 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3923 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3924 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3925 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3926
3927 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3928 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3929
3930 action->esp_aes_gcm.ctx =
3931 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3932 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3933 err = PTR_ERR(action->esp_aes_gcm.ctx);
3934 goto err_parse;
3935 }
3936
3937 action->esp_aes_gcm.ib_flags = attr->flags;
3938
3939 return &action->ib_action;
3940
3941err_parse:
3942 kfree(action);
3943 return ERR_PTR(err);
3944}
3945
349705c1
MB		 3946static int
3947mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3948 const struct ib_flow_action_attrs_esp *attr,
3949 struct uverbs_attr_bundle *attrs)
3950{
3951 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3952 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3953 int err = 0;
3954
3955 if (attr->keymat || attr->replay || attr->encap ||
3956 attr->spi || attr->seq || attr->tfc_pad ||
3957 attr->hard_limit_pkts ||
3958 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3959 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3960 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3961 return -EOPNOTSUPP;
3962
3963 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3964 * be modified.
3965 */
3966 if (!(maction->esp_aes_gcm.ib_flags &
3967 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3968 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3969 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3970 return -EINVAL;
3971
3972 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3973 sizeof(accel_attrs));
3974
3975 accel_attrs.esn = attr->esn;
3976 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3977 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3978 else
3979 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3980
3981 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3982 &accel_attrs);
3983 if (err)
3984 return err;
3985
3986 maction->esp_aes_gcm.ib_flags &=
3987 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3988 maction->esp_aes_gcm.ib_flags |=
3989 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3990
3991 return 0;
3992}
3993
c6475a0b
AY		 3994static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3995{
3996 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3997
3998 switch (action->type) {
3999 case IB_FLOW_ACTION_ESP:
4000 /*
4001 * We only support aes_gcm by now, so we implicitly know this is
4002 * the underline crypto.
4003 */
4004 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4005 break;
b4749bf2
MB		 4006 case IB_FLOW_ACTION_UNSPECIFIED:
4007 mlx5_ib_destroy_flow_action_raw(maction);
4008 break;
c6475a0b
AY		 4009 default:
4010 WARN_ON(true);
4011 break;
4012 }
4013
4014 kfree(maction);
4015 return 0;
4016}
4017
e126ba97
EC		 4018static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4019{
4020 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4021 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 4022 int err;
4023
81e30880
YH		 4024 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4025 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4026 return -EOPNOTSUPP;
4027 }
4028
9603b61d 4029 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 4030 if (err)
4031 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4032 ibqp->qp_num, gid->raw);
4033
4034 return err;
4035}
4036
4037static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4038{
4039 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4040 int err;
4041
9603b61d 4042 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 4043 if (err)
4044 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4045 ibqp->qp_num, gid->raw);
4046
4047 return err;
4048}
4049
4050static int init_node_data(struct mlx5_ib_dev *dev)
4051{
1b5daf11 4052 int err;
e126ba97 4053
1b5daf11 4054 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4055 if (err)
1b5daf11 4056 return err;
e126ba97 4057
1b5daf11 4058 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4059
1b5daf11 4060 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4061}
4062
4063static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4064 char *buf)
4065{
4066 struct mlx5_ib_dev *dev =
4067 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4068
9603b61d 4069 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 4070}
4071
4072static ssize_t show_reg_pages(struct device *device,
4073 struct device_attribute *attr, char *buf)
4074{
4075 struct mlx5_ib_dev *dev =
4076 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4077
6aec21f6 4078 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 4079}
4080
4081static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4082 char *buf)
4083{
4084 struct mlx5_ib_dev *dev =
4085 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 4086 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 4087}
4088
e126ba97
EC		 4089static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4090 char *buf)
4091{
4092 struct mlx5_ib_dev *dev =
4093 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 4094 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 4095}
4096
4097static ssize_t show_board(struct device *device, struct device_attribute *attr,
4098 char *buf)
4099{
4100 struct mlx5_ib_dev *dev =
4101 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4102 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4103 dev->mdev->board_id);
e126ba97
EC		 4104}
4105
4106static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 4107static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
4108static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
4109static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4110static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4111
4112static struct device_attribute *mlx5_class_attributes[] = {
4113 &dev_attr_hw_rev,
e126ba97
EC		 4114 &dev_attr_hca_type,
4115 &dev_attr_board_id,
4116 &dev_attr_fw_pages,
4117 &dev_attr_reg_pages,
4118};
4119
7722f47e
HE		 4120static void pkey_change_handler(struct work_struct *work)
4121{
4122 struct mlx5_ib_port_resources *ports =
4123 container_of(work, struct mlx5_ib_port_resources,
4124 pkey_change_work);
4125
4126 mutex_lock(&ports->devr->mutex);
4127 mlx5_ib_gsi_pkey_change(ports->gsi);
4128 mutex_unlock(&ports->devr->mutex);
4129}
4130
89ea94a7
MG		 4131static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4132{
4133 struct mlx5_ib_qp *mqp;
4134 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4135 struct mlx5_core_cq *mcq;
4136 struct list_head cq_armed_list;
4137 unsigned long flags_qp;
4138 unsigned long flags_cq;
4139 unsigned long flags;
4140
4141 INIT_LIST_HEAD(&cq_armed_list);
4142
4143 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4144 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4145 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4146 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4147 if (mqp->sq.tail != mqp->sq.head) {
4148 send_mcq = to_mcq(mqp->ibqp.send_cq);
4149 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4150 if (send_mcq->mcq.comp &&
4151 mqp->ibqp.send_cq->comp_handler) {
4152 if (!send_mcq->mcq.reset_notify_added) {
4153 send_mcq->mcq.reset_notify_added = 1;
4154 list_add_tail(&send_mcq->mcq.reset_notify,
4155 &cq_armed_list);
4156 }
4157 }
4158 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4159 }
4160 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4161 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4162 /* no handling is needed for SRQ */
4163 if (!mqp->ibqp.srq) {
4164 if (mqp->rq.tail != mqp->rq.head) {
4165 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4166 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4167 if (recv_mcq->mcq.comp &&
4168 mqp->ibqp.recv_cq->comp_handler) {
4169 if (!recv_mcq->mcq.reset_notify_added) {
4170 recv_mcq->mcq.reset_notify_added = 1;
4171 list_add_tail(&recv_mcq->mcq.reset_notify,
4172 &cq_armed_list);
4173 }
4174 }
4175 spin_unlock_irqrestore(&recv_mcq->lock,
4176 flags_cq);
4177 }
4178 }
4179 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4180 }
4181 /*At that point all inflight post send were put to be executed as of we
4182 * lock/unlock above locks Now need to arm all involved CQs.
4183 */
4184 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4185 mcq->comp(mcq);
4186 }
4187 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4188}
4189
03404e8a
MG		 4190static void delay_drop_handler(struct work_struct *work)
4191{
4192 int err;
4193 struct mlx5_ib_delay_drop *delay_drop =
4194 container_of(work, struct mlx5_ib_delay_drop,
4195 delay_drop_work);
4196
fe248c3a
MG		 4197 atomic_inc(&delay_drop->events_cnt);
4198
03404e8a
MG		 4199 mutex_lock(&delay_drop->lock);
4200 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4201 delay_drop->timeout);
4202 if (err) {
4203 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4204 delay_drop->timeout);
4205 delay_drop->activate = false;
4206 }
4207 mutex_unlock(&delay_drop->lock);
4208}
4209
d69a24e0 4210static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4211{
d69a24e0
DJ		 4212 struct mlx5_ib_event_work *work =
4213 container_of(_work, struct mlx5_ib_event_work, work);
4214 struct mlx5_ib_dev *ibdev;
e126ba97 4215 struct ib_event ibev;
dbaaff2a 4216 bool fatal = false;
aba46213 4217 u8 port = (u8)work->param;
e126ba97 4218
d69a24e0
DJ		 4219 if (mlx5_core_is_mp_slave(work->dev)) {
4220 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4221 if (!ibdev)
4222 goto out;
4223 } else {
4224 ibdev = work->context;
4225 }
4226
4227 switch (work->event) {
e126ba97 4228 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4229 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4230 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 4231 fatal = true;
e126ba97
EC		 4232 break;
4233
4234 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 4235 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 4236 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 4237 /* In RoCE, port up/down events are handled in
4238 * mlx5_netdev_event().
4239 */
4240 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4241 IB_LINK_LAYER_ETHERNET)
d69a24e0 4242 goto out;
5ec8c83e 4243
d69a24e0 4244 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 4245 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 4246 break;
4247
e126ba97
EC		 4248 case MLX5_DEV_EVENT_LID_CHANGE:
4249 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 4250 break;
4251
4252 case MLX5_DEV_EVENT_PKEY_CHANGE:
4253 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 4254 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 4255 break;
4256
4257 case MLX5_DEV_EVENT_GUID_CHANGE:
4258 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 4259 break;
4260
4261 case MLX5_DEV_EVENT_CLIENT_REREG:
4262 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 4263 break;
03404e8a
MG		 4264 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4265 schedule_work(&ibdev->delay_drop.delay_drop_work);
4266 goto out;
bdc37924 4267 default:
03404e8a 4268 goto out;
e126ba97
EC		 4269 }
4270
4271 ibev.device = &ibdev->ib_dev;
4272 ibev.element.port_num = port;
4273
aba46213 4274 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 4275 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 4276 goto out;
a0c84c32
EC		 4277 }
4278
e126ba97
EC		 4279 if (ibdev->ib_active)
4280 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4281
4282 if (fatal)
4283 ibdev->ib_active = false;
03404e8a 4284out:
d69a24e0
DJ		 4285 kfree(work);
4286}
4287
4288static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4289 enum mlx5_dev_event event, unsigned long param)
4290{
4291 struct mlx5_ib_event_work *work;
4292
4293 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4294 if (!work)
d69a24e0 4295 return;
d69a24e0 4296
10bea9c8
LR		 4297 INIT_WORK(&work->work, mlx5_ib_handle_event);
4298 work->dev = dev;
4299 work->param = param;
4300 work->context = context;
4301 work->event = event;
4302
4303 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 4304}
4305
c43f1112
MG		 4306static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4307{
4308 struct mlx5_hca_vport_context vport_ctx;
4309 int err;
4310 int port;
4311
508562d6 4312 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 4313 dev->mdev->port_caps[port - 1].has_smi = false;
4314 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4315 MLX5_CAP_PORT_TYPE_IB) {
4316 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4317 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4318 port, 0,
4319 &vport_ctx);
4320 if (err) {
4321 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4322 port, err);
4323 return err;
4324 }
4325 dev->mdev->port_caps[port - 1].has_smi =
4326 vport_ctx.has_smi;
4327 } else {
4328 dev->mdev->port_caps[port - 1].has_smi = true;
4329 }
4330 }
4331 }
4332 return 0;
4333}
4334
e126ba97
EC		 4335static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4336{
4337 int port;
4338
508562d6 4339 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4340 mlx5_query_ext_port_caps(dev, port);
4341}
4342
32f69e4b 4343static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4344{
4345 struct ib_device_attr *dprops = NULL;
4346 struct ib_port_attr *pprops = NULL;
f614fc15 4347 int err = -ENOMEM;
2528e33e 4348 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 4349
4350 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4351 if (!pprops)
4352 goto out;
4353
4354 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4355 if (!dprops)
4356 goto out;
4357
c43f1112
MG		 4358 err = set_has_smi_cap(dev);
4359 if (err)
4360 goto out;
4361
2528e33e 4362 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4363 if (err) {
4364 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4365 goto out;
4366 }
4367
32f69e4b
DJ		 4368 memset(pprops, 0, sizeof(*pprops));
4369 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4370 if (err) {
4371 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4372 port, err);
4373 goto out;
e126ba97
EC		 4374 }
4375
32f69e4b
DJ		 4376 dev->mdev->port_caps[port - 1].pkey_table_len =
4377 dprops->max_pkeys;
4378 dev->mdev->port_caps[port - 1].gid_table_len =
4379 pprops->gid_tbl_len;
4380 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4381 port, dprops->max_pkeys, pprops->gid_tbl_len);
4382
e126ba97
EC		 4383out:
4384 kfree(pprops);
4385 kfree(dprops);
4386
4387 return err;
4388}
4389
4390static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4391{
4392 int err;
4393
4394 err = mlx5_mr_cache_cleanup(dev);
4395 if (err)
4396 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4397
32927e28
MB		 4398 if (dev->umrc.qp)
4399 mlx5_ib_destroy_qp(dev->umrc.qp);
4400 if (dev->umrc.cq)
4401 ib_free_cq(dev->umrc.cq);
4402 if (dev->umrc.pd)
4403 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4404}
4405
4406enum {
4407 MAX_UMR_WR = 128,
4408};
4409
4410static int create_umr_res(struct mlx5_ib_dev *dev)
4411{
4412 struct ib_qp_init_attr *init_attr = NULL;
4413 struct ib_qp_attr *attr = NULL;
4414 struct ib_pd *pd;
4415 struct ib_cq *cq;
4416 struct ib_qp *qp;
e126ba97
EC		 4417 int ret;
4418
4419 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4420 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4421 if (!attr || !init_attr) {
4422 ret = -ENOMEM;
4423 goto error_0;
4424 }
4425
ed082d36 4426 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4427 if (IS_ERR(pd)) {
4428 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4429 ret = PTR_ERR(pd);
4430 goto error_0;
4431 }
4432
add08d76 4433 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4434 if (IS_ERR(cq)) {
4435 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4436 ret = PTR_ERR(cq);
4437 goto error_2;
4438 }
e126ba97
EC		 4439
4440 init_attr->send_cq = cq;
4441 init_attr->recv_cq = cq;
4442 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4443 init_attr->cap.max_send_wr = MAX_UMR_WR;
4444 init_attr->cap.max_send_sge = 1;
4445 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4446 init_attr->port_num = 1;
4447 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4448 if (IS_ERR(qp)) {
4449 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4450 ret = PTR_ERR(qp);
4451 goto error_3;
4452 }
4453 qp->device = &dev->ib_dev;
4454 qp->real_qp = qp;
4455 qp->uobject = NULL;
4456 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4457 qp->send_cq = init_attr->send_cq;
4458 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4459
4460 attr->qp_state = IB_QPS_INIT;
4461 attr->port_num = 1;
4462 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4463 IB_QP_PORT, NULL);
4464 if (ret) {
4465 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4466 goto error_4;
4467 }
4468
4469 memset(attr, 0, sizeof(*attr));
4470 attr->qp_state = IB_QPS_RTR;
4471 attr->path_mtu = IB_MTU_256;
4472
4473 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4474 if (ret) {
4475 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4476 goto error_4;
4477 }
4478
4479 memset(attr, 0, sizeof(*attr));
4480 attr->qp_state = IB_QPS_RTS;
4481 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4482 if (ret) {
4483 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4484 goto error_4;
4485 }
4486
4487 dev->umrc.qp = qp;
4488 dev->umrc.cq = cq;
e126ba97
EC		 4489 dev->umrc.pd = pd;
4490
4491 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4492 ret = mlx5_mr_cache_init(dev);
4493 if (ret) {
4494 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4495 goto error_4;
4496 }
4497
4498 kfree(attr);
4499 kfree(init_attr);
4500
4501 return 0;
4502
4503error_4:
4504 mlx5_ib_destroy_qp(qp);
32927e28 4505 dev->umrc.qp = NULL;
e126ba97
EC		 4506
4507error_3:
add08d76 4508 ib_free_cq(cq);
32927e28 4509 dev->umrc.cq = NULL;
e126ba97
EC		 4510
4511error_2:
e126ba97 4512 ib_dealloc_pd(pd);
32927e28 4513 dev->umrc.pd = NULL;
e126ba97
EC		 4514
4515error_0:
4516 kfree(attr);
4517 kfree(init_attr);
4518 return ret;
4519}
4520
6e8484c5
MG		 4521static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4522{
4523 switch (umr_fence_cap) {
4524 case MLX5_CAP_UMR_FENCE_NONE:
4525 return MLX5_FENCE_MODE_NONE;
4526 case MLX5_CAP_UMR_FENCE_SMALL:
4527 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4528 default:
4529 return MLX5_FENCE_MODE_STRONG_ORDERING;
4530 }
4531}
4532
e126ba97
EC		 4533static int create_dev_resources(struct mlx5_ib_resources *devr)
4534{
4535 struct ib_srq_init_attr attr;
4536 struct mlx5_ib_dev *dev;
bcf4c1ea 4537 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4538 int port;
e126ba97
EC		 4539 int ret = 0;
4540
4541 dev = container_of(devr, struct mlx5_ib_dev, devr);
4542
d16e91da
HE		 4543 mutex_init(&devr->mutex);
4544
e126ba97
EC		 4545 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4546 if (IS_ERR(devr->p0)) {
4547 ret = PTR_ERR(devr->p0);
4548 goto error0;
4549 }
4550 devr->p0->device = &dev->ib_dev;
4551 devr->p0->uobject = NULL;
4552 atomic_set(&devr->p0->usecnt, 0);
4553
bcf4c1ea 4554 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4555 if (IS_ERR(devr->c0)) {
4556 ret = PTR_ERR(devr->c0);
4557 goto error1;
4558 }
4559 devr->c0->device = &dev->ib_dev;
4560 devr->c0->uobject = NULL;
4561 devr->c0->comp_handler = NULL;
4562 devr->c0->event_handler = NULL;
4563 devr->c0->cq_context = NULL;
4564 atomic_set(&devr->c0->usecnt, 0);
4565
4566 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4567 if (IS_ERR(devr->x0)) {
4568 ret = PTR_ERR(devr->x0);
4569 goto error2;
4570 }
4571 devr->x0->device = &dev->ib_dev;
4572 devr->x0->inode = NULL;
4573 atomic_set(&devr->x0->usecnt, 0);
4574 mutex_init(&devr->x0->tgt_qp_mutex);
4575 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4576
4577 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4578 if (IS_ERR(devr->x1)) {
4579 ret = PTR_ERR(devr->x1);
4580 goto error3;
4581 }
4582 devr->x1->device = &dev->ib_dev;
4583 devr->x1->inode = NULL;
4584 atomic_set(&devr->x1->usecnt, 0);
4585 mutex_init(&devr->x1->tgt_qp_mutex);
4586 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4587
4588 memset(&attr, 0, sizeof(attr));
4589 attr.attr.max_sge = 1;
4590 attr.attr.max_wr = 1;
4591 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4592 attr.ext.cq = devr->c0;
e126ba97
EC		 4593 attr.ext.xrc.xrcd = devr->x0;
4594
4595 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4596 if (IS_ERR(devr->s0)) {
4597 ret = PTR_ERR(devr->s0);
4598 goto error4;
4599 }
4600 devr->s0->device = &dev->ib_dev;
4601 devr->s0->pd = devr->p0;
4602 devr->s0->uobject = NULL;
4603 devr->s0->event_handler = NULL;
4604 devr->s0->srq_context = NULL;
4605 devr->s0->srq_type = IB_SRQT_XRC;
4606 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4607 devr->s0->ext.cq = devr->c0;
e126ba97 4608 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4609 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4610 atomic_inc(&devr->p0->usecnt);
4611 atomic_set(&devr->s0->usecnt, 0);
4612
4aa17b28
HA		 4613 memset(&attr, 0, sizeof(attr));
4614 attr.attr.max_sge = 1;
4615 attr.attr.max_wr = 1;
4616 attr.srq_type = IB_SRQT_BASIC;
4617 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4618 if (IS_ERR(devr->s1)) {
4619 ret = PTR_ERR(devr->s1);
4620 goto error5;
4621 }
4622 devr->s1->device = &dev->ib_dev;
4623 devr->s1->pd = devr->p0;
4624 devr->s1->uobject = NULL;
4625 devr->s1->event_handler = NULL;
4626 devr->s1->srq_context = NULL;
4627 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4628 devr->s1->ext.cq = devr->c0;
4aa17b28 4629 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4630 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4631
7722f47e
HE		 4632 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4633 INIT_WORK(&devr->ports[port].pkey_change_work,
4634 pkey_change_handler);
4635 devr->ports[port].devr = devr;
4636 }
4637
e126ba97
EC		 4638 return 0;
4639
4aa17b28
HA		 4640error5:
4641 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4642error4:
4643 mlx5_ib_dealloc_xrcd(devr->x1);
4644error3:
4645 mlx5_ib_dealloc_xrcd(devr->x0);
4646error2:
4647 mlx5_ib_destroy_cq(devr->c0);
4648error1:
4649 mlx5_ib_dealloc_pd(devr->p0);
4650error0:
4651 return ret;
4652}
4653
4654static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4655{
7722f47e
HE		 4656 struct mlx5_ib_dev *dev =
4657 container_of(devr, struct mlx5_ib_dev, devr);
4658 int port;
4659
4aa17b28 4660 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4661 mlx5_ib_destroy_srq(devr->s0);
4662 mlx5_ib_dealloc_xrcd(devr->x0);
4663 mlx5_ib_dealloc_xrcd(devr->x1);
4664 mlx5_ib_destroy_cq(devr->c0);
4665 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4666
4667 /* Make sure no change P_Key work items are still executing */
4668 for (port = 0; port < dev->num_ports; ++port)
4669 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4670}
4671
b02289b3
AK		 4672static u32 get_core_cap_flags(struct ib_device *ibdev,
4673 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 4674{
4675 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4676 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4677 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4678 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4679 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4680 u32 ret = 0;
4681
b02289b3
AK		 4682 if (rep->grh_required)
4683 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4684
e53505a8 4685 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 4686 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 4687
85c7c014 4688 if (raw_support)
b02289b3 4689 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4690
e53505a8 4691 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4692 return ret;
e53505a8
AS		 4693
4694 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4695 return ret;
e53505a8
AS		 4696
4697 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4698 ret |= RDMA_CORE_PORT_IBA_ROCE;
4699
4700 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4701 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4702
4703 return ret;
4704}
4705
7738613e
IW		 4706static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4707 struct ib_port_immutable *immutable)
4708{
4709 struct ib_port_attr attr;
ca5b91d6
OG		 4710 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4711 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 4712 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 4713 int err;
4714
c4550c63 4715 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4716 if (err)
4717 return err;
4718
b02289b3
AK		 4719 if (ll == IB_LINK_LAYER_INFINIBAND) {
4720 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4721 &rep);
4722 if (err)
4723 return err;
4724 }
4725
7738613e
IW		 4726 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4727 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 4728 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 4729 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4730 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4731
4732 return 0;
4733}
4734
8e6efa3a
MB		 4735static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4736 struct ib_port_immutable *immutable)
4737{
4738 struct ib_port_attr attr;
4739 int err;
4740
4741 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4742
4743 err = ib_query_port(ibdev, port_num, &attr);
4744 if (err)
4745 return err;
4746
4747 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4748 immutable->gid_tbl_len = attr.gid_tbl_len;
4749 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4750
4751 return 0;
4752}
4753
9abb0d1b 4754static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4755{
4756 struct mlx5_ib_dev *dev =
4757 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4758 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4759 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4760 fw_rev_sub(dev->mdev));
c7342823
IW		 4761}
4762
45f95acd 4763static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4764{
4765 struct mlx5_core_dev *mdev = dev->mdev;
4766 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4767 MLX5_FLOW_NAMESPACE_LAG);
4768 struct mlx5_flow_table *ft;
4769 int err;
4770
4771 if (!ns || !mlx5_lag_is_active(mdev))
4772 return 0;
4773
4774 err = mlx5_cmd_create_vport_lag(mdev);
4775 if (err)
4776 return err;
4777
4778 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4779 if (IS_ERR(ft)) {
4780 err = PTR_ERR(ft);
4781 goto err_destroy_vport_lag;
4782 }
4783
9a4ca38d 4784 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4785 return 0;
4786
4787err_destroy_vport_lag:
4788 mlx5_cmd_destroy_vport_lag(mdev);
4789 return err;
4790}
4791
45f95acd 4792static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4793{
4794 struct mlx5_core_dev *mdev = dev->mdev;
4795
9a4ca38d
MB		 4796 if (dev->flow_db->lag_demux_ft) {
4797 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4798 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4799
4800 mlx5_cmd_destroy_vport_lag(mdev);
4801 }
4802}
4803
7fd8aefb 4804static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4805{
4806 int err;
4807
7fd8aefb
DJ		 4808 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4809 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4810 if (err) {
7fd8aefb 4811 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4812 return err;
4813 }
4814
4815 return 0;
4816}
4817
7fd8aefb 4818static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4819{
7fd8aefb
DJ		 4820 if (dev->roce[port_num].nb.notifier_call) {
4821 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4822 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4823 }
4824}
4825
e3f1ed1f 4826static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4827{
e53505a8
AS		 4828 int err;
4829
ca5b91d6
OG		 4830 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4831 err = mlx5_nic_vport_enable_roce(dev->mdev);
4832 if (err)
8e6efa3a 4833 return err;
ca5b91d6 4834 }
e53505a8 4835
45f95acd 4836 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4837 if (err)
4838 goto err_disable_roce;
4839
e53505a8
AS		 4840 return 0;
4841
9ef9c640 4842err_disable_roce:
ca5b91d6
OG		 4843 if (MLX5_CAP_GEN(dev->mdev, roce))
4844 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4845
e53505a8 4846 return err;
fc24fc5e
AS		 4847}
4848
45f95acd 4849static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4850{
45f95acd 4851 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4852 if (MLX5_CAP_GEN(dev->mdev, roce))
4853 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4854}
4855
e1f24a79 4856struct mlx5_ib_counter {
7c16f477
KH		 4857 const char *name;
4858 size_t offset;
4859};
4860
4861#define INIT_Q_COUNTER(_name) \
4862 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4863
e1f24a79 4864static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4865 INIT_Q_COUNTER(rx_write_requests),
4866 INIT_Q_COUNTER(rx_read_requests),
4867 INIT_Q_COUNTER(rx_atomic_requests),
4868 INIT_Q_COUNTER(out_of_buffer),
4869};
4870
e1f24a79 4871static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4872 INIT_Q_COUNTER(out_of_sequence),
4873};
4874
e1f24a79 4875static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4876 INIT_Q_COUNTER(duplicate_request),
4877 INIT_Q_COUNTER(rnr_nak_retry_err),
4878 INIT_Q_COUNTER(packet_seq_err),
4879 INIT_Q_COUNTER(implied_nak_seq_err),
4880 INIT_Q_COUNTER(local_ack_timeout_err),
4881};
4882
e1f24a79
PP		 4883#define INIT_CONG_COUNTER(_name) \
4884 { .name = #_name, .offset = \
4885 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4886
4887static const struct mlx5_ib_counter cong_cnts[] = {
4888 INIT_CONG_COUNTER(rp_cnp_ignored),
4889 INIT_CONG_COUNTER(rp_cnp_handled),
4890 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4891 INIT_CONG_COUNTER(np_cnp_sent),
4892};
4893
58dcb60a
PP		 4894static const struct mlx5_ib_counter extended_err_cnts[] = {
4895 INIT_Q_COUNTER(resp_local_length_error),
4896 INIT_Q_COUNTER(resp_cqe_error),
4897 INIT_Q_COUNTER(req_cqe_error),
4898 INIT_Q_COUNTER(req_remote_invalid_request),
4899 INIT_Q_COUNTER(req_remote_access_errors),
4900 INIT_Q_COUNTER(resp_remote_access_errors),
4901 INIT_Q_COUNTER(resp_cqe_flush_error),
4902 INIT_Q_COUNTER(req_cqe_flush_error),
4903};
4904
9f876f3d
TB		 4905#define INIT_EXT_PPCNT_COUNTER(_name) \
4906 { .name = #_name, .offset = \
4907 MLX5_BYTE_OFF(ppcnt_reg, \
4908 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4909
4910static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4911 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4912};
4913
e1f24a79 4914static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4915{
aac4492e 4916 int i;
0837e86a 4917
7c16f477 4918 for (i = 0; i < dev->num_ports; i++) {
921c0f5b 4919 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 4920 mlx5_core_dealloc_q_counter(dev->mdev,
4921 dev->port[i].cnts.set_id);
e1f24a79
PP		 4922 kfree(dev->port[i].cnts.names);
4923 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4924 }
4925}
4926
e1f24a79
PP		 4927static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4928 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4929{
4930 u32 num_counters;
4931
4932 num_counters = ARRAY_SIZE(basic_q_cnts);
4933
4934 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4935 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4936
4937 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4938 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4939
4940 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4941 num_counters += ARRAY_SIZE(extended_err_cnts);
4942
e1f24a79 4943 cnts->num_q_counters = num_counters;
7c16f477 4944
e1f24a79
PP		 4945 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4946 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4947 num_counters += ARRAY_SIZE(cong_cnts);
4948 }
9f876f3d
TB		 4949 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4950 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4951 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4952 }
e1f24a79
PP		 4953 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4954 if (!cnts->names)
7c16f477
KH		 4955 return -ENOMEM;
4956
e1f24a79
PP		 4957 cnts->offsets = kcalloc(num_counters,
4958 sizeof(cnts->offsets), GFP_KERNEL);
4959 if (!cnts->offsets)
7c16f477
KH		 4960 goto err_names;
4961
7c16f477
KH		 4962 return 0;
4963
4964err_names:
e1f24a79 4965 kfree(cnts->names);
aac4492e 4966 cnts->names = NULL;
7c16f477
KH		 4967 return -ENOMEM;
4968}
4969
e1f24a79
PP		 4970static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4971 const char **names,
4972 size_t *offsets)
7c16f477
KH		 4973{
4974 int i;
4975 int j = 0;
4976
4977 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4978 names[j] = basic_q_cnts[i].name;
4979 offsets[j] = basic_q_cnts[i].offset;
4980 }
4981
4982 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4983 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4984 names[j] = out_of_seq_q_cnts[i].name;
4985 offsets[j] = out_of_seq_q_cnts[i].offset;
4986 }
4987 }
4988
4989 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4990 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4991 names[j] = retrans_q_cnts[i].name;
4992 offsets[j] = retrans_q_cnts[i].offset;
4993 }
4994 }
e1f24a79 4995
58dcb60a
PP		 4996 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4997 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4998 names[j] = extended_err_cnts[i].name;
4999 offsets[j] = extended_err_cnts[i].offset;
5000 }
5001 }
5002
e1f24a79
PP		 5003 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5004 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5005 names[j] = cong_cnts[i].name;
5006 offsets[j] = cong_cnts[i].offset;
5007 }
5008 }
9f876f3d
TB		 5009
5010 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5011 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5012 names[j] = ext_ppcnt_cnts[i].name;
5013 offsets[j] = ext_ppcnt_cnts[i].offset;
5014 }
5015 }
0837e86a
MB		 5016}
5017
e1f24a79 5018static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5019{
aac4492e 5020 int err = 0;
0837e86a 5021 int i;
0837e86a
MB		 5022
5023 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 5024 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5025 if (err)
5026 goto err_alloc;
5027
5028 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5029 dev->port[i].cnts.offsets);
7c16f477 5030
aac4492e
DJ		 5031 err = mlx5_core_alloc_q_counter(dev->mdev,
5032 &dev->port[i].cnts.set_id);
5033 if (err) {
0837e86a
MB		 5034 mlx5_ib_warn(dev,
5035 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5036 i + 1, err);
5037 goto err_alloc;
0837e86a 5038 }
aac4492e 5039 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 5040 }
5041
5042 return 0;
5043
aac4492e
DJ		 5044err_alloc:
5045 mlx5_ib_dealloc_counters(dev);
5046 return err;
0837e86a
MB		 5047}
5048
0ad17a8f
MB		 5049static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5050 u8 port_num)
5051{
7c16f477
KH		 5052 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5053 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 5054
5055 /* We support only per port stats */
5056 if (port_num == 0)
5057 return NULL;
5058
e1f24a79
PP		 5059 return rdma_alloc_hw_stats_struct(port->cnts.names,
5060 port->cnts.num_q_counters +
9f876f3d
TB		 5061 port->cnts.num_cong_counters +
5062 port->cnts.num_ext_ppcnt_counters,
0ad17a8f
MB		 5063 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5064}
5065
aac4492e 5066static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 5067 struct mlx5_ib_port *port,
5068 struct rdma_hw_stats *stats)
0ad17a8f 5069{
0ad17a8f
MB		 5070 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5071 void *out;
5072 __be32 val;
e1f24a79 5073 int ret, i;
0ad17a8f 5074
1b9a07ee 5075 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5076 if (!out)
5077 return -ENOMEM;
5078
aac4492e 5079 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 5080 port->cnts.set_id, 0,
0ad17a8f
MB		 5081 out, outlen);
5082 if (ret)
5083 goto free;
5084
e1f24a79
PP		 5085 for (i = 0; i < port->cnts.num_q_counters; i++) {
5086 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 5087 stats->value[i] = (u64)be32_to_cpu(val);
5088 }
7c16f477 5089
0ad17a8f
MB		 5090free:
5091 kvfree(out);
e1f24a79
PP		 5092 return ret;
5093}
5094
9f876f3d
TB		 5095static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5096 struct mlx5_ib_port *port,
5097 struct rdma_hw_stats *stats)
5098{
5099 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5100 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5101 int ret, i;
5102 void *out;
5103
5104 out = kvzalloc(sz, GFP_KERNEL);
5105 if (!out)
5106 return -ENOMEM;
5107
5108 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5109 if (ret)
5110 goto free;
5111
5112 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5113 stats->value[i + offset] =
5114 be64_to_cpup((__be64 *)(out +
5115 port->cnts.offsets[i + offset]));
5116 }
5117
5118free:
5119 kvfree(out);
5120 return ret;
5121}
5122
e1f24a79
PP		 5123static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5124 struct rdma_hw_stats *stats,
5125 u8 port_num, int index)
5126{
5127 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5128 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 5129 struct mlx5_core_dev *mdev;
e1f24a79 5130 int ret, num_counters;
aac4492e 5131 u8 mdev_port_num;
e1f24a79
PP		 5132
5133 if (!stats)
5134 return -EINVAL;
5135
9f876f3d
TB		 5136 num_counters = port->cnts.num_q_counters +
5137 port->cnts.num_cong_counters +
5138 port->cnts.num_ext_ppcnt_counters;
aac4492e
DJ		 5139
5140 /* q_counters are per IB device, query the master mdev */
5141 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 5142 if (ret)
5143 return ret;
e1f24a79 5144
9f876f3d
TB		 5145 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5146 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5147 if (ret)
5148 return ret;
5149 }
5150
e1f24a79 5151 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5152 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5153 &mdev_port_num);
5154 if (!mdev) {
5155 /* If port is not affiliated yet, its in down state
5156 * which doesn't have any counters yet, so it would be
5157 * zero. So no need to read from the HCA.
5158 */
5159 goto done;
5160 }
71a0ff65
MD		 5161 ret = mlx5_lag_query_cong_counters(dev->mdev,
5162 stats->value +
5163 port->cnts.num_q_counters,
5164 port->cnts.num_cong_counters,
5165 port->cnts.offsets +
5166 port->cnts.num_q_counters);
aac4492e
DJ		 5167
5168 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5169 if (ret)
5170 return ret;
e1f24a79
PP		 5171 }
5172
aac4492e 5173done:
e1f24a79 5174 return num_counters;
0ad17a8f
MB		 5175}
5176
693dfd5a
ES		 5177static struct net_device*
5178mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
5179 u8 port_num,
5180 enum rdma_netdev_t type,
5181 const char *name,
5182 unsigned char name_assign_type,
5183 void (*setup)(struct net_device *))
5184{
8e959601 5185 struct net_device *netdev;
8e959601 5186
693dfd5a
ES		 5187 if (type != RDMA_NETDEV_IPOIB)
5188 return ERR_PTR(-EOPNOTSUPP);
5189
8e959601
NV		 5190 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
5191 name, setup);
8e959601 5192 return netdev;
693dfd5a
ES		 5193}
5194
fe248c3a
MG		 5195static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5196{
5197 if (!dev->delay_drop.dbg)
5198 return;
5199 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5200 kfree(dev->delay_drop.dbg);
5201 dev->delay_drop.dbg = NULL;
5202}
5203
03404e8a
MG		 5204static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5205{
5206 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5207 return;
5208
5209 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5210 delay_drop_debugfs_cleanup(dev);
5211}
5212
5213static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5214 size_t count, loff_t *pos)
5215{
5216 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5217 char lbuf[20];
5218 int len;
5219
5220 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5221 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5222}
5223
5224static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5225 size_t count, loff_t *pos)
5226{
5227 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5228 u32 timeout;
5229 u32 var;
5230
5231 if (kstrtouint_from_user(buf, count, 0, &var))
5232 return -EFAULT;
5233
5234 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5235 1000);
5236 if (timeout != var)
5237 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5238 timeout);
5239
5240 delay_drop->timeout = timeout;
5241
5242 return count;
5243}
5244
5245static const struct file_operations fops_delay_drop_timeout = {
5246 .owner = THIS_MODULE,
5247 .open = simple_open,
5248 .write = delay_drop_timeout_write,
5249 .read = delay_drop_timeout_read,
5250};
5251
5252static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5253{
5254 struct mlx5_ib_dbg_delay_drop *dbg;
5255
5256 if (!mlx5_debugfs_root)
5257 return 0;
5258
5259 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5260 if (!dbg)
5261 return -ENOMEM;
5262
cbafad87
SM		 5263 dev->delay_drop.dbg = dbg;
5264
fe248c3a
MG		 5265 dbg->dir_debugfs =
5266 debugfs_create_dir("delay_drop",
5267 dev->mdev->priv.dbg_root);
5268 if (!dbg->dir_debugfs)
cbafad87 5269 goto out_debugfs;
fe248c3a
MG		 5270
5271 dbg->events_cnt_debugfs =
5272 debugfs_create_atomic_t("num_timeout_events", 0400,
5273 dbg->dir_debugfs,
5274 &dev->delay_drop.events_cnt);
5275 if (!dbg->events_cnt_debugfs)
5276 goto out_debugfs;
5277
5278 dbg->rqs_cnt_debugfs =
5279 debugfs_create_atomic_t("num_rqs", 0400,
5280 dbg->dir_debugfs,
5281 &dev->delay_drop.rqs_cnt);
5282 if (!dbg->rqs_cnt_debugfs)
5283 goto out_debugfs;
5284
5285 dbg->timeout_debugfs =
5286 debugfs_create_file("timeout", 0600,
5287 dbg->dir_debugfs,
5288 &dev->delay_drop,
5289 &fops_delay_drop_timeout);
5290 if (!dbg->timeout_debugfs)
5291 goto out_debugfs;
5292
5293 return 0;
5294
5295out_debugfs:
5296 delay_drop_debugfs_cleanup(dev);
5297 return -ENOMEM;
03404e8a
MG		 5298}
5299
5300static void init_delay_drop(struct mlx5_ib_dev *dev)
5301{
5302 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5303 return;
5304
5305 mutex_init(&dev->delay_drop.lock);
5306 dev->delay_drop.dev = dev;
5307 dev->delay_drop.activate = false;
5308 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5309 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5310 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5311 atomic_set(&dev->delay_drop.events_cnt, 0);
5312
5313 if (delay_drop_debugfs_init(dev))
5314 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5315}
5316
84305d71
LR		 5317static const struct cpumask *
5318mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 5319{
5320 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5321
6082d9c9 5322 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
40b24403
SG		 5323}
5324
32f69e4b
DJ		 5325/* The mlx5_ib_multiport_mutex should be held when calling this function */
5326static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5327 struct mlx5_ib_multiport_info *mpi)
5328{
5329 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5330 struct mlx5_ib_port *port = &ibdev->port[port_num];
5331 int comps;
5332 int err;
5333 int i;
5334
a9e546e7
PP		 5335 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5336
32f69e4b
DJ		 5337 spin_lock(&port->mp.mpi_lock);
5338 if (!mpi->ibdev) {
5339 spin_unlock(&port->mp.mpi_lock);
5340 return;
5341 }
5342 mpi->ibdev = NULL;
5343
5344 spin_unlock(&port->mp.mpi_lock);
5345 mlx5_remove_netdev_notifier(ibdev, port_num);
5346 spin_lock(&port->mp.mpi_lock);
5347
5348 comps = mpi->mdev_refcnt;
5349 if (comps) {
5350 mpi->unaffiliate = true;
5351 init_completion(&mpi->unref_comp);
5352 spin_unlock(&port->mp.mpi_lock);
5353
5354 for (i = 0; i < comps; i++)
5355 wait_for_completion(&mpi->unref_comp);
5356
5357 spin_lock(&port->mp.mpi_lock);
5358 mpi->unaffiliate = false;
5359 }
5360
5361 port->mp.mpi = NULL;
5362
5363 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5364
5365 spin_unlock(&port->mp.mpi_lock);
5366
5367 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5368
5369 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5370 /* Log an error, still needed to cleanup the pointers and add
5371 * it back to the list.
5372 */
5373 if (err)
5374 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5375 port_num + 1);
5376
5377 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5378}
5379
5380/* The mlx5_ib_multiport_mutex should be held when calling this function */
5381static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5382 struct mlx5_ib_multiport_info *mpi)
5383{
5384 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5385 int err;
5386
5387 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5388 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5389 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5390 port_num + 1);
32f69e4b
DJ		 5391 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5392 return false;
5393 }
5394
5395 ibdev->port[port_num].mp.mpi = mpi;
5396 mpi->ibdev = ibdev;
5397 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5398
5399 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5400 if (err)
5401 goto unbind;
5402
5403 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5404 if (err)
5405 goto unbind;
5406
5407 err = mlx5_add_netdev_notifier(ibdev, port_num);
5408 if (err) {
5409 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5410 port_num + 1);
5411 goto unbind;
5412 }
5413
a9e546e7
PP		 5414 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5415 if (err)
5416 goto unbind;
5417
32f69e4b
DJ		 5418 return true;
5419
5420unbind:
5421 mlx5_ib_unbind_slave_port(ibdev, mpi);
5422 return false;
5423}
5424
5425static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5426{
5427 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5428 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5429 port_num + 1);
5430 struct mlx5_ib_multiport_info *mpi;
5431 int err;
5432 int i;
5433
5434 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5435 return 0;
5436
5437 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5438 &dev->sys_image_guid);
5439 if (err)
5440 return err;
5441
5442 err = mlx5_nic_vport_enable_roce(dev->mdev);
5443 if (err)
5444 return err;
5445
5446 mutex_lock(&mlx5_ib_multiport_mutex);
5447 for (i = 0; i < dev->num_ports; i++) {
5448 bool bound = false;
5449
5450 /* build a stub multiport info struct for the native port. */
5451 if (i == port_num) {
5452 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5453 if (!mpi) {
5454 mutex_unlock(&mlx5_ib_multiport_mutex);
5455 mlx5_nic_vport_disable_roce(dev->mdev);
5456 return -ENOMEM;
5457 }
5458
5459 mpi->is_master = true;
5460 mpi->mdev = dev->mdev;
5461 mpi->sys_image_guid = dev->sys_image_guid;
5462 dev->port[i].mp.mpi = mpi;
5463 mpi->ibdev = dev;
5464 mpi = NULL;
5465 continue;
5466 }
5467
5468 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5469 list) {
5470 if (dev->sys_image_guid == mpi->sys_image_guid &&
5471 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5472 bound = mlx5_ib_bind_slave_port(dev, mpi);
5473 }
5474
5475 if (bound) {
5476 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5477 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5478 list_del(&mpi->list);
5479 break;
5480 }
5481 }
5482 if (!bound) {
5483 get_port_caps(dev, i + 1);
5484 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5485 i + 1);
5486 }
5487 }
5488
5489 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5490 mutex_unlock(&mlx5_ib_multiport_mutex);
5491 return err;
5492}
5493
5494static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5495{
5496 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5497 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5498 port_num + 1);
5499 int i;
5500
5501 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5502 return;
5503
5504 mutex_lock(&mlx5_ib_multiport_mutex);
5505 for (i = 0; i < dev->num_ports; i++) {
5506 if (dev->port[i].mp.mpi) {
5507 /* Destroy the native port stub */
5508 if (i == port_num) {
5509 kfree(dev->port[i].mp.mpi);
5510 dev->port[i].mp.mpi = NULL;
5511 } else {
5512 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5513 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5514 }
5515 }
5516 }
5517
5518 mlx5_ib_dbg(dev, "removing from devlist\n");
5519 list_del(&dev->ib_dev_list);
5520 mutex_unlock(&mlx5_ib_multiport_mutex);
5521
5522 mlx5_nic_vport_disable_roce(dev->mdev);
5523}
5524
9a119cd5
JG		 5525ADD_UVERBS_ATTRIBUTES_SIMPLE(
5526 mlx5_ib_dm,
5527 UVERBS_OBJECT_DM,
5528 UVERBS_METHOD_DM_ALLOC,
5529 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5530 UVERBS_ATTR_TYPE(u64),
83bb4442 5531 UA_MANDATORY),
9a119cd5
JG		 5532 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5533 UVERBS_ATTR_TYPE(u16),
83bb4442 5534 UA_MANDATORY));
9a119cd5
JG		 5535
5536ADD_UVERBS_ATTRIBUTES_SIMPLE(
5537 mlx5_ib_flow_action,
5538 UVERBS_OBJECT_FLOW_ACTION,
5539 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 5540 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5541 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 5542
8c84660b
MB		 5543static int populate_specs_root(struct mlx5_ib_dev *dev)
5544{
7d96c9b1
JG		 5545 const struct uverbs_object_tree_def **trees = dev->driver_trees;
5546 size_t num_trees = 0;
8c84660b 5547
7d96c9b1
JG		 5548 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5549 MLX5_ACCEL_IPSEC_CAP_DEVICE)
5550 trees[num_trees++] = &mlx5_ib_flow_action;
c6475a0b 5551
7d96c9b1
JG		 5552 if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5553 trees[num_trees++] = &mlx5_ib_dm;
24da0016 5554
c59450c4 5555 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
7d96c9b1
JG		 5556 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5557 trees[num_trees++] = mlx5_ib_get_devx_tree();
c59450c4 5558
7d96c9b1 5559 num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
cb80fb18 5560
7d96c9b1
JG		 5561 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5562 trees[num_trees] = NULL;
5563 dev->ib_dev.driver_specs = trees;
8c84660b 5564
7d96c9b1 5565 return 0;
8c84660b
MB		 5566}
5567
1a1e03dc
RS		 5568static int mlx5_ib_read_counters(struct ib_counters *counters,
5569 struct ib_counters_read_attr *read_attr,
5570 struct uverbs_attr_bundle *attrs)
5571{
5572 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5573 struct mlx5_read_counters_attr mread_attr = {};
5574 struct mlx5_ib_flow_counters_desc *desc;
5575 int ret, i;
5576
5577 mutex_lock(&mcounters->mcntrs_mutex);
5578 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5579 ret = -EINVAL;
5580 goto err_bound;
5581 }
5582
5583 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5584 GFP_KERNEL);
5585 if (!mread_attr.out) {
5586 ret = -ENOMEM;
5587 goto err_bound;
5588 }
5589
5590 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5591 mread_attr.flags = read_attr->flags;
5592 ret = mcounters->read_counters(counters->device, &mread_attr);
5593 if (ret)
5594 goto err_read;
5595
5596 /* do the pass over the counters data array to assign according to the
5597 * descriptions and indexing pairs
5598 */
5599 desc = mcounters->counters_data;
5600 for (i = 0; i < mcounters->ncounters; i++)
5601 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5602
5603err_read:
5604 kfree(mread_attr.out);
5605err_bound:
5606 mutex_unlock(&mcounters->mcntrs_mutex);
5607 return ret;
5608}
5609
b29e2a13
RS		 5610static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5611{
5612 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5613
3b3233fb
RS		 5614 counters_clear_description(counters);
5615 if (mcounters->hw_cntrs_hndl)
5616 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5617 mcounters->hw_cntrs_hndl);
5618
b29e2a13
RS		 5619 kfree(mcounters);
5620
5621 return 0;
5622}
5623
5624static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5625 struct uverbs_attr_bundle *attrs)
5626{
5627 struct mlx5_ib_mcounters *mcounters;
5628
5629 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5630 if (!mcounters)
5631 return ERR_PTR(-ENOMEM);
5632
3b3233fb
RS		 5633 mutex_init(&mcounters->mcntrs_mutex);
5634
b29e2a13
RS		 5635 return &mcounters->ibcntrs;
5636}
5637
b5ca15ad 5638void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5639{
32f69e4b 5640 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 5641#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5642 cleanup_srcu_struct(&dev->mr_srcu);
5643#endif
16c1975f
MB		 5644 kfree(dev->port);
5645}
5646
b5ca15ad 5647int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5648{
5649 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 5650 const char *name;
e126ba97 5651 int err;
32f69e4b 5652 int i;
e126ba97 5653
508562d6 5654 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5655 GFP_KERNEL);
5656 if (!dev->port)
16c1975f 5657 return -ENOMEM;
0837e86a 5658
32f69e4b
DJ		 5659 for (i = 0; i < dev->num_ports; i++) {
5660 spin_lock_init(&dev->port[i].mp.mpi_lock);
5661 rwlock_init(&dev->roce[i].netdev_lock);
5662 }
5663
5664 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5665 if (err)
0837e86a 5666 goto err_free_port;
e126ba97 5667
32f69e4b 5668 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5669 for (i = 1; i <= dev->num_ports; i++) {
5670 err = get_port_caps(dev, i);
5671 if (err)
5672 break;
5673 }
5674 } else {
5675 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5676 }
5677 if (err)
5678 goto err_mp;
5679
1b5daf11
MD		 5680 if (mlx5_use_mad_ifc(dev))
5681 get_ext_port_caps(dev);
e126ba97 5682
4babcf97
AH		 5683 if (!mlx5_lag_is_active(mdev))
5684 name = "mlx5_%d";
5685 else
5686 name = "mlx5_bond_%d";
5687
5688 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 5689 dev->ib_dev.owner = THIS_MODULE;
5690 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5691 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5692 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 5693 dev->ib_dev.num_comp_vectors =
5694 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 5695 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5696
3cc297db
MB		 5697 mutex_init(&dev->cap_mask_mutex);
5698 INIT_LIST_HEAD(&dev->qp_list);
5699 spin_lock_init(&dev->reset_flow_resource_lock);
5700
24da0016
AL		 5701 spin_lock_init(&dev->memic.memic_lock);
5702 dev->memic.dev = mdev;
5703
3cc297db
MB		 5704#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5705 err = init_srcu_struct(&dev->mr_srcu);
5706 if (err)
5707 goto err_free_port;
5708#endif
5709
16c1975f 5710 return 0;
32f69e4b
DJ		 5711err_mp:
5712 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5713
5714err_free_port:
5715 kfree(dev->port);
5716
5717 return -ENOMEM;
5718}
5719
9a4ca38d
MB		 5720static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5721{
5722 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5723
5724 if (!dev->flow_db)
5725 return -ENOMEM;
5726
5727 mutex_init(&dev->flow_db->lock);
5728
5729 return 0;
5730}
5731
b5ca15ad
MB		 5732int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5733{
5734 struct mlx5_ib_dev *nic_dev;
5735
5736 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5737
5738 if (!nic_dev)
5739 return -EINVAL;
5740
5741 dev->flow_db = nic_dev->flow_db;
5742
5743 return 0;
5744}
5745
9a4ca38d
MB		 5746static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5747{
5748 kfree(dev->flow_db);
5749}
5750
b5ca15ad 5751int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5752{
5753 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5754 int err;
5755
e126ba97
EC		 5756 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5757 dev->ib_dev.uverbs_cmd_mask =
5758 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5759 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5760 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5761 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5762 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5763 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5764 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5765 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5766 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5767 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5768 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5769 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5770 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5771 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5772 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5773 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5774 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5775 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5776 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5777 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5778 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5779 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5780 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5781 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5782 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5783 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5784 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5785 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5786 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5787 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5788 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5789 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5790
5791 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5792 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5793 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5794 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5795 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5796 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5797 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5798 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5799 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5800 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5801 dev->ib_dev.mmap = mlx5_ib_mmap;
5802 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5803 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5804 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5805 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5806 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5807 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5808 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5809 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5810 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5811 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5812 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5813 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5814 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5815 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
d0e84c0a
YH		 5816 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5817 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
e126ba97
EC		 5818 dev->ib_dev.post_send = mlx5_ib_post_send;
5819 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5820 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5821 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5822 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5823 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5824 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5825 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5826 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5827 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5828 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5829 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5830 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5831 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5832 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5833 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5834 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5835 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5836 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5837 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5838 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5839 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5840
eff901d3
EC		 5841 if (mlx5_core_is_pf(mdev)) {
5842 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5843 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5844 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5845 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5846 }
e126ba97 5847
7c2344c3
MG		 5848 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5849
6e8484c5
MG		 5850 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5851
d2370e0a
MB		 5852 if (MLX5_CAP_GEN(mdev, imaicl)) {
5853 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5854 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5855 dev->ib_dev.uverbs_cmd_mask |=
5856 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5857 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5858 }
5859
938fe83c 5860 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5861 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5862 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5863 dev->ib_dev.uverbs_cmd_mask |=
5864 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5865 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5866 }
5867
24da0016
AL		 5868 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5869 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5870 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
6c29f57e 5871 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
24da0016
AL		 5872 }
5873
81e30880
YH		 5874 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5875 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5876 dev->ib_dev.uverbs_ex_cmd_mask |=
5877 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5878 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5879 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5880 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5881 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5882 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
b29e2a13
RS		 5883 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5884 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
1a1e03dc 5885 dev->ib_dev.read_counters = mlx5_ib_read_counters;
81e30880 5886
e126ba97
EC		 5887 err = init_node_data(dev);
5888 if (err)
16c1975f 5889 return err;
e126ba97 5890
c8b89924 5891 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5892 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5893 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 5894 mutex_init(&dev->lb_mutex);
5895
16c1975f
MB		 5896 return 0;
5897}
5898
8e6efa3a
MB		 5899static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5900{
5901 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5902 dev->ib_dev.query_port = mlx5_ib_query_port;
5903
5904 return 0;
5905}
5906
b5ca15ad 5907int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5908{
5909 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5910 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5911
5912 return 0;
5913}
5914
e3f1ed1f 5915static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 5916{
e3f1ed1f 5917 u8 port_num;
8e6efa3a
MB		 5918 int i;
5919
5920 for (i = 0; i < dev->num_ports; i++) {
5921 dev->roce[i].dev = dev;
5922 dev->roce[i].native_port_num = i + 1;
5923 dev->roce[i].last_port_state = IB_PORT_DOWN;
5924 }
5925
5926 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5927 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5928 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5929 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5930 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5931 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5932
5933 dev->ib_dev.uverbs_ex_cmd_mask |=
5934 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5935 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5936 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5937 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5938 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5939
e3f1ed1f
LR		 5940 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5941
8e6efa3a
MB		 5942 return mlx5_add_netdev_notifier(dev, port_num);
5943}
5944
5945static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5946{
5947 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5948
5949 mlx5_remove_netdev_notifier(dev, port_num);
5950}
5951
5952int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5953{
5954 struct mlx5_core_dev *mdev = dev->mdev;
5955 enum rdma_link_layer ll;
5956 int port_type_cap;
5957 int err = 0;
8e6efa3a 5958
8e6efa3a
MB		 5959 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5960 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5961
5962 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 5963 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5964
5965 return err;
5966}
5967
5968void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5969{
5970 mlx5_ib_stage_common_roce_cleanup(dev);
5971}
5972
16c1975f
MB		 5973static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5974{
5975 struct mlx5_core_dev *mdev = dev->mdev;
5976 enum rdma_link_layer ll;
5977 int port_type_cap;
5978 int err;
5979
5980 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5981 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5982
fc24fc5e 5983 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 5984 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 5985 if (err)
5986 return err;
7fd8aefb 5987
e3f1ed1f 5988 err = mlx5_enable_eth(dev);
fc24fc5e 5989 if (err)
8e6efa3a 5990 goto cleanup;
fc24fc5e
AS		 5991 }
5992
16c1975f 5993 return 0;
8e6efa3a
MB		 5994cleanup:
5995 mlx5_ib_stage_common_roce_cleanup(dev);
5996
5997 return err;
16c1975f 5998}
e126ba97 5999
16c1975f
MB		 6000static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6001{
6002 struct mlx5_core_dev *mdev = dev->mdev;
6003 enum rdma_link_layer ll;
6004 int port_type_cap;
e126ba97 6005
16c1975f
MB		 6006 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6007 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6008
6009 if (ll == IB_LINK_LAYER_ETHERNET) {
6010 mlx5_disable_eth(dev);
8e6efa3a 6011 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6012 }
16c1975f 6013}
6aec21f6 6014
b5ca15ad 6015int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6016{
6017 return create_dev_resources(&dev->devr);
6018}
6019
b5ca15ad 6020void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6021{
6022 destroy_dev_resources(&dev->devr);
6023}
6024
6025static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6026{
07321b3c
MB		 6027 mlx5_ib_internal_fill_odp_caps(dev);
6028
16c1975f
MB		 6029 return mlx5_ib_odp_init_one(dev);
6030}
4a2da0b8 6031
b5ca15ad 6032int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6033{
5e1e7612
MB		 6034 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6035 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
6036 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
6037
6038 return mlx5_ib_alloc_counters(dev);
6039 }
16c1975f
MB		 6040
6041 return 0;
6042}
6043
b5ca15ad 6044void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6045{
6046 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6047 mlx5_ib_dealloc_counters(dev);
6048}
6049
6050static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6051{
a9e546e7
PP		 6052 return mlx5_ib_init_cong_debugfs(dev,
6053 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6054}
6055
6056static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6057{
a9e546e7
PP		 6058 mlx5_ib_cleanup_cong_debugfs(dev,
6059 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6060}
6061
6062static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6063{
5fe9dec0 6064 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6065 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6066}
6067
6068static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6069{
6070 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6071}
6072
b5ca15ad 6073int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6074{
6075 int err;
5fe9dec0
EC		 6076
6077 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6078 if (err)
16c1975f 6079 return err;
5fe9dec0
EC		 6080
6081 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6082 if (err)
16c1975f 6083 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6084
16c1975f
MB		 6085 return err;
6086}
0837e86a 6087
b5ca15ad 6088void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6089{
6090 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6091 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6092}
e126ba97 6093
8c84660b
MB		 6094static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6095{
6096 return populate_specs_root(dev);
6097}
6098
b5ca15ad 6099int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6100{
6101 return ib_register_device(&dev->ib_dev, NULL);
6102}
6103
03fe2deb 6104void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6105{
42cea83f 6106 destroy_umrc_res(dev);
16c1975f
MB		 6107}
6108
03fe2deb 6109void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6110{
42cea83f 6111 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6112}
6113
03fe2deb 6114int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6115{
42cea83f 6116 return create_umr_res(dev);
16c1975f
MB		 6117}
6118
6119static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6120{
03404e8a
MG		 6121 init_delay_drop(dev);
6122
16c1975f
MB		 6123 return 0;
6124}
6125
6126static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6127{
6128 cancel_delay_drop(dev);
6129}
6130
b5ca15ad 6131int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6132{
6133 int err;
6134 int i;
6135
e126ba97 6136 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 6137 err = device_create_file(&dev->ib_dev.dev,
6138 mlx5_class_attributes[i]);
6139 if (err)
16c1975f 6140 return err;
e126ba97
EC		 6141 }
6142
16c1975f
MB		 6143 return 0;
6144}
6145
fc385b7a
MB		 6146static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6147{
6148 mlx5_ib_register_vport_reps(dev);
6149
6150 return 0;
6151}
6152
6153static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6154{
6155 mlx5_ib_unregister_vport_reps(dev);
6156}
6157
b5ca15ad
MB		 6158void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6159 const struct mlx5_ib_profile *profile,
6160 int stage)
16c1975f
MB		 6161{
6162 /* Number of stages to cleanup */
6163 while (stage) {
6164 stage--;
6165 if (profile->stage[stage].cleanup)
6166 profile->stage[stage].cleanup(dev);
6167 }
e126ba97 6168
16c1975f
MB		 6169 ib_dealloc_device((struct ib_device *)dev);
6170}
e126ba97 6171
b5ca15ad
MB		 6172void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6173 const struct mlx5_ib_profile *profile)
16c1975f 6174{
16c1975f
MB		 6175 int err;
6176 int i;
e126ba97 6177
16c1975f 6178 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 6179
16c1975f
MB		 6180 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6181 if (profile->stage[i].init) {
6182 err = profile->stage[i].init(dev);
6183 if (err)
6184 goto err_out;
6185 }
6186 }
0837e86a 6187
16c1975f
MB		 6188 dev->profile = profile;
6189 dev->ib_active = true;
6aec21f6 6190
16c1975f 6191 return dev;
e126ba97 6192
16c1975f
MB		 6193err_out:
6194 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6195
16c1975f
MB		 6196 return NULL;
6197}
0837e86a 6198
16c1975f
MB		 6199static const struct mlx5_ib_profile pf_profile = {
6200 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6201 mlx5_ib_stage_init_init,
6202 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6203 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6204 mlx5_ib_stage_flow_db_init,
6205 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6206 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6207 mlx5_ib_stage_caps_init,
6208 NULL),
8e6efa3a
MB		 6209 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6210 mlx5_ib_stage_non_default_cb,
6211 NULL),
16c1975f
MB		 6212 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6213 mlx5_ib_stage_roce_init,
6214 mlx5_ib_stage_roce_cleanup),
6215 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6216 mlx5_ib_stage_dev_res_init,
6217 mlx5_ib_stage_dev_res_cleanup),
6218 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6219 mlx5_ib_stage_odp_init,
3cc297db 6220 NULL),
16c1975f
MB		 6221 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6222 mlx5_ib_stage_counters_init,
6223 mlx5_ib_stage_counters_cleanup),
6224 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6225 mlx5_ib_stage_cong_debugfs_init,
6226 mlx5_ib_stage_cong_debugfs_cleanup),
6227 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6228 mlx5_ib_stage_uar_init,
6229 mlx5_ib_stage_uar_cleanup),
6230 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6231 mlx5_ib_stage_bfrag_init,
6232 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6233 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6234 NULL,
6235 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6236 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6237 mlx5_ib_stage_populate_specs,
7d96c9b1 6238 NULL),
16c1975f
MB		 6239 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6240 mlx5_ib_stage_ib_reg_init,
6241 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6242 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6243 mlx5_ib_stage_post_ib_reg_umr_init,
6244 NULL),
16c1975f
MB		 6245 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6246 mlx5_ib_stage_delay_drop_init,
6247 mlx5_ib_stage_delay_drop_cleanup),
6248 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6249 mlx5_ib_stage_class_attr_init,
6250 NULL),
16c1975f 6251};
e126ba97 6252
b5ca15ad
MB		 6253static const struct mlx5_ib_profile nic_rep_profile = {
6254 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6255 mlx5_ib_stage_init_init,
6256 mlx5_ib_stage_init_cleanup),
6257 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6258 mlx5_ib_stage_flow_db_init,
6259 mlx5_ib_stage_flow_db_cleanup),
6260 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6261 mlx5_ib_stage_caps_init,
6262 NULL),
6263 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6264 mlx5_ib_stage_rep_non_default_cb,
6265 NULL),
6266 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6267 mlx5_ib_stage_rep_roce_init,
6268 mlx5_ib_stage_rep_roce_cleanup),
6269 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6270 mlx5_ib_stage_dev_res_init,
6271 mlx5_ib_stage_dev_res_cleanup),
6272 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6273 mlx5_ib_stage_counters_init,
6274 mlx5_ib_stage_counters_cleanup),
6275 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6276 mlx5_ib_stage_uar_init,
6277 mlx5_ib_stage_uar_cleanup),
6278 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6279 mlx5_ib_stage_bfrag_init,
6280 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6281 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6282 NULL,
6283 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 6284 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6285 mlx5_ib_stage_populate_specs,
7d96c9b1 6286 NULL),
b5ca15ad
MB		 6287 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6288 mlx5_ib_stage_ib_reg_init,
6289 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6290 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6291 mlx5_ib_stage_post_ib_reg_umr_init,
6292 NULL),
b5ca15ad
MB		 6293 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6294 mlx5_ib_stage_class_attr_init,
6295 NULL),
6296 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6297 mlx5_ib_stage_rep_reg_init,
6298 mlx5_ib_stage_rep_reg_cleanup),
6299};
6300
e3f1ed1f 6301static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6302{
6303 struct mlx5_ib_multiport_info *mpi;
6304 struct mlx5_ib_dev *dev;
6305 bool bound = false;
6306 int err;
6307
6308 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6309 if (!mpi)
6310 return NULL;
6311
6312 mpi->mdev = mdev;
6313
6314 err = mlx5_query_nic_vport_system_image_guid(mdev,
6315 &mpi->sys_image_guid);
6316 if (err) {
6317 kfree(mpi);
6318 return NULL;
6319 }
6320
6321 mutex_lock(&mlx5_ib_multiport_mutex);
6322 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6323 if (dev->sys_image_guid == mpi->sys_image_guid)
6324 bound = mlx5_ib_bind_slave_port(dev, mpi);
6325
6326 if (bound) {
6327 rdma_roce_rescan_device(&dev->ib_dev);
6328 break;
6329 }
6330 }
6331
6332 if (!bound) {
6333 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6334 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6335 }
6336 mutex_unlock(&mlx5_ib_multiport_mutex);
6337
6338 return mpi;
6339}
6340
16c1975f
MB		 6341static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6342{
32f69e4b 6343 enum rdma_link_layer ll;
b5ca15ad 6344 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 6345 int port_type_cap;
6346
b5ca15ad
MB		 6347 printk_once(KERN_INFO "%s", mlx5_version);
6348
32f69e4b
DJ		 6349 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6350 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6351
e3f1ed1f
LR		 6352 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6353 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6354
b5ca15ad
MB		 6355 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6356 if (!dev)
6357 return NULL;
6358
6359 dev->mdev = mdev;
6360 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6361 MLX5_CAP_GEN(mdev, num_vhca_ports));
6362
aff2252a 6363 if (MLX5_ESWITCH_MANAGER(mdev) &&
b5ca15ad
MB		 6364 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6365 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6366
6367 return __mlx5_ib_add(dev, &nic_rep_profile);
6368 }
6369
6370 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6371}
6372
9603b61d 6373static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6374{
32f69e4b
DJ		 6375 struct mlx5_ib_multiport_info *mpi;
6376 struct mlx5_ib_dev *dev;
6377
6378 if (mlx5_core_is_mp_slave(mdev)) {
6379 mpi = context;
6380 mutex_lock(&mlx5_ib_multiport_mutex);
6381 if (mpi->ibdev)
6382 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6383 list_del(&mpi->list);
6384 mutex_unlock(&mlx5_ib_multiport_mutex);
6385 return;
6386 }
6aec21f6 6387
32f69e4b 6388 dev = context;
16c1975f 6389 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6390}
6391
9603b61d
JM		 6392static struct mlx5_interface mlx5_ib_interface = {
6393 .add = mlx5_ib_add,
6394 .remove = mlx5_ib_remove,
6395 .event = mlx5_ib_event,
d9aaed83
AK		 6396#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6397 .pfault = mlx5_ib_pfault,
6398#endif
64613d94 6399 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6400};
6401
c44ef998
IL		 6402unsigned long mlx5_ib_get_xlt_emergency_page(void)
6403{
6404 mutex_lock(&xlt_emergency_page_mutex);
6405 return xlt_emergency_page;
6406}
6407
6408void mlx5_ib_put_xlt_emergency_page(void)
6409{
6410 mutex_unlock(&xlt_emergency_page_mutex);
6411}
6412
e126ba97
EC		 6413static int __init mlx5_ib_init(void)
6414{
6aec21f6
HE		 6415 int err;
6416
c44ef998
IL		 6417 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6418 if (!xlt_emergency_page)
6419 return -ENOMEM;
6420
6421 mutex_init(&xlt_emergency_page_mutex);
6422
d69a24e0 6423 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6424 if (!mlx5_ib_event_wq) {
6425 free_page(xlt_emergency_page);
d69a24e0 6426 return -ENOMEM;
c44ef998 6427 }
d69a24e0 6428
81713d37 6429 mlx5_ib_odp_init();
9603b61d 6430
6aec21f6 6431 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 6432
6aec21f6 6433 return err;
e126ba97
EC		 6434}
6435
6436static void __exit mlx5_ib_cleanup(void)
6437{
9603b61d 6438 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 6439 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 6440 mutex_destroy(&xlt_emergency_page_mutex);
6441 free_page(xlt_emergency_page);
e126ba97
EC		 6442}
6443
6444module_init(mlx5_ib_init);
6445module_exit(mlx5_ib_cleanup);
Ubuntu Hirsute Linux kernel mirror