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IB/core: add support to create a unsafe global rkey to ib_create_pd
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
7c2344c3 45#include <linux/delay.h>
e126ba97 46#include <rdma/ib_user_verbs.h>
3f89a643 47#include <rdma/ib_addr.h>
2811ba51 48#include <rdma/ib_cache.h>
ada68c31 49#include <linux/mlx5/port.h>
1b5daf11 50#include <linux/mlx5/vport.h>
7c2344c3 51#include <linux/list.h>
e126ba97
EC		 52#include <rdma/ib_smi.h>
53#include <rdma/ib_umem.h>
038d2ef8
MG		 54#include <linux/in.h>
55#include <linux/etherdevice.h>
56#include <linux/mlx5/fs.h>
e126ba97
EC		 57#include "user.h"
58#include "mlx5_ib.h"
59
60#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 61#define DRIVER_VERSION "2.2-1"
62#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 63
64MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRIVER_VERSION);
68
9603b61d
JM		 69static int deprecated_prof_sel = 2;
70module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
71MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 72
73static char mlx5_version[] =
74 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
75 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
76
da7525d2
EBE		 77enum {
78 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
79};
80
1b5daf11 81static enum rdma_link_layer
ebd61f68 82mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 83{
ebd61f68 84 switch (port_type_cap) {
1b5daf11
MD		 85 case MLX5_CAP_PORT_TYPE_IB:
86 return IB_LINK_LAYER_INFINIBAND;
87 case MLX5_CAP_PORT_TYPE_ETH:
88 return IB_LINK_LAYER_ETHERNET;
89 default:
90 return IB_LINK_LAYER_UNSPECIFIED;
91 }
92}
93
ebd61f68
AS		 94static enum rdma_link_layer
95mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
96{
97 struct mlx5_ib_dev *dev = to_mdev(device);
98 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
99
100 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
101}
102
fc24fc5e
AS		 103static int mlx5_netdev_event(struct notifier_block *this,
104 unsigned long event, void *ptr)
105{
106 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
107 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
108 roce.nb);
109
110 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
111 return NOTIFY_DONE;
112
113 write_lock(&ibdev->roce.netdev_lock);
114 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
115 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
116 write_unlock(&ibdev->roce.netdev_lock);
117
118 return NOTIFY_DONE;
119}
120
121static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
122 u8 port_num)
123{
124 struct mlx5_ib_dev *ibdev = to_mdev(device);
125 struct net_device *ndev;
126
127 /* Ensure ndev does not disappear before we invoke dev_hold()
128 */
129 read_lock(&ibdev->roce.netdev_lock);
130 ndev = ibdev->roce.netdev;
131 if (ndev)
132 dev_hold(ndev);
133 read_unlock(&ibdev->roce.netdev_lock);
134
135 return ndev;
136}
137
3f89a643
AS		 138static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
139 struct ib_port_attr *props)
140{
141 struct mlx5_ib_dev *dev = to_mdev(device);
142 struct net_device *ndev;
143 enum ib_mtu ndev_ib_mtu;
c876a1b7 144 u16 qkey_viol_cntr;
3f89a643
AS		 145
146 memset(props, 0, sizeof(*props));
147
148 props->port_cap_flags |= IB_PORT_CM_SUP;
149 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
150
151 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
152 roce_address_table_size);
153 props->max_mtu = IB_MTU_4096;
154 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
155 props->pkey_tbl_len = 1;
156 props->state = IB_PORT_DOWN;
157 props->phys_state = 3;
158
c876a1b7
LR		 159 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
160 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 161
162 ndev = mlx5_ib_get_netdev(device, port_num);
163 if (!ndev)
164 return 0;
165
166 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
167 props->state = IB_PORT_ACTIVE;
168 props->phys_state = 5;
169 }
170
171 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
172
173 dev_put(ndev);
174
175 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
176
177 props->active_width = IB_WIDTH_4X; /* TODO */
178 props->active_speed = IB_SPEED_QDR; /* TODO */
179
180 return 0;
181}
182
3cca2606
AS		 183static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
184 const struct ib_gid_attr *attr,
185 void *mlx5_addr)
186{
187#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
188 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
189 source_l3_address);
190 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
191 source_mac_47_32);
192
193 if (!gid)
194 return;
195
196 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
197
198 if (is_vlan_dev(attr->ndev)) {
199 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
200 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
201 }
202
203 switch (attr->gid_type) {
204 case IB_GID_TYPE_IB:
205 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
206 break;
207 case IB_GID_TYPE_ROCE_UDP_ENCAP:
208 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
209 break;
210
211 default:
212 WARN_ON(true);
213 }
214
215 if (attr->gid_type != IB_GID_TYPE_IB) {
216 if (ipv6_addr_v4mapped((void *)gid))
217 MLX5_SET_RA(mlx5_addr, roce_l3_type,
218 MLX5_ROCE_L3_TYPE_IPV4);
219 else
220 MLX5_SET_RA(mlx5_addr, roce_l3_type,
221 MLX5_ROCE_L3_TYPE_IPV6);
222 }
223
224 if ((attr->gid_type == IB_GID_TYPE_IB) ||
225 !ipv6_addr_v4mapped((void *)gid))
226 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
227 else
228 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
229}
230
231static int set_roce_addr(struct ib_device *device, u8 port_num,
232 unsigned int index,
233 const union ib_gid *gid,
234 const struct ib_gid_attr *attr)
235{
c4f287c4
SM		 236 struct mlx5_ib_dev *dev = to_mdev(device);
237 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
238 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
3cca2606
AS		 239 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
240 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
241
242 if (ll != IB_LINK_LAYER_ETHERNET)
243 return -EINVAL;
244
3cca2606
AS		 245 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
246
247 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
248 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
3cca2606
AS		 249 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
250}
251
252static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
253 unsigned int index, const union ib_gid *gid,
254 const struct ib_gid_attr *attr,
255 __always_unused void **context)
256{
257 return set_roce_addr(device, port_num, index, gid, attr);
258}
259
260static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
261 unsigned int index, __always_unused void **context)
262{
263 return set_roce_addr(device, port_num, index, NULL, NULL);
264}
265
2811ba51
AS		 266__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
267 int index)
268{
269 struct ib_gid_attr attr;
270 union ib_gid gid;
271
272 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
273 return 0;
274
275 if (!attr.ndev)
276 return 0;
277
278 dev_put(attr.ndev);
279
280 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
281 return 0;
282
283 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
284}
285
1b5daf11
MD		 286static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
287{
d603c809 288 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
1b5daf11
MD		 289}
290
291enum {
292 MLX5_VPORT_ACCESS_METHOD_MAD,
293 MLX5_VPORT_ACCESS_METHOD_HCA,
294 MLX5_VPORT_ACCESS_METHOD_NIC,
295};
296
297static int mlx5_get_vport_access_method(struct ib_device *ibdev)
298{
299 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
300 return MLX5_VPORT_ACCESS_METHOD_MAD;
301
ebd61f68 302 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 303 IB_LINK_LAYER_ETHERNET)
304 return MLX5_VPORT_ACCESS_METHOD_NIC;
305
306 return MLX5_VPORT_ACCESS_METHOD_HCA;
307}
308
da7525d2
EBE		 309static void get_atomic_caps(struct mlx5_ib_dev *dev,
310 struct ib_device_attr *props)
311{
312 u8 tmp;
313 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
314 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
315 u8 atomic_req_8B_endianness_mode =
316 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
317
318 /* Check if HW supports 8 bytes standard atomic operations and capable
319 * of host endianness respond
320 */
321 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
322 if (((atomic_operations & tmp) == tmp) &&
323 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
324 (atomic_req_8B_endianness_mode)) {
325 props->atomic_cap = IB_ATOMIC_HCA;
326 } else {
327 props->atomic_cap = IB_ATOMIC_NONE;
328 }
329}
330
1b5daf11
MD		 331static int mlx5_query_system_image_guid(struct ib_device *ibdev,
332 __be64 *sys_image_guid)
333{
334 struct mlx5_ib_dev *dev = to_mdev(ibdev);
335 struct mlx5_core_dev *mdev = dev->mdev;
336 u64 tmp;
337 int err;
338
339 switch (mlx5_get_vport_access_method(ibdev)) {
340 case MLX5_VPORT_ACCESS_METHOD_MAD:
341 return mlx5_query_mad_ifc_system_image_guid(ibdev,
342 sys_image_guid);
343
344 case MLX5_VPORT_ACCESS_METHOD_HCA:
345 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 346 break;
347
348 case MLX5_VPORT_ACCESS_METHOD_NIC:
349 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
350 break;
1b5daf11
MD		 351
352 default:
353 return -EINVAL;
354 }
3f89a643
AS		 355
356 if (!err)
357 *sys_image_guid = cpu_to_be64(tmp);
358
359 return err;
360
1b5daf11
MD		 361}
362
363static int mlx5_query_max_pkeys(struct ib_device *ibdev,
364 u16 *max_pkeys)
365{
366 struct mlx5_ib_dev *dev = to_mdev(ibdev);
367 struct mlx5_core_dev *mdev = dev->mdev;
368
369 switch (mlx5_get_vport_access_method(ibdev)) {
370 case MLX5_VPORT_ACCESS_METHOD_MAD:
371 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
372
373 case MLX5_VPORT_ACCESS_METHOD_HCA:
374 case MLX5_VPORT_ACCESS_METHOD_NIC:
375 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
376 pkey_table_size));
377 return 0;
378
379 default:
380 return -EINVAL;
381 }
382}
383
384static int mlx5_query_vendor_id(struct ib_device *ibdev,
385 u32 *vendor_id)
386{
387 struct mlx5_ib_dev *dev = to_mdev(ibdev);
388
389 switch (mlx5_get_vport_access_method(ibdev)) {
390 case MLX5_VPORT_ACCESS_METHOD_MAD:
391 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
392
393 case MLX5_VPORT_ACCESS_METHOD_HCA:
394 case MLX5_VPORT_ACCESS_METHOD_NIC:
395 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
396
397 default:
398 return -EINVAL;
399 }
400}
401
402static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
403 __be64 *node_guid)
404{
405 u64 tmp;
406 int err;
407
408 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
409 case MLX5_VPORT_ACCESS_METHOD_MAD:
410 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
411
412 case MLX5_VPORT_ACCESS_METHOD_HCA:
413 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 414 break;
415
416 case MLX5_VPORT_ACCESS_METHOD_NIC:
417 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
418 break;
1b5daf11
MD		 419
420 default:
421 return -EINVAL;
422 }
3f89a643
AS		 423
424 if (!err)
425 *node_guid = cpu_to_be64(tmp);
426
427 return err;
1b5daf11
MD		 428}
429
430struct mlx5_reg_node_desc {
431 u8 desc[64];
432};
433
434static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
435{
436 struct mlx5_reg_node_desc in;
437
438 if (mlx5_use_mad_ifc(dev))
439 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
440
441 memset(&in, 0, sizeof(in));
442
443 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
444 sizeof(struct mlx5_reg_node_desc),
445 MLX5_REG_NODE_DESC, 0, 0);
446}
447
e126ba97 448static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 449 struct ib_device_attr *props,
450 struct ib_udata *uhw)
e126ba97
EC		 451{
452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 453 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 454 int err = -ENOMEM;
455 int max_rq_sg;
456 int max_sq_sg;
e0238a6a 457 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 458 struct mlx5_ib_query_device_resp resp = {};
459 size_t resp_len;
460 u64 max_tso;
e126ba97 461
402ca536
BW		 462 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
463 if (uhw->outlen && uhw->outlen < resp_len)
464 return -EINVAL;
465 else
466 resp.response_length = resp_len;
467
468 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 469 return -EINVAL;
470
1b5daf11
MD		 471 memset(props, 0, sizeof(*props));
472 err = mlx5_query_system_image_guid(ibdev,
473 &props->sys_image_guid);
474 if (err)
475 return err;
e126ba97 476
1b5daf11 477 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 478 if (err)
1b5daf11 479 return err;
e126ba97 480
1b5daf11
MD		 481 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
482 if (err)
483 return err;
e126ba97 484
9603b61d
JM		 485 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
486 (fw_rev_min(dev->mdev) << 16) |
487 fw_rev_sub(dev->mdev);
e126ba97
EC		 488 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
489 IB_DEVICE_PORT_ACTIVE_EVENT |
490 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 491 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 492
493 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 494 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 495 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 496 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 497 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 498 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 499 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 500 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 501 if (MLX5_CAP_GEN(mdev, imaicl)) {
502 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
503 IB_DEVICE_MEM_WINDOW_TYPE_2B;
504 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 505 /* We support 'Gappy' memory registration too */
506 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 507 }
e126ba97 508 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 509 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 510 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
511 /* At this stage no support for signature handover */
512 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
513 IB_PROT_T10DIF_TYPE_2 |
514 IB_PROT_T10DIF_TYPE_3;
515 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
516 IB_GUARD_T10DIF_CSUM;
517 }
938fe83c 518 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 519 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 520
402ca536
BW		 521 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
522 if (MLX5_CAP_ETH(mdev, csum_cap))
88115fe7
BW		 523 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
524
402ca536
BW		 525 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
526 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
527 if (max_tso) {
528 resp.tso_caps.max_tso = 1 << max_tso;
529 resp.tso_caps.supported_qpts |=
530 1 << IB_QPT_RAW_PACKET;
531 resp.response_length += sizeof(resp.tso_caps);
532 }
533 }
534 }
535
f0313965
ES		 536 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
537 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
538 props->device_cap_flags |= IB_DEVICE_UD_TSO;
539 }
540
cff5a0f3
MD		 541 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
542 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
543 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
544
da6d6ba3
MG		 545 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
546 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
547
1b5daf11
MD		 548 props->vendor_part_id = mdev->pdev->device;
549 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 550
551 props->max_mr_size = ~0ull;
e0238a6a 552 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 553 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
554 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
555 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
556 sizeof(struct mlx5_wqe_data_seg);
557 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
558 sizeof(struct mlx5_wqe_ctrl_seg)) /
559 sizeof(struct mlx5_wqe_data_seg);
e126ba97 560 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 561 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 562 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 563 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 564 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
565 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
566 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
567 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
568 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
569 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
570 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 571 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 572 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 573 props->max_fast_reg_page_list_len =
574 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 575 get_atomic_caps(dev, props);
81bea28f 576 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 577 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
578 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 579 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
580 props->max_mcast_grp;
581 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 582 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
583 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 584
8cdd312c 585#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 586 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 587 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
588 props->odp_caps = dev->odp_caps;
589#endif
590
051f2630
LR		 591 if (MLX5_CAP_GEN(mdev, cd))
592 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
593
eff901d3
EC		 594 if (!mlx5_core_is_pf(mdev))
595 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
596
402ca536
BW		 597 if (uhw->outlen) {
598 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
599
600 if (err)
601 return err;
602 }
603
1b5daf11 604 return 0;
e126ba97
EC		 605}
606
1b5daf11
MD		 607enum mlx5_ib_width {
608 MLX5_IB_WIDTH_1X = 1 << 0,
609 MLX5_IB_WIDTH_2X = 1 << 1,
610 MLX5_IB_WIDTH_4X = 1 << 2,
611 MLX5_IB_WIDTH_8X = 1 << 3,
612 MLX5_IB_WIDTH_12X = 1 << 4
613};
614
615static int translate_active_width(struct ib_device *ibdev, u8 active_width,
616 u8 *ib_width)
e126ba97
EC		 617{
618 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 619 int err = 0;
620
621 if (active_width & MLX5_IB_WIDTH_1X) {
622 *ib_width = IB_WIDTH_1X;
623 } else if (active_width & MLX5_IB_WIDTH_2X) {
624 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
625 (int)active_width);
626 err = -EINVAL;
627 } else if (active_width & MLX5_IB_WIDTH_4X) {
628 *ib_width = IB_WIDTH_4X;
629 } else if (active_width & MLX5_IB_WIDTH_8X) {
630 *ib_width = IB_WIDTH_8X;
631 } else if (active_width & MLX5_IB_WIDTH_12X) {
632 *ib_width = IB_WIDTH_12X;
633 } else {
634 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
635 (int)active_width);
636 err = -EINVAL;
e126ba97
EC		 637 }
638
1b5daf11
MD		 639 return err;
640}
e126ba97 641
1b5daf11
MD		 642static int mlx5_mtu_to_ib_mtu(int mtu)
643{
644 switch (mtu) {
645 case 256: return 1;
646 case 512: return 2;
647 case 1024: return 3;
648 case 2048: return 4;
649 case 4096: return 5;
650 default:
651 pr_warn("invalid mtu\n");
652 return -1;
e126ba97 653 }
1b5daf11 654}
e126ba97 655
1b5daf11
MD		 656enum ib_max_vl_num {
657 __IB_MAX_VL_0 = 1,
658 __IB_MAX_VL_0_1 = 2,
659 __IB_MAX_VL_0_3 = 3,
660 __IB_MAX_VL_0_7 = 4,
661 __IB_MAX_VL_0_14 = 5,
662};
e126ba97 663
1b5daf11
MD		 664enum mlx5_vl_hw_cap {
665 MLX5_VL_HW_0 = 1,
666 MLX5_VL_HW_0_1 = 2,
667 MLX5_VL_HW_0_2 = 3,
668 MLX5_VL_HW_0_3 = 4,
669 MLX5_VL_HW_0_4 = 5,
670 MLX5_VL_HW_0_5 = 6,
671 MLX5_VL_HW_0_6 = 7,
672 MLX5_VL_HW_0_7 = 8,
673 MLX5_VL_HW_0_14 = 15
674};
e126ba97 675
1b5daf11
MD		 676static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
677 u8 *max_vl_num)
678{
679 switch (vl_hw_cap) {
680 case MLX5_VL_HW_0:
681 *max_vl_num = __IB_MAX_VL_0;
682 break;
683 case MLX5_VL_HW_0_1:
684 *max_vl_num = __IB_MAX_VL_0_1;
685 break;
686 case MLX5_VL_HW_0_3:
687 *max_vl_num = __IB_MAX_VL_0_3;
688 break;
689 case MLX5_VL_HW_0_7:
690 *max_vl_num = __IB_MAX_VL_0_7;
691 break;
692 case MLX5_VL_HW_0_14:
693 *max_vl_num = __IB_MAX_VL_0_14;
694 break;
e126ba97 695
1b5daf11
MD		 696 default:
697 return -EINVAL;
e126ba97 698 }
e126ba97 699
1b5daf11 700 return 0;
e126ba97
EC		 701}
702
1b5daf11
MD		 703static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
704 struct ib_port_attr *props)
e126ba97 705{
1b5daf11
MD		 706 struct mlx5_ib_dev *dev = to_mdev(ibdev);
707 struct mlx5_core_dev *mdev = dev->mdev;
708 struct mlx5_hca_vport_context *rep;
046339ea
SM		 709 u16 max_mtu;
710 u16 oper_mtu;
1b5daf11
MD		 711 int err;
712 u8 ib_link_width_oper;
713 u8 vl_hw_cap;
e126ba97 714
1b5daf11
MD		 715 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
716 if (!rep) {
717 err = -ENOMEM;
e126ba97 718 goto out;
e126ba97 719 }
e126ba97 720
1b5daf11 721 memset(props, 0, sizeof(*props));
e126ba97 722
1b5daf11 723 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 724 if (err)
725 goto out;
726
1b5daf11
MD		 727 props->lid = rep->lid;
728 props->lmc = rep->lmc;
729 props->sm_lid = rep->sm_lid;
730 props->sm_sl = rep->sm_sl;
731 props->state = rep->vport_state;
732 props->phys_state = rep->port_physical_state;
733 props->port_cap_flags = rep->cap_mask1;
734 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
735 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
736 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
737 props->bad_pkey_cntr = rep->pkey_violation_counter;
738 props->qkey_viol_cntr = rep->qkey_violation_counter;
739 props->subnet_timeout = rep->subnet_timeout;
740 props->init_type_reply = rep->init_type_reply;
eff901d3 741 props->grh_required = rep->grh_required;
e126ba97 742
1b5daf11
MD		 743 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
744 if (err)
e126ba97 745 goto out;
e126ba97 746
1b5daf11
MD		 747 err = translate_active_width(ibdev, ib_link_width_oper,
748 &props->active_width);
749 if (err)
750 goto out;
d5beb7f2 751 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 752 if (err)
753 goto out;
754
facc9699 755 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 756
1b5daf11 757 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 758
facc9699 759 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 760
1b5daf11 761 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 762
1b5daf11
MD		 763 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
764 if (err)
765 goto out;
e126ba97 766
1b5daf11
MD		 767 err = translate_max_vl_num(ibdev, vl_hw_cap,
768 &props->max_vl_num);
e126ba97 769out:
1b5daf11 770 kfree(rep);
e126ba97
EC		 771 return err;
772}
773
1b5daf11
MD		 774int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
775 struct ib_port_attr *props)
e126ba97 776{
1b5daf11
MD		 777 switch (mlx5_get_vport_access_method(ibdev)) {
778 case MLX5_VPORT_ACCESS_METHOD_MAD:
779 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 780
1b5daf11
MD		 781 case MLX5_VPORT_ACCESS_METHOD_HCA:
782 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 783
3f89a643
AS		 784 case MLX5_VPORT_ACCESS_METHOD_NIC:
785 return mlx5_query_port_roce(ibdev, port, props);
786
1b5daf11
MD		 787 default:
788 return -EINVAL;
789 }
790}
e126ba97 791
1b5daf11
MD		 792static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
793 union ib_gid *gid)
794{
795 struct mlx5_ib_dev *dev = to_mdev(ibdev);
796 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 797
1b5daf11
MD		 798 switch (mlx5_get_vport_access_method(ibdev)) {
799 case MLX5_VPORT_ACCESS_METHOD_MAD:
800 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 801
1b5daf11
MD		 802 case MLX5_VPORT_ACCESS_METHOD_HCA:
803 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
804
805 default:
806 return -EINVAL;
807 }
e126ba97 808
e126ba97
EC		 809}
810
1b5daf11
MD		 811static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
812 u16 *pkey)
813{
814 struct mlx5_ib_dev *dev = to_mdev(ibdev);
815 struct mlx5_core_dev *mdev = dev->mdev;
816
817 switch (mlx5_get_vport_access_method(ibdev)) {
818 case MLX5_VPORT_ACCESS_METHOD_MAD:
819 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
820
821 case MLX5_VPORT_ACCESS_METHOD_HCA:
822 case MLX5_VPORT_ACCESS_METHOD_NIC:
823 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
824 pkey);
825 default:
826 return -EINVAL;
827 }
828}
e126ba97
EC		 829
830static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
831 struct ib_device_modify *props)
832{
833 struct mlx5_ib_dev *dev = to_mdev(ibdev);
834 struct mlx5_reg_node_desc in;
835 struct mlx5_reg_node_desc out;
836 int err;
837
838 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
839 return -EOPNOTSUPP;
840
841 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
842 return 0;
843
844 /*
845 * If possible, pass node desc to FW, so it can generate
846 * a 144 trap. If cmd fails, just ignore.
847 */
848 memcpy(&in, props->node_desc, 64);
9603b61d 849 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 850 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
851 if (err)
852 return err;
853
854 memcpy(ibdev->node_desc, props->node_desc, 64);
855
856 return err;
857}
858
859static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
860 struct ib_port_modify *props)
861{
862 struct mlx5_ib_dev *dev = to_mdev(ibdev);
863 struct ib_port_attr attr;
864 u32 tmp;
865 int err;
866
867 mutex_lock(&dev->cap_mask_mutex);
868
869 err = mlx5_ib_query_port(ibdev, port, &attr);
870 if (err)
871 goto out;
872
873 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
874 ~props->clr_port_cap_mask;
875
9603b61d 876 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 877
878out:
879 mutex_unlock(&dev->cap_mask_mutex);
880 return err;
881}
882
883static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
884 struct ib_udata *udata)
885{
886 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 887 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
888 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 889 struct mlx5_ib_ucontext *context;
890 struct mlx5_uuar_info *uuari;
891 struct mlx5_uar *uars;
c1be5232 892 int gross_uuars;
e126ba97 893 int num_uars;
78c0f98c 894 int ver;
e126ba97
EC		 895 int uuarn;
896 int err;
897 int i;
f241e749 898 size_t reqlen;
a168a41c
MD		 899 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
900 max_cqe_version);
e126ba97
EC		 901
902 if (!dev->ib_active)
903 return ERR_PTR(-EAGAIN);
904
dfbee859
HA		 905 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
906 return ERR_PTR(-EINVAL);
907
78c0f98c
EC		 908 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
909 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
910 ver = 0;
a168a41c 911 else if (reqlen >= min_req_v2)
78c0f98c
EC		 912 ver = 2;
913 else
914 return ERR_PTR(-EINVAL);
915
b368d7cb 916 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 917 if (err)
918 return ERR_PTR(err);
919
b368d7cb 920 if (req.flags)
78c0f98c
EC		 921 return ERR_PTR(-EINVAL);
922
e126ba97
EC		 923 if (req.total_num_uuars > MLX5_MAX_UUARS)
924 return ERR_PTR(-ENOMEM);
925
926 if (req.total_num_uuars == 0)
927 return ERR_PTR(-EINVAL);
928
f72300c5 929 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 930 return ERR_PTR(-EOPNOTSUPP);
931
932 if (reqlen > sizeof(req) &&
933 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 934 reqlen - sizeof(req)))
b368d7cb
MB		 935 return ERR_PTR(-EOPNOTSUPP);
936
c1be5232
EC		 937 req.total_num_uuars = ALIGN(req.total_num_uuars,
938 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 939 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
940 return ERR_PTR(-EINVAL);
941
c1be5232
EC		 942 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
943 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c 944 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 945 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
946 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
938fe83c
SM		 947 resp.cache_line_size = L1_CACHE_BYTES;
948 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
949 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
950 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
951 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
952 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 953 resp.cqe_version = min_t(__u8,
954 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
955 req.max_cqe_version);
b368d7cb
MB		 956 resp.response_length = min(offsetof(typeof(resp), response_length) +
957 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 958
959 context = kzalloc(sizeof(*context), GFP_KERNEL);
960 if (!context)
961 return ERR_PTR(-ENOMEM);
962
963 uuari = &context->uuari;
964 mutex_init(&uuari->lock);
965 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
966 if (!uars) {
967 err = -ENOMEM;
968 goto out_ctx;
969 }
970
c1be5232 971 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 972 sizeof(*uuari->bitmap),
973 GFP_KERNEL);
974 if (!uuari->bitmap) {
975 err = -ENOMEM;
976 goto out_uar_ctx;
977 }
978 /*
979 * clear all fast path uuars
980 */
c1be5232 981 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 982 uuarn = i & 3;
983 if (uuarn == 2 || uuarn == 3)
984 set_bit(i, uuari->bitmap);
985 }
986
c1be5232 987 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 988 if (!uuari->count) {
989 err = -ENOMEM;
990 goto out_bitmap;
991 }
992
993 for (i = 0; i < num_uars; i++) {
9603b61d 994 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 995 if (err)
996 goto out_count;
997 }
998
b4cfe447
HE		 999#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1000 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1001#endif
1002
146d2f1a 1003 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1004 err = mlx5_core_alloc_transport_domain(dev->mdev,
1005 &context->tdn);
1006 if (err)
1007 goto out_uars;
1008 }
1009
7c2344c3 1010 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1011 INIT_LIST_HEAD(&context->db_page_list);
1012 mutex_init(&context->db_page_mutex);
1013
1014 resp.tot_uuars = req.total_num_uuars;
938fe83c 1015 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1016
f72300c5
HA		 1017 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1018 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1019
402ca536
BW		 1020 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1021 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1022 resp.response_length += sizeof(resp.cmds_supp_uhw);
1023 }
1024
bc5c6eed
NO		 1025 /*
1026 * We don't want to expose information from the PCI bar that is located
1027 * after 4096 bytes, so if the arch only supports larger pages, let's
1028 * pretend we don't support reading the HCA's core clock. This is also
1029 * forced by mmap function.
1030 */
1031 if (PAGE_SIZE <= 4096 &&
1032 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
b368d7cb
MB		 1033 resp.comp_mask |=
1034 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1035 resp.hca_core_clock_offset =
1036 offsetof(struct mlx5_init_seg, internal_timer_h) %
1037 PAGE_SIZE;
f72300c5 1038 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1039 sizeof(resp.reserved2);
b368d7cb
MB		 1040 }
1041
1042 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1043 if (err)
146d2f1a 1044 goto out_td;
e126ba97 1045
78c0f98c 1046 uuari->ver = ver;
e126ba97
EC		 1047 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1048 uuari->uars = uars;
1049 uuari->num_uars = num_uars;
f72300c5
HA		 1050 context->cqe_version = resp.cqe_version;
1051
e126ba97
EC		 1052 return &context->ibucontext;
1053
146d2f1a 1054out_td:
1055 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1056 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1057
e126ba97
EC		 1058out_uars:
1059 for (i--; i >= 0; i--)
9603b61d 1060 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1061out_count:
1062 kfree(uuari->count);
1063
1064out_bitmap:
1065 kfree(uuari->bitmap);
1066
1067out_uar_ctx:
1068 kfree(uars);
1069
1070out_ctx:
1071 kfree(context);
1072 return ERR_PTR(err);
1073}
1074
1075static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1076{
1077 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1078 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1079 struct mlx5_uuar_info *uuari = &context->uuari;
1080 int i;
1081
146d2f1a 1082 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1083 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1084
e126ba97 1085 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1086 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1087 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1088 }
1089
1090 kfree(uuari->count);
1091 kfree(uuari->bitmap);
1092 kfree(uuari->uars);
1093 kfree(context);
1094
1095 return 0;
1096}
1097
1098static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1099{
9603b61d 1100 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1101}
1102
1103static int get_command(unsigned long offset)
1104{
1105 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1106}
1107
1108static int get_arg(unsigned long offset)
1109{
1110 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1111}
1112
1113static int get_index(unsigned long offset)
1114{
1115 return get_arg(offset);
1116}
1117
7c2344c3
MG		 1118static void mlx5_ib_vma_open(struct vm_area_struct *area)
1119{
1120 /* vma_open is called when a new VMA is created on top of our VMA. This
1121 * is done through either mremap flow or split_vma (usually due to
1122 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1123 * as this VMA is strongly hardware related. Therefore we set the
1124 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1125 * calling us again and trying to do incorrect actions. We assume that
1126 * the original VMA size is exactly a single page, and therefore all
1127 * "splitting" operation will not happen to it.
1128 */
1129 area->vm_ops = NULL;
1130}
1131
1132static void mlx5_ib_vma_close(struct vm_area_struct *area)
1133{
1134 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1135
1136 /* It's guaranteed that all VMAs opened on a FD are closed before the
1137 * file itself is closed, therefore no sync is needed with the regular
1138 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1139 * However need a sync with accessing the vma as part of
1140 * mlx5_ib_disassociate_ucontext.
1141 * The close operation is usually called under mm->mmap_sem except when
1142 * process is exiting.
1143 * The exiting case is handled explicitly as part of
1144 * mlx5_ib_disassociate_ucontext.
1145 */
1146 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1147
1148 /* setting the vma context pointer to null in the mlx5_ib driver's
1149 * private data, to protect a race condition in
1150 * mlx5_ib_disassociate_ucontext().
1151 */
1152 mlx5_ib_vma_priv_data->vma = NULL;
1153 list_del(&mlx5_ib_vma_priv_data->list);
1154 kfree(mlx5_ib_vma_priv_data);
1155}
1156
1157static const struct vm_operations_struct mlx5_ib_vm_ops = {
1158 .open = mlx5_ib_vma_open,
1159 .close = mlx5_ib_vma_close
1160};
1161
1162static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1163 struct mlx5_ib_ucontext *ctx)
1164{
1165 struct mlx5_ib_vma_private_data *vma_prv;
1166 struct list_head *vma_head = &ctx->vma_private_list;
1167
1168 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1169 if (!vma_prv)
1170 return -ENOMEM;
1171
1172 vma_prv->vma = vma;
1173 vma->vm_private_data = vma_prv;
1174 vma->vm_ops = &mlx5_ib_vm_ops;
1175
1176 list_add(&vma_prv->list, vma_head);
1177
1178 return 0;
1179}
1180
1181static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1182{
1183 int ret;
1184 struct vm_area_struct *vma;
1185 struct mlx5_ib_vma_private_data *vma_private, *n;
1186 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1187 struct task_struct *owning_process = NULL;
1188 struct mm_struct *owning_mm = NULL;
1189
1190 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1191 if (!owning_process)
1192 return;
1193
1194 owning_mm = get_task_mm(owning_process);
1195 if (!owning_mm) {
1196 pr_info("no mm, disassociate ucontext is pending task termination\n");
1197 while (1) {
1198 put_task_struct(owning_process);
1199 usleep_range(1000, 2000);
1200 owning_process = get_pid_task(ibcontext->tgid,
1201 PIDTYPE_PID);
1202 if (!owning_process ||
1203 owning_process->state == TASK_DEAD) {
1204 pr_info("disassociate ucontext done, task was terminated\n");
1205 /* in case task was dead need to release the
1206 * task struct.
1207 */
1208 if (owning_process)
1209 put_task_struct(owning_process);
1210 return;
1211 }
1212 }
1213 }
1214
1215 /* need to protect from a race on closing the vma as part of
1216 * mlx5_ib_vma_close.
1217 */
1218 down_read(&owning_mm->mmap_sem);
1219 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1220 list) {
1221 vma = vma_private->vma;
1222 ret = zap_vma_ptes(vma, vma->vm_start,
1223 PAGE_SIZE);
1224 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1225 /* context going to be destroyed, should
1226 * not access ops any more.
1227 */
1228 vma->vm_ops = NULL;
1229 list_del(&vma_private->list);
1230 kfree(vma_private);
1231 }
1232 up_read(&owning_mm->mmap_sem);
1233 mmput(owning_mm);
1234 put_task_struct(owning_process);
1235}
1236
37aa5c36
GL		 1237static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1238{
1239 switch (cmd) {
1240 case MLX5_IB_MMAP_WC_PAGE:
1241 return "WC";
1242 case MLX5_IB_MMAP_REGULAR_PAGE:
1243 return "best effort WC";
1244 case MLX5_IB_MMAP_NC_PAGE:
1245 return "NC";
1246 default:
1247 return NULL;
1248 }
1249}
1250
1251static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1252 struct vm_area_struct *vma,
1253 struct mlx5_ib_ucontext *context)
37aa5c36 1254{
7c2344c3 1255 struct mlx5_uuar_info *uuari = &context->uuari;
37aa5c36
GL		 1256 int err;
1257 unsigned long idx;
1258 phys_addr_t pfn, pa;
1259 pgprot_t prot;
1260
1261 switch (cmd) {
1262 case MLX5_IB_MMAP_WC_PAGE:
1263/* Some architectures don't support WC memory */
1264#if defined(CONFIG_X86)
1265 if (!pat_enabled())
1266 return -EPERM;
1267#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1268 return -EPERM;
1269#endif
1270 /* fall through */
1271 case MLX5_IB_MMAP_REGULAR_PAGE:
1272 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1273 prot = pgprot_writecombine(vma->vm_page_prot);
1274 break;
1275 case MLX5_IB_MMAP_NC_PAGE:
1276 prot = pgprot_noncached(vma->vm_page_prot);
1277 break;
1278 default:
1279 return -EINVAL;
1280 }
1281
1282 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1283 return -EINVAL;
1284
1285 idx = get_index(vma->vm_pgoff);
1286 if (idx >= uuari->num_uars)
1287 return -EINVAL;
1288
1289 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1290 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1291
1292 vma->vm_page_prot = prot;
1293 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1294 PAGE_SIZE, vma->vm_page_prot);
1295 if (err) {
1296 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1297 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1298 return -EAGAIN;
1299 }
1300
1301 pa = pfn << PAGE_SHIFT;
1302 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1303 vma->vm_start, &pa);
1304
7c2344c3 1305 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1306}
1307
e126ba97
EC		 1308static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1309{
1310 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1311 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1312 unsigned long command;
e126ba97
EC		 1313 phys_addr_t pfn;
1314
1315 command = get_command(vma->vm_pgoff);
1316 switch (command) {
37aa5c36
GL		 1317 case MLX5_IB_MMAP_WC_PAGE:
1318 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1319 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1320 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1321
1322 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1323 return -ENOSYS;
1324
d69e3bcf 1325 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1326 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1327 return -EINVAL;
1328
6cbac1e4 1329 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1330 return -EPERM;
1331
1332 /* Don't expose to user-space information it shouldn't have */
1333 if (PAGE_SIZE > 4096)
1334 return -EOPNOTSUPP;
1335
1336 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1337 pfn = (dev->mdev->iseg_base +
1338 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1339 PAGE_SHIFT;
1340 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1341 PAGE_SIZE, vma->vm_page_prot))
1342 return -EAGAIN;
1343
1344 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1345 vma->vm_start,
1346 (unsigned long long)pfn << PAGE_SHIFT);
1347 break;
d69e3bcf 1348
e126ba97
EC		 1349 default:
1350 return -EINVAL;
1351 }
1352
1353 return 0;
1354}
1355
e126ba97
EC		 1356static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1357 struct ib_ucontext *context,
1358 struct ib_udata *udata)
1359{
1360 struct mlx5_ib_alloc_pd_resp resp;
1361 struct mlx5_ib_pd *pd;
1362 int err;
1363
1364 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1365 if (!pd)
1366 return ERR_PTR(-ENOMEM);
1367
9603b61d 1368 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1369 if (err) {
1370 kfree(pd);
1371 return ERR_PTR(err);
1372 }
1373
1374 if (context) {
1375 resp.pdn = pd->pdn;
1376 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1377 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1378 kfree(pd);
1379 return ERR_PTR(-EFAULT);
1380 }
e126ba97
EC		 1381 }
1382
1383 return &pd->ibpd;
1384}
1385
1386static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1387{
1388 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1389 struct mlx5_ib_pd *mpd = to_mpd(pd);
1390
9603b61d 1391 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1392 kfree(mpd);
1393
1394 return 0;
1395}
1396
038d2ef8
MG		 1397static bool outer_header_zero(u32 *match_criteria)
1398{
1399 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1400 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1401 outer_headers);
1402
1403 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1404 outer_headers_c + 1,
1405 size - 1);
1406}
1407
1408static int parse_flow_attr(u32 *match_c, u32 *match_v,
1409 union ib_flow_spec *ib_spec)
1410{
1411 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1412 outer_headers);
1413 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1414 outer_headers);
1415 switch (ib_spec->type) {
1416 case IB_FLOW_SPEC_ETH:
1417 if (ib_spec->size != sizeof(ib_spec->eth))
1418 return -EINVAL;
1419
1420 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1421 dmac_47_16),
1422 ib_spec->eth.mask.dst_mac);
1423 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1424 dmac_47_16),
1425 ib_spec->eth.val.dst_mac);
1426
1427 if (ib_spec->eth.mask.vlan_tag) {
1428 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1429 vlan_tag, 1);
1430 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1431 vlan_tag, 1);
1432
1433 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1434 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1435 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1436 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1437
1438 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1439 first_cfi,
1440 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1441 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1442 first_cfi,
1443 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1444
1445 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1446 first_prio,
1447 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1448 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1449 first_prio,
1450 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1451 }
1452 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1453 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1454 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1455 ethertype, ntohs(ib_spec->eth.val.ether_type));
1456 break;
1457 case IB_FLOW_SPEC_IPV4:
1458 if (ib_spec->size != sizeof(ib_spec->ipv4))
1459 return -EINVAL;
1460
1461 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1462 ethertype, 0xffff);
1463 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1464 ethertype, ETH_P_IP);
1465
1466 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1467 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1468 &ib_spec->ipv4.mask.src_ip,
1469 sizeof(ib_spec->ipv4.mask.src_ip));
1470 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1471 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1472 &ib_spec->ipv4.val.src_ip,
1473 sizeof(ib_spec->ipv4.val.src_ip));
1474 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1475 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1476 &ib_spec->ipv4.mask.dst_ip,
1477 sizeof(ib_spec->ipv4.mask.dst_ip));
1478 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1479 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1480 &ib_spec->ipv4.val.dst_ip,
1481 sizeof(ib_spec->ipv4.val.dst_ip));
1482 break;
026bae0c
MG		 1483 case IB_FLOW_SPEC_IPV6:
1484 if (ib_spec->size != sizeof(ib_spec->ipv6))
1485 return -EINVAL;
1486
1487 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1488 ethertype, 0xffff);
1489 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1490 ethertype, ETH_P_IPV6);
1491
1492 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1493 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1494 &ib_spec->ipv6.mask.src_ip,
1495 sizeof(ib_spec->ipv6.mask.src_ip));
1496 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1497 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1498 &ib_spec->ipv6.val.src_ip,
1499 sizeof(ib_spec->ipv6.val.src_ip));
1500 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1501 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1502 &ib_spec->ipv6.mask.dst_ip,
1503 sizeof(ib_spec->ipv6.mask.dst_ip));
1504 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1505 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1506 &ib_spec->ipv6.val.dst_ip,
1507 sizeof(ib_spec->ipv6.val.dst_ip));
1508 break;
038d2ef8
MG		 1509 case IB_FLOW_SPEC_TCP:
1510 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1511 return -EINVAL;
1512
1513 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1514 0xff);
1515 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1516 IPPROTO_TCP);
1517
1518 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1519 ntohs(ib_spec->tcp_udp.mask.src_port));
1520 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1521 ntohs(ib_spec->tcp_udp.val.src_port));
1522
1523 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1524 ntohs(ib_spec->tcp_udp.mask.dst_port));
1525 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1526 ntohs(ib_spec->tcp_udp.val.dst_port));
1527 break;
1528 case IB_FLOW_SPEC_UDP:
1529 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1530 return -EINVAL;
1531
1532 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1533 0xff);
1534 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1535 IPPROTO_UDP);
1536
1537 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1538 ntohs(ib_spec->tcp_udp.mask.src_port));
1539 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1540 ntohs(ib_spec->tcp_udp.val.src_port));
1541
1542 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1543 ntohs(ib_spec->tcp_udp.mask.dst_port));
1544 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1545 ntohs(ib_spec->tcp_udp.val.dst_port));
1546 break;
1547 default:
1548 return -EINVAL;
1549 }
1550
1551 return 0;
1552}
1553
1554/* If a flow could catch both multicast and unicast packets,
1555 * it won't fall into the multicast flow steering table and this rule
1556 * could steal other multicast packets.
1557 */
1558static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1559{
1560 struct ib_flow_spec_eth *eth_spec;
1561
1562 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1563 ib_attr->size < sizeof(struct ib_flow_attr) +
1564 sizeof(struct ib_flow_spec_eth) ||
1565 ib_attr->num_of_specs < 1)
1566 return false;
1567
1568 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1569 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1570 eth_spec->size != sizeof(*eth_spec))
1571 return false;
1572
1573 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1574 is_multicast_ether_addr(eth_spec->val.dst_mac);
1575}
1576
1577static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1578{
1579 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1580 bool has_ipv4_spec = false;
1581 bool eth_type_ipv4 = true;
1582 unsigned int spec_index;
1583
1584 /* Validate that ethertype is correct */
1585 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1586 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1587 ib_spec->eth.mask.ether_type) {
1588 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1589 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1590 eth_type_ipv4 = false;
1591 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1592 has_ipv4_spec = true;
1593 }
1594 ib_spec = (void *)ib_spec + ib_spec->size;
1595 }
1596 return !has_ipv4_spec || eth_type_ipv4;
1597}
1598
1599static void put_flow_table(struct mlx5_ib_dev *dev,
1600 struct mlx5_ib_flow_prio *prio, bool ft_added)
1601{
1602 prio->refcount -= !!ft_added;
1603 if (!prio->refcount) {
1604 mlx5_destroy_flow_table(prio->flow_table);
1605 prio->flow_table = NULL;
1606 }
1607}
1608
1609static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1610{
1611 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1612 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1613 struct mlx5_ib_flow_handler,
1614 ibflow);
1615 struct mlx5_ib_flow_handler *iter, *tmp;
1616
1617 mutex_lock(&dev->flow_db.lock);
1618
1619 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1620 mlx5_del_flow_rule(iter->rule);
1621 list_del(&iter->list);
1622 kfree(iter);
1623 }
1624
1625 mlx5_del_flow_rule(handler->rule);
1626 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1627 mutex_unlock(&dev->flow_db.lock);
1628
1629 kfree(handler);
1630
1631 return 0;
1632}
1633
35d19011
MG		 1634static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1635{
1636 priority *= 2;
1637 if (!dont_trap)
1638 priority++;
1639 return priority;
1640}
1641
038d2ef8
MG		 1642#define MLX5_FS_MAX_TYPES 10
1643#define MLX5_FS_MAX_ENTRIES 32000UL
1644static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1645 struct ib_flow_attr *flow_attr)
1646{
35d19011 1647 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1648 struct mlx5_flow_namespace *ns = NULL;
1649 struct mlx5_ib_flow_prio *prio;
1650 struct mlx5_flow_table *ft;
1651 int num_entries;
1652 int num_groups;
1653 int priority;
1654 int err = 0;
1655
1656 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1657 if (flow_is_multicast_only(flow_attr) &&
1658 !dont_trap)
038d2ef8
MG		 1659 priority = MLX5_IB_FLOW_MCAST_PRIO;
1660 else
35d19011
MG		 1661 priority = ib_prio_to_core_prio(flow_attr->priority,
1662 dont_trap);
038d2ef8
MG		 1663 ns = mlx5_get_flow_namespace(dev->mdev,
1664 MLX5_FLOW_NAMESPACE_BYPASS);
1665 num_entries = MLX5_FS_MAX_ENTRIES;
1666 num_groups = MLX5_FS_MAX_TYPES;
1667 prio = &dev->flow_db.prios[priority];
1668 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1669 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1670 ns = mlx5_get_flow_namespace(dev->mdev,
1671 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1672 build_leftovers_ft_param(&priority,
1673 &num_entries,
1674 &num_groups);
1675 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1676 }
1677
1678 if (!ns)
1679 return ERR_PTR(-ENOTSUPP);
1680
1681 ft = prio->flow_table;
1682 if (!ft) {
1683 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1684 num_entries,
d63cd286
MG		 1685 num_groups,
1686 0);
038d2ef8
MG		 1687
1688 if (!IS_ERR(ft)) {
1689 prio->refcount = 0;
1690 prio->flow_table = ft;
1691 } else {
1692 err = PTR_ERR(ft);
1693 }
1694 }
1695
1696 return err ? ERR_PTR(err) : prio;
1697}
1698
1699static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1700 struct mlx5_ib_flow_prio *ft_prio,
1701 struct ib_flow_attr *flow_attr,
1702 struct mlx5_flow_destination *dst)
1703{
1704 struct mlx5_flow_table *ft = ft_prio->flow_table;
1705 struct mlx5_ib_flow_handler *handler;
c5bb1730 1706 struct mlx5_flow_spec *spec;
038d2ef8 1707 void *ib_flow = flow_attr + 1;
038d2ef8 1708 unsigned int spec_index;
35d19011 1709 u32 action;
038d2ef8
MG		 1710 int err = 0;
1711
1712 if (!is_valid_attr(flow_attr))
1713 return ERR_PTR(-EINVAL);
1714
c5bb1730 1715 spec = mlx5_vzalloc(sizeof(*spec));
038d2ef8 1716 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 1717 if (!handler || !spec) {
038d2ef8
MG		 1718 err = -ENOMEM;
1719 goto free;
1720 }
1721
1722 INIT_LIST_HEAD(&handler->list);
1723
1724 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
c5bb1730
MG		 1725 err = parse_flow_attr(spec->match_criteria,
1726 spec->match_value, ib_flow);
038d2ef8
MG		 1727 if (err < 0)
1728 goto free;
1729
1730 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1731 }
1732
1733 /* Outer header support only */
c5bb1730
MG		 1734 spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria))
1735 << 0;
35d19011
MG		 1736 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1737 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
c5bb1730 1738 handler->rule = mlx5_add_flow_rule(ft, spec,
35d19011 1739 action,
038d2ef8
MG		 1740 MLX5_FS_DEFAULT_FLOW_TAG,
1741 dst);
1742
1743 if (IS_ERR(handler->rule)) {
1744 err = PTR_ERR(handler->rule);
1745 goto free;
1746 }
1747
1748 handler->prio = ft_prio - dev->flow_db.prios;
1749
1750 ft_prio->flow_table = ft;
1751free:
1752 if (err)
1753 kfree(handler);
c5bb1730 1754 kvfree(spec);
038d2ef8
MG		 1755 return err ? ERR_PTR(err) : handler;
1756}
1757
35d19011
MG		 1758static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1759 struct mlx5_ib_flow_prio *ft_prio,
1760 struct ib_flow_attr *flow_attr,
1761 struct mlx5_flow_destination *dst)
1762{
1763 struct mlx5_ib_flow_handler *handler_dst = NULL;
1764 struct mlx5_ib_flow_handler *handler = NULL;
1765
1766 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1767 if (!IS_ERR(handler)) {
1768 handler_dst = create_flow_rule(dev, ft_prio,
1769 flow_attr, dst);
1770 if (IS_ERR(handler_dst)) {
1771 mlx5_del_flow_rule(handler->rule);
1772 kfree(handler);
1773 handler = handler_dst;
1774 } else {
1775 list_add(&handler_dst->list, &handler->list);
1776 }
1777 }
1778
1779 return handler;
1780}
038d2ef8
MG		 1781enum {
1782 LEFTOVERS_MC,
1783 LEFTOVERS_UC,
1784};
1785
1786static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1787 struct mlx5_ib_flow_prio *ft_prio,
1788 struct ib_flow_attr *flow_attr,
1789 struct mlx5_flow_destination *dst)
1790{
1791 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1792 struct mlx5_ib_flow_handler *handler = NULL;
1793
1794 static struct {
1795 struct ib_flow_attr flow_attr;
1796 struct ib_flow_spec_eth eth_flow;
1797 } leftovers_specs[] = {
1798 [LEFTOVERS_MC] = {
1799 .flow_attr = {
1800 .num_of_specs = 1,
1801 .size = sizeof(leftovers_specs[0])
1802 },
1803 .eth_flow = {
1804 .type = IB_FLOW_SPEC_ETH,
1805 .size = sizeof(struct ib_flow_spec_eth),
1806 .mask = {.dst_mac = {0x1} },
1807 .val = {.dst_mac = {0x1} }
1808 }
1809 },
1810 [LEFTOVERS_UC] = {
1811 .flow_attr = {
1812 .num_of_specs = 1,
1813 .size = sizeof(leftovers_specs[0])
1814 },
1815 .eth_flow = {
1816 .type = IB_FLOW_SPEC_ETH,
1817 .size = sizeof(struct ib_flow_spec_eth),
1818 .mask = {.dst_mac = {0x1} },
1819 .val = {.dst_mac = {} }
1820 }
1821 }
1822 };
1823
1824 handler = create_flow_rule(dev, ft_prio,
1825 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1826 dst);
1827 if (!IS_ERR(handler) &&
1828 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1829 handler_ucast = create_flow_rule(dev, ft_prio,
1830 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1831 dst);
1832 if (IS_ERR(handler_ucast)) {
1833 kfree(handler);
1834 handler = handler_ucast;
1835 } else {
1836 list_add(&handler_ucast->list, &handler->list);
1837 }
1838 }
1839
1840 return handler;
1841}
1842
1843static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1844 struct ib_flow_attr *flow_attr,
1845 int domain)
1846{
1847 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1848 struct mlx5_ib_flow_handler *handler = NULL;
1849 struct mlx5_flow_destination *dst = NULL;
1850 struct mlx5_ib_flow_prio *ft_prio;
1851 int err;
1852
1853 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1854 return ERR_PTR(-ENOSPC);
1855
1856 if (domain != IB_FLOW_DOMAIN_USER ||
1857 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 1858 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 1859 return ERR_PTR(-EINVAL);
1860
1861 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1862 if (!dst)
1863 return ERR_PTR(-ENOMEM);
1864
1865 mutex_lock(&dev->flow_db.lock);
1866
1867 ft_prio = get_flow_table(dev, flow_attr);
1868 if (IS_ERR(ft_prio)) {
1869 err = PTR_ERR(ft_prio);
1870 goto unlock;
1871 }
1872
1873 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1874 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1875
1876 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1877 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
1878 handler = create_dont_trap_rule(dev, ft_prio,
1879 flow_attr, dst);
1880 } else {
1881 handler = create_flow_rule(dev, ft_prio, flow_attr,
1882 dst);
1883 }
038d2ef8
MG		 1884 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1885 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1886 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1887 dst);
1888 } else {
1889 err = -EINVAL;
1890 goto destroy_ft;
1891 }
1892
1893 if (IS_ERR(handler)) {
1894 err = PTR_ERR(handler);
1895 handler = NULL;
1896 goto destroy_ft;
1897 }
1898
1899 ft_prio->refcount++;
1900 mutex_unlock(&dev->flow_db.lock);
1901 kfree(dst);
1902
1903 return &handler->ibflow;
1904
1905destroy_ft:
1906 put_flow_table(dev, ft_prio, false);
1907unlock:
1908 mutex_unlock(&dev->flow_db.lock);
1909 kfree(dst);
1910 kfree(handler);
1911 return ERR_PTR(err);
1912}
1913
e126ba97
EC		 1914static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1915{
1916 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1917 int err;
1918
9603b61d 1919 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1920 if (err)
1921 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1922 ibqp->qp_num, gid->raw);
1923
1924 return err;
1925}
1926
1927static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1928{
1929 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1930 int err;
1931
9603b61d 1932 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1933 if (err)
1934 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1935 ibqp->qp_num, gid->raw);
1936
1937 return err;
1938}
1939
1940static int init_node_data(struct mlx5_ib_dev *dev)
1941{
1b5daf11 1942 int err;
e126ba97 1943
1b5daf11 1944 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1945 if (err)
1b5daf11 1946 return err;
e126ba97 1947
1b5daf11 1948 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1949
1b5daf11 1950 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1951}
1952
1953static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1954 char *buf)
1955{
1956 struct mlx5_ib_dev *dev =
1957 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1958
9603b61d 1959 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1960}
1961
1962static ssize_t show_reg_pages(struct device *device,
1963 struct device_attribute *attr, char *buf)
1964{
1965 struct mlx5_ib_dev *dev =
1966 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1967
6aec21f6 1968 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1969}
1970
1971static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1972 char *buf)
1973{
1974 struct mlx5_ib_dev *dev =
1975 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1976 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1977}
1978
e126ba97
EC		 1979static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1980 char *buf)
1981{
1982 struct mlx5_ib_dev *dev =
1983 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1984 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1985}
1986
1987static ssize_t show_board(struct device *device, struct device_attribute *attr,
1988 char *buf)
1989{
1990 struct mlx5_ib_dev *dev =
1991 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1992 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1993 dev->mdev->board_id);
e126ba97
EC		 1994}
1995
1996static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 1997static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1998static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1999static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2000static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2001
2002static struct device_attribute *mlx5_class_attributes[] = {
2003 &dev_attr_hw_rev,
e126ba97
EC		 2004 &dev_attr_hca_type,
2005 &dev_attr_board_id,
2006 &dev_attr_fw_pages,
2007 &dev_attr_reg_pages,
2008};
2009
7722f47e
HE		 2010static void pkey_change_handler(struct work_struct *work)
2011{
2012 struct mlx5_ib_port_resources *ports =
2013 container_of(work, struct mlx5_ib_port_resources,
2014 pkey_change_work);
2015
2016 mutex_lock(&ports->devr->mutex);
2017 mlx5_ib_gsi_pkey_change(ports->gsi);
2018 mutex_unlock(&ports->devr->mutex);
2019}
2020
89ea94a7
MG		 2021static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2022{
2023 struct mlx5_ib_qp *mqp;
2024 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2025 struct mlx5_core_cq *mcq;
2026 struct list_head cq_armed_list;
2027 unsigned long flags_qp;
2028 unsigned long flags_cq;
2029 unsigned long flags;
2030
2031 INIT_LIST_HEAD(&cq_armed_list);
2032
2033 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2034 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2035 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2036 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2037 if (mqp->sq.tail != mqp->sq.head) {
2038 send_mcq = to_mcq(mqp->ibqp.send_cq);
2039 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2040 if (send_mcq->mcq.comp &&
2041 mqp->ibqp.send_cq->comp_handler) {
2042 if (!send_mcq->mcq.reset_notify_added) {
2043 send_mcq->mcq.reset_notify_added = 1;
2044 list_add_tail(&send_mcq->mcq.reset_notify,
2045 &cq_armed_list);
2046 }
2047 }
2048 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2049 }
2050 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2051 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2052 /* no handling is needed for SRQ */
2053 if (!mqp->ibqp.srq) {
2054 if (mqp->rq.tail != mqp->rq.head) {
2055 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2056 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2057 if (recv_mcq->mcq.comp &&
2058 mqp->ibqp.recv_cq->comp_handler) {
2059 if (!recv_mcq->mcq.reset_notify_added) {
2060 recv_mcq->mcq.reset_notify_added = 1;
2061 list_add_tail(&recv_mcq->mcq.reset_notify,
2062 &cq_armed_list);
2063 }
2064 }
2065 spin_unlock_irqrestore(&recv_mcq->lock,
2066 flags_cq);
2067 }
2068 }
2069 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2070 }
2071 /*At that point all inflight post send were put to be executed as of we
2072 * lock/unlock above locks Now need to arm all involved CQs.
2073 */
2074 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2075 mcq->comp(mcq);
2076 }
2077 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2078}
2079
9603b61d 2080static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2081 enum mlx5_dev_event event, unsigned long param)
e126ba97 2082{
9603b61d 2083 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2084 struct ib_event ibev;
9603b61d 2085
e126ba97
EC		 2086 u8 port = 0;
2087
2088 switch (event) {
2089 case MLX5_DEV_EVENT_SYS_ERROR:
2090 ibdev->ib_active = false;
2091 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2092 mlx5_ib_handle_internal_error(ibdev);
e126ba97
EC		 2093 break;
2094
2095 case MLX5_DEV_EVENT_PORT_UP:
2096 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 2097 port = (u8)param;
e126ba97
EC		 2098 break;
2099
2100 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2101 case MLX5_DEV_EVENT_PORT_INITIALIZED:
e126ba97 2102 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 2103 port = (u8)param;
e126ba97
EC		 2104 break;
2105
e126ba97
EC		 2106 case MLX5_DEV_EVENT_LID_CHANGE:
2107 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2108 port = (u8)param;
e126ba97
EC		 2109 break;
2110
2111 case MLX5_DEV_EVENT_PKEY_CHANGE:
2112 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2113 port = (u8)param;
7722f47e
HE		 2114
2115 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2116 break;
2117
2118 case MLX5_DEV_EVENT_GUID_CHANGE:
2119 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2120 port = (u8)param;
e126ba97
EC		 2121 break;
2122
2123 case MLX5_DEV_EVENT_CLIENT_REREG:
2124 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2125 port = (u8)param;
e126ba97
EC		 2126 break;
2127 }
2128
2129 ibev.device = &ibdev->ib_dev;
2130 ibev.element.port_num = port;
2131
a0c84c32
EC		 2132 if (port < 1 || port > ibdev->num_ports) {
2133 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2134 return;
2135 }
2136
e126ba97
EC		 2137 if (ibdev->ib_active)
2138 ib_dispatch_event(&ibev);
2139}
2140
2141static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2142{
2143 int port;
2144
938fe83c 2145 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2146 mlx5_query_ext_port_caps(dev, port);
2147}
2148
2149static int get_port_caps(struct mlx5_ib_dev *dev)
2150{
2151 struct ib_device_attr *dprops = NULL;
2152 struct ib_port_attr *pprops = NULL;
f614fc15 2153 int err = -ENOMEM;
e126ba97 2154 int port;
2528e33e 2155 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2156
2157 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2158 if (!pprops)
2159 goto out;
2160
2161 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2162 if (!dprops)
2163 goto out;
2164
2528e33e 2165 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2166 if (err) {
2167 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2168 goto out;
2169 }
2170
938fe83c 2171 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 2172 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2173 if (err) {
938fe83c
SM		 2174 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2175 port, err);
e126ba97
EC		 2176 break;
2177 }
938fe83c
SM		 2178 dev->mdev->port_caps[port - 1].pkey_table_len =
2179 dprops->max_pkeys;
2180 dev->mdev->port_caps[port - 1].gid_table_len =
2181 pprops->gid_tbl_len;
e126ba97
EC		 2182 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2183 dprops->max_pkeys, pprops->gid_tbl_len);
2184 }
2185
2186out:
2187 kfree(pprops);
2188 kfree(dprops);
2189
2190 return err;
2191}
2192
2193static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2194{
2195 int err;
2196
2197 err = mlx5_mr_cache_cleanup(dev);
2198 if (err)
2199 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2200
2201 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2202 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2203 ib_dealloc_pd(dev->umrc.pd);
2204}
2205
2206enum {
2207 MAX_UMR_WR = 128,
2208};
2209
2210static int create_umr_res(struct mlx5_ib_dev *dev)
2211{
2212 struct ib_qp_init_attr *init_attr = NULL;
2213 struct ib_qp_attr *attr = NULL;
2214 struct ib_pd *pd;
2215 struct ib_cq *cq;
2216 struct ib_qp *qp;
e126ba97
EC		 2217 int ret;
2218
2219 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2220 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2221 if (!attr || !init_attr) {
2222 ret = -ENOMEM;
2223 goto error_0;
2224 }
2225
ed082d36 2226 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2227 if (IS_ERR(pd)) {
2228 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2229 ret = PTR_ERR(pd);
2230 goto error_0;
2231 }
2232
add08d76 2233 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2234 if (IS_ERR(cq)) {
2235 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2236 ret = PTR_ERR(cq);
2237 goto error_2;
2238 }
e126ba97
EC		 2239
2240 init_attr->send_cq = cq;
2241 init_attr->recv_cq = cq;
2242 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2243 init_attr->cap.max_send_wr = MAX_UMR_WR;
2244 init_attr->cap.max_send_sge = 1;
2245 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2246 init_attr->port_num = 1;
2247 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2248 if (IS_ERR(qp)) {
2249 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2250 ret = PTR_ERR(qp);
2251 goto error_3;
2252 }
2253 qp->device = &dev->ib_dev;
2254 qp->real_qp = qp;
2255 qp->uobject = NULL;
2256 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2257
2258 attr->qp_state = IB_QPS_INIT;
2259 attr->port_num = 1;
2260 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2261 IB_QP_PORT, NULL);
2262 if (ret) {
2263 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2264 goto error_4;
2265 }
2266
2267 memset(attr, 0, sizeof(*attr));
2268 attr->qp_state = IB_QPS_RTR;
2269 attr->path_mtu = IB_MTU_256;
2270
2271 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2272 if (ret) {
2273 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2274 goto error_4;
2275 }
2276
2277 memset(attr, 0, sizeof(*attr));
2278 attr->qp_state = IB_QPS_RTS;
2279 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2280 if (ret) {
2281 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2282 goto error_4;
2283 }
2284
2285 dev->umrc.qp = qp;
2286 dev->umrc.cq = cq;
e126ba97
EC		 2287 dev->umrc.pd = pd;
2288
2289 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2290 ret = mlx5_mr_cache_init(dev);
2291 if (ret) {
2292 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2293 goto error_4;
2294 }
2295
2296 kfree(attr);
2297 kfree(init_attr);
2298
2299 return 0;
2300
2301error_4:
2302 mlx5_ib_destroy_qp(qp);
2303
2304error_3:
add08d76 2305 ib_free_cq(cq);
e126ba97
EC		 2306
2307error_2:
e126ba97
EC		 2308 ib_dealloc_pd(pd);
2309
2310error_0:
2311 kfree(attr);
2312 kfree(init_attr);
2313 return ret;
2314}
2315
2316static int create_dev_resources(struct mlx5_ib_resources *devr)
2317{
2318 struct ib_srq_init_attr attr;
2319 struct mlx5_ib_dev *dev;
bcf4c1ea 2320 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2321 int port;
e126ba97
EC		 2322 int ret = 0;
2323
2324 dev = container_of(devr, struct mlx5_ib_dev, devr);
2325
d16e91da
HE		 2326 mutex_init(&devr->mutex);
2327
e126ba97
EC		 2328 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2329 if (IS_ERR(devr->p0)) {
2330 ret = PTR_ERR(devr->p0);
2331 goto error0;
2332 }
2333 devr->p0->device = &dev->ib_dev;
2334 devr->p0->uobject = NULL;
2335 atomic_set(&devr->p0->usecnt, 0);
2336
bcf4c1ea 2337 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2338 if (IS_ERR(devr->c0)) {
2339 ret = PTR_ERR(devr->c0);
2340 goto error1;
2341 }
2342 devr->c0->device = &dev->ib_dev;
2343 devr->c0->uobject = NULL;
2344 devr->c0->comp_handler = NULL;
2345 devr->c0->event_handler = NULL;
2346 devr->c0->cq_context = NULL;
2347 atomic_set(&devr->c0->usecnt, 0);
2348
2349 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2350 if (IS_ERR(devr->x0)) {
2351 ret = PTR_ERR(devr->x0);
2352 goto error2;
2353 }
2354 devr->x0->device = &dev->ib_dev;
2355 devr->x0->inode = NULL;
2356 atomic_set(&devr->x0->usecnt, 0);
2357 mutex_init(&devr->x0->tgt_qp_mutex);
2358 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2359
2360 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2361 if (IS_ERR(devr->x1)) {
2362 ret = PTR_ERR(devr->x1);
2363 goto error3;
2364 }
2365 devr->x1->device = &dev->ib_dev;
2366 devr->x1->inode = NULL;
2367 atomic_set(&devr->x1->usecnt, 0);
2368 mutex_init(&devr->x1->tgt_qp_mutex);
2369 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2370
2371 memset(&attr, 0, sizeof(attr));
2372 attr.attr.max_sge = 1;
2373 attr.attr.max_wr = 1;
2374 attr.srq_type = IB_SRQT_XRC;
2375 attr.ext.xrc.cq = devr->c0;
2376 attr.ext.xrc.xrcd = devr->x0;
2377
2378 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2379 if (IS_ERR(devr->s0)) {
2380 ret = PTR_ERR(devr->s0);
2381 goto error4;
2382 }
2383 devr->s0->device = &dev->ib_dev;
2384 devr->s0->pd = devr->p0;
2385 devr->s0->uobject = NULL;
2386 devr->s0->event_handler = NULL;
2387 devr->s0->srq_context = NULL;
2388 devr->s0->srq_type = IB_SRQT_XRC;
2389 devr->s0->ext.xrc.xrcd = devr->x0;
2390 devr->s0->ext.xrc.cq = devr->c0;
2391 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2392 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2393 atomic_inc(&devr->p0->usecnt);
2394 atomic_set(&devr->s0->usecnt, 0);
2395
4aa17b28
HA		 2396 memset(&attr, 0, sizeof(attr));
2397 attr.attr.max_sge = 1;
2398 attr.attr.max_wr = 1;
2399 attr.srq_type = IB_SRQT_BASIC;
2400 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2401 if (IS_ERR(devr->s1)) {
2402 ret = PTR_ERR(devr->s1);
2403 goto error5;
2404 }
2405 devr->s1->device = &dev->ib_dev;
2406 devr->s1->pd = devr->p0;
2407 devr->s1->uobject = NULL;
2408 devr->s1->event_handler = NULL;
2409 devr->s1->srq_context = NULL;
2410 devr->s1->srq_type = IB_SRQT_BASIC;
2411 devr->s1->ext.xrc.cq = devr->c0;
2412 atomic_inc(&devr->p0->usecnt);
2413 atomic_set(&devr->s0->usecnt, 0);
2414
7722f47e
HE		 2415 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2416 INIT_WORK(&devr->ports[port].pkey_change_work,
2417 pkey_change_handler);
2418 devr->ports[port].devr = devr;
2419 }
2420
e126ba97
EC		 2421 return 0;
2422
4aa17b28
HA		 2423error5:
2424 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2425error4:
2426 mlx5_ib_dealloc_xrcd(devr->x1);
2427error3:
2428 mlx5_ib_dealloc_xrcd(devr->x0);
2429error2:
2430 mlx5_ib_destroy_cq(devr->c0);
2431error1:
2432 mlx5_ib_dealloc_pd(devr->p0);
2433error0:
2434 return ret;
2435}
2436
2437static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2438{
7722f47e
HE		 2439 struct mlx5_ib_dev *dev =
2440 container_of(devr, struct mlx5_ib_dev, devr);
2441 int port;
2442
4aa17b28 2443 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2444 mlx5_ib_destroy_srq(devr->s0);
2445 mlx5_ib_dealloc_xrcd(devr->x0);
2446 mlx5_ib_dealloc_xrcd(devr->x1);
2447 mlx5_ib_destroy_cq(devr->c0);
2448 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2449
2450 /* Make sure no change P_Key work items are still executing */
2451 for (port = 0; port < dev->num_ports; ++port)
2452 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2453}
2454
e53505a8
AS		 2455static u32 get_core_cap_flags(struct ib_device *ibdev)
2456{
2457 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2458 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2459 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2460 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2461 u32 ret = 0;
2462
2463 if (ll == IB_LINK_LAYER_INFINIBAND)
2464 return RDMA_CORE_PORT_IBA_IB;
2465
2466 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2467 return 0;
2468
2469 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2470 return 0;
2471
2472 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2473 ret |= RDMA_CORE_PORT_IBA_ROCE;
2474
2475 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2476 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2477
2478 return ret;
2479}
2480
7738613e
IW		 2481static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2482 struct ib_port_immutable *immutable)
2483{
2484 struct ib_port_attr attr;
2485 int err;
2486
2487 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2488 if (err)
2489 return err;
2490
2491 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2492 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2493 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2494 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2495
2496 return 0;
2497}
2498
c7342823
IW		 2499static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2500 size_t str_len)
2501{
2502 struct mlx5_ib_dev *dev =
2503 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2504 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2505 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2506}
2507
fc24fc5e
AS		 2508static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2509{
e53505a8
AS		 2510 int err;
2511
fc24fc5e 2512 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 2513 err = register_netdevice_notifier(&dev->roce.nb);
2514 if (err)
2515 return err;
2516
2517 err = mlx5_nic_vport_enable_roce(dev->mdev);
2518 if (err)
2519 goto err_unregister_netdevice_notifier;
2520
2521 return 0;
2522
2523err_unregister_netdevice_notifier:
2524 unregister_netdevice_notifier(&dev->roce.nb);
2525 return err;
fc24fc5e
AS		 2526}
2527
2528static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2529{
e53505a8 2530 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2531 unregister_netdevice_notifier(&dev->roce.nb);
2532}
2533
0837e86a
MB		 2534static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2535{
2536 unsigned int i;
2537
2538 for (i = 0; i < dev->num_ports; i++)
2539 mlx5_core_dealloc_q_counter(dev->mdev,
2540 dev->port[i].q_cnt_id);
2541}
2542
2543static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2544{
2545 int i;
2546 int ret;
2547
2548 for (i = 0; i < dev->num_ports; i++) {
2549 ret = mlx5_core_alloc_q_counter(dev->mdev,
2550 &dev->port[i].q_cnt_id);
2551 if (ret) {
2552 mlx5_ib_warn(dev,
2553 "couldn't allocate queue counter for port %d, err %d\n",
2554 i + 1, ret);
2555 goto dealloc_counters;
2556 }
2557 }
2558
2559 return 0;
2560
2561dealloc_counters:
2562 while (--i >= 0)
2563 mlx5_core_dealloc_q_counter(dev->mdev,
2564 dev->port[i].q_cnt_id);
2565
2566 return ret;
2567}
2568
61961500 2569static const char * const names[] = {
0ad17a8f
MB		 2570 "rx_write_requests",
2571 "rx_read_requests",
2572 "rx_atomic_requests",
2573 "out_of_buffer",
2574 "out_of_sequence",
2575 "duplicate_request",
2576 "rnr_nak_retry_err",
2577 "packet_seq_err",
2578 "implied_nak_seq_err",
2579 "local_ack_timeout_err",
2580};
2581
2582static const size_t stats_offsets[] = {
2583 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2584 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2585 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2586 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2587 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2588 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2589 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2590 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2591 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2592 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2593};
2594
2595static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2596 u8 port_num)
2597{
2598 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2599
2600 /* We support only per port stats */
2601 if (port_num == 0)
2602 return NULL;
2603
2604 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2605 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2606}
2607
2608static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2609 struct rdma_hw_stats *stats,
2610 u8 port, int index)
2611{
2612 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2613 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2614 void *out;
2615 __be32 val;
2616 int ret;
2617 int i;
2618
2619 if (!port || !stats)
2620 return -ENOSYS;
2621
2622 out = mlx5_vzalloc(outlen);
2623 if (!out)
2624 return -ENOMEM;
2625
2626 ret = mlx5_core_query_q_counter(dev->mdev,
2627 dev->port[port - 1].q_cnt_id, 0,
2628 out, outlen);
2629 if (ret)
2630 goto free;
2631
2632 for (i = 0; i < ARRAY_SIZE(names); i++) {
2633 val = *(__be32 *)(out + stats_offsets[i]);
2634 stats->value[i] = (u64)be32_to_cpu(val);
2635 }
2636free:
2637 kvfree(out);
2638 return ARRAY_SIZE(names);
2639}
2640
9603b61d 2641static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2642{
e126ba97 2643 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2644 enum rdma_link_layer ll;
2645 int port_type_cap;
e126ba97
EC		 2646 int err;
2647 int i;
2648
ebd61f68
AS		 2649 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2650 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2651
e53505a8 2652 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2653 return NULL;
2654
e126ba97
EC		 2655 printk_once(KERN_INFO "%s", mlx5_version);
2656
2657 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2658 if (!dev)
9603b61d 2659 return NULL;
e126ba97 2660
9603b61d 2661 dev->mdev = mdev;
e126ba97 2662
0837e86a
MB		 2663 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2664 GFP_KERNEL);
2665 if (!dev->port)
2666 goto err_dealloc;
2667
fc24fc5e 2668 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2669 err = get_port_caps(dev);
2670 if (err)
0837e86a 2671 goto err_free_port;
e126ba97 2672
1b5daf11
MD		 2673 if (mlx5_use_mad_ifc(dev))
2674 get_ext_port_caps(dev);
e126ba97 2675
e126ba97
EC		 2676 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2677
2678 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2679 dev->ib_dev.owner = THIS_MODULE;
2680 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2681 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2682 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2683 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2684 dev->ib_dev.num_comp_vectors =
2685 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2686 dev->ib_dev.dma_device = &mdev->pdev->dev;
2687
2688 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2689 dev->ib_dev.uverbs_cmd_mask =
2690 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2691 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2692 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2693 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2694 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2695 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2696 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2697 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2698 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2699 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2700 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2701 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2702 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2703 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2704 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2705 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2706 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2707 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2708 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2709 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2710 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2711 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2712 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2713 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 2714 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 2715 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2716 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2717 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 2718
2719 dev->ib_dev.query_device = mlx5_ib_query_device;
2720 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 2721 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 2722 if (ll == IB_LINK_LAYER_ETHERNET)
2723 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 2724 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 2725 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2726 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 2727 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2728 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2729 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2730 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2731 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2732 dev->ib_dev.mmap = mlx5_ib_mmap;
2733 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2734 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2735 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2736 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2737 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2738 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2739 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2740 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2741 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2742 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2743 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2744 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2745 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2746 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2747 dev->ib_dev.post_send = mlx5_ib_post_send;
2748 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2749 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2750 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2751 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2752 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2753 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2754 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2755 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2756 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 2757 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 2758 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2759 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2760 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2761 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 2762 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 2763 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 2764 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 2765 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 2766 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
eff901d3
EC		 2767 if (mlx5_core_is_pf(mdev)) {
2768 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
2769 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
2770 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
2771 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
2772 }
e126ba97 2773
7c2344c3
MG		 2774 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
2775
938fe83c 2776 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 2777
d2370e0a
MB		 2778 if (MLX5_CAP_GEN(mdev, imaicl)) {
2779 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2780 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2781 dev->ib_dev.uverbs_cmd_mask |=
2782 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2783 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2784 }
2785
0ad17a8f
MB		 2786 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
2787 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
2788 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
2789 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
2790 }
2791
938fe83c 2792 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 2793 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2794 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2795 dev->ib_dev.uverbs_cmd_mask |=
2796 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2797 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2798 }
2799
048ccca8 2800 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 2801 IB_LINK_LAYER_ETHERNET) {
2802 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2803 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 2804 dev->ib_dev.create_wq = mlx5_ib_create_wq;
2805 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
2806 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 2807 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
2808 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 2809 dev->ib_dev.uverbs_ex_cmd_mask |=
2810 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 2811 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
2812 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2813 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 2814 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2815 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2816 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 2817 }
e126ba97
EC		 2818 err = init_node_data(dev);
2819 if (err)
233d05d2 2820 goto err_dealloc;
e126ba97 2821
038d2ef8 2822 mutex_init(&dev->flow_db.lock);
e126ba97 2823 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 2824 INIT_LIST_HEAD(&dev->qp_list);
2825 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 2826
fc24fc5e
AS		 2827 if (ll == IB_LINK_LAYER_ETHERNET) {
2828 err = mlx5_enable_roce(dev);
2829 if (err)
2830 goto err_dealloc;
2831 }
2832
e126ba97
EC		 2833 err = create_dev_resources(&dev->devr);
2834 if (err)
fc24fc5e 2835 goto err_disable_roce;
e126ba97 2836
6aec21f6 2837 err = mlx5_ib_odp_init_one(dev);
281d1a92 2838 if (err)
e126ba97
EC		 2839 goto err_rsrc;
2840
0837e86a 2841 err = mlx5_ib_alloc_q_counters(dev);
6aec21f6
HE		 2842 if (err)
2843 goto err_odp;
2844
0837e86a
MB		 2845 err = ib_register_device(&dev->ib_dev, NULL);
2846 if (err)
2847 goto err_q_cnt;
2848
e126ba97
EC		 2849 err = create_umr_res(dev);
2850 if (err)
2851 goto err_dev;
2852
2853 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 2854 err = device_create_file(&dev->ib_dev.dev,
2855 mlx5_class_attributes[i]);
2856 if (err)
e126ba97
EC		 2857 goto err_umrc;
2858 }
2859
2860 dev->ib_active = true;
2861
9603b61d 2862 return dev;
e126ba97
EC		 2863
2864err_umrc:
2865 destroy_umrc_res(dev);
2866
2867err_dev:
2868 ib_unregister_device(&dev->ib_dev);
2869
0837e86a
MB		 2870err_q_cnt:
2871 mlx5_ib_dealloc_q_counters(dev);
2872
6aec21f6
HE		 2873err_odp:
2874 mlx5_ib_odp_remove_one(dev);
2875
e126ba97
EC		 2876err_rsrc:
2877 destroy_dev_resources(&dev->devr);
2878
fc24fc5e
AS		 2879err_disable_roce:
2880 if (ll == IB_LINK_LAYER_ETHERNET)
2881 mlx5_disable_roce(dev);
2882
0837e86a
MB		 2883err_free_port:
2884 kfree(dev->port);
2885
9603b61d 2886err_dealloc:
e126ba97
EC		 2887 ib_dealloc_device((struct ib_device *)dev);
2888
9603b61d 2889 return NULL;
e126ba97
EC		 2890}
2891
9603b61d 2892static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 2893{
9603b61d 2894 struct mlx5_ib_dev *dev = context;
fc24fc5e 2895 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 2896
e126ba97 2897 ib_unregister_device(&dev->ib_dev);
0837e86a 2898 mlx5_ib_dealloc_q_counters(dev);
eefd56e5 2899 destroy_umrc_res(dev);
6aec21f6 2900 mlx5_ib_odp_remove_one(dev);
e126ba97 2901 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 2902 if (ll == IB_LINK_LAYER_ETHERNET)
2903 mlx5_disable_roce(dev);
0837e86a 2904 kfree(dev->port);
e126ba97
EC		 2905 ib_dealloc_device(&dev->ib_dev);
2906}
2907
9603b61d
JM		 2908static struct mlx5_interface mlx5_ib_interface = {
2909 .add = mlx5_ib_add,
2910 .remove = mlx5_ib_remove,
2911 .event = mlx5_ib_event,
64613d94 2912 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 2913};
2914
2915static int __init mlx5_ib_init(void)
2916{
6aec21f6
HE		 2917 int err;
2918
9603b61d
JM		 2919 if (deprecated_prof_sel != 2)
2920 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2921
6aec21f6
HE		 2922 err = mlx5_ib_odp_init();
2923 if (err)
2924 return err;
2925
2926 err = mlx5_register_interface(&mlx5_ib_interface);
2927 if (err)
2928 goto clean_odp;
2929
2930 return err;
2931
2932clean_odp:
2933 mlx5_ib_odp_cleanup();
2934 return err;
e126ba97
EC		 2935}
2936
2937static void __exit mlx5_ib_cleanup(void)
2938{
9603b61d 2939 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 2940 mlx5_ib_odp_cleanup();
e126ba97
EC		 2941}
2942
2943module_init(mlx5_ib_init);
2944module_exit(mlx5_ib_cleanup);
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