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RDMA/mlx5: Use SRCU properly in ODP prefetch
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
cecae747 55#include <linux/mlx5/eswitch.h>
7c2344c3 56#include <linux/list.h>
e126ba97
EC		 57#include <rdma/ib_smi.h>
58#include <rdma/ib_umem.h>
038d2ef8
MG		 59#include <linux/in.h>
60#include <linux/etherdevice.h>
e126ba97 61#include "mlx5_ib.h"
fc385b7a 62#include "ib_rep.h"
e1f24a79 63#include "cmd.h"
f3da6577 64#include "srq.h"
3346c487 65#include <linux/mlx5/fs_helpers.h>
c6475a0b 66#include <linux/mlx5/accel.h>
8c84660b 67#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 68#include <rdma/mlx5_user_ioctl_verbs.h>
69#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 70
71#define UVERBS_MODULE_NAME mlx5_ib
72#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 73
74#define DRIVER_NAME "mlx5_ib"
b359911d 75#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 76
77MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
79MODULE_LICENSE("Dual BSD/GPL");
e126ba97 80
e126ba97
EC		 81static char mlx5_version[] =
82 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 83 DRIVER_VERSION "\n";
e126ba97 84
d69a24e0
DJ		 85struct mlx5_ib_event_work {
86 struct work_struct work;
df097a27
SM		 87 union {
88 struct mlx5_ib_dev *dev;
89 struct mlx5_ib_multiport_info *mpi;
90 };
91 bool is_slave;
134e9349 92 unsigned int event;
df097a27 93 void *param;
d69a24e0
DJ		 94};
95
da7525d2
EBE		 96enum {
97 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
98};
99
d69a24e0 100static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 101static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
102static LIST_HEAD(mlx5_ib_dev_list);
103/*
104 * This mutex should be held when accessing either of the above lists
105 */
106static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
107
c44ef998
IL		 108/* We can't use an array for xlt_emergency_page because dma_map_single
109 * doesn't work on kernel modules memory
110 */
111static unsigned long xlt_emergency_page;
112static struct mutex xlt_emergency_page_mutex;
113
32f69e4b
DJ		 114struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
115{
116 struct mlx5_ib_dev *dev;
117
118 mutex_lock(&mlx5_ib_multiport_mutex);
119 dev = mpi->ibdev;
120 mutex_unlock(&mlx5_ib_multiport_mutex);
121 return dev;
122}
123
1b5daf11 124static enum rdma_link_layer
ebd61f68 125mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 126{
ebd61f68 127 switch (port_type_cap) {
1b5daf11
MD		 128 case MLX5_CAP_PORT_TYPE_IB:
129 return IB_LINK_LAYER_INFINIBAND;
130 case MLX5_CAP_PORT_TYPE_ETH:
131 return IB_LINK_LAYER_ETHERNET;
132 default:
133 return IB_LINK_LAYER_UNSPECIFIED;
134 }
135}
136
ebd61f68
AS		 137static enum rdma_link_layer
138mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
139{
140 struct mlx5_ib_dev *dev = to_mdev(device);
141 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
142
143 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
144}
145
fd65f1b8
MS		 146static int get_port_state(struct ib_device *ibdev,
147 u8 port_num,
148 enum ib_port_state *state)
149{
150 struct ib_port_attr attr;
151 int ret;
152
153 memset(&attr, 0, sizeof(attr));
3023a1e9 154 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 155 if (!ret)
156 *state = attr.state;
157 return ret;
158}
159
35b0aa67
MB		 160static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
161 struct net_device *ndev,
162 u8 *port_num)
163{
164 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
165 struct net_device *rep_ndev;
166 struct mlx5_ib_port *port;
167 int i;
168
169 for (i = 0; i < dev->num_ports; i++) {
170 port = &dev->port[i];
171 if (!port->rep)
172 continue;
173
174 read_lock(&port->roce.netdev_lock);
175 rep_ndev = mlx5_ib_get_rep_netdev(esw,
176 port->rep->vport);
177 if (rep_ndev == ndev) {
178 read_unlock(&port->roce.netdev_lock);
179 *port_num = i + 1;
180 return &port->roce;
181 }
182 read_unlock(&port->roce.netdev_lock);
183 }
184
185 return NULL;
186}
187
fc24fc5e
AS		 188static int mlx5_netdev_event(struct notifier_block *this,
189 unsigned long event, void *ptr)
190{
7fd8aefb 191 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 192 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 193 u8 port_num = roce->native_port_num;
194 struct mlx5_core_dev *mdev;
195 struct mlx5_ib_dev *ibdev;
196
197 ibdev = roce->dev;
32f69e4b
DJ		 198 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
199 if (!mdev)
200 return NOTIFY_DONE;
fc24fc5e 201
5ec8c83e
AH		 202 switch (event) {
203 case NETDEV_REGISTER:
35b0aa67
MB		 204 /* Should already be registered during the load */
205 if (ibdev->is_rep)
206 break;
7fd8aefb 207 write_lock(&roce->netdev_lock);
dce45af5 208 if (ndev->dev.parent == mdev->device)
842a9c83 209 roce->netdev = ndev;
7fd8aefb 210 write_unlock(&roce->netdev_lock);
5ec8c83e 211 break;
fc24fc5e 212
842a9c83 213 case NETDEV_UNREGISTER:
35b0aa67 214 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 215 write_lock(&roce->netdev_lock);
216 if (roce->netdev == ndev)
217 roce->netdev = NULL;
218 write_unlock(&roce->netdev_lock);
219 break;
220
fd65f1b8 221 case NETDEV_CHANGE:
5ec8c83e 222 case NETDEV_UP:
88621dfe 223 case NETDEV_DOWN: {
7fd8aefb 224 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 225 struct net_device *upper = NULL;
226
227 if (lag_ndev) {
228 upper = netdev_master_upper_dev_get(lag_ndev);
229 dev_put(lag_ndev);
230 }
231
35b0aa67
MB		 232 if (ibdev->is_rep)
233 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
234 if (!roce)
235 return NOTIFY_DONE;
7fd8aefb 236 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 237 && ibdev->ib_active) {
626bc02d 238 struct ib_event ibev = { };
fd65f1b8 239 enum ib_port_state port_state;
5ec8c83e 240
7fd8aefb
DJ		 241 if (get_port_state(&ibdev->ib_dev, port_num,
242 &port_state))
243 goto done;
fd65f1b8 244
7fd8aefb
DJ		 245 if (roce->last_port_state == port_state)
246 goto done;
fd65f1b8 247
7fd8aefb 248 roce->last_port_state = port_state;
5ec8c83e 249 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 250 if (port_state == IB_PORT_DOWN)
251 ibev.event = IB_EVENT_PORT_ERR;
252 else if (port_state == IB_PORT_ACTIVE)
253 ibev.event = IB_EVENT_PORT_ACTIVE;
254 else
7fd8aefb 255 goto done;
fd65f1b8 256
7fd8aefb 257 ibev.element.port_num = port_num;
5ec8c83e
AH		 258 ib_dispatch_event(&ibev);
259 }
260 break;
88621dfe 261 }
fc24fc5e 262
5ec8c83e
AH		 263 default:
264 break;
265 }
7fd8aefb 266done:
32f69e4b 267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return NOTIFY_DONE;
269}
270
271static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
272 u8 port_num)
273{
274 struct mlx5_ib_dev *ibdev = to_mdev(device);
275 struct net_device *ndev;
32f69e4b
DJ		 276 struct mlx5_core_dev *mdev;
277
278 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
279 if (!mdev)
280 return NULL;
fc24fc5e 281
32f69e4b 282 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 283 if (ndev)
32f69e4b 284 goto out;
88621dfe 285
fc24fc5e
AS		 286 /* Ensure ndev does not disappear before we invoke dev_hold()
287 */
95579e78
MB		 288 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
289 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 290 if (ndev)
291 dev_hold(ndev);
95579e78 292 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 293
32f69e4b
DJ		 294out:
295 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 296 return ndev;
297}
298
32f69e4b
DJ		 299struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
300 u8 ib_port_num,
301 u8 *native_port_num)
302{
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 ib_port_num);
305 struct mlx5_core_dev *mdev = NULL;
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
210b1f78
MB		 309 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
310 ll != IB_LINK_LAYER_ETHERNET) {
311 if (native_port_num)
312 *native_port_num = ib_port_num;
313 return ibdev->mdev;
314 }
315
32f69e4b
DJ		 316 if (native_port_num)
317 *native_port_num = 1;
318
32f69e4b
DJ		 319 port = &ibdev->port[ib_port_num - 1];
320 if (!port)
321 return NULL;
322
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
325 if (mpi && !mpi->unaffiliate) {
326 mdev = mpi->mdev;
327 /* If it's the master no need to refcount, it'll exist
328 * as long as the ib_dev exists.
329 */
330 if (!mpi->is_master)
331 mpi->mdev_refcnt++;
332 }
333 spin_unlock(&port->mp.mpi_lock);
334
335 return mdev;
336}
337
338void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
339{
340 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
341 port_num);
342 struct mlx5_ib_multiport_info *mpi;
343 struct mlx5_ib_port *port;
344
345 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
346 return;
347
348 port = &ibdev->port[port_num - 1];
349
350 spin_lock(&port->mp.mpi_lock);
351 mpi = ibdev->port[port_num - 1].mp.mpi;
352 if (mpi->is_master)
353 goto out;
354
355 mpi->mdev_refcnt--;
356 if (mpi->unaffiliate)
357 complete(&mpi->unref_comp);
358out:
359 spin_unlock(&port->mp.mpi_lock);
360}
361
08e8676f
AL		 362static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
363 u8 *active_width)
f1b65df5
NO		 364{
365 switch (eth_proto_oper) {
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
368 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
369 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
370 *active_width = IB_WIDTH_1X;
371 *active_speed = IB_SPEED_SDR;
372 break;
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_QDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
386 *active_width = IB_WIDTH_1X;
387 *active_speed = IB_SPEED_EDR;
388 break;
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
393 *active_width = IB_WIDTH_4X;
394 *active_speed = IB_SPEED_QDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_HDR;
401 break;
402 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
403 *active_width = IB_WIDTH_4X;
404 *active_speed = IB_SPEED_FDR;
405 break;
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
410 *active_width = IB_WIDTH_4X;
411 *active_speed = IB_SPEED_EDR;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
08e8676f
AL		 420static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
421 u8 *active_width)
422{
423 switch (eth_proto_oper) {
424 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
425 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
426 *active_width = IB_WIDTH_1X;
427 *active_speed = IB_SPEED_SDR;
428 break;
429 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
430 *active_width = IB_WIDTH_1X;
431 *active_speed = IB_SPEED_DDR;
432 break;
433 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
434 *active_width = IB_WIDTH_1X;
435 *active_speed = IB_SPEED_QDR;
436 break;
437 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
438 *active_width = IB_WIDTH_4X;
439 *active_speed = IB_SPEED_QDR;
440 break;
441 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
442 *active_width = IB_WIDTH_1X;
443 *active_speed = IB_SPEED_EDR;
444 break;
445 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 446 *active_width = IB_WIDTH_2X;
447 *active_speed = IB_SPEED_EDR;
448 break;
08e8676f
AL		 449 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
450 *active_width = IB_WIDTH_1X;
451 *active_speed = IB_SPEED_HDR;
452 break;
cd272875
AL		 453 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
454 *active_width = IB_WIDTH_4X;
455 *active_speed = IB_SPEED_EDR;
456 break;
08e8676f
AL		 457 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
458 *active_width = IB_WIDTH_2X;
459 *active_speed = IB_SPEED_HDR;
460 break;
461 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
462 *active_width = IB_WIDTH_4X;
463 *active_speed = IB_SPEED_HDR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470}
471
472static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
473 u8 *active_width, bool ext)
474{
475 return ext ?
476 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
477 active_width) :
478 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
479 active_width);
480}
481
095b0927
IT		 482static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
483 struct ib_port_attr *props)
3f89a643
AS		 484{
485 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 486 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 487 struct mlx5_core_dev *mdev;
88621dfe 488 struct net_device *ndev, *upper;
3f89a643 489 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 490 bool put_mdev = true;
c876a1b7 491 u16 qkey_viol_cntr;
f1b65df5 492 u32 eth_prot_oper;
b3cbd6f0 493 u8 mdev_port_num;
08e8676f 494 bool ext;
095b0927 495 int err;
3f89a643 496
b3cbd6f0
DJ		 497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499 /* This means the port isn't affiliated yet. Get the
500 * info for the master port instead.
501 */
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
f1b65df5
NO		 508 /* Possible bad flows are checked before filling out props so in case
509 * of an error it will still be zeroed out.
26628e2d 510 * Use native port in case of reps
50f22fd8 511 */
26628e2d
MB		 512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514 1);
515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 mdev_port_num);
095b0927 518 if (err)
b3cbd6f0 519 goto out;
08e8676f
AL		 520 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 522
7672ed33
HL		 523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
f1b65df5 526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 527 &props->active_width, ext);
3f89a643 528
2f944c0f
JG		 529 props->port_cap_flags |= IB_PORT_CM_SUP;
530 props->ip_gids = true;
3f89a643
AS		 531
532 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
533 roce_address_table_size);
534 props->max_mtu = IB_MTU_4096;
535 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
536 props->pkey_tbl_len = 1;
537 props->state = IB_PORT_DOWN;
72a7720f 538 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
3f89a643 539
b3cbd6f0 540 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 541 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 542
b3cbd6f0
DJ		 543 /* If this is a stub query for an unaffiliated port stop here */
544 if (!put_mdev)
545 goto out;
546
3f89a643
AS		 547 ndev = mlx5_ib_get_netdev(device, port_num);
548 if (!ndev)
b3cbd6f0 549 goto out;
3f89a643 550
7c34ec19 551 if (dev->lag_active) {
88621dfe
AH		 552 rcu_read_lock();
553 upper = netdev_master_upper_dev_get_rcu(ndev);
554 if (upper) {
555 dev_put(ndev);
556 ndev = upper;
557 dev_hold(ndev);
558 }
559 rcu_read_unlock();
560 }
561
3f89a643
AS		 562 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
563 props->state = IB_PORT_ACTIVE;
72a7720f 564 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
3f89a643
AS		 565 }
566
567 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
568
569 dev_put(ndev);
570
571 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 572out:
573 if (put_mdev)
574 mlx5_ib_put_native_port_mdev(dev, port_num);
575 return err;
3f89a643
AS		 576}
577
095b0927
IT		 578static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
579 unsigned int index, const union ib_gid *gid,
580 const struct ib_gid_attr *attr)
3cca2606 581{
095b0927 582 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 583 u16 vlan_id = 0xffff;
095b0927
IT		 584 u8 roce_version = 0;
585 u8 roce_l3_type = 0;
095b0927 586 u8 mac[ETH_ALEN];
a70c0739 587 int ret;
095b0927
IT		 588
589 if (gid) {
590 gid_type = attr->gid_type;
a70c0739
PP		 591 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
592 if (ret)
593 return ret;
3cca2606
AS		 594 }
595
095b0927 596 switch (gid_type) {
3cca2606 597 case IB_GID_TYPE_IB:
095b0927 598 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 599 break;
600 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 601 roce_version = MLX5_ROCE_VERSION_2;
602 if (ipv6_addr_v4mapped((void *)gid))
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
604 else
605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 606 break;
607
608 default:
095b0927 609 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 610 }
611
095b0927 612 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 613 roce_l3_type, gid->raw, mac,
a70c0739 614 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 615 port_num);
3cca2606
AS		 616}
617
f4df9a7c 618static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 619 __always_unused void **context)
620{
414448d2 621 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 622 attr->index, &attr->gid, attr);
3cca2606
AS		 623}
624
414448d2
PP		 625static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
626 __always_unused void **context)
3cca2606 627{
414448d2
PP		 628 return set_roce_addr(to_mdev(attr->device), attr->port_num,
629 attr->index, NULL, NULL);
3cca2606
AS		 630}
631
47ec3866
PP		 632__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
633 const struct ib_gid_attr *attr)
2811ba51 634{
47ec3866 635 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 636 return 0;
637
638 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
639}
640
1b5daf11
MD		 641static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
642{
7fae6655
NO		 643 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
644 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
645 return 0;
1b5daf11
MD		 646}
647
648enum {
649 MLX5_VPORT_ACCESS_METHOD_MAD,
650 MLX5_VPORT_ACCESS_METHOD_HCA,
651 MLX5_VPORT_ACCESS_METHOD_NIC,
652};
653
654static int mlx5_get_vport_access_method(struct ib_device *ibdev)
655{
656 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
657 return MLX5_VPORT_ACCESS_METHOD_MAD;
658
ebd61f68 659 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 660 IB_LINK_LAYER_ETHERNET)
661 return MLX5_VPORT_ACCESS_METHOD_NIC;
662
663 return MLX5_VPORT_ACCESS_METHOD_HCA;
664}
665
da7525d2 666static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 667 u8 atomic_size_qp,
da7525d2
EBE		 668 struct ib_device_attr *props)
669{
670 u8 tmp;
671 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 672 u8 atomic_req_8B_endianness_mode =
bd10838a 673 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 674
675 /* Check if HW supports 8 bytes standard atomic operations and capable
676 * of host endianness respond
677 */
678 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
679 if (((atomic_operations & tmp) == tmp) &&
680 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
681 (atomic_req_8B_endianness_mode)) {
682 props->atomic_cap = IB_ATOMIC_HCA;
683 } else {
684 props->atomic_cap = IB_ATOMIC_NONE;
685 }
686}
687
776a3906
MS		 688static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
689 struct ib_device_attr *props)
690{
691 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
692
693 get_atomic_caps(dev, atomic_size_qp, props);
694}
695
696static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
697 struct ib_device_attr *props)
698{
699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
700
701 get_atomic_caps(dev, atomic_size_qp, props);
702}
703
704bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
705{
706 struct ib_device_attr props = {};
707
708 get_atomic_caps_dc(dev, &props);
709 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
710}
1b5daf11
MD		 711static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713{
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
1b5daf11
MD		 731
732 default:
733 return -EINVAL;
734 }
3f89a643
AS		 735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
1b5daf11
MD		 741}
742
743static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745{
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762}
763
764static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766{
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780}
781
782static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784{
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
1b5daf11
MD		 799
800 default:
801 return -EINVAL;
802 }
3f89a643
AS		 803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
1b5daf11
MD		 808}
809
810struct mlx5_reg_node_desc {
bd99fdea 811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 812};
813
814static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815{
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826}
827
e126ba97 828static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 829 struct ib_device_attr *props,
830 struct ib_udata *uhw)
e126ba97
EC		 831{
832 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 833 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 834 int err = -ENOMEM;
288c01b7 835 int max_sq_desc;
e126ba97
EC		 836 int max_rq_sg;
837 int max_sq_sg;
e0238a6a 838 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 839 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 840 struct mlx5_ib_query_device_resp resp = {};
841 size_t resp_len;
842 u64 max_tso;
e126ba97 843
402ca536
BW		 844 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
845 if (uhw->outlen && uhw->outlen < resp_len)
846 return -EINVAL;
847 else
848 resp.response_length = resp_len;
849
850 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 851 return -EINVAL;
852
1b5daf11
MD		 853 memset(props, 0, sizeof(*props));
854 err = mlx5_query_system_image_guid(ibdev,
855 &props->sys_image_guid);
856 if (err)
857 return err;
e126ba97 858
1b5daf11 859 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 860 if (err)
1b5daf11 861 return err;
e126ba97 862
1b5daf11
MD		 863 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
864 if (err)
865 return err;
e126ba97 866
9603b61d
JM		 867 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
868 (fw_rev_min(dev->mdev) << 16) |
869 fw_rev_sub(dev->mdev);
e126ba97
EC		 870 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
871 IB_DEVICE_PORT_ACTIVE_EVENT |
872 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 873 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 874
875 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 876 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 877 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 878 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 879 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 880 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 881 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 882 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 883 if (MLX5_CAP_GEN(mdev, imaicl)) {
884 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
885 IB_DEVICE_MEM_WINDOW_TYPE_2B;
886 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 887 /* We support 'Gappy' memory registration too */
888 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 889 }
e126ba97 890 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 891 if (MLX5_CAP_GEN(mdev, sho)) {
c0a6cbb9 892 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
2dea9094
SG		 893 /* At this stage no support for signature handover */
894 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
895 IB_PROT_T10DIF_TYPE_2 |
896 IB_PROT_T10DIF_TYPE_3;
897 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
898 IB_GUARD_T10DIF_CSUM;
899 }
938fe83c 900 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 901 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 902
85c7c014 903 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 904 if (MLX5_CAP_ETH(mdev, csum_cap)) {
905 /* Legacy bit to support old userspace libraries */
88115fe7 906 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 907 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
908 }
909
910 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
911 props->raw_packet_caps |=
912 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 913
402ca536
BW		 914 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
915 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
916 if (max_tso) {
917 resp.tso_caps.max_tso = 1 << max_tso;
918 resp.tso_caps.supported_qpts |=
919 1 << IB_QPT_RAW_PACKET;
920 resp.response_length += sizeof(resp.tso_caps);
921 }
922 }
31f69a82
YH		 923
924 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
925 resp.rss_caps.rx_hash_function =
926 MLX5_RX_HASH_FUNC_TOEPLITZ;
927 resp.rss_caps.rx_hash_fields_mask =
928 MLX5_RX_HASH_SRC_IPV4 |
929 MLX5_RX_HASH_DST_IPV4 |
930 MLX5_RX_HASH_SRC_IPV6 |
931 MLX5_RX_HASH_DST_IPV6 |
932 MLX5_RX_HASH_SRC_PORT_TCP |
933 MLX5_RX_HASH_DST_PORT_TCP |
934 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 935 MLX5_RX_HASH_DST_PORT_UDP |
936 MLX5_RX_HASH_INNER;
2d93fc85
MB		 937 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
938 MLX5_ACCEL_IPSEC_CAP_DEVICE)
939 resp.rss_caps.rx_hash_fields_mask |=
940 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 941 resp.response_length += sizeof(resp.rss_caps);
942 }
943 } else {
944 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
945 resp.response_length += sizeof(resp.tso_caps);
946 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
947 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 948 }
949
f0313965
ES		 950 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
951 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
952 props->device_cap_flags |= IB_DEVICE_UD_TSO;
953 }
954
03404e8a 955 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 956 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
957 raw_support)
03404e8a
MG		 958 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
959
1d54f890
YH		 960 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
961 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
962 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
963
cff5a0f3 964 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 965 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
966 raw_support) {
e8161334 967 /* Legacy bit to support old userspace libraries */
cff5a0f3 968 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 969 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
970 }
cff5a0f3 971
24da0016
AL		 972 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
973 props->max_dm_size =
974 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
975 }
976
da6d6ba3
MG		 977 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
978 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
979
b1383aa6
NO		 980 if (MLX5_CAP_GEN(mdev, end_pad))
981 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
982
1b5daf11
MD		 983 props->vendor_part_id = mdev->pdev->device;
984 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 985
986 props->max_mr_size = ~0ull;
e0238a6a 987 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 988 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
989 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
990 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
991 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 992 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
993 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
994 sizeof(struct mlx5_wqe_raddr_seg)) /
995 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 996 props->max_send_sge = max_sq_sg;
997 props->max_recv_sge = max_rq_sg;
986ef95e 998 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 999 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 1000 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 1001 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 1008 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 1009 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 1010 props->max_fast_reg_page_list_len =
1011 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 1012 props->max_pi_fast_reg_page_list_len =
1013 props->max_fast_reg_page_list_len / 2;
776a3906 1014 get_atomic_caps_qp(dev, props);
81bea28f 1015 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1016 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1017 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1018 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1019 props->max_mcast_grp;
1020 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1021 props->max_ah = INT_MAX;
7c60bcbb
MB		 1022 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1023 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1024
e502b8b0 1025 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
00815752 1026 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
e502b8b0
LR		 1027 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1028 props->odp_caps = dev->odp_caps;
1029 }
8cdd312c 1030
051f2630
LR		 1031 if (MLX5_CAP_GEN(mdev, cd))
1032 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1033
eff901d3
EC		 1034 if (!mlx5_core_is_pf(mdev))
1035 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1036
31f69a82 1037 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1038 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1039 props->rss_caps.max_rwq_indirection_tables =
1040 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1041 props->rss_caps.max_rwq_indirection_table_size =
1042 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1043 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1044 props->max_wq_type_rq =
1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1046 }
1047
eb761894 1048 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1049 props->tm_caps.max_num_tags =
eb761894 1050 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1051 props->tm_caps.max_ops =
eb761894 1052 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1053 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1054 }
1055
89705e92
DG		 1056 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1057 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1058 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1059 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1060 }
1061
87ab3f52
YC		 1062 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1063 props->cq_caps.max_cq_moderation_count =
1064 MLX5_MAX_CQ_COUNT;
1065 props->cq_caps.max_cq_moderation_period =
1066 MLX5_MAX_CQ_PERIOD;
1067 }
1068
7e43a2a5 1069 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
7e43a2a5 1070 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1071
1072 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1073 resp.cqe_comp_caps.max_num =
1074 MLX5_CAP_GEN(dev->mdev,
1075 cqe_compression_max_num);
1076
1077 resp.cqe_comp_caps.supported_format =
1078 MLX5_IB_CQE_RES_FORMAT_HASH |
1079 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1080
1081 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1082 resp.cqe_comp_caps.supported_format |=
1083 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1084 }
7e43a2a5
BW		 1085 }
1086
85c7c014
DJ		 1087 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1088 raw_support) {
d949167d
BW		 1089 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1090 MLX5_CAP_GEN(mdev, qos)) {
1091 resp.packet_pacing_caps.qp_rate_limit_max =
1092 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1093 resp.packet_pacing_caps.qp_rate_limit_min =
1094 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1095 resp.packet_pacing_caps.supported_qpts |=
1096 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1097 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1098 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1099 resp.packet_pacing_caps.cap_flags |=
1100 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1101 }
1102 resp.response_length += sizeof(resp.packet_pacing_caps);
1103 }
1104
9f885201
LR		 1105 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1106 uhw->outlen)) {
795b609c
BW		 1107 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1108 resp.mlx5_ib_support_multi_pkt_send_wqes =
1109 MLX5_IB_ALLOW_MPW;
050da902
BW		 1110
1111 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1112 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1113 MLX5_IB_SUPPORT_EMPW;
1114
9f885201
LR		 1115 resp.response_length +=
1116 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1117 }
1118
de57f2ad
GL		 1119 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1120 resp.response_length += sizeof(resp.flags);
7a0c8f42 1121
de57f2ad
GL		 1122 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1123 resp.flags |=
1124 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1125
1126 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1127 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1128 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1129 resp.flags |=
1130 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1131
1132 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1133 }
9f885201 1134
96dc3fc5
NO		 1135 if (field_avail(typeof(resp), sw_parsing_caps,
1136 uhw->outlen)) {
1137 resp.response_length += sizeof(resp.sw_parsing_caps);
1138 if (MLX5_CAP_ETH(mdev, swp)) {
1139 resp.sw_parsing_caps.sw_parsing_offloads |=
1140 MLX5_IB_SW_PARSING;
1141
1142 if (MLX5_CAP_ETH(mdev, swp_csum))
1143 resp.sw_parsing_caps.sw_parsing_offloads |=
1144 MLX5_IB_SW_PARSING_CSUM;
1145
1146 if (MLX5_CAP_ETH(mdev, swp_lso))
1147 resp.sw_parsing_caps.sw_parsing_offloads |=
1148 MLX5_IB_SW_PARSING_LSO;
1149
1150 if (resp.sw_parsing_caps.sw_parsing_offloads)
1151 resp.sw_parsing_caps.supported_qpts =
1152 BIT(IB_QPT_RAW_PACKET);
1153 }
1154 }
1155
85c7c014
DJ		 1156 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1157 raw_support) {
b4f34597
NO		 1158 resp.response_length += sizeof(resp.striding_rq_caps);
1159 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1165 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1166 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1167 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1168 resp.striding_rq_caps.supported_qpts =
1169 BIT(IB_QPT_RAW_PACKET);
1170 }
1171 }
1172
f95ef6cb
MG		 1173 if (field_avail(typeof(resp), tunnel_offloads_caps,
1174 uhw->outlen)) {
1175 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1176 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1177 resp.tunnel_offloads_caps |=
1178 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1179 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1180 resp.tunnel_offloads_caps |=
1181 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1182 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1183 resp.tunnel_offloads_caps |=
1184 MLX5_IB_TUNNELED_OFFLOADS_GRE;
e818e255
AL		 1185 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1186 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1187 resp.tunnel_offloads_caps |=
1188 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1189 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1190 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1191 resp.tunnel_offloads_caps |=
1192 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1193 }
1194
402ca536
BW		 1195 if (uhw->outlen) {
1196 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1197
1198 if (err)
1199 return err;
1200 }
1201
1b5daf11 1202 return 0;
e126ba97
EC		 1203}
1204
1b5daf11
MD		 1205enum mlx5_ib_width {
1206 MLX5_IB_WIDTH_1X = 1 << 0,
1207 MLX5_IB_WIDTH_2X = 1 << 1,
1208 MLX5_IB_WIDTH_4X = 1 << 2,
1209 MLX5_IB_WIDTH_8X = 1 << 3,
1210 MLX5_IB_WIDTH_12X = 1 << 4
1211};
1212
db7a691a 1213static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1214 u8 *ib_width)
e126ba97
EC		 1215{
1216 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1217
db7a691a 1218 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1219 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1220 else if (active_width & MLX5_IB_WIDTH_2X)
1221 *ib_width = IB_WIDTH_2X;
db7a691a 1222 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1223 *ib_width = IB_WIDTH_4X;
db7a691a 1224 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1225 *ib_width = IB_WIDTH_8X;
db7a691a 1226 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1227 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1228 else {
1229 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1230 (int)active_width);
db7a691a 1231 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1232 }
1233
db7a691a 1234 return;
1b5daf11 1235}
e126ba97 1236
1b5daf11
MD		 1237static int mlx5_mtu_to_ib_mtu(int mtu)
1238{
1239 switch (mtu) {
1240 case 256: return 1;
1241 case 512: return 2;
1242 case 1024: return 3;
1243 case 2048: return 4;
1244 case 4096: return 5;
1245 default:
1246 pr_warn("invalid mtu\n");
1247 return -1;
e126ba97 1248 }
1b5daf11 1249}
e126ba97 1250
1b5daf11
MD		 1251enum ib_max_vl_num {
1252 __IB_MAX_VL_0 = 1,
1253 __IB_MAX_VL_0_1 = 2,
1254 __IB_MAX_VL_0_3 = 3,
1255 __IB_MAX_VL_0_7 = 4,
1256 __IB_MAX_VL_0_14 = 5,
1257};
e126ba97 1258
1b5daf11
MD		 1259enum mlx5_vl_hw_cap {
1260 MLX5_VL_HW_0 = 1,
1261 MLX5_VL_HW_0_1 = 2,
1262 MLX5_VL_HW_0_2 = 3,
1263 MLX5_VL_HW_0_3 = 4,
1264 MLX5_VL_HW_0_4 = 5,
1265 MLX5_VL_HW_0_5 = 6,
1266 MLX5_VL_HW_0_6 = 7,
1267 MLX5_VL_HW_0_7 = 8,
1268 MLX5_VL_HW_0_14 = 15
1269};
e126ba97 1270
1b5daf11
MD		 1271static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1272 u8 *max_vl_num)
1273{
1274 switch (vl_hw_cap) {
1275 case MLX5_VL_HW_0:
1276 *max_vl_num = __IB_MAX_VL_0;
1277 break;
1278 case MLX5_VL_HW_0_1:
1279 *max_vl_num = __IB_MAX_VL_0_1;
1280 break;
1281 case MLX5_VL_HW_0_3:
1282 *max_vl_num = __IB_MAX_VL_0_3;
1283 break;
1284 case MLX5_VL_HW_0_7:
1285 *max_vl_num = __IB_MAX_VL_0_7;
1286 break;
1287 case MLX5_VL_HW_0_14:
1288 *max_vl_num = __IB_MAX_VL_0_14;
1289 break;
e126ba97 1290
1b5daf11
MD		 1291 default:
1292 return -EINVAL;
e126ba97 1293 }
e126ba97 1294
1b5daf11 1295 return 0;
e126ba97
EC		 1296}
1297
1b5daf11
MD		 1298static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1299 struct ib_port_attr *props)
e126ba97 1300{
1b5daf11
MD		 1301 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1302 struct mlx5_core_dev *mdev = dev->mdev;
1303 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1304 u16 max_mtu;
1305 u16 oper_mtu;
1b5daf11
MD		 1306 int err;
1307 u8 ib_link_width_oper;
1308 u8 vl_hw_cap;
e126ba97 1309
1b5daf11
MD		 1310 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1311 if (!rep) {
1312 err = -ENOMEM;
e126ba97 1313 goto out;
e126ba97 1314 }
e126ba97 1315
c4550c63 1316 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1317
1b5daf11 1318 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1319 if (err)
1320 goto out;
1321
1b5daf11
MD		 1322 props->lid = rep->lid;
1323 props->lmc = rep->lmc;
1324 props->sm_lid = rep->sm_lid;
1325 props->sm_sl = rep->sm_sl;
1326 props->state = rep->vport_state;
1327 props->phys_state = rep->port_physical_state;
1328 props->port_cap_flags = rep->cap_mask1;
1329 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1330 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1331 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1332 props->bad_pkey_cntr = rep->pkey_violation_counter;
1333 props->qkey_viol_cntr = rep->qkey_violation_counter;
1334 props->subnet_timeout = rep->subnet_timeout;
1335 props->init_type_reply = rep->init_type_reply;
e126ba97 1336
4106a758
MG		 1337 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1338 props->port_cap_flags2 = rep->cap_mask2;
1339
1b5daf11
MD		 1340 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1341 if (err)
e126ba97 1342 goto out;
e126ba97 1343
db7a691a
MG		 1344 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1345
d5beb7f2 1346 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1347 if (err)
1348 goto out;
1349
facc9699 1350 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1351
1b5daf11 1352 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1353
facc9699 1354 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1355
1b5daf11 1356 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1357
1b5daf11
MD		 1358 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1359 if (err)
1360 goto out;
e126ba97 1361
1b5daf11
MD		 1362 err = translate_max_vl_num(ibdev, vl_hw_cap,
1363 &props->max_vl_num);
e126ba97 1364out:
1b5daf11 1365 kfree(rep);
e126ba97
EC		 1366 return err;
1367}
1368
1b5daf11
MD		 1369int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1370 struct ib_port_attr *props)
e126ba97 1371{
095b0927
IT		 1372 unsigned int count;
1373 int ret;
1374
1b5daf11
MD		 1375 switch (mlx5_get_vport_access_method(ibdev)) {
1376 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1377 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1378 break;
e126ba97 1379
1b5daf11 1380 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1381 ret = mlx5_query_hca_port(ibdev, port, props);
1382 break;
e126ba97 1383
3f89a643 1384 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1385 ret = mlx5_query_port_roce(ibdev, port, props);
1386 break;
3f89a643 1387
1b5daf11 1388 default:
095b0927
IT		 1389 ret = -EINVAL;
1390 }
1391
1392 if (!ret && props) {
b3cbd6f0
DJ		 1393 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394 struct mlx5_core_dev *mdev;
1395 bool put_mdev = true;
1396
1397 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1398 if (!mdev) {
1399 /* If the port isn't affiliated yet query the master.
1400 * The master and slave will have the same values.
1401 */
1402 mdev = dev->mdev;
1403 port = 1;
1404 put_mdev = false;
1405 }
1406 count = mlx5_core_reserved_gids_count(mdev);
1407 if (put_mdev)
1408 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1409 props->gid_tbl_len -= count;
1b5daf11 1410 }
095b0927 1411 return ret;
1b5daf11 1412}
e126ba97 1413
8e6efa3a
MB		 1414static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1415 struct ib_port_attr *props)
1416{
1417 int ret;
1418
26628e2d
MB		 1419 /* Only link layer == ethernet is valid for representors
1420 * and we always use port 1
1421 */
8e6efa3a
MB		 1422 ret = mlx5_query_port_roce(ibdev, port, props);
1423 if (ret || !props)
1424 return ret;
1425
1426 /* We don't support GIDS */
1427 props->gid_tbl_len = 0;
1428
1429 return ret;
1430}
1431
1b5daf11
MD		 1432static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1433 union ib_gid *gid)
1434{
1435 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1436 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1437
1b5daf11
MD		 1438 switch (mlx5_get_vport_access_method(ibdev)) {
1439 case MLX5_VPORT_ACCESS_METHOD_MAD:
1440 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1441
1b5daf11
MD		 1442 case MLX5_VPORT_ACCESS_METHOD_HCA:
1443 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1444
1445 default:
1446 return -EINVAL;
1447 }
e126ba97 1448
e126ba97
EC		 1449}
1450
b3cbd6f0
DJ		 1451static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1452 u16 index, u16 *pkey)
1b5daf11
MD		 1453{
1454 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1455 struct mlx5_core_dev *mdev;
1456 bool put_mdev = true;
1457 u8 mdev_port_num;
1458 int err;
1b5daf11 1459
b3cbd6f0
DJ		 1460 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1461 if (!mdev) {
1462 /* The port isn't affiliated yet, get the PKey from the master
1463 * port. For RoCE the PKey tables will be the same.
1464 */
1465 put_mdev = false;
1466 mdev = dev->mdev;
1467 mdev_port_num = 1;
1468 }
1469
1470 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1471 index, pkey);
1472 if (put_mdev)
1473 mlx5_ib_put_native_port_mdev(dev, port);
1474
1475 return err;
1476}
1477
1478static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1479 u16 *pkey)
1480{
1b5daf11
MD		 1481 switch (mlx5_get_vport_access_method(ibdev)) {
1482 case MLX5_VPORT_ACCESS_METHOD_MAD:
1483 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1484
1485 case MLX5_VPORT_ACCESS_METHOD_HCA:
1486 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1487 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1488 default:
1489 return -EINVAL;
1490 }
1491}
e126ba97
EC		 1492
1493static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1494 struct ib_device_modify *props)
1495{
1496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1497 struct mlx5_reg_node_desc in;
1498 struct mlx5_reg_node_desc out;
1499 int err;
1500
1501 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1502 return -EOPNOTSUPP;
1503
1504 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1505 return 0;
1506
1507 /*
1508 * If possible, pass node desc to FW, so it can generate
1509 * a 144 trap. If cmd fails, just ignore.
1510 */
bd99fdea 1511 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1512 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1513 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1514 if (err)
1515 return err;
1516
bd99fdea 1517 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1518
1519 return err;
1520}
1521
cdbe33d0
EC		 1522static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1523 u32 value)
1524{
1525 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1526 struct mlx5_core_dev *mdev;
1527 u8 mdev_port_num;
cdbe33d0
EC		 1528 int err;
1529
b3cbd6f0
DJ		 1530 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1531 if (!mdev)
1532 return -ENODEV;
1533
1534 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1535 if (err)
b3cbd6f0 1536 goto out;
cdbe33d0
EC		 1537
1538 if (~ctx.cap_mask1_perm & mask) {
1539 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1540 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1541 err = -EINVAL;
1542 goto out;
cdbe33d0
EC		 1543 }
1544
1545 ctx.cap_mask1 = value;
1546 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1547 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1548 0, &ctx);
1549
1550out:
1551 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1552
1553 return err;
1554}
1555
e126ba97
EC		 1556static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1557 struct ib_port_modify *props)
1558{
1559 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1560 struct ib_port_attr attr;
1561 u32 tmp;
1562 int err;
cdbe33d0
EC		 1563 u32 change_mask;
1564 u32 value;
1565 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1566 IB_LINK_LAYER_INFINIBAND);
1567
ec255879
MD		 1568 /* CM layer calls ib_modify_port() regardless of the link layer. For
1569 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1570 */
1571 if (!is_ib)
1572 return 0;
1573
cdbe33d0
EC		 1574 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1575 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1577 return set_port_caps_atomic(dev, port, change_mask, value);
1578 }
e126ba97
EC		 1579
1580 mutex_lock(&dev->cap_mask_mutex);
1581
c4550c63 1582 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1583 if (err)
1584 goto out;
1585
1586 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587 ~props->clr_port_cap_mask;
1588
9603b61d 1589 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1590
1591out:
1592 mutex_unlock(&dev->cap_mask_mutex);
1593 return err;
1594}
1595
30aa60b3
EC		 1596static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1597{
1598 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1599 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1600}
1601
31a78a5a
YH		 1602static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1603{
1604 /* Large page with non 4k uar support might limit the dynamic size */
1605 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1606 return MLX5_MIN_DYN_BFREGS;
1607
1608 return MLX5_MAX_DYN_BFREGS;
1609}
1610
b037c29a
EC		 1611static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1612 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1613 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1614{
1615 int uars_per_sys_page;
1616 int bfregs_per_sys_page;
1617 int ref_bfregs = req->total_num_bfregs;
1618
1619 if (req->total_num_bfregs == 0)
1620 return -EINVAL;
1621
1622 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1623 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1624
1625 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1626 return -ENOMEM;
1627
1628 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1629 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1630 /* This holds the required static allocation asked by the user */
b037c29a 1631 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1632 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1633 return -EINVAL;
1634
31a78a5a
YH		 1635 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1636 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1637 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1638 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1639
1640 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1641 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1642 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1643 req->total_num_bfregs, bfregi->total_num_bfregs,
1644 bfregi->num_sys_pages);
b037c29a
EC		 1645
1646 return 0;
1647}
1648
1649static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1650{
1651 struct mlx5_bfreg_info *bfregi;
1652 int err;
1653 int i;
1654
1655 bfregi = &context->bfregi;
31a78a5a 1656 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1657 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1658 if (err)
1659 goto error;
1660
1661 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1662 }
4ed131d0
YH		 1663
1664 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1665 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1666
b037c29a
EC		 1667 return 0;
1668
1669error:
1670 for (--i; i >= 0; i--)
1671 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1672 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1673
1674 return err;
1675}
1676
15177999
LR		 1677static void deallocate_uars(struct mlx5_ib_dev *dev,
1678 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1679{
1680 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1681 int i;
1682
1683 bfregi = &context->bfregi;
15177999 1684 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1685 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1686 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1687 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1688}
1689
0042f9e4 1690int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1691{
1692 int err = 0;
1693
1694 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1695 if (td)
1696 dev->lb.user_td++;
1697 if (qp)
1698 dev->lb.qps++;
1699
1700 if (dev->lb.user_td == 2 ||
1701 dev->lb.qps == 1) {
1702 if (!dev->lb.enabled) {
1703 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1704 dev->lb.enabled = true;
1705 }
1706 }
a560f1d9
MB		 1707
1708 mutex_unlock(&dev->lb.mutex);
1709
1710 return err;
1711}
1712
0042f9e4 1713void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1714{
1715 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1716 if (td)
1717 dev->lb.user_td--;
1718 if (qp)
1719 dev->lb.qps--;
1720
1721 if (dev->lb.user_td == 1 &&
1722 dev->lb.qps == 0) {
1723 if (dev->lb.enabled) {
1724 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1725 dev->lb.enabled = false;
1726 }
1727 }
a560f1d9
MB		 1728
1729 mutex_unlock(&dev->lb.mutex);
1730}
1731
d2d19121
YH		 1732static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1733 u16 uid)
c85023e1
HN		 1734{
1735 int err;
1736
cfdeb893
LR		 1737 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1738 return 0;
1739
d2d19121 1740 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1741 if (err)
1742 return err;
1743
1744 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1745 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1746 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1747 return err;
1748
0042f9e4 1749 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1750}
1751
d2d19121
YH		 1752static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1753 u16 uid)
c85023e1 1754{
cfdeb893
LR		 1755 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1756 return;
1757
d2d19121 1758 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1759
1760 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1761 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1762 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1763 return;
1764
0042f9e4 1765 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1766}
1767
a2a074ef
LR		 1768static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1769 struct ib_udata *udata)
e126ba97 1770{
a2a074ef 1771 struct ib_device *ibdev = uctx->device;
e126ba97 1772 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1773 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1774 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1775 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1776 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1777 struct mlx5_bfreg_info *bfregi;
78c0f98c 1778 int ver;
e126ba97 1779 int err;
a168a41c
MD		 1780 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1781 max_cqe_version);
25bb36e7 1782 u32 dump_fill_mkey;
b037c29a 1783 bool lib_uar_4k;
e126ba97
EC		 1784
1785 if (!dev->ib_active)
a2a074ef 1786 return -EAGAIN;
e126ba97 1787
e093111d 1788 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1789 ver = 0;
e093111d 1790 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1791 ver = 2;
1792 else
a2a074ef 1793 return -EINVAL;
78c0f98c 1794
e093111d 1795 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1796 if (err)
a2a074ef 1797 return err;
e126ba97 1798
a8b92ca1 1799 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1800 return -EOPNOTSUPP;
78c0f98c 1801
f72300c5 1802 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1803 return -EOPNOTSUPP;
b368d7cb 1804
2f5ff264
EC		 1805 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1806 MLX5_NON_FP_BFREGS_PER_UAR);
1807 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1808 return -EINVAL;
e126ba97 1809
938fe83c 1810 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1811 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1812 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1813 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1814 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1815 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1816 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1817 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1818 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1819 resp.cqe_version = min_t(__u8,
1820 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1821 req.max_cqe_version);
30aa60b3
EC		 1822 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1823 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1824 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1825 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1826 resp.response_length = min(offsetof(typeof(resp), response_length) +
1827 sizeof(resp.response_length), udata->outlen);
e126ba97 1828
c03faa56
MB		 1829 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1830 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1831 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1832 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1833 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1834 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1835 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1836 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1837 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1838 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1839 }
1840
30aa60b3 1841 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1842 bfregi = &context->bfregi;
b037c29a
EC		 1843
1844 /* updates req->total_num_bfregs */
31a78a5a 1845 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1846 if (err)
e126ba97 1847 goto out_ctx;
e126ba97 1848
b037c29a
EC		 1849 mutex_init(&bfregi->lock);
1850 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1851 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1852 GFP_KERNEL);
b037c29a 1853 if (!bfregi->count) {
e126ba97 1854 err = -ENOMEM;
b037c29a 1855 goto out_ctx;
e126ba97
EC		 1856 }
1857
b037c29a
EC		 1858 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1859 sizeof(*bfregi->sys_pages),
1860 GFP_KERNEL);
1861 if (!bfregi->sys_pages) {
e126ba97 1862 err = -ENOMEM;
b037c29a 1863 goto out_count;
e126ba97
EC		 1864 }
1865
b037c29a
EC		 1866 err = allocate_uars(dev, context);
1867 if (err)
1868 goto out_sys_pages;
e126ba97 1869
a8b92ca1 1870 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1871 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1872 if (err < 0)
d2d19121 1873 goto out_uars;
76dc5a84 1874 context->devx_uid = err;
a8b92ca1
YH		 1875 }
1876
d2d19121
YH		 1877 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1878 context->devx_uid);
1879 if (err)
1880 goto out_devx;
1881
25bb36e7
YC		 1882 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1883 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1884 if (err)
8193abb6 1885 goto out_mdev;
25bb36e7
YC		 1886 }
1887
e126ba97
EC		 1888 INIT_LIST_HEAD(&context->db_page_list);
1889 mutex_init(&context->db_page_mutex);
1890
2f5ff264 1891 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1892 resp.num_ports = dev->num_ports;
b368d7cb 1893
f72300c5
HA		 1894 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1895 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1896
402ca536 1897 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1898 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1899 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1900 resp.response_length += sizeof(resp.cmds_supp_uhw);
1901 }
1902
78984898
OG		 1903 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1904 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1905 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1906 resp.eth_min_inline++;
1907 }
1908 resp.response_length += sizeof(resp.eth_min_inline);
1909 }
1910
5c99eaec
FD		 1911 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1912 if (mdev->clock_info)
1913 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1914 resp.response_length += sizeof(resp.clock_info_versions);
1915 }
1916
bc5c6eed
NO		 1917 /*
1918 * We don't want to expose information from the PCI bar that is located
1919 * after 4096 bytes, so if the arch only supports larger pages, let's
1920 * pretend we don't support reading the HCA's core clock. This is also
1921 * forced by mmap function.
1922 */
de8d6e02
EC		 1923 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1924 if (PAGE_SIZE <= 4096) {
1925 resp.comp_mask |=
1926 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1927 resp.hca_core_clock_offset =
1928 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1929 }
5c99eaec 1930 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1931 }
1932
30aa60b3
EC		 1933 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1934 resp.response_length += sizeof(resp.log_uar_size);
1935
1936 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1937 resp.response_length += sizeof(resp.num_uars_per_page);
1938
31a78a5a
YH		 1939 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1940 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1941 resp.response_length += sizeof(resp.num_dyn_bfregs);
1942 }
1943
25bb36e7
YC		 1944 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1945 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1946 resp.dump_fill_mkey = dump_fill_mkey;
1947 resp.comp_mask |=
1948 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1949 }
1950 resp.response_length += sizeof(resp.dump_fill_mkey);
1951 }
1952
b368d7cb 1953 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1954 if (err)
a8b92ca1 1955 goto out_mdev;
e126ba97 1956
2f5ff264
EC		 1957 bfregi->ver = ver;
1958 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1959 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1960 context->lib_caps = req.lib_caps;
1961 print_lib_caps(dev, context->lib_caps);
f72300c5 1962
7c34ec19 1963 if (dev->lag_active) {
95579e78 1964 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1965
1966 atomic_set(&context->tx_port_affinity,
1967 atomic_add_return(
95579e78 1968 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1969 }
1970
a2a074ef 1971 return 0;
e126ba97 1972
a8b92ca1 1973out_mdev:
d2d19121
YH		 1974 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1975out_devx:
a8b92ca1 1976 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1977 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1978
e126ba97 1979out_uars:
b037c29a 1980 deallocate_uars(dev, context);
e126ba97 1981
b037c29a
EC		 1982out_sys_pages:
1983 kfree(bfregi->sys_pages);
e126ba97 1984
b037c29a
EC		 1985out_count:
1986 kfree(bfregi->count);
e126ba97
EC		 1987
1988out_ctx:
a2a074ef 1989 return err;
e126ba97
EC		 1990}
1991
a2a074ef 1992static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 1993{
1994 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1995 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1996 struct mlx5_bfreg_info *bfregi;
e126ba97 1997
b037c29a 1998 bfregi = &context->bfregi;
d2d19121
YH		 1999 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2000
a8b92ca1 2001 if (context->devx_uid)
76dc5a84 2002 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2003
b037c29a
EC		 2004 deallocate_uars(dev, context);
2005 kfree(bfregi->sys_pages);
2f5ff264 2006 kfree(bfregi->count);
e126ba97
EC		 2007}
2008
b037c29a 2009static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2010 int uar_idx)
e126ba97 2011{
b037c29a
EC		 2012 int fw_uars_per_page;
2013
2014 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2015
aa8106f1 2016 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2017}
2018
2019static int get_command(unsigned long offset)
2020{
2021 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2022}
2023
2024static int get_arg(unsigned long offset)
2025{
2026 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2027}
2028
2029static int get_index(unsigned long offset)
2030{
2031 return get_arg(offset);
2032}
2033
4ed131d0
YH		 2034/* Index resides in an extra byte to enable larger values than 255 */
2035static int get_extended_index(unsigned long offset)
2036{
2037 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2038}
2039
7c2344c3
MG		 2040
2041static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2042{
7c2344c3
MG		 2043}
2044
37aa5c36
GL		 2045static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2046{
2047 switch (cmd) {
2048 case MLX5_IB_MMAP_WC_PAGE:
2049 return "WC";
2050 case MLX5_IB_MMAP_REGULAR_PAGE:
2051 return "best effort WC";
2052 case MLX5_IB_MMAP_NC_PAGE:
2053 return "NC";
24da0016
AL		 2054 case MLX5_IB_MMAP_DEVICE_MEM:
2055 return "Device Memory";
37aa5c36
GL		 2056 default:
2057 return NULL;
2058 }
2059}
2060
5c99eaec
FD		 2061static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2062 struct vm_area_struct *vma,
2063 struct mlx5_ib_ucontext *context)
2064{
4eb6ab13
JG		 2065 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2066 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2067 return -EINVAL;
2068
2069 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2070 return -EOPNOTSUPP;
2071
4eb6ab13 2072 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2073 return -EPERM;
c660133c 2074 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2075
ddcdc368 2076 if (!dev->mdev->clock_info)
5c99eaec
FD		 2077 return -EOPNOTSUPP;
2078
4eb6ab13
JG		 2079 return vm_insert_page(vma, vma->vm_start,
2080 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2081}
2082
37aa5c36 2083static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2084 struct vm_area_struct *vma,
2085 struct mlx5_ib_ucontext *context)
37aa5c36 2086{
2f5ff264 2087 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2088 int err;
2089 unsigned long idx;
aa09ea6e 2090 phys_addr_t pfn;
37aa5c36 2091 pgprot_t prot;
4ed131d0
YH		 2092 u32 bfreg_dyn_idx = 0;
2093 u32 uar_index;
2094 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2095 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2096 bfregi->num_static_sys_pages;
b037c29a
EC		 2097
2098 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2099 return -EINVAL;
2100
4ed131d0
YH		 2101 if (dyn_uar)
2102 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2103 else
2104 idx = get_index(vma->vm_pgoff);
2105
2106 if (idx >= max_valid_idx) {
2107 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2108 idx, max_valid_idx);
b037c29a
EC		 2109 return -EINVAL;
2110 }
37aa5c36
GL		 2111
2112 switch (cmd) {
2113 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2114 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2115/* Some architectures don't support WC memory */
2116#if defined(CONFIG_X86)
2117 if (!pat_enabled())
2118 return -EPERM;
2119#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2120 return -EPERM;
2121#endif
2122 /* fall through */
2123 case MLX5_IB_MMAP_REGULAR_PAGE:
2124 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2125 prot = pgprot_writecombine(vma->vm_page_prot);
2126 break;
2127 case MLX5_IB_MMAP_NC_PAGE:
2128 prot = pgprot_noncached(vma->vm_page_prot);
2129 break;
2130 default:
2131 return -EINVAL;
2132 }
2133
4ed131d0
YH		 2134 if (dyn_uar) {
2135 int uars_per_page;
2136
2137 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2138 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2139 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2140 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2141 bfreg_dyn_idx, bfregi->total_num_bfregs);
2142 return -EINVAL;
2143 }
2144
2145 mutex_lock(&bfregi->lock);
2146 /* Fail if uar already allocated, first bfreg index of each
2147 * page holds its count.
2148 */
2149 if (bfregi->count[bfreg_dyn_idx]) {
2150 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2151 mutex_unlock(&bfregi->lock);
2152 return -EINVAL;
2153 }
2154
2155 bfregi->count[bfreg_dyn_idx]++;
2156 mutex_unlock(&bfregi->lock);
2157
2158 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2159 if (err) {
2160 mlx5_ib_warn(dev, "UAR alloc failed\n");
2161 goto free_bfreg;
2162 }
2163 } else {
2164 uar_index = bfregi->sys_pages[idx];
2165 }
2166
2167 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2168 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2169
e2cd1d1a
JG		 2170 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2171 prot);
37aa5c36 2172 if (err) {
8f062287 2173 mlx5_ib_err(dev,
e2cd1d1a 2174 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2175 err, mmap_cmd2str(cmd));
4ed131d0 2176 goto err;
37aa5c36
GL		 2177 }
2178
4ed131d0
YH		 2179 if (dyn_uar)
2180 bfregi->sys_pages[idx] = uar_index;
2181 return 0;
2182
2183err:
2184 if (!dyn_uar)
2185 return err;
2186
2187 mlx5_cmd_free_uar(dev->mdev, idx);
2188
2189free_bfreg:
2190 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2191
2192 return err;
37aa5c36
GL		 2193}
2194
24da0016
AL		 2195static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2196{
2197 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2198 struct mlx5_ib_dev *dev = to_mdev(context->device);
2199 u16 page_idx = get_extended_index(vma->vm_pgoff);
2200 size_t map_size = vma->vm_end - vma->vm_start;
2201 u32 npages = map_size >> PAGE_SHIFT;
2202 phys_addr_t pfn;
24da0016
AL		 2203
2204 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2205 page_idx + npages)
2206 return -EINVAL;
2207
aa8106f1 2208 pfn = ((dev->mdev->bar_addr +
24da0016
AL		 2209 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2210 PAGE_SHIFT) +
2211 page_idx;
e2cd1d1a
JG		 2212 return rdma_user_mmap_io(context, vma, pfn, map_size,
2213 pgprot_writecombine(vma->vm_page_prot));
24da0016
AL		 2214}
2215
e126ba97
EC		 2216static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2217{
2218 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2219 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2220 unsigned long command;
e126ba97
EC		 2221 phys_addr_t pfn;
2222
2223 command = get_command(vma->vm_pgoff);
2224 switch (command) {
37aa5c36
GL		 2225 case MLX5_IB_MMAP_WC_PAGE:
2226 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2227 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2228 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2229 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2230
2231 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2232 return -ENOSYS;
2233
d69e3bcf 2234 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2235 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2236 return -EINVAL;
2237
6cbac1e4 2238 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2239 return -EPERM;
c660133c 2240 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2241
2242 /* Don't expose to user-space information it shouldn't have */
2243 if (PAGE_SIZE > 4096)
2244 return -EOPNOTSUPP;
2245
d69e3bcf
MB		 2246 pfn = (dev->mdev->iseg_base +
2247 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2248 PAGE_SHIFT;
d5e560d3
JG		 2249 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2250 PAGE_SIZE,
2251 pgprot_noncached(vma->vm_page_prot));
5c99eaec
FD		 2252 case MLX5_IB_MMAP_CLOCK_INFO:
2253 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2254
24da0016
AL		 2255 case MLX5_IB_MMAP_DEVICE_MEM:
2256 return dm_mmap(ibcontext, vma);
2257
e126ba97
EC		 2258 default:
2259 return -EINVAL;
2260 }
2261
2262 return 0;
2263}
2264
25c13324
AL		 2265static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2266 u32 type)
24da0016 2267{
25c13324
AL		 2268 switch (type) {
2269 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2270 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2271 return -EOPNOTSUPP;
2272 break;
2273 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4 2274 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
25c13324
AL		 2275 if (!capable(CAP_SYS_RAWIO) ||
2276 !capable(CAP_NET_RAW))
2277 return -EPERM;
2278
2279 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2280 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2281 return -EOPNOTSUPP;
2282 break;
2283 }
2284
2285 return 0;
2286}
2287
3b113a1e
AL		 2288static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2289 struct mlx5_ib_dm *dm,
2290 struct ib_dm_alloc_attr *attr,
2291 struct uverbs_attr_bundle *attrs)
24da0016 2292{
3b113a1e 2293 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016
AL		 2294 u64 start_offset;
2295 u32 page_idx;
2296 int err;
2297
3b113a1e 2298 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2299
3b113a1e
AL		 2300 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2301 dm->size, attr->alignment);
24da0016 2302 if (err)
3b113a1e 2303 return err;
24da0016 2304
3b113a1e
AL		 2305 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2306 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
24da0016
AL		 2307 PAGE_SHIFT;
2308
2309 err = uverbs_copy_to(attrs,
3b113a1e
AL		 2310 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2311 &page_idx, sizeof(page_idx));
24da0016
AL		 2312 if (err)
2313 goto err_dealloc;
2314
3b113a1e 2315 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2316 err = uverbs_copy_to(attrs,
2317 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2318 &start_offset, sizeof(start_offset));
2319 if (err)
2320 goto err_dealloc;
2321
3b113a1e
AL		 2322 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2323 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2324
2325 return 0;
2326
2327err_dealloc:
2328 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2329
2330 return err;
2331}
2332
25c13324
AL		 2333static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2334 struct mlx5_ib_dm *dm,
2335 struct ib_dm_alloc_attr *attr,
2336 struct uverbs_attr_bundle *attrs,
2337 int type)
2338{
c9b9dcb4 2339 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
25c13324
AL		 2340 u64 act_size;
2341 int err;
2342
2343 /* Allocation size must a multiple of the basic block size
2344 * and a power of 2.
2345 */
c9b9dcb4 2346 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
25c13324
AL		 2347 act_size = roundup_pow_of_two(act_size);
2348
2349 dm->size = act_size;
c9b9dcb4
AL		 2350 err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2351 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2352 &dm->icm_dm.obj_id);
25c13324
AL		 2353 if (err)
2354 return err;
2355
24da0016 2356 err = uverbs_copy_to(attrs,
25c13324
AL		 2357 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2358 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2359 if (err)
c9b9dcb4
AL		 2360 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2361 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2362 dm->icm_dm.obj_id);
25c13324
AL		 2363
2364 return err;
2365}
2366
3b113a1e
AL		 2367struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2368 struct ib_ucontext *context,
2369 struct ib_dm_alloc_attr *attr,
2370 struct uverbs_attr_bundle *attrs)
2371{
2372 struct mlx5_ib_dm *dm;
2373 enum mlx5_ib_uapi_dm_type type;
2374 int err;
24da0016 2375
3b113a1e
AL		 2376 err = uverbs_get_const_default(&type, attrs,
2377 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2378 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2379 if (err)
2380 return ERR_PTR(err);
24da0016 2381
3b113a1e
AL		 2382 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2383 type, attr->length, attr->alignment);
2384
25c13324
AL		 2385 err = check_dm_type_support(to_mdev(ibdev), type);
2386 if (err)
2387 return ERR_PTR(err);
2388
3b113a1e
AL		 2389 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2390 if (!dm)
2391 return ERR_PTR(-ENOMEM);
2392
2393 dm->type = type;
2394
2395 switch (type) {
2396 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2397 err = handle_alloc_dm_memic(context, dm,
2398 attr,
2399 attrs);
2400 break;
25c13324 2401 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2402 err = handle_alloc_dm_sw_icm(context, dm,
2403 attr, attrs,
2404 MLX5_SW_ICM_TYPE_STEERING);
2405 break;
25c13324 2406 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2407 err = handle_alloc_dm_sw_icm(context, dm,
2408 attr, attrs,
2409 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
25c13324 2410 break;
3b113a1e
AL		 2411 default:
2412 err = -EOPNOTSUPP;
2413 }
24da0016 2414
3b113a1e
AL		 2415 if (err)
2416 goto err_free;
24da0016
AL		 2417
2418 return &dm->ibdm;
2419
24da0016
AL		 2420err_free:
2421 kfree(dm);
2422 return ERR_PTR(err);
2423}
2424
c4367a26 2425int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2426{
25c13324
AL		 2427 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2428 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
c9b9dcb4 2429 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
3b113a1e 2430 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
24da0016 2431 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2432 u32 page_idx;
2433 int ret;
2434
3b113a1e
AL		 2435 switch (dm->type) {
2436 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2437 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2438 if (ret)
2439 return ret;
24da0016 2440
c9b9dcb4
AL		 2441 page_idx = (dm->dev_addr - pci_resource_start(dev->pdev, 0) -
2442 MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr)) >>
2443 PAGE_SHIFT;
25c13324
AL		 2444 bitmap_clear(ctx->dm_pages, page_idx,
2445 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2446 break;
2447 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2448 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2449 dm->size, ctx->devx_uid, dm->dev_addr,
2450 dm->icm_dm.obj_id);
2451 if (ret)
2452 return ret;
2453 break;
25c13324 2454 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2455 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2456 dm->size, ctx->devx_uid, dm->dev_addr,
2457 dm->icm_dm.obj_id);
25c13324
AL		 2458 if (ret)
2459 return ret;
3b113a1e
AL		 2460 break;
2461 default:
2462 return -EOPNOTSUPP;
2463 }
24da0016
AL		 2464
2465 kfree(dm);
2466
2467 return 0;
2468}
2469
ff23dfa1 2470static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2471{
21a428a0
LR		 2472 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2473 struct ib_device *ibdev = ibpd->device;
e126ba97 2474 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2475 int err;
a1069c1c
YH		 2476 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2477 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2478 u16 uid = 0;
ff23dfa1
SR		 2479 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2480 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2481
ff23dfa1 2482 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2483 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2484 MLX5_SET(alloc_pd_in, in, uid, uid);
2485 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2486 out, sizeof(out));
21a428a0
LR		 2487 if (err)
2488 return err;
e126ba97 2489
a1069c1c
YH		 2490 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2491 pd->uid = uid;
ff23dfa1 2492 if (udata) {
e126ba97
EC		 2493 resp.pdn = pd->pdn;
2494 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2495 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2496 return -EFAULT;
e126ba97 2497 }
e126ba97
EC		 2498 }
2499
21a428a0 2500 return 0;
e126ba97
EC		 2501}
2502
c4367a26 2503static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2504{
2505 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2506 struct mlx5_ib_pd *mpd = to_mpd(pd);
2507
a1069c1c 2508 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2509}
2510
466fa6d2
MG		 2511enum {
2512 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2513 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2514 MATCH_CRITERIA_ENABLE_INNER_BIT,
2515 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2516};
2517
2518#define HEADER_IS_ZERO(match_criteria, headers) \
2519 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2520 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2521
466fa6d2 2522static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2523{
466fa6d2 2524 u8 match_criteria_enable;
038d2ef8 2525
466fa6d2
MG		 2526 match_criteria_enable =
2527 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2528 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2529 match_criteria_enable |=
2530 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2531 MATCH_CRITERIA_ENABLE_MISC_BIT;
2532 match_criteria_enable |=
2533 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2534 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2535 match_criteria_enable |=
2536 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2537 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2538
2539 return match_criteria_enable;
038d2ef8
MG		 2540}
2541
6113cc44 2542static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2543{
6113cc44
MG		 2544 u8 entry_mask;
2545 u8 entry_val;
2546 int err = 0;
2547
2548 if (!mask)
2549 goto out;
2550
2551 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2552 ip_protocol);
2553 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2554 ip_protocol);
2555 if (!entry_mask) {
2556 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2557 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2558 goto out;
2559 }
2560 /* Don't override existing ip protocol */
2561 if (mask != entry_mask || val != entry_val)
2562 err = -EINVAL;
2563out:
2564 return err;
038d2ef8
MG		 2565}
2566
37da2a03 2567static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2568 bool inner)
2569{
2570 if (inner) {
2571 MLX5_SET(fte_match_set_misc,
2572 misc_c, inner_ipv6_flow_label, mask);
2573 MLX5_SET(fte_match_set_misc,
2574 misc_v, inner_ipv6_flow_label, val);
2575 } else {
2576 MLX5_SET(fte_match_set_misc,
2577 misc_c, outer_ipv6_flow_label, mask);
2578 MLX5_SET(fte_match_set_misc,
2579 misc_v, outer_ipv6_flow_label, val);
2580 }
2581}
2582
ca0d4753
MG		 2583static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2584{
2585 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2586 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2587 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2588 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2589}
2590
71c6e863
AL		 2591static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2592{
2593 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2594 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2595 return -EOPNOTSUPP;
2596
2597 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2598 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2599 return -EOPNOTSUPP;
2600
2601 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2602 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2603 return -EOPNOTSUPP;
2604
2605 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2606 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2607 return -EOPNOTSUPP;
2608
2609 return 0;
2610}
2611
c47ac6ae
MG		 2612#define LAST_ETH_FIELD vlan_tag
2613#define LAST_IB_FIELD sl
ca0d4753 2614#define LAST_IPV4_FIELD tos
466fa6d2 2615#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2616#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2617#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2618#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2619#define LAST_DROP_FIELD size
3b3233fb 2620#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2621
2622/* Field is the last supported field */
2623#define FIELDS_NOT_SUPPORTED(filter, field)\
2624 memchr_inv((void *)&filter.field +\
2625 sizeof(filter.field), 0,\
2626 sizeof(filter) -\
2627 offsetof(typeof(filter), field) -\
2628 sizeof(filter.field))
2629
2ea26203
MB		 2630int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2631 bool is_egress,
2632 struct mlx5_flow_act *action)
802c2125 2633{
802c2125
AY		 2634
2635 switch (maction->ib_action.type) {
2636 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2637 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2638 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2639 return -EINVAL;
802c2125
AY		 2640 /* Currently only AES_GCM keymat is supported by the driver */
2641 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2642 action->action |= is_egress ?
802c2125
AY		 2643 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2644 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2645 return 0;
b1085be3
MB		 2646 case IB_FLOW_ACTION_UNSPECIFIED:
2647 if (maction->flow_action_raw.sub_type ==
2648 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2649 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2650 return -EINVAL;
b1085be3 2651 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2b688ea5
MG		 2652 action->modify_hdr =
2653 maction->flow_action_raw.modify_hdr;
b1085be3
MB		 2654 return 0;
2655 }
10a30896
MB		 2656 if (maction->flow_action_raw.sub_type ==
2657 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2658 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2659 return -EINVAL;
10a30896
MB		 2660 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2661 return 0;
2662 }
e806f932
MB		 2663 if (maction->flow_action_raw.sub_type ==
2664 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2665 if (action->action &
2666 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2667 return -EINVAL;
e806f932
MB		 2668 action->action |=
2669 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2b688ea5
MG		 2670 action->pkt_reformat =
2671 maction->flow_action_raw.pkt_reformat;
e806f932
MB		 2672 return 0;
2673 }
b1085be3 2674 /* fall through */
802c2125
AY		 2675 default:
2676 return -EOPNOTSUPP;
2677 }
2678}
2679
bb0ee7dc
JL		 2680static int parse_flow_attr(struct mlx5_core_dev *mdev,
2681 struct mlx5_flow_spec *spec,
2682 const union ib_flow_spec *ib_spec,
802c2125 2683 const struct ib_flow_attr *flow_attr,
71c6e863 2684 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2685{
bb0ee7dc
JL		 2686 struct mlx5_flow_context *flow_context = &spec->flow_context;
2687 u32 *match_c = spec->match_criteria;
2688 u32 *match_v = spec->match_value;
466fa6d2
MG		 2689 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2690 misc_parameters);
2691 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2692 misc_parameters);
71c6e863
AL		 2693 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2694 misc_parameters_2);
2695 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2696 misc_parameters_2);
2d1e697e
MR		 2697 void *headers_c;
2698 void *headers_v;
19cc7524 2699 int match_ipv;
802c2125 2700 int ret;
2d1e697e
MR		 2701
2702 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2703 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2704 inner_headers);
2705 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2706 inner_headers);
19cc7524
AL		 2707 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2708 ft_field_support.inner_ip_version);
2d1e697e
MR		 2709 } else {
2710 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2711 outer_headers);
2712 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2713 outer_headers);
19cc7524
AL		 2714 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2715 ft_field_support.outer_ip_version);
2d1e697e 2716 }
466fa6d2 2717
2d1e697e 2718 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2719 case IB_FLOW_SPEC_ETH:
c47ac6ae 2720 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2721 return -EOPNOTSUPP;
038d2ef8 2722
2d1e697e 2723 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2724 dmac_47_16),
2725 ib_spec->eth.mask.dst_mac);
2d1e697e 2726 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2727 dmac_47_16),
2728 ib_spec->eth.val.dst_mac);
2729
2d1e697e 2730 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2731 smac_47_16),
2732 ib_spec->eth.mask.src_mac);
2d1e697e 2733 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2734 smac_47_16),
2735 ib_spec->eth.val.src_mac);
2736
038d2ef8 2737 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2738 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2739 cvlan_tag, 1);
2d1e697e 2740 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2741 cvlan_tag, 1);
038d2ef8 2742
2d1e697e 2743 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2744 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2745 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2746 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2747
2d1e697e 2748 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2749 first_cfi,
2750 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2751 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2752 first_cfi,
2753 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2754
2d1e697e 2755 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2756 first_prio,
2757 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2758 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2759 first_prio,
2760 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2761 }
2d1e697e 2762 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2763 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2764 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2765 ethertype, ntohs(ib_spec->eth.val.ether_type));
2766 break;
2767 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2768 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2769 return -EOPNOTSUPP;
038d2ef8 2770
19cc7524
AL		 2771 if (match_ipv) {
2772 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2773 ip_version, 0xf);
2774 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2775 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2776 } else {
2777 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2778 ethertype, 0xffff);
2779 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2780 ethertype, ETH_P_IP);
2781 }
038d2ef8 2782
2d1e697e 2783 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2784 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2785 &ib_spec->ipv4.mask.src_ip,
2786 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2787 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2788 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2789 &ib_spec->ipv4.val.src_ip,
2790 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2791 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2792 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2793 &ib_spec->ipv4.mask.dst_ip,
2794 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2795 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2796 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2797 &ib_spec->ipv4.val.dst_ip,
2798 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2799
2d1e697e 2800 set_tos(headers_c, headers_v,
ca0d4753
MG		 2801 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2802
6113cc44
MG		 2803 if (set_proto(headers_c, headers_v,
2804 ib_spec->ipv4.mask.proto,
2805 ib_spec->ipv4.val.proto))
2806 return -EINVAL;
038d2ef8 2807 break;
026bae0c 2808 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2809 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2810 return -EOPNOTSUPP;
026bae0c 2811
19cc7524
AL		 2812 if (match_ipv) {
2813 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2814 ip_version, 0xf);
2815 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2816 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2817 } else {
2818 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2819 ethertype, 0xffff);
2820 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2821 ethertype, ETH_P_IPV6);
2822 }
026bae0c 2823
2d1e697e 2824 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2825 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2826 &ib_spec->ipv6.mask.src_ip,
2827 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2828 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2829 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2830 &ib_spec->ipv6.val.src_ip,
2831 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2832 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2833 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2834 &ib_spec->ipv6.mask.dst_ip,
2835 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2836 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2837 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2838 &ib_spec->ipv6.val.dst_ip,
2839 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2840
2d1e697e 2841 set_tos(headers_c, headers_v,
466fa6d2
MG		 2842 ib_spec->ipv6.mask.traffic_class,
2843 ib_spec->ipv6.val.traffic_class);
2844
6113cc44
MG		 2845 if (set_proto(headers_c, headers_v,
2846 ib_spec->ipv6.mask.next_hdr,
2847 ib_spec->ipv6.val.next_hdr))
2848 return -EINVAL;
466fa6d2 2849
2d1e697e
MR		 2850 set_flow_label(misc_params_c, misc_params_v,
2851 ntohl(ib_spec->ipv6.mask.flow_label),
2852 ntohl(ib_spec->ipv6.val.flow_label),
2853 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2854 break;
2855 case IB_FLOW_SPEC_ESP:
2856 if (ib_spec->esp.mask.seq)
2857 return -EOPNOTSUPP;
2d1e697e 2858
802c2125
AY		 2859 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2860 ntohl(ib_spec->esp.mask.spi));
2861 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2862 ntohl(ib_spec->esp.val.spi));
026bae0c 2863 break;
038d2ef8 2864 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2865 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2866 LAST_TCP_UDP_FIELD))
1ffd3a26 2867 return -EOPNOTSUPP;
038d2ef8 2868
6113cc44
MG		 2869 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2870 return -EINVAL;
038d2ef8 2871
2d1e697e 2872 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2873 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2874 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2875 ntohs(ib_spec->tcp_udp.val.src_port));
2876
2d1e697e 2877 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2878 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2879 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2880 ntohs(ib_spec->tcp_udp.val.dst_port));
2881 break;
2882 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2883 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2884 LAST_TCP_UDP_FIELD))
1ffd3a26 2885 return -EOPNOTSUPP;
038d2ef8 2886
6113cc44
MG		 2887 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2888 return -EINVAL;
038d2ef8 2889
2d1e697e 2890 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2891 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2892 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2893 ntohs(ib_spec->tcp_udp.val.src_port));
2894
2d1e697e 2895 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2896 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2897 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2898 ntohs(ib_spec->tcp_udp.val.dst_port));
2899 break;
da2f22ae
AL		 2900 case IB_FLOW_SPEC_GRE:
2901 if (ib_spec->gre.mask.c_ks_res0_ver)
2902 return -EOPNOTSUPP;
2903
6113cc44
MG		 2904 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2905 return -EINVAL;
2906
da2f22ae
AL		 2907 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2908 0xff);
2909 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2910 IPPROTO_GRE);
2911
2912 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2913 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2914 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2915 ntohs(ib_spec->gre.val.protocol));
2916
2917 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2918 gre_key.nvgre.hi),
da2f22ae
AL		 2919 &ib_spec->gre.mask.key,
2920 sizeof(ib_spec->gre.mask.key));
2921 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2922 gre_key.nvgre.hi),
da2f22ae
AL		 2923 &ib_spec->gre.val.key,
2924 sizeof(ib_spec->gre.val.key));
2925 break;
71c6e863
AL		 2926 case IB_FLOW_SPEC_MPLS:
2927 switch (prev_type) {
2928 case IB_FLOW_SPEC_UDP:
2929 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2930 ft_field_support.outer_first_mpls_over_udp),
2931 &ib_spec->mpls.mask.tag))
2932 return -EOPNOTSUPP;
2933
2934 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2935 outer_first_mpls_over_udp),
2936 &ib_spec->mpls.val.tag,
2937 sizeof(ib_spec->mpls.val.tag));
2938 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2939 outer_first_mpls_over_udp),
2940 &ib_spec->mpls.mask.tag,
2941 sizeof(ib_spec->mpls.mask.tag));
2942 break;
2943 case IB_FLOW_SPEC_GRE:
2944 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2945 ft_field_support.outer_first_mpls_over_gre),
2946 &ib_spec->mpls.mask.tag))
2947 return -EOPNOTSUPP;
2948
2949 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2950 outer_first_mpls_over_gre),
2951 &ib_spec->mpls.val.tag,
2952 sizeof(ib_spec->mpls.val.tag));
2953 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2954 outer_first_mpls_over_gre),
2955 &ib_spec->mpls.mask.tag,
2956 sizeof(ib_spec->mpls.mask.tag));
2957 break;
2958 default:
2959 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2960 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2961 ft_field_support.inner_first_mpls),
2962 &ib_spec->mpls.mask.tag))
2963 return -EOPNOTSUPP;
2964
2965 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2966 inner_first_mpls),
2967 &ib_spec->mpls.val.tag,
2968 sizeof(ib_spec->mpls.val.tag));
2969 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2970 inner_first_mpls),
2971 &ib_spec->mpls.mask.tag,
2972 sizeof(ib_spec->mpls.mask.tag));
2973 } else {
2974 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2975 ft_field_support.outer_first_mpls),
2976 &ib_spec->mpls.mask.tag))
2977 return -EOPNOTSUPP;
2978
2979 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2980 outer_first_mpls),
2981 &ib_spec->mpls.val.tag,
2982 sizeof(ib_spec->mpls.val.tag));
2983 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2984 outer_first_mpls),
2985 &ib_spec->mpls.mask.tag,
2986 sizeof(ib_spec->mpls.mask.tag));
2987 }
2988 }
2989 break;
ffb30d8f
MR		 2990 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2991 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2992 LAST_TUNNEL_FIELD))
1ffd3a26 2993 return -EOPNOTSUPP;
ffb30d8f
MR		 2994
2995 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2996 ntohl(ib_spec->tunnel.mask.tunnel_id));
2997 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2998 ntohl(ib_spec->tunnel.val.tunnel_id));
2999 break;
2ac693f9
MR		 3000 case IB_FLOW_SPEC_ACTION_TAG:
3001 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
3002 LAST_FLOW_TAG_FIELD))
3003 return -EOPNOTSUPP;
3004 if (ib_spec->flow_tag.tag_id >= BIT(24))
3005 return -EINVAL;
3006
bb0ee7dc
JL		 3007 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3008 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2ac693f9 3009 break;
a22ed86c
SS		 3010 case IB_FLOW_SPEC_ACTION_DROP:
3011 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3012 LAST_DROP_FIELD))
3013 return -EOPNOTSUPP;
075572d4 3014 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3015 break;
802c2125 3016 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3017 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3018 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3019 if (ret)
3020 return ret;
3021 break;
3b3233fb
RS		 3022 case IB_FLOW_SPEC_ACTION_COUNT:
3023 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3024 LAST_COUNTERS_FIELD))
3025 return -EOPNOTSUPP;
3026
3027 /* for now support only one counters spec per flow */
3028 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3029 return -EINVAL;
3030
3031 action->counters = ib_spec->flow_count.counters;
3032 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3033 break;
038d2ef8
MG		 3034 default:
3035 return -EINVAL;
3036 }
3037
3038 return 0;
3039}
3040
3041/* If a flow could catch both multicast and unicast packets,
3042 * it won't fall into the multicast flow steering table and this rule
3043 * could steal other multicast packets.
3044 */
a550ddfc 3045static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3046{
81e30880 3047 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3048
3049 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3050 ib_attr->num_of_specs < 1)
3051 return false;
3052
81e30880
YH		 3053 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3054 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3055 struct ib_flow_spec_ipv4 *ipv4_spec;
3056
3057 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3058 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3059 return true;
3060
038d2ef8 3061 return false;
81e30880
YH		 3062 }
3063
3064 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3065 struct ib_flow_spec_eth *eth_spec;
3066
3067 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3068 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3069 is_multicast_ether_addr(eth_spec->val.dst_mac);
3070 }
038d2ef8 3071
81e30880 3072 return false;
038d2ef8
MG		 3073}
3074
802c2125
AY		 3075enum valid_spec {
3076 VALID_SPEC_INVALID,
3077 VALID_SPEC_VALID,
3078 VALID_SPEC_NA,
3079};
3080
3081static enum valid_spec
3082is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3083 const struct mlx5_flow_spec *spec,
3084 const struct mlx5_flow_act *flow_act,
3085 bool egress)
3086{
3087 const u32 *match_c = spec->match_criteria;
3088 bool is_crypto =
3089 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3090 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3091 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3092 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3093
3094 /*
3095 * Currently only crypto is supported in egress, when regular egress
3096 * rules would be supported, always return VALID_SPEC_NA.
3097 */
3098 if (!is_crypto)
78dd0c43 3099 return VALID_SPEC_NA;
802c2125
AY		 3100
3101 return is_crypto && is_ipsec &&
bb0ee7dc
JL		 3102 (!egress || (!is_drop &&
3103 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
802c2125
AY		 3104 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3105}
3106
3107static bool is_valid_spec(struct mlx5_core_dev *mdev,
3108 const struct mlx5_flow_spec *spec,
3109 const struct mlx5_flow_act *flow_act,
3110 bool egress)
3111{
3112 /* We curretly only support ipsec egress flow */
3113 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3114}
3115
19cc7524
AL		 3116static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3117 const struct ib_flow_attr *flow_attr,
0f750966 3118 bool check_inner)
038d2ef8
MG		 3119{
3120 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3121 int match_ipv = check_inner ?
3122 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3123 ft_field_support.inner_ip_version) :
3124 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3125 ft_field_support.outer_ip_version);
0f750966
AL		 3126 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3127 bool ipv4_spec_valid, ipv6_spec_valid;
3128 unsigned int ip_spec_type = 0;
3129 bool has_ethertype = false;
038d2ef8 3130 unsigned int spec_index;
0f750966
AL		 3131 bool mask_valid = true;
3132 u16 eth_type = 0;
3133 bool type_valid;
038d2ef8
MG		 3134
3135 /* Validate that ethertype is correct */
3136 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3137 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3138 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3139 mask_valid = (ib_spec->eth.mask.ether_type ==
3140 htons(0xffff));
3141 has_ethertype = true;
3142 eth_type = ntohs(ib_spec->eth.val.ether_type);
3143 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3144 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3145 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3146 }
3147 ib_spec = (void *)ib_spec + ib_spec->size;
3148 }
0f750966
AL		 3149
3150 type_valid = (!has_ethertype) || (!ip_spec_type);
3151 if (!type_valid && mask_valid) {
3152 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3153 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3154 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3155 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3156
3157 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3158 (((eth_type == ETH_P_MPLS_UC) ||
3159 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3160 }
3161
3162 return type_valid;
3163}
3164
19cc7524
AL		 3165static bool is_valid_attr(struct mlx5_core_dev *mdev,
3166 const struct ib_flow_attr *flow_attr)
0f750966 3167{
19cc7524
AL		 3168 return is_valid_ethertype(mdev, flow_attr, false) &&
3169 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3170}
3171
3172static void put_flow_table(struct mlx5_ib_dev *dev,
3173 struct mlx5_ib_flow_prio *prio, bool ft_added)
3174{
3175 prio->refcount -= !!ft_added;
3176 if (!prio->refcount) {
3177 mlx5_destroy_flow_table(prio->flow_table);
3178 prio->flow_table = NULL;
3179 }
3180}
3181
3b3233fb
RS		 3182static void counters_clear_description(struct ib_counters *counters)
3183{
3184 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3185
3186 mutex_lock(&mcounters->mcntrs_mutex);
3187 kfree(mcounters->counters_data);
3188 mcounters->counters_data = NULL;
3189 mcounters->cntrs_max_index = 0;
3190 mutex_unlock(&mcounters->mcntrs_mutex);
3191}
3192
038d2ef8
MG		 3193static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3194{
038d2ef8
MG		 3195 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3196 struct mlx5_ib_flow_handler,
3197 ibflow);
3198 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3199 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3200
9a4ca38d 3201 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3202
3203 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3204 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3205 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3206 list_del(&iter->list);
3207 kfree(iter);
3208 }
3209
74491de9 3210 mlx5_del_flow_rules(handler->rule);
5497adc6 3211 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3212 if (handler->ibcounters &&
3213 atomic_read(&handler->ibcounters->usecnt) == 1)
3214 counters_clear_description(handler->ibcounters);
038d2ef8 3215
3b3233fb 3216 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3217 if (handler->flow_matcher)
3218 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3219 kfree(handler);
3220
3221 return 0;
3222}
3223
35d19011
MG		 3224static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3225{
3226 priority *= 2;
3227 if (!dont_trap)
3228 priority++;
3229 return priority;
3230}
3231
cc0e5d42
MG		 3232enum flow_table_type {
3233 MLX5_IB_FT_RX,
3234 MLX5_IB_FT_TX
3235};
3236
00b7c2ab
MG		 3237#define MLX5_FS_MAX_TYPES 6
3238#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3239
3240static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3241 struct mlx5_ib_flow_prio *prio,
3242 int priority,
4adda112
MB		 3243 int num_entries, int num_groups,
3244 u32 flags)
d4be3f44
YH		 3245{
3246 struct mlx5_flow_table *ft;
3247
3248 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3249 num_entries,
3250 num_groups,
4adda112 3251 0, flags);
d4be3f44
YH		 3252 if (IS_ERR(ft))
3253 return ERR_CAST(ft);
3254
3255 prio->flow_table = ft;
3256 prio->refcount = 0;
3257 return prio;
3258}
3259
038d2ef8 3260static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3261 struct ib_flow_attr *flow_attr,
3262 enum flow_table_type ft_type)
038d2ef8 3263{
35d19011 3264 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3265 struct mlx5_flow_namespace *ns = NULL;
3266 struct mlx5_ib_flow_prio *prio;
3267 struct mlx5_flow_table *ft;
dac388ef 3268 int max_table_size;
038d2ef8
MG		 3269 int num_entries;
3270 int num_groups;
cecae747 3271 bool esw_encap;
4adda112 3272 u32 flags = 0;
038d2ef8 3273 int priority;
038d2ef8 3274
dac388ef
MG		 3275 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3276 log_max_ft_size));
cecae747
MG		 3277 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3278 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3279 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3280 enum mlx5_flow_namespace_type fn_type;
3281
3282 if (flow_is_multicast_only(flow_attr) &&
3283 !dont_trap)
038d2ef8
MG		 3284 priority = MLX5_IB_FLOW_MCAST_PRIO;
3285 else
35d19011
MG		 3286 priority = ib_prio_to_core_prio(flow_attr->priority,
3287 dont_trap);
78dd0c43
MB		 3288 if (ft_type == MLX5_IB_FT_RX) {
3289 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3290 prio = &dev->flow_db->prios[priority];
cecae747 3291 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3292 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3293 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3294 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3295 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3296 reformat_l3_tunnel_to_l2))
3297 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3298 } else {
3299 max_table_size =
3300 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3301 log_max_ft_size));
3302 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3303 prio = &dev->flow_db->egress_prios[priority];
cecae747 3304 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3305 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3306 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3307 }
3308 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3309 num_entries = MLX5_FS_MAX_ENTRIES;
3310 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3311 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3312 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3313 ns = mlx5_get_flow_namespace(dev->mdev,
3314 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3315 build_leftovers_ft_param(&priority,
3316 &num_entries,
3317 &num_groups);
9a4ca38d 3318 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3319 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3320 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3321 allow_sniffer_and_nic_rx_shared_tir))
3322 return ERR_PTR(-ENOTSUPP);
3323
3324 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3325 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3326 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3327
9a4ca38d 3328 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3329 priority = 0;
3330 num_entries = 1;
3331 num_groups = 1;
038d2ef8
MG		 3332 }
3333
3334 if (!ns)
3335 return ERR_PTR(-ENOTSUPP);
3336
3b70508a 3337 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3338
038d2ef8 3339 ft = prio->flow_table;
d4be3f44 3340 if (!ft)
3b70508a 3341 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3342 flags);
038d2ef8 3343
d4be3f44 3344 return prio;
038d2ef8
MG		 3345}
3346
a550ddfc
YH		 3347static void set_underlay_qp(struct mlx5_ib_dev *dev,
3348 struct mlx5_flow_spec *spec,
3349 u32 underlay_qpn)
3350{
3351 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3352 spec->match_criteria,
3353 misc_parameters);
3354 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3355 misc_parameters);
3356
3357 if (underlay_qpn &&
3358 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3359 ft_field_support.bth_dst_qp)) {
3360 MLX5_SET(fte_match_set_misc,
3361 misc_params_v, bth_dst_qp, underlay_qpn);
3362 MLX5_SET(fte_match_set_misc,
3363 misc_params_c, bth_dst_qp, 0xffffff);
3364 }
3365}
3366
5e95af5f
RS		 3367static int read_flow_counters(struct ib_device *ibdev,
3368 struct mlx5_read_counters_attr *read_attr)
3369{
3370 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3371 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3372
3373 return mlx5_fc_query(dev->mdev, fc,
3374 &read_attr->out[IB_COUNTER_PACKETS],
3375 &read_attr->out[IB_COUNTER_BYTES]);
3376}
3377
3378/* flow counters currently expose two counters packets and bytes */
3379#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3380static int counters_set_description(struct ib_counters *counters,
3381 enum mlx5_ib_counters_type counters_type,
3382 struct mlx5_ib_flow_counters_desc *desc_data,
3383 u32 ncounters)
3384{
3385 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3386 u32 cntrs_max_index = 0;
3387 int i;
3388
3389 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3390 return -EINVAL;
3391
3392 /* init the fields for the object */
3393 mcounters->type = counters_type;
5e95af5f
RS		 3394 mcounters->read_counters = read_flow_counters;
3395 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3396 mcounters->ncounters = ncounters;
3397 /* each counter entry have both description and index pair */
3398 for (i = 0; i < ncounters; i++) {
3399 if (desc_data[i].description > IB_COUNTER_BYTES)
3400 return -EINVAL;
3401
3402 if (cntrs_max_index <= desc_data[i].index)
3403 cntrs_max_index = desc_data[i].index + 1;
3404 }
3405
3406 mutex_lock(&mcounters->mcntrs_mutex);
3407 mcounters->counters_data = desc_data;
3408 mcounters->cntrs_max_index = cntrs_max_index;
3409 mutex_unlock(&mcounters->mcntrs_mutex);
3410
3411 return 0;
3412}
3413
3414#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3415static int flow_counters_set_data(struct ib_counters *ibcounters,
3416 struct mlx5_ib_create_flow *ucmd)
3417{
3418 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3419 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3420 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3421 bool hw_hndl = false;
3422 int ret = 0;
3423
3424 if (ucmd && ucmd->ncounters_data != 0) {
3425 cntrs_data = ucmd->data;
3426 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3427 return -EINVAL;
3428
3429 desc_data = kcalloc(cntrs_data->ncounters,
3430 sizeof(*desc_data),
3431 GFP_KERNEL);
3432 if (!desc_data)
3433 return -ENOMEM;
3434
3435 if (copy_from_user(desc_data,
3436 u64_to_user_ptr(cntrs_data->counters_data),
3437 sizeof(*desc_data) * cntrs_data->ncounters)) {
3438 ret = -EFAULT;
3439 goto free;
3440 }
3441 }
3442
3443 if (!mcounters->hw_cntrs_hndl) {
3444 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3445 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3446 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3447 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3448 goto free;
3449 }
3450 hw_hndl = true;
3451 }
3452
3453 if (desc_data) {
3454 /* counters already bound to at least one flow */
3455 if (mcounters->cntrs_max_index) {
3456 ret = -EINVAL;
3457 goto free_hndl;
3458 }
3459
3460 ret = counters_set_description(ibcounters,
3461 MLX5_IB_COUNTERS_FLOW,
3462 desc_data,
3463 cntrs_data->ncounters);
3464 if (ret)
3465 goto free_hndl;
3466
3467 } else if (!mcounters->cntrs_max_index) {
3468 /* counters not bound yet, must have udata passed */
3469 ret = -EINVAL;
3470 goto free_hndl;
3471 }
3472
3473 return 0;
3474
3475free_hndl:
3476 if (hw_hndl) {
3477 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3478 mcounters->hw_cntrs_hndl);
3479 mcounters->hw_cntrs_hndl = NULL;
3480 }
3481free:
3482 kfree(desc_data);
3483 return ret;
3484}
3485
669ff1e3
JL		 3486static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3487 struct mlx5_flow_spec *spec,
3488 struct mlx5_eswitch_rep *rep)
3489{
3490 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3491 void *misc;
3492
3493 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3494 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3495 misc_parameters_2);
3496
3497 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3498 mlx5_eswitch_get_vport_metadata_for_match(esw,
3499 rep->vport));
3500 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3501 misc_parameters_2);
3502
3503 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3504 } else {
3505 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3506 misc_parameters);
3507
3508 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3509
3510 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3511 misc_parameters);
3512
3513 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3514 }
3515}
3516
a550ddfc
YH		 3517static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3518 struct mlx5_ib_flow_prio *ft_prio,
3519 const struct ib_flow_attr *flow_attr,
3520 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3521 u32 underlay_qpn,
3522 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3523{
3524 struct mlx5_flow_table *ft = ft_prio->flow_table;
3525 struct mlx5_ib_flow_handler *handler;
bb0ee7dc 3526 struct mlx5_flow_act flow_act = {};
c5bb1730 3527 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3528 struct mlx5_flow_destination dest_arr[2] = {};
3529 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3530 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3531 unsigned int spec_index;
71c6e863 3532 u32 prev_type = 0;
038d2ef8 3533 int err = 0;
3b3233fb 3534 int dest_num = 0;
802c2125 3535 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3536
19cc7524 3537 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3538 return ERR_PTR(-EINVAL);
3539
6a4d00be 3540 if (dev->is_rep && is_egress)
78dd0c43
MB		 3541 return ERR_PTR(-EINVAL);
3542
1b9a07ee 3543 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3544 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3545 if (!handler || !spec) {
038d2ef8
MG		 3546 err = -ENOMEM;
3547 goto free;
3548 }
3549
3550 INIT_LIST_HEAD(&handler->list);
3b3233fb
RS		 3551 if (dst) {
3552 memcpy(&dest_arr[0], dst, sizeof(*dst));
3553 dest_num++;
3554 }
038d2ef8
MG		 3555
3556 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
bb0ee7dc 3557 err = parse_flow_attr(dev->mdev, spec,
71c6e863
AL		 3558 ib_flow, flow_attr, &flow_act,
3559 prev_type);
038d2ef8
MG		 3560 if (err < 0)
3561 goto free;
3562
71c6e863 3563 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3564 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3565 }
3566
a550ddfc
YH		 3567 if (!flow_is_multicast_only(flow_attr))
3568 set_underlay_qp(dev, spec, underlay_qpn);
3569
6a4d00be 3570 if (dev->is_rep) {
669ff1e3 3571 struct mlx5_eswitch_rep *rep;
018a94ee 3572
669ff1e3
JL		 3573 rep = dev->port[flow_attr->port - 1].rep;
3574 if (!rep) {
6a4d00be
MB		 3575 err = -EINVAL;
3576 goto free;
3577 }
669ff1e3
JL		 3578
3579 mlx5_ib_set_rule_source_port(dev, spec, rep);
018a94ee
MB		 3580 }
3581
466fa6d2 3582 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3583
3584 if (is_egress &&
3585 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3586 err = -EINVAL;
3587 goto free;
3588 }
3589
3b3233fb 3590 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3591 struct mlx5_ib_mcounters *mcounters;
3592
3b3233fb
RS		 3593 err = flow_counters_set_data(flow_act.counters, ucmd);
3594 if (err)
3595 goto free;
3596
171c7625 3597 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3598 handler->ibcounters = flow_act.counters;
3599 dest_arr[dest_num].type =
3600 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3601 dest_arr[dest_num].counter_id =
3602 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3603 dest_num++;
3604 }
3605
075572d4 3606 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3b3233fb
RS		 3607 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3608 rule_dst = NULL;
3609 dest_num = 0;
3610 }
a22ed86c 3611 } else {
802c2125
AY		 3612 if (is_egress)
3613 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3614 else
3615 flow_act.action |=
3b3233fb 3616 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3617 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3618 }
2ac693f9 3619
bb0ee7dc 3620 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
2ac693f9
MR		 3621 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3622 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3623 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
bb0ee7dc 3624 spec->flow_context.flow_tag, flow_attr->type);
2ac693f9
MR		 3625 err = -EINVAL;
3626 goto free;
3627 }
74491de9 3628 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3629 &flow_act,
a22ed86c 3630 rule_dst, dest_num);
038d2ef8
MG		 3631
3632 if (IS_ERR(handler->rule)) {
3633 err = PTR_ERR(handler->rule);
3634 goto free;
3635 }
3636
d9d4980a 3637 ft_prio->refcount++;
5497adc6 3638 handler->prio = ft_prio;
d4be3f44 3639 handler->dev = dev;
038d2ef8
MG		 3640
3641 ft_prio->flow_table = ft;
3642free:
3b3233fb
RS		 3643 if (err && handler) {
3644 if (handler->ibcounters &&
3645 atomic_read(&handler->ibcounters->usecnt) == 1)
3646 counters_clear_description(handler->ibcounters);
038d2ef8 3647 kfree(handler);
3b3233fb 3648 }
c5bb1730 3649 kvfree(spec);
038d2ef8
MG		 3650 return err ? ERR_PTR(err) : handler;
3651}
3652
a550ddfc
YH		 3653static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3654 struct mlx5_ib_flow_prio *ft_prio,
3655 const struct ib_flow_attr *flow_attr,
3656 struct mlx5_flow_destination *dst)
3657{
3b3233fb 3658 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3659}
3660
35d19011
MG		 3661static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3662 struct mlx5_ib_flow_prio *ft_prio,
3663 struct ib_flow_attr *flow_attr,
3664 struct mlx5_flow_destination *dst)
3665{
3666 struct mlx5_ib_flow_handler *handler_dst = NULL;
3667 struct mlx5_ib_flow_handler *handler = NULL;
3668
3669 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3670 if (!IS_ERR(handler)) {
3671 handler_dst = create_flow_rule(dev, ft_prio,
3672 flow_attr, dst);
3673 if (IS_ERR(handler_dst)) {
74491de9 3674 mlx5_del_flow_rules(handler->rule);
d9d4980a 3675 ft_prio->refcount--;
35d19011
MG		 3676 kfree(handler);
3677 handler = handler_dst;
3678 } else {
3679 list_add(&handler_dst->list, &handler->list);
3680 }
3681 }
3682
3683 return handler;
3684}
038d2ef8
MG		 3685enum {
3686 LEFTOVERS_MC,
3687 LEFTOVERS_UC,
3688};
3689
3690static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3691 struct mlx5_ib_flow_prio *ft_prio,
3692 struct ib_flow_attr *flow_attr,
3693 struct mlx5_flow_destination *dst)
3694{
3695 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3696 struct mlx5_ib_flow_handler *handler = NULL;
3697
3698 static struct {
3699 struct ib_flow_attr flow_attr;
3700 struct ib_flow_spec_eth eth_flow;
3701 } leftovers_specs[] = {
3702 [LEFTOVERS_MC] = {
3703 .flow_attr = {
3704 .num_of_specs = 1,
3705 .size = sizeof(leftovers_specs[0])
3706 },
3707 .eth_flow = {
3708 .type = IB_FLOW_SPEC_ETH,
3709 .size = sizeof(struct ib_flow_spec_eth),
3710 .mask = {.dst_mac = {0x1} },
3711 .val = {.dst_mac = {0x1} }
3712 }
3713 },
3714 [LEFTOVERS_UC] = {
3715 .flow_attr = {
3716 .num_of_specs = 1,
3717 .size = sizeof(leftovers_specs[0])
3718 },
3719 .eth_flow = {
3720 .type = IB_FLOW_SPEC_ETH,
3721 .size = sizeof(struct ib_flow_spec_eth),
3722 .mask = {.dst_mac = {0x1} },
3723 .val = {.dst_mac = {} }
3724 }
3725 }
3726 };
3727
3728 handler = create_flow_rule(dev, ft_prio,
3729 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3730 dst);
3731 if (!IS_ERR(handler) &&
3732 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3733 handler_ucast = create_flow_rule(dev, ft_prio,
3734 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3735 dst);
3736 if (IS_ERR(handler_ucast)) {
74491de9 3737 mlx5_del_flow_rules(handler->rule);
d9d4980a 3738 ft_prio->refcount--;
038d2ef8
MG		 3739 kfree(handler);
3740 handler = handler_ucast;
3741 } else {
3742 list_add(&handler_ucast->list, &handler->list);
3743 }
3744 }
3745
3746 return handler;
3747}
3748
cc0e5d42
MG		 3749static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3750 struct mlx5_ib_flow_prio *ft_rx,
3751 struct mlx5_ib_flow_prio *ft_tx,
3752 struct mlx5_flow_destination *dst)
3753{
3754 struct mlx5_ib_flow_handler *handler_rx;
3755 struct mlx5_ib_flow_handler *handler_tx;
3756 int err;
3757 static const struct ib_flow_attr flow_attr = {
3758 .num_of_specs = 0,
3759 .size = sizeof(flow_attr)
3760 };
3761
3762 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3763 if (IS_ERR(handler_rx)) {
3764 err = PTR_ERR(handler_rx);
3765 goto err;
3766 }
3767
3768 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3769 if (IS_ERR(handler_tx)) {
3770 err = PTR_ERR(handler_tx);
3771 goto err_tx;
3772 }
3773
3774 list_add(&handler_tx->list, &handler_rx->list);
3775
3776 return handler_rx;
3777
3778err_tx:
74491de9 3779 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3780 ft_rx->refcount--;
3781 kfree(handler_rx);
3782err:
3783 return ERR_PTR(err);
3784}
3785
038d2ef8
MG		 3786static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3787 struct ib_flow_attr *flow_attr,
59082a32
MB		 3788 int domain,
3789 struct ib_udata *udata)
038d2ef8
MG		 3790{
3791 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3792 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3793 struct mlx5_ib_flow_handler *handler = NULL;
3794 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3795 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3796 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3797 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3798 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3799 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3800 int err;
a550ddfc 3801 int underlay_qpn;
038d2ef8 3802
3b3233fb
RS		 3803 if (udata && udata->inlen) {
3804 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3805 sizeof(ucmd_hdr.reserved);
3806 if (udata->inlen < min_ucmd_sz)
3807 return ERR_PTR(-EOPNOTSUPP);
3808
3809 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3810 if (err)
3811 return ERR_PTR(err);
3812
3813 /* currently supports only one counters data */
3814 if (ucmd_hdr.ncounters_data > 1)
3815 return ERR_PTR(-EINVAL);
3816
3817 required_ucmd_sz = min_ucmd_sz +
3818 sizeof(struct mlx5_ib_flow_counters_data) *
3819 ucmd_hdr.ncounters_data;
3820 if (udata->inlen > required_ucmd_sz &&
3821 !ib_is_udata_cleared(udata, required_ucmd_sz,
3822 udata->inlen - required_ucmd_sz))
3823 return ERR_PTR(-EOPNOTSUPP);
3824
3825 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3826 if (!ucmd)
3827 return ERR_PTR(-ENOMEM);
3828
3829 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3830 if (err)
3831 goto free_ucmd;
3b3233fb 3832 }
59082a32 3833
299eafee
GS		 3834 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3835 err = -ENOMEM;
3836 goto free_ucmd;
3837 }
038d2ef8
MG		 3838
3839 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3840 flow_attr->port > dev->num_ports ||
802c2125 3841 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3842 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3843 err = -EINVAL;
3844 goto free_ucmd;
3845 }
802c2125
AY		 3846
3847 if (is_egress &&
3848 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3849 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3850 err = -EINVAL;
3851 goto free_ucmd;
3852 }
038d2ef8
MG		 3853
3854 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3855 if (!dst) {
3856 err = -ENOMEM;
3857 goto free_ucmd;
3858 }
038d2ef8 3859
9a4ca38d 3860 mutex_lock(&dev->flow_db->lock);
038d2ef8 3861
802c2125
AY		 3862 ft_prio = get_flow_table(dev, flow_attr,
3863 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3864 if (IS_ERR(ft_prio)) {
3865 err = PTR_ERR(ft_prio);
3866 goto unlock;
3867 }
cc0e5d42
MG		 3868 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3869 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3870 if (IS_ERR(ft_prio_tx)) {
3871 err = PTR_ERR(ft_prio_tx);
3872 ft_prio_tx = NULL;
3873 goto destroy_ft;
3874 }
3875 }
038d2ef8 3876
802c2125
AY		 3877 if (is_egress) {
3878 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3879 } else {
3880 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3881 if (mqp->flags & MLX5_IB_QP_RSS)
3882 dst->tir_num = mqp->rss_qp.tirn;
3883 else
3884 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3885 }
038d2ef8
MG		 3886
3887 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3888 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3889 handler = create_dont_trap_rule(dev, ft_prio,
3890 flow_attr, dst);
3891 } else {
a550ddfc
YH		 3892 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3893 mqp->underlay_qpn : 0;
3894 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3895 dst, underlay_qpn, ucmd);
35d19011 3896 }
038d2ef8
MG		 3897 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3898 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3899 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3900 dst);
cc0e5d42
MG		 3901 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3902 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3903 } else {
3904 err = -EINVAL;
3905 goto destroy_ft;
3906 }
3907
3908 if (IS_ERR(handler)) {
3909 err = PTR_ERR(handler);
3910 handler = NULL;
3911 goto destroy_ft;
3912 }
3913
9a4ca38d 3914 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3915 kfree(dst);
3b3233fb 3916 kfree(ucmd);
038d2ef8
MG		 3917
3918 return &handler->ibflow;
3919
3920destroy_ft:
3921 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3922 if (ft_prio_tx)
3923 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3924unlock:
9a4ca38d 3925 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3926 kfree(dst);
299eafee 3927free_ucmd:
3b3233fb 3928 kfree(ucmd);
038d2ef8
MG		 3929 return ERR_PTR(err);
3930}
3931
b47fd4ff
MB		 3932static struct mlx5_ib_flow_prio *
3933_get_flow_table(struct mlx5_ib_dev *dev,
3934 struct mlx5_ib_flow_matcher *fs_matcher,
3935 bool mcast)
d4be3f44 3936{
d4be3f44 3937 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 3938 struct mlx5_ib_flow_prio *prio = NULL;
3939 int max_table_size = 0;
cecae747 3940 bool esw_encap;
b47fd4ff
MB		 3941 u32 flags = 0;
3942 int priority;
3943
13a43765
MB		 3944 if (mcast)
3945 priority = MLX5_IB_FLOW_MCAST_PRIO;
3946 else
3947 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3948
cecae747
MG		 3949 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3950 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 3951 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3952 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3953 log_max_ft_size));
cecae747 3954 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 3955 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3956 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 3957 reformat_l3_tunnel_to_l2) &&
3958 !esw_encap)
b47fd4ff 3959 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3960 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3961 max_table_size = BIT(
3962 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 3963 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 3964 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3965 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3966 max_table_size = BIT(
3967 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
09d985be
MG		 3968 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3969 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3970 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3971 esw_encap)
3972 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765 3973 priority = FDB_BYPASS_PATH;
d8abe884
MZ		 3974 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
3975 max_table_size =
3976 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
3977 log_max_ft_size));
3978 priority = fs_matcher->priority;
b47fd4ff 3979 }
d4be3f44 3980
3b70508a 3981 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 3982
b47fd4ff 3983 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3984 if (!ns)
3985 return ERR_PTR(-ENOTSUPP);
3986
b47fd4ff
MB		 3987 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3988 prio = &dev->flow_db->prios[priority];
13a43765 3989 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 3990 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 3991 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3992 prio = &dev->flow_db->fdb;
d8abe884
MZ		 3993 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
3994 prio = &dev->flow_db->rdma_rx[priority];
13a43765
MB		 3995
3996 if (!prio)
3997 return ERR_PTR(-EINVAL);
d4be3f44
YH		 3998
3999 if (prio->flow_table)
4000 return prio;
4001
3b70508a 4002 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 4003 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 4004}
4005
4006static struct mlx5_ib_flow_handler *
4007_create_raw_flow_rule(struct mlx5_ib_dev *dev,
4008 struct mlx5_ib_flow_prio *ft_prio,
4009 struct mlx5_flow_destination *dst,
4010 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4011 struct mlx5_flow_context *flow_context,
b823dd6d 4012 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 4013 void *cmd_in, int inlen,
4014 int dst_num)
d4be3f44
YH		 4015{
4016 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 4017 struct mlx5_flow_spec *spec;
4018 struct mlx5_flow_table *ft = ft_prio->flow_table;
4019 int err = 0;
4020
4021 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4022 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4023 if (!handler || !spec) {
4024 err = -ENOMEM;
4025 goto free;
4026 }
4027
4028 INIT_LIST_HEAD(&handler->list);
4029
4030 memcpy(spec->match_value, cmd_in, inlen);
4031 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4032 fs_matcher->mask_len);
4033 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
bb0ee7dc 4034 spec->flow_context = *flow_context;
d4be3f44 4035
d4be3f44 4036 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 4037 flow_act, dst, dst_num);
d4be3f44
YH		 4038
4039 if (IS_ERR(handler->rule)) {
4040 err = PTR_ERR(handler->rule);
4041 goto free;
4042 }
4043
4044 ft_prio->refcount++;
4045 handler->prio = ft_prio;
4046 handler->dev = dev;
4047 ft_prio->flow_table = ft;
4048
4049free:
4050 if (err)
4051 kfree(handler);
4052 kvfree(spec);
4053 return err ? ERR_PTR(err) : handler;
4054}
4055
4056static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4057 void *match_v)
4058{
4059 void *match_c;
4060 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4061 void *dmac, *dmac_mask;
4062 void *ipv4, *ipv4_mask;
4063
4064 if (!(fs_matcher->match_criteria_enable &
4065 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4066 return false;
4067
4068 match_c = fs_matcher->matcher_mask.match_params;
4069 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4070 outer_headers);
4071 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4072 outer_headers);
4073
4074 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4075 dmac_47_16);
4076 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4077 dmac_47_16);
4078
4079 if (is_multicast_ether_addr(dmac) &&
4080 is_multicast_ether_addr(dmac_mask))
4081 return true;
4082
4083 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4084 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4085
4086 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4087 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4088
4089 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4090 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4091 return true;
4092
4093 return false;
4094}
4095
32269441
YH		 4096struct mlx5_ib_flow_handler *
4097mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4098 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4099 struct mlx5_flow_context *flow_context,
b823dd6d 4100 struct mlx5_flow_act *flow_act,
bfc5d839 4101 u32 counter_id,
32269441
YH		 4102 void *cmd_in, int inlen, int dest_id,
4103 int dest_type)
4104{
d4be3f44
YH		 4105 struct mlx5_flow_destination *dst;
4106 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4107 struct mlx5_ib_flow_handler *handler;
bfc5d839 4108 int dst_num = 0;
d4be3f44
YH		 4109 bool mcast;
4110 int err;
4111
4112 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4113 return ERR_PTR(-EOPNOTSUPP);
4114
4115 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4116 return ERR_PTR(-ENOMEM);
4117
8e8aa145 4118 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4119 if (!dst)
4120 return ERR_PTR(-ENOMEM);
4121
4122 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4123 mutex_lock(&dev->flow_db->lock);
4124
b47fd4ff 4125 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4126 if (IS_ERR(ft_prio)) {
4127 err = PTR_ERR(ft_prio);
4128 goto unlock;
4129 }
4130
6346f0bf 4131 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4132 dst[dst_num].type = dest_type;
4133 dst[dst_num].tir_num = dest_id;
b823dd6d 4134 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4135 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4136 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4137 dst[dst_num].ft_num = dest_id;
b823dd6d 4138 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4139 } else {
bfc5d839 4140 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4141 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4142 }
4143
bfc5d839
MB		 4144 dst_num++;
4145
4146 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4147 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4148 dst[dst_num].counter_id = counter_id;
4149 dst_num++;
4150 }
4151
bb0ee7dc
JL		 4152 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4153 flow_context, flow_act,
bfc5d839 4154 cmd_in, inlen, dst_num);
d4be3f44
YH		 4155
4156 if (IS_ERR(handler)) {
4157 err = PTR_ERR(handler);
4158 goto destroy_ft;
4159 }
4160
4161 mutex_unlock(&dev->flow_db->lock);
4162 atomic_inc(&fs_matcher->usecnt);
4163 handler->flow_matcher = fs_matcher;
4164
4165 kfree(dst);
4166
4167 return handler;
4168
4169destroy_ft:
4170 put_flow_table(dev, ft_prio, false);
4171unlock:
4172 mutex_unlock(&dev->flow_db->lock);
4173 kfree(dst);
4174
4175 return ERR_PTR(err);
32269441
YH		 4176}
4177
c6475a0b
AY		 4178static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4179{
4180 u32 flags = 0;
4181
4182 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4183 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4184
4185 return flags;
4186}
4187
4188#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4189static struct ib_flow_action *
4190mlx5_ib_create_flow_action_esp(struct ib_device *device,
4191 const struct ib_flow_action_attrs_esp *attr,
4192 struct uverbs_attr_bundle *attrs)
4193{
4194 struct mlx5_ib_dev *mdev = to_mdev(device);
4195 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4196 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4197 struct mlx5_ib_flow_action *action;
4198 u64 action_flags;
4199 u64 flags;
4200 int err = 0;
4201
bccd0622
JG		 4202 err = uverbs_get_flags64(
4203 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4204 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4205 if (err)
4206 return ERR_PTR(err);
c6475a0b
AY		 4207
4208 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4209
4210 /* We current only support a subset of the standard features. Only a
4211 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4212 * (with overlap). Full offload mode isn't supported.
4213 */
4214 if (!attr->keymat || attr->replay || attr->encap ||
4215 attr->spi || attr->seq || attr->tfc_pad ||
4216 attr->hard_limit_pkts ||
4217 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4218 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4219 return ERR_PTR(-EOPNOTSUPP);
4220
4221 if (attr->keymat->protocol !=
4222 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4223 return ERR_PTR(-EOPNOTSUPP);
4224
4225 aes_gcm = &attr->keymat->keymat.aes_gcm;
4226
4227 if (aes_gcm->icv_len != 16 ||
4228 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4229 return ERR_PTR(-EOPNOTSUPP);
4230
4231 action = kmalloc(sizeof(*action), GFP_KERNEL);
4232 if (!action)
4233 return ERR_PTR(-ENOMEM);
4234
4235 action->esp_aes_gcm.ib_flags = attr->flags;
4236 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4237 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4238 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4239 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4240 sizeof(accel_attrs.keymat.aes_gcm.salt));
4241 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4242 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4243 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4244 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4245 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4246
4247 accel_attrs.esn = attr->esn;
4248 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4249 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4250 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4251 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4252
4253 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4254 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4255
4256 action->esp_aes_gcm.ctx =
4257 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4258 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4259 err = PTR_ERR(action->esp_aes_gcm.ctx);
4260 goto err_parse;
4261 }
4262
4263 action->esp_aes_gcm.ib_flags = attr->flags;
4264
4265 return &action->ib_action;
4266
4267err_parse:
4268 kfree(action);
4269 return ERR_PTR(err);
4270}
4271
349705c1
MB		 4272static int
4273mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4274 const struct ib_flow_action_attrs_esp *attr,
4275 struct uverbs_attr_bundle *attrs)
4276{
4277 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4278 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4279 int err = 0;
4280
4281 if (attr->keymat || attr->replay || attr->encap ||
4282 attr->spi || attr->seq || attr->tfc_pad ||
4283 attr->hard_limit_pkts ||
4284 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4285 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4286 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4287 return -EOPNOTSUPP;
4288
4289 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4290 * be modified.
4291 */
4292 if (!(maction->esp_aes_gcm.ib_flags &
4293 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4294 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4295 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4296 return -EINVAL;
4297
4298 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4299 sizeof(accel_attrs));
4300
4301 accel_attrs.esn = attr->esn;
4302 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4303 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4304 else
4305 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4306
4307 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4308 &accel_attrs);
4309 if (err)
4310 return err;
4311
4312 maction->esp_aes_gcm.ib_flags &=
4313 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4314 maction->esp_aes_gcm.ib_flags |=
4315 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4316
4317 return 0;
4318}
4319
c6475a0b
AY		 4320static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4321{
4322 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4323
4324 switch (action->type) {
4325 case IB_FLOW_ACTION_ESP:
4326 /*
4327 * We only support aes_gcm by now, so we implicitly know this is
4328 * the underline crypto.
4329 */
4330 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4331 break;
b4749bf2
MB		 4332 case IB_FLOW_ACTION_UNSPECIFIED:
4333 mlx5_ib_destroy_flow_action_raw(maction);
4334 break;
c6475a0b
AY		 4335 default:
4336 WARN_ON(true);
4337 break;
4338 }
4339
4340 kfree(maction);
4341 return 0;
4342}
4343
e126ba97
EC		 4344static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4345{
4346 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4347 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4348 int err;
539ec982
YH		 4349 u16 uid;
4350
4351 uid = ibqp->pd ?
4352 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4353
81e30880
YH		 4354 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4355 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4356 return -EOPNOTSUPP;
4357 }
4358
539ec982 4359 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4360 if (err)
4361 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4362 ibqp->qp_num, gid->raw);
4363
4364 return err;
4365}
4366
4367static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4368{
4369 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4370 int err;
539ec982 4371 u16 uid;
e126ba97 4372
539ec982
YH		 4373 uid = ibqp->pd ?
4374 to_mpd(ibqp->pd)->uid : 0;
4375 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4376 if (err)
4377 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4378 ibqp->qp_num, gid->raw);
4379
4380 return err;
4381}
4382
4383static int init_node_data(struct mlx5_ib_dev *dev)
4384{
1b5daf11 4385 int err;
e126ba97 4386
1b5daf11 4387 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4388 if (err)
1b5daf11 4389 return err;
e126ba97 4390
1b5daf11 4391 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4392
1b5daf11 4393 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4394}
4395
508a523f
PP		 4396static ssize_t fw_pages_show(struct device *device,
4397 struct device_attribute *attr, char *buf)
e126ba97
EC		 4398{
4399 struct mlx5_ib_dev *dev =
54747231 4400 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4401
9603b61d 4402 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4403}
508a523f 4404static DEVICE_ATTR_RO(fw_pages);
e126ba97 4405
508a523f 4406static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4407 struct device_attribute *attr, char *buf)
4408{
4409 struct mlx5_ib_dev *dev =
54747231 4410 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4411
6aec21f6 4412 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4413}
508a523f 4414static DEVICE_ATTR_RO(reg_pages);
e126ba97 4415
508a523f
PP		 4416static ssize_t hca_type_show(struct device *device,
4417 struct device_attribute *attr, char *buf)
e126ba97
EC		 4418{
4419 struct mlx5_ib_dev *dev =
54747231
PP		 4420 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4421
9603b61d 4422 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4423}
508a523f 4424static DEVICE_ATTR_RO(hca_type);
e126ba97 4425
508a523f
PP		 4426static ssize_t hw_rev_show(struct device *device,
4427 struct device_attribute *attr, char *buf)
e126ba97
EC		 4428{
4429 struct mlx5_ib_dev *dev =
54747231
PP		 4430 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4431
9603b61d 4432 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4433}
508a523f 4434static DEVICE_ATTR_RO(hw_rev);
e126ba97 4435
508a523f
PP		 4436static ssize_t board_id_show(struct device *device,
4437 struct device_attribute *attr, char *buf)
e126ba97
EC		 4438{
4439 struct mlx5_ib_dev *dev =
54747231
PP		 4440 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4441
e126ba97 4442 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4443 dev->mdev->board_id);
e126ba97 4444}
508a523f 4445static DEVICE_ATTR_RO(board_id);
e126ba97 4446
508a523f
PP		 4447static struct attribute *mlx5_class_attributes[] = {
4448 &dev_attr_hw_rev.attr,
4449 &dev_attr_hca_type.attr,
4450 &dev_attr_board_id.attr,
4451 &dev_attr_fw_pages.attr,
4452 &dev_attr_reg_pages.attr,
4453 NULL,
4454};
e126ba97 4455
508a523f
PP		 4456static const struct attribute_group mlx5_attr_group = {
4457 .attrs = mlx5_class_attributes,
e126ba97
EC		 4458};
4459
7722f47e
HE		 4460static void pkey_change_handler(struct work_struct *work)
4461{
4462 struct mlx5_ib_port_resources *ports =
4463 container_of(work, struct mlx5_ib_port_resources,
4464 pkey_change_work);
4465
4466 mutex_lock(&ports->devr->mutex);
4467 mlx5_ib_gsi_pkey_change(ports->gsi);
4468 mutex_unlock(&ports->devr->mutex);
4469}
4470
89ea94a7
MG		 4471static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4472{
4473 struct mlx5_ib_qp *mqp;
4474 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4475 struct mlx5_core_cq *mcq;
4476 struct list_head cq_armed_list;
4477 unsigned long flags_qp;
4478 unsigned long flags_cq;
4479 unsigned long flags;
4480
4481 INIT_LIST_HEAD(&cq_armed_list);
4482
4483 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4484 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4485 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4486 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4487 if (mqp->sq.tail != mqp->sq.head) {
4488 send_mcq = to_mcq(mqp->ibqp.send_cq);
4489 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4490 if (send_mcq->mcq.comp &&
4491 mqp->ibqp.send_cq->comp_handler) {
4492 if (!send_mcq->mcq.reset_notify_added) {
4493 send_mcq->mcq.reset_notify_added = 1;
4494 list_add_tail(&send_mcq->mcq.reset_notify,
4495 &cq_armed_list);
4496 }
4497 }
4498 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4499 }
4500 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4501 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4502 /* no handling is needed for SRQ */
4503 if (!mqp->ibqp.srq) {
4504 if (mqp->rq.tail != mqp->rq.head) {
4505 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4506 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4507 if (recv_mcq->mcq.comp &&
4508 mqp->ibqp.recv_cq->comp_handler) {
4509 if (!recv_mcq->mcq.reset_notify_added) {
4510 recv_mcq->mcq.reset_notify_added = 1;
4511 list_add_tail(&recv_mcq->mcq.reset_notify,
4512 &cq_armed_list);
4513 }
4514 }
4515 spin_unlock_irqrestore(&recv_mcq->lock,
4516 flags_cq);
4517 }
4518 }
4519 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4520 }
4521 /*At that point all inflight post send were put to be executed as of we
4522 * lock/unlock above locks Now need to arm all involved CQs.
4523 */
4524 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 4525 mcq->comp(mcq, NULL);
89ea94a7
MG		 4526 }
4527 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4528}
4529
03404e8a
MG		 4530static void delay_drop_handler(struct work_struct *work)
4531{
4532 int err;
4533 struct mlx5_ib_delay_drop *delay_drop =
4534 container_of(work, struct mlx5_ib_delay_drop,
4535 delay_drop_work);
4536
fe248c3a
MG		 4537 atomic_inc(&delay_drop->events_cnt);
4538
03404e8a
MG		 4539 mutex_lock(&delay_drop->lock);
4540 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4541 delay_drop->timeout);
4542 if (err) {
4543 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4544 delay_drop->timeout);
4545 delay_drop->activate = false;
4546 }
4547 mutex_unlock(&delay_drop->lock);
4548}
4549
09e574fa
SM		 4550static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4551 struct ib_event *ibev)
4552{
6cfdc7e4
AL		 4553 u8 port = (eqe->data.port.port >> 4) & 0xf;
4554
09e574fa
SM		 4555 switch (eqe->sub_type) {
4556 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4557 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4558 IB_LINK_LAYER_ETHERNET)
4559 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4560 break;
4561 default: /* do nothing */
4562 return;
4563 }
4564}
4565
134e9349
SM		 4566static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4567 struct ib_event *ibev)
4568{
4569 u8 port = (eqe->data.port.port >> 4) & 0xf;
4570
4571 ibev->element.port_num = port;
4572
4573 switch (eqe->sub_type) {
4574 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4575 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4576 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4577 /* In RoCE, port up/down events are handled in
4578 * mlx5_netdev_event().
4579 */
4580 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4581 IB_LINK_LAYER_ETHERNET)
4582 return -EINVAL;
4583
4584 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4585 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4586 break;
4587
4588 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4589 ibev->event = IB_EVENT_LID_CHANGE;
4590 break;
4591
4592 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4593 ibev->event = IB_EVENT_PKEY_CHANGE;
4594 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4595 break;
4596
4597 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4598 ibev->event = IB_EVENT_GID_CHANGE;
4599 break;
4600
4601 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4602 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4603 break;
4604 default:
4605 return -EINVAL;
4606 }
4607
4608 return 0;
4609}
4610
d69a24e0 4611static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4612{
d69a24e0
DJ		 4613 struct mlx5_ib_event_work *work =
4614 container_of(_work, struct mlx5_ib_event_work, work);
4615 struct mlx5_ib_dev *ibdev;
e126ba97 4616 struct ib_event ibev;
dbaaff2a 4617 bool fatal = false;
e126ba97 4618
df097a27
SM		 4619 if (work->is_slave) {
4620 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4621 if (!ibdev)
4622 goto out;
4623 } else {
df097a27 4624 ibdev = work->dev;
d69a24e0
DJ		 4625 }
4626
4627 switch (work->event) {
e126ba97 4628 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4629 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4630 mlx5_ib_handle_internal_error(ibdev);
134e9349 4631 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4632 fatal = true;
e126ba97 4633 break;
134e9349
SM		 4634 case MLX5_EVENT_TYPE_PORT_CHANGE:
4635 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4636 goto out;
e126ba97 4637 break;
09e574fa
SM		 4638 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4639 handle_general_event(ibdev, work->param, &ibev);
4640 /* fall through */
bdc37924 4641 default:
03404e8a 4642 goto out;
e126ba97
EC		 4643 }
4644
134e9349 4645 ibev.device = &ibdev->ib_dev;
e126ba97 4646
134e9349
SM		 4647 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4648 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4649 goto out;
a0c84c32
EC		 4650 }
4651
e126ba97
EC		 4652 if (ibdev->ib_active)
4653 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4654
4655 if (fatal)
4656 ibdev->ib_active = false;
03404e8a 4657out:
d69a24e0
DJ		 4658 kfree(work);
4659}
4660
df097a27
SM		 4661static int mlx5_ib_event(struct notifier_block *nb,
4662 unsigned long event, void *param)
d69a24e0
DJ		 4663{
4664 struct mlx5_ib_event_work *work;
4665
4666 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4667 if (!work)
df097a27 4668 return NOTIFY_DONE;
d69a24e0 4669
10bea9c8 4670 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4671 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4672 work->is_slave = false;
10bea9c8 4673 work->param = param;
10bea9c8
LR		 4674 work->event = event;
4675
4676 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4677
4678 return NOTIFY_OK;
4679}
4680
4681static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4682 unsigned long event, void *param)
4683{
4684 struct mlx5_ib_event_work *work;
4685
4686 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4687 if (!work)
4688 return NOTIFY_DONE;
4689
4690 INIT_WORK(&work->work, mlx5_ib_handle_event);
4691 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4692 work->is_slave = true;
4693 work->param = param;
4694 work->event = event;
4695 queue_work(mlx5_ib_event_wq, &work->work);
4696
4697 return NOTIFY_OK;
e126ba97
EC		 4698}
4699
c43f1112
MG		 4700static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4701{
4702 struct mlx5_hca_vport_context vport_ctx;
4703 int err;
4704 int port;
4705
a989ea01 4706 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4707 dev->mdev->port_caps[port - 1].has_smi = false;
4708 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4709 MLX5_CAP_PORT_TYPE_IB) {
4710 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4711 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4712 port, 0,
4713 &vport_ctx);
4714 if (err) {
4715 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4716 port, err);
4717 return err;
4718 }
4719 dev->mdev->port_caps[port - 1].has_smi =
4720 vport_ctx.has_smi;
4721 } else {
4722 dev->mdev->port_caps[port - 1].has_smi = true;
4723 }
4724 }
4725 }
4726 return 0;
4727}
4728
e126ba97
EC		 4729static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4730{
4731 int port;
4732
508562d6 4733 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4734 mlx5_query_ext_port_caps(dev, port);
4735}
4736
26628e2d 4737static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4738{
4739 struct ib_device_attr *dprops = NULL;
4740 struct ib_port_attr *pprops = NULL;
f614fc15 4741 int err = -ENOMEM;
2528e33e 4742 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97 4743
50ba3c18 4744 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
e126ba97
EC		 4745 if (!pprops)
4746 goto out;
4747
4748 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4749 if (!dprops)
4750 goto out;
4751
2528e33e 4752 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 4753 if (err) {
4754 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4755 goto out;
4756 }
4757
32f69e4b
DJ		 4758 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4759 if (err) {
4760 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4761 port, err);
4762 goto out;
e126ba97
EC		 4763 }
4764
32f69e4b
DJ		 4765 dev->mdev->port_caps[port - 1].pkey_table_len =
4766 dprops->max_pkeys;
4767 dev->mdev->port_caps[port - 1].gid_table_len =
4768 pprops->gid_tbl_len;
4769 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4770 port, dprops->max_pkeys, pprops->gid_tbl_len);
4771
e126ba97
EC		 4772out:
4773 kfree(pprops);
4774 kfree(dprops);
4775
4776 return err;
4777}
4778
26628e2d
MB		 4779static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4780{
4781 /* For representors use port 1, is this is the only native
4782 * port
4783 */
4784 if (dev->is_rep)
4785 return __get_port_caps(dev, 1);
4786 return __get_port_caps(dev, port);
4787}
4788
e126ba97
EC		 4789static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4790{
4791 int err;
4792
4793 err = mlx5_mr_cache_cleanup(dev);
4794 if (err)
4795 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4796
32927e28 4797 if (dev->umrc.qp)
c4367a26 4798 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4799 if (dev->umrc.cq)
4800 ib_free_cq(dev->umrc.cq);
4801 if (dev->umrc.pd)
4802 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4803}
4804
4805enum {
4806 MAX_UMR_WR = 128,
4807};
4808
4809static int create_umr_res(struct mlx5_ib_dev *dev)
4810{
4811 struct ib_qp_init_attr *init_attr = NULL;
4812 struct ib_qp_attr *attr = NULL;
4813 struct ib_pd *pd;
4814 struct ib_cq *cq;
4815 struct ib_qp *qp;
e126ba97
EC		 4816 int ret;
4817
4818 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4819 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4820 if (!attr || !init_attr) {
4821 ret = -ENOMEM;
4822 goto error_0;
4823 }
4824
ed082d36 4825 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4826 if (IS_ERR(pd)) {
4827 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4828 ret = PTR_ERR(pd);
4829 goto error_0;
4830 }
4831
add08d76 4832 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4833 if (IS_ERR(cq)) {
4834 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4835 ret = PTR_ERR(cq);
4836 goto error_2;
4837 }
e126ba97
EC		 4838
4839 init_attr->send_cq = cq;
4840 init_attr->recv_cq = cq;
4841 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4842 init_attr->cap.max_send_wr = MAX_UMR_WR;
4843 init_attr->cap.max_send_sge = 1;
4844 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4845 init_attr->port_num = 1;
4846 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4847 if (IS_ERR(qp)) {
4848 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4849 ret = PTR_ERR(qp);
4850 goto error_3;
4851 }
4852 qp->device = &dev->ib_dev;
4853 qp->real_qp = qp;
4854 qp->uobject = NULL;
4855 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4856 qp->send_cq = init_attr->send_cq;
4857 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4858
4859 attr->qp_state = IB_QPS_INIT;
4860 attr->port_num = 1;
4861 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4862 IB_QP_PORT, NULL);
4863 if (ret) {
4864 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4865 goto error_4;
4866 }
4867
4868 memset(attr, 0, sizeof(*attr));
4869 attr->qp_state = IB_QPS_RTR;
4870 attr->path_mtu = IB_MTU_256;
4871
4872 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4873 if (ret) {
4874 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4875 goto error_4;
4876 }
4877
4878 memset(attr, 0, sizeof(*attr));
4879 attr->qp_state = IB_QPS_RTS;
4880 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4881 if (ret) {
4882 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4883 goto error_4;
4884 }
4885
4886 dev->umrc.qp = qp;
4887 dev->umrc.cq = cq;
e126ba97
EC		 4888 dev->umrc.pd = pd;
4889
4890 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4891 ret = mlx5_mr_cache_init(dev);
4892 if (ret) {
4893 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4894 goto error_4;
4895 }
4896
4897 kfree(attr);
4898 kfree(init_attr);
4899
4900 return 0;
4901
4902error_4:
c4367a26 4903 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4904 dev->umrc.qp = NULL;
e126ba97
EC		 4905
4906error_3:
add08d76 4907 ib_free_cq(cq);
32927e28 4908 dev->umrc.cq = NULL;
e126ba97
EC		 4909
4910error_2:
e126ba97 4911 ib_dealloc_pd(pd);
32927e28 4912 dev->umrc.pd = NULL;
e126ba97
EC		 4913
4914error_0:
4915 kfree(attr);
4916 kfree(init_attr);
4917 return ret;
4918}
4919
6e8484c5
MG		 4920static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4921{
4922 switch (umr_fence_cap) {
4923 case MLX5_CAP_UMR_FENCE_NONE:
4924 return MLX5_FENCE_MODE_NONE;
4925 case MLX5_CAP_UMR_FENCE_SMALL:
4926 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4927 default:
4928 return MLX5_FENCE_MODE_STRONG_ORDERING;
4929 }
4930}
4931
e126ba97
EC		 4932static int create_dev_resources(struct mlx5_ib_resources *devr)
4933{
4934 struct ib_srq_init_attr attr;
4935 struct mlx5_ib_dev *dev;
21a428a0 4936 struct ib_device *ibdev;
bcf4c1ea 4937 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4938 int port;
e126ba97
EC		 4939 int ret = 0;
4940
4941 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 4942 ibdev = &dev->ib_dev;
e126ba97 4943
d16e91da
HE		 4944 mutex_init(&devr->mutex);
4945
21a428a0
LR		 4946 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4947 if (!devr->p0)
4948 return -ENOMEM;
4949
4950 devr->p0->device = ibdev;
e126ba97
EC		 4951 devr->p0->uobject = NULL;
4952 atomic_set(&devr->p0->usecnt, 0);
4953
ff23dfa1 4954 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 4955 if (ret)
4956 goto error0;
4957
e39afe3d
LR		 4958 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4959 if (!devr->c0) {
4960 ret = -ENOMEM;
e126ba97
EC		 4961 goto error1;
4962 }
e39afe3d
LR		 4963
4964 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 4965 atomic_set(&devr->c0->usecnt, 0);
4966
e39afe3d
LR		 4967 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4968 if (ret)
4969 goto err_create_cq;
4970
ff23dfa1 4971 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4972 if (IS_ERR(devr->x0)) {
4973 ret = PTR_ERR(devr->x0);
4974 goto error2;
4975 }
4976 devr->x0->device = &dev->ib_dev;
4977 devr->x0->inode = NULL;
4978 atomic_set(&devr->x0->usecnt, 0);
4979 mutex_init(&devr->x0->tgt_qp_mutex);
4980 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4981
ff23dfa1 4982 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4983 if (IS_ERR(devr->x1)) {
4984 ret = PTR_ERR(devr->x1);
4985 goto error3;
4986 }
4987 devr->x1->device = &dev->ib_dev;
4988 devr->x1->inode = NULL;
4989 atomic_set(&devr->x1->usecnt, 0);
4990 mutex_init(&devr->x1->tgt_qp_mutex);
4991 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4992
4993 memset(&attr, 0, sizeof(attr));
4994 attr.attr.max_sge = 1;
4995 attr.attr.max_wr = 1;
4996 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4997 attr.ext.cq = devr->c0;
e126ba97
EC		 4998 attr.ext.xrc.xrcd = devr->x0;
4999
68e326de
LR		 5000 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5001 if (!devr->s0) {
5002 ret = -ENOMEM;
e126ba97
EC		 5003 goto error4;
5004 }
68e326de 5005
e126ba97
EC		 5006 devr->s0->device = &dev->ib_dev;
5007 devr->s0->pd = devr->p0;
e126ba97
EC		 5008 devr->s0->srq_type = IB_SRQT_XRC;
5009 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 5010 devr->s0->ext.cq = devr->c0;
68e326de
LR		 5011 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5012 if (ret)
5013 goto err_create;
5014
e126ba97 5015 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 5016 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 5017 atomic_inc(&devr->p0->usecnt);
5018 atomic_set(&devr->s0->usecnt, 0);
5019
4aa17b28
HA		 5020 memset(&attr, 0, sizeof(attr));
5021 attr.attr.max_sge = 1;
5022 attr.attr.max_wr = 1;
5023 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 5024 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5025 if (!devr->s1) {
5026 ret = -ENOMEM;
4aa17b28
HA		 5027 goto error5;
5028 }
68e326de 5029
4aa17b28
HA		 5030 devr->s1->device = &dev->ib_dev;
5031 devr->s1->pd = devr->p0;
4aa17b28 5032 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 5033 devr->s1->ext.cq = devr->c0;
68e326de
LR		 5034
5035 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5036 if (ret)
5037 goto error6;
5038
4aa17b28 5039 atomic_inc(&devr->p0->usecnt);
1a56ff6d 5040 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 5041
7722f47e
HE		 5042 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5043 INIT_WORK(&devr->ports[port].pkey_change_work,
5044 pkey_change_handler);
5045 devr->ports[port].devr = devr;
5046 }
5047
e126ba97
EC		 5048 return 0;
5049
68e326de
LR		 5050error6:
5051 kfree(devr->s1);
4aa17b28 5052error5:
c4367a26 5053 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 5054err_create:
5055 kfree(devr->s0);
e126ba97 5056error4:
c4367a26 5057 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5058error3:
c4367a26 5059 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5060error2:
c4367a26 5061 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5062err_create_cq:
5063 kfree(devr->c0);
e126ba97 5064error1:
c4367a26 5065 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5066error0:
21a428a0 5067 kfree(devr->p0);
e126ba97
EC		 5068 return ret;
5069}
5070
5071static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5072{
7722f47e
HE		 5073 int port;
5074
c4367a26 5075 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5076 kfree(devr->s1);
c4367a26 5077 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5078 kfree(devr->s0);
c4367a26
SR		 5079 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5080 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5081 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5082 kfree(devr->c0);
c4367a26 5083 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5084 kfree(devr->p0);
7722f47e
HE		 5085
5086 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5087 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5088 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5089}
5090
b02289b3
AK		 5091static u32 get_core_cap_flags(struct ib_device *ibdev,
5092 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5093{
5094 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5095 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5096 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5097 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5098 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5099 u32 ret = 0;
5100
b02289b3
AK		 5101 if (rep->grh_required)
5102 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5103
e53505a8 5104 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5105 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5106
85c7c014 5107 if (raw_support)
b02289b3 5108 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5109
e53505a8 5110 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5111 return ret;
e53505a8
AS		 5112
5113 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5114 return ret;
e53505a8
AS		 5115
5116 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5117 ret |= RDMA_CORE_PORT_IBA_ROCE;
5118
5119 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5120 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5121
5122 return ret;
5123}
5124
7738613e
IW		 5125static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5126 struct ib_port_immutable *immutable)
5127{
5128 struct ib_port_attr attr;
ca5b91d6
OG		 5129 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5130 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5131 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5132 int err;
5133
c4550c63 5134 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5135 if (err)
5136 return err;
5137
b02289b3
AK		 5138 if (ll == IB_LINK_LAYER_INFINIBAND) {
5139 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5140 &rep);
5141 if (err)
5142 return err;
5143 }
5144
7738613e
IW		 5145 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5146 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5147 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
ca5b91d6
OG		 5148 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5149 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5150
5151 return 0;
5152}
5153
8e6efa3a
MB		 5154static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5155 struct ib_port_immutable *immutable)
5156{
5157 struct ib_port_attr attr;
5158 int err;
5159
5160 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5161
5162 err = ib_query_port(ibdev, port_num, &attr);
5163 if (err)
5164 return err;
5165
5166 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5167 immutable->gid_tbl_len = attr.gid_tbl_len;
5168 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5169
5170 return 0;
5171}
5172
9abb0d1b 5173static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5174{
5175 struct mlx5_ib_dev *dev =
5176 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5177 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5178 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5179 fw_rev_sub(dev->mdev));
c7342823
IW		 5180}
5181
45f95acd 5182static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5183{
5184 struct mlx5_core_dev *mdev = dev->mdev;
5185 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5186 MLX5_FLOW_NAMESPACE_LAG);
5187 struct mlx5_flow_table *ft;
5188 int err;
5189
7c34ec19 5190 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5191 return 0;
5192
5193 err = mlx5_cmd_create_vport_lag(mdev);
5194 if (err)
5195 return err;
5196
5197 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5198 if (IS_ERR(ft)) {
5199 err = PTR_ERR(ft);
5200 goto err_destroy_vport_lag;
5201 }
5202
9a4ca38d 5203 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5204 dev->lag_active = true;
9ef9c640
AH		 5205 return 0;
5206
5207err_destroy_vport_lag:
5208 mlx5_cmd_destroy_vport_lag(mdev);
5209 return err;
5210}
5211
45f95acd 5212static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5213{
5214 struct mlx5_core_dev *mdev = dev->mdev;
5215
7c34ec19
AH		 5216 if (dev->lag_active) {
5217 dev->lag_active = false;
5218
9a4ca38d
MB		 5219 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5220 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5221
5222 mlx5_cmd_destroy_vport_lag(mdev);
5223 }
5224}
5225
7fd8aefb 5226static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5227{
5228 int err;
5229
95579e78
MB		 5230 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5231 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5232 if (err) {
95579e78 5233 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5234 return err;
5235 }
5236
5237 return 0;
5238}
5239
7fd8aefb 5240static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5241{
95579e78
MB		 5242 if (dev->port[port_num].roce.nb.notifier_call) {
5243 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5244 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5245 }
5246}
5247
e3f1ed1f 5248static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5249{
e53505a8
AS		 5250 int err;
5251
ca5b91d6
OG		 5252 if (MLX5_CAP_GEN(dev->mdev, roce)) {
5253 err = mlx5_nic_vport_enable_roce(dev->mdev);
5254 if (err)
8e6efa3a 5255 return err;
ca5b91d6 5256 }
e53505a8 5257
45f95acd 5258 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5259 if (err)
5260 goto err_disable_roce;
5261
e53505a8
AS		 5262 return 0;
5263
9ef9c640 5264err_disable_roce:
ca5b91d6
OG		 5265 if (MLX5_CAP_GEN(dev->mdev, roce))
5266 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5267
e53505a8 5268 return err;
fc24fc5e
AS		 5269}
5270
45f95acd 5271static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5272{
45f95acd 5273 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 5274 if (MLX5_CAP_GEN(dev->mdev, roce))
5275 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5276}
5277
e1f24a79 5278struct mlx5_ib_counter {
7c16f477
KH		 5279 const char *name;
5280 size_t offset;
5281};
5282
5283#define INIT_Q_COUNTER(_name) \
5284 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5285
e1f24a79 5286static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5287 INIT_Q_COUNTER(rx_write_requests),
5288 INIT_Q_COUNTER(rx_read_requests),
5289 INIT_Q_COUNTER(rx_atomic_requests),
5290 INIT_Q_COUNTER(out_of_buffer),
5291};
5292
e1f24a79 5293static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5294 INIT_Q_COUNTER(out_of_sequence),
5295};
5296
e1f24a79 5297static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5298 INIT_Q_COUNTER(duplicate_request),
5299 INIT_Q_COUNTER(rnr_nak_retry_err),
5300 INIT_Q_COUNTER(packet_seq_err),
5301 INIT_Q_COUNTER(implied_nak_seq_err),
5302 INIT_Q_COUNTER(local_ack_timeout_err),
5303};
5304
e1f24a79
PP		 5305#define INIT_CONG_COUNTER(_name) \
5306 { .name = #_name, .offset = \
5307 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5308
5309static const struct mlx5_ib_counter cong_cnts[] = {
5310 INIT_CONG_COUNTER(rp_cnp_ignored),
5311 INIT_CONG_COUNTER(rp_cnp_handled),
5312 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5313 INIT_CONG_COUNTER(np_cnp_sent),
5314};
5315
58dcb60a
PP		 5316static const struct mlx5_ib_counter extended_err_cnts[] = {
5317 INIT_Q_COUNTER(resp_local_length_error),
5318 INIT_Q_COUNTER(resp_cqe_error),
5319 INIT_Q_COUNTER(req_cqe_error),
5320 INIT_Q_COUNTER(req_remote_invalid_request),
5321 INIT_Q_COUNTER(req_remote_access_errors),
5322 INIT_Q_COUNTER(resp_remote_access_errors),
5323 INIT_Q_COUNTER(resp_cqe_flush_error),
5324 INIT_Q_COUNTER(req_cqe_flush_error),
5325};
5326
9f876f3d
TB		 5327#define INIT_EXT_PPCNT_COUNTER(_name) \
5328 { .name = #_name, .offset = \
5329 MLX5_BYTE_OFF(ppcnt_reg, \
5330 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5331
5332static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5333 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5334};
5335
3e1f000f
PP		 5336static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5337{
5338 return MLX5_ESWITCH_MANAGER(mdev) &&
5339 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5340 MLX5_ESWITCH_OFFLOADS;
5341}
5342
e1f24a79 5343static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5344{
3e1f000f 5345 int num_cnt_ports;
aac4492e 5346 int i;
0837e86a 5347
3e1f000f
PP		 5348 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5349
5350 for (i = 0; i < num_cnt_ports; i++) {
921c0f5b 5351 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5352 mlx5_core_dealloc_q_counter(dev->mdev,
5353 dev->port[i].cnts.set_id);
e1f24a79
PP		 5354 kfree(dev->port[i].cnts.names);
5355 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5356 }
5357}
5358
e1f24a79
PP		 5359static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5360 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5361{
5362 u32 num_counters;
5363
5364 num_counters = ARRAY_SIZE(basic_q_cnts);
5365
5366 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5367 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5368
5369 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5370 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5371
5372 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5373 num_counters += ARRAY_SIZE(extended_err_cnts);
5374
e1f24a79 5375 cnts->num_q_counters = num_counters;
7c16f477 5376
e1f24a79
PP		 5377 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5378 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5379 num_counters += ARRAY_SIZE(cong_cnts);
5380 }
9f876f3d
TB		 5381 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5382 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5383 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5384 }
e1f24a79
PP		 5385 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5386 if (!cnts->names)
7c16f477
KH		 5387 return -ENOMEM;
5388
e1f24a79
PP		 5389 cnts->offsets = kcalloc(num_counters,
5390 sizeof(cnts->offsets), GFP_KERNEL);
5391 if (!cnts->offsets)
7c16f477
KH		 5392 goto err_names;
5393
7c16f477
KH		 5394 return 0;
5395
5396err_names:
e1f24a79 5397 kfree(cnts->names);
aac4492e 5398 cnts->names = NULL;
7c16f477
KH		 5399 return -ENOMEM;
5400}
5401
e1f24a79
PP		 5402static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5403 const char **names,
5404 size_t *offsets)
7c16f477
KH		 5405{
5406 int i;
5407 int j = 0;
5408
5409 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5410 names[j] = basic_q_cnts[i].name;
5411 offsets[j] = basic_q_cnts[i].offset;
5412 }
5413
5414 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5415 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5416 names[j] = out_of_seq_q_cnts[i].name;
5417 offsets[j] = out_of_seq_q_cnts[i].offset;
5418 }
5419 }
5420
5421 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5422 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5423 names[j] = retrans_q_cnts[i].name;
5424 offsets[j] = retrans_q_cnts[i].offset;
5425 }
5426 }
e1f24a79 5427
58dcb60a
PP		 5428 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5429 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5430 names[j] = extended_err_cnts[i].name;
5431 offsets[j] = extended_err_cnts[i].offset;
5432 }
5433 }
5434
e1f24a79
PP		 5435 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5436 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5437 names[j] = cong_cnts[i].name;
5438 offsets[j] = cong_cnts[i].offset;
5439 }
5440 }
9f876f3d
TB		 5441
5442 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5443 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5444 names[j] = ext_ppcnt_cnts[i].name;
5445 offsets[j] = ext_ppcnt_cnts[i].offset;
5446 }
5447 }
0837e86a
MB		 5448}
5449
e1f24a79 5450static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5451{
3e1f000f 5452 int num_cnt_ports;
aac4492e 5453 int err = 0;
0837e86a 5454 int i;
aa74be6e
YH		 5455 bool is_shared;
5456
5457 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
3e1f000f 5458 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
0837e86a 5459
3e1f000f 5460 for (i = 0; i < num_cnt_ports; i++) {
aac4492e
DJ		 5461 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5462 if (err)
5463 goto err_alloc;
5464
5465 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5466 dev->port[i].cnts.offsets);
7c16f477 5467
aa74be6e
YH		 5468 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5469 &dev->port[i].cnts.set_id,
5470 is_shared ?
5471 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5472 if (err) {
0837e86a
MB		 5473 mlx5_ib_warn(dev,
5474 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5475 i + 1, err);
5476 goto err_alloc;
0837e86a 5477 }
aac4492e 5478 dev->port[i].cnts.set_id_valid = true;
0837e86a 5479 }
0837e86a
MB		 5480 return 0;
5481
aac4492e
DJ		 5482err_alloc:
5483 mlx5_ib_dealloc_counters(dev);
5484 return err;
0837e86a
MB		 5485}
5486
3e1f000f
PP		 5487static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5488 u8 port_num)
5489{
5490 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5491 &dev->port[port_num].cnts;
5492}
5493
5494/**
5495 * mlx5_ib_get_counters_id - Returns counters id to use for device+port
5496 * @dev: Pointer to mlx5 IB device
5497 * @port_num: Zero based port number
5498 *
5499 * mlx5_ib_get_counters_id() Returns counters set id to use for given
5500 * device port combination in switchdev and non switchdev mode of the
5501 * parent device.
5502 */
5503u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5504{
5505 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5506
5507 return cnts->set_id;
5508}
5509
0ad17a8f
MB		 5510static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5511 u8 port_num)
5512{
7c16f477 5513 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f
PP		 5514 const struct mlx5_ib_counters *cnts;
5515 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
0ad17a8f 5516
3e1f000f 5517 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
0ad17a8f
MB		 5518 return NULL;
5519
3e1f000f
PP		 5520 cnts = get_counters(dev, port_num - 1);
5521
5dcecbc9
PP		 5522 return rdma_alloc_hw_stats_struct(cnts->names,
5523 cnts->num_q_counters +
5524 cnts->num_cong_counters +
5525 cnts->num_ext_ppcnt_counters,
0ad17a8f
MB		 5526 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5527}
5528
aac4492e 5529static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5dcecbc9 5530 const struct mlx5_ib_counters *cnts,
318d535c
MZ		 5531 struct rdma_hw_stats *stats,
5532 u16 set_id)
0ad17a8f 5533{
0ad17a8f
MB		 5534 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5535 void *out;
5536 __be32 val;
e1f24a79 5537 int ret, i;
0ad17a8f 5538
1b9a07ee 5539 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5540 if (!out)
5541 return -ENOMEM;
5542
318d535c 5543 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
0ad17a8f
MB		 5544 if (ret)
5545 goto free;
5546
5dcecbc9
PP		 5547 for (i = 0; i < cnts->num_q_counters; i++) {
5548 val = *(__be32 *)(out + cnts->offsets[i]);
0ad17a8f
MB		 5549 stats->value[i] = (u64)be32_to_cpu(val);
5550 }
7c16f477 5551
0ad17a8f
MB		 5552free:
5553 kvfree(out);
e1f24a79
PP		 5554 return ret;
5555}
5556
9f876f3d 5557static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5dcecbc9
PP		 5558 const struct mlx5_ib_counters *cnts,
5559 struct rdma_hw_stats *stats)
9f876f3d 5560{
5dcecbc9 5561 int offset = cnts->num_q_counters + cnts->num_cong_counters;
9f876f3d
TB		 5562 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5563 int ret, i;
5564 void *out;
5565
5566 out = kvzalloc(sz, GFP_KERNEL);
5567 if (!out)
5568 return -ENOMEM;
5569
5570 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5571 if (ret)
5572 goto free;
5573
5dcecbc9 5574 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
9f876f3d
TB		 5575 stats->value[i + offset] =
5576 be64_to_cpup((__be64 *)(out +
5dcecbc9 5577 cnts->offsets[i + offset]));
9f876f3d
TB		 5578free:
5579 kvfree(out);
5580 return ret;
5581}
5582
e1f24a79
PP		 5583static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5584 struct rdma_hw_stats *stats,
5585 u8 port_num, int index)
5586{
5587 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f 5588 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
aac4492e 5589 struct mlx5_core_dev *mdev;
e1f24a79 5590 int ret, num_counters;
aac4492e 5591 u8 mdev_port_num;
e1f24a79
PP		 5592
5593 if (!stats)
5594 return -EINVAL;
5595
5dcecbc9
PP		 5596 num_counters = cnts->num_q_counters +
5597 cnts->num_cong_counters +
5598 cnts->num_ext_ppcnt_counters;
aac4492e
DJ		 5599
5600 /* q_counters are per IB device, query the master mdev */
5dcecbc9 5601 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
e1f24a79
PP		 5602 if (ret)
5603 return ret;
e1f24a79 5604
9f876f3d 5605 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5dcecbc9 5606 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
9f876f3d
TB		 5607 if (ret)
5608 return ret;
5609 }
5610
e1f24a79 5611 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5612 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5613 &mdev_port_num);
5614 if (!mdev) {
5615 /* If port is not affiliated yet, its in down state
5616 * which doesn't have any counters yet, so it would be
5617 * zero. So no need to read from the HCA.
5618 */
5619 goto done;
5620 }
71a0ff65
MD		 5621 ret = mlx5_lag_query_cong_counters(dev->mdev,
5622 stats->value +
5dcecbc9
PP		 5623 cnts->num_q_counters,
5624 cnts->num_cong_counters,
5625 cnts->offsets +
5626 cnts->num_q_counters);
aac4492e
DJ		 5627
5628 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5629 if (ret)
5630 return ret;
e1f24a79
PP		 5631 }
5632
aac4492e 5633done:
e1f24a79 5634 return num_counters;
0ad17a8f
MB		 5635}
5636
18d422ce
MZ		 5637static struct rdma_hw_stats *
5638mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5639{
5640 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5dcecbc9 5641 const struct mlx5_ib_counters *cnts =
3e1f000f 5642 get_counters(dev, counter->port - 1);
18d422ce
MZ		 5643
5644 /* Q counters are in the beginning of all counters */
5dcecbc9
PP		 5645 return rdma_alloc_hw_stats_struct(cnts->names,
5646 cnts->num_q_counters,
18d422ce
MZ		 5647 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5648}
5649
5650static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5651{
5652 struct mlx5_ib_dev *dev = to_mdev(counter->device);
3e1f000f
PP		 5653 const struct mlx5_ib_counters *cnts =
5654 get_counters(dev, counter->port - 1);
18d422ce 5655
5dcecbc9 5656 return mlx5_ib_query_q_counters(dev->mdev, cnts,
18d422ce
MZ		 5657 counter->stats, counter->id);
5658}
5659
45842fc6
MZ		 5660static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5661 struct ib_qp *qp)
5662{
5663 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5664 u16 cnt_set_id = 0;
5665 int err;
5666
5667 if (!counter->id) {
5668 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5669 &cnt_set_id,
5670 MLX5_SHARED_RESOURCE_UID);
5671 if (err)
5672 return err;
5673 counter->id = cnt_set_id;
5674 }
5675
5676 err = mlx5_ib_qp_set_counter(qp, counter);
5677 if (err)
5678 goto fail_set_counter;
5679
5680 return 0;
5681
5682fail_set_counter:
5683 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5684 counter->id = 0;
5685
5686 return err;
5687}
5688
5689static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5690{
5691 return mlx5_ib_qp_set_counter(qp, NULL);
5692}
5693
5694static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5695{
5696 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5697
5698 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5699}
5700
f6a8a19b
DD		 5701static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5702 enum rdma_netdev_t type,
5703 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5704{
5705 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5706 return -EOPNOTSUPP;
693dfd5a 5707
f6a8a19b 5708 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5709}
5710
fe248c3a
MG		 5711static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5712{
5713 if (!dev->delay_drop.dbg)
5714 return;
5715 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5716 kfree(dev->delay_drop.dbg);
5717 dev->delay_drop.dbg = NULL;
5718}
5719
03404e8a
MG		 5720static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5721{
5722 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5723 return;
5724
5725 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5726 delay_drop_debugfs_cleanup(dev);
5727}
5728
5729static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5730 size_t count, loff_t *pos)
5731{
5732 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5733 char lbuf[20];
5734 int len;
5735
5736 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5737 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5738}
5739
5740static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5741 size_t count, loff_t *pos)
5742{
5743 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5744 u32 timeout;
5745 u32 var;
5746
5747 if (kstrtouint_from_user(buf, count, 0, &var))
5748 return -EFAULT;
5749
5750 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5751 1000);
5752 if (timeout != var)
5753 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5754 timeout);
5755
5756 delay_drop->timeout = timeout;
5757
5758 return count;
5759}
5760
5761static const struct file_operations fops_delay_drop_timeout = {
5762 .owner = THIS_MODULE,
5763 .open = simple_open,
5764 .write = delay_drop_timeout_write,
5765 .read = delay_drop_timeout_read,
5766};
5767
5768static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5769{
5770 struct mlx5_ib_dbg_delay_drop *dbg;
5771
5772 if (!mlx5_debugfs_root)
5773 return 0;
5774
5775 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5776 if (!dbg)
5777 return -ENOMEM;
5778
cbafad87
SM		 5779 dev->delay_drop.dbg = dbg;
5780
fe248c3a
MG		 5781 dbg->dir_debugfs =
5782 debugfs_create_dir("delay_drop",
5783 dev->mdev->priv.dbg_root);
5784 if (!dbg->dir_debugfs)
cbafad87 5785 goto out_debugfs;
fe248c3a
MG		 5786
5787 dbg->events_cnt_debugfs =
5788 debugfs_create_atomic_t("num_timeout_events", 0400,
5789 dbg->dir_debugfs,
5790 &dev->delay_drop.events_cnt);
5791 if (!dbg->events_cnt_debugfs)
5792 goto out_debugfs;
5793
5794 dbg->rqs_cnt_debugfs =
5795 debugfs_create_atomic_t("num_rqs", 0400,
5796 dbg->dir_debugfs,
5797 &dev->delay_drop.rqs_cnt);
5798 if (!dbg->rqs_cnt_debugfs)
5799 goto out_debugfs;
5800
5801 dbg->timeout_debugfs =
5802 debugfs_create_file("timeout", 0600,
5803 dbg->dir_debugfs,
5804 &dev->delay_drop,
5805 &fops_delay_drop_timeout);
5806 if (!dbg->timeout_debugfs)
5807 goto out_debugfs;
5808
5809 return 0;
5810
5811out_debugfs:
5812 delay_drop_debugfs_cleanup(dev);
5813 return -ENOMEM;
03404e8a
MG		 5814}
5815
5816static void init_delay_drop(struct mlx5_ib_dev *dev)
5817{
5818 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5819 return;
5820
5821 mutex_init(&dev->delay_drop.lock);
5822 dev->delay_drop.dev = dev;
5823 dev->delay_drop.activate = false;
5824 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5825 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5826 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5827 atomic_set(&dev->delay_drop.events_cnt, 0);
5828
5829 if (delay_drop_debugfs_init(dev))
5830 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5831}
5832
32f69e4b
DJ		 5833static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5834 struct mlx5_ib_multiport_info *mpi)
5835{
5836 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5837 struct mlx5_ib_port *port = &ibdev->port[port_num];
5838 int comps;
5839 int err;
5840 int i;
5841
9dc4cfff
LR		 5842 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5843
a9e546e7
PP		 5844 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5845
32f69e4b
DJ		 5846 spin_lock(&port->mp.mpi_lock);
5847 if (!mpi->ibdev) {
5848 spin_unlock(&port->mp.mpi_lock);
5849 return;
5850 }
df097a27 5851
32f69e4b
DJ		 5852 mpi->ibdev = NULL;
5853
5854 spin_unlock(&port->mp.mpi_lock);
23eaf3b5
LR		 5855 if (mpi->mdev_events.notifier_call)
5856 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5857 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5858 mlx5_remove_netdev_notifier(ibdev, port_num);
5859 spin_lock(&port->mp.mpi_lock);
5860
5861 comps = mpi->mdev_refcnt;
5862 if (comps) {
5863 mpi->unaffiliate = true;
5864 init_completion(&mpi->unref_comp);
5865 spin_unlock(&port->mp.mpi_lock);
5866
5867 for (i = 0; i < comps; i++)
5868 wait_for_completion(&mpi->unref_comp);
5869
5870 spin_lock(&port->mp.mpi_lock);
5871 mpi->unaffiliate = false;
5872 }
5873
5874 port->mp.mpi = NULL;
5875
5876 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5877
5878 spin_unlock(&port->mp.mpi_lock);
5879
5880 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5881
5882 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5883 /* Log an error, still needed to cleanup the pointers and add
5884 * it back to the list.
5885 */
5886 if (err)
5887 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5888 port_num + 1);
5889
95579e78 5890 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5891}
5892
32f69e4b
DJ		 5893static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5894 struct mlx5_ib_multiport_info *mpi)
5895{
5896 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5897 int err;
5898
9dc4cfff
LR		 5899 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5900
32f69e4b
DJ		 5901 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5902 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5903 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5904 port_num + 1);
32f69e4b
DJ		 5905 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5906 return false;
5907 }
5908
5909 ibdev->port[port_num].mp.mpi = mpi;
5910 mpi->ibdev = ibdev;
df097a27 5911 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5912 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5913
5914 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5915 if (err)
5916 goto unbind;
5917
5918 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5919 if (err)
5920 goto unbind;
5921
5922 err = mlx5_add_netdev_notifier(ibdev, port_num);
5923 if (err) {
5924 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5925 port_num + 1);
5926 goto unbind;
5927 }
5928
df097a27
SM		 5929 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5930 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5931
73eb8f03 5932 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5933
32f69e4b
DJ		 5934 return true;
5935
5936unbind:
5937 mlx5_ib_unbind_slave_port(ibdev, mpi);
5938 return false;
5939}
5940
5941static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5942{
5943 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5944 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5945 port_num + 1);
5946 struct mlx5_ib_multiport_info *mpi;
5947 int err;
5948 int i;
5949
5950 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5951 return 0;
5952
5953 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5954 &dev->sys_image_guid);
5955 if (err)
5956 return err;
5957
5958 err = mlx5_nic_vport_enable_roce(dev->mdev);
5959 if (err)
5960 return err;
5961
5962 mutex_lock(&mlx5_ib_multiport_mutex);
5963 for (i = 0; i < dev->num_ports; i++) {
5964 bool bound = false;
5965
5966 /* build a stub multiport info struct for the native port. */
5967 if (i == port_num) {
5968 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5969 if (!mpi) {
5970 mutex_unlock(&mlx5_ib_multiport_mutex);
5971 mlx5_nic_vport_disable_roce(dev->mdev);
5972 return -ENOMEM;
5973 }
5974
5975 mpi->is_master = true;
5976 mpi->mdev = dev->mdev;
5977 mpi->sys_image_guid = dev->sys_image_guid;
5978 dev->port[i].mp.mpi = mpi;
5979 mpi->ibdev = dev;
5980 mpi = NULL;
5981 continue;
5982 }
5983
5984 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5985 list) {
5986 if (dev->sys_image_guid == mpi->sys_image_guid &&
5987 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5988 bound = mlx5_ib_bind_slave_port(dev, mpi);
5989 }
5990
5991 if (bound) {
c42260f1
VP		 5992 dev_dbg(mpi->mdev->device,
5993 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 5994 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5995 list_del(&mpi->list);
5996 break;
5997 }
5998 }
5999 if (!bound) {
6000 get_port_caps(dev, i + 1);
6001 mlx5_ib_dbg(dev, "no free port found for port %d\n",
6002 i + 1);
6003 }
6004 }
6005
6006 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
6007 mutex_unlock(&mlx5_ib_multiport_mutex);
6008 return err;
6009}
6010
6011static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6012{
6013 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6014 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6015 port_num + 1);
6016 int i;
6017
6018 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6019 return;
6020
6021 mutex_lock(&mlx5_ib_multiport_mutex);
6022 for (i = 0; i < dev->num_ports; i++) {
6023 if (dev->port[i].mp.mpi) {
6024 /* Destroy the native port stub */
6025 if (i == port_num) {
6026 kfree(dev->port[i].mp.mpi);
6027 dev->port[i].mp.mpi = NULL;
6028 } else {
6029 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
6030 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
6031 }
6032 }
6033 }
6034
6035 mlx5_ib_dbg(dev, "removing from devlist\n");
6036 list_del(&dev->ib_dev_list);
6037 mutex_unlock(&mlx5_ib_multiport_mutex);
6038
6039 mlx5_nic_vport_disable_roce(dev->mdev);
6040}
6041
9a119cd5
JG		 6042ADD_UVERBS_ATTRIBUTES_SIMPLE(
6043 mlx5_ib_dm,
6044 UVERBS_OBJECT_DM,
6045 UVERBS_METHOD_DM_ALLOC,
6046 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6047 UVERBS_ATTR_TYPE(u64),
83bb4442 6048 UA_MANDATORY),
9a119cd5
JG		 6049 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6050 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 6051 UA_OPTIONAL),
6052 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6053 enum mlx5_ib_uapi_dm_type,
6054 UA_OPTIONAL));
9a119cd5
JG		 6055
6056ADD_UVERBS_ATTRIBUTES_SIMPLE(
6057 mlx5_ib_flow_action,
6058 UVERBS_OBJECT_FLOW_ACTION,
6059 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 6060 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6061 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 6062
0cbf432d
JG		 6063static const struct uapi_definition mlx5_ib_defs[] = {
6064#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 6065 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 6066 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6067#endif
8c84660b 6068
0cbf432d
JG		 6069 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6070 &mlx5_ib_flow_action),
6071 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6072 {}
6073};
8c84660b 6074
1a1e03dc
RS		 6075static int mlx5_ib_read_counters(struct ib_counters *counters,
6076 struct ib_counters_read_attr *read_attr,
6077 struct uverbs_attr_bundle *attrs)
6078{
6079 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6080 struct mlx5_read_counters_attr mread_attr = {};
6081 struct mlx5_ib_flow_counters_desc *desc;
6082 int ret, i;
6083
6084 mutex_lock(&mcounters->mcntrs_mutex);
6085 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6086 ret = -EINVAL;
6087 goto err_bound;
6088 }
6089
6090 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6091 GFP_KERNEL);
6092 if (!mread_attr.out) {
6093 ret = -ENOMEM;
6094 goto err_bound;
6095 }
6096
6097 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6098 mread_attr.flags = read_attr->flags;
6099 ret = mcounters->read_counters(counters->device, &mread_attr);
6100 if (ret)
6101 goto err_read;
6102
6103 /* do the pass over the counters data array to assign according to the
6104 * descriptions and indexing pairs
6105 */
6106 desc = mcounters->counters_data;
6107 for (i = 0; i < mcounters->ncounters; i++)
6108 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6109
6110err_read:
6111 kfree(mread_attr.out);
6112err_bound:
6113 mutex_unlock(&mcounters->mcntrs_mutex);
6114 return ret;
6115}
6116
b29e2a13
RS		 6117static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6118{
6119 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6120
3b3233fb
RS		 6121 counters_clear_description(counters);
6122 if (mcounters->hw_cntrs_hndl)
6123 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6124 mcounters->hw_cntrs_hndl);
6125
b29e2a13
RS		 6126 kfree(mcounters);
6127
6128 return 0;
6129}
6130
6131static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6132 struct uverbs_attr_bundle *attrs)
6133{
6134 struct mlx5_ib_mcounters *mcounters;
6135
6136 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6137 if (!mcounters)
6138 return ERR_PTR(-ENOMEM);
6139
3b3233fb
RS		 6140 mutex_init(&mcounters->mcntrs_mutex);
6141
b29e2a13
RS		 6142 return &mcounters->ibcntrs;
6143}
6144
fb652d32 6145static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 6146{
32f69e4b 6147 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 6148 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 6149 srcu_barrier(&dev->mr_srcu);
13859d5d 6150 cleanup_srcu_struct(&dev->mr_srcu);
13859d5d 6151 }
4056b12e
AL		 6152
6153 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
16c1975f
MB		 6154}
6155
fb652d32 6156static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6157{
6158 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 6159 int err;
32f69e4b 6160 int i;
e126ba97 6161
32f69e4b
DJ		 6162 for (i = 0; i < dev->num_ports; i++) {
6163 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6164 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6165 dev->port[i].roce.dev = dev;
6166 dev->port[i].roce.native_port_num = i + 1;
6167 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6168 }
6169
00815752
MS		 6170 mlx5_ib_internal_fill_odp_caps(dev);
6171
32f69e4b 6172 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6173 if (err)
da796ccb 6174 return err;
e126ba97 6175
a989ea01
MB		 6176 err = set_has_smi_cap(dev);
6177 if (err)
6178 return err;
e126ba97 6179
32f69e4b 6180 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6181 for (i = 1; i <= dev->num_ports; i++) {
6182 err = get_port_caps(dev, i);
6183 if (err)
6184 break;
6185 }
6186 } else {
6187 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6188 }
6189 if (err)
6190 goto err_mp;
6191
1b5daf11
MD		 6192 if (mlx5_use_mad_ifc(dev))
6193 get_ext_port_caps(dev);
e126ba97 6194
e126ba97 6195 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6196 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6197 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6198 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6199 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6200
3cc297db
MB		 6201 mutex_init(&dev->cap_mask_mutex);
6202 INIT_LIST_HEAD(&dev->qp_list);
6203 spin_lock_init(&dev->reset_flow_resource_lock);
6204
3b113a1e
AL		 6205 spin_lock_init(&dev->dm.lock);
6206 dev->dm.dev = mdev;
24da0016 6207
13859d5d 6208 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
13859d5d 6209 err = init_srcu_struct(&dev->mr_srcu);
a6bc3875 6210 if (err)
c9b9dcb4 6211 goto err_mp;
623d1543 6212 }
3cc297db 6213
16c1975f 6214 return 0;
25c13324 6215
32f69e4b
DJ		 6216err_mp:
6217 mlx5_ib_cleanup_multiport_master(dev);
16c1975f 6218
16c1975f
MB		 6219 return -ENOMEM;
6220}
6221
9a4ca38d
MB		 6222static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6223{
6224 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6225
6226 if (!dev->flow_db)
6227 return -ENOMEM;
6228
6229 mutex_init(&dev->flow_db->lock);
6230
6231 return 0;
6232}
6233
6234static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6235{
6236 kfree(dev->flow_db);
6237}
6238
96458233 6239static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6240 .owner = THIS_MODULE,
b9560a41 6241 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6242 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6243
96458233
KH		 6244 .add_gid = mlx5_ib_add_gid,
6245 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 6246 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 6247 .alloc_pd = mlx5_ib_alloc_pd,
6248 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6249 .attach_mcast = mlx5_ib_mcg_attach,
6250 .check_mr_status = mlx5_ib_check_mr_status,
6251 .create_ah = mlx5_ib_create_ah,
6252 .create_counters = mlx5_ib_create_counters,
6253 .create_cq = mlx5_ib_create_cq,
6254 .create_flow = mlx5_ib_create_flow,
6255 .create_qp = mlx5_ib_create_qp,
6256 .create_srq = mlx5_ib_create_srq,
6257 .dealloc_pd = mlx5_ib_dealloc_pd,
6258 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6259 .del_gid = mlx5_ib_del_gid,
6260 .dereg_mr = mlx5_ib_dereg_mr,
6261 .destroy_ah = mlx5_ib_destroy_ah,
6262 .destroy_counters = mlx5_ib_destroy_counters,
6263 .destroy_cq = mlx5_ib_destroy_cq,
6264 .destroy_flow = mlx5_ib_destroy_flow,
6265 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6266 .destroy_qp = mlx5_ib_destroy_qp,
6267 .destroy_srq = mlx5_ib_destroy_srq,
6268 .detach_mcast = mlx5_ib_mcg_detach,
6269 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6270 .drain_rq = mlx5_ib_drain_rq,
6271 .drain_sq = mlx5_ib_drain_sq,
6272 .get_dev_fw_str = get_dev_fw_str,
6273 .get_dma_mr = mlx5_ib_get_dma_mr,
6274 .get_link_layer = mlx5_ib_port_link_layer,
6275 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 6276 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233
KH		 6277 .mmap = mlx5_ib_mmap,
6278 .modify_cq = mlx5_ib_modify_cq,
6279 .modify_device = mlx5_ib_modify_device,
6280 .modify_port = mlx5_ib_modify_port,
6281 .modify_qp = mlx5_ib_modify_qp,
6282 .modify_srq = mlx5_ib_modify_srq,
6283 .poll_cq = mlx5_ib_poll_cq,
6284 .post_recv = mlx5_ib_post_recv,
6285 .post_send = mlx5_ib_post_send,
6286 .post_srq_recv = mlx5_ib_post_srq_recv,
6287 .process_mad = mlx5_ib_process_mad,
6288 .query_ah = mlx5_ib_query_ah,
6289 .query_device = mlx5_ib_query_device,
6290 .query_gid = mlx5_ib_query_gid,
6291 .query_pkey = mlx5_ib_query_pkey,
6292 .query_qp = mlx5_ib_query_qp,
6293 .query_srq = mlx5_ib_query_srq,
6294 .read_counters = mlx5_ib_read_counters,
6295 .reg_user_mr = mlx5_ib_reg_user_mr,
6296 .req_notify_cq = mlx5_ib_arm_cq,
6297 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6298 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6299
6300 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6301 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6302 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6303 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6304 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6305};
6306
6307static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6308 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6309 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6310};
6311
6312static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6313 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6314};
6315
6316static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6317 .get_vf_config = mlx5_ib_get_vf_config,
6318 .get_vf_stats = mlx5_ib_get_vf_stats,
6319 .set_vf_guid = mlx5_ib_set_vf_guid,
6320 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6321};
6322
6323static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6324 .alloc_mw = mlx5_ib_alloc_mw,
6325 .dealloc_mw = mlx5_ib_dealloc_mw,
6326};
6327
6328static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6329 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6330 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6331};
6332
6333static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6334 .alloc_dm = mlx5_ib_alloc_dm,
6335 .dealloc_dm = mlx5_ib_dealloc_dm,
6336 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6337};
6338
fb652d32 6339static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6340{
6341 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6342 int err;
6343
e126ba97
EC		 6344 dev->ib_dev.uverbs_cmd_mask =
6345 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6346 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6347 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6348 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6349 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6350 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6351 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6352 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6353 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6354 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6355 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6356 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6357 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6358 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6359 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6360 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6361 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6362 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6363 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6364 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6365 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6366 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6367 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6368 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6369 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6370 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6371 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6372 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6373 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6374 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6375 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6376 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6377 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6378 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6379
f6a8a19b
DD		 6380 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6381 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6382 ib_set_device_ops(&dev->ib_dev,
6383 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6384
96458233
KH		 6385 if (mlx5_core_is_pf(mdev))
6386 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6387
6e8484c5
MG		 6388 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6389
d2370e0a 6390 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6391 dev->ib_dev.uverbs_cmd_mask |=
6392 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6393 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6394 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6395 }
6396
938fe83c 6397 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6398 dev->ib_dev.uverbs_cmd_mask |=
6399 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6400 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6401 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6402 }
6403
25c13324
AL		 6404 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6405 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6406 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6407 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6408
dfb631a1 6409 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6410 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6411 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6412 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6413
36e235c8
JG		 6414 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6415 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6416
e126ba97
EC		 6417 err = init_node_data(dev);
6418 if (err)
16c1975f 6419 return err;
e126ba97 6420
c8b89924 6421 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6422 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6423 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6424 mutex_init(&dev->lb.mutex);
c8b89924 6425
96e2fd73
LR		 6426 dev->ib_dev.use_cq_dim = true;
6427
16c1975f
MB		 6428 return 0;
6429}
6430
96458233
KH		 6431static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6432 .get_port_immutable = mlx5_port_immutable,
6433 .query_port = mlx5_ib_query_port,
6434};
6435
8e6efa3a
MB		 6436static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6437{
96458233 6438 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6439 return 0;
6440}
6441
96458233
KH		 6442static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6443 .get_port_immutable = mlx5_port_rep_immutable,
6444 .query_port = mlx5_ib_rep_query_port,
6445};
6446
fb652d32 6447static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6448{
96458233 6449 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6450 return 0;
6451}
6452
96458233
KH		 6453static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6454 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6455 .create_wq = mlx5_ib_create_wq,
6456 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6457 .destroy_wq = mlx5_ib_destroy_wq,
6458 .get_netdev = mlx5_ib_get_netdev,
6459 .modify_wq = mlx5_ib_modify_wq,
6460};
6461
e3f1ed1f 6462static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6463{
e3f1ed1f 6464 u8 port_num;
8e6efa3a 6465
8e6efa3a
MB		 6466 dev->ib_dev.uverbs_ex_cmd_mask |=
6467 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6468 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6469 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6470 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6471 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6472 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6473
e3f1ed1f
LR		 6474 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6475
26628e2d 6476 /* Register only for native ports */
8e6efa3a
MB		 6477 return mlx5_add_netdev_notifier(dev, port_num);
6478}
6479
6480static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6481{
6482 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6483
6484 mlx5_remove_netdev_notifier(dev, port_num);
6485}
6486
fb652d32 6487static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6488{
6489 struct mlx5_core_dev *mdev = dev->mdev;
6490 enum rdma_link_layer ll;
6491 int port_type_cap;
6492 int err = 0;
8e6efa3a 6493
8e6efa3a
MB		 6494 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6495 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6496
6497 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6498 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6499
6500 return err;
6501}
6502
fb652d32 6503static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6504{
6505 mlx5_ib_stage_common_roce_cleanup(dev);
6506}
6507
16c1975f
MB		 6508static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6509{
6510 struct mlx5_core_dev *mdev = dev->mdev;
6511 enum rdma_link_layer ll;
6512 int port_type_cap;
6513 int err;
6514
6515 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6516 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6517
fc24fc5e 6518 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6519 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6520 if (err)
6521 return err;
7fd8aefb 6522
e3f1ed1f 6523 err = mlx5_enable_eth(dev);
fc24fc5e 6524 if (err)
8e6efa3a 6525 goto cleanup;
fc24fc5e
AS		 6526 }
6527
16c1975f 6528 return 0;
8e6efa3a
MB		 6529cleanup:
6530 mlx5_ib_stage_common_roce_cleanup(dev);
6531
6532 return err;
16c1975f 6533}
e126ba97 6534
16c1975f
MB		 6535static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6536{
6537 struct mlx5_core_dev *mdev = dev->mdev;
6538 enum rdma_link_layer ll;
6539 int port_type_cap;
e126ba97 6540
16c1975f
MB		 6541 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6542 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6543
6544 if (ll == IB_LINK_LAYER_ETHERNET) {
6545 mlx5_disable_eth(dev);
8e6efa3a 6546 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6547 }
16c1975f 6548}
6aec21f6 6549
fb652d32 6550static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6551{
6552 return create_dev_resources(&dev->devr);
6553}
6554
fb652d32 6555static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6556{
6557 destroy_dev_resources(&dev->devr);
6558}
6559
6560static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6561{
6562 return mlx5_ib_odp_init_one(dev);
6563}
4a2da0b8 6564
f3ffed0c 6565static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6566{
6567 mlx5_ib_odp_cleanup_one(dev);
6568}
6569
96458233
KH		 6570static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6571 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6572 .get_hw_stats = mlx5_ib_get_hw_stats,
45842fc6
MZ		 6573 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6574 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6575 .counter_dealloc = mlx5_ib_counter_dealloc,
18d422ce
MZ		 6576 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6577 .counter_update_stats = mlx5_ib_counter_update_stats,
96458233
KH		 6578};
6579
fb652d32 6580static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6581{
5e1e7612 6582 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6583 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6584
6585 return mlx5_ib_alloc_counters(dev);
6586 }
16c1975f
MB		 6587
6588 return 0;
6589}
6590
fb652d32 6591static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6592{
6593 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6594 mlx5_ib_dealloc_counters(dev);
6595}
6596
6597static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6598{
73eb8f03
GKH		 6599 mlx5_ib_init_cong_debugfs(dev,
6600 mlx5_core_native_port_num(dev->mdev) - 1);
6601 return 0;
16c1975f
MB		 6602}
6603
6604static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6605{
a9e546e7
PP		 6606 mlx5_ib_cleanup_cong_debugfs(dev,
6607 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6608}
6609
6610static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6611{
5fe9dec0 6612 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6613 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6614}
6615
6616static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6617{
6618 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6619}
6620
fb652d32 6621static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6622{
6623 int err;
5fe9dec0
EC		 6624
6625 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6626 if (err)
16c1975f 6627 return err;
5fe9dec0
EC		 6628
6629 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6630 if (err)
16c1975f 6631 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 6632
16c1975f
MB		 6633 return err;
6634}
0837e86a 6635
fb652d32 6636static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6637{
6638 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6639 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6640}
e126ba97 6641
fb652d32 6642static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6643{
e349f858
JG		 6644 const char *name;
6645
508a523f 6646 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6647 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6648 name = "mlx5_%d";
6649 else
6650 name = "mlx5_bond_%d";
ea4baf7f 6651 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6652}
6653
fb652d32 6654static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6655{
42cea83f 6656 destroy_umrc_res(dev);
16c1975f
MB		 6657}
6658
fb652d32 6659static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6660{
42cea83f 6661 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6662}
6663
fb652d32 6664static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6665{
42cea83f 6666 return create_umr_res(dev);
16c1975f
MB		 6667}
6668
6669static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6670{
03404e8a
MG		 6671 init_delay_drop(dev);
6672
16c1975f
MB		 6673 return 0;
6674}
6675
6676static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6677{
6678 cancel_delay_drop(dev);
6679}
6680
df097a27
SM		 6681static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6682{
6683 dev->mdev_events.notifier_call = mlx5_ib_event;
6684 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6685 return 0;
6686}
6687
6688static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6689{
6690 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6691}
6692
81773ce5
LR		 6693static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6694{
6695 int uid;
6696
fb98153b 6697 uid = mlx5_ib_devx_create(dev, false);
e337dd53 6698 if (uid > 0) {
81773ce5 6699 dev->devx_whitelist_uid = uid;
e337dd53
YH		 6700 mlx5_ib_devx_init_event_table(dev);
6701 }
81773ce5
LR		 6702
6703 return 0;
6704}
6705static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6706{
e337dd53
YH		 6707 if (dev->devx_whitelist_uid) {
6708 mlx5_ib_devx_cleanup_event_table(dev);
81773ce5 6709 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
e337dd53 6710 }
81773ce5
LR		 6711}
6712
b5ca15ad
MB		 6713void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6714 const struct mlx5_ib_profile *profile,
6715 int stage)
16c1975f
MB		 6716{
6717 /* Number of stages to cleanup */
6718 while (stage) {
6719 stage--;
6720 if (profile->stage[stage].cleanup)
6721 profile->stage[stage].cleanup(dev);
6722 }
4a6dc855 6723
da796ccb 6724 kfree(dev->port);
4a6dc855 6725 ib_dealloc_device(&dev->ib_dev);
16c1975f 6726}
e126ba97 6727
b5ca15ad
MB		 6728void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6729 const struct mlx5_ib_profile *profile)
16c1975f 6730{
16c1975f
MB		 6731 int err;
6732 int i;
5fe9dec0 6733
16c1975f
MB		 6734 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6735 if (profile->stage[i].init) {
6736 err = profile->stage[i].init(dev);
6737 if (err)
6738 goto err_out;
6739 }
6740 }
0837e86a 6741
16c1975f
MB		 6742 dev->profile = profile;
6743 dev->ib_active = true;
6aec21f6 6744
16c1975f 6745 return dev;
e126ba97 6746
16c1975f
MB		 6747err_out:
6748 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6749
16c1975f
MB		 6750 return NULL;
6751}
0837e86a 6752
16c1975f
MB		 6753static const struct mlx5_ib_profile pf_profile = {
6754 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6755 mlx5_ib_stage_init_init,
6756 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6757 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6758 mlx5_ib_stage_flow_db_init,
6759 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6760 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6761 mlx5_ib_stage_caps_init,
6762 NULL),
8e6efa3a
MB		 6763 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6764 mlx5_ib_stage_non_default_cb,
6765 NULL),
16c1975f
MB		 6766 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6767 mlx5_ib_stage_roce_init,
6768 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6769 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6770 mlx5_init_srq_table,
6771 mlx5_cleanup_srq_table),
16c1975f
MB		 6772 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6773 mlx5_ib_stage_dev_res_init,
6774 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6775 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6776 mlx5_ib_stage_dev_notifier_init,
6777 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6778 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6779 mlx5_ib_stage_odp_init,
d5d284b8 6780 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6781 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6782 mlx5_ib_stage_counters_init,
6783 mlx5_ib_stage_counters_cleanup),
6784 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6785 mlx5_ib_stage_cong_debugfs_init,
6786 mlx5_ib_stage_cong_debugfs_cleanup),
6787 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6788 mlx5_ib_stage_uar_init,
6789 mlx5_ib_stage_uar_cleanup),
6790 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6791 mlx5_ib_stage_bfrag_init,
6792 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6793 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6794 NULL,
6795 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6796 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6797 mlx5_ib_stage_devx_init,
6798 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6799 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6800 mlx5_ib_stage_ib_reg_init,
6801 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6802 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6803 mlx5_ib_stage_post_ib_reg_umr_init,
6804 NULL),
16c1975f
MB		 6805 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6806 mlx5_ib_stage_delay_drop_init,
6807 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6808};
e126ba97 6809
f0666f1f 6810const struct mlx5_ib_profile uplink_rep_profile = {
b5ca15ad
MB		 6811 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6812 mlx5_ib_stage_init_init,
6813 mlx5_ib_stage_init_cleanup),
6814 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6815 mlx5_ib_stage_flow_db_init,
6816 mlx5_ib_stage_flow_db_cleanup),
6817 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6818 mlx5_ib_stage_caps_init,
6819 NULL),
6820 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6821 mlx5_ib_stage_rep_non_default_cb,
6822 NULL),
6823 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6824 mlx5_ib_stage_rep_roce_init,
6825 mlx5_ib_stage_rep_roce_cleanup),
f3da6577
LR		 6826 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6827 mlx5_init_srq_table,
6828 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6829 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6830 mlx5_ib_stage_dev_res_init,
6831 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6832 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6833 mlx5_ib_stage_dev_notifier_init,
6834 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6835 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6836 mlx5_ib_stage_counters_init,
6837 mlx5_ib_stage_counters_cleanup),
6838 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6839 mlx5_ib_stage_uar_init,
6840 mlx5_ib_stage_uar_cleanup),
6841 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6842 mlx5_ib_stage_bfrag_init,
6843 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6844 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6845 NULL,
6846 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 6847 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6848 mlx5_ib_stage_devx_init,
6849 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 6850 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6851 mlx5_ib_stage_ib_reg_init,
6852 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6853 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6854 mlx5_ib_stage_post_ib_reg_umr_init,
6855 NULL),
b5ca15ad
MB		 6856};
6857
e3f1ed1f 6858static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6859{
6860 struct mlx5_ib_multiport_info *mpi;
6861 struct mlx5_ib_dev *dev;
6862 bool bound = false;
6863 int err;
6864
6865 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6866 if (!mpi)
6867 return NULL;
6868
6869 mpi->mdev = mdev;
6870
6871 err = mlx5_query_nic_vport_system_image_guid(mdev,
6872 &mpi->sys_image_guid);
6873 if (err) {
6874 kfree(mpi);
6875 return NULL;
6876 }
6877
6878 mutex_lock(&mlx5_ib_multiport_mutex);
6879 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6880 if (dev->sys_image_guid == mpi->sys_image_guid)
6881 bound = mlx5_ib_bind_slave_port(dev, mpi);
6882
6883 if (bound) {
6884 rdma_roce_rescan_device(&dev->ib_dev);
6885 break;
6886 }
6887 }
6888
6889 if (!bound) {
6890 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 6891 dev_dbg(mdev->device,
6892 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6893 }
6894 mutex_unlock(&mlx5_ib_multiport_mutex);
6895
6896 return mpi;
6897}
6898
16c1975f
MB		 6899static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6900{
32f69e4b 6901 enum rdma_link_layer ll;
b5ca15ad 6902 struct mlx5_ib_dev *dev;
32f69e4b 6903 int port_type_cap;
da796ccb 6904 int num_ports;
32f69e4b 6905
b5ca15ad
MB		 6906 printk_once(KERN_INFO "%s", mlx5_version);
6907
f0666f1f 6908 if (MLX5_ESWITCH_MANAGER(mdev) &&
f6455de0 6909 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5fb58c9e
MB		 6910 if (!mlx5_core_mp_enabled(mdev))
6911 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 6912 return mdev;
6913 }
6914
32f69e4b
DJ		 6915 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6916 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6917
e3f1ed1f
LR		 6918 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6919 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6920
da796ccb
MB		 6921 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6922 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 6923 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 6924 if (!dev)
6925 return NULL;
da796ccb
MB		 6926 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6927 GFP_KERNEL);
6928 if (!dev->port) {
a5c9c299 6929 ib_dealloc_device(&dev->ib_dev);
da796ccb
MB		 6930 return NULL;
6931 }
b5ca15ad
MB		 6932
6933 dev->mdev = mdev;
da796ccb 6934 dev->num_ports = num_ports;
b5ca15ad 6935
b5ca15ad 6936 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 6937}
6938
9603b61d 6939static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6940{
32f69e4b
DJ		 6941 struct mlx5_ib_multiport_info *mpi;
6942 struct mlx5_ib_dev *dev;
6943
f0666f1f
BW		 6944 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6945 mlx5_ib_unregister_vport_reps(mdev);
6946 return;
6947 }
6948
32f69e4b
DJ		 6949 if (mlx5_core_is_mp_slave(mdev)) {
6950 mpi = context;
6951 mutex_lock(&mlx5_ib_multiport_mutex);
6952 if (mpi->ibdev)
6953 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6954 list_del(&mpi->list);
6955 mutex_unlock(&mlx5_ib_multiport_mutex);
5d44adeb 6956 kfree(mpi);
32f69e4b
DJ		 6957 return;
6958 }
6aec21f6 6959
32f69e4b 6960 dev = context;
f0666f1f 6961 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6962}
6963
9603b61d
JM		 6964static struct mlx5_interface mlx5_ib_interface = {
6965 .add = mlx5_ib_add,
6966 .remove = mlx5_ib_remove,
64613d94 6967 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6968};
6969
c44ef998
IL		 6970unsigned long mlx5_ib_get_xlt_emergency_page(void)
6971{
6972 mutex_lock(&xlt_emergency_page_mutex);
6973 return xlt_emergency_page;
6974}
6975
6976void mlx5_ib_put_xlt_emergency_page(void)
6977{
6978 mutex_unlock(&xlt_emergency_page_mutex);
6979}
6980
e126ba97
EC		 6981static int __init mlx5_ib_init(void)
6982{
6aec21f6
HE		 6983 int err;
6984
c44ef998
IL		 6985 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6986 if (!xlt_emergency_page)
6987 return -ENOMEM;
6988
6989 mutex_init(&xlt_emergency_page_mutex);
6990
d69a24e0 6991 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6992 if (!mlx5_ib_event_wq) {
6993 free_page(xlt_emergency_page);
d69a24e0 6994 return -ENOMEM;
c44ef998 6995 }
d69a24e0 6996
81713d37 6997 mlx5_ib_odp_init();
9603b61d 6998
6aec21f6 6999 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 7000
6aec21f6 7001 return err;
e126ba97
EC		 7002}
7003
7004static void __exit mlx5_ib_cleanup(void)
7005{
9603b61d 7006 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 7007 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 7008 mutex_destroy(&xlt_emergency_page_mutex);
7009 free_page(xlt_emergency_page);
e126ba97
EC		 7010}
7011
7012module_init(mlx5_ib_init);
7013module_exit(mlx5_ib_cleanup);
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