]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/infiniband/hw/mlx5/main.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'ntb-4.13-bugfixes' of git://github.com/jonmason/ntb
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
37aa5c36
GL		 40#if defined(CONFIG_X86)
41#include <asm/pat.h>
42#endif
e126ba97 43#include <linux/sched.h>
6e84f315 44#include <linux/sched/mm.h>
0881e7bd 45#include <linux/sched/task.h>
7c2344c3 46#include <linux/delay.h>
e126ba97 47#include <rdma/ib_user_verbs.h>
3f89a643 48#include <rdma/ib_addr.h>
2811ba51 49#include <rdma/ib_cache.h>
ada68c31 50#include <linux/mlx5/port.h>
1b5daf11 51#include <linux/mlx5/vport.h>
7c2344c3 52#include <linux/list.h>
e126ba97
EC		 53#include <rdma/ib_smi.h>
54#include <rdma/ib_umem.h>
038d2ef8
MG		 55#include <linux/in.h>
56#include <linux/etherdevice.h>
57#include <linux/mlx5/fs.h>
78984898 58#include <linux/mlx5/vport.h>
e126ba97 59#include "mlx5_ib.h"
e1f24a79 60#include "cmd.h"
e126ba97
EC		 61
62#define DRIVER_NAME "mlx5_ib"
b359911d 63#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
68MODULE_VERSION(DRIVER_VERSION);
69
e126ba97
EC		 70static char mlx5_version[] =
71 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 72 DRIVER_VERSION "\n";
e126ba97 73
da7525d2
EBE		 74enum {
75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
76};
77
1b5daf11 78static enum rdma_link_layer
ebd61f68 79mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 80{
ebd61f68 81 switch (port_type_cap) {
1b5daf11
MD		 82 case MLX5_CAP_PORT_TYPE_IB:
83 return IB_LINK_LAYER_INFINIBAND;
84 case MLX5_CAP_PORT_TYPE_ETH:
85 return IB_LINK_LAYER_ETHERNET;
86 default:
87 return IB_LINK_LAYER_UNSPECIFIED;
88 }
89}
90
ebd61f68
AS		 91static enum rdma_link_layer
92mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
93{
94 struct mlx5_ib_dev *dev = to_mdev(device);
95 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
96
97 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
98}
99
fc24fc5e
AS		 100static int mlx5_netdev_event(struct notifier_block *this,
101 unsigned long event, void *ptr)
102{
103 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
104 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
105 roce.nb);
106
5ec8c83e
AH		 107 switch (event) {
108 case NETDEV_REGISTER:
109 case NETDEV_UNREGISTER:
110 write_lock(&ibdev->roce.netdev_lock);
111 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
112 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
113 NULL : ndev;
114 write_unlock(&ibdev->roce.netdev_lock);
115 break;
fc24fc5e 116
5ec8c83e 117 case NETDEV_UP:
88621dfe
AH		 118 case NETDEV_DOWN: {
119 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
120 struct net_device *upper = NULL;
121
122 if (lag_ndev) {
123 upper = netdev_master_upper_dev_get(lag_ndev);
124 dev_put(lag_ndev);
125 }
126
127 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
128 && ibdev->ib_active) {
626bc02d 129 struct ib_event ibev = { };
5ec8c83e
AH		 130
131 ibev.device = &ibdev->ib_dev;
132 ibev.event = (event == NETDEV_UP) ?
133 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
134 ibev.element.port_num = 1;
135 ib_dispatch_event(&ibev);
136 }
137 break;
88621dfe 138 }
fc24fc5e 139
5ec8c83e
AH		 140 default:
141 break;
142 }
fc24fc5e
AS		 143
144 return NOTIFY_DONE;
145}
146
147static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
148 u8 port_num)
149{
150 struct mlx5_ib_dev *ibdev = to_mdev(device);
151 struct net_device *ndev;
152
88621dfe
AH		 153 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
154 if (ndev)
155 return ndev;
156
fc24fc5e
AS		 157 /* Ensure ndev does not disappear before we invoke dev_hold()
158 */
159 read_lock(&ibdev->roce.netdev_lock);
160 ndev = ibdev->roce.netdev;
161 if (ndev)
162 dev_hold(ndev);
163 read_unlock(&ibdev->roce.netdev_lock);
164
165 return ndev;
166}
167
f1b65df5
NO		 168static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
169 u8 *active_width)
170{
171 switch (eth_proto_oper) {
172 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
173 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
174 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
175 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
176 *active_width = IB_WIDTH_1X;
177 *active_speed = IB_SPEED_SDR;
178 break;
179 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
180 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
181 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
182 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
183 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
184 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
185 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
186 *active_width = IB_WIDTH_1X;
187 *active_speed = IB_SPEED_QDR;
188 break;
189 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
190 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
191 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
192 *active_width = IB_WIDTH_1X;
193 *active_speed = IB_SPEED_EDR;
194 break;
195 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
196 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
197 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
198 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
199 *active_width = IB_WIDTH_4X;
200 *active_speed = IB_SPEED_QDR;
201 break;
202 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
203 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
204 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
205 *active_width = IB_WIDTH_1X;
206 *active_speed = IB_SPEED_HDR;
207 break;
208 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
209 *active_width = IB_WIDTH_4X;
210 *active_speed = IB_SPEED_FDR;
211 break;
212 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
213 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
214 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
215 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
216 *active_width = IB_WIDTH_4X;
217 *active_speed = IB_SPEED_EDR;
218 break;
219 default:
220 return -EINVAL;
221 }
222
223 return 0;
224}
225
095b0927
IT		 226static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
227 struct ib_port_attr *props)
3f89a643
AS		 228{
229 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 230 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 231 struct net_device *ndev, *upper;
3f89a643 232 enum ib_mtu ndev_ib_mtu;
c876a1b7 233 u16 qkey_viol_cntr;
f1b65df5 234 u32 eth_prot_oper;
095b0927 235 int err;
3f89a643 236
f1b65df5
NO		 237 /* Possible bad flows are checked before filling out props so in case
238 * of an error it will still be zeroed out.
50f22fd8 239 */
095b0927
IT		 240 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
241 if (err)
242 return err;
f1b65df5
NO		 243
244 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
245 &props->active_width);
3f89a643
AS		 246
247 props->port_cap_flags |= IB_PORT_CM_SUP;
248 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
249
250 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
251 roce_address_table_size);
252 props->max_mtu = IB_MTU_4096;
253 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
254 props->pkey_tbl_len = 1;
255 props->state = IB_PORT_DOWN;
256 props->phys_state = 3;
257
c876a1b7
LR		 258 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
259 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 260
261 ndev = mlx5_ib_get_netdev(device, port_num);
262 if (!ndev)
095b0927 263 return 0;
3f89a643 264
88621dfe
AH		 265 if (mlx5_lag_is_active(dev->mdev)) {
266 rcu_read_lock();
267 upper = netdev_master_upper_dev_get_rcu(ndev);
268 if (upper) {
269 dev_put(ndev);
270 ndev = upper;
271 dev_hold(ndev);
272 }
273 rcu_read_unlock();
274 }
275
3f89a643
AS		 276 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
277 props->state = IB_PORT_ACTIVE;
278 props->phys_state = 5;
279 }
280
281 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
282
283 dev_put(ndev);
284
285 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 286 return 0;
3f89a643
AS		 287}
288
095b0927
IT		 289static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
290 unsigned int index, const union ib_gid *gid,
291 const struct ib_gid_attr *attr)
3cca2606 292{
095b0927
IT		 293 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
294 u8 roce_version = 0;
295 u8 roce_l3_type = 0;
296 bool vlan = false;
297 u8 mac[ETH_ALEN];
298 u16 vlan_id = 0;
299
300 if (gid) {
301 gid_type = attr->gid_type;
302 ether_addr_copy(mac, attr->ndev->dev_addr);
303
304 if (is_vlan_dev(attr->ndev)) {
305 vlan = true;
306 vlan_id = vlan_dev_vlan_id(attr->ndev);
307 }
3cca2606
AS		 308 }
309
095b0927 310 switch (gid_type) {
3cca2606 311 case IB_GID_TYPE_IB:
095b0927 312 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 313 break;
314 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 315 roce_version = MLX5_ROCE_VERSION_2;
316 if (ipv6_addr_v4mapped((void *)gid))
317 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
318 else
319 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 320 break;
321
322 default:
095b0927 323 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 324 }
325
095b0927
IT		 326 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
327 roce_l3_type, gid->raw, mac, vlan,
328 vlan_id);
3cca2606
AS		 329}
330
331static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
332 unsigned int index, const union ib_gid *gid,
333 const struct ib_gid_attr *attr,
334 __always_unused void **context)
335{
095b0927 336 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 337}
338
339static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
340 unsigned int index, __always_unused void **context)
341{
095b0927 342 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 343}
344
2811ba51
AS		 345__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
346 int index)
347{
348 struct ib_gid_attr attr;
349 union ib_gid gid;
350
351 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
352 return 0;
353
354 if (!attr.ndev)
355 return 0;
356
357 dev_put(attr.ndev);
358
359 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
360 return 0;
361
362 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
363}
364
ed88451e
MD		 365int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
366 int index, enum ib_gid_type *gid_type)
367{
368 struct ib_gid_attr attr;
369 union ib_gid gid;
370 int ret;
371
372 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
373 if (ret)
374 return ret;
375
376 if (!attr.ndev)
377 return -ENODEV;
378
379 dev_put(attr.ndev);
380
381 *gid_type = attr.gid_type;
382
383 return 0;
384}
385
1b5daf11
MD		 386static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
387{
7fae6655
NO		 388 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
389 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
390 return 0;
1b5daf11
MD		 391}
392
393enum {
394 MLX5_VPORT_ACCESS_METHOD_MAD,
395 MLX5_VPORT_ACCESS_METHOD_HCA,
396 MLX5_VPORT_ACCESS_METHOD_NIC,
397};
398
399static int mlx5_get_vport_access_method(struct ib_device *ibdev)
400{
401 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
402 return MLX5_VPORT_ACCESS_METHOD_MAD;
403
ebd61f68 404 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 405 IB_LINK_LAYER_ETHERNET)
406 return MLX5_VPORT_ACCESS_METHOD_NIC;
407
408 return MLX5_VPORT_ACCESS_METHOD_HCA;
409}
410
da7525d2
EBE		 411static void get_atomic_caps(struct mlx5_ib_dev *dev,
412 struct ib_device_attr *props)
413{
414 u8 tmp;
415 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
416 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
417 u8 atomic_req_8B_endianness_mode =
bd10838a 418 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 419
420 /* Check if HW supports 8 bytes standard atomic operations and capable
421 * of host endianness respond
422 */
423 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
424 if (((atomic_operations & tmp) == tmp) &&
425 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
426 (atomic_req_8B_endianness_mode)) {
427 props->atomic_cap = IB_ATOMIC_HCA;
428 } else {
429 props->atomic_cap = IB_ATOMIC_NONE;
430 }
431}
432
1b5daf11
MD		 433static int mlx5_query_system_image_guid(struct ib_device *ibdev,
434 __be64 *sys_image_guid)
435{
436 struct mlx5_ib_dev *dev = to_mdev(ibdev);
437 struct mlx5_core_dev *mdev = dev->mdev;
438 u64 tmp;
439 int err;
440
441 switch (mlx5_get_vport_access_method(ibdev)) {
442 case MLX5_VPORT_ACCESS_METHOD_MAD:
443 return mlx5_query_mad_ifc_system_image_guid(ibdev,
444 sys_image_guid);
445
446 case MLX5_VPORT_ACCESS_METHOD_HCA:
447 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 448 break;
449
450 case MLX5_VPORT_ACCESS_METHOD_NIC:
451 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
452 break;
1b5daf11
MD		 453
454 default:
455 return -EINVAL;
456 }
3f89a643
AS		 457
458 if (!err)
459 *sys_image_guid = cpu_to_be64(tmp);
460
461 return err;
462
1b5daf11
MD		 463}
464
465static int mlx5_query_max_pkeys(struct ib_device *ibdev,
466 u16 *max_pkeys)
467{
468 struct mlx5_ib_dev *dev = to_mdev(ibdev);
469 struct mlx5_core_dev *mdev = dev->mdev;
470
471 switch (mlx5_get_vport_access_method(ibdev)) {
472 case MLX5_VPORT_ACCESS_METHOD_MAD:
473 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
474
475 case MLX5_VPORT_ACCESS_METHOD_HCA:
476 case MLX5_VPORT_ACCESS_METHOD_NIC:
477 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
478 pkey_table_size));
479 return 0;
480
481 default:
482 return -EINVAL;
483 }
484}
485
486static int mlx5_query_vendor_id(struct ib_device *ibdev,
487 u32 *vendor_id)
488{
489 struct mlx5_ib_dev *dev = to_mdev(ibdev);
490
491 switch (mlx5_get_vport_access_method(ibdev)) {
492 case MLX5_VPORT_ACCESS_METHOD_MAD:
493 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
494
495 case MLX5_VPORT_ACCESS_METHOD_HCA:
496 case MLX5_VPORT_ACCESS_METHOD_NIC:
497 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
498
499 default:
500 return -EINVAL;
501 }
502}
503
504static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
505 __be64 *node_guid)
506{
507 u64 tmp;
508 int err;
509
510 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
511 case MLX5_VPORT_ACCESS_METHOD_MAD:
512 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
513
514 case MLX5_VPORT_ACCESS_METHOD_HCA:
515 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 516 break;
517
518 case MLX5_VPORT_ACCESS_METHOD_NIC:
519 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
520 break;
1b5daf11
MD		 521
522 default:
523 return -EINVAL;
524 }
3f89a643
AS		 525
526 if (!err)
527 *node_guid = cpu_to_be64(tmp);
528
529 return err;
1b5daf11
MD		 530}
531
532struct mlx5_reg_node_desc {
bd99fdea 533 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 534};
535
536static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
537{
538 struct mlx5_reg_node_desc in;
539
540 if (mlx5_use_mad_ifc(dev))
541 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
542
543 memset(&in, 0, sizeof(in));
544
545 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
546 sizeof(struct mlx5_reg_node_desc),
547 MLX5_REG_NODE_DESC, 0, 0);
548}
549
e126ba97 550static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 551 struct ib_device_attr *props,
552 struct ib_udata *uhw)
e126ba97
EC		 553{
554 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 555 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 556 int err = -ENOMEM;
288c01b7 557 int max_sq_desc;
e126ba97
EC		 558 int max_rq_sg;
559 int max_sq_sg;
e0238a6a 560 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 561 struct mlx5_ib_query_device_resp resp = {};
562 size_t resp_len;
563 u64 max_tso;
e126ba97 564
402ca536
BW		 565 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
566 if (uhw->outlen && uhw->outlen < resp_len)
567 return -EINVAL;
568 else
569 resp.response_length = resp_len;
570
571 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 572 return -EINVAL;
573
1b5daf11
MD		 574 memset(props, 0, sizeof(*props));
575 err = mlx5_query_system_image_guid(ibdev,
576 &props->sys_image_guid);
577 if (err)
578 return err;
e126ba97 579
1b5daf11 580 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 581 if (err)
1b5daf11 582 return err;
e126ba97 583
1b5daf11
MD		 584 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
585 if (err)
586 return err;
e126ba97 587
9603b61d
JM		 588 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
589 (fw_rev_min(dev->mdev) << 16) |
590 fw_rev_sub(dev->mdev);
e126ba97
EC		 591 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
592 IB_DEVICE_PORT_ACTIVE_EVENT |
593 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 594 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 595
596 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 597 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 598 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 599 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 600 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 601 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 602 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 603 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 604 if (MLX5_CAP_GEN(mdev, imaicl)) {
605 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
606 IB_DEVICE_MEM_WINDOW_TYPE_2B;
607 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 608 /* We support 'Gappy' memory registration too */
609 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 610 }
e126ba97 611 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 612 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 613 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
614 /* At this stage no support for signature handover */
615 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
616 IB_PROT_T10DIF_TYPE_2 |
617 IB_PROT_T10DIF_TYPE_3;
618 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
619 IB_GUARD_T10DIF_CSUM;
620 }
938fe83c 621 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 622 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 623
402ca536 624 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 625 if (MLX5_CAP_ETH(mdev, csum_cap)) {
626 /* Legacy bit to support old userspace libraries */
88115fe7 627 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 628 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
629 }
630
631 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
632 props->raw_packet_caps |=
633 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 634
402ca536
BW		 635 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
636 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
637 if (max_tso) {
638 resp.tso_caps.max_tso = 1 << max_tso;
639 resp.tso_caps.supported_qpts |=
640 1 << IB_QPT_RAW_PACKET;
641 resp.response_length += sizeof(resp.tso_caps);
642 }
643 }
31f69a82
YH		 644
645 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
646 resp.rss_caps.rx_hash_function =
647 MLX5_RX_HASH_FUNC_TOEPLITZ;
648 resp.rss_caps.rx_hash_fields_mask =
649 MLX5_RX_HASH_SRC_IPV4 |
650 MLX5_RX_HASH_DST_IPV4 |
651 MLX5_RX_HASH_SRC_IPV6 |
652 MLX5_RX_HASH_DST_IPV6 |
653 MLX5_RX_HASH_SRC_PORT_TCP |
654 MLX5_RX_HASH_DST_PORT_TCP |
655 MLX5_RX_HASH_SRC_PORT_UDP |
656 MLX5_RX_HASH_DST_PORT_UDP;
657 resp.response_length += sizeof(resp.rss_caps);
658 }
659 } else {
660 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
661 resp.response_length += sizeof(resp.tso_caps);
662 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
663 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 664 }
665
f0313965
ES		 666 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
667 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
668 props->device_cap_flags |= IB_DEVICE_UD_TSO;
669 }
670
cff5a0f3 671 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 672 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
673 /* Legacy bit to support old userspace libraries */
cff5a0f3 674 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 675 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
676 }
cff5a0f3 677
da6d6ba3
MG		 678 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
679 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
680
1b5daf11
MD		 681 props->vendor_part_id = mdev->pdev->device;
682 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 683
684 props->max_mr_size = ~0ull;
e0238a6a 685 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 686 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
687 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
688 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
689 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 690 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
691 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
692 sizeof(struct mlx5_wqe_raddr_seg)) /
693 sizeof(struct mlx5_wqe_data_seg);
e126ba97 694 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 695 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 696 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 697 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 698 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
699 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
700 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
701 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
702 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
703 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
704 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 705 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 706 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 707 props->max_fast_reg_page_list_len =
708 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 709 get_atomic_caps(dev, props);
81bea28f 710 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 711 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
712 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 713 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
714 props->max_mcast_grp;
715 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 716 props->max_ah = INT_MAX;
7c60bcbb
MB		 717 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
718 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 719
8cdd312c 720#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 721 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 722 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
723 props->odp_caps = dev->odp_caps;
724#endif
725
051f2630
LR		 726 if (MLX5_CAP_GEN(mdev, cd))
727 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
728
eff901d3
EC		 729 if (!mlx5_core_is_pf(mdev))
730 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
731
31f69a82
YH		 732 if (mlx5_ib_port_link_layer(ibdev, 1) ==
733 IB_LINK_LAYER_ETHERNET) {
734 props->rss_caps.max_rwq_indirection_tables =
735 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
736 props->rss_caps.max_rwq_indirection_table_size =
737 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
738 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
739 props->max_wq_type_rq =
740 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
741 }
742
7e43a2a5
BW		 743 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
744 resp.cqe_comp_caps.max_num =
745 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
746 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
747 resp.cqe_comp_caps.supported_format =
748 MLX5_IB_CQE_RES_FORMAT_HASH |
749 MLX5_IB_CQE_RES_FORMAT_CSUM;
750 resp.response_length += sizeof(resp.cqe_comp_caps);
751 }
752
d949167d
BW		 753 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
754 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
755 MLX5_CAP_GEN(mdev, qos)) {
756 resp.packet_pacing_caps.qp_rate_limit_max =
757 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
758 resp.packet_pacing_caps.qp_rate_limit_min =
759 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
760 resp.packet_pacing_caps.supported_qpts |=
761 1 << IB_QPT_RAW_PACKET;
762 }
763 resp.response_length += sizeof(resp.packet_pacing_caps);
764 }
765
9f885201
LR		 766 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
767 uhw->outlen)) {
768 resp.mlx5_ib_support_multi_pkt_send_wqes =
769 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
770 resp.response_length +=
771 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
772 }
773
774 if (field_avail(typeof(resp), reserved, uhw->outlen))
775 resp.response_length += sizeof(resp.reserved);
776
402ca536
BW		 777 if (uhw->outlen) {
778 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
779
780 if (err)
781 return err;
782 }
783
1b5daf11 784 return 0;
e126ba97
EC		 785}
786
1b5daf11
MD		 787enum mlx5_ib_width {
788 MLX5_IB_WIDTH_1X = 1 << 0,
789 MLX5_IB_WIDTH_2X = 1 << 1,
790 MLX5_IB_WIDTH_4X = 1 << 2,
791 MLX5_IB_WIDTH_8X = 1 << 3,
792 MLX5_IB_WIDTH_12X = 1 << 4
793};
794
795static int translate_active_width(struct ib_device *ibdev, u8 active_width,
796 u8 *ib_width)
e126ba97
EC		 797{
798 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 799 int err = 0;
800
801 if (active_width & MLX5_IB_WIDTH_1X) {
802 *ib_width = IB_WIDTH_1X;
803 } else if (active_width & MLX5_IB_WIDTH_2X) {
804 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
805 (int)active_width);
806 err = -EINVAL;
807 } else if (active_width & MLX5_IB_WIDTH_4X) {
808 *ib_width = IB_WIDTH_4X;
809 } else if (active_width & MLX5_IB_WIDTH_8X) {
810 *ib_width = IB_WIDTH_8X;
811 } else if (active_width & MLX5_IB_WIDTH_12X) {
812 *ib_width = IB_WIDTH_12X;
813 } else {
814 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
815 (int)active_width);
816 err = -EINVAL;
e126ba97
EC		 817 }
818
1b5daf11
MD		 819 return err;
820}
e126ba97 821
1b5daf11
MD		 822static int mlx5_mtu_to_ib_mtu(int mtu)
823{
824 switch (mtu) {
825 case 256: return 1;
826 case 512: return 2;
827 case 1024: return 3;
828 case 2048: return 4;
829 case 4096: return 5;
830 default:
831 pr_warn("invalid mtu\n");
832 return -1;
e126ba97 833 }
1b5daf11 834}
e126ba97 835
1b5daf11
MD		 836enum ib_max_vl_num {
837 __IB_MAX_VL_0 = 1,
838 __IB_MAX_VL_0_1 = 2,
839 __IB_MAX_VL_0_3 = 3,
840 __IB_MAX_VL_0_7 = 4,
841 __IB_MAX_VL_0_14 = 5,
842};
e126ba97 843
1b5daf11
MD		 844enum mlx5_vl_hw_cap {
845 MLX5_VL_HW_0 = 1,
846 MLX5_VL_HW_0_1 = 2,
847 MLX5_VL_HW_0_2 = 3,
848 MLX5_VL_HW_0_3 = 4,
849 MLX5_VL_HW_0_4 = 5,
850 MLX5_VL_HW_0_5 = 6,
851 MLX5_VL_HW_0_6 = 7,
852 MLX5_VL_HW_0_7 = 8,
853 MLX5_VL_HW_0_14 = 15
854};
e126ba97 855
1b5daf11
MD		 856static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
857 u8 *max_vl_num)
858{
859 switch (vl_hw_cap) {
860 case MLX5_VL_HW_0:
861 *max_vl_num = __IB_MAX_VL_0;
862 break;
863 case MLX5_VL_HW_0_1:
864 *max_vl_num = __IB_MAX_VL_0_1;
865 break;
866 case MLX5_VL_HW_0_3:
867 *max_vl_num = __IB_MAX_VL_0_3;
868 break;
869 case MLX5_VL_HW_0_7:
870 *max_vl_num = __IB_MAX_VL_0_7;
871 break;
872 case MLX5_VL_HW_0_14:
873 *max_vl_num = __IB_MAX_VL_0_14;
874 break;
e126ba97 875
1b5daf11
MD		 876 default:
877 return -EINVAL;
e126ba97 878 }
e126ba97 879
1b5daf11 880 return 0;
e126ba97
EC		 881}
882
1b5daf11
MD		 883static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
884 struct ib_port_attr *props)
e126ba97 885{
1b5daf11
MD		 886 struct mlx5_ib_dev *dev = to_mdev(ibdev);
887 struct mlx5_core_dev *mdev = dev->mdev;
888 struct mlx5_hca_vport_context *rep;
046339ea
SM		 889 u16 max_mtu;
890 u16 oper_mtu;
1b5daf11
MD		 891 int err;
892 u8 ib_link_width_oper;
893 u8 vl_hw_cap;
e126ba97 894
1b5daf11
MD		 895 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
896 if (!rep) {
897 err = -ENOMEM;
e126ba97 898 goto out;
e126ba97 899 }
e126ba97 900
c4550c63 901 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 902
1b5daf11 903 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 904 if (err)
905 goto out;
906
1b5daf11
MD		 907 props->lid = rep->lid;
908 props->lmc = rep->lmc;
909 props->sm_lid = rep->sm_lid;
910 props->sm_sl = rep->sm_sl;
911 props->state = rep->vport_state;
912 props->phys_state = rep->port_physical_state;
913 props->port_cap_flags = rep->cap_mask1;
914 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
915 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
916 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
917 props->bad_pkey_cntr = rep->pkey_violation_counter;
918 props->qkey_viol_cntr = rep->qkey_violation_counter;
919 props->subnet_timeout = rep->subnet_timeout;
920 props->init_type_reply = rep->init_type_reply;
eff901d3 921 props->grh_required = rep->grh_required;
e126ba97 922
1b5daf11
MD		 923 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
924 if (err)
e126ba97 925 goto out;
e126ba97 926
1b5daf11
MD		 927 err = translate_active_width(ibdev, ib_link_width_oper,
928 &props->active_width);
929 if (err)
930 goto out;
d5beb7f2 931 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 932 if (err)
933 goto out;
934
facc9699 935 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 936
1b5daf11 937 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 938
facc9699 939 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 940
1b5daf11 941 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 942
1b5daf11
MD		 943 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
944 if (err)
945 goto out;
e126ba97 946
1b5daf11
MD		 947 err = translate_max_vl_num(ibdev, vl_hw_cap,
948 &props->max_vl_num);
e126ba97 949out:
1b5daf11 950 kfree(rep);
e126ba97
EC		 951 return err;
952}
953
1b5daf11
MD		 954int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
955 struct ib_port_attr *props)
e126ba97 956{
095b0927
IT		 957 unsigned int count;
958 int ret;
959
1b5daf11
MD		 960 switch (mlx5_get_vport_access_method(ibdev)) {
961 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 962 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
963 break;
e126ba97 964
1b5daf11 965 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 966 ret = mlx5_query_hca_port(ibdev, port, props);
967 break;
e126ba97 968
3f89a643 969 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 970 ret = mlx5_query_port_roce(ibdev, port, props);
971 break;
3f89a643 972
1b5daf11 973 default:
095b0927
IT		 974 ret = -EINVAL;
975 }
976
977 if (!ret && props) {
978 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
979 props->gid_tbl_len -= count;
1b5daf11 980 }
095b0927 981 return ret;
1b5daf11 982}
e126ba97 983
1b5daf11
MD		 984static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
985 union ib_gid *gid)
986{
987 struct mlx5_ib_dev *dev = to_mdev(ibdev);
988 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 989
1b5daf11
MD		 990 switch (mlx5_get_vport_access_method(ibdev)) {
991 case MLX5_VPORT_ACCESS_METHOD_MAD:
992 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 993
1b5daf11
MD		 994 case MLX5_VPORT_ACCESS_METHOD_HCA:
995 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
996
997 default:
998 return -EINVAL;
999 }
e126ba97 1000
e126ba97
EC		 1001}
1002
1b5daf11
MD		 1003static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1004 u16 *pkey)
1005{
1006 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1007 struct mlx5_core_dev *mdev = dev->mdev;
1008
1009 switch (mlx5_get_vport_access_method(ibdev)) {
1010 case MLX5_VPORT_ACCESS_METHOD_MAD:
1011 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1012
1013 case MLX5_VPORT_ACCESS_METHOD_HCA:
1014 case MLX5_VPORT_ACCESS_METHOD_NIC:
1015 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1016 pkey);
1017 default:
1018 return -EINVAL;
1019 }
1020}
e126ba97
EC		 1021
1022static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1023 struct ib_device_modify *props)
1024{
1025 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1026 struct mlx5_reg_node_desc in;
1027 struct mlx5_reg_node_desc out;
1028 int err;
1029
1030 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1031 return -EOPNOTSUPP;
1032
1033 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1034 return 0;
1035
1036 /*
1037 * If possible, pass node desc to FW, so it can generate
1038 * a 144 trap. If cmd fails, just ignore.
1039 */
bd99fdea 1040 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1041 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1042 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1043 if (err)
1044 return err;
1045
bd99fdea 1046 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1047
1048 return err;
1049}
1050
cdbe33d0
EC		 1051static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1052 u32 value)
1053{
1054 struct mlx5_hca_vport_context ctx = {};
1055 int err;
1056
1057 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1058 port_num, 0, &ctx);
1059 if (err)
1060 return err;
1061
1062 if (~ctx.cap_mask1_perm & mask) {
1063 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1064 mask, ctx.cap_mask1_perm);
1065 return -EINVAL;
1066 }
1067
1068 ctx.cap_mask1 = value;
1069 ctx.cap_mask1_perm = mask;
1070 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1071 port_num, 0, &ctx);
1072
1073 return err;
1074}
1075
e126ba97
EC		 1076static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1077 struct ib_port_modify *props)
1078{
1079 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1080 struct ib_port_attr attr;
1081 u32 tmp;
1082 int err;
cdbe33d0
EC		 1083 u32 change_mask;
1084 u32 value;
1085 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1086 IB_LINK_LAYER_INFINIBAND);
1087
ec255879
MD		 1088 /* CM layer calls ib_modify_port() regardless of the link layer. For
1089 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1090 */
1091 if (!is_ib)
1092 return 0;
1093
cdbe33d0
EC		 1094 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1095 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1096 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1097 return set_port_caps_atomic(dev, port, change_mask, value);
1098 }
e126ba97
EC		 1099
1100 mutex_lock(&dev->cap_mask_mutex);
1101
c4550c63 1102 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1103 if (err)
1104 goto out;
1105
1106 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1107 ~props->clr_port_cap_mask;
1108
9603b61d 1109 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1110
1111out:
1112 mutex_unlock(&dev->cap_mask_mutex);
1113 return err;
1114}
1115
30aa60b3
EC		 1116static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1117{
1118 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1119 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1120}
1121
b037c29a
EC		 1122static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1123 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1124 u32 *num_sys_pages)
1125{
1126 int uars_per_sys_page;
1127 int bfregs_per_sys_page;
1128 int ref_bfregs = req->total_num_bfregs;
1129
1130 if (req->total_num_bfregs == 0)
1131 return -EINVAL;
1132
1133 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1134 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1135
1136 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1137 return -ENOMEM;
1138
1139 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1140 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1141 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1142 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1143
1144 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1145 return -EINVAL;
1146
1147 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1148 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1149 lib_uar_4k ? "yes" : "no", ref_bfregs,
1150 req->total_num_bfregs, *num_sys_pages);
1151
1152 return 0;
1153}
1154
1155static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1156{
1157 struct mlx5_bfreg_info *bfregi;
1158 int err;
1159 int i;
1160
1161 bfregi = &context->bfregi;
1162 for (i = 0; i < bfregi->num_sys_pages; i++) {
1163 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1164 if (err)
1165 goto error;
1166
1167 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1168 }
1169 return 0;
1170
1171error:
1172 for (--i; i >= 0; i--)
1173 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1174 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1175
1176 return err;
1177}
1178
1179static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1180{
1181 struct mlx5_bfreg_info *bfregi;
1182 int err;
1183 int i;
1184
1185 bfregi = &context->bfregi;
1186 for (i = 0; i < bfregi->num_sys_pages; i++) {
1187 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1188 if (err) {
1189 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1190 return err;
1191 }
1192 }
1193 return 0;
1194}
1195
e126ba97
EC		 1196static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1197 struct ib_udata *udata)
1198{
1199 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1200 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1201 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1202 struct mlx5_ib_ucontext *context;
2f5ff264 1203 struct mlx5_bfreg_info *bfregi;
78c0f98c 1204 int ver;
e126ba97 1205 int err;
f241e749 1206 size_t reqlen;
a168a41c
MD		 1207 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1208 max_cqe_version);
b037c29a 1209 bool lib_uar_4k;
e126ba97
EC		 1210
1211 if (!dev->ib_active)
1212 return ERR_PTR(-EAGAIN);
1213
dfbee859
HA		 1214 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1215 return ERR_PTR(-EINVAL);
1216
78c0f98c
EC		 1217 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1218 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1219 ver = 0;
a168a41c 1220 else if (reqlen >= min_req_v2)
78c0f98c
EC		 1221 ver = 2;
1222 else
1223 return ERR_PTR(-EINVAL);
1224
b368d7cb 1225 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 1226 if (err)
1227 return ERR_PTR(err);
1228
b368d7cb 1229 if (req.flags)
78c0f98c
EC		 1230 return ERR_PTR(-EINVAL);
1231
f72300c5 1232 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1233 return ERR_PTR(-EOPNOTSUPP);
1234
2f5ff264
EC		 1235 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1236 MLX5_NON_FP_BFREGS_PER_UAR);
1237 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1238 return ERR_PTR(-EINVAL);
1239
938fe83c 1240 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1241 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1242 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1243 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1244 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1245 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1246 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1247 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1248 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1249 resp.cqe_version = min_t(__u8,
1250 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1251 req.max_cqe_version);
30aa60b3
EC		 1252 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1253 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1254 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1255 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1256 resp.response_length = min(offsetof(typeof(resp), response_length) +
1257 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1258
1259 context = kzalloc(sizeof(*context), GFP_KERNEL);
1260 if (!context)
1261 return ERR_PTR(-ENOMEM);
1262
30aa60b3 1263 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1264 bfregi = &context->bfregi;
b037c29a
EC		 1265
1266 /* updates req->total_num_bfregs */
1267 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1268 if (err)
e126ba97 1269 goto out_ctx;
e126ba97 1270
b037c29a
EC		 1271 mutex_init(&bfregi->lock);
1272 bfregi->lib_uar_4k = lib_uar_4k;
1273 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1274 GFP_KERNEL);
b037c29a 1275 if (!bfregi->count) {
e126ba97 1276 err = -ENOMEM;
b037c29a 1277 goto out_ctx;
e126ba97
EC		 1278 }
1279
b037c29a
EC		 1280 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1281 sizeof(*bfregi->sys_pages),
1282 GFP_KERNEL);
1283 if (!bfregi->sys_pages) {
e126ba97 1284 err = -ENOMEM;
b037c29a 1285 goto out_count;
e126ba97
EC		 1286 }
1287
b037c29a
EC		 1288 err = allocate_uars(dev, context);
1289 if (err)
1290 goto out_sys_pages;
e126ba97 1291
b4cfe447
HE		 1292#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1293 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1294#endif
1295
7d0cc6ed
AK		 1296 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1297 if (!context->upd_xlt_page) {
1298 err = -ENOMEM;
1299 goto out_uars;
1300 }
1301 mutex_init(&context->upd_xlt_page_mutex);
1302
146d2f1a 1303 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1304 err = mlx5_core_alloc_transport_domain(dev->mdev,
1305 &context->tdn);
1306 if (err)
7d0cc6ed 1307 goto out_page;
146d2f1a 1308 }
1309
7c2344c3 1310 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1311 INIT_LIST_HEAD(&context->db_page_list);
1312 mutex_init(&context->db_page_mutex);
1313
2f5ff264 1314 resp.tot_bfregs = req.total_num_bfregs;
938fe83c 1315 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1316
f72300c5
HA		 1317 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1318 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1319
402ca536 1320 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1321 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1322 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1323 resp.response_length += sizeof(resp.cmds_supp_uhw);
1324 }
1325
78984898
OG		 1326 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1327 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1328 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1329 resp.eth_min_inline++;
1330 }
1331 resp.response_length += sizeof(resp.eth_min_inline);
1332 }
1333
bc5c6eed
NO		 1334 /*
1335 * We don't want to expose information from the PCI bar that is located
1336 * after 4096 bytes, so if the arch only supports larger pages, let's
1337 * pretend we don't support reading the HCA's core clock. This is also
1338 * forced by mmap function.
1339 */
de8d6e02
EC		 1340 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1341 if (PAGE_SIZE <= 4096) {
1342 resp.comp_mask |=
1343 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1344 resp.hca_core_clock_offset =
1345 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1346 }
f72300c5 1347 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1348 sizeof(resp.reserved2);
b368d7cb
MB		 1349 }
1350
30aa60b3
EC		 1351 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1352 resp.response_length += sizeof(resp.log_uar_size);
1353
1354 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1355 resp.response_length += sizeof(resp.num_uars_per_page);
1356
b368d7cb 1357 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1358 if (err)
146d2f1a 1359 goto out_td;
e126ba97 1360
2f5ff264
EC		 1361 bfregi->ver = ver;
1362 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1363 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1364 context->lib_caps = req.lib_caps;
1365 print_lib_caps(dev, context->lib_caps);
f72300c5 1366
e126ba97
EC		 1367 return &context->ibucontext;
1368
146d2f1a 1369out_td:
1370 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1371 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1372
7d0cc6ed
AK		 1373out_page:
1374 free_page(context->upd_xlt_page);
1375
e126ba97 1376out_uars:
b037c29a 1377 deallocate_uars(dev, context);
e126ba97 1378
b037c29a
EC		 1379out_sys_pages:
1380 kfree(bfregi->sys_pages);
e126ba97 1381
b037c29a
EC		 1382out_count:
1383 kfree(bfregi->count);
e126ba97
EC		 1384
1385out_ctx:
1386 kfree(context);
b037c29a 1387
e126ba97
EC		 1388 return ERR_PTR(err);
1389}
1390
1391static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1392{
1393 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1394 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1395 struct mlx5_bfreg_info *bfregi;
e126ba97 1396
b037c29a 1397 bfregi = &context->bfregi;
146d2f1a 1398 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1399 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1400
7d0cc6ed 1401 free_page(context->upd_xlt_page);
b037c29a
EC		 1402 deallocate_uars(dev, context);
1403 kfree(bfregi->sys_pages);
2f5ff264 1404 kfree(bfregi->count);
e126ba97
EC		 1405 kfree(context);
1406
1407 return 0;
1408}
1409
b037c29a
EC		 1410static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1411 struct mlx5_bfreg_info *bfregi,
1412 int idx)
e126ba97 1413{
b037c29a
EC		 1414 int fw_uars_per_page;
1415
1416 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1417
1418 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1419 bfregi->sys_pages[idx] / fw_uars_per_page;
e126ba97
EC		 1420}
1421
1422static int get_command(unsigned long offset)
1423{
1424 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1425}
1426
1427static int get_arg(unsigned long offset)
1428{
1429 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1430}
1431
1432static int get_index(unsigned long offset)
1433{
1434 return get_arg(offset);
1435}
1436
7c2344c3
MG		 1437static void mlx5_ib_vma_open(struct vm_area_struct *area)
1438{
1439 /* vma_open is called when a new VMA is created on top of our VMA. This
1440 * is done through either mremap flow or split_vma (usually due to
1441 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1442 * as this VMA is strongly hardware related. Therefore we set the
1443 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1444 * calling us again and trying to do incorrect actions. We assume that
1445 * the original VMA size is exactly a single page, and therefore all
1446 * "splitting" operation will not happen to it.
1447 */
1448 area->vm_ops = NULL;
1449}
1450
1451static void mlx5_ib_vma_close(struct vm_area_struct *area)
1452{
1453 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1454
1455 /* It's guaranteed that all VMAs opened on a FD are closed before the
1456 * file itself is closed, therefore no sync is needed with the regular
1457 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1458 * However need a sync with accessing the vma as part of
1459 * mlx5_ib_disassociate_ucontext.
1460 * The close operation is usually called under mm->mmap_sem except when
1461 * process is exiting.
1462 * The exiting case is handled explicitly as part of
1463 * mlx5_ib_disassociate_ucontext.
1464 */
1465 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1466
1467 /* setting the vma context pointer to null in the mlx5_ib driver's
1468 * private data, to protect a race condition in
1469 * mlx5_ib_disassociate_ucontext().
1470 */
1471 mlx5_ib_vma_priv_data->vma = NULL;
1472 list_del(&mlx5_ib_vma_priv_data->list);
1473 kfree(mlx5_ib_vma_priv_data);
1474}
1475
1476static const struct vm_operations_struct mlx5_ib_vm_ops = {
1477 .open = mlx5_ib_vma_open,
1478 .close = mlx5_ib_vma_close
1479};
1480
1481static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1482 struct mlx5_ib_ucontext *ctx)
1483{
1484 struct mlx5_ib_vma_private_data *vma_prv;
1485 struct list_head *vma_head = &ctx->vma_private_list;
1486
1487 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1488 if (!vma_prv)
1489 return -ENOMEM;
1490
1491 vma_prv->vma = vma;
1492 vma->vm_private_data = vma_prv;
1493 vma->vm_ops = &mlx5_ib_vm_ops;
1494
1495 list_add(&vma_prv->list, vma_head);
1496
1497 return 0;
1498}
1499
1500static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1501{
1502 int ret;
1503 struct vm_area_struct *vma;
1504 struct mlx5_ib_vma_private_data *vma_private, *n;
1505 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1506 struct task_struct *owning_process = NULL;
1507 struct mm_struct *owning_mm = NULL;
1508
1509 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1510 if (!owning_process)
1511 return;
1512
1513 owning_mm = get_task_mm(owning_process);
1514 if (!owning_mm) {
1515 pr_info("no mm, disassociate ucontext is pending task termination\n");
1516 while (1) {
1517 put_task_struct(owning_process);
1518 usleep_range(1000, 2000);
1519 owning_process = get_pid_task(ibcontext->tgid,
1520 PIDTYPE_PID);
1521 if (!owning_process ||
1522 owning_process->state == TASK_DEAD) {
1523 pr_info("disassociate ucontext done, task was terminated\n");
1524 /* in case task was dead need to release the
1525 * task struct.
1526 */
1527 if (owning_process)
1528 put_task_struct(owning_process);
1529 return;
1530 }
1531 }
1532 }
1533
1534 /* need to protect from a race on closing the vma as part of
1535 * mlx5_ib_vma_close.
1536 */
ecc7d83b 1537 down_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1538 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1539 list) {
1540 vma = vma_private->vma;
1541 ret = zap_vma_ptes(vma, vma->vm_start,
1542 PAGE_SIZE);
1543 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1544 /* context going to be destroyed, should
1545 * not access ops any more.
1546 */
13776612 1547 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1548 vma->vm_ops = NULL;
1549 list_del(&vma_private->list);
1550 kfree(vma_private);
1551 }
ecc7d83b 1552 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1553 mmput(owning_mm);
1554 put_task_struct(owning_process);
1555}
1556
37aa5c36
GL		 1557static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1558{
1559 switch (cmd) {
1560 case MLX5_IB_MMAP_WC_PAGE:
1561 return "WC";
1562 case MLX5_IB_MMAP_REGULAR_PAGE:
1563 return "best effort WC";
1564 case MLX5_IB_MMAP_NC_PAGE:
1565 return "NC";
1566 default:
1567 return NULL;
1568 }
1569}
1570
1571static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1572 struct vm_area_struct *vma,
1573 struct mlx5_ib_ucontext *context)
37aa5c36 1574{
2f5ff264 1575 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1576 int err;
1577 unsigned long idx;
1578 phys_addr_t pfn, pa;
1579 pgprot_t prot;
b037c29a
EC		 1580 int uars_per_page;
1581
1582 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1583 return -EINVAL;
1584
1585 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1586 idx = get_index(vma->vm_pgoff);
1587 if (idx % uars_per_page ||
1588 idx * uars_per_page >= bfregi->num_sys_pages) {
1589 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1590 return -EINVAL;
1591 }
37aa5c36
GL		 1592
1593 switch (cmd) {
1594 case MLX5_IB_MMAP_WC_PAGE:
1595/* Some architectures don't support WC memory */
1596#if defined(CONFIG_X86)
1597 if (!pat_enabled())
1598 return -EPERM;
1599#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1600 return -EPERM;
1601#endif
1602 /* fall through */
1603 case MLX5_IB_MMAP_REGULAR_PAGE:
1604 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1605 prot = pgprot_writecombine(vma->vm_page_prot);
1606 break;
1607 case MLX5_IB_MMAP_NC_PAGE:
1608 prot = pgprot_noncached(vma->vm_page_prot);
1609 break;
1610 default:
1611 return -EINVAL;
1612 }
1613
b037c29a 1614 pfn = uar_index2pfn(dev, bfregi, idx);
37aa5c36
GL		 1615 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1616
1617 vma->vm_page_prot = prot;
1618 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1619 PAGE_SIZE, vma->vm_page_prot);
1620 if (err) {
1621 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1622 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1623 return -EAGAIN;
1624 }
1625
1626 pa = pfn << PAGE_SHIFT;
1627 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1628 vma->vm_start, &pa);
1629
7c2344c3 1630 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1631}
1632
e126ba97
EC		 1633static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1634{
1635 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1636 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1637 unsigned long command;
e126ba97
EC		 1638 phys_addr_t pfn;
1639
1640 command = get_command(vma->vm_pgoff);
1641 switch (command) {
37aa5c36
GL		 1642 case MLX5_IB_MMAP_WC_PAGE:
1643 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1644 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1645 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1646
1647 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1648 return -ENOSYS;
1649
d69e3bcf 1650 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1651 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1652 return -EINVAL;
1653
6cbac1e4 1654 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1655 return -EPERM;
1656
1657 /* Don't expose to user-space information it shouldn't have */
1658 if (PAGE_SIZE > 4096)
1659 return -EOPNOTSUPP;
1660
1661 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1662 pfn = (dev->mdev->iseg_base +
1663 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1664 PAGE_SHIFT;
1665 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1666 PAGE_SIZE, vma->vm_page_prot))
1667 return -EAGAIN;
1668
1669 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1670 vma->vm_start,
1671 (unsigned long long)pfn << PAGE_SHIFT);
1672 break;
d69e3bcf 1673
e126ba97
EC		 1674 default:
1675 return -EINVAL;
1676 }
1677
1678 return 0;
1679}
1680
e126ba97
EC		 1681static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1682 struct ib_ucontext *context,
1683 struct ib_udata *udata)
1684{
1685 struct mlx5_ib_alloc_pd_resp resp;
1686 struct mlx5_ib_pd *pd;
1687 int err;
1688
1689 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1690 if (!pd)
1691 return ERR_PTR(-ENOMEM);
1692
9603b61d 1693 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1694 if (err) {
1695 kfree(pd);
1696 return ERR_PTR(err);
1697 }
1698
1699 if (context) {
1700 resp.pdn = pd->pdn;
1701 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1702 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1703 kfree(pd);
1704 return ERR_PTR(-EFAULT);
1705 }
e126ba97
EC		 1706 }
1707
1708 return &pd->ibpd;
1709}
1710
1711static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1712{
1713 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1714 struct mlx5_ib_pd *mpd = to_mpd(pd);
1715
9603b61d 1716 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1717 kfree(mpd);
1718
1719 return 0;
1720}
1721
466fa6d2
MG		 1722enum {
1723 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1724 MATCH_CRITERIA_ENABLE_MISC_BIT,
1725 MATCH_CRITERIA_ENABLE_INNER_BIT
1726};
1727
1728#define HEADER_IS_ZERO(match_criteria, headers) \
1729 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1730 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1731
466fa6d2 1732static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1733{
466fa6d2 1734 u8 match_criteria_enable;
038d2ef8 1735
466fa6d2
MG		 1736 match_criteria_enable =
1737 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1738 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1739 match_criteria_enable |=
1740 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1741 MATCH_CRITERIA_ENABLE_MISC_BIT;
1742 match_criteria_enable |=
1743 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1744 MATCH_CRITERIA_ENABLE_INNER_BIT;
1745
1746 return match_criteria_enable;
038d2ef8
MG		 1747}
1748
ca0d4753
MG		 1749static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1750{
1751 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1752 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1753}
1754
2d1e697e
MR		 1755static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1756 bool inner)
1757{
1758 if (inner) {
1759 MLX5_SET(fte_match_set_misc,
1760 misc_c, inner_ipv6_flow_label, mask);
1761 MLX5_SET(fte_match_set_misc,
1762 misc_v, inner_ipv6_flow_label, val);
1763 } else {
1764 MLX5_SET(fte_match_set_misc,
1765 misc_c, outer_ipv6_flow_label, mask);
1766 MLX5_SET(fte_match_set_misc,
1767 misc_v, outer_ipv6_flow_label, val);
1768 }
1769}
1770
ca0d4753
MG		 1771static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1772{
1773 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1774 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1775 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1776 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1777}
1778
c47ac6ae
MG		 1779#define LAST_ETH_FIELD vlan_tag
1780#define LAST_IB_FIELD sl
ca0d4753 1781#define LAST_IPV4_FIELD tos
466fa6d2 1782#define LAST_IPV6_FIELD traffic_class
c47ac6ae 1783#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 1784#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 1785#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 1786#define LAST_DROP_FIELD size
c47ac6ae
MG		 1787
1788/* Field is the last supported field */
1789#define FIELDS_NOT_SUPPORTED(filter, field)\
1790 memchr_inv((void *)&filter.field +\
1791 sizeof(filter.field), 0,\
1792 sizeof(filter) -\
1793 offsetof(typeof(filter), field) -\
1794 sizeof(filter.field))
1795
19cc7524
AL		 1796#define IPV4_VERSION 4
1797#define IPV6_VERSION 6
1798static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1799 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 1800 u32 *tag_id, bool *is_drop)
038d2ef8 1801{
466fa6d2
MG		 1802 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1803 misc_parameters);
1804 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1805 misc_parameters);
2d1e697e
MR		 1806 void *headers_c;
1807 void *headers_v;
19cc7524 1808 int match_ipv;
2d1e697e
MR		 1809
1810 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1811 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1812 inner_headers);
1813 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1814 inner_headers);
19cc7524
AL		 1815 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1816 ft_field_support.inner_ip_version);
2d1e697e
MR		 1817 } else {
1818 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1819 outer_headers);
1820 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1821 outer_headers);
19cc7524
AL		 1822 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1823 ft_field_support.outer_ip_version);
2d1e697e 1824 }
466fa6d2 1825
2d1e697e 1826 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 1827 case IB_FLOW_SPEC_ETH:
c47ac6ae 1828 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 1829 return -EOPNOTSUPP;
038d2ef8 1830
2d1e697e 1831 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1832 dmac_47_16),
1833 ib_spec->eth.mask.dst_mac);
2d1e697e 1834 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1835 dmac_47_16),
1836 ib_spec->eth.val.dst_mac);
1837
2d1e697e 1838 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 1839 smac_47_16),
1840 ib_spec->eth.mask.src_mac);
2d1e697e 1841 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 1842 smac_47_16),
1843 ib_spec->eth.val.src_mac);
1844
038d2ef8 1845 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 1846 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 1847 cvlan_tag, 1);
2d1e697e 1848 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 1849 cvlan_tag, 1);
038d2ef8 1850
2d1e697e 1851 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1852 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 1853 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1854 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1855
2d1e697e 1856 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1857 first_cfi,
1858 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 1859 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1860 first_cfi,
1861 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1862
2d1e697e 1863 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1864 first_prio,
1865 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 1866 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1867 first_prio,
1868 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1869 }
2d1e697e 1870 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 1871 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 1872 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1873 ethertype, ntohs(ib_spec->eth.val.ether_type));
1874 break;
1875 case IB_FLOW_SPEC_IPV4:
c47ac6ae 1876 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 1877 return -EOPNOTSUPP;
038d2ef8 1878
19cc7524
AL		 1879 if (match_ipv) {
1880 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1881 ip_version, 0xf);
1882 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1883 ip_version, IPV4_VERSION);
1884 } else {
1885 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1886 ethertype, 0xffff);
1887 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1888 ethertype, ETH_P_IP);
1889 }
038d2ef8 1890
2d1e697e 1891 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1892 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1893 &ib_spec->ipv4.mask.src_ip,
1894 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 1895 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1896 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1897 &ib_spec->ipv4.val.src_ip,
1898 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 1899 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 1900 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1901 &ib_spec->ipv4.mask.dst_ip,
1902 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 1903 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 1904 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1905 &ib_spec->ipv4.val.dst_ip,
1906 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 1907
2d1e697e 1908 set_tos(headers_c, headers_v,
ca0d4753
MG		 1909 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1910
2d1e697e 1911 set_proto(headers_c, headers_v,
ca0d4753 1912 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 1913 break;
026bae0c 1914 case IB_FLOW_SPEC_IPV6:
c47ac6ae 1915 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 1916 return -EOPNOTSUPP;
026bae0c 1917
19cc7524
AL		 1918 if (match_ipv) {
1919 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1920 ip_version, 0xf);
1921 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1922 ip_version, IPV6_VERSION);
1923 } else {
1924 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1925 ethertype, 0xffff);
1926 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1927 ethertype, ETH_P_IPV6);
1928 }
026bae0c 1929
2d1e697e 1930 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1931 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1932 &ib_spec->ipv6.mask.src_ip,
1933 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 1934 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1935 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1936 &ib_spec->ipv6.val.src_ip,
1937 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 1938 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 1939 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1940 &ib_spec->ipv6.mask.dst_ip,
1941 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 1942 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 1943 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1944 &ib_spec->ipv6.val.dst_ip,
1945 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 1946
2d1e697e 1947 set_tos(headers_c, headers_v,
466fa6d2
MG		 1948 ib_spec->ipv6.mask.traffic_class,
1949 ib_spec->ipv6.val.traffic_class);
1950
2d1e697e 1951 set_proto(headers_c, headers_v,
466fa6d2
MG		 1952 ib_spec->ipv6.mask.next_hdr,
1953 ib_spec->ipv6.val.next_hdr);
1954
2d1e697e
MR		 1955 set_flow_label(misc_params_c, misc_params_v,
1956 ntohl(ib_spec->ipv6.mask.flow_label),
1957 ntohl(ib_spec->ipv6.val.flow_label),
1958 ib_spec->type & IB_FLOW_SPEC_INNER);
1959
026bae0c 1960 break;
038d2ef8 1961 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 1962 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1963 LAST_TCP_UDP_FIELD))
1ffd3a26 1964 return -EOPNOTSUPP;
038d2ef8 1965
2d1e697e 1966 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1967 0xff);
2d1e697e 1968 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1969 IPPROTO_TCP);
1970
2d1e697e 1971 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 1972 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1973 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 1974 ntohs(ib_spec->tcp_udp.val.src_port));
1975
2d1e697e 1976 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 1977 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1978 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 1979 ntohs(ib_spec->tcp_udp.val.dst_port));
1980 break;
1981 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 1982 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1983 LAST_TCP_UDP_FIELD))
1ffd3a26 1984 return -EOPNOTSUPP;
038d2ef8 1985
2d1e697e 1986 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 1987 0xff);
2d1e697e 1988 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 1989 IPPROTO_UDP);
1990
2d1e697e 1991 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 1992 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 1993 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 1994 ntohs(ib_spec->tcp_udp.val.src_port));
1995
2d1e697e 1996 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 1997 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 1998 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 1999 ntohs(ib_spec->tcp_udp.val.dst_port));
2000 break;
ffb30d8f
MR		 2001 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2002 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2003 LAST_TUNNEL_FIELD))
1ffd3a26 2004 return -EOPNOTSUPP;
ffb30d8f
MR		 2005
2006 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2007 ntohl(ib_spec->tunnel.mask.tunnel_id));
2008 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2009 ntohl(ib_spec->tunnel.val.tunnel_id));
2010 break;
2ac693f9
MR		 2011 case IB_FLOW_SPEC_ACTION_TAG:
2012 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2013 LAST_FLOW_TAG_FIELD))
2014 return -EOPNOTSUPP;
2015 if (ib_spec->flow_tag.tag_id >= BIT(24))
2016 return -EINVAL;
2017
2018 *tag_id = ib_spec->flow_tag.tag_id;
2019 break;
a22ed86c
SS		 2020 case IB_FLOW_SPEC_ACTION_DROP:
2021 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2022 LAST_DROP_FIELD))
2023 return -EOPNOTSUPP;
2024 *is_drop = true;
2025 break;
038d2ef8
MG		 2026 default:
2027 return -EINVAL;
2028 }
2029
2030 return 0;
2031}
2032
2033/* If a flow could catch both multicast and unicast packets,
2034 * it won't fall into the multicast flow steering table and this rule
2035 * could steal other multicast packets.
2036 */
2037static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2038{
2039 struct ib_flow_spec_eth *eth_spec;
2040
2041 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2042 ib_attr->size < sizeof(struct ib_flow_attr) +
2043 sizeof(struct ib_flow_spec_eth) ||
2044 ib_attr->num_of_specs < 1)
2045 return false;
2046
2047 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2048 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2049 eth_spec->size != sizeof(*eth_spec))
2050 return false;
2051
2052 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2053 is_multicast_ether_addr(eth_spec->val.dst_mac);
2054}
2055
19cc7524
AL		 2056static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2057 const struct ib_flow_attr *flow_attr,
0f750966 2058 bool check_inner)
038d2ef8
MG		 2059{
2060 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2061 int match_ipv = check_inner ?
2062 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2063 ft_field_support.inner_ip_version) :
2064 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2065 ft_field_support.outer_ip_version);
0f750966
AL		 2066 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2067 bool ipv4_spec_valid, ipv6_spec_valid;
2068 unsigned int ip_spec_type = 0;
2069 bool has_ethertype = false;
038d2ef8 2070 unsigned int spec_index;
0f750966
AL		 2071 bool mask_valid = true;
2072 u16 eth_type = 0;
2073 bool type_valid;
038d2ef8
MG		 2074
2075 /* Validate that ethertype is correct */
2076 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2077 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2078 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2079 mask_valid = (ib_spec->eth.mask.ether_type ==
2080 htons(0xffff));
2081 has_ethertype = true;
2082 eth_type = ntohs(ib_spec->eth.val.ether_type);
2083 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2084 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2085 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2086 }
2087 ib_spec = (void *)ib_spec + ib_spec->size;
2088 }
0f750966
AL		 2089
2090 type_valid = (!has_ethertype) || (!ip_spec_type);
2091 if (!type_valid && mask_valid) {
2092 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2093 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2094 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2095 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2096
2097 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2098 (((eth_type == ETH_P_MPLS_UC) ||
2099 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2100 }
2101
2102 return type_valid;
2103}
2104
19cc7524
AL		 2105static bool is_valid_attr(struct mlx5_core_dev *mdev,
2106 const struct ib_flow_attr *flow_attr)
0f750966 2107{
19cc7524
AL		 2108 return is_valid_ethertype(mdev, flow_attr, false) &&
2109 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2110}
2111
2112static void put_flow_table(struct mlx5_ib_dev *dev,
2113 struct mlx5_ib_flow_prio *prio, bool ft_added)
2114{
2115 prio->refcount -= !!ft_added;
2116 if (!prio->refcount) {
2117 mlx5_destroy_flow_table(prio->flow_table);
2118 prio->flow_table = NULL;
2119 }
2120}
2121
2122static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2123{
2124 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2125 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2126 struct mlx5_ib_flow_handler,
2127 ibflow);
2128 struct mlx5_ib_flow_handler *iter, *tmp;
2129
2130 mutex_lock(&dev->flow_db.lock);
2131
2132 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2133 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2134 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2135 list_del(&iter->list);
2136 kfree(iter);
2137 }
2138
74491de9 2139 mlx5_del_flow_rules(handler->rule);
5497adc6 2140 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2141 mutex_unlock(&dev->flow_db.lock);
2142
2143 kfree(handler);
2144
2145 return 0;
2146}
2147
35d19011
MG		 2148static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2149{
2150 priority *= 2;
2151 if (!dont_trap)
2152 priority++;
2153 return priority;
2154}
2155
cc0e5d42
MG		 2156enum flow_table_type {
2157 MLX5_IB_FT_RX,
2158 MLX5_IB_FT_TX
2159};
2160
00b7c2ab
MG		 2161#define MLX5_FS_MAX_TYPES 6
2162#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2163static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2164 struct ib_flow_attr *flow_attr,
2165 enum flow_table_type ft_type)
038d2ef8 2166{
35d19011 2167 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2168 struct mlx5_flow_namespace *ns = NULL;
2169 struct mlx5_ib_flow_prio *prio;
2170 struct mlx5_flow_table *ft;
dac388ef 2171 int max_table_size;
038d2ef8
MG		 2172 int num_entries;
2173 int num_groups;
2174 int priority;
2175 int err = 0;
2176
dac388ef
MG		 2177 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2178 log_max_ft_size));
038d2ef8 2179 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2180 if (flow_is_multicast_only(flow_attr) &&
2181 !dont_trap)
038d2ef8
MG		 2182 priority = MLX5_IB_FLOW_MCAST_PRIO;
2183 else
35d19011
MG		 2184 priority = ib_prio_to_core_prio(flow_attr->priority,
2185 dont_trap);
038d2ef8
MG		 2186 ns = mlx5_get_flow_namespace(dev->mdev,
2187 MLX5_FLOW_NAMESPACE_BYPASS);
2188 num_entries = MLX5_FS_MAX_ENTRIES;
2189 num_groups = MLX5_FS_MAX_TYPES;
2190 prio = &dev->flow_db.prios[priority];
2191 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2192 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2193 ns = mlx5_get_flow_namespace(dev->mdev,
2194 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2195 build_leftovers_ft_param(&priority,
2196 &num_entries,
2197 &num_groups);
2198 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2199 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2200 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2201 allow_sniffer_and_nic_rx_shared_tir))
2202 return ERR_PTR(-ENOTSUPP);
2203
2204 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2205 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2206 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2207
2208 prio = &dev->flow_db.sniffer[ft_type];
2209 priority = 0;
2210 num_entries = 1;
2211 num_groups = 1;
038d2ef8
MG		 2212 }
2213
2214 if (!ns)
2215 return ERR_PTR(-ENOTSUPP);
2216
dac388ef
MG		 2217 if (num_entries > max_table_size)
2218 return ERR_PTR(-ENOMEM);
2219
038d2ef8
MG		 2220 ft = prio->flow_table;
2221 if (!ft) {
2222 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2223 num_entries,
d63cd286 2224 num_groups,
c9f1b073 2225 0, 0);
038d2ef8
MG		 2226
2227 if (!IS_ERR(ft)) {
2228 prio->refcount = 0;
2229 prio->flow_table = ft;
2230 } else {
2231 err = PTR_ERR(ft);
2232 }
2233 }
2234
2235 return err ? ERR_PTR(err) : prio;
2236}
2237
2238static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2239 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 2240 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 2241 struct mlx5_flow_destination *dst)
2242{
2243 struct mlx5_flow_table *ft = ft_prio->flow_table;
2244 struct mlx5_ib_flow_handler *handler;
66958ed9 2245 struct mlx5_flow_act flow_act = {0};
c5bb1730 2246 struct mlx5_flow_spec *spec;
a22ed86c 2247 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2248 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2249 unsigned int spec_index;
2ac693f9 2250 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2251 bool is_drop = false;
038d2ef8 2252 int err = 0;
a22ed86c 2253 int dest_num = 1;
038d2ef8 2254
19cc7524 2255 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2256 return ERR_PTR(-EINVAL);
2257
1b9a07ee 2258 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2259 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2260 if (!handler || !spec) {
038d2ef8
MG		 2261 err = -ENOMEM;
2262 goto free;
2263 }
2264
2265 INIT_LIST_HEAD(&handler->list);
2266
2267 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2268 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2269 spec->match_value,
2270 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2271 if (err < 0)
2272 goto free;
2273
2274 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2275 }
2276
466fa6d2 2277 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2278 if (is_drop) {
2279 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2280 rule_dst = NULL;
2281 dest_num = 0;
2282 } else {
2283 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2284 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2285 }
2ac693f9
MR		 2286
2287 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2288 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2289 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2290 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2291 flow_tag, flow_attr->type);
2292 err = -EINVAL;
2293 goto free;
2294 }
2295 flow_act.flow_tag = flow_tag;
74491de9 2296 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2297 &flow_act,
a22ed86c 2298 rule_dst, dest_num);
038d2ef8
MG		 2299
2300 if (IS_ERR(handler->rule)) {
2301 err = PTR_ERR(handler->rule);
2302 goto free;
2303 }
2304
d9d4980a 2305 ft_prio->refcount++;
5497adc6 2306 handler->prio = ft_prio;
038d2ef8
MG		 2307
2308 ft_prio->flow_table = ft;
2309free:
2310 if (err)
2311 kfree(handler);
c5bb1730 2312 kvfree(spec);
038d2ef8
MG		 2313 return err ? ERR_PTR(err) : handler;
2314}
2315
35d19011
MG		 2316static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2317 struct mlx5_ib_flow_prio *ft_prio,
2318 struct ib_flow_attr *flow_attr,
2319 struct mlx5_flow_destination *dst)
2320{
2321 struct mlx5_ib_flow_handler *handler_dst = NULL;
2322 struct mlx5_ib_flow_handler *handler = NULL;
2323
2324 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2325 if (!IS_ERR(handler)) {
2326 handler_dst = create_flow_rule(dev, ft_prio,
2327 flow_attr, dst);
2328 if (IS_ERR(handler_dst)) {
74491de9 2329 mlx5_del_flow_rules(handler->rule);
d9d4980a 2330 ft_prio->refcount--;
35d19011
MG		 2331 kfree(handler);
2332 handler = handler_dst;
2333 } else {
2334 list_add(&handler_dst->list, &handler->list);
2335 }
2336 }
2337
2338 return handler;
2339}
038d2ef8
MG		 2340enum {
2341 LEFTOVERS_MC,
2342 LEFTOVERS_UC,
2343};
2344
2345static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2346 struct mlx5_ib_flow_prio *ft_prio,
2347 struct ib_flow_attr *flow_attr,
2348 struct mlx5_flow_destination *dst)
2349{
2350 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2351 struct mlx5_ib_flow_handler *handler = NULL;
2352
2353 static struct {
2354 struct ib_flow_attr flow_attr;
2355 struct ib_flow_spec_eth eth_flow;
2356 } leftovers_specs[] = {
2357 [LEFTOVERS_MC] = {
2358 .flow_attr = {
2359 .num_of_specs = 1,
2360 .size = sizeof(leftovers_specs[0])
2361 },
2362 .eth_flow = {
2363 .type = IB_FLOW_SPEC_ETH,
2364 .size = sizeof(struct ib_flow_spec_eth),
2365 .mask = {.dst_mac = {0x1} },
2366 .val = {.dst_mac = {0x1} }
2367 }
2368 },
2369 [LEFTOVERS_UC] = {
2370 .flow_attr = {
2371 .num_of_specs = 1,
2372 .size = sizeof(leftovers_specs[0])
2373 },
2374 .eth_flow = {
2375 .type = IB_FLOW_SPEC_ETH,
2376 .size = sizeof(struct ib_flow_spec_eth),
2377 .mask = {.dst_mac = {0x1} },
2378 .val = {.dst_mac = {} }
2379 }
2380 }
2381 };
2382
2383 handler = create_flow_rule(dev, ft_prio,
2384 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2385 dst);
2386 if (!IS_ERR(handler) &&
2387 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2388 handler_ucast = create_flow_rule(dev, ft_prio,
2389 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2390 dst);
2391 if (IS_ERR(handler_ucast)) {
74491de9 2392 mlx5_del_flow_rules(handler->rule);
d9d4980a 2393 ft_prio->refcount--;
038d2ef8
MG		 2394 kfree(handler);
2395 handler = handler_ucast;
2396 } else {
2397 list_add(&handler_ucast->list, &handler->list);
2398 }
2399 }
2400
2401 return handler;
2402}
2403
cc0e5d42
MG		 2404static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2405 struct mlx5_ib_flow_prio *ft_rx,
2406 struct mlx5_ib_flow_prio *ft_tx,
2407 struct mlx5_flow_destination *dst)
2408{
2409 struct mlx5_ib_flow_handler *handler_rx;
2410 struct mlx5_ib_flow_handler *handler_tx;
2411 int err;
2412 static const struct ib_flow_attr flow_attr = {
2413 .num_of_specs = 0,
2414 .size = sizeof(flow_attr)
2415 };
2416
2417 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2418 if (IS_ERR(handler_rx)) {
2419 err = PTR_ERR(handler_rx);
2420 goto err;
2421 }
2422
2423 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2424 if (IS_ERR(handler_tx)) {
2425 err = PTR_ERR(handler_tx);
2426 goto err_tx;
2427 }
2428
2429 list_add(&handler_tx->list, &handler_rx->list);
2430
2431 return handler_rx;
2432
2433err_tx:
74491de9 2434 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2435 ft_rx->refcount--;
2436 kfree(handler_rx);
2437err:
2438 return ERR_PTR(err);
2439}
2440
038d2ef8
MG		 2441static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2442 struct ib_flow_attr *flow_attr,
2443 int domain)
2444{
2445 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2446 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2447 struct mlx5_ib_flow_handler *handler = NULL;
2448 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2449 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2450 struct mlx5_ib_flow_prio *ft_prio;
2451 int err;
2452
2453 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2454 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2455
2456 if (domain != IB_FLOW_DOMAIN_USER ||
2457 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2458 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2459 return ERR_PTR(-EINVAL);
2460
2461 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2462 if (!dst)
2463 return ERR_PTR(-ENOMEM);
2464
2465 mutex_lock(&dev->flow_db.lock);
2466
cc0e5d42 2467 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2468 if (IS_ERR(ft_prio)) {
2469 err = PTR_ERR(ft_prio);
2470 goto unlock;
2471 }
cc0e5d42
MG		 2472 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2473 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2474 if (IS_ERR(ft_prio_tx)) {
2475 err = PTR_ERR(ft_prio_tx);
2476 ft_prio_tx = NULL;
2477 goto destroy_ft;
2478 }
2479 }
038d2ef8
MG		 2480
2481 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2482 if (mqp->flags & MLX5_IB_QP_RSS)
2483 dst->tir_num = mqp->rss_qp.tirn;
2484 else
2485 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2486
2487 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2488 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2489 handler = create_dont_trap_rule(dev, ft_prio,
2490 flow_attr, dst);
2491 } else {
2492 handler = create_flow_rule(dev, ft_prio, flow_attr,
2493 dst);
2494 }
038d2ef8
MG		 2495 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2496 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2497 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2498 dst);
cc0e5d42
MG		 2499 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2500 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2501 } else {
2502 err = -EINVAL;
2503 goto destroy_ft;
2504 }
2505
2506 if (IS_ERR(handler)) {
2507 err = PTR_ERR(handler);
2508 handler = NULL;
2509 goto destroy_ft;
2510 }
2511
038d2ef8
MG		 2512 mutex_unlock(&dev->flow_db.lock);
2513 kfree(dst);
2514
2515 return &handler->ibflow;
2516
2517destroy_ft:
2518 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2519 if (ft_prio_tx)
2520 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2521unlock:
2522 mutex_unlock(&dev->flow_db.lock);
2523 kfree(dst);
2524 kfree(handler);
2525 return ERR_PTR(err);
2526}
2527
e126ba97
EC		 2528static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2529{
2530 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2531 int err;
2532
9603b61d 2533 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2534 if (err)
2535 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2536 ibqp->qp_num, gid->raw);
2537
2538 return err;
2539}
2540
2541static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2542{
2543 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2544 int err;
2545
9603b61d 2546 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2547 if (err)
2548 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2549 ibqp->qp_num, gid->raw);
2550
2551 return err;
2552}
2553
2554static int init_node_data(struct mlx5_ib_dev *dev)
2555{
1b5daf11 2556 int err;
e126ba97 2557
1b5daf11 2558 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2559 if (err)
1b5daf11 2560 return err;
e126ba97 2561
1b5daf11 2562 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2563
1b5daf11 2564 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2565}
2566
2567static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2568 char *buf)
2569{
2570 struct mlx5_ib_dev *dev =
2571 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2572
9603b61d 2573 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2574}
2575
2576static ssize_t show_reg_pages(struct device *device,
2577 struct device_attribute *attr, char *buf)
2578{
2579 struct mlx5_ib_dev *dev =
2580 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2581
6aec21f6 2582 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2583}
2584
2585static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2586 char *buf)
2587{
2588 struct mlx5_ib_dev *dev =
2589 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2590 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2591}
2592
e126ba97
EC		 2593static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2594 char *buf)
2595{
2596 struct mlx5_ib_dev *dev =
2597 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2598 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2599}
2600
2601static ssize_t show_board(struct device *device, struct device_attribute *attr,
2602 char *buf)
2603{
2604 struct mlx5_ib_dev *dev =
2605 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2606 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2607 dev->mdev->board_id);
e126ba97
EC		 2608}
2609
2610static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2611static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2612static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2613static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2614static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2615
2616static struct device_attribute *mlx5_class_attributes[] = {
2617 &dev_attr_hw_rev,
e126ba97
EC		 2618 &dev_attr_hca_type,
2619 &dev_attr_board_id,
2620 &dev_attr_fw_pages,
2621 &dev_attr_reg_pages,
2622};
2623
7722f47e
HE		 2624static void pkey_change_handler(struct work_struct *work)
2625{
2626 struct mlx5_ib_port_resources *ports =
2627 container_of(work, struct mlx5_ib_port_resources,
2628 pkey_change_work);
2629
2630 mutex_lock(&ports->devr->mutex);
2631 mlx5_ib_gsi_pkey_change(ports->gsi);
2632 mutex_unlock(&ports->devr->mutex);
2633}
2634
89ea94a7
MG		 2635static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2636{
2637 struct mlx5_ib_qp *mqp;
2638 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2639 struct mlx5_core_cq *mcq;
2640 struct list_head cq_armed_list;
2641 unsigned long flags_qp;
2642 unsigned long flags_cq;
2643 unsigned long flags;
2644
2645 INIT_LIST_HEAD(&cq_armed_list);
2646
2647 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2648 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2649 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2650 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2651 if (mqp->sq.tail != mqp->sq.head) {
2652 send_mcq = to_mcq(mqp->ibqp.send_cq);
2653 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2654 if (send_mcq->mcq.comp &&
2655 mqp->ibqp.send_cq->comp_handler) {
2656 if (!send_mcq->mcq.reset_notify_added) {
2657 send_mcq->mcq.reset_notify_added = 1;
2658 list_add_tail(&send_mcq->mcq.reset_notify,
2659 &cq_armed_list);
2660 }
2661 }
2662 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2663 }
2664 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2665 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2666 /* no handling is needed for SRQ */
2667 if (!mqp->ibqp.srq) {
2668 if (mqp->rq.tail != mqp->rq.head) {
2669 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2670 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2671 if (recv_mcq->mcq.comp &&
2672 mqp->ibqp.recv_cq->comp_handler) {
2673 if (!recv_mcq->mcq.reset_notify_added) {
2674 recv_mcq->mcq.reset_notify_added = 1;
2675 list_add_tail(&recv_mcq->mcq.reset_notify,
2676 &cq_armed_list);
2677 }
2678 }
2679 spin_unlock_irqrestore(&recv_mcq->lock,
2680 flags_cq);
2681 }
2682 }
2683 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2684 }
2685 /*At that point all inflight post send were put to be executed as of we
2686 * lock/unlock above locks Now need to arm all involved CQs.
2687 */
2688 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2689 mcq->comp(mcq);
2690 }
2691 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2692}
2693
9603b61d 2694static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2695 enum mlx5_dev_event event, unsigned long param)
e126ba97 2696{
9603b61d 2697 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2698 struct ib_event ibev;
dbaaff2a 2699 bool fatal = false;
e126ba97
EC		 2700 u8 port = 0;
2701
2702 switch (event) {
2703 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 2704 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2705 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 2706 fatal = true;
e126ba97
EC		 2707 break;
2708
2709 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2710 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2711 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2712 port = (u8)param;
5ec8c83e
AH		 2713
2714 /* In RoCE, port up/down events are handled in
2715 * mlx5_netdev_event().
2716 */
2717 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2718 IB_LINK_LAYER_ETHERNET)
2719 return;
2720
2721 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2722 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2723 break;
2724
e126ba97
EC		 2725 case MLX5_DEV_EVENT_LID_CHANGE:
2726 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2727 port = (u8)param;
e126ba97
EC		 2728 break;
2729
2730 case MLX5_DEV_EVENT_PKEY_CHANGE:
2731 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2732 port = (u8)param;
7722f47e
HE		 2733
2734 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2735 break;
2736
2737 case MLX5_DEV_EVENT_GUID_CHANGE:
2738 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2739 port = (u8)param;
e126ba97
EC		 2740 break;
2741
2742 case MLX5_DEV_EVENT_CLIENT_REREG:
2743 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2744 port = (u8)param;
e126ba97 2745 break;
bdc37924
SM		 2746 default:
2747 return;
e126ba97
EC		 2748 }
2749
2750 ibev.device = &ibdev->ib_dev;
2751 ibev.element.port_num = port;
2752
a0c84c32
EC		 2753 if (port < 1 || port > ibdev->num_ports) {
2754 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2755 return;
2756 }
2757
e126ba97
EC		 2758 if (ibdev->ib_active)
2759 ib_dispatch_event(&ibev);
dbaaff2a
EC		 2760
2761 if (fatal)
2762 ibdev->ib_active = false;
e126ba97
EC		 2763}
2764
c43f1112
MG		 2765static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2766{
2767 struct mlx5_hca_vport_context vport_ctx;
2768 int err;
2769 int port;
2770
2771 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2772 dev->mdev->port_caps[port - 1].has_smi = false;
2773 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2774 MLX5_CAP_PORT_TYPE_IB) {
2775 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2776 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2777 port, 0,
2778 &vport_ctx);
2779 if (err) {
2780 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2781 port, err);
2782 return err;
2783 }
2784 dev->mdev->port_caps[port - 1].has_smi =
2785 vport_ctx.has_smi;
2786 } else {
2787 dev->mdev->port_caps[port - 1].has_smi = true;
2788 }
2789 }
2790 }
2791 return 0;
2792}
2793
e126ba97
EC		 2794static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2795{
2796 int port;
2797
938fe83c 2798 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2799 mlx5_query_ext_port_caps(dev, port);
2800}
2801
2802static int get_port_caps(struct mlx5_ib_dev *dev)
2803{
2804 struct ib_device_attr *dprops = NULL;
2805 struct ib_port_attr *pprops = NULL;
f614fc15 2806 int err = -ENOMEM;
e126ba97 2807 int port;
2528e33e 2808 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2809
2810 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2811 if (!pprops)
2812 goto out;
2813
2814 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2815 if (!dprops)
2816 goto out;
2817
c43f1112
MG		 2818 err = set_has_smi_cap(dev);
2819 if (err)
2820 goto out;
2821
2528e33e 2822 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2823 if (err) {
2824 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2825 goto out;
2826 }
2827
938fe83c 2828 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
c4550c63 2829 memset(pprops, 0, sizeof(*pprops));
e126ba97
EC		 2830 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2831 if (err) {
938fe83c
SM		 2832 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2833 port, err);
e126ba97
EC		 2834 break;
2835 }
938fe83c
SM		 2836 dev->mdev->port_caps[port - 1].pkey_table_len =
2837 dprops->max_pkeys;
2838 dev->mdev->port_caps[port - 1].gid_table_len =
2839 pprops->gid_tbl_len;
e126ba97
EC		 2840 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2841 dprops->max_pkeys, pprops->gid_tbl_len);
2842 }
2843
2844out:
2845 kfree(pprops);
2846 kfree(dprops);
2847
2848 return err;
2849}
2850
2851static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2852{
2853 int err;
2854
2855 err = mlx5_mr_cache_cleanup(dev);
2856 if (err)
2857 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2858
2859 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2860 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2861 ib_dealloc_pd(dev->umrc.pd);
2862}
2863
2864enum {
2865 MAX_UMR_WR = 128,
2866};
2867
2868static int create_umr_res(struct mlx5_ib_dev *dev)
2869{
2870 struct ib_qp_init_attr *init_attr = NULL;
2871 struct ib_qp_attr *attr = NULL;
2872 struct ib_pd *pd;
2873 struct ib_cq *cq;
2874 struct ib_qp *qp;
e126ba97
EC		 2875 int ret;
2876
2877 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2878 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2879 if (!attr || !init_attr) {
2880 ret = -ENOMEM;
2881 goto error_0;
2882 }
2883
ed082d36 2884 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2885 if (IS_ERR(pd)) {
2886 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2887 ret = PTR_ERR(pd);
2888 goto error_0;
2889 }
2890
add08d76 2891 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2892 if (IS_ERR(cq)) {
2893 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2894 ret = PTR_ERR(cq);
2895 goto error_2;
2896 }
e126ba97
EC		 2897
2898 init_attr->send_cq = cq;
2899 init_attr->recv_cq = cq;
2900 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2901 init_attr->cap.max_send_wr = MAX_UMR_WR;
2902 init_attr->cap.max_send_sge = 1;
2903 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2904 init_attr->port_num = 1;
2905 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2906 if (IS_ERR(qp)) {
2907 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2908 ret = PTR_ERR(qp);
2909 goto error_3;
2910 }
2911 qp->device = &dev->ib_dev;
2912 qp->real_qp = qp;
2913 qp->uobject = NULL;
2914 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2915
2916 attr->qp_state = IB_QPS_INIT;
2917 attr->port_num = 1;
2918 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2919 IB_QP_PORT, NULL);
2920 if (ret) {
2921 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2922 goto error_4;
2923 }
2924
2925 memset(attr, 0, sizeof(*attr));
2926 attr->qp_state = IB_QPS_RTR;
2927 attr->path_mtu = IB_MTU_256;
2928
2929 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2930 if (ret) {
2931 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2932 goto error_4;
2933 }
2934
2935 memset(attr, 0, sizeof(*attr));
2936 attr->qp_state = IB_QPS_RTS;
2937 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2938 if (ret) {
2939 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2940 goto error_4;
2941 }
2942
2943 dev->umrc.qp = qp;
2944 dev->umrc.cq = cq;
e126ba97
EC		 2945 dev->umrc.pd = pd;
2946
2947 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2948 ret = mlx5_mr_cache_init(dev);
2949 if (ret) {
2950 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2951 goto error_4;
2952 }
2953
2954 kfree(attr);
2955 kfree(init_attr);
2956
2957 return 0;
2958
2959error_4:
2960 mlx5_ib_destroy_qp(qp);
2961
2962error_3:
add08d76 2963 ib_free_cq(cq);
e126ba97
EC		 2964
2965error_2:
e126ba97
EC		 2966 ib_dealloc_pd(pd);
2967
2968error_0:
2969 kfree(attr);
2970 kfree(init_attr);
2971 return ret;
2972}
2973
6e8484c5
MG		 2974static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2975{
2976 switch (umr_fence_cap) {
2977 case MLX5_CAP_UMR_FENCE_NONE:
2978 return MLX5_FENCE_MODE_NONE;
2979 case MLX5_CAP_UMR_FENCE_SMALL:
2980 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2981 default:
2982 return MLX5_FENCE_MODE_STRONG_ORDERING;
2983 }
2984}
2985
e126ba97
EC		 2986static int create_dev_resources(struct mlx5_ib_resources *devr)
2987{
2988 struct ib_srq_init_attr attr;
2989 struct mlx5_ib_dev *dev;
bcf4c1ea 2990 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2991 int port;
e126ba97
EC		 2992 int ret = 0;
2993
2994 dev = container_of(devr, struct mlx5_ib_dev, devr);
2995
d16e91da
HE		 2996 mutex_init(&devr->mutex);
2997
e126ba97
EC		 2998 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2999 if (IS_ERR(devr->p0)) {
3000 ret = PTR_ERR(devr->p0);
3001 goto error0;
3002 }
3003 devr->p0->device = &dev->ib_dev;
3004 devr->p0->uobject = NULL;
3005 atomic_set(&devr->p0->usecnt, 0);
3006
bcf4c1ea 3007 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3008 if (IS_ERR(devr->c0)) {
3009 ret = PTR_ERR(devr->c0);
3010 goto error1;
3011 }
3012 devr->c0->device = &dev->ib_dev;
3013 devr->c0->uobject = NULL;
3014 devr->c0->comp_handler = NULL;
3015 devr->c0->event_handler = NULL;
3016 devr->c0->cq_context = NULL;
3017 atomic_set(&devr->c0->usecnt, 0);
3018
3019 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3020 if (IS_ERR(devr->x0)) {
3021 ret = PTR_ERR(devr->x0);
3022 goto error2;
3023 }
3024 devr->x0->device = &dev->ib_dev;
3025 devr->x0->inode = NULL;
3026 atomic_set(&devr->x0->usecnt, 0);
3027 mutex_init(&devr->x0->tgt_qp_mutex);
3028 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3029
3030 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3031 if (IS_ERR(devr->x1)) {
3032 ret = PTR_ERR(devr->x1);
3033 goto error3;
3034 }
3035 devr->x1->device = &dev->ib_dev;
3036 devr->x1->inode = NULL;
3037 atomic_set(&devr->x1->usecnt, 0);
3038 mutex_init(&devr->x1->tgt_qp_mutex);
3039 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3040
3041 memset(&attr, 0, sizeof(attr));
3042 attr.attr.max_sge = 1;
3043 attr.attr.max_wr = 1;
3044 attr.srq_type = IB_SRQT_XRC;
3045 attr.ext.xrc.cq = devr->c0;
3046 attr.ext.xrc.xrcd = devr->x0;
3047
3048 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3049 if (IS_ERR(devr->s0)) {
3050 ret = PTR_ERR(devr->s0);
3051 goto error4;
3052 }
3053 devr->s0->device = &dev->ib_dev;
3054 devr->s0->pd = devr->p0;
3055 devr->s0->uobject = NULL;
3056 devr->s0->event_handler = NULL;
3057 devr->s0->srq_context = NULL;
3058 devr->s0->srq_type = IB_SRQT_XRC;
3059 devr->s0->ext.xrc.xrcd = devr->x0;
3060 devr->s0->ext.xrc.cq = devr->c0;
3061 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3062 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3063 atomic_inc(&devr->p0->usecnt);
3064 atomic_set(&devr->s0->usecnt, 0);
3065
4aa17b28
HA		 3066 memset(&attr, 0, sizeof(attr));
3067 attr.attr.max_sge = 1;
3068 attr.attr.max_wr = 1;
3069 attr.srq_type = IB_SRQT_BASIC;
3070 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3071 if (IS_ERR(devr->s1)) {
3072 ret = PTR_ERR(devr->s1);
3073 goto error5;
3074 }
3075 devr->s1->device = &dev->ib_dev;
3076 devr->s1->pd = devr->p0;
3077 devr->s1->uobject = NULL;
3078 devr->s1->event_handler = NULL;
3079 devr->s1->srq_context = NULL;
3080 devr->s1->srq_type = IB_SRQT_BASIC;
3081 devr->s1->ext.xrc.cq = devr->c0;
3082 atomic_inc(&devr->p0->usecnt);
3083 atomic_set(&devr->s0->usecnt, 0);
3084
7722f47e
HE		 3085 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3086 INIT_WORK(&devr->ports[port].pkey_change_work,
3087 pkey_change_handler);
3088 devr->ports[port].devr = devr;
3089 }
3090
e126ba97
EC		 3091 return 0;
3092
4aa17b28
HA		 3093error5:
3094 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3095error4:
3096 mlx5_ib_dealloc_xrcd(devr->x1);
3097error3:
3098 mlx5_ib_dealloc_xrcd(devr->x0);
3099error2:
3100 mlx5_ib_destroy_cq(devr->c0);
3101error1:
3102 mlx5_ib_dealloc_pd(devr->p0);
3103error0:
3104 return ret;
3105}
3106
3107static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3108{
7722f47e
HE		 3109 struct mlx5_ib_dev *dev =
3110 container_of(devr, struct mlx5_ib_dev, devr);
3111 int port;
3112
4aa17b28 3113 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3114 mlx5_ib_destroy_srq(devr->s0);
3115 mlx5_ib_dealloc_xrcd(devr->x0);
3116 mlx5_ib_dealloc_xrcd(devr->x1);
3117 mlx5_ib_destroy_cq(devr->c0);
3118 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3119
3120 /* Make sure no change P_Key work items are still executing */
3121 for (port = 0; port < dev->num_ports; ++port)
3122 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3123}
3124
e53505a8
AS		 3125static u32 get_core_cap_flags(struct ib_device *ibdev)
3126{
3127 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3128 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3129 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3130 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3131 u32 ret = 0;
3132
3133 if (ll == IB_LINK_LAYER_INFINIBAND)
3134 return RDMA_CORE_PORT_IBA_IB;
3135
72cd5717
OG		 3136 ret = RDMA_CORE_PORT_RAW_PACKET;
3137
e53505a8 3138 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3139 return ret;
e53505a8
AS		 3140
3141 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3142 return ret;
e53505a8
AS		 3143
3144 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3145 ret |= RDMA_CORE_PORT_IBA_ROCE;
3146
3147 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3148 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3149
3150 return ret;
3151}
3152
7738613e
IW		 3153static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3154 struct ib_port_immutable *immutable)
3155{
3156 struct ib_port_attr attr;
ca5b91d6
OG		 3157 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3158 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3159 int err;
3160
c4550c63
OG		 3161 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3162
3163 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3164 if (err)
3165 return err;
3166
3167 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3168 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3169 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3170 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3171 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3172
3173 return 0;
3174}
3175
c7342823
IW		 3176static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3177 size_t str_len)
3178{
3179 struct mlx5_ib_dev *dev =
3180 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3181 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3182 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3183}
3184
45f95acd 3185static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3186{
3187 struct mlx5_core_dev *mdev = dev->mdev;
3188 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3189 MLX5_FLOW_NAMESPACE_LAG);
3190 struct mlx5_flow_table *ft;
3191 int err;
3192
3193 if (!ns || !mlx5_lag_is_active(mdev))
3194 return 0;
3195
3196 err = mlx5_cmd_create_vport_lag(mdev);
3197 if (err)
3198 return err;
3199
3200 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3201 if (IS_ERR(ft)) {
3202 err = PTR_ERR(ft);
3203 goto err_destroy_vport_lag;
3204 }
3205
3206 dev->flow_db.lag_demux_ft = ft;
3207 return 0;
3208
3209err_destroy_vport_lag:
3210 mlx5_cmd_destroy_vport_lag(mdev);
3211 return err;
3212}
3213
45f95acd 3214static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3215{
3216 struct mlx5_core_dev *mdev = dev->mdev;
3217
3218 if (dev->flow_db.lag_demux_ft) {
3219 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3220 dev->flow_db.lag_demux_ft = NULL;
3221
3222 mlx5_cmd_destroy_vport_lag(mdev);
3223 }
3224}
3225
d012f5d6
OG		 3226static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3227{
3228 int err;
3229
3230 dev->roce.nb.notifier_call = mlx5_netdev_event;
3231 err = register_netdevice_notifier(&dev->roce.nb);
3232 if (err) {
3233 dev->roce.nb.notifier_call = NULL;
3234 return err;
3235 }
3236
3237 return 0;
3238}
3239
3240static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
5ec8c83e
AH		 3241{
3242 if (dev->roce.nb.notifier_call) {
3243 unregister_netdevice_notifier(&dev->roce.nb);
3244 dev->roce.nb.notifier_call = NULL;
3245 }
3246}
3247
45f95acd 3248static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3249{
e53505a8
AS		 3250 int err;
3251
d012f5d6
OG		 3252 err = mlx5_add_netdev_notifier(dev);
3253 if (err)
e53505a8
AS		 3254 return err;
3255
ca5b91d6
OG		 3256 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3257 err = mlx5_nic_vport_enable_roce(dev->mdev);
3258 if (err)
3259 goto err_unregister_netdevice_notifier;
3260 }
e53505a8 3261
45f95acd 3262 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3263 if (err)
3264 goto err_disable_roce;
3265
e53505a8
AS		 3266 return 0;
3267
9ef9c640 3268err_disable_roce:
ca5b91d6
OG		 3269 if (MLX5_CAP_GEN(dev->mdev, roce))
3270 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3271
e53505a8 3272err_unregister_netdevice_notifier:
d012f5d6 3273 mlx5_remove_netdev_notifier(dev);
e53505a8 3274 return err;
fc24fc5e
AS		 3275}
3276
45f95acd 3277static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3278{
45f95acd 3279 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3280 if (MLX5_CAP_GEN(dev->mdev, roce))
3281 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3282}
3283
e1f24a79 3284struct mlx5_ib_counter {
7c16f477
KH		 3285 const char *name;
3286 size_t offset;
3287};
3288
3289#define INIT_Q_COUNTER(_name) \
3290 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3291
e1f24a79 3292static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3293 INIT_Q_COUNTER(rx_write_requests),
3294 INIT_Q_COUNTER(rx_read_requests),
3295 INIT_Q_COUNTER(rx_atomic_requests),
3296 INIT_Q_COUNTER(out_of_buffer),
3297};
3298
e1f24a79 3299static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3300 INIT_Q_COUNTER(out_of_sequence),
3301};
3302
e1f24a79 3303static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3304 INIT_Q_COUNTER(duplicate_request),
3305 INIT_Q_COUNTER(rnr_nak_retry_err),
3306 INIT_Q_COUNTER(packet_seq_err),
3307 INIT_Q_COUNTER(implied_nak_seq_err),
3308 INIT_Q_COUNTER(local_ack_timeout_err),
3309};
3310
e1f24a79
PP		 3311#define INIT_CONG_COUNTER(_name) \
3312 { .name = #_name, .offset = \
3313 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3314
3315static const struct mlx5_ib_counter cong_cnts[] = {
3316 INIT_CONG_COUNTER(rp_cnp_ignored),
3317 INIT_CONG_COUNTER(rp_cnp_handled),
3318 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3319 INIT_CONG_COUNTER(np_cnp_sent),
3320};
3321
3322static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3323{
3324 unsigned int i;
3325
7c16f477 3326 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3327 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3328 dev->port[i].cnts.set_id);
3329 kfree(dev->port[i].cnts.names);
3330 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3331 }
3332}
3333
e1f24a79
PP		 3334static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3335 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3336{
3337 u32 num_counters;
3338
3339 num_counters = ARRAY_SIZE(basic_q_cnts);
3340
3341 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3342 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3343
3344 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3345 num_counters += ARRAY_SIZE(retrans_q_cnts);
e1f24a79 3346 cnts->num_q_counters = num_counters;
7c16f477 3347
e1f24a79
PP		 3348 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3349 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3350 num_counters += ARRAY_SIZE(cong_cnts);
3351 }
3352
3353 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3354 if (!cnts->names)
7c16f477
KH		 3355 return -ENOMEM;
3356
e1f24a79
PP		 3357 cnts->offsets = kcalloc(num_counters,
3358 sizeof(cnts->offsets), GFP_KERNEL);
3359 if (!cnts->offsets)
7c16f477
KH		 3360 goto err_names;
3361
7c16f477
KH		 3362 return 0;
3363
3364err_names:
e1f24a79 3365 kfree(cnts->names);
7c16f477
KH		 3366 return -ENOMEM;
3367}
3368
e1f24a79
PP		 3369static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3370 const char **names,
3371 size_t *offsets)
7c16f477
KH		 3372{
3373 int i;
3374 int j = 0;
3375
3376 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3377 names[j] = basic_q_cnts[i].name;
3378 offsets[j] = basic_q_cnts[i].offset;
3379 }
3380
3381 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3382 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3383 names[j] = out_of_seq_q_cnts[i].name;
3384 offsets[j] = out_of_seq_q_cnts[i].offset;
3385 }
3386 }
3387
3388 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3389 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3390 names[j] = retrans_q_cnts[i].name;
3391 offsets[j] = retrans_q_cnts[i].offset;
3392 }
3393 }
e1f24a79
PP		 3394
3395 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3396 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3397 names[j] = cong_cnts[i].name;
3398 offsets[j] = cong_cnts[i].offset;
3399 }
3400 }
0837e86a
MB		 3401}
3402
e1f24a79 3403static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3404{
3405 int i;
3406 int ret;
3407
3408 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3409 struct mlx5_ib_port *port = &dev->port[i];
3410
0837e86a 3411 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3412 &port->cnts.set_id);
0837e86a
MB		 3413 if (ret) {
3414 mlx5_ib_warn(dev,
3415 "couldn't allocate queue counter for port %d, err %d\n",
3416 i + 1, ret);
3417 goto dealloc_counters;
3418 }
7c16f477 3419
e1f24a79 3420 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3421 if (ret)
3422 goto dealloc_counters;
3423
e1f24a79
PP		 3424 mlx5_ib_fill_counters(dev, port->cnts.names,
3425 port->cnts.offsets);
0837e86a
MB		 3426 }
3427
3428 return 0;
3429
3430dealloc_counters:
3431 while (--i >= 0)
3432 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3433 dev->port[i].cnts.set_id);
0837e86a
MB		 3434
3435 return ret;
3436}
3437
0ad17a8f
MB		 3438static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3439 u8 port_num)
3440{
7c16f477
KH		 3441 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3442 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3443
3444 /* We support only per port stats */
3445 if (port_num == 0)
3446 return NULL;
3447
e1f24a79
PP		 3448 return rdma_alloc_hw_stats_struct(port->cnts.names,
3449 port->cnts.num_q_counters +
3450 port->cnts.num_cong_counters,
0ad17a8f
MB		 3451 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3452}
3453
e1f24a79
PP		 3454static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3455 struct mlx5_ib_port *port,
3456 struct rdma_hw_stats *stats)
0ad17a8f 3457{
0ad17a8f
MB		 3458 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3459 void *out;
3460 __be32 val;
e1f24a79 3461 int ret, i;
0ad17a8f 3462
1b9a07ee 3463 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3464 if (!out)
3465 return -ENOMEM;
3466
3467 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3468 port->cnts.set_id, 0,
0ad17a8f
MB		 3469 out, outlen);
3470 if (ret)
3471 goto free;
3472
e1f24a79
PP		 3473 for (i = 0; i < port->cnts.num_q_counters; i++) {
3474 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3475 stats->value[i] = (u64)be32_to_cpu(val);
3476 }
7c16f477 3477
0ad17a8f
MB		 3478free:
3479 kvfree(out);
e1f24a79
PP		 3480 return ret;
3481}
3482
3483static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3484 struct mlx5_ib_port *port,
3485 struct rdma_hw_stats *stats)
3486{
3487 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3488 void *out;
3489 int ret, i;
3490 int offset = port->cnts.num_q_counters;
3491
1b9a07ee 3492 out = kvzalloc(outlen, GFP_KERNEL);
e1f24a79
PP		 3493 if (!out)
3494 return -ENOMEM;
3495
3496 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3497 if (ret)
3498 goto free;
3499
3500 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3501 stats->value[i + offset] =
3502 be64_to_cpup((__be64 *)(out +
3503 port->cnts.offsets[i + offset]));
3504 }
3505
3506free:
3507 kvfree(out);
3508 return ret;
3509}
3510
3511static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3512 struct rdma_hw_stats *stats,
3513 u8 port_num, int index)
3514{
3515 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3516 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3517 int ret, num_counters;
3518
3519 if (!stats)
3520 return -EINVAL;
3521
3522 ret = mlx5_ib_query_q_counters(dev, port, stats);
3523 if (ret)
3524 return ret;
3525 num_counters = port->cnts.num_q_counters;
3526
3527 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3528 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3529 if (ret)
3530 return ret;
3531 num_counters += port->cnts.num_cong_counters;
3532 }
3533
3534 return num_counters;
0ad17a8f
MB		 3535}
3536
8e959601
NV		 3537static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3538{
3539 return mlx5_rdma_netdev_free(netdev);
3540}
3541
693dfd5a
ES		 3542static struct net_device*
3543mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3544 u8 port_num,
3545 enum rdma_netdev_t type,
3546 const char *name,
3547 unsigned char name_assign_type,
3548 void (*setup)(struct net_device *))
3549{
8e959601
NV		 3550 struct net_device *netdev;
3551 struct rdma_netdev *rn;
3552
693dfd5a
ES		 3553 if (type != RDMA_NETDEV_IPOIB)
3554 return ERR_PTR(-EOPNOTSUPP);
3555
8e959601
NV		 3556 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3557 name, setup);
3558 if (likely(!IS_ERR_OR_NULL(netdev))) {
3559 rn = netdev_priv(netdev);
3560 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3561 }
3562 return netdev;
693dfd5a
ES		 3563}
3564
9603b61d 3565static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 3566{
e126ba97 3567 struct mlx5_ib_dev *dev;
ebd61f68
AS		 3568 enum rdma_link_layer ll;
3569 int port_type_cap;
4babcf97 3570 const char *name;
e126ba97
EC		 3571 int err;
3572 int i;
3573
ebd61f68
AS		 3574 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3575 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3576
e126ba97
EC		 3577 printk_once(KERN_INFO "%s", mlx5_version);
3578
3579 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3580 if (!dev)
9603b61d 3581 return NULL;
e126ba97 3582
9603b61d 3583 dev->mdev = mdev;
e126ba97 3584
0837e86a
MB		 3585 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3586 GFP_KERNEL);
3587 if (!dev->port)
3588 goto err_dealloc;
3589
fc24fc5e 3590 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 3591 err = get_port_caps(dev);
3592 if (err)
0837e86a 3593 goto err_free_port;
e126ba97 3594
1b5daf11
MD		 3595 if (mlx5_use_mad_ifc(dev))
3596 get_ext_port_caps(dev);
e126ba97 3597
4babcf97
AH		 3598 if (!mlx5_lag_is_active(mdev))
3599 name = "mlx5_%d";
3600 else
3601 name = "mlx5_bond_%d";
3602
3603 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 3604 dev->ib_dev.owner = THIS_MODULE;
3605 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 3606 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 3607 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 3608 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 3609 dev->ib_dev.num_comp_vectors =
3610 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 3611 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97
EC		 3612
3613 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3614 dev->ib_dev.uverbs_cmd_mask =
3615 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3616 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3617 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3618 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3619 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 3620 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3621 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 3622 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 3623 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 3624 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3625 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3626 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3627 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3628 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3629 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3630 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3631 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3632 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3633 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3634 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3635 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3636 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3637 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3638 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3639 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3640 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3641 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3642 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3643 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349
BW		 3644 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3645 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
e126ba97
EC		 3646
3647 dev->ib_dev.query_device = mlx5_ib_query_device;
3648 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3649 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3650 if (ll == IB_LINK_LAYER_ETHERNET)
3651 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3652 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3653 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3654 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3655 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3656 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3657 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3658 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3659 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3660 dev->ib_dev.mmap = mlx5_ib_mmap;
3661 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3662 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3663 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3664 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3665 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3666 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3667 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3668 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3669 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3670 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3671 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3672 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3673 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3674 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3675 dev->ib_dev.post_send = mlx5_ib_post_send;
3676 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3677 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3678 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3679 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3680 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3681 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3682 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3683 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3684 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 3685 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 3686 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3687 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3688 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3689 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 3690 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 3691 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 3692 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 3693 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 3694 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
8e959601 3695 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 3696 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 3697
eff901d3
EC		 3698 if (mlx5_core_is_pf(mdev)) {
3699 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3700 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3701 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3702 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3703 }
e126ba97 3704
7c2344c3
MG		 3705 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3706
938fe83c 3707 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 3708
6e8484c5
MG		 3709 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3710
d2370e0a
MB		 3711 if (MLX5_CAP_GEN(mdev, imaicl)) {
3712 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3713 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3714 dev->ib_dev.uverbs_cmd_mask |=
3715 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3716 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3717 }
3718
7c16f477 3719 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
0ad17a8f
MB		 3720 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3721 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3722 }
3723
938fe83c 3724 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 3725 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3726 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3727 dev->ib_dev.uverbs_cmd_mask |=
3728 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3729 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3730 }
3731
048ccca8 3732 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 3733 IB_LINK_LAYER_ETHERNET) {
3734 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3735 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 3736 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3737 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3738 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 3739 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3740 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 3741 dev->ib_dev.uverbs_ex_cmd_mask |=
3742 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 3743 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3744 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3745 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 3746 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3747 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3748 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 3749 }
e126ba97
EC		 3750 err = init_node_data(dev);
3751 if (err)
90be7c8a 3752 goto err_free_port;
e126ba97 3753
038d2ef8 3754 mutex_init(&dev->flow_db.lock);
e126ba97 3755 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 3756 INIT_LIST_HEAD(&dev->qp_list);
3757 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 3758
fc24fc5e 3759 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 3760 err = mlx5_enable_eth(dev);
fc24fc5e 3761 if (err)
90be7c8a 3762 goto err_free_port;
fc24fc5e
AS		 3763 }
3764
e126ba97
EC		 3765 err = create_dev_resources(&dev->devr);
3766 if (err)
45f95acd 3767 goto err_disable_eth;
e126ba97 3768
6aec21f6 3769 err = mlx5_ib_odp_init_one(dev);
281d1a92 3770 if (err)
e126ba97
EC		 3771 goto err_rsrc;
3772
45bded2c 3773 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
e1f24a79 3774 err = mlx5_ib_alloc_counters(dev);
45bded2c
KH		 3775 if (err)
3776 goto err_odp;
3777 }
6aec21f6 3778
5fe9dec0
EC		 3779 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3780 if (!dev->mdev->priv.uar)
e1f24a79 3781 goto err_cnt;
5fe9dec0
EC		 3782
3783 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3784 if (err)
3785 goto err_uar_page;
3786
3787 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3788 if (err)
3789 goto err_bfreg;
3790
0837e86a
MB		 3791 err = ib_register_device(&dev->ib_dev, NULL);
3792 if (err)
5fe9dec0 3793 goto err_fp_bfreg;
0837e86a 3794
e126ba97
EC		 3795 err = create_umr_res(dev);
3796 if (err)
3797 goto err_dev;
3798
3799 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 3800 err = device_create_file(&dev->ib_dev.dev,
3801 mlx5_class_attributes[i]);
3802 if (err)
e126ba97
EC		 3803 goto err_umrc;
3804 }
3805
3806 dev->ib_active = true;
3807
9603b61d 3808 return dev;
e126ba97
EC		 3809
3810err_umrc:
3811 destroy_umrc_res(dev);
3812
3813err_dev:
3814 ib_unregister_device(&dev->ib_dev);
3815
5fe9dec0
EC		 3816err_fp_bfreg:
3817 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3818
3819err_bfreg:
3820 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3821
3822err_uar_page:
3823 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3824
e1f24a79 3825err_cnt:
45bded2c 3826 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 3827 mlx5_ib_dealloc_counters(dev);
0837e86a 3828
6aec21f6
HE		 3829err_odp:
3830 mlx5_ib_odp_remove_one(dev);
3831
e126ba97
EC		 3832err_rsrc:
3833 destroy_dev_resources(&dev->devr);
3834
45f95acd 3835err_disable_eth:
5ec8c83e 3836 if (ll == IB_LINK_LAYER_ETHERNET) {
45f95acd 3837 mlx5_disable_eth(dev);
d012f5d6 3838 mlx5_remove_netdev_notifier(dev);
5ec8c83e 3839 }
fc24fc5e 3840
0837e86a
MB		 3841err_free_port:
3842 kfree(dev->port);
3843
9603b61d 3844err_dealloc:
e126ba97
EC		 3845 ib_dealloc_device((struct ib_device *)dev);
3846
9603b61d 3847 return NULL;
e126ba97
EC		 3848}
3849
9603b61d 3850static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 3851{
9603b61d 3852 struct mlx5_ib_dev *dev = context;
fc24fc5e 3853 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 3854
d012f5d6 3855 mlx5_remove_netdev_notifier(dev);
e126ba97 3856 ib_unregister_device(&dev->ib_dev);
5fe9dec0
EC		 3857 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3858 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3859 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
45bded2c 3860 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
e1f24a79 3861 mlx5_ib_dealloc_counters(dev);
eefd56e5 3862 destroy_umrc_res(dev);
6aec21f6 3863 mlx5_ib_odp_remove_one(dev);
e126ba97 3864 destroy_dev_resources(&dev->devr);
fc24fc5e 3865 if (ll == IB_LINK_LAYER_ETHERNET)
45f95acd 3866 mlx5_disable_eth(dev);
0837e86a 3867 kfree(dev->port);
e126ba97
EC		 3868 ib_dealloc_device(&dev->ib_dev);
3869}
3870
9603b61d
JM		 3871static struct mlx5_interface mlx5_ib_interface = {
3872 .add = mlx5_ib_add,
3873 .remove = mlx5_ib_remove,
3874 .event = mlx5_ib_event,
d9aaed83
AK		 3875#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3876 .pfault = mlx5_ib_pfault,
3877#endif
64613d94 3878 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 3879};
3880
3881static int __init mlx5_ib_init(void)
3882{
6aec21f6
HE		 3883 int err;
3884
81713d37 3885 mlx5_ib_odp_init();
9603b61d 3886
6aec21f6 3887 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 3888
6aec21f6 3889 return err;
e126ba97
EC		 3890}
3891
3892static void __exit mlx5_ib_cleanup(void)
3893{
9603b61d 3894 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 3895}
3896
3897module_init(mlx5_ib_init);
3898module_exit(mlx5_ib_cleanup);
Ubuntu Artful kernel mirror