]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/infiniband/hw/mlx5/main.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UBUNTU: Ubuntu-5.4.0-117.132
[mirror_ubuntu-focal-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
cecae747 55#include <linux/mlx5/eswitch.h>
7c2344c3 56#include <linux/list.h>
e126ba97
EC		 57#include <rdma/ib_smi.h>
58#include <rdma/ib_umem.h>
038d2ef8
MG		 59#include <linux/in.h>
60#include <linux/etherdevice.h>
e126ba97 61#include "mlx5_ib.h"
fc385b7a 62#include "ib_rep.h"
e1f24a79 63#include "cmd.h"
f3da6577 64#include "srq.h"
3346c487 65#include <linux/mlx5/fs_helpers.h>
c6475a0b 66#include <linux/mlx5/accel.h>
8c84660b 67#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 68#include <rdma/mlx5_user_ioctl_verbs.h>
69#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 70
71#define UVERBS_MODULE_NAME mlx5_ib
72#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 73
74#define DRIVER_NAME "mlx5_ib"
b359911d 75#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 76
77MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
79MODULE_LICENSE("Dual BSD/GPL");
e126ba97 80
e126ba97
EC		 81static char mlx5_version[] =
82 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 83 DRIVER_VERSION "\n";
e126ba97 84
d69a24e0
DJ		 85struct mlx5_ib_event_work {
86 struct work_struct work;
df097a27
SM		 87 union {
88 struct mlx5_ib_dev *dev;
89 struct mlx5_ib_multiport_info *mpi;
90 };
91 bool is_slave;
134e9349 92 unsigned int event;
df097a27 93 void *param;
d69a24e0
DJ		 94};
95
da7525d2
EBE		 96enum {
97 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
98};
99
d69a24e0 100static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 101static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
102static LIST_HEAD(mlx5_ib_dev_list);
103/*
104 * This mutex should be held when accessing either of the above lists
105 */
106static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
107
c44ef998
IL		 108/* We can't use an array for xlt_emergency_page because dma_map_single
109 * doesn't work on kernel modules memory
110 */
111static unsigned long xlt_emergency_page;
112static struct mutex xlt_emergency_page_mutex;
113
32f69e4b
DJ		 114struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
115{
116 struct mlx5_ib_dev *dev;
117
118 mutex_lock(&mlx5_ib_multiport_mutex);
119 dev = mpi->ibdev;
120 mutex_unlock(&mlx5_ib_multiport_mutex);
121 return dev;
122}
123
1b5daf11 124static enum rdma_link_layer
ebd61f68 125mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 126{
ebd61f68 127 switch (port_type_cap) {
1b5daf11
MD		 128 case MLX5_CAP_PORT_TYPE_IB:
129 return IB_LINK_LAYER_INFINIBAND;
130 case MLX5_CAP_PORT_TYPE_ETH:
131 return IB_LINK_LAYER_ETHERNET;
132 default:
133 return IB_LINK_LAYER_UNSPECIFIED;
134 }
135}
136
ebd61f68
AS		 137static enum rdma_link_layer
138mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
139{
140 struct mlx5_ib_dev *dev = to_mdev(device);
141 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
142
143 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
144}
145
fd65f1b8
MS		 146static int get_port_state(struct ib_device *ibdev,
147 u8 port_num,
148 enum ib_port_state *state)
149{
150 struct ib_port_attr attr;
151 int ret;
152
153 memset(&attr, 0, sizeof(attr));
3023a1e9 154 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 155 if (!ret)
156 *state = attr.state;
157 return ret;
158}
159
35b0aa67
MB		 160static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
161 struct net_device *ndev,
162 u8 *port_num)
163{
164 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
165 struct net_device *rep_ndev;
166 struct mlx5_ib_port *port;
167 int i;
168
169 for (i = 0; i < dev->num_ports; i++) {
170 port = &dev->port[i];
171 if (!port->rep)
172 continue;
173
174 read_lock(&port->roce.netdev_lock);
175 rep_ndev = mlx5_ib_get_rep_netdev(esw,
176 port->rep->vport);
177 if (rep_ndev == ndev) {
178 read_unlock(&port->roce.netdev_lock);
179 *port_num = i + 1;
180 return &port->roce;
181 }
182 read_unlock(&port->roce.netdev_lock);
183 }
184
185 return NULL;
186}
187
fc24fc5e
AS		 188static int mlx5_netdev_event(struct notifier_block *this,
189 unsigned long event, void *ptr)
190{
7fd8aefb 191 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 192 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 193 u8 port_num = roce->native_port_num;
194 struct mlx5_core_dev *mdev;
195 struct mlx5_ib_dev *ibdev;
196
197 ibdev = roce->dev;
32f69e4b
DJ		 198 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
199 if (!mdev)
200 return NOTIFY_DONE;
fc24fc5e 201
5ec8c83e
AH		 202 switch (event) {
203 case NETDEV_REGISTER:
35b0aa67
MB		 204 /* Should already be registered during the load */
205 if (ibdev->is_rep)
206 break;
7fd8aefb 207 write_lock(&roce->netdev_lock);
dce45af5 208 if (ndev->dev.parent == mdev->device)
842a9c83 209 roce->netdev = ndev;
7fd8aefb 210 write_unlock(&roce->netdev_lock);
5ec8c83e 211 break;
fc24fc5e 212
842a9c83 213 case NETDEV_UNREGISTER:
35b0aa67 214 /* In case of reps, ib device goes away before the netdevs */
842a9c83
OG		 215 write_lock(&roce->netdev_lock);
216 if (roce->netdev == ndev)
217 roce->netdev = NULL;
218 write_unlock(&roce->netdev_lock);
219 break;
220
fd65f1b8 221 case NETDEV_CHANGE:
5ec8c83e 222 case NETDEV_UP:
88621dfe 223 case NETDEV_DOWN: {
7fd8aefb 224 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 225 struct net_device *upper = NULL;
226
227 if (lag_ndev) {
228 upper = netdev_master_upper_dev_get(lag_ndev);
229 dev_put(lag_ndev);
230 }
231
35b0aa67
MB		 232 if (ibdev->is_rep)
233 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
234 if (!roce)
235 return NOTIFY_DONE;
7fd8aefb 236 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 237 && ibdev->ib_active) {
626bc02d 238 struct ib_event ibev = { };
fd65f1b8 239 enum ib_port_state port_state;
5ec8c83e 240
7fd8aefb
DJ		 241 if (get_port_state(&ibdev->ib_dev, port_num,
242 &port_state))
243 goto done;
fd65f1b8 244
7fd8aefb
DJ		 245 if (roce->last_port_state == port_state)
246 goto done;
fd65f1b8 247
7fd8aefb 248 roce->last_port_state = port_state;
5ec8c83e 249 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 250 if (port_state == IB_PORT_DOWN)
251 ibev.event = IB_EVENT_PORT_ERR;
252 else if (port_state == IB_PORT_ACTIVE)
253 ibev.event = IB_EVENT_PORT_ACTIVE;
254 else
7fd8aefb 255 goto done;
fd65f1b8 256
7fd8aefb 257 ibev.element.port_num = port_num;
5ec8c83e
AH		 258 ib_dispatch_event(&ibev);
259 }
260 break;
88621dfe 261 }
fc24fc5e 262
5ec8c83e
AH		 263 default:
264 break;
265 }
7fd8aefb 266done:
32f69e4b 267 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 268 return NOTIFY_DONE;
269}
270
271static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
272 u8 port_num)
273{
274 struct mlx5_ib_dev *ibdev = to_mdev(device);
275 struct net_device *ndev;
32f69e4b
DJ		 276 struct mlx5_core_dev *mdev;
277
278 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
279 if (!mdev)
280 return NULL;
fc24fc5e 281
32f69e4b 282 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 283 if (ndev)
32f69e4b 284 goto out;
88621dfe 285
fc24fc5e
AS		 286 /* Ensure ndev does not disappear before we invoke dev_hold()
287 */
95579e78
MB		 288 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
289 ndev = ibdev->port[port_num - 1].roce.netdev;
fc24fc5e
AS		 290 if (ndev)
291 dev_hold(ndev);
95579e78 292 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
fc24fc5e 293
32f69e4b
DJ		 294out:
295 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 296 return ndev;
297}
298
32f69e4b
DJ		 299struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
300 u8 ib_port_num,
301 u8 *native_port_num)
302{
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 ib_port_num);
305 struct mlx5_core_dev *mdev = NULL;
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
210b1f78
MB		 309 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
310 ll != IB_LINK_LAYER_ETHERNET) {
311 if (native_port_num)
312 *native_port_num = ib_port_num;
313 return ibdev->mdev;
314 }
315
32f69e4b
DJ		 316 if (native_port_num)
317 *native_port_num = 1;
318
32f69e4b
DJ		 319 port = &ibdev->port[ib_port_num - 1];
320 if (!port)
321 return NULL;
322
323 spin_lock(&port->mp.mpi_lock);
324 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
325 if (mpi && !mpi->unaffiliate) {
326 mdev = mpi->mdev;
327 /* If it's the master no need to refcount, it'll exist
328 * as long as the ib_dev exists.
329 */
330 if (!mpi->is_master)
331 mpi->mdev_refcnt++;
332 }
333 spin_unlock(&port->mp.mpi_lock);
334
335 return mdev;
336}
337
338void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
339{
340 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
341 port_num);
342 struct mlx5_ib_multiport_info *mpi;
343 struct mlx5_ib_port *port;
344
345 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
346 return;
347
348 port = &ibdev->port[port_num - 1];
349
350 spin_lock(&port->mp.mpi_lock);
351 mpi = ibdev->port[port_num - 1].mp.mpi;
352 if (mpi->is_master)
353 goto out;
354
355 mpi->mdev_refcnt--;
356 if (mpi->unaffiliate)
357 complete(&mpi->unref_comp);
358out:
359 spin_unlock(&port->mp.mpi_lock);
360}
361
08e8676f
AL		 362static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
363 u8 *active_width)
f1b65df5
NO		 364{
365 switch (eth_proto_oper) {
366 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
367 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
368 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
369 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
370 *active_width = IB_WIDTH_1X;
371 *active_speed = IB_SPEED_SDR;
372 break;
373 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
374 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
375 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
376 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
377 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
378 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
379 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
380 *active_width = IB_WIDTH_1X;
381 *active_speed = IB_SPEED_QDR;
382 break;
383 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
384 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
385 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
386 *active_width = IB_WIDTH_1X;
387 *active_speed = IB_SPEED_EDR;
388 break;
389 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
390 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
391 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
392 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
393 *active_width = IB_WIDTH_4X;
394 *active_speed = IB_SPEED_QDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
397 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
398 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
399 *active_width = IB_WIDTH_1X;
400 *active_speed = IB_SPEED_HDR;
401 break;
402 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
403 *active_width = IB_WIDTH_4X;
404 *active_speed = IB_SPEED_FDR;
405 break;
406 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
407 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
408 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
409 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
410 *active_width = IB_WIDTH_4X;
411 *active_speed = IB_SPEED_EDR;
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
08e8676f
AL		 420static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
421 u8 *active_width)
422{
423 switch (eth_proto_oper) {
424 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
425 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
426 *active_width = IB_WIDTH_1X;
427 *active_speed = IB_SPEED_SDR;
428 break;
429 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
430 *active_width = IB_WIDTH_1X;
431 *active_speed = IB_SPEED_DDR;
432 break;
433 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
434 *active_width = IB_WIDTH_1X;
435 *active_speed = IB_SPEED_QDR;
436 break;
437 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
438 *active_width = IB_WIDTH_4X;
439 *active_speed = IB_SPEED_QDR;
440 break;
441 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
442 *active_width = IB_WIDTH_1X;
443 *active_speed = IB_SPEED_EDR;
444 break;
445 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
cd272875
AL		 446 *active_width = IB_WIDTH_2X;
447 *active_speed = IB_SPEED_EDR;
448 break;
08e8676f
AL		 449 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
450 *active_width = IB_WIDTH_1X;
451 *active_speed = IB_SPEED_HDR;
452 break;
cd272875
AL		 453 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
454 *active_width = IB_WIDTH_4X;
455 *active_speed = IB_SPEED_EDR;
456 break;
08e8676f
AL		 457 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
458 *active_width = IB_WIDTH_2X;
459 *active_speed = IB_SPEED_HDR;
460 break;
461 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
462 *active_width = IB_WIDTH_4X;
463 *active_speed = IB_SPEED_HDR;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 return 0;
470}
471
472static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
473 u8 *active_width, bool ext)
474{
475 return ext ?
476 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
477 active_width) :
478 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
479 active_width);
480}
481
095b0927
IT		 482static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
483 struct ib_port_attr *props)
3f89a643
AS		 484{
485 struct mlx5_ib_dev *dev = to_mdev(device);
bc4e12ff 486 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
da005f9f 487 struct mlx5_core_dev *mdev;
88621dfe 488 struct net_device *ndev, *upper;
3f89a643 489 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 490 bool put_mdev = true;
c876a1b7 491 u16 qkey_viol_cntr;
f1b65df5 492 u32 eth_prot_oper;
b3cbd6f0 493 u8 mdev_port_num;
08e8676f 494 bool ext;
095b0927 495 int err;
3f89a643 496
b3cbd6f0
DJ		 497 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
498 if (!mdev) {
499 /* This means the port isn't affiliated yet. Get the
500 * info for the master port instead.
501 */
502 put_mdev = false;
503 mdev = dev->mdev;
504 mdev_port_num = 1;
505 port_num = 1;
506 }
507
f1b65df5
NO		 508 /* Possible bad flows are checked before filling out props so in case
509 * of an error it will still be zeroed out.
26628e2d 510 * Use native port in case of reps
50f22fd8 511 */
26628e2d
MB		 512 if (dev->is_rep)
513 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
514 1);
515 else
516 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
517 mdev_port_num);
095b0927 518 if (err)
b3cbd6f0 519 goto out;
1d8d3109 520 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
08e8676f 521 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
f1b65df5 522
7672ed33
HL		 523 props->active_width = IB_WIDTH_4X;
524 props->active_speed = IB_SPEED_QDR;
525
f1b65df5 526 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
08e8676f 527 &props->active_width, ext);
3f89a643 528
2f944c0f
JG		 529 props->port_cap_flags |= IB_PORT_CM_SUP;
530 props->ip_gids = true;
3f89a643
AS		 531
532 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
533 roce_address_table_size);
534 props->max_mtu = IB_MTU_4096;
535 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
536 props->pkey_tbl_len = 1;
537 props->state = IB_PORT_DOWN;
72a7720f 538 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
3f89a643 539
b3cbd6f0 540 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 541 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 542
b3cbd6f0
DJ		 543 /* If this is a stub query for an unaffiliated port stop here */
544 if (!put_mdev)
545 goto out;
546
3f89a643
AS		 547 ndev = mlx5_ib_get_netdev(device, port_num);
548 if (!ndev)
b3cbd6f0 549 goto out;
3f89a643 550
7c34ec19 551 if (dev->lag_active) {
88621dfe
AH		 552 rcu_read_lock();
553 upper = netdev_master_upper_dev_get_rcu(ndev);
554 if (upper) {
555 dev_put(ndev);
556 ndev = upper;
557 dev_hold(ndev);
558 }
559 rcu_read_unlock();
560 }
561
3f89a643
AS		 562 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
563 props->state = IB_PORT_ACTIVE;
72a7720f 564 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
3f89a643
AS		 565 }
566
567 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
568
569 dev_put(ndev);
570
571 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 572out:
573 if (put_mdev)
574 mlx5_ib_put_native_port_mdev(dev, port_num);
575 return err;
3f89a643
AS		 576}
577
095b0927
IT		 578static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
579 unsigned int index, const union ib_gid *gid,
580 const struct ib_gid_attr *attr)
3cca2606 581{
095b0927 582 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
a70c0739 583 u16 vlan_id = 0xffff;
095b0927
IT		 584 u8 roce_version = 0;
585 u8 roce_l3_type = 0;
095b0927 586 u8 mac[ETH_ALEN];
a70c0739 587 int ret;
095b0927
IT		 588
589 if (gid) {
590 gid_type = attr->gid_type;
a70c0739
PP		 591 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
592 if (ret)
593 return ret;
3cca2606
AS		 594 }
595
095b0927 596 switch (gid_type) {
3cca2606 597 case IB_GID_TYPE_IB:
095b0927 598 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 599 break;
600 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 601 roce_version = MLX5_ROCE_VERSION_2;
602 if (ipv6_addr_v4mapped((void *)gid))
603 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
604 else
605 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 606 break;
607
608 default:
095b0927 609 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 610 }
611
095b0927 612 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
cf34e1fe 613 roce_l3_type, gid->raw, mac,
a70c0739 614 vlan_id < VLAN_CFI_MASK, vlan_id,
cf34e1fe 615 port_num);
3cca2606
AS		 616}
617
f4df9a7c 618static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
3cca2606
AS		 619 __always_unused void **context)
620{
414448d2 621 return set_roce_addr(to_mdev(attr->device), attr->port_num,
f4df9a7c 622 attr->index, &attr->gid, attr);
3cca2606
AS		 623}
624
414448d2
PP		 625static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
626 __always_unused void **context)
3cca2606 627{
414448d2
PP		 628 return set_roce_addr(to_mdev(attr->device), attr->port_num,
629 attr->index, NULL, NULL);
3cca2606
AS		 630}
631
47ec3866
PP		 632__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
633 const struct ib_gid_attr *attr)
2811ba51 634{
47ec3866 635 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
2811ba51
AS		 636 return 0;
637
638 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
639}
640
1b5daf11
MD		 641static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
642{
7fae6655
NO		 643 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
644 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
645 return 0;
1b5daf11
MD		 646}
647
648enum {
649 MLX5_VPORT_ACCESS_METHOD_MAD,
650 MLX5_VPORT_ACCESS_METHOD_HCA,
651 MLX5_VPORT_ACCESS_METHOD_NIC,
652};
653
654static int mlx5_get_vport_access_method(struct ib_device *ibdev)
655{
656 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
657 return MLX5_VPORT_ACCESS_METHOD_MAD;
658
ebd61f68 659 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 660 IB_LINK_LAYER_ETHERNET)
661 return MLX5_VPORT_ACCESS_METHOD_NIC;
662
663 return MLX5_VPORT_ACCESS_METHOD_HCA;
664}
665
da7525d2 666static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 667 u8 atomic_size_qp,
da7525d2
EBE		 668 struct ib_device_attr *props)
669{
670 u8 tmp;
671 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 672 u8 atomic_req_8B_endianness_mode =
bd10838a 673 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 674
675 /* Check if HW supports 8 bytes standard atomic operations and capable
676 * of host endianness respond
677 */
678 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
679 if (((atomic_operations & tmp) == tmp) &&
680 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
681 (atomic_req_8B_endianness_mode)) {
682 props->atomic_cap = IB_ATOMIC_HCA;
683 } else {
684 props->atomic_cap = IB_ATOMIC_NONE;
685 }
686}
687
776a3906
MS		 688static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
689 struct ib_device_attr *props)
690{
691 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
692
693 get_atomic_caps(dev, atomic_size_qp, props);
694}
695
696static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
697 struct ib_device_attr *props)
698{
699 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
700
701 get_atomic_caps(dev, atomic_size_qp, props);
702}
703
704bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
705{
706 struct ib_device_attr props = {};
707
708 get_atomic_caps_dc(dev, &props);
709 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
710}
1b5daf11
MD		 711static int mlx5_query_system_image_guid(struct ib_device *ibdev,
712 __be64 *sys_image_guid)
713{
714 struct mlx5_ib_dev *dev = to_mdev(ibdev);
715 struct mlx5_core_dev *mdev = dev->mdev;
716 u64 tmp;
717 int err;
718
719 switch (mlx5_get_vport_access_method(ibdev)) {
720 case MLX5_VPORT_ACCESS_METHOD_MAD:
721 return mlx5_query_mad_ifc_system_image_guid(ibdev,
722 sys_image_guid);
723
724 case MLX5_VPORT_ACCESS_METHOD_HCA:
725 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 726 break;
727
728 case MLX5_VPORT_ACCESS_METHOD_NIC:
729 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
730 break;
1b5daf11
MD		 731
732 default:
733 return -EINVAL;
734 }
3f89a643
AS		 735
736 if (!err)
737 *sys_image_guid = cpu_to_be64(tmp);
738
739 return err;
740
1b5daf11
MD		 741}
742
743static int mlx5_query_max_pkeys(struct ib_device *ibdev,
744 u16 *max_pkeys)
745{
746 struct mlx5_ib_dev *dev = to_mdev(ibdev);
747 struct mlx5_core_dev *mdev = dev->mdev;
748
749 switch (mlx5_get_vport_access_method(ibdev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 case MLX5_VPORT_ACCESS_METHOD_NIC:
755 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
756 pkey_table_size));
757 return 0;
758
759 default:
760 return -EINVAL;
761 }
762}
763
764static int mlx5_query_vendor_id(struct ib_device *ibdev,
765 u32 *vendor_id)
766{
767 struct mlx5_ib_dev *dev = to_mdev(ibdev);
768
769 switch (mlx5_get_vport_access_method(ibdev)) {
770 case MLX5_VPORT_ACCESS_METHOD_MAD:
771 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
772
773 case MLX5_VPORT_ACCESS_METHOD_HCA:
774 case MLX5_VPORT_ACCESS_METHOD_NIC:
775 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
776
777 default:
778 return -EINVAL;
779 }
780}
781
782static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
783 __be64 *node_guid)
784{
785 u64 tmp;
786 int err;
787
788 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
789 case MLX5_VPORT_ACCESS_METHOD_MAD:
790 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
791
792 case MLX5_VPORT_ACCESS_METHOD_HCA:
793 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 794 break;
795
796 case MLX5_VPORT_ACCESS_METHOD_NIC:
797 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
798 break;
1b5daf11
MD		 799
800 default:
801 return -EINVAL;
802 }
3f89a643
AS		 803
804 if (!err)
805 *node_guid = cpu_to_be64(tmp);
806
807 return err;
1b5daf11
MD		 808}
809
810struct mlx5_reg_node_desc {
bd99fdea 811 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 812};
813
814static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
815{
816 struct mlx5_reg_node_desc in;
817
818 if (mlx5_use_mad_ifc(dev))
819 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
820
821 memset(&in, 0, sizeof(in));
822
823 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
824 sizeof(struct mlx5_reg_node_desc),
825 MLX5_REG_NODE_DESC, 0, 0);
826}
827
e126ba97 828static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 829 struct ib_device_attr *props,
830 struct ib_udata *uhw)
e126ba97 831{
759be092 832 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
e126ba97 833 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 834 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 835 int err = -ENOMEM;
288c01b7 836 int max_sq_desc;
e126ba97
EC		 837 int max_rq_sg;
838 int max_sq_sg;
e0238a6a 839 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 840 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 841 struct mlx5_ib_query_device_resp resp = {};
842 size_t resp_len;
843 u64 max_tso;
e126ba97 844
402ca536 845 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
759be092 846 if (uhw_outlen && uhw_outlen < resp_len)
402ca536
BW		 847 return -EINVAL;
848 else
849 resp.response_length = resp_len;
850
759be092 851 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 852 return -EINVAL;
853
1b5daf11
MD		 854 memset(props, 0, sizeof(*props));
855 err = mlx5_query_system_image_guid(ibdev,
856 &props->sys_image_guid);
857 if (err)
858 return err;
e126ba97 859
1b5daf11 860 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 861 if (err)
1b5daf11 862 return err;
e126ba97 863
1b5daf11
MD		 864 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
865 if (err)
866 return err;
e126ba97 867
9603b61d
JM		 868 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
869 (fw_rev_min(dev->mdev) << 16) |
870 fw_rev_sub(dev->mdev);
e126ba97
EC		 871 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
872 IB_DEVICE_PORT_ACTIVE_EVENT |
873 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 874 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 875
876 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 877 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 878 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 879 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 880 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 881 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 882 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 883 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 884 if (MLX5_CAP_GEN(mdev, imaicl)) {
885 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
886 IB_DEVICE_MEM_WINDOW_TYPE_2B;
887 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 888 /* We support 'Gappy' memory registration too */
889 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 890 }
c960e2a2
JG		 891 /* IB_WR_REG_MR always requires changing the entity size with UMR */
892 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
893 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 894 if (MLX5_CAP_GEN(mdev, sho)) {
c0a6cbb9 895 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
2dea9094
SG		 896 /* At this stage no support for signature handover */
897 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
898 IB_PROT_T10DIF_TYPE_2 |
899 IB_PROT_T10DIF_TYPE_3;
900 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
901 IB_GUARD_T10DIF_CSUM;
902 }
938fe83c 903 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 904 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 905
85c7c014 906 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 907 if (MLX5_CAP_ETH(mdev, csum_cap)) {
908 /* Legacy bit to support old userspace libraries */
88115fe7 909 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 910 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
911 }
912
913 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
914 props->raw_packet_caps |=
915 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 916
759be092 917 if (field_avail(typeof(resp), tso_caps, uhw_outlen)) {
402ca536
BW		 918 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
919 if (max_tso) {
920 resp.tso_caps.max_tso = 1 << max_tso;
921 resp.tso_caps.supported_qpts |=
922 1 << IB_QPT_RAW_PACKET;
923 resp.response_length += sizeof(resp.tso_caps);
924 }
925 }
31f69a82 926
759be092 927 if (field_avail(typeof(resp), rss_caps, uhw_outlen)) {
31f69a82
YH		 928 resp.rss_caps.rx_hash_function =
929 MLX5_RX_HASH_FUNC_TOEPLITZ;
930 resp.rss_caps.rx_hash_fields_mask =
931 MLX5_RX_HASH_SRC_IPV4 |
932 MLX5_RX_HASH_DST_IPV4 |
933 MLX5_RX_HASH_SRC_IPV6 |
934 MLX5_RX_HASH_DST_IPV6 |
935 MLX5_RX_HASH_SRC_PORT_TCP |
936 MLX5_RX_HASH_DST_PORT_TCP |
937 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 938 MLX5_RX_HASH_DST_PORT_UDP |
939 MLX5_RX_HASH_INNER;
2d93fc85
MB		 940 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
941 MLX5_ACCEL_IPSEC_CAP_DEVICE)
942 resp.rss_caps.rx_hash_fields_mask |=
943 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 944 resp.response_length += sizeof(resp.rss_caps);
945 }
946 } else {
759be092 947 if (field_avail(typeof(resp), tso_caps, uhw_outlen))
31f69a82 948 resp.response_length += sizeof(resp.tso_caps);
759be092 949 if (field_avail(typeof(resp), rss_caps, uhw_outlen))
31f69a82 950 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 951 }
952
f0313965
ES		 953 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
954 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
955 props->device_cap_flags |= IB_DEVICE_UD_TSO;
956 }
957
03404e8a 958 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 959 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
960 raw_support)
03404e8a
MG		 961 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
962
1d54f890
YH		 963 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
964 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
965 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
966
cff5a0f3 967 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 968 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
969 raw_support) {
e8161334 970 /* Legacy bit to support old userspace libraries */
cff5a0f3 971 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 972 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
973 }
cff5a0f3 974
24da0016
AL		 975 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
976 props->max_dm_size =
977 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
978 }
979
da6d6ba3
MG		 980 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
981 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
982
b1383aa6
NO		 983 if (MLX5_CAP_GEN(mdev, end_pad))
984 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
985
1b5daf11
MD		 986 props->vendor_part_id = mdev->pdev->device;
987 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 988
989 props->max_mr_size = ~0ull;
e0238a6a 990 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 991 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
992 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
993 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
994 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 995 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
996 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
997 sizeof(struct mlx5_wqe_raddr_seg)) /
998 sizeof(struct mlx5_wqe_data_seg);
33023fb8
SW		 999 props->max_send_sge = max_sq_sg;
1000 props->max_recv_sge = max_rq_sg;
986ef95e 1001 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 1002 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 1003 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 1004 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1005 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1006 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1007 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1008 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1009 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1010 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 1011 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 1012 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 1013 props->max_fast_reg_page_list_len =
1014 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
62e3c379
MG		 1015 props->max_pi_fast_reg_page_list_len =
1016 props->max_fast_reg_page_list_len / 2;
776a3906 1017 get_atomic_caps_qp(dev, props);
81bea28f 1018 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 1019 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1020 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 1021 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1022 props->max_mcast_grp;
1023 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 1024 props->max_ah = INT_MAX;
7c60bcbb
MB		 1025 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1026 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 1027
e502b8b0 1028 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
00815752 1029 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
e502b8b0
LR		 1030 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1031 props->odp_caps = dev->odp_caps;
1032 }
8cdd312c 1033
051f2630
LR		 1034 if (MLX5_CAP_GEN(mdev, cd))
1035 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1036
eff901d3
EC		 1037 if (!mlx5_core_is_pf(mdev))
1038 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1039
31f69a82 1040 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 1041 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 1042 props->rss_caps.max_rwq_indirection_tables =
1043 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1044 props->rss_caps.max_rwq_indirection_table_size =
1045 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1046 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1047 props->max_wq_type_rq =
1048 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1049 }
1050
eb761894 1051 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0 1052 props->tm_caps.max_num_tags =
eb761894 1053 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0 1054 props->tm_caps.max_ops =
eb761894 1055 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 1056 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 1057 }
1058
89705e92
DG		 1059 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1060 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1061 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1062 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1063 }
1064
87ab3f52
YC		 1065 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1066 props->cq_caps.max_cq_moderation_count =
1067 MLX5_MAX_CQ_COUNT;
1068 props->cq_caps.max_cq_moderation_period =
1069 MLX5_MAX_CQ_PERIOD;
1070 }
1071
759be092 1072 if (field_avail(typeof(resp), cqe_comp_caps, uhw_outlen)) {
7e43a2a5 1073 resp.response_length += sizeof(resp.cqe_comp_caps);
572f46bf
YC		 1074
1075 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1076 resp.cqe_comp_caps.max_num =
1077 MLX5_CAP_GEN(dev->mdev,
1078 cqe_compression_max_num);
1079
1080 resp.cqe_comp_caps.supported_format =
1081 MLX5_IB_CQE_RES_FORMAT_HASH |
1082 MLX5_IB_CQE_RES_FORMAT_CSUM;
6f1006a4
YC		 1083
1084 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1085 resp.cqe_comp_caps.supported_format |=
1086 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
572f46bf 1087 }
7e43a2a5
BW		 1088 }
1089
759be092 1090 if (field_avail(typeof(resp), packet_pacing_caps, uhw_outlen) &&
85c7c014 1091 raw_support) {
d949167d
BW		 1092 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1093 MLX5_CAP_GEN(mdev, qos)) {
1094 resp.packet_pacing_caps.qp_rate_limit_max =
1095 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1096 resp.packet_pacing_caps.qp_rate_limit_min =
1097 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1098 resp.packet_pacing_caps.supported_qpts |=
1099 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1100 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1101 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1102 resp.packet_pacing_caps.cap_flags |=
1103 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1104 }
1105 resp.response_length += sizeof(resp.packet_pacing_caps);
1106 }
1107
9f885201 1108 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
759be092 1109 uhw_outlen)) {
795b609c
BW		 1110 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1111 resp.mlx5_ib_support_multi_pkt_send_wqes =
1112 MLX5_IB_ALLOW_MPW;
050da902
BW		 1113
1114 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1115 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1116 MLX5_IB_SUPPORT_EMPW;
1117
9f885201
LR		 1118 resp.response_length +=
1119 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1120 }
1121
759be092 1122 if (field_avail(typeof(resp), flags, uhw_outlen)) {
de57f2ad 1123 resp.response_length += sizeof(resp.flags);
7a0c8f42 1124
de57f2ad
GL		 1125 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1126 resp.flags |=
1127 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1128
1129 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1130 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
7e11b911
DG		 1131 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1132 resp.flags |=
1133 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
7249c8ea
GL		 1134
1135 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
de57f2ad 1136 }
9f885201 1137
759be092 1138 if (field_avail(typeof(resp), sw_parsing_caps, uhw_outlen)) {
96dc3fc5
NO		 1139 resp.response_length += sizeof(resp.sw_parsing_caps);
1140 if (MLX5_CAP_ETH(mdev, swp)) {
1141 resp.sw_parsing_caps.sw_parsing_offloads |=
1142 MLX5_IB_SW_PARSING;
1143
1144 if (MLX5_CAP_ETH(mdev, swp_csum))
1145 resp.sw_parsing_caps.sw_parsing_offloads |=
1146 MLX5_IB_SW_PARSING_CSUM;
1147
1148 if (MLX5_CAP_ETH(mdev, swp_lso))
1149 resp.sw_parsing_caps.sw_parsing_offloads |=
1150 MLX5_IB_SW_PARSING_LSO;
1151
1152 if (resp.sw_parsing_caps.sw_parsing_offloads)
1153 resp.sw_parsing_caps.supported_qpts =
1154 BIT(IB_QPT_RAW_PACKET);
1155 }
1156 }
1157
759be092 1158 if (field_avail(typeof(resp), striding_rq_caps, uhw_outlen) &&
85c7c014 1159 raw_support) {
b4f34597
NO		 1160 resp.response_length += sizeof(resp.striding_rq_caps);
1161 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1162 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1163 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1165 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1166 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1167 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1168 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1169 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1170 resp.striding_rq_caps.supported_qpts =
1171 BIT(IB_QPT_RAW_PACKET);
1172 }
1173 }
1174
759be092 1175 if (field_avail(typeof(resp), tunnel_offloads_caps, uhw_outlen)) {
f95ef6cb
MG		 1176 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1177 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1178 resp.tunnel_offloads_caps |=
1179 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1180 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1181 resp.tunnel_offloads_caps |=
1182 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1183 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1184 resp.tunnel_offloads_caps |=
1185 MLX5_IB_TUNNELED_OFFLOADS_GRE;
c4becfff 1186 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
e818e255
AL		 1187 resp.tunnel_offloads_caps |=
1188 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
c4becfff 1189 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
e818e255
AL		 1190 resp.tunnel_offloads_caps |=
1191 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
f95ef6cb
MG		 1192 }
1193
759be092 1194 if (uhw_outlen) {
402ca536
BW		 1195 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1196
1197 if (err)
1198 return err;
1199 }
1200
1b5daf11 1201 return 0;
e126ba97
EC		 1202}
1203
1b5daf11
MD		 1204enum mlx5_ib_width {
1205 MLX5_IB_WIDTH_1X = 1 << 0,
1206 MLX5_IB_WIDTH_2X = 1 << 1,
1207 MLX5_IB_WIDTH_4X = 1 << 2,
1208 MLX5_IB_WIDTH_8X = 1 << 3,
1209 MLX5_IB_WIDTH_12X = 1 << 4
1210};
1211
db7a691a 1212static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1b5daf11 1213 u8 *ib_width)
e126ba97
EC		 1214{
1215 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11 1216
db7a691a 1217 if (active_width & MLX5_IB_WIDTH_1X)
1b5daf11 1218 *ib_width = IB_WIDTH_1X;
d764970b
MG		 1219 else if (active_width & MLX5_IB_WIDTH_2X)
1220 *ib_width = IB_WIDTH_2X;
db7a691a 1221 else if (active_width & MLX5_IB_WIDTH_4X)
1b5daf11 1222 *ib_width = IB_WIDTH_4X;
db7a691a 1223 else if (active_width & MLX5_IB_WIDTH_8X)
1b5daf11 1224 *ib_width = IB_WIDTH_8X;
db7a691a 1225 else if (active_width & MLX5_IB_WIDTH_12X)
1b5daf11 1226 *ib_width = IB_WIDTH_12X;
db7a691a
MG		 1227 else {
1228 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1b5daf11 1229 (int)active_width);
db7a691a 1230 *ib_width = IB_WIDTH_4X;
e126ba97
EC		 1231 }
1232
db7a691a 1233 return;
1b5daf11 1234}
e126ba97 1235
1b5daf11
MD		 1236static int mlx5_mtu_to_ib_mtu(int mtu)
1237{
1238 switch (mtu) {
1239 case 256: return 1;
1240 case 512: return 2;
1241 case 1024: return 3;
1242 case 2048: return 4;
1243 case 4096: return 5;
1244 default:
1245 pr_warn("invalid mtu\n");
1246 return -1;
e126ba97 1247 }
1b5daf11 1248}
e126ba97 1249
1b5daf11
MD		 1250enum ib_max_vl_num {
1251 __IB_MAX_VL_0 = 1,
1252 __IB_MAX_VL_0_1 = 2,
1253 __IB_MAX_VL_0_3 = 3,
1254 __IB_MAX_VL_0_7 = 4,
1255 __IB_MAX_VL_0_14 = 5,
1256};
e126ba97 1257
1b5daf11
MD		 1258enum mlx5_vl_hw_cap {
1259 MLX5_VL_HW_0 = 1,
1260 MLX5_VL_HW_0_1 = 2,
1261 MLX5_VL_HW_0_2 = 3,
1262 MLX5_VL_HW_0_3 = 4,
1263 MLX5_VL_HW_0_4 = 5,
1264 MLX5_VL_HW_0_5 = 6,
1265 MLX5_VL_HW_0_6 = 7,
1266 MLX5_VL_HW_0_7 = 8,
1267 MLX5_VL_HW_0_14 = 15
1268};
e126ba97 1269
1b5daf11
MD		 1270static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1271 u8 *max_vl_num)
1272{
1273 switch (vl_hw_cap) {
1274 case MLX5_VL_HW_0:
1275 *max_vl_num = __IB_MAX_VL_0;
1276 break;
1277 case MLX5_VL_HW_0_1:
1278 *max_vl_num = __IB_MAX_VL_0_1;
1279 break;
1280 case MLX5_VL_HW_0_3:
1281 *max_vl_num = __IB_MAX_VL_0_3;
1282 break;
1283 case MLX5_VL_HW_0_7:
1284 *max_vl_num = __IB_MAX_VL_0_7;
1285 break;
1286 case MLX5_VL_HW_0_14:
1287 *max_vl_num = __IB_MAX_VL_0_14;
1288 break;
e126ba97 1289
1b5daf11
MD		 1290 default:
1291 return -EINVAL;
e126ba97 1292 }
e126ba97 1293
1b5daf11 1294 return 0;
e126ba97
EC		 1295}
1296
1b5daf11
MD		 1297static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1298 struct ib_port_attr *props)
e126ba97 1299{
1b5daf11
MD		 1300 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1301 struct mlx5_core_dev *mdev = dev->mdev;
1302 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1303 u16 max_mtu;
1304 u16 oper_mtu;
1b5daf11
MD		 1305 int err;
1306 u8 ib_link_width_oper;
1307 u8 vl_hw_cap;
e126ba97 1308
1b5daf11
MD		 1309 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1310 if (!rep) {
1311 err = -ENOMEM;
e126ba97 1312 goto out;
e126ba97 1313 }
e126ba97 1314
c4550c63 1315 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1316
1b5daf11 1317 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1318 if (err)
1319 goto out;
1320
1b5daf11
MD		 1321 props->lid = rep->lid;
1322 props->lmc = rep->lmc;
1323 props->sm_lid = rep->sm_lid;
1324 props->sm_sl = rep->sm_sl;
1325 props->state = rep->vport_state;
1326 props->phys_state = rep->port_physical_state;
1327 props->port_cap_flags = rep->cap_mask1;
1328 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1329 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1330 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1331 props->bad_pkey_cntr = rep->pkey_violation_counter;
1332 props->qkey_viol_cntr = rep->qkey_violation_counter;
1333 props->subnet_timeout = rep->subnet_timeout;
1334 props->init_type_reply = rep->init_type_reply;
e126ba97 1335
4106a758
MG		 1336 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1337 props->port_cap_flags2 = rep->cap_mask2;
1338
1b5daf11
MD		 1339 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1340 if (err)
e126ba97 1341 goto out;
e126ba97 1342
db7a691a
MG		 1343 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1344
d5beb7f2 1345 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1346 if (err)
1347 goto out;
1348
facc9699 1349 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1350
1b5daf11 1351 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1352
facc9699 1353 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1354
1b5daf11 1355 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1356
1b5daf11
MD		 1357 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1358 if (err)
1359 goto out;
e126ba97 1360
1b5daf11
MD		 1361 err = translate_max_vl_num(ibdev, vl_hw_cap,
1362 &props->max_vl_num);
e126ba97 1363out:
1b5daf11 1364 kfree(rep);
e126ba97
EC		 1365 return err;
1366}
1367
1b5daf11
MD		 1368int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1369 struct ib_port_attr *props)
e126ba97 1370{
095b0927
IT		 1371 unsigned int count;
1372 int ret;
1373
1b5daf11
MD		 1374 switch (mlx5_get_vport_access_method(ibdev)) {
1375 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1376 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1377 break;
e126ba97 1378
1b5daf11 1379 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1380 ret = mlx5_query_hca_port(ibdev, port, props);
1381 break;
e126ba97 1382
3f89a643 1383 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1384 ret = mlx5_query_port_roce(ibdev, port, props);
1385 break;
3f89a643 1386
1b5daf11 1387 default:
095b0927
IT		 1388 ret = -EINVAL;
1389 }
1390
1391 if (!ret && props) {
b3cbd6f0
DJ		 1392 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1393 struct mlx5_core_dev *mdev;
1394 bool put_mdev = true;
1395
1396 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1397 if (!mdev) {
1398 /* If the port isn't affiliated yet query the master.
1399 * The master and slave will have the same values.
1400 */
1401 mdev = dev->mdev;
1402 port = 1;
1403 put_mdev = false;
1404 }
1405 count = mlx5_core_reserved_gids_count(mdev);
1406 if (put_mdev)
1407 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1408 props->gid_tbl_len -= count;
1b5daf11 1409 }
095b0927 1410 return ret;
1b5daf11 1411}
e126ba97 1412
8e6efa3a
MB		 1413static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1414 struct ib_port_attr *props)
1415{
1416 int ret;
1417
26628e2d
MB		 1418 /* Only link layer == ethernet is valid for representors
1419 * and we always use port 1
1420 */
8e6efa3a
MB		 1421 ret = mlx5_query_port_roce(ibdev, port, props);
1422 if (ret || !props)
1423 return ret;
1424
1425 /* We don't support GIDS */
1426 props->gid_tbl_len = 0;
1427
1428 return ret;
1429}
1430
1b5daf11
MD		 1431static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1432 union ib_gid *gid)
1433{
1434 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1435 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1436
1b5daf11
MD		 1437 switch (mlx5_get_vport_access_method(ibdev)) {
1438 case MLX5_VPORT_ACCESS_METHOD_MAD:
1439 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1440
1b5daf11
MD		 1441 case MLX5_VPORT_ACCESS_METHOD_HCA:
1442 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1443
1444 default:
1445 return -EINVAL;
1446 }
e126ba97 1447
e126ba97
EC		 1448}
1449
b3cbd6f0
DJ		 1450static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1451 u16 index, u16 *pkey)
1b5daf11
MD		 1452{
1453 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1454 struct mlx5_core_dev *mdev;
1455 bool put_mdev = true;
1456 u8 mdev_port_num;
1457 int err;
1b5daf11 1458
b3cbd6f0
DJ		 1459 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1460 if (!mdev) {
1461 /* The port isn't affiliated yet, get the PKey from the master
1462 * port. For RoCE the PKey tables will be the same.
1463 */
1464 put_mdev = false;
1465 mdev = dev->mdev;
1466 mdev_port_num = 1;
1467 }
1468
1469 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1470 index, pkey);
1471 if (put_mdev)
1472 mlx5_ib_put_native_port_mdev(dev, port);
1473
1474 return err;
1475}
1476
1477static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1478 u16 *pkey)
1479{
1b5daf11
MD		 1480 switch (mlx5_get_vport_access_method(ibdev)) {
1481 case MLX5_VPORT_ACCESS_METHOD_MAD:
1482 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1483
1484 case MLX5_VPORT_ACCESS_METHOD_HCA:
1485 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1486 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1487 default:
1488 return -EINVAL;
1489 }
1490}
e126ba97
EC		 1491
1492static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1493 struct ib_device_modify *props)
1494{
1495 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1496 struct mlx5_reg_node_desc in;
1497 struct mlx5_reg_node_desc out;
1498 int err;
1499
1500 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1501 return -EOPNOTSUPP;
1502
1503 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1504 return 0;
1505
1506 /*
1507 * If possible, pass node desc to FW, so it can generate
1508 * a 144 trap. If cmd fails, just ignore.
1509 */
bd99fdea 1510 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1511 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1512 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1513 if (err)
1514 return err;
1515
bd99fdea 1516 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1517
1518 return err;
1519}
1520
cdbe33d0
EC		 1521static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1522 u32 value)
1523{
1524 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1525 struct mlx5_core_dev *mdev;
1526 u8 mdev_port_num;
cdbe33d0
EC		 1527 int err;
1528
b3cbd6f0
DJ		 1529 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1530 if (!mdev)
1531 return -ENODEV;
1532
1533 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1534 if (err)
b3cbd6f0 1535 goto out;
cdbe33d0
EC		 1536
1537 if (~ctx.cap_mask1_perm & mask) {
1538 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1539 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1540 err = -EINVAL;
1541 goto out;
cdbe33d0
EC		 1542 }
1543
1544 ctx.cap_mask1 = value;
1545 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1546 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1547 0, &ctx);
1548
1549out:
1550 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1551
1552 return err;
1553}
1554
e126ba97
EC		 1555static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1556 struct ib_port_modify *props)
1557{
1558 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1559 struct ib_port_attr attr;
1560 u32 tmp;
1561 int err;
cdbe33d0
EC		 1562 u32 change_mask;
1563 u32 value;
1564 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1565 IB_LINK_LAYER_INFINIBAND);
1566
ec255879
MD		 1567 /* CM layer calls ib_modify_port() regardless of the link layer. For
1568 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1569 */
1570 if (!is_ib)
1571 return 0;
1572
cdbe33d0
EC		 1573 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1574 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1575 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1576 return set_port_caps_atomic(dev, port, change_mask, value);
1577 }
e126ba97
EC		 1578
1579 mutex_lock(&dev->cap_mask_mutex);
1580
c4550c63 1581 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1582 if (err)
1583 goto out;
1584
1585 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1586 ~props->clr_port_cap_mask;
1587
9603b61d 1588 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1589
1590out:
1591 mutex_unlock(&dev->cap_mask_mutex);
1592 return err;
1593}
1594
30aa60b3
EC		 1595static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1596{
1597 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1598 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1599}
1600
31a78a5a
YH		 1601static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1602{
1603 /* Large page with non 4k uar support might limit the dynamic size */
1604 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1605 return MLX5_MIN_DYN_BFREGS;
1606
1607 return MLX5_MAX_DYN_BFREGS;
1608}
1609
b037c29a
EC		 1610static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1611 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1612 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1613{
1614 int uars_per_sys_page;
1615 int bfregs_per_sys_page;
1616 int ref_bfregs = req->total_num_bfregs;
1617
1618 if (req->total_num_bfregs == 0)
1619 return -EINVAL;
1620
1621 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1622 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1623
1624 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1625 return -ENOMEM;
1626
1627 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1628 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1629 /* This holds the required static allocation asked by the user */
b037c29a 1630 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1631 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1632 return -EINVAL;
1633
31a78a5a
YH		 1634 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1635 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1636 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1637 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1638
1639 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1640 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1641 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1642 req->total_num_bfregs, bfregi->total_num_bfregs,
1643 bfregi->num_sys_pages);
b037c29a
EC		 1644
1645 return 0;
1646}
1647
1648static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1649{
1650 struct mlx5_bfreg_info *bfregi;
1651 int err;
1652 int i;
1653
1654 bfregi = &context->bfregi;
31a78a5a 1655 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1656 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1657 if (err)
1658 goto error;
1659
1660 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1661 }
4ed131d0
YH		 1662
1663 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1664 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1665
b037c29a
EC		 1666 return 0;
1667
1668error:
1669 for (--i; i >= 0; i--)
1670 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1671 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1672
1673 return err;
1674}
1675
15177999
LR		 1676static void deallocate_uars(struct mlx5_ib_dev *dev,
1677 struct mlx5_ib_ucontext *context)
b037c29a
EC		 1678{
1679 struct mlx5_bfreg_info *bfregi;
b037c29a
EC		 1680 int i;
1681
1682 bfregi = &context->bfregi;
15177999 1683 for (i = 0; i < bfregi->num_sys_pages; i++)
4ed131d0 1684 if (i < bfregi->num_static_sys_pages ||
15177999
LR		 1685 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1686 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
b037c29a
EC		 1687}
1688
0042f9e4 1689int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1690{
1691 int err = 0;
1692
1693 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1694 if (td)
1695 dev->lb.user_td++;
1696 if (qp)
1697 dev->lb.qps++;
1698
1699 if (dev->lb.user_td == 2 ||
1700 dev->lb.qps == 1) {
1701 if (!dev->lb.enabled) {
1702 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1703 dev->lb.enabled = true;
1704 }
1705 }
a560f1d9
MB		 1706
1707 mutex_unlock(&dev->lb.mutex);
1708
1709 return err;
1710}
1711
0042f9e4 1712void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
a560f1d9
MB		 1713{
1714 mutex_lock(&dev->lb.mutex);
0042f9e4
MB		 1715 if (td)
1716 dev->lb.user_td--;
1717 if (qp)
1718 dev->lb.qps--;
1719
1720 if (dev->lb.user_td == 1 &&
1721 dev->lb.qps == 0) {
1722 if (dev->lb.enabled) {
1723 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1724 dev->lb.enabled = false;
1725 }
1726 }
a560f1d9
MB		 1727
1728 mutex_unlock(&dev->lb.mutex);
1729}
1730
d2d19121
YH		 1731static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1732 u16 uid)
c85023e1
HN		 1733{
1734 int err;
1735
cfdeb893
LR		 1736 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1737 return 0;
1738
d2d19121 1739 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1740 if (err)
1741 return err;
1742
1743 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1744 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1745 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1746 return err;
1747
0042f9e4 1748 return mlx5_ib_enable_lb(dev, true, false);
c85023e1
HN		 1749}
1750
d2d19121
YH		 1751static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1752 u16 uid)
c85023e1 1753{
cfdeb893
LR		 1754 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1755 return;
1756
d2d19121 1757 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
c85023e1
HN		 1758
1759 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1760 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1761 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1762 return;
1763
0042f9e4 1764 mlx5_ib_disable_lb(dev, true, false);
c85023e1
HN		 1765}
1766
a2a074ef
LR		 1767static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1768 struct ib_udata *udata)
e126ba97 1769{
a2a074ef 1770 struct ib_device *ibdev = uctx->device;
e126ba97 1771 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1772 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1773 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1774 struct mlx5_core_dev *mdev = dev->mdev;
a2a074ef 1775 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
2f5ff264 1776 struct mlx5_bfreg_info *bfregi;
78c0f98c 1777 int ver;
e126ba97 1778 int err;
a168a41c
MD		 1779 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1780 max_cqe_version);
25bb36e7 1781 u32 dump_fill_mkey;
b037c29a 1782 bool lib_uar_4k;
e126ba97
EC		 1783
1784 if (!dev->ib_active)
a2a074ef 1785 return -EAGAIN;
e126ba97 1786
e093111d 1787 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1788 ver = 0;
e093111d 1789 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1790 ver = 2;
1791 else
a2a074ef 1792 return -EINVAL;
78c0f98c 1793
e093111d 1794 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97 1795 if (err)
a2a074ef 1796 return err;
e126ba97 1797
a8b92ca1 1798 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
a2a074ef 1799 return -EOPNOTSUPP;
78c0f98c 1800
f72300c5 1801 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
a2a074ef 1802 return -EOPNOTSUPP;
b368d7cb 1803
2f5ff264
EC		 1804 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1805 MLX5_NON_FP_BFREGS_PER_UAR);
1806 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
a2a074ef 1807 return -EINVAL;
e126ba97 1808
938fe83c 1809 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1810 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1811 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1812 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1813 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1814 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1815 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1816 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1817 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1818 resp.cqe_version = min_t(__u8,
1819 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1820 req.max_cqe_version);
30aa60b3
EC		 1821 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1822 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1823 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1824 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1825 resp.response_length = min(offsetof(typeof(resp), response_length) +
1826 sizeof(resp.response_length), udata->outlen);
e126ba97 1827
c03faa56
MB		 1828 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1829 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1830 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1831 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1832 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1833 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1834 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1835 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1836 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1837 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1838 }
1839
30aa60b3 1840 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1841 bfregi = &context->bfregi;
b037c29a
EC		 1842
1843 /* updates req->total_num_bfregs */
31a78a5a 1844 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1845 if (err)
e126ba97 1846 goto out_ctx;
e126ba97 1847
b037c29a
EC		 1848 mutex_init(&bfregi->lock);
1849 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1850 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1851 GFP_KERNEL);
b037c29a 1852 if (!bfregi->count) {
e126ba97 1853 err = -ENOMEM;
b037c29a 1854 goto out_ctx;
e126ba97
EC		 1855 }
1856
b037c29a
EC		 1857 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1858 sizeof(*bfregi->sys_pages),
1859 GFP_KERNEL);
1860 if (!bfregi->sys_pages) {
e126ba97 1861 err = -ENOMEM;
b037c29a 1862 goto out_count;
e126ba97
EC		 1863 }
1864
b037c29a
EC		 1865 err = allocate_uars(dev, context);
1866 if (err)
1867 goto out_sys_pages;
e126ba97 1868
a8b92ca1 1869 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
fb98153b 1870 err = mlx5_ib_devx_create(dev, true);
76dc5a84 1871 if (err < 0)
d2d19121 1872 goto out_uars;
76dc5a84 1873 context->devx_uid = err;
a8b92ca1
YH		 1874 }
1875
d2d19121
YH		 1876 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1877 context->devx_uid);
1878 if (err)
1879 goto out_devx;
1880
25bb36e7
YC		 1881 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1882 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1883 if (err)
8193abb6 1884 goto out_mdev;
25bb36e7
YC		 1885 }
1886
e126ba97
EC		 1887 INIT_LIST_HEAD(&context->db_page_list);
1888 mutex_init(&context->db_page_mutex);
1889
2f5ff264 1890 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1891 resp.num_ports = dev->num_ports;
b368d7cb 1892
f72300c5
HA		 1893 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1894 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1895
402ca536 1896 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1897 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1898 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1899 resp.response_length += sizeof(resp.cmds_supp_uhw);
1900 }
1901
78984898
OG		 1902 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1903 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1904 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1905 resp.eth_min_inline++;
1906 }
1907 resp.response_length += sizeof(resp.eth_min_inline);
1908 }
1909
5c99eaec
FD		 1910 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1911 if (mdev->clock_info)
1912 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1913 resp.response_length += sizeof(resp.clock_info_versions);
1914 }
1915
bc5c6eed
NO		 1916 /*
1917 * We don't want to expose information from the PCI bar that is located
1918 * after 4096 bytes, so if the arch only supports larger pages, let's
1919 * pretend we don't support reading the HCA's core clock. This is also
1920 * forced by mmap function.
1921 */
de8d6e02
EC		 1922 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1923 if (PAGE_SIZE <= 4096) {
1924 resp.comp_mask |=
1925 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1926 resp.hca_core_clock_offset =
1927 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1928 }
5c99eaec 1929 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1930 }
1931
30aa60b3
EC		 1932 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1933 resp.response_length += sizeof(resp.log_uar_size);
1934
1935 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1936 resp.response_length += sizeof(resp.num_uars_per_page);
1937
31a78a5a
YH		 1938 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1939 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1940 resp.response_length += sizeof(resp.num_dyn_bfregs);
1941 }
1942
25bb36e7
YC		 1943 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1944 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1945 resp.dump_fill_mkey = dump_fill_mkey;
1946 resp.comp_mask |=
1947 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1948 }
1949 resp.response_length += sizeof(resp.dump_fill_mkey);
1950 }
1951
b368d7cb 1952 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1953 if (err)
a8b92ca1 1954 goto out_mdev;
e126ba97 1955
2f5ff264
EC		 1956 bfregi->ver = ver;
1957 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1958 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1959 context->lib_caps = req.lib_caps;
1960 print_lib_caps(dev, context->lib_caps);
f72300c5 1961
7c34ec19 1962 if (dev->lag_active) {
95579e78 1963 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
c6a21c38
MD		 1964
1965 atomic_set(&context->tx_port_affinity,
1966 atomic_add_return(
95579e78 1967 1, &dev->port[port].roce.tx_port_affinity));
c6a21c38
MD		 1968 }
1969
a2a074ef 1970 return 0;
e126ba97 1971
a8b92ca1 1972out_mdev:
d2d19121
YH		 1973 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1974out_devx:
a8b92ca1 1975 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
76dc5a84 1976 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 1977
e126ba97 1978out_uars:
b037c29a 1979 deallocate_uars(dev, context);
e126ba97 1980
b037c29a
EC		 1981out_sys_pages:
1982 kfree(bfregi->sys_pages);
e126ba97 1983
b037c29a
EC		 1984out_count:
1985 kfree(bfregi->count);
e126ba97
EC		 1986
1987out_ctx:
a2a074ef 1988 return err;
e126ba97
EC		 1989}
1990
a2a074ef 1991static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
e126ba97
EC		 1992{
1993 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1994 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1995 struct mlx5_bfreg_info *bfregi;
e126ba97 1996
b037c29a 1997 bfregi = &context->bfregi;
d2d19121
YH		 1998 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1999
a8b92ca1 2000 if (context->devx_uid)
76dc5a84 2001 mlx5_ib_devx_destroy(dev, context->devx_uid);
146d2f1a 2002
b037c29a
EC		 2003 deallocate_uars(dev, context);
2004 kfree(bfregi->sys_pages);
2f5ff264 2005 kfree(bfregi->count);
e126ba97
EC		 2006}
2007
b037c29a 2008static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 2009 int uar_idx)
e126ba97 2010{
b037c29a
EC		 2011 int fw_uars_per_page;
2012
2013 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2014
aa8106f1 2015 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 2016}
2017
2018static int get_command(unsigned long offset)
2019{
2020 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2021}
2022
2023static int get_arg(unsigned long offset)
2024{
2025 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2026}
2027
2028static int get_index(unsigned long offset)
2029{
2030 return get_arg(offset);
2031}
2032
4ed131d0
YH		 2033/* Index resides in an extra byte to enable larger values than 255 */
2034static int get_extended_index(unsigned long offset)
2035{
2036 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2037}
2038
7c2344c3
MG		 2039
2040static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2041{
7c2344c3
MG		 2042}
2043
37aa5c36
GL		 2044static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2045{
2046 switch (cmd) {
2047 case MLX5_IB_MMAP_WC_PAGE:
2048 return "WC";
2049 case MLX5_IB_MMAP_REGULAR_PAGE:
2050 return "best effort WC";
2051 case MLX5_IB_MMAP_NC_PAGE:
2052 return "NC";
24da0016
AL		 2053 case MLX5_IB_MMAP_DEVICE_MEM:
2054 return "Device Memory";
37aa5c36
GL		 2055 default:
2056 return NULL;
2057 }
2058}
2059
5c99eaec
FD		 2060static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2061 struct vm_area_struct *vma,
2062 struct mlx5_ib_ucontext *context)
2063{
4eb6ab13
JG		 2064 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2065 !(vma->vm_flags & VM_SHARED))
5c99eaec
FD		 2066 return -EINVAL;
2067
2068 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2069 return -EOPNOTSUPP;
2070
4eb6ab13 2071 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
5c99eaec 2072 return -EPERM;
c660133c 2073 vma->vm_flags &= ~VM_MAYWRITE;
5c99eaec 2074
ddcdc368 2075 if (!dev->mdev->clock_info)
5c99eaec
FD		 2076 return -EOPNOTSUPP;
2077
4eb6ab13
JG		 2078 return vm_insert_page(vma, vma->vm_start,
2079 virt_to_page(dev->mdev->clock_info));
5c99eaec
FD		 2080}
2081
37aa5c36 2082static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2083 struct vm_area_struct *vma,
2084 struct mlx5_ib_ucontext *context)
37aa5c36 2085{
2f5ff264 2086 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2087 int err;
2088 unsigned long idx;
aa09ea6e 2089 phys_addr_t pfn;
37aa5c36 2090 pgprot_t prot;
4ed131d0
YH		 2091 u32 bfreg_dyn_idx = 0;
2092 u32 uar_index;
2093 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2094 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2095 bfregi->num_static_sys_pages;
b037c29a
EC		 2096
2097 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2098 return -EINVAL;
2099
4ed131d0
YH		 2100 if (dyn_uar)
2101 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2102 else
2103 idx = get_index(vma->vm_pgoff);
2104
2105 if (idx >= max_valid_idx) {
2106 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2107 idx, max_valid_idx);
b037c29a
EC		 2108 return -EINVAL;
2109 }
37aa5c36
GL		 2110
2111 switch (cmd) {
2112 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2113 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2114/* Some architectures don't support WC memory */
2115#if defined(CONFIG_X86)
2116 if (!pat_enabled())
2117 return -EPERM;
2118#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2119 return -EPERM;
2120#endif
2121 /* fall through */
2122 case MLX5_IB_MMAP_REGULAR_PAGE:
2123 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2124 prot = pgprot_writecombine(vma->vm_page_prot);
2125 break;
2126 case MLX5_IB_MMAP_NC_PAGE:
2127 prot = pgprot_noncached(vma->vm_page_prot);
2128 break;
2129 default:
2130 return -EINVAL;
2131 }
2132
4ed131d0
YH		 2133 if (dyn_uar) {
2134 int uars_per_page;
2135
2136 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2137 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2138 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2139 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2140 bfreg_dyn_idx, bfregi->total_num_bfregs);
2141 return -EINVAL;
2142 }
2143
2144 mutex_lock(&bfregi->lock);
2145 /* Fail if uar already allocated, first bfreg index of each
2146 * page holds its count.
2147 */
2148 if (bfregi->count[bfreg_dyn_idx]) {
2149 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2150 mutex_unlock(&bfregi->lock);
2151 return -EINVAL;
2152 }
2153
2154 bfregi->count[bfreg_dyn_idx]++;
2155 mutex_unlock(&bfregi->lock);
2156
2157 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2158 if (err) {
2159 mlx5_ib_warn(dev, "UAR alloc failed\n");
2160 goto free_bfreg;
2161 }
2162 } else {
2163 uar_index = bfregi->sys_pages[idx];
2164 }
2165
2166 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2167 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2168
e2cd1d1a 2169 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
6d984a87 2170 prot, NULL);
37aa5c36 2171 if (err) {
8f062287 2172 mlx5_ib_err(dev,
e2cd1d1a 2173 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
8f062287 2174 err, mmap_cmd2str(cmd));
4ed131d0 2175 goto err;
37aa5c36
GL		 2176 }
2177
4ed131d0
YH		 2178 if (dyn_uar)
2179 bfregi->sys_pages[idx] = uar_index;
2180 return 0;
2181
2182err:
2183 if (!dyn_uar)
2184 return err;
2185
2186 mlx5_cmd_free_uar(dev->mdev, idx);
2187
2188free_bfreg:
2189 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2190
2191 return err;
37aa5c36
GL		 2192}
2193
24da0016
AL		 2194static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2195{
2196 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2197 struct mlx5_ib_dev *dev = to_mdev(context->device);
2198 u16 page_idx = get_extended_index(vma->vm_pgoff);
2199 size_t map_size = vma->vm_end - vma->vm_start;
2200 u32 npages = map_size >> PAGE_SHIFT;
2201 phys_addr_t pfn;
24da0016
AL		 2202
2203 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2204 page_idx + npages)
2205 return -EINVAL;
2206
aa8106f1 2207 pfn = ((dev->mdev->bar_addr +
24da0016
AL		 2208 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2209 PAGE_SHIFT) +
2210 page_idx;
e2cd1d1a 2211 return rdma_user_mmap_io(context, vma, pfn, map_size,
6d984a87
MK		 2212 pgprot_writecombine(vma->vm_page_prot),
2213 NULL);
24da0016
AL		 2214}
2215
e126ba97
EC		 2216static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2217{
2218 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2219 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2220 unsigned long command;
e126ba97
EC		 2221 phys_addr_t pfn;
2222
2223 command = get_command(vma->vm_pgoff);
2224 switch (command) {
37aa5c36
GL		 2225 case MLX5_IB_MMAP_WC_PAGE:
2226 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2227 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2228 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2229 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2230
2231 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2232 return -ENOSYS;
2233
d69e3bcf 2234 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2235 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2236 return -EINVAL;
2237
6cbac1e4 2238 if (vma->vm_flags & VM_WRITE)
d69e3bcf 2239 return -EPERM;
c660133c 2240 vma->vm_flags &= ~VM_MAYWRITE;
d69e3bcf
MB		 2241
2242 /* Don't expose to user-space information it shouldn't have */
2243 if (PAGE_SIZE > 4096)
2244 return -EOPNOTSUPP;
2245
d69e3bcf
MB		 2246 pfn = (dev->mdev->iseg_base +
2247 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2248 PAGE_SHIFT;
d5e560d3
JG		 2249 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2250 PAGE_SIZE,
6d984a87
MK		 2251 pgprot_noncached(vma->vm_page_prot),
2252 NULL);
5c99eaec
FD		 2253 case MLX5_IB_MMAP_CLOCK_INFO:
2254 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2255
24da0016
AL		 2256 case MLX5_IB_MMAP_DEVICE_MEM:
2257 return dm_mmap(ibcontext, vma);
2258
e126ba97
EC		 2259 default:
2260 return -EINVAL;
2261 }
2262
2263 return 0;
2264}
2265
25c13324
AL		 2266static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2267 u32 type)
24da0016 2268{
25c13324
AL		 2269 switch (type) {
2270 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2271 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2272 return -EOPNOTSUPP;
2273 break;
2274 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4 2275 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
25c13324
AL		 2276 if (!capable(CAP_SYS_RAWIO) ||
2277 !capable(CAP_NET_RAW))
2278 return -EPERM;
2279
2280 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2281 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2282 return -EOPNOTSUPP;
2283 break;
2284 }
2285
2286 return 0;
2287}
2288
3b113a1e
AL		 2289static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2290 struct mlx5_ib_dm *dm,
2291 struct ib_dm_alloc_attr *attr,
2292 struct uverbs_attr_bundle *attrs)
24da0016 2293{
3b113a1e 2294 struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
24da0016
AL		 2295 u64 start_offset;
2296 u32 page_idx;
2297 int err;
2298
3b113a1e 2299 dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
24da0016 2300
3b113a1e
AL		 2301 err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2302 dm->size, attr->alignment);
24da0016 2303 if (err)
3b113a1e 2304 return err;
24da0016 2305
3b113a1e
AL		 2306 page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2307 MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
24da0016
AL		 2308 PAGE_SHIFT;
2309
2310 err = uverbs_copy_to(attrs,
3b113a1e
AL		 2311 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2312 &page_idx, sizeof(page_idx));
24da0016
AL		 2313 if (err)
2314 goto err_dealloc;
2315
3b113a1e 2316 start_offset = dm->dev_addr & ~PAGE_MASK;
24da0016
AL		 2317 err = uverbs_copy_to(attrs,
2318 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2319 &start_offset, sizeof(start_offset));
2320 if (err)
2321 goto err_dealloc;
2322
3b113a1e
AL		 2323 bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2324 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2325
2326 return 0;
2327
2328err_dealloc:
2329 mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2330
2331 return err;
2332}
2333
25c13324
AL		 2334static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2335 struct mlx5_ib_dm *dm,
2336 struct ib_dm_alloc_attr *attr,
2337 struct uverbs_attr_bundle *attrs,
2338 int type)
2339{
c9b9dcb4 2340 struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
25c13324
AL		 2341 u64 act_size;
2342 int err;
2343
2344 /* Allocation size must a multiple of the basic block size
2345 * and a power of 2.
2346 */
c9b9dcb4 2347 act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
25c13324
AL		 2348 act_size = roundup_pow_of_two(act_size);
2349
2350 dm->size = act_size;
c9b9dcb4
AL		 2351 err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2352 to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2353 &dm->icm_dm.obj_id);
25c13324
AL		 2354 if (err)
2355 return err;
2356
24da0016 2357 err = uverbs_copy_to(attrs,
25c13324
AL		 2358 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2359 &dm->dev_addr, sizeof(dm->dev_addr));
24da0016 2360 if (err)
c9b9dcb4
AL		 2361 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2362 to_mucontext(ctx)->devx_uid, dm->dev_addr,
2363 dm->icm_dm.obj_id);
25c13324
AL		 2364
2365 return err;
2366}
2367
3b113a1e
AL		 2368struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2369 struct ib_ucontext *context,
2370 struct ib_dm_alloc_attr *attr,
2371 struct uverbs_attr_bundle *attrs)
2372{
2373 struct mlx5_ib_dm *dm;
2374 enum mlx5_ib_uapi_dm_type type;
2375 int err;
24da0016 2376
3b113a1e
AL		 2377 err = uverbs_get_const_default(&type, attrs,
2378 MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2379 MLX5_IB_UAPI_DM_TYPE_MEMIC);
2380 if (err)
2381 return ERR_PTR(err);
24da0016 2382
3b113a1e
AL		 2383 mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2384 type, attr->length, attr->alignment);
2385
25c13324
AL		 2386 err = check_dm_type_support(to_mdev(ibdev), type);
2387 if (err)
2388 return ERR_PTR(err);
2389
3b113a1e
AL		 2390 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2391 if (!dm)
2392 return ERR_PTR(-ENOMEM);
2393
2394 dm->type = type;
2395
2396 switch (type) {
2397 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2398 err = handle_alloc_dm_memic(context, dm,
2399 attr,
2400 attrs);
2401 break;
25c13324 2402 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2403 err = handle_alloc_dm_sw_icm(context, dm,
2404 attr, attrs,
2405 MLX5_SW_ICM_TYPE_STEERING);
2406 break;
25c13324 2407 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2408 err = handle_alloc_dm_sw_icm(context, dm,
2409 attr, attrs,
2410 MLX5_SW_ICM_TYPE_HEADER_MODIFY);
25c13324 2411 break;
3b113a1e
AL		 2412 default:
2413 err = -EOPNOTSUPP;
2414 }
24da0016 2415
3b113a1e
AL		 2416 if (err)
2417 goto err_free;
24da0016
AL		 2418
2419 return &dm->ibdm;
2420
24da0016
AL		 2421err_free:
2422 kfree(dm);
2423 return ERR_PTR(err);
2424}
2425
c4367a26 2426int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
24da0016 2427{
25c13324
AL		 2428 struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2429 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
c9b9dcb4 2430 struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
3b113a1e 2431 struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
24da0016 2432 struct mlx5_ib_dm *dm = to_mdm(ibdm);
24da0016
AL		 2433 u32 page_idx;
2434 int ret;
2435
3b113a1e
AL		 2436 switch (dm->type) {
2437 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2438 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2439 if (ret)
2440 return ret;
24da0016 2441
c9b9dcb4
AL		 2442 page_idx = (dm->dev_addr - pci_resource_start(dev->pdev, 0) -
2443 MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr)) >>
2444 PAGE_SHIFT;
25c13324
AL		 2445 bitmap_clear(ctx->dm_pages, page_idx,
2446 DIV_ROUND_UP(dm->size, PAGE_SIZE));
2447 break;
2448 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
c9b9dcb4
AL		 2449 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2450 dm->size, ctx->devx_uid, dm->dev_addr,
2451 dm->icm_dm.obj_id);
2452 if (ret)
2453 return ret;
2454 break;
25c13324 2455 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
c9b9dcb4
AL		 2456 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2457 dm->size, ctx->devx_uid, dm->dev_addr,
2458 dm->icm_dm.obj_id);
25c13324
AL		 2459 if (ret)
2460 return ret;
3b113a1e
AL		 2461 break;
2462 default:
2463 return -EOPNOTSUPP;
2464 }
24da0016
AL		 2465
2466 kfree(dm);
2467
2468 return 0;
2469}
2470
ff23dfa1 2471static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
e126ba97 2472{
21a428a0
LR		 2473 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2474 struct ib_device *ibdev = ibpd->device;
e126ba97 2475 struct mlx5_ib_alloc_pd_resp resp;
e126ba97 2476 int err;
a1069c1c
YH		 2477 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2478 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2479 u16 uid = 0;
ff23dfa1
SR		 2480 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2481 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 2482
ff23dfa1 2483 uid = context ? context->devx_uid : 0;
a1069c1c
YH		 2484 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2485 MLX5_SET(alloc_pd_in, in, uid, uid);
2486 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2487 out, sizeof(out));
21a428a0
LR		 2488 if (err)
2489 return err;
e126ba97 2490
a1069c1c
YH		 2491 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2492 pd->uid = uid;
ff23dfa1 2493 if (udata) {
e126ba97
EC		 2494 resp.pdn = pd->pdn;
2495 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
a1069c1c 2496 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
21a428a0 2497 return -EFAULT;
e126ba97 2498 }
e126ba97
EC		 2499 }
2500
21a428a0 2501 return 0;
e126ba97
EC		 2502}
2503
c4367a26 2504static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
e126ba97
EC		 2505{
2506 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2507 struct mlx5_ib_pd *mpd = to_mpd(pd);
2508
a1069c1c 2509 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
e126ba97
EC		 2510}
2511
466fa6d2
MG		 2512enum {
2513 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2514 MATCH_CRITERIA_ENABLE_MISC_BIT,
71c6e863
AL		 2515 MATCH_CRITERIA_ENABLE_INNER_BIT,
2516 MATCH_CRITERIA_ENABLE_MISC2_BIT
466fa6d2
MG		 2517};
2518
2519#define HEADER_IS_ZERO(match_criteria, headers) \
2520 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2521 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2522
466fa6d2 2523static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2524{
466fa6d2 2525 u8 match_criteria_enable;
038d2ef8 2526
466fa6d2
MG		 2527 match_criteria_enable =
2528 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2529 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2530 match_criteria_enable |=
2531 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2532 MATCH_CRITERIA_ENABLE_MISC_BIT;
2533 match_criteria_enable |=
2534 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2535 MATCH_CRITERIA_ENABLE_INNER_BIT;
71c6e863
AL		 2536 match_criteria_enable |=
2537 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2538 MATCH_CRITERIA_ENABLE_MISC2_BIT;
466fa6d2
MG		 2539
2540 return match_criteria_enable;
038d2ef8
MG		 2541}
2542
6113cc44 2543static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
ca0d4753 2544{
6113cc44
MG		 2545 u8 entry_mask;
2546 u8 entry_val;
2547 int err = 0;
2548
2549 if (!mask)
2550 goto out;
2551
2552 entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2553 ip_protocol);
2554 entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2555 ip_protocol);
2556 if (!entry_mask) {
2557 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2558 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2559 goto out;
2560 }
2561 /* Don't override existing ip protocol */
2562 if (mask != entry_mask || val != entry_val)
2563 err = -EINVAL;
2564out:
2565 return err;
038d2ef8
MG		 2566}
2567
37da2a03 2568static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2d1e697e
MR		 2569 bool inner)
2570{
2571 if (inner) {
2572 MLX5_SET(fte_match_set_misc,
2573 misc_c, inner_ipv6_flow_label, mask);
2574 MLX5_SET(fte_match_set_misc,
2575 misc_v, inner_ipv6_flow_label, val);
2576 } else {
2577 MLX5_SET(fte_match_set_misc,
2578 misc_c, outer_ipv6_flow_label, mask);
2579 MLX5_SET(fte_match_set_misc,
2580 misc_v, outer_ipv6_flow_label, val);
2581 }
2582}
2583
ca0d4753
MG		 2584static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2585{
2586 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2587 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2588 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2589 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2590}
2591
71c6e863
AL		 2592static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2593{
2594 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2595 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2596 return -EOPNOTSUPP;
2597
2598 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2599 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2600 return -EOPNOTSUPP;
2601
2602 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2603 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2604 return -EOPNOTSUPP;
2605
2606 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2607 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2608 return -EOPNOTSUPP;
2609
2610 return 0;
2611}
2612
c47ac6ae
MG		 2613#define LAST_ETH_FIELD vlan_tag
2614#define LAST_IB_FIELD sl
ca0d4753 2615#define LAST_IPV4_FIELD tos
466fa6d2 2616#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2617#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2618#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2619#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2620#define LAST_DROP_FIELD size
3b3233fb 2621#define LAST_COUNTERS_FIELD counters
c47ac6ae
MG		 2622
2623/* Field is the last supported field */
2624#define FIELDS_NOT_SUPPORTED(filter, field)\
2625 memchr_inv((void *)&filter.field +\
2626 sizeof(filter.field), 0,\
2627 sizeof(filter) -\
2628 offsetof(typeof(filter), field) -\
2629 sizeof(filter.field))
2630
2ea26203
MB		 2631int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2632 bool is_egress,
2633 struct mlx5_flow_act *action)
802c2125 2634{
802c2125
AY		 2635
2636 switch (maction->ib_action.type) {
2637 case IB_FLOW_ACTION_ESP:
501f14e3
MB		 2638 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2639 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2640 return -EINVAL;
802c2125
AY		 2641 /* Currently only AES_GCM keymat is supported by the driver */
2642 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2ea26203 2643 action->action |= is_egress ?
802c2125
AY		 2644 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2645 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2646 return 0;
b1085be3
MB		 2647 case IB_FLOW_ACTION_UNSPECIFIED:
2648 if (maction->flow_action_raw.sub_type ==
2649 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
501f14e3
MB		 2650 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2651 return -EINVAL;
b1085be3 2652 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2b688ea5
MG		 2653 action->modify_hdr =
2654 maction->flow_action_raw.modify_hdr;
b1085be3
MB		 2655 return 0;
2656 }
10a30896
MB		 2657 if (maction->flow_action_raw.sub_type ==
2658 MLX5_IB_FLOW_ACTION_DECAP) {
501f14e3
MB		 2659 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2660 return -EINVAL;
10a30896
MB		 2661 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2662 return 0;
2663 }
e806f932
MB		 2664 if (maction->flow_action_raw.sub_type ==
2665 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
501f14e3
MB		 2666 if (action->action &
2667 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2668 return -EINVAL;
e806f932
MB		 2669 action->action |=
2670 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2b688ea5
MG		 2671 action->pkt_reformat =
2672 maction->flow_action_raw.pkt_reformat;
e806f932
MB		 2673 return 0;
2674 }
b1085be3 2675 /* fall through */
802c2125
AY		 2676 default:
2677 return -EOPNOTSUPP;
2678 }
2679}
2680
bb0ee7dc
JL		 2681static int parse_flow_attr(struct mlx5_core_dev *mdev,
2682 struct mlx5_flow_spec *spec,
2683 const union ib_flow_spec *ib_spec,
802c2125 2684 const struct ib_flow_attr *flow_attr,
71c6e863 2685 struct mlx5_flow_act *action, u32 prev_type)
038d2ef8 2686{
bb0ee7dc
JL		 2687 struct mlx5_flow_context *flow_context = &spec->flow_context;
2688 u32 *match_c = spec->match_criteria;
2689 u32 *match_v = spec->match_value;
466fa6d2
MG		 2690 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2691 misc_parameters);
2692 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2693 misc_parameters);
71c6e863
AL		 2694 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2695 misc_parameters_2);
2696 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2697 misc_parameters_2);
2d1e697e
MR		 2698 void *headers_c;
2699 void *headers_v;
19cc7524 2700 int match_ipv;
802c2125 2701 int ret;
2d1e697e
MR		 2702
2703 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2704 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2705 inner_headers);
2706 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2707 inner_headers);
19cc7524
AL		 2708 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2709 ft_field_support.inner_ip_version);
2d1e697e
MR		 2710 } else {
2711 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2712 outer_headers);
2713 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2714 outer_headers);
19cc7524
AL		 2715 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2716 ft_field_support.outer_ip_version);
2d1e697e 2717 }
466fa6d2 2718
2d1e697e 2719 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2720 case IB_FLOW_SPEC_ETH:
c47ac6ae 2721 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2722 return -EOPNOTSUPP;
038d2ef8 2723
2d1e697e 2724 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2725 dmac_47_16),
2726 ib_spec->eth.mask.dst_mac);
2d1e697e 2727 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2728 dmac_47_16),
2729 ib_spec->eth.val.dst_mac);
2730
2d1e697e 2731 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2732 smac_47_16),
2733 ib_spec->eth.mask.src_mac);
2d1e697e 2734 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2735 smac_47_16),
2736 ib_spec->eth.val.src_mac);
2737
038d2ef8 2738 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2739 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2740 cvlan_tag, 1);
2d1e697e 2741 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2742 cvlan_tag, 1);
038d2ef8 2743
2d1e697e 2744 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2745 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2746 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2747 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2748
2d1e697e 2749 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2750 first_cfi,
2751 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2752 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2753 first_cfi,
2754 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2755
2d1e697e 2756 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2757 first_prio,
2758 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2759 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2760 first_prio,
2761 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2762 }
2d1e697e 2763 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2764 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2765 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2766 ethertype, ntohs(ib_spec->eth.val.ether_type));
2767 break;
2768 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2769 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2770 return -EOPNOTSUPP;
038d2ef8 2771
19cc7524
AL		 2772 if (match_ipv) {
2773 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2774 ip_version, 0xf);
2775 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2776 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2777 } else {
2778 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2779 ethertype, 0xffff);
2780 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2781 ethertype, ETH_P_IP);
2782 }
038d2ef8 2783
2d1e697e 2784 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2785 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2786 &ib_spec->ipv4.mask.src_ip,
2787 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2788 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2789 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2790 &ib_spec->ipv4.val.src_ip,
2791 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2792 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2793 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2794 &ib_spec->ipv4.mask.dst_ip,
2795 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2796 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2797 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2798 &ib_spec->ipv4.val.dst_ip,
2799 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2800
2d1e697e 2801 set_tos(headers_c, headers_v,
ca0d4753
MG		 2802 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2803
6113cc44
MG		 2804 if (set_proto(headers_c, headers_v,
2805 ib_spec->ipv4.mask.proto,
2806 ib_spec->ipv4.val.proto))
2807 return -EINVAL;
038d2ef8 2808 break;
026bae0c 2809 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2810 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2811 return -EOPNOTSUPP;
026bae0c 2812
19cc7524
AL		 2813 if (match_ipv) {
2814 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2815 ip_version, 0xf);
2816 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2817 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2818 } else {
2819 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2820 ethertype, 0xffff);
2821 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2822 ethertype, ETH_P_IPV6);
2823 }
026bae0c 2824
2d1e697e 2825 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2826 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2827 &ib_spec->ipv6.mask.src_ip,
2828 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2829 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2830 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2831 &ib_spec->ipv6.val.src_ip,
2832 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2833 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2834 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2835 &ib_spec->ipv6.mask.dst_ip,
2836 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2837 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2838 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2839 &ib_spec->ipv6.val.dst_ip,
2840 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2841
2d1e697e 2842 set_tos(headers_c, headers_v,
466fa6d2
MG		 2843 ib_spec->ipv6.mask.traffic_class,
2844 ib_spec->ipv6.val.traffic_class);
2845
6113cc44
MG		 2846 if (set_proto(headers_c, headers_v,
2847 ib_spec->ipv6.mask.next_hdr,
2848 ib_spec->ipv6.val.next_hdr))
2849 return -EINVAL;
466fa6d2 2850
2d1e697e
MR		 2851 set_flow_label(misc_params_c, misc_params_v,
2852 ntohl(ib_spec->ipv6.mask.flow_label),
2853 ntohl(ib_spec->ipv6.val.flow_label),
2854 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2855 break;
2856 case IB_FLOW_SPEC_ESP:
2857 if (ib_spec->esp.mask.seq)
2858 return -EOPNOTSUPP;
2d1e697e 2859
802c2125
AY		 2860 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2861 ntohl(ib_spec->esp.mask.spi));
2862 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2863 ntohl(ib_spec->esp.val.spi));
026bae0c 2864 break;
038d2ef8 2865 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2866 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2867 LAST_TCP_UDP_FIELD))
1ffd3a26 2868 return -EOPNOTSUPP;
038d2ef8 2869
6113cc44
MG		 2870 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2871 return -EINVAL;
038d2ef8 2872
2d1e697e 2873 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2874 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2875 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2876 ntohs(ib_spec->tcp_udp.val.src_port));
2877
2d1e697e 2878 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2879 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2880 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2881 ntohs(ib_spec->tcp_udp.val.dst_port));
2882 break;
2883 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2884 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2885 LAST_TCP_UDP_FIELD))
1ffd3a26 2886 return -EOPNOTSUPP;
038d2ef8 2887
6113cc44
MG		 2888 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2889 return -EINVAL;
038d2ef8 2890
2d1e697e 2891 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2892 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2893 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2894 ntohs(ib_spec->tcp_udp.val.src_port));
2895
2d1e697e 2896 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2897 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2898 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2899 ntohs(ib_spec->tcp_udp.val.dst_port));
2900 break;
da2f22ae
AL		 2901 case IB_FLOW_SPEC_GRE:
2902 if (ib_spec->gre.mask.c_ks_res0_ver)
2903 return -EOPNOTSUPP;
2904
6113cc44
MG		 2905 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2906 return -EINVAL;
2907
da2f22ae
AL		 2908 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2909 0xff);
2910 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2911 IPPROTO_GRE);
2912
2913 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
a93b632c 2914 ntohs(ib_spec->gre.mask.protocol));
da2f22ae
AL		 2915 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2916 ntohs(ib_spec->gre.val.protocol));
2917
2918 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
5886a96a 2919 gre_key.nvgre.hi),
da2f22ae
AL		 2920 &ib_spec->gre.mask.key,
2921 sizeof(ib_spec->gre.mask.key));
2922 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
5886a96a 2923 gre_key.nvgre.hi),
da2f22ae
AL		 2924 &ib_spec->gre.val.key,
2925 sizeof(ib_spec->gre.val.key));
2926 break;
71c6e863
AL		 2927 case IB_FLOW_SPEC_MPLS:
2928 switch (prev_type) {
2929 case IB_FLOW_SPEC_UDP:
2930 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2931 ft_field_support.outer_first_mpls_over_udp),
2932 &ib_spec->mpls.mask.tag))
2933 return -EOPNOTSUPP;
2934
2935 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2936 outer_first_mpls_over_udp),
2937 &ib_spec->mpls.val.tag,
2938 sizeof(ib_spec->mpls.val.tag));
2939 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2940 outer_first_mpls_over_udp),
2941 &ib_spec->mpls.mask.tag,
2942 sizeof(ib_spec->mpls.mask.tag));
2943 break;
2944 case IB_FLOW_SPEC_GRE:
2945 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2946 ft_field_support.outer_first_mpls_over_gre),
2947 &ib_spec->mpls.mask.tag))
2948 return -EOPNOTSUPP;
2949
2950 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2951 outer_first_mpls_over_gre),
2952 &ib_spec->mpls.val.tag,
2953 sizeof(ib_spec->mpls.val.tag));
2954 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2955 outer_first_mpls_over_gre),
2956 &ib_spec->mpls.mask.tag,
2957 sizeof(ib_spec->mpls.mask.tag));
2958 break;
2959 default:
2960 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2961 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2962 ft_field_support.inner_first_mpls),
2963 &ib_spec->mpls.mask.tag))
2964 return -EOPNOTSUPP;
2965
2966 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2967 inner_first_mpls),
2968 &ib_spec->mpls.val.tag,
2969 sizeof(ib_spec->mpls.val.tag));
2970 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2971 inner_first_mpls),
2972 &ib_spec->mpls.mask.tag,
2973 sizeof(ib_spec->mpls.mask.tag));
2974 } else {
2975 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2976 ft_field_support.outer_first_mpls),
2977 &ib_spec->mpls.mask.tag))
2978 return -EOPNOTSUPP;
2979
2980 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2981 outer_first_mpls),
2982 &ib_spec->mpls.val.tag,
2983 sizeof(ib_spec->mpls.val.tag));
2984 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2985 outer_first_mpls),
2986 &ib_spec->mpls.mask.tag,
2987 sizeof(ib_spec->mpls.mask.tag));
2988 }
2989 }
2990 break;
ffb30d8f
MR		 2991 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2992 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2993 LAST_TUNNEL_FIELD))
1ffd3a26 2994 return -EOPNOTSUPP;
ffb30d8f
MR		 2995
2996 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2997 ntohl(ib_spec->tunnel.mask.tunnel_id));
2998 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2999 ntohl(ib_spec->tunnel.val.tunnel_id));
3000 break;
2ac693f9
MR		 3001 case IB_FLOW_SPEC_ACTION_TAG:
3002 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
3003 LAST_FLOW_TAG_FIELD))
3004 return -EOPNOTSUPP;
3005 if (ib_spec->flow_tag.tag_id >= BIT(24))
3006 return -EINVAL;
3007
bb0ee7dc
JL		 3008 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3009 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
2ac693f9 3010 break;
a22ed86c
SS		 3011 case IB_FLOW_SPEC_ACTION_DROP:
3012 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3013 LAST_DROP_FIELD))
3014 return -EOPNOTSUPP;
075572d4 3015 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 3016 break;
802c2125 3017 case IB_FLOW_SPEC_ACTION_HANDLE:
2ea26203
MB		 3018 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3019 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
802c2125
AY		 3020 if (ret)
3021 return ret;
3022 break;
3b3233fb
RS		 3023 case IB_FLOW_SPEC_ACTION_COUNT:
3024 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3025 LAST_COUNTERS_FIELD))
3026 return -EOPNOTSUPP;
3027
3028 /* for now support only one counters spec per flow */
3029 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3030 return -EINVAL;
3031
3032 action->counters = ib_spec->flow_count.counters;
3033 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3034 break;
038d2ef8
MG		 3035 default:
3036 return -EINVAL;
3037 }
3038
3039 return 0;
3040}
3041
3042/* If a flow could catch both multicast and unicast packets,
3043 * it won't fall into the multicast flow steering table and this rule
3044 * could steal other multicast packets.
3045 */
a550ddfc 3046static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 3047{
81e30880 3048 union ib_flow_spec *flow_spec;
038d2ef8
MG		 3049
3050 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 3051 ib_attr->num_of_specs < 1)
3052 return false;
3053
81e30880
YH		 3054 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3055 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3056 struct ib_flow_spec_ipv4 *ipv4_spec;
3057
3058 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3059 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3060 return true;
3061
038d2ef8 3062 return false;
81e30880
YH		 3063 }
3064
3065 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3066 struct ib_flow_spec_eth *eth_spec;
3067
3068 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3069 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3070 is_multicast_ether_addr(eth_spec->val.dst_mac);
3071 }
038d2ef8 3072
81e30880 3073 return false;
038d2ef8
MG		 3074}
3075
802c2125
AY		 3076enum valid_spec {
3077 VALID_SPEC_INVALID,
3078 VALID_SPEC_VALID,
3079 VALID_SPEC_NA,
3080};
3081
3082static enum valid_spec
3083is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3084 const struct mlx5_flow_spec *spec,
3085 const struct mlx5_flow_act *flow_act,
3086 bool egress)
3087{
3088 const u32 *match_c = spec->match_criteria;
3089 bool is_crypto =
3090 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3091 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3092 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3093 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3094
3095 /*
3096 * Currently only crypto is supported in egress, when regular egress
3097 * rules would be supported, always return VALID_SPEC_NA.
3098 */
3099 if (!is_crypto)
78dd0c43 3100 return VALID_SPEC_NA;
802c2125
AY		 3101
3102 return is_crypto && is_ipsec &&
bb0ee7dc
JL		 3103 (!egress || (!is_drop &&
3104 !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
802c2125
AY		 3105 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3106}
3107
3108static bool is_valid_spec(struct mlx5_core_dev *mdev,
3109 const struct mlx5_flow_spec *spec,
3110 const struct mlx5_flow_act *flow_act,
3111 bool egress)
3112{
3113 /* We curretly only support ipsec egress flow */
3114 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3115}
3116
19cc7524
AL		 3117static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3118 const struct ib_flow_attr *flow_attr,
0f750966 3119 bool check_inner)
038d2ef8
MG		 3120{
3121 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 3122 int match_ipv = check_inner ?
3123 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3124 ft_field_support.inner_ip_version) :
3125 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3126 ft_field_support.outer_ip_version);
0f750966
AL		 3127 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3128 bool ipv4_spec_valid, ipv6_spec_valid;
3129 unsigned int ip_spec_type = 0;
3130 bool has_ethertype = false;
038d2ef8 3131 unsigned int spec_index;
0f750966
AL		 3132 bool mask_valid = true;
3133 u16 eth_type = 0;
3134 bool type_valid;
038d2ef8
MG		 3135
3136 /* Validate that ethertype is correct */
3137 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 3138 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 3139 ib_spec->eth.mask.ether_type) {
0f750966
AL		 3140 mask_valid = (ib_spec->eth.mask.ether_type ==
3141 htons(0xffff));
3142 has_ethertype = true;
3143 eth_type = ntohs(ib_spec->eth.val.ether_type);
3144 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3145 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3146 ip_spec_type = ib_spec->type;
038d2ef8
MG		 3147 }
3148 ib_spec = (void *)ib_spec + ib_spec->size;
3149 }
0f750966
AL		 3150
3151 type_valid = (!has_ethertype) || (!ip_spec_type);
3152 if (!type_valid && mask_valid) {
3153 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3154 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3155 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3156 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 3157
3158 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3159 (((eth_type == ETH_P_MPLS_UC) ||
3160 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 3161 }
3162
3163 return type_valid;
3164}
3165
19cc7524
AL		 3166static bool is_valid_attr(struct mlx5_core_dev *mdev,
3167 const struct ib_flow_attr *flow_attr)
0f750966 3168{
19cc7524
AL		 3169 return is_valid_ethertype(mdev, flow_attr, false) &&
3170 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 3171}
3172
3173static void put_flow_table(struct mlx5_ib_dev *dev,
3174 struct mlx5_ib_flow_prio *prio, bool ft_added)
3175{
3176 prio->refcount -= !!ft_added;
3177 if (!prio->refcount) {
3178 mlx5_destroy_flow_table(prio->flow_table);
3179 prio->flow_table = NULL;
3180 }
3181}
3182
3b3233fb
RS		 3183static void counters_clear_description(struct ib_counters *counters)
3184{
3185 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3186
3187 mutex_lock(&mcounters->mcntrs_mutex);
3188 kfree(mcounters->counters_data);
3189 mcounters->counters_data = NULL;
3190 mcounters->cntrs_max_index = 0;
3191 mutex_unlock(&mcounters->mcntrs_mutex);
3192}
3193
038d2ef8
MG		 3194static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3195{
038d2ef8
MG		 3196 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3197 struct mlx5_ib_flow_handler,
3198 ibflow);
3199 struct mlx5_ib_flow_handler *iter, *tmp;
d4be3f44 3200 struct mlx5_ib_dev *dev = handler->dev;
038d2ef8 3201
9a4ca38d 3202 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 3203
3204 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 3205 mlx5_del_flow_rules(iter->rule);
cc0e5d42 3206 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 3207 list_del(&iter->list);
3208 kfree(iter);
3209 }
3210
74491de9 3211 mlx5_del_flow_rules(handler->rule);
5497adc6 3212 put_flow_table(dev, handler->prio, true);
3b3233fb
RS		 3213 if (handler->ibcounters &&
3214 atomic_read(&handler->ibcounters->usecnt) == 1)
3215 counters_clear_description(handler->ibcounters);
038d2ef8 3216
3b3233fb 3217 mutex_unlock(&dev->flow_db->lock);
d4be3f44
YH		 3218 if (handler->flow_matcher)
3219 atomic_dec(&handler->flow_matcher->usecnt);
038d2ef8
MG		 3220 kfree(handler);
3221
3222 return 0;
3223}
3224
35d19011
MG		 3225static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3226{
3227 priority *= 2;
3228 if (!dont_trap)
3229 priority++;
3230 return priority;
3231}
3232
cc0e5d42
MG		 3233enum flow_table_type {
3234 MLX5_IB_FT_RX,
3235 MLX5_IB_FT_TX
3236};
3237
00b7c2ab
MG		 3238#define MLX5_FS_MAX_TYPES 6
3239#define MLX5_FS_MAX_ENTRIES BIT(16)
d4be3f44
YH		 3240
3241static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3242 struct mlx5_ib_flow_prio *prio,
3243 int priority,
4adda112
MB		 3244 int num_entries, int num_groups,
3245 u32 flags)
d4be3f44
YH		 3246{
3247 struct mlx5_flow_table *ft;
3248
3249 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3250 num_entries,
3251 num_groups,
4adda112 3252 0, flags);
d4be3f44
YH		 3253 if (IS_ERR(ft))
3254 return ERR_CAST(ft);
3255
3256 prio->flow_table = ft;
3257 prio->refcount = 0;
3258 return prio;
3259}
3260
038d2ef8 3261static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 3262 struct ib_flow_attr *flow_attr,
3263 enum flow_table_type ft_type)
038d2ef8 3264{
35d19011 3265 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 3266 struct mlx5_flow_namespace *ns = NULL;
3267 struct mlx5_ib_flow_prio *prio;
3268 struct mlx5_flow_table *ft;
dac388ef 3269 int max_table_size;
038d2ef8
MG		 3270 int num_entries;
3271 int num_groups;
cecae747 3272 bool esw_encap;
4adda112 3273 u32 flags = 0;
038d2ef8 3274 int priority;
038d2ef8 3275
dac388ef
MG		 3276 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3277 log_max_ft_size));
cecae747
MG		 3278 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3279 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
038d2ef8 3280 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
78dd0c43
MB		 3281 enum mlx5_flow_namespace_type fn_type;
3282
3283 if (flow_is_multicast_only(flow_attr) &&
3284 !dont_trap)
038d2ef8
MG		 3285 priority = MLX5_IB_FLOW_MCAST_PRIO;
3286 else
35d19011
MG		 3287 priority = ib_prio_to_core_prio(flow_attr->priority,
3288 dont_trap);
78dd0c43
MB		 3289 if (ft_type == MLX5_IB_FT_RX) {
3290 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3291 prio = &dev->flow_db->prios[priority];
cecae747 3292 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3293 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3294 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
cecae747 3295 if (!dev->is_rep && !esw_encap &&
5c2db53f
MB		 3296 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3297 reformat_l3_tunnel_to_l2))
3298 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3299 } else {
3300 max_table_size =
3301 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3302 log_max_ft_size));
3303 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3304 prio = &dev->flow_db->egress_prios[priority];
cecae747 3305 if (!dev->is_rep && !esw_encap &&
4adda112
MB		 3306 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3307 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
78dd0c43
MB		 3308 }
3309 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
038d2ef8
MG		 3310 num_entries = MLX5_FS_MAX_ENTRIES;
3311 num_groups = MLX5_FS_MAX_TYPES;
038d2ef8
MG		 3312 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3313 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3314 ns = mlx5_get_flow_namespace(dev->mdev,
3315 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3316 build_leftovers_ft_param(&priority,
3317 &num_entries,
3318 &num_groups);
9a4ca38d 3319 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 3320 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3321 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3322 allow_sniffer_and_nic_rx_shared_tir))
3323 return ERR_PTR(-ENOTSUPP);
3324
3325 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3326 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3327 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3328
9a4ca38d 3329 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 3330 priority = 0;
3331 num_entries = 1;
3332 num_groups = 1;
038d2ef8
MG		 3333 }
3334
3335 if (!ns)
3336 return ERR_PTR(-ENOTSUPP);
3337
3b70508a 3338 max_table_size = min_t(int, num_entries, max_table_size);
dac388ef 3339
038d2ef8 3340 ft = prio->flow_table;
d4be3f44 3341 if (!ft)
3b70508a 3342 return _get_prio(ns, prio, priority, max_table_size, num_groups,
4adda112 3343 flags);
038d2ef8 3344
d4be3f44 3345 return prio;
038d2ef8
MG		 3346}
3347
a550ddfc
YH		 3348static void set_underlay_qp(struct mlx5_ib_dev *dev,
3349 struct mlx5_flow_spec *spec,
3350 u32 underlay_qpn)
3351{
3352 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3353 spec->match_criteria,
3354 misc_parameters);
3355 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3356 misc_parameters);
3357
3358 if (underlay_qpn &&
3359 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3360 ft_field_support.bth_dst_qp)) {
3361 MLX5_SET(fte_match_set_misc,
3362 misc_params_v, bth_dst_qp, underlay_qpn);
3363 MLX5_SET(fte_match_set_misc,
3364 misc_params_c, bth_dst_qp, 0xffffff);
3365 }
3366}
3367
5e95af5f
RS		 3368static int read_flow_counters(struct ib_device *ibdev,
3369 struct mlx5_read_counters_attr *read_attr)
3370{
3371 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3372 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3373
3374 return mlx5_fc_query(dev->mdev, fc,
3375 &read_attr->out[IB_COUNTER_PACKETS],
3376 &read_attr->out[IB_COUNTER_BYTES]);
3377}
3378
3379/* flow counters currently expose two counters packets and bytes */
3380#define FLOW_COUNTERS_NUM 2
3b3233fb
RS		 3381static int counters_set_description(struct ib_counters *counters,
3382 enum mlx5_ib_counters_type counters_type,
3383 struct mlx5_ib_flow_counters_desc *desc_data,
3384 u32 ncounters)
3385{
3386 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3387 u32 cntrs_max_index = 0;
3388 int i;
3389
3390 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3391 return -EINVAL;
3392
3393 /* init the fields for the object */
3394 mcounters->type = counters_type;
5e95af5f
RS		 3395 mcounters->read_counters = read_flow_counters;
3396 mcounters->counters_num = FLOW_COUNTERS_NUM;
3b3233fb
RS		 3397 mcounters->ncounters = ncounters;
3398 /* each counter entry have both description and index pair */
3399 for (i = 0; i < ncounters; i++) {
3400 if (desc_data[i].description > IB_COUNTER_BYTES)
3401 return -EINVAL;
3402
3403 if (cntrs_max_index <= desc_data[i].index)
3404 cntrs_max_index = desc_data[i].index + 1;
3405 }
3406
3407 mutex_lock(&mcounters->mcntrs_mutex);
3408 mcounters->counters_data = desc_data;
3409 mcounters->cntrs_max_index = cntrs_max_index;
3410 mutex_unlock(&mcounters->mcntrs_mutex);
3411
3412 return 0;
3413}
3414
3415#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3416static int flow_counters_set_data(struct ib_counters *ibcounters,
3417 struct mlx5_ib_create_flow *ucmd)
3418{
3419 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3420 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3421 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3422 bool hw_hndl = false;
3423 int ret = 0;
3424
3425 if (ucmd && ucmd->ncounters_data != 0) {
3426 cntrs_data = ucmd->data;
3427 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3428 return -EINVAL;
3429
3430 desc_data = kcalloc(cntrs_data->ncounters,
3431 sizeof(*desc_data),
3432 GFP_KERNEL);
3433 if (!desc_data)
3434 return -ENOMEM;
3435
3436 if (copy_from_user(desc_data,
3437 u64_to_user_ptr(cntrs_data->counters_data),
3438 sizeof(*desc_data) * cntrs_data->ncounters)) {
3439 ret = -EFAULT;
3440 goto free;
3441 }
3442 }
3443
3444 if (!mcounters->hw_cntrs_hndl) {
3445 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3446 to_mdev(ibcounters->device)->mdev, false);
e31abf76 3447 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3448 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3449 goto free;
3450 }
3451 hw_hndl = true;
3452 }
3453
3454 if (desc_data) {
3455 /* counters already bound to at least one flow */
3456 if (mcounters->cntrs_max_index) {
3457 ret = -EINVAL;
3458 goto free_hndl;
3459 }
3460
3461 ret = counters_set_description(ibcounters,
3462 MLX5_IB_COUNTERS_FLOW,
3463 desc_data,
3464 cntrs_data->ncounters);
3465 if (ret)
3466 goto free_hndl;
3467
3468 } else if (!mcounters->cntrs_max_index) {
3469 /* counters not bound yet, must have udata passed */
3470 ret = -EINVAL;
3471 goto free_hndl;
3472 }
3473
3474 return 0;
3475
3476free_hndl:
3477 if (hw_hndl) {
3478 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3479 mcounters->hw_cntrs_hndl);
3480 mcounters->hw_cntrs_hndl = NULL;
3481 }
3482free:
3483 kfree(desc_data);
3484 return ret;
3485}
3486
669ff1e3
JL		 3487static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3488 struct mlx5_flow_spec *spec,
3489 struct mlx5_eswitch_rep *rep)
3490{
3491 struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3492 void *misc;
3493
3494 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3495 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3496 misc_parameters_2);
3497
3498 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3499 mlx5_eswitch_get_vport_metadata_for_match(esw,
3500 rep->vport));
3501 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3502 misc_parameters_2);
3503
3504 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3505 } else {
3506 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3507 misc_parameters);
3508
3509 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3510
3511 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3512 misc_parameters);
3513
3514 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3515 }
3516}
3517
a550ddfc
YH		 3518static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3519 struct mlx5_ib_flow_prio *ft_prio,
3520 const struct ib_flow_attr *flow_attr,
3521 struct mlx5_flow_destination *dst,
3b3233fb
RS		 3522 u32 underlay_qpn,
3523 struct mlx5_ib_create_flow *ucmd)
038d2ef8
MG		 3524{
3525 struct mlx5_flow_table *ft = ft_prio->flow_table;
3526 struct mlx5_ib_flow_handler *handler;
bb0ee7dc 3527 struct mlx5_flow_act flow_act = {};
c5bb1730 3528 struct mlx5_flow_spec *spec;
3b3233fb
RS		 3529 struct mlx5_flow_destination dest_arr[2] = {};
3530 struct mlx5_flow_destination *rule_dst = dest_arr;
dd063d0e 3531 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3532 unsigned int spec_index;
71c6e863 3533 u32 prev_type = 0;
038d2ef8 3534 int err = 0;
3b3233fb 3535 int dest_num = 0;
802c2125 3536 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3537
19cc7524 3538 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3539 return ERR_PTR(-EINVAL);
3540
6a4d00be 3541 if (dev->is_rep && is_egress)
78dd0c43
MB		 3542 return ERR_PTR(-EINVAL);
3543
1b9a07ee 3544 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3545 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3546 if (!handler || !spec) {
038d2ef8
MG		 3547 err = -ENOMEM;
3548 goto free;
3549 }
3550
3551 INIT_LIST_HEAD(&handler->list);
3552
3553 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
bb0ee7dc 3554 err = parse_flow_attr(dev->mdev, spec,
71c6e863
AL		 3555 ib_flow, flow_attr, &flow_act,
3556 prev_type);
038d2ef8
MG		 3557 if (err < 0)
3558 goto free;
3559
71c6e863 3560 prev_type = ((union ib_flow_spec *)ib_flow)->type;
038d2ef8
MG		 3561 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3562 }
3563
40179392
MG		 3564 if (dst && !(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP)) {
3565 memcpy(&dest_arr[0], dst, sizeof(*dst));
3566 dest_num++;
3567 }
3568
a550ddfc
YH		 3569 if (!flow_is_multicast_only(flow_attr))
3570 set_underlay_qp(dev, spec, underlay_qpn);
3571
6a4d00be 3572 if (dev->is_rep) {
669ff1e3 3573 struct mlx5_eswitch_rep *rep;
018a94ee 3574
669ff1e3
JL		 3575 rep = dev->port[flow_attr->port - 1].rep;
3576 if (!rep) {
6a4d00be
MB		 3577 err = -EINVAL;
3578 goto free;
3579 }
669ff1e3
JL		 3580
3581 mlx5_ib_set_rule_source_port(dev, spec, rep);
018a94ee
MB		 3582 }
3583
466fa6d2 3584 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3585
3586 if (is_egress &&
3587 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3588 err = -EINVAL;
3589 goto free;
3590 }
3591
3b3233fb 3592 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
171c7625
MB		 3593 struct mlx5_ib_mcounters *mcounters;
3594
3b3233fb
RS		 3595 err = flow_counters_set_data(flow_act.counters, ucmd);
3596 if (err)
3597 goto free;
3598
171c7625 3599 mcounters = to_mcounters(flow_act.counters);
3b3233fb
RS		 3600 handler->ibcounters = flow_act.counters;
3601 dest_arr[dest_num].type =
3602 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625
MB		 3603 dest_arr[dest_num].counter_id =
3604 mlx5_fc_id(mcounters->hw_cntrs_hndl);
3b3233fb
RS		 3605 dest_num++;
3606 }
3607
075572d4 3608 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
40179392 3609 if (!dest_num)
3b3233fb 3610 rule_dst = NULL;
a22ed86c 3611 } else {
802c2125
AY		 3612 if (is_egress)
3613 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3614 else
3615 flow_act.action |=
3b3233fb 3616 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
802c2125 3617 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3618 }
2ac693f9 3619
bb0ee7dc 3620 if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG) &&
2ac693f9
MR		 3621 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3622 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3623 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
bb0ee7dc 3624 spec->flow_context.flow_tag, flow_attr->type);
2ac693f9
MR		 3625 err = -EINVAL;
3626 goto free;
3627 }
74491de9 3628 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3629 &flow_act,
a22ed86c 3630 rule_dst, dest_num);
038d2ef8
MG		 3631
3632 if (IS_ERR(handler->rule)) {
3633 err = PTR_ERR(handler->rule);
3634 goto free;
3635 }
3636
d9d4980a 3637 ft_prio->refcount++;
5497adc6 3638 handler->prio = ft_prio;
d4be3f44 3639 handler->dev = dev;
038d2ef8
MG		 3640
3641 ft_prio->flow_table = ft;
3642free:
3b3233fb
RS		 3643 if (err && handler) {
3644 if (handler->ibcounters &&
3645 atomic_read(&handler->ibcounters->usecnt) == 1)
3646 counters_clear_description(handler->ibcounters);
038d2ef8 3647 kfree(handler);
3b3233fb 3648 }
c5bb1730 3649 kvfree(spec);
038d2ef8
MG		 3650 return err ? ERR_PTR(err) : handler;
3651}
3652
a550ddfc
YH		 3653static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3654 struct mlx5_ib_flow_prio *ft_prio,
3655 const struct ib_flow_attr *flow_attr,
3656 struct mlx5_flow_destination *dst)
3657{
3b3233fb 3658 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
a550ddfc
YH		 3659}
3660
35d19011
MG		 3661static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3662 struct mlx5_ib_flow_prio *ft_prio,
3663 struct ib_flow_attr *flow_attr,
3664 struct mlx5_flow_destination *dst)
3665{
3666 struct mlx5_ib_flow_handler *handler_dst = NULL;
3667 struct mlx5_ib_flow_handler *handler = NULL;
3668
3669 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3670 if (!IS_ERR(handler)) {
3671 handler_dst = create_flow_rule(dev, ft_prio,
3672 flow_attr, dst);
3673 if (IS_ERR(handler_dst)) {
74491de9 3674 mlx5_del_flow_rules(handler->rule);
d9d4980a 3675 ft_prio->refcount--;
35d19011
MG		 3676 kfree(handler);
3677 handler = handler_dst;
3678 } else {
3679 list_add(&handler_dst->list, &handler->list);
3680 }
3681 }
3682
3683 return handler;
3684}
038d2ef8
MG		 3685enum {
3686 LEFTOVERS_MC,
3687 LEFTOVERS_UC,
3688};
3689
3690static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3691 struct mlx5_ib_flow_prio *ft_prio,
3692 struct ib_flow_attr *flow_attr,
3693 struct mlx5_flow_destination *dst)
3694{
3695 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3696 struct mlx5_ib_flow_handler *handler = NULL;
3697
3698 static struct {
3699 struct ib_flow_attr flow_attr;
3700 struct ib_flow_spec_eth eth_flow;
3701 } leftovers_specs[] = {
3702 [LEFTOVERS_MC] = {
3703 .flow_attr = {
3704 .num_of_specs = 1,
3705 .size = sizeof(leftovers_specs[0])
3706 },
3707 .eth_flow = {
3708 .type = IB_FLOW_SPEC_ETH,
3709 .size = sizeof(struct ib_flow_spec_eth),
3710 .mask = {.dst_mac = {0x1} },
3711 .val = {.dst_mac = {0x1} }
3712 }
3713 },
3714 [LEFTOVERS_UC] = {
3715 .flow_attr = {
3716 .num_of_specs = 1,
3717 .size = sizeof(leftovers_specs[0])
3718 },
3719 .eth_flow = {
3720 .type = IB_FLOW_SPEC_ETH,
3721 .size = sizeof(struct ib_flow_spec_eth),
3722 .mask = {.dst_mac = {0x1} },
3723 .val = {.dst_mac = {} }
3724 }
3725 }
3726 };
3727
3728 handler = create_flow_rule(dev, ft_prio,
3729 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3730 dst);
3731 if (!IS_ERR(handler) &&
3732 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3733 handler_ucast = create_flow_rule(dev, ft_prio,
3734 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3735 dst);
3736 if (IS_ERR(handler_ucast)) {
74491de9 3737 mlx5_del_flow_rules(handler->rule);
d9d4980a 3738 ft_prio->refcount--;
038d2ef8
MG		 3739 kfree(handler);
3740 handler = handler_ucast;
3741 } else {
3742 list_add(&handler_ucast->list, &handler->list);
3743 }
3744 }
3745
3746 return handler;
3747}
3748
cc0e5d42
MG		 3749static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3750 struct mlx5_ib_flow_prio *ft_rx,
3751 struct mlx5_ib_flow_prio *ft_tx,
3752 struct mlx5_flow_destination *dst)
3753{
3754 struct mlx5_ib_flow_handler *handler_rx;
3755 struct mlx5_ib_flow_handler *handler_tx;
3756 int err;
3757 static const struct ib_flow_attr flow_attr = {
3758 .num_of_specs = 0,
3759 .size = sizeof(flow_attr)
3760 };
3761
3762 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3763 if (IS_ERR(handler_rx)) {
3764 err = PTR_ERR(handler_rx);
3765 goto err;
3766 }
3767
3768 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3769 if (IS_ERR(handler_tx)) {
3770 err = PTR_ERR(handler_tx);
3771 goto err_tx;
3772 }
3773
3774 list_add(&handler_tx->list, &handler_rx->list);
3775
3776 return handler_rx;
3777
3778err_tx:
74491de9 3779 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3780 ft_rx->refcount--;
3781 kfree(handler_rx);
3782err:
3783 return ERR_PTR(err);
3784}
3785
038d2ef8
MG		 3786static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3787 struct ib_flow_attr *flow_attr,
59082a32
MB		 3788 int domain,
3789 struct ib_udata *udata)
038d2ef8
MG		 3790{
3791 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3792 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3793 struct mlx5_ib_flow_handler *handler = NULL;
3794 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3795 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3796 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3797 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3b3233fb
RS		 3798 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3799 size_t min_ucmd_sz, required_ucmd_sz;
038d2ef8 3800 int err;
a550ddfc 3801 int underlay_qpn;
038d2ef8 3802
3b3233fb
RS		 3803 if (udata && udata->inlen) {
3804 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3805 sizeof(ucmd_hdr.reserved);
3806 if (udata->inlen < min_ucmd_sz)
3807 return ERR_PTR(-EOPNOTSUPP);
3808
3809 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3810 if (err)
3811 return ERR_PTR(err);
3812
3813 /* currently supports only one counters data */
3814 if (ucmd_hdr.ncounters_data > 1)
3815 return ERR_PTR(-EINVAL);
3816
3817 required_ucmd_sz = min_ucmd_sz +
3818 sizeof(struct mlx5_ib_flow_counters_data) *
3819 ucmd_hdr.ncounters_data;
3820 if (udata->inlen > required_ucmd_sz &&
3821 !ib_is_udata_cleared(udata, required_ucmd_sz,
3822 udata->inlen - required_ucmd_sz))
3823 return ERR_PTR(-EOPNOTSUPP);
3824
3825 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3826 if (!ucmd)
3827 return ERR_PTR(-ENOMEM);
3828
3829 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
299eafee
GS		 3830 if (err)
3831 goto free_ucmd;
3b3233fb 3832 }
59082a32 3833
299eafee
GS		 3834 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3835 err = -ENOMEM;
3836 goto free_ucmd;
3837 }
038d2ef8
MG		 3838
3839 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3840 flow_attr->port > dev->num_ports ||
802c2125 3841 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
299eafee
GS		 3842 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3843 err = -EINVAL;
3844 goto free_ucmd;
3845 }
802c2125
AY		 3846
3847 if (is_egress &&
3848 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
299eafee
GS		 3849 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3850 err = -EINVAL;
3851 goto free_ucmd;
3852 }
038d2ef8
MG		 3853
3854 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
299eafee
GS		 3855 if (!dst) {
3856 err = -ENOMEM;
3857 goto free_ucmd;
3858 }
038d2ef8 3859
9a4ca38d 3860 mutex_lock(&dev->flow_db->lock);
038d2ef8 3861
802c2125
AY		 3862 ft_prio = get_flow_table(dev, flow_attr,
3863 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3864 if (IS_ERR(ft_prio)) {
3865 err = PTR_ERR(ft_prio);
3866 goto unlock;
3867 }
cc0e5d42
MG		 3868 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3869 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3870 if (IS_ERR(ft_prio_tx)) {
3871 err = PTR_ERR(ft_prio_tx);
3872 ft_prio_tx = NULL;
3873 goto destroy_ft;
3874 }
3875 }
038d2ef8 3876
802c2125
AY		 3877 if (is_egress) {
3878 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3879 } else {
3880 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3881 if (mqp->flags & MLX5_IB_QP_RSS)
3882 dst->tir_num = mqp->rss_qp.tirn;
3883 else
3884 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3885 }
038d2ef8
MG		 3886
3887 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3888 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3889 handler = create_dont_trap_rule(dev, ft_prio,
3890 flow_attr, dst);
3891 } else {
a550ddfc
YH		 3892 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3893 mqp->underlay_qpn : 0;
3894 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3b3233fb 3895 dst, underlay_qpn, ucmd);
35d19011 3896 }
038d2ef8
MG		 3897 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3898 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3899 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3900 dst);
cc0e5d42
MG		 3901 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3902 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3903 } else {
3904 err = -EINVAL;
3905 goto destroy_ft;
3906 }
3907
3908 if (IS_ERR(handler)) {
3909 err = PTR_ERR(handler);
3910 handler = NULL;
3911 goto destroy_ft;
3912 }
3913
9a4ca38d 3914 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3915 kfree(dst);
3b3233fb 3916 kfree(ucmd);
038d2ef8
MG		 3917
3918 return &handler->ibflow;
3919
3920destroy_ft:
3921 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3922 if (ft_prio_tx)
3923 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3924unlock:
9a4ca38d 3925 mutex_unlock(&dev->flow_db->lock);
038d2ef8 3926 kfree(dst);
299eafee 3927free_ucmd:
3b3233fb 3928 kfree(ucmd);
038d2ef8
MG		 3929 return ERR_PTR(err);
3930}
3931
b47fd4ff
MB		 3932static struct mlx5_ib_flow_prio *
3933_get_flow_table(struct mlx5_ib_dev *dev,
3934 struct mlx5_ib_flow_matcher *fs_matcher,
3935 bool mcast)
d4be3f44 3936{
d4be3f44 3937 struct mlx5_flow_namespace *ns = NULL;
13a43765
MB		 3938 struct mlx5_ib_flow_prio *prio = NULL;
3939 int max_table_size = 0;
cecae747 3940 bool esw_encap;
b47fd4ff
MB		 3941 u32 flags = 0;
3942 int priority;
3943
13a43765
MB		 3944 if (mcast)
3945 priority = MLX5_IB_FLOW_MCAST_PRIO;
3946 else
3947 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3948
cecae747
MG		 3949 esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3950 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
b47fd4ff
MB		 3951 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3952 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3953 log_max_ft_size));
cecae747 3954 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
b47fd4ff
MB		 3955 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3956 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
cecae747
MG		 3957 reformat_l3_tunnel_to_l2) &&
3958 !esw_encap)
b47fd4ff 3959 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3960 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3961 max_table_size = BIT(
3962 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
cecae747 3963 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
b47fd4ff 3964 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765
MB		 3965 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3966 max_table_size = BIT(
3967 MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
09d985be
MG		 3968 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3969 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3970 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3971 esw_encap)
3972 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
13a43765 3973 priority = FDB_BYPASS_PATH;
d8abe884
MZ		 3974 } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX) {
3975 max_table_size =
3976 BIT(MLX5_CAP_FLOWTABLE_RDMA_RX(dev->mdev,
3977 log_max_ft_size));
3978 priority = fs_matcher->priority;
b47fd4ff 3979 }
d4be3f44 3980
3b70508a 3981 max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
d4be3f44 3982
b47fd4ff 3983 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
d4be3f44
YH		 3984 if (!ns)
3985 return ERR_PTR(-ENOTSUPP);
3986
b47fd4ff
MB		 3987 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3988 prio = &dev->flow_db->prios[priority];
13a43765 3989 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
b47fd4ff 3990 prio = &dev->flow_db->egress_prios[priority];
13a43765
MB		 3991 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3992 prio = &dev->flow_db->fdb;
d8abe884
MZ		 3993 else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_RDMA_RX)
3994 prio = &dev->flow_db->rdma_rx[priority];
13a43765
MB		 3995
3996 if (!prio)
3997 return ERR_PTR(-EINVAL);
d4be3f44
YH		 3998
3999 if (prio->flow_table)
4000 return prio;
4001
3b70508a 4002 return _get_prio(ns, prio, priority, max_table_size,
b47fd4ff 4003 MLX5_FS_MAX_TYPES, flags);
d4be3f44
YH		 4004}
4005
4006static struct mlx5_ib_flow_handler *
4007_create_raw_flow_rule(struct mlx5_ib_dev *dev,
4008 struct mlx5_ib_flow_prio *ft_prio,
4009 struct mlx5_flow_destination *dst,
4010 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4011 struct mlx5_flow_context *flow_context,
b823dd6d 4012 struct mlx5_flow_act *flow_act,
bfc5d839
MB		 4013 void *cmd_in, int inlen,
4014 int dst_num)
d4be3f44
YH		 4015{
4016 struct mlx5_ib_flow_handler *handler;
d4be3f44
YH		 4017 struct mlx5_flow_spec *spec;
4018 struct mlx5_flow_table *ft = ft_prio->flow_table;
4019 int err = 0;
4020
4021 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4022 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4023 if (!handler || !spec) {
4024 err = -ENOMEM;
4025 goto free;
4026 }
4027
4028 INIT_LIST_HEAD(&handler->list);
4029
4030 memcpy(spec->match_value, cmd_in, inlen);
4031 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4032 fs_matcher->mask_len);
4033 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
bb0ee7dc 4034 spec->flow_context = *flow_context;
d4be3f44 4035
d4be3f44 4036 handler->rule = mlx5_add_flow_rules(ft, spec,
bfc5d839 4037 flow_act, dst, dst_num);
d4be3f44
YH		 4038
4039 if (IS_ERR(handler->rule)) {
4040 err = PTR_ERR(handler->rule);
4041 goto free;
4042 }
4043
4044 ft_prio->refcount++;
4045 handler->prio = ft_prio;
4046 handler->dev = dev;
4047 ft_prio->flow_table = ft;
4048
4049free:
4050 if (err)
4051 kfree(handler);
4052 kvfree(spec);
4053 return err ? ERR_PTR(err) : handler;
4054}
4055
4056static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4057 void *match_v)
4058{
4059 void *match_c;
4060 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4061 void *dmac, *dmac_mask;
4062 void *ipv4, *ipv4_mask;
4063
4064 if (!(fs_matcher->match_criteria_enable &
4065 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4066 return false;
4067
4068 match_c = fs_matcher->matcher_mask.match_params;
4069 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4070 outer_headers);
4071 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4072 outer_headers);
4073
4074 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4075 dmac_47_16);
4076 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4077 dmac_47_16);
4078
4079 if (is_multicast_ether_addr(dmac) &&
4080 is_multicast_ether_addr(dmac_mask))
4081 return true;
4082
4083 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4084 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4085
4086 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4087 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4088
4089 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4090 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4091 return true;
4092
4093 return false;
4094}
4095
32269441
YH		 4096struct mlx5_ib_flow_handler *
4097mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4098 struct mlx5_ib_flow_matcher *fs_matcher,
bb0ee7dc 4099 struct mlx5_flow_context *flow_context,
b823dd6d 4100 struct mlx5_flow_act *flow_act,
bfc5d839 4101 u32 counter_id,
32269441
YH		 4102 void *cmd_in, int inlen, int dest_id,
4103 int dest_type)
4104{
d4be3f44
YH		 4105 struct mlx5_flow_destination *dst;
4106 struct mlx5_ib_flow_prio *ft_prio;
d4be3f44 4107 struct mlx5_ib_flow_handler *handler;
bfc5d839 4108 int dst_num = 0;
d4be3f44
YH		 4109 bool mcast;
4110 int err;
4111
4112 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4113 return ERR_PTR(-EOPNOTSUPP);
4114
4115 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4116 return ERR_PTR(-ENOMEM);
4117
8e8aa145 4118 dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
d4be3f44
YH		 4119 if (!dst)
4120 return ERR_PTR(-ENOMEM);
4121
4122 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4123 mutex_lock(&dev->flow_db->lock);
4124
b47fd4ff 4125 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
d4be3f44
YH		 4126 if (IS_ERR(ft_prio)) {
4127 err = PTR_ERR(ft_prio);
4128 goto unlock;
4129 }
4130
6346f0bf 4131 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
bfc5d839
MB		 4132 dst[dst_num].type = dest_type;
4133 dst[dst_num].tir_num = dest_id;
b823dd6d 4134 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4135 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
bfc5d839
MB		 4136 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4137 dst[dst_num].ft_num = dest_id;
b823dd6d 4138 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
a7ee18bd 4139 } else {
bfc5d839 4140 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
a7ee18bd 4141 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
6346f0bf
YH		 4142 }
4143
bfc5d839
MB		 4144 dst_num++;
4145
4146 if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4147 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4148 dst[dst_num].counter_id = counter_id;
4149 dst_num++;
4150 }
4151
bb0ee7dc
JL		 4152 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4153 flow_context, flow_act,
bfc5d839 4154 cmd_in, inlen, dst_num);
d4be3f44
YH		 4155
4156 if (IS_ERR(handler)) {
4157 err = PTR_ERR(handler);
4158 goto destroy_ft;
4159 }
4160
4161 mutex_unlock(&dev->flow_db->lock);
4162 atomic_inc(&fs_matcher->usecnt);
4163 handler->flow_matcher = fs_matcher;
4164
4165 kfree(dst);
4166
4167 return handler;
4168
4169destroy_ft:
4170 put_flow_table(dev, ft_prio, false);
4171unlock:
4172 mutex_unlock(&dev->flow_db->lock);
4173 kfree(dst);
4174
4175 return ERR_PTR(err);
32269441
YH		 4176}
4177
c6475a0b
AY		 4178static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4179{
4180 u32 flags = 0;
4181
4182 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4183 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4184
4185 return flags;
4186}
4187
4188#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4189static struct ib_flow_action *
4190mlx5_ib_create_flow_action_esp(struct ib_device *device,
4191 const struct ib_flow_action_attrs_esp *attr,
4192 struct uverbs_attr_bundle *attrs)
4193{
4194 struct mlx5_ib_dev *mdev = to_mdev(device);
4195 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4196 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4197 struct mlx5_ib_flow_action *action;
4198 u64 action_flags;
4199 u64 flags;
4200 int err = 0;
4201
bccd0622
JG		 4202 err = uverbs_get_flags64(
4203 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4204 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4205 if (err)
4206 return ERR_PTR(err);
c6475a0b
AY		 4207
4208 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4209
4210 /* We current only support a subset of the standard features. Only a
4211 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4212 * (with overlap). Full offload mode isn't supported.
4213 */
4214 if (!attr->keymat || attr->replay || attr->encap ||
4215 attr->spi || attr->seq || attr->tfc_pad ||
4216 attr->hard_limit_pkts ||
4217 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4218 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4219 return ERR_PTR(-EOPNOTSUPP);
4220
4221 if (attr->keymat->protocol !=
4222 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4223 return ERR_PTR(-EOPNOTSUPP);
4224
4225 aes_gcm = &attr->keymat->keymat.aes_gcm;
4226
4227 if (aes_gcm->icv_len != 16 ||
4228 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4229 return ERR_PTR(-EOPNOTSUPP);
4230
4231 action = kmalloc(sizeof(*action), GFP_KERNEL);
4232 if (!action)
4233 return ERR_PTR(-ENOMEM);
4234
4235 action->esp_aes_gcm.ib_flags = attr->flags;
4236 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4237 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4238 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4239 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4240 sizeof(accel_attrs.keymat.aes_gcm.salt));
4241 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4242 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4243 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4244 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4245 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4246
4247 accel_attrs.esn = attr->esn;
4248 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4249 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4250 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4251 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4252
4253 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4254 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4255
4256 action->esp_aes_gcm.ctx =
4257 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4258 if (IS_ERR(action->esp_aes_gcm.ctx)) {
4259 err = PTR_ERR(action->esp_aes_gcm.ctx);
4260 goto err_parse;
4261 }
4262
4263 action->esp_aes_gcm.ib_flags = attr->flags;
4264
4265 return &action->ib_action;
4266
4267err_parse:
4268 kfree(action);
4269 return ERR_PTR(err);
4270}
4271
349705c1
MB		 4272static int
4273mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4274 const struct ib_flow_action_attrs_esp *attr,
4275 struct uverbs_attr_bundle *attrs)
4276{
4277 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4278 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4279 int err = 0;
4280
4281 if (attr->keymat || attr->replay || attr->encap ||
4282 attr->spi || attr->seq || attr->tfc_pad ||
4283 attr->hard_limit_pkts ||
4284 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4285 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4286 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4287 return -EOPNOTSUPP;
4288
4289 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4290 * be modified.
4291 */
4292 if (!(maction->esp_aes_gcm.ib_flags &
4293 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4294 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4295 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4296 return -EINVAL;
4297
4298 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4299 sizeof(accel_attrs));
4300
4301 accel_attrs.esn = attr->esn;
4302 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4303 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4304 else
4305 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4306
4307 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4308 &accel_attrs);
4309 if (err)
4310 return err;
4311
4312 maction->esp_aes_gcm.ib_flags &=
4313 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4314 maction->esp_aes_gcm.ib_flags |=
4315 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4316
4317 return 0;
4318}
4319
c6475a0b
AY		 4320static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4321{
4322 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4323
4324 switch (action->type) {
4325 case IB_FLOW_ACTION_ESP:
4326 /*
4327 * We only support aes_gcm by now, so we implicitly know this is
4328 * the underline crypto.
4329 */
4330 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4331 break;
b4749bf2
MB		 4332 case IB_FLOW_ACTION_UNSPECIFIED:
4333 mlx5_ib_destroy_flow_action_raw(maction);
4334 break;
c6475a0b
AY		 4335 default:
4336 WARN_ON(true);
4337 break;
4338 }
4339
4340 kfree(maction);
4341 return 0;
4342}
4343
e126ba97
EC		 4344static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4345{
4346 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 4347 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97 4348 int err;
539ec982
YH		 4349 u16 uid;
4350
4351 uid = ibqp->pd ?
4352 to_mpd(ibqp->pd)->uid : 0;
e126ba97 4353
81e30880
YH		 4354 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4355 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4356 return -EOPNOTSUPP;
4357 }
4358
539ec982 4359 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4360 if (err)
4361 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4362 ibqp->qp_num, gid->raw);
4363
4364 return err;
4365}
4366
4367static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4368{
4369 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4370 int err;
539ec982 4371 u16 uid;
e126ba97 4372
539ec982
YH		 4373 uid = ibqp->pd ?
4374 to_mpd(ibqp->pd)->uid : 0;
4375 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
e126ba97
EC		 4376 if (err)
4377 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4378 ibqp->qp_num, gid->raw);
4379
4380 return err;
4381}
4382
4383static int init_node_data(struct mlx5_ib_dev *dev)
4384{
1b5daf11 4385 int err;
e126ba97 4386
1b5daf11 4387 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 4388 if (err)
1b5daf11 4389 return err;
e126ba97 4390
1b5daf11 4391 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 4392
1b5daf11 4393 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 4394}
4395
508a523f
PP		 4396static ssize_t fw_pages_show(struct device *device,
4397 struct device_attribute *attr, char *buf)
e126ba97
EC		 4398{
4399 struct mlx5_ib_dev *dev =
54747231 4400 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4401
9603b61d 4402 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97 4403}
508a523f 4404static DEVICE_ATTR_RO(fw_pages);
e126ba97 4405
508a523f 4406static ssize_t reg_pages_show(struct device *device,
e126ba97
EC		 4407 struct device_attribute *attr, char *buf)
4408{
4409 struct mlx5_ib_dev *dev =
54747231 4410 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
e126ba97 4411
6aec21f6 4412 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97 4413}
508a523f 4414static DEVICE_ATTR_RO(reg_pages);
e126ba97 4415
508a523f
PP		 4416static ssize_t hca_type_show(struct device *device,
4417 struct device_attribute *attr, char *buf)
e126ba97
EC		 4418{
4419 struct mlx5_ib_dev *dev =
54747231
PP		 4420 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4421
9603b61d 4422 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97 4423}
508a523f 4424static DEVICE_ATTR_RO(hca_type);
e126ba97 4425
508a523f
PP		 4426static ssize_t hw_rev_show(struct device *device,
4427 struct device_attribute *attr, char *buf)
e126ba97
EC		 4428{
4429 struct mlx5_ib_dev *dev =
54747231
PP		 4430 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4431
9603b61d 4432 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97 4433}
508a523f 4434static DEVICE_ATTR_RO(hw_rev);
e126ba97 4435
508a523f
PP		 4436static ssize_t board_id_show(struct device *device,
4437 struct device_attribute *attr, char *buf)
e126ba97
EC		 4438{
4439 struct mlx5_ib_dev *dev =
54747231
PP		 4440 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4441
e126ba97 4442 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 4443 dev->mdev->board_id);
e126ba97 4444}
508a523f 4445static DEVICE_ATTR_RO(board_id);
e126ba97 4446
508a523f
PP		 4447static struct attribute *mlx5_class_attributes[] = {
4448 &dev_attr_hw_rev.attr,
4449 &dev_attr_hca_type.attr,
4450 &dev_attr_board_id.attr,
4451 &dev_attr_fw_pages.attr,
4452 &dev_attr_reg_pages.attr,
4453 NULL,
4454};
e126ba97 4455
508a523f
PP		 4456static const struct attribute_group mlx5_attr_group = {
4457 .attrs = mlx5_class_attributes,
e126ba97
EC		 4458};
4459
7722f47e
HE		 4460static void pkey_change_handler(struct work_struct *work)
4461{
4462 struct mlx5_ib_port_resources *ports =
4463 container_of(work, struct mlx5_ib_port_resources,
4464 pkey_change_work);
4465
4466 mutex_lock(&ports->devr->mutex);
4467 mlx5_ib_gsi_pkey_change(ports->gsi);
4468 mutex_unlock(&ports->devr->mutex);
4469}
4470
89ea94a7
MG		 4471static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4472{
4473 struct mlx5_ib_qp *mqp;
4474 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4475 struct mlx5_core_cq *mcq;
4476 struct list_head cq_armed_list;
4477 unsigned long flags_qp;
4478 unsigned long flags_cq;
4479 unsigned long flags;
4480
4481 INIT_LIST_HEAD(&cq_armed_list);
4482
4483 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4484 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4485 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4486 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4487 if (mqp->sq.tail != mqp->sq.head) {
4488 send_mcq = to_mcq(mqp->ibqp.send_cq);
4489 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4490 if (send_mcq->mcq.comp &&
4491 mqp->ibqp.send_cq->comp_handler) {
4492 if (!send_mcq->mcq.reset_notify_added) {
4493 send_mcq->mcq.reset_notify_added = 1;
4494 list_add_tail(&send_mcq->mcq.reset_notify,
4495 &cq_armed_list);
4496 }
4497 }
4498 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4499 }
4500 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4501 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4502 /* no handling is needed for SRQ */
4503 if (!mqp->ibqp.srq) {
4504 if (mqp->rq.tail != mqp->rq.head) {
4505 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4506 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4507 if (recv_mcq->mcq.comp &&
4508 mqp->ibqp.recv_cq->comp_handler) {
4509 if (!recv_mcq->mcq.reset_notify_added) {
4510 recv_mcq->mcq.reset_notify_added = 1;
4511 list_add_tail(&recv_mcq->mcq.reset_notify,
4512 &cq_armed_list);
4513 }
4514 }
4515 spin_unlock_irqrestore(&recv_mcq->lock,
4516 flags_cq);
4517 }
4518 }
4519 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4520 }
4521 /*At that point all inflight post send were put to be executed as of we
4522 * lock/unlock above locks Now need to arm all involved CQs.
4523 */
4524 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4e0e2ea1 4525 mcq->comp(mcq, NULL);
89ea94a7
MG		 4526 }
4527 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4528}
4529
03404e8a
MG		 4530static void delay_drop_handler(struct work_struct *work)
4531{
4532 int err;
4533 struct mlx5_ib_delay_drop *delay_drop =
4534 container_of(work, struct mlx5_ib_delay_drop,
4535 delay_drop_work);
4536
fe248c3a
MG		 4537 atomic_inc(&delay_drop->events_cnt);
4538
03404e8a
MG		 4539 mutex_lock(&delay_drop->lock);
4540 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4541 delay_drop->timeout);
4542 if (err) {
4543 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4544 delay_drop->timeout);
4545 delay_drop->activate = false;
4546 }
4547 mutex_unlock(&delay_drop->lock);
4548}
4549
09e574fa
SM		 4550static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4551 struct ib_event *ibev)
4552{
6cfdc7e4
AL		 4553 u8 port = (eqe->data.port.port >> 4) & 0xf;
4554
09e574fa
SM		 4555 switch (eqe->sub_type) {
4556 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
6cfdc7e4
AL		 4557 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4558 IB_LINK_LAYER_ETHERNET)
4559 schedule_work(&ibdev->delay_drop.delay_drop_work);
09e574fa
SM		 4560 break;
4561 default: /* do nothing */
4562 return;
4563 }
4564}
4565
134e9349
SM		 4566static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4567 struct ib_event *ibev)
4568{
4569 u8 port = (eqe->data.port.port >> 4) & 0xf;
4570
4571 ibev->element.port_num = port;
4572
4573 switch (eqe->sub_type) {
4574 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4575 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4576 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4577 /* In RoCE, port up/down events are handled in
4578 * mlx5_netdev_event().
4579 */
4580 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4581 IB_LINK_LAYER_ETHERNET)
4582 return -EINVAL;
4583
4584 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4585 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4586 break;
4587
4588 case MLX5_PORT_CHANGE_SUBTYPE_LID:
4589 ibev->event = IB_EVENT_LID_CHANGE;
4590 break;
4591
4592 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4593 ibev->event = IB_EVENT_PKEY_CHANGE;
4594 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4595 break;
4596
4597 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4598 ibev->event = IB_EVENT_GID_CHANGE;
4599 break;
4600
4601 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4602 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4603 break;
4604 default:
4605 return -EINVAL;
4606 }
4607
4608 return 0;
4609}
4610
d69a24e0 4611static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 4612{
d69a24e0
DJ		 4613 struct mlx5_ib_event_work *work =
4614 container_of(_work, struct mlx5_ib_event_work, work);
4615 struct mlx5_ib_dev *ibdev;
e126ba97 4616 struct ib_event ibev;
dbaaff2a 4617 bool fatal = false;
e126ba97 4618
df097a27
SM		 4619 if (work->is_slave) {
4620 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
d69a24e0
DJ		 4621 if (!ibdev)
4622 goto out;
4623 } else {
df097a27 4624 ibdev = work->dev;
d69a24e0
DJ		 4625 }
4626
4627 switch (work->event) {
e126ba97 4628 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 4629 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 4630 mlx5_ib_handle_internal_error(ibdev);
134e9349 4631 ibev.element.port_num = (u8)(unsigned long)work->param;
dbaaff2a 4632 fatal = true;
e126ba97 4633 break;
134e9349
SM		 4634 case MLX5_EVENT_TYPE_PORT_CHANGE:
4635 if (handle_port_change(ibdev, work->param, &ibev))
d69a24e0 4636 goto out;
e126ba97 4637 break;
09e574fa
SM		 4638 case MLX5_EVENT_TYPE_GENERAL_EVENT:
4639 handle_general_event(ibdev, work->param, &ibev);
4640 /* fall through */
bdc37924 4641 default:
03404e8a 4642 goto out;
e126ba97
EC		 4643 }
4644
134e9349 4645 ibev.device = &ibdev->ib_dev;
e126ba97 4646
134e9349
SM		 4647 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4648 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
03404e8a 4649 goto out;
a0c84c32
EC		 4650 }
4651
e126ba97
EC		 4652 if (ibdev->ib_active)
4653 ib_dispatch_event(&ibev);
dbaaff2a
EC		 4654
4655 if (fatal)
4656 ibdev->ib_active = false;
03404e8a 4657out:
d69a24e0
DJ		 4658 kfree(work);
4659}
4660
df097a27
SM		 4661static int mlx5_ib_event(struct notifier_block *nb,
4662 unsigned long event, void *param)
d69a24e0
DJ		 4663{
4664 struct mlx5_ib_event_work *work;
4665
4666 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 4667 if (!work)
df097a27 4668 return NOTIFY_DONE;
d69a24e0 4669
10bea9c8 4670 INIT_WORK(&work->work, mlx5_ib_handle_event);
df097a27
SM		 4671 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4672 work->is_slave = false;
10bea9c8 4673 work->param = param;
10bea9c8
LR		 4674 work->event = event;
4675
4676 queue_work(mlx5_ib_event_wq, &work->work);
df097a27
SM		 4677
4678 return NOTIFY_OK;
4679}
4680
4681static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4682 unsigned long event, void *param)
4683{
4684 struct mlx5_ib_event_work *work;
4685
4686 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4687 if (!work)
4688 return NOTIFY_DONE;
4689
4690 INIT_WORK(&work->work, mlx5_ib_handle_event);
4691 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4692 work->is_slave = true;
4693 work->param = param;
4694 work->event = event;
4695 queue_work(mlx5_ib_event_wq, &work->work);
4696
4697 return NOTIFY_OK;
e126ba97
EC		 4698}
4699
c43f1112
MG		 4700static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4701{
4702 struct mlx5_hca_vport_context vport_ctx;
4703 int err;
4704 int port;
4705
a989ea01 4706 for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
c43f1112
MG		 4707 dev->mdev->port_caps[port - 1].has_smi = false;
4708 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4709 MLX5_CAP_PORT_TYPE_IB) {
4710 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4711 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4712 port, 0,
4713 &vport_ctx);
4714 if (err) {
4715 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4716 port, err);
4717 return err;
4718 }
4719 dev->mdev->port_caps[port - 1].has_smi =
4720 vport_ctx.has_smi;
4721 } else {
4722 dev->mdev->port_caps[port - 1].has_smi = true;
4723 }
4724 }
4725 }
4726 return 0;
4727}
4728
e126ba97
EC		 4729static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4730{
4731 int port;
4732
508562d6 4733 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 4734 mlx5_query_ext_port_caps(dev, port);
4735}
4736
26628e2d 4737static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 4738{
4739 struct ib_device_attr *dprops = NULL;
4740 struct ib_port_attr *pprops = NULL;
f614fc15 4741 int err = -ENOMEM;
e126ba97 4742
50ba3c18 4743 pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
e126ba97
EC		 4744 if (!pprops)
4745 goto out;
4746
4747 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4748 if (!dprops)
4749 goto out;
4750
759be092 4751 err = mlx5_ib_query_device(&dev->ib_dev, dprops, NULL);
e126ba97
EC		 4752 if (err) {
4753 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4754 goto out;
4755 }
4756
32f69e4b
DJ		 4757 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4758 if (err) {
4759 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4760 port, err);
4761 goto out;
e126ba97
EC		 4762 }
4763
32f69e4b
DJ		 4764 dev->mdev->port_caps[port - 1].pkey_table_len =
4765 dprops->max_pkeys;
4766 dev->mdev->port_caps[port - 1].gid_table_len =
4767 pprops->gid_tbl_len;
4768 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4769 port, dprops->max_pkeys, pprops->gid_tbl_len);
4770
e126ba97
EC		 4771out:
4772 kfree(pprops);
4773 kfree(dprops);
4774
4775 return err;
4776}
4777
26628e2d
MB		 4778static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4779{
4780 /* For representors use port 1, is this is the only native
4781 * port
4782 */
4783 if (dev->is_rep)
4784 return __get_port_caps(dev, 1);
4785 return __get_port_caps(dev, port);
4786}
4787
e126ba97
EC		 4788static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4789{
4790 int err;
4791
4792 err = mlx5_mr_cache_cleanup(dev);
4793 if (err)
4794 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4795
32927e28 4796 if (dev->umrc.qp)
c4367a26 4797 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
32927e28
MB		 4798 if (dev->umrc.cq)
4799 ib_free_cq(dev->umrc.cq);
4800 if (dev->umrc.pd)
4801 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 4802}
4803
4804enum {
4805 MAX_UMR_WR = 128,
4806};
4807
4808static int create_umr_res(struct mlx5_ib_dev *dev)
4809{
4810 struct ib_qp_init_attr *init_attr = NULL;
4811 struct ib_qp_attr *attr = NULL;
4812 struct ib_pd *pd;
4813 struct ib_cq *cq;
4814 struct ib_qp *qp;
e126ba97
EC		 4815 int ret;
4816
4817 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4818 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4819 if (!attr || !init_attr) {
4820 ret = -ENOMEM;
4821 goto error_0;
4822 }
4823
ed082d36 4824 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 4825 if (IS_ERR(pd)) {
4826 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4827 ret = PTR_ERR(pd);
4828 goto error_0;
4829 }
4830
add08d76 4831 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 4832 if (IS_ERR(cq)) {
4833 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4834 ret = PTR_ERR(cq);
4835 goto error_2;
4836 }
e126ba97
EC		 4837
4838 init_attr->send_cq = cq;
4839 init_attr->recv_cq = cq;
4840 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4841 init_attr->cap.max_send_wr = MAX_UMR_WR;
4842 init_attr->cap.max_send_sge = 1;
4843 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4844 init_attr->port_num = 1;
4845 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4846 if (IS_ERR(qp)) {
4847 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4848 ret = PTR_ERR(qp);
4849 goto error_3;
4850 }
4851 qp->device = &dev->ib_dev;
4852 qp->real_qp = qp;
4853 qp->uobject = NULL;
4854 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 4855 qp->send_cq = init_attr->send_cq;
4856 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 4857
4858 attr->qp_state = IB_QPS_INIT;
4859 attr->port_num = 1;
4860 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4861 IB_QP_PORT, NULL);
4862 if (ret) {
4863 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4864 goto error_4;
4865 }
4866
4867 memset(attr, 0, sizeof(*attr));
4868 attr->qp_state = IB_QPS_RTR;
4869 attr->path_mtu = IB_MTU_256;
4870
4871 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4872 if (ret) {
4873 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4874 goto error_4;
4875 }
4876
4877 memset(attr, 0, sizeof(*attr));
4878 attr->qp_state = IB_QPS_RTS;
4879 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4880 if (ret) {
4881 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4882 goto error_4;
4883 }
4884
4885 dev->umrc.qp = qp;
4886 dev->umrc.cq = cq;
e126ba97
EC		 4887 dev->umrc.pd = pd;
4888
4889 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4890 ret = mlx5_mr_cache_init(dev);
4891 if (ret) {
4892 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4893 goto error_4;
4894 }
4895
4896 kfree(attr);
4897 kfree(init_attr);
4898
4899 return 0;
4900
4901error_4:
c4367a26 4902 mlx5_ib_destroy_qp(qp, NULL);
32927e28 4903 dev->umrc.qp = NULL;
e126ba97
EC		 4904
4905error_3:
add08d76 4906 ib_free_cq(cq);
32927e28 4907 dev->umrc.cq = NULL;
e126ba97
EC		 4908
4909error_2:
e126ba97 4910 ib_dealloc_pd(pd);
32927e28 4911 dev->umrc.pd = NULL;
e126ba97
EC		 4912
4913error_0:
4914 kfree(attr);
4915 kfree(init_attr);
4916 return ret;
4917}
4918
6e8484c5
MG		 4919static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4920{
4921 switch (umr_fence_cap) {
4922 case MLX5_CAP_UMR_FENCE_NONE:
4923 return MLX5_FENCE_MODE_NONE;
4924 case MLX5_CAP_UMR_FENCE_SMALL:
4925 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4926 default:
4927 return MLX5_FENCE_MODE_STRONG_ORDERING;
4928 }
4929}
4930
e126ba97
EC		 4931static int create_dev_resources(struct mlx5_ib_resources *devr)
4932{
4933 struct ib_srq_init_attr attr;
4934 struct mlx5_ib_dev *dev;
21a428a0 4935 struct ib_device *ibdev;
bcf4c1ea 4936 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4937 int port;
e126ba97
EC		 4938 int ret = 0;
4939
4940 dev = container_of(devr, struct mlx5_ib_dev, devr);
21a428a0 4941 ibdev = &dev->ib_dev;
e126ba97 4942
d16e91da
HE		 4943 mutex_init(&devr->mutex);
4944
21a428a0
LR		 4945 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4946 if (!devr->p0)
4947 return -ENOMEM;
4948
4949 devr->p0->device = ibdev;
e126ba97
EC		 4950 devr->p0->uobject = NULL;
4951 atomic_set(&devr->p0->usecnt, 0);
4952
ff23dfa1 4953 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
21a428a0
LR		 4954 if (ret)
4955 goto error0;
4956
e39afe3d
LR		 4957 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4958 if (!devr->c0) {
4959 ret = -ENOMEM;
e126ba97
EC		 4960 goto error1;
4961 }
e39afe3d
LR		 4962
4963 devr->c0->device = &dev->ib_dev;
e126ba97
EC		 4964 atomic_set(&devr->c0->usecnt, 0);
4965
e39afe3d
LR		 4966 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4967 if (ret)
4968 goto err_create_cq;
4969
ff23dfa1 4970 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4971 if (IS_ERR(devr->x0)) {
4972 ret = PTR_ERR(devr->x0);
4973 goto error2;
4974 }
4975 devr->x0->device = &dev->ib_dev;
4976 devr->x0->inode = NULL;
4977 atomic_set(&devr->x0->usecnt, 0);
4978 mutex_init(&devr->x0->tgt_qp_mutex);
4979 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4980
ff23dfa1 4981 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
e126ba97
EC		 4982 if (IS_ERR(devr->x1)) {
4983 ret = PTR_ERR(devr->x1);
4984 goto error3;
4985 }
4986 devr->x1->device = &dev->ib_dev;
4987 devr->x1->inode = NULL;
4988 atomic_set(&devr->x1->usecnt, 0);
4989 mutex_init(&devr->x1->tgt_qp_mutex);
4990 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4991
4992 memset(&attr, 0, sizeof(attr));
4993 attr.attr.max_sge = 1;
4994 attr.attr.max_wr = 1;
4995 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4996 attr.ext.cq = devr->c0;
e126ba97
EC		 4997 attr.ext.xrc.xrcd = devr->x0;
4998
68e326de
LR		 4999 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5000 if (!devr->s0) {
5001 ret = -ENOMEM;
e126ba97
EC		 5002 goto error4;
5003 }
68e326de 5004
e126ba97
EC		 5005 devr->s0->device = &dev->ib_dev;
5006 devr->s0->pd = devr->p0;
e126ba97
EC		 5007 devr->s0->srq_type = IB_SRQT_XRC;
5008 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 5009 devr->s0->ext.cq = devr->c0;
68e326de
LR		 5010 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5011 if (ret)
5012 goto err_create;
5013
e126ba97 5014 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 5015 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 5016 atomic_inc(&devr->p0->usecnt);
5017 atomic_set(&devr->s0->usecnt, 0);
5018
4aa17b28
HA		 5019 memset(&attr, 0, sizeof(attr));
5020 attr.attr.max_sge = 1;
5021 attr.attr.max_wr = 1;
5022 attr.srq_type = IB_SRQT_BASIC;
68e326de
LR		 5023 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5024 if (!devr->s1) {
5025 ret = -ENOMEM;
4aa17b28
HA		 5026 goto error5;
5027 }
68e326de 5028
4aa17b28
HA		 5029 devr->s1->device = &dev->ib_dev;
5030 devr->s1->pd = devr->p0;
4aa17b28 5031 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 5032 devr->s1->ext.cq = devr->c0;
68e326de
LR		 5033
5034 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5035 if (ret)
5036 goto error6;
5037
4aa17b28 5038 atomic_inc(&devr->p0->usecnt);
1a56ff6d 5039 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 5040
7722f47e
HE		 5041 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5042 INIT_WORK(&devr->ports[port].pkey_change_work,
5043 pkey_change_handler);
5044 devr->ports[port].devr = devr;
5045 }
5046
e126ba97
EC		 5047 return 0;
5048
68e326de
LR		 5049error6:
5050 kfree(devr->s1);
4aa17b28 5051error5:
c4367a26 5052 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de
LR		 5053err_create:
5054 kfree(devr->s0);
e126ba97 5055error4:
c4367a26 5056 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
e126ba97 5057error3:
c4367a26 5058 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
e126ba97 5059error2:
c4367a26 5060 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d
LR		 5061err_create_cq:
5062 kfree(devr->c0);
e126ba97 5063error1:
c4367a26 5064 mlx5_ib_dealloc_pd(devr->p0, NULL);
e126ba97 5065error0:
21a428a0 5066 kfree(devr->p0);
e126ba97
EC		 5067 return ret;
5068}
5069
5070static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5071{
7722f47e
HE		 5072 int port;
5073
c4367a26 5074 mlx5_ib_destroy_srq(devr->s1, NULL);
68e326de 5075 kfree(devr->s1);
c4367a26 5076 mlx5_ib_destroy_srq(devr->s0, NULL);
68e326de 5077 kfree(devr->s0);
c4367a26
SR		 5078 mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5079 mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5080 mlx5_ib_destroy_cq(devr->c0, NULL);
e39afe3d 5081 kfree(devr->c0);
c4367a26 5082 mlx5_ib_dealloc_pd(devr->p0, NULL);
21a428a0 5083 kfree(devr->p0);
7722f47e
HE		 5084
5085 /* Make sure no change P_Key work items are still executing */
5d8f6a0e 5086 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
7722f47e 5087 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 5088}
5089
b02289b3
AK		 5090static u32 get_core_cap_flags(struct ib_device *ibdev,
5091 struct mlx5_hca_vport_context *rep)
e53505a8
AS		 5092{
5093 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5094 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5095 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5096 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 5097 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 5098 u32 ret = 0;
5099
b02289b3
AK		 5100 if (rep->grh_required)
5101 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5102
e53505a8 5103 if (ll == IB_LINK_LAYER_INFINIBAND)
b02289b3 5104 return ret | RDMA_CORE_PORT_IBA_IB;
e53505a8 5105
85c7c014 5106 if (raw_support)
b02289b3 5107 ret |= RDMA_CORE_PORT_RAW_PACKET;
72cd5717 5108
e53505a8 5109 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 5110 return ret;
e53505a8
AS		 5111
5112 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 5113 return ret;
e53505a8
AS		 5114
5115 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5116 ret |= RDMA_CORE_PORT_IBA_ROCE;
5117
5118 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5119 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5120
5121 return ret;
5122}
5123
7738613e
IW		 5124static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5125 struct ib_port_immutable *immutable)
5126{
5127 struct ib_port_attr attr;
ca5b91d6
OG		 5128 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5129 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
b02289b3 5130 struct mlx5_hca_vport_context rep = {0};
7738613e
IW		 5131 int err;
5132
c4550c63 5133 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 5134 if (err)
5135 return err;
5136
b02289b3
AK		 5137 if (ll == IB_LINK_LAYER_INFINIBAND) {
5138 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5139 &rep);
5140 if (err)
5141 return err;
5142 }
5143
7738613e
IW		 5144 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5145 immutable->gid_tbl_len = attr.gid_tbl_len;
b02289b3 5146 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
0e73e016 5147 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 5148
5149 return 0;
5150}
5151
8e6efa3a
MB		 5152static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5153 struct ib_port_immutable *immutable)
5154{
5155 struct ib_port_attr attr;
5156 int err;
5157
5158 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5159
5160 err = ib_query_port(ibdev, port_num, &attr);
5161 if (err)
5162 return err;
5163
5164 immutable->pkey_tbl_len = attr.pkey_tbl_len;
5165 immutable->gid_tbl_len = attr.gid_tbl_len;
5166 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5167
5168 return 0;
5169}
5170
9abb0d1b 5171static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 5172{
5173 struct mlx5_ib_dev *dev =
5174 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 5175 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5176 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5177 fw_rev_sub(dev->mdev));
c7342823
IW		 5178}
5179
45f95acd 5180static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5181{
5182 struct mlx5_core_dev *mdev = dev->mdev;
5183 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5184 MLX5_FLOW_NAMESPACE_LAG);
5185 struct mlx5_flow_table *ft;
5186 int err;
5187
7c34ec19 5188 if (!ns || !mlx5_lag_is_roce(mdev))
9ef9c640
AH		 5189 return 0;
5190
5191 err = mlx5_cmd_create_vport_lag(mdev);
5192 if (err)
5193 return err;
5194
5195 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5196 if (IS_ERR(ft)) {
5197 err = PTR_ERR(ft);
5198 goto err_destroy_vport_lag;
5199 }
5200
9a4ca38d 5201 dev->flow_db->lag_demux_ft = ft;
7c34ec19 5202 dev->lag_active = true;
9ef9c640
AH		 5203 return 0;
5204
5205err_destroy_vport_lag:
5206 mlx5_cmd_destroy_vport_lag(mdev);
5207 return err;
5208}
5209
45f95acd 5210static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 5211{
5212 struct mlx5_core_dev *mdev = dev->mdev;
5213
7c34ec19
AH		 5214 if (dev->lag_active) {
5215 dev->lag_active = false;
5216
9a4ca38d
MB		 5217 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5218 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 5219
5220 mlx5_cmd_destroy_vport_lag(mdev);
5221 }
5222}
5223
7fd8aefb 5224static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 5225{
5226 int err;
5227
95579e78
MB		 5228 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5229 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
d012f5d6 5230 if (err) {
95579e78 5231 dev->port[port_num].roce.nb.notifier_call = NULL;
d012f5d6
OG		 5232 return err;
5233 }
5234
5235 return 0;
5236}
5237
7fd8aefb 5238static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 5239{
95579e78
MB		 5240 if (dev->port[port_num].roce.nb.notifier_call) {
5241 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5242 dev->port[port_num].roce.nb.notifier_call = NULL;
5ec8c83e
AH		 5243 }
5244}
5245
e3f1ed1f 5246static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5247{
e53505a8
AS		 5248 int err;
5249
0e73e016
MG		 5250 err = mlx5_nic_vport_enable_roce(dev->mdev);
5251 if (err)
5252 return err;
e53505a8 5253
45f95acd 5254 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 5255 if (err)
5256 goto err_disable_roce;
5257
e53505a8
AS		 5258 return 0;
5259
9ef9c640 5260err_disable_roce:
0e73e016 5261 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 5262
e53505a8 5263 return err;
fc24fc5e
AS		 5264}
5265
45f95acd 5266static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 5267{
45f95acd 5268 mlx5_eth_lag_cleanup(dev);
0e73e016 5269 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 5270}
5271
e1f24a79 5272struct mlx5_ib_counter {
7c16f477
KH		 5273 const char *name;
5274 size_t offset;
5275};
5276
5277#define INIT_Q_COUNTER(_name) \
5278 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5279
e1f24a79 5280static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 5281 INIT_Q_COUNTER(rx_write_requests),
5282 INIT_Q_COUNTER(rx_read_requests),
5283 INIT_Q_COUNTER(rx_atomic_requests),
5284 INIT_Q_COUNTER(out_of_buffer),
5285};
5286
e1f24a79 5287static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 5288 INIT_Q_COUNTER(out_of_sequence),
5289};
5290
e1f24a79 5291static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 5292 INIT_Q_COUNTER(duplicate_request),
5293 INIT_Q_COUNTER(rnr_nak_retry_err),
5294 INIT_Q_COUNTER(packet_seq_err),
5295 INIT_Q_COUNTER(implied_nak_seq_err),
5296 INIT_Q_COUNTER(local_ack_timeout_err),
5297};
5298
e1f24a79
PP		 5299#define INIT_CONG_COUNTER(_name) \
5300 { .name = #_name, .offset = \
5301 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5302
5303static const struct mlx5_ib_counter cong_cnts[] = {
5304 INIT_CONG_COUNTER(rp_cnp_ignored),
5305 INIT_CONG_COUNTER(rp_cnp_handled),
5306 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5307 INIT_CONG_COUNTER(np_cnp_sent),
5308};
5309
58dcb60a
PP		 5310static const struct mlx5_ib_counter extended_err_cnts[] = {
5311 INIT_Q_COUNTER(resp_local_length_error),
5312 INIT_Q_COUNTER(resp_cqe_error),
5313 INIT_Q_COUNTER(req_cqe_error),
5314 INIT_Q_COUNTER(req_remote_invalid_request),
5315 INIT_Q_COUNTER(req_remote_access_errors),
5316 INIT_Q_COUNTER(resp_remote_access_errors),
5317 INIT_Q_COUNTER(resp_cqe_flush_error),
5318 INIT_Q_COUNTER(req_cqe_flush_error),
5319};
5320
9f876f3d
TB		 5321#define INIT_EXT_PPCNT_COUNTER(_name) \
5322 { .name = #_name, .offset = \
5323 MLX5_BYTE_OFF(ppcnt_reg, \
5324 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5325
5326static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5327 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5328};
5329
3e1f000f
PP		 5330static bool is_mdev_switchdev_mode(const struct mlx5_core_dev *mdev)
5331{
5332 return MLX5_ESWITCH_MANAGER(mdev) &&
5333 mlx5_ib_eswitch_mode(mdev->priv.eswitch) ==
5334 MLX5_ESWITCH_OFFLOADS;
5335}
5336
e1f24a79 5337static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5338{
3e1f000f 5339 int num_cnt_ports;
aac4492e 5340 int i;
0837e86a 5341
3e1f000f
PP		 5342 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
5343
5344 for (i = 0; i < num_cnt_ports; i++) {
921c0f5b 5345 if (dev->port[i].cnts.set_id_valid)
aac4492e
DJ		 5346 mlx5_core_dealloc_q_counter(dev->mdev,
5347 dev->port[i].cnts.set_id);
e1f24a79
PP		 5348 kfree(dev->port[i].cnts.names);
5349 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 5350 }
5351}
5352
e1f24a79
PP		 5353static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5354 struct mlx5_ib_counters *cnts)
7c16f477
KH		 5355{
5356 u32 num_counters;
5357
5358 num_counters = ARRAY_SIZE(basic_q_cnts);
5359
5360 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5361 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5362
5363 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5364 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 5365
5366 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5367 num_counters += ARRAY_SIZE(extended_err_cnts);
5368
e1f24a79 5369 cnts->num_q_counters = num_counters;
7c16f477 5370
e1f24a79
PP		 5371 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5372 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5373 num_counters += ARRAY_SIZE(cong_cnts);
5374 }
9f876f3d
TB		 5375 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5376 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5377 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5378 }
e1f24a79
PP		 5379 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5380 if (!cnts->names)
7c16f477
KH		 5381 return -ENOMEM;
5382
e1f24a79
PP		 5383 cnts->offsets = kcalloc(num_counters,
5384 sizeof(cnts->offsets), GFP_KERNEL);
5385 if (!cnts->offsets)
7c16f477
KH		 5386 goto err_names;
5387
7c16f477
KH		 5388 return 0;
5389
5390err_names:
e1f24a79 5391 kfree(cnts->names);
aac4492e 5392 cnts->names = NULL;
7c16f477
KH		 5393 return -ENOMEM;
5394}
5395
e1f24a79
PP		 5396static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5397 const char **names,
5398 size_t *offsets)
7c16f477
KH		 5399{
5400 int i;
5401 int j = 0;
5402
5403 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5404 names[j] = basic_q_cnts[i].name;
5405 offsets[j] = basic_q_cnts[i].offset;
5406 }
5407
5408 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5409 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5410 names[j] = out_of_seq_q_cnts[i].name;
5411 offsets[j] = out_of_seq_q_cnts[i].offset;
5412 }
5413 }
5414
5415 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5416 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5417 names[j] = retrans_q_cnts[i].name;
5418 offsets[j] = retrans_q_cnts[i].offset;
5419 }
5420 }
e1f24a79 5421
58dcb60a
PP		 5422 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5423 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5424 names[j] = extended_err_cnts[i].name;
5425 offsets[j] = extended_err_cnts[i].offset;
5426 }
5427 }
5428
e1f24a79
PP		 5429 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5430 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5431 names[j] = cong_cnts[i].name;
5432 offsets[j] = cong_cnts[i].offset;
5433 }
5434 }
9f876f3d
TB		 5435
5436 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5437 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5438 names[j] = ext_ppcnt_cnts[i].name;
5439 offsets[j] = ext_ppcnt_cnts[i].offset;
5440 }
5441 }
0837e86a
MB		 5442}
5443
e1f24a79 5444static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 5445{
3e1f000f 5446 int num_cnt_ports;
aac4492e 5447 int err = 0;
0837e86a 5448 int i;
aa74be6e
YH		 5449 bool is_shared;
5450
5451 is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
3e1f000f 5452 num_cnt_ports = is_mdev_switchdev_mode(dev->mdev) ? 1 : dev->num_ports;
0837e86a 5453
3e1f000f 5454 for (i = 0; i < num_cnt_ports; i++) {
aac4492e
DJ		 5455 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5456 if (err)
5457 goto err_alloc;
5458
5459 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5460 dev->port[i].cnts.offsets);
7c16f477 5461
aa74be6e
YH		 5462 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5463 &dev->port[i].cnts.set_id,
5464 is_shared ?
5465 MLX5_SHARED_RESOURCE_UID : 0);
aac4492e 5466 if (err) {
0837e86a
MB		 5467 mlx5_ib_warn(dev,
5468 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 5469 i + 1, err);
5470 goto err_alloc;
0837e86a 5471 }
aac4492e 5472 dev->port[i].cnts.set_id_valid = true;
0837e86a 5473 }
0837e86a
MB		 5474 return 0;
5475
aac4492e
DJ		 5476err_alloc:
5477 mlx5_ib_dealloc_counters(dev);
5478 return err;
0837e86a
MB		 5479}
5480
3e1f000f
PP		 5481static const struct mlx5_ib_counters *get_counters(struct mlx5_ib_dev *dev,
5482 u8 port_num)
5483{
5484 return is_mdev_switchdev_mode(dev->mdev) ? &dev->port[0].cnts :
5485 &dev->port[port_num].cnts;
5486}
5487
5488/**
5489 * mlx5_ib_get_counters_id - Returns counters id to use for device+port
5490 * @dev: Pointer to mlx5 IB device
5491 * @port_num: Zero based port number
5492 *
5493 * mlx5_ib_get_counters_id() Returns counters set id to use for given
5494 * device port combination in switchdev and non switchdev mode of the
5495 * parent device.
5496 */
5497u16 mlx5_ib_get_counters_id(struct mlx5_ib_dev *dev, u8 port_num)
5498{
5499 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num);
5500
5501 return cnts->set_id;
5502}
5503
0ad17a8f
MB		 5504static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5505 u8 port_num)
5506{
7c16f477 5507 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f
PP		 5508 const struct mlx5_ib_counters *cnts;
5509 bool is_switchdev = is_mdev_switchdev_mode(dev->mdev);
0ad17a8f 5510
3e1f000f 5511 if ((is_switchdev && port_num) || (!is_switchdev && !port_num))
0ad17a8f
MB		 5512 return NULL;
5513
3e1f000f
PP		 5514 cnts = get_counters(dev, port_num - 1);
5515
5dcecbc9
PP		 5516 return rdma_alloc_hw_stats_struct(cnts->names,
5517 cnts->num_q_counters +
5518 cnts->num_cong_counters +
5519 cnts->num_ext_ppcnt_counters,
0ad17a8f
MB		 5520 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5521}
5522
aac4492e 5523static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5dcecbc9 5524 const struct mlx5_ib_counters *cnts,
318d535c
MZ		 5525 struct rdma_hw_stats *stats,
5526 u16 set_id)
0ad17a8f 5527{
0ad17a8f
MB		 5528 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5529 void *out;
5530 __be32 val;
e1f24a79 5531 int ret, i;
0ad17a8f 5532
1b9a07ee 5533 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 5534 if (!out)
5535 return -ENOMEM;
5536
318d535c 5537 ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
0ad17a8f
MB		 5538 if (ret)
5539 goto free;
5540
5dcecbc9
PP		 5541 for (i = 0; i < cnts->num_q_counters; i++) {
5542 val = *(__be32 *)(out + cnts->offsets[i]);
0ad17a8f
MB		 5543 stats->value[i] = (u64)be32_to_cpu(val);
5544 }
7c16f477 5545
0ad17a8f
MB		 5546free:
5547 kvfree(out);
e1f24a79
PP		 5548 return ret;
5549}
5550
9f876f3d 5551static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5dcecbc9
PP		 5552 const struct mlx5_ib_counters *cnts,
5553 struct rdma_hw_stats *stats)
9f876f3d 5554{
5dcecbc9 5555 int offset = cnts->num_q_counters + cnts->num_cong_counters;
9f876f3d
TB		 5556 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5557 int ret, i;
5558 void *out;
5559
5560 out = kvzalloc(sz, GFP_KERNEL);
5561 if (!out)
5562 return -ENOMEM;
5563
5564 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5565 if (ret)
5566 goto free;
5567
5dcecbc9 5568 for (i = 0; i < cnts->num_ext_ppcnt_counters; i++)
9f876f3d
TB		 5569 stats->value[i + offset] =
5570 be64_to_cpup((__be64 *)(out +
5dcecbc9 5571 cnts->offsets[i + offset]));
9f876f3d
TB		 5572free:
5573 kvfree(out);
5574 return ret;
5575}
5576
e1f24a79
PP		 5577static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5578 struct rdma_hw_stats *stats,
5579 u8 port_num, int index)
5580{
5581 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3e1f000f 5582 const struct mlx5_ib_counters *cnts = get_counters(dev, port_num - 1);
aac4492e 5583 struct mlx5_core_dev *mdev;
e1f24a79 5584 int ret, num_counters;
aac4492e 5585 u8 mdev_port_num;
e1f24a79
PP		 5586
5587 if (!stats)
5588 return -EINVAL;
5589
5dcecbc9
PP		 5590 num_counters = cnts->num_q_counters +
5591 cnts->num_cong_counters +
5592 cnts->num_ext_ppcnt_counters;
aac4492e
DJ		 5593
5594 /* q_counters are per IB device, query the master mdev */
5dcecbc9 5595 ret = mlx5_ib_query_q_counters(dev->mdev, cnts, stats, cnts->set_id);
e1f24a79
PP		 5596 if (ret)
5597 return ret;
e1f24a79 5598
9f876f3d 5599 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5dcecbc9 5600 ret = mlx5_ib_query_ext_ppcnt_counters(dev, cnts, stats);
9f876f3d
TB		 5601 if (ret)
5602 return ret;
5603 }
5604
e1f24a79 5605 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 5606 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5607 &mdev_port_num);
5608 if (!mdev) {
5609 /* If port is not affiliated yet, its in down state
5610 * which doesn't have any counters yet, so it would be
5611 * zero. So no need to read from the HCA.
5612 */
5613 goto done;
5614 }
71a0ff65
MD		 5615 ret = mlx5_lag_query_cong_counters(dev->mdev,
5616 stats->value +
5dcecbc9
PP		 5617 cnts->num_q_counters,
5618 cnts->num_cong_counters,
5619 cnts->offsets +
5620 cnts->num_q_counters);
aac4492e
DJ		 5621
5622 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 5623 if (ret)
5624 return ret;
e1f24a79
PP		 5625 }
5626
aac4492e 5627done:
e1f24a79 5628 return num_counters;
0ad17a8f
MB		 5629}
5630
18d422ce
MZ		 5631static struct rdma_hw_stats *
5632mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5633{
5634 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5dcecbc9 5635 const struct mlx5_ib_counters *cnts =
3e1f000f 5636 get_counters(dev, counter->port - 1);
18d422ce 5637
5dcecbc9 5638 return rdma_alloc_hw_stats_struct(cnts->names,
05037f32
MZ		 5639 cnts->num_q_counters +
5640 cnts->num_cong_counters +
5641 cnts->num_ext_ppcnt_counters,
18d422ce
MZ		 5642 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5643}
5644
5645static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5646{
5647 struct mlx5_ib_dev *dev = to_mdev(counter->device);
3e1f000f
PP		 5648 const struct mlx5_ib_counters *cnts =
5649 get_counters(dev, counter->port - 1);
18d422ce 5650
5dcecbc9 5651 return mlx5_ib_query_q_counters(dev->mdev, cnts,
18d422ce
MZ		 5652 counter->stats, counter->id);
5653}
5654
45842fc6
MZ		 5655static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5656 struct ib_qp *qp)
5657{
5658 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5659 u16 cnt_set_id = 0;
5660 int err;
5661
5662 if (!counter->id) {
5663 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5664 &cnt_set_id,
5665 MLX5_SHARED_RESOURCE_UID);
5666 if (err)
5667 return err;
5668 counter->id = cnt_set_id;
5669 }
5670
5671 err = mlx5_ib_qp_set_counter(qp, counter);
5672 if (err)
5673 goto fail_set_counter;
5674
5675 return 0;
5676
5677fail_set_counter:
5678 mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5679 counter->id = 0;
5680
5681 return err;
5682}
5683
5684static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5685{
5686 return mlx5_ib_qp_set_counter(qp, NULL);
5687}
5688
5689static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5690{
5691 struct mlx5_ib_dev *dev = to_mdev(counter->device);
5692
5693 return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5694}
5695
f6a8a19b
DD		 5696static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5697 enum rdma_netdev_t type,
5698 struct rdma_netdev_alloc_params *params)
693dfd5a
ES		 5699{
5700 if (type != RDMA_NETDEV_IPOIB)
f6a8a19b 5701 return -EOPNOTSUPP;
693dfd5a 5702
f6a8a19b 5703 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
693dfd5a
ES		 5704}
5705
fe248c3a
MG		 5706static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5707{
5708 if (!dev->delay_drop.dbg)
5709 return;
5710 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5711 kfree(dev->delay_drop.dbg);
5712 dev->delay_drop.dbg = NULL;
5713}
5714
03404e8a
MG		 5715static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5716{
5717 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5718 return;
5719
5720 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 5721 delay_drop_debugfs_cleanup(dev);
5722}
5723
5724static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5725 size_t count, loff_t *pos)
5726{
5727 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5728 char lbuf[20];
5729 int len;
5730
5731 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5732 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5733}
5734
5735static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5736 size_t count, loff_t *pos)
5737{
5738 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5739 u32 timeout;
5740 u32 var;
5741
5742 if (kstrtouint_from_user(buf, count, 0, &var))
5743 return -EFAULT;
5744
5745 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5746 1000);
5747 if (timeout != var)
5748 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5749 timeout);
5750
5751 delay_drop->timeout = timeout;
5752
5753 return count;
5754}
5755
5756static const struct file_operations fops_delay_drop_timeout = {
5757 .owner = THIS_MODULE,
5758 .open = simple_open,
5759 .write = delay_drop_timeout_write,
5760 .read = delay_drop_timeout_read,
5761};
5762
5763static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5764{
5765 struct mlx5_ib_dbg_delay_drop *dbg;
5766
5767 if (!mlx5_debugfs_root)
5768 return 0;
5769
5770 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5771 if (!dbg)
5772 return -ENOMEM;
5773
cbafad87
SM		 5774 dev->delay_drop.dbg = dbg;
5775
fe248c3a
MG		 5776 dbg->dir_debugfs =
5777 debugfs_create_dir("delay_drop",
5778 dev->mdev->priv.dbg_root);
5779 if (!dbg->dir_debugfs)
cbafad87 5780 goto out_debugfs;
fe248c3a
MG		 5781
5782 dbg->events_cnt_debugfs =
5783 debugfs_create_atomic_t("num_timeout_events", 0400,
5784 dbg->dir_debugfs,
5785 &dev->delay_drop.events_cnt);
5786 if (!dbg->events_cnt_debugfs)
5787 goto out_debugfs;
5788
5789 dbg->rqs_cnt_debugfs =
5790 debugfs_create_atomic_t("num_rqs", 0400,
5791 dbg->dir_debugfs,
5792 &dev->delay_drop.rqs_cnt);
5793 if (!dbg->rqs_cnt_debugfs)
5794 goto out_debugfs;
5795
5796 dbg->timeout_debugfs =
5797 debugfs_create_file("timeout", 0600,
5798 dbg->dir_debugfs,
5799 &dev->delay_drop,
5800 &fops_delay_drop_timeout);
5801 if (!dbg->timeout_debugfs)
5802 goto out_debugfs;
5803
5804 return 0;
5805
5806out_debugfs:
5807 delay_drop_debugfs_cleanup(dev);
5808 return -ENOMEM;
03404e8a
MG		 5809}
5810
5811static void init_delay_drop(struct mlx5_ib_dev *dev)
5812{
5813 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5814 return;
5815
5816 mutex_init(&dev->delay_drop.lock);
5817 dev->delay_drop.dev = dev;
5818 dev->delay_drop.activate = false;
5819 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5820 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 5821 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5822 atomic_set(&dev->delay_drop.events_cnt, 0);
5823
5824 if (delay_drop_debugfs_init(dev))
5825 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 5826}
5827
32f69e4b
DJ		 5828static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5829 struct mlx5_ib_multiport_info *mpi)
5830{
5831 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5832 struct mlx5_ib_port *port = &ibdev->port[port_num];
5833 int comps;
5834 int err;
5835 int i;
5836
9dc4cfff
LR		 5837 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5838
a9e546e7
PP		 5839 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5840
32f69e4b
DJ		 5841 spin_lock(&port->mp.mpi_lock);
5842 if (!mpi->ibdev) {
5843 spin_unlock(&port->mp.mpi_lock);
5844 return;
5845 }
df097a27 5846
32f69e4b
DJ		 5847 mpi->ibdev = NULL;
5848
5849 spin_unlock(&port->mp.mpi_lock);
23eaf3b5
LR		 5850 if (mpi->mdev_events.notifier_call)
5851 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5852 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5853 mlx5_remove_netdev_notifier(ibdev, port_num);
5854 spin_lock(&port->mp.mpi_lock);
5855
5856 comps = mpi->mdev_refcnt;
5857 if (comps) {
5858 mpi->unaffiliate = true;
5859 init_completion(&mpi->unref_comp);
5860 spin_unlock(&port->mp.mpi_lock);
5861
5862 for (i = 0; i < comps; i++)
5863 wait_for_completion(&mpi->unref_comp);
5864
5865 spin_lock(&port->mp.mpi_lock);
5866 mpi->unaffiliate = false;
5867 }
5868
5869 port->mp.mpi = NULL;
5870
32f69e4b
DJ		 5871 spin_unlock(&port->mp.mpi_lock);
5872
5873 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5874
5875 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5876 /* Log an error, still needed to cleanup the pointers and add
5877 * it back to the list.
5878 */
5879 if (err)
5880 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5881 port_num + 1);
5882
95579e78 5883 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 5884}
5885
32f69e4b
DJ		 5886static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5887 struct mlx5_ib_multiport_info *mpi)
5888{
5889 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5890 int err;
5891
9dc4cfff
LR		 5892 lockdep_assert_held(&mlx5_ib_multiport_mutex);
5893
32f69e4b
DJ		 5894 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5895 if (ibdev->port[port_num].mp.mpi) {
2577188e
QH		 5896 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5897 port_num + 1);
32f69e4b
DJ		 5898 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5899 return false;
5900 }
5901
5902 ibdev->port[port_num].mp.mpi = mpi;
5903 mpi->ibdev = ibdev;
df097a27 5904 mpi->mdev_events.notifier_call = NULL;
32f69e4b
DJ		 5905 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5906
5907 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5908 if (err)
5909 goto unbind;
5910
5911 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5912 if (err)
5913 goto unbind;
5914
5915 err = mlx5_add_netdev_notifier(ibdev, port_num);
5916 if (err) {
5917 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5918 port_num + 1);
5919 goto unbind;
5920 }
5921
df097a27
SM		 5922 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5923 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5924
73eb8f03 5925 mlx5_ib_init_cong_debugfs(ibdev, port_num);
a9e546e7 5926
32f69e4b
DJ		 5927 return true;
5928
5929unbind:
5930 mlx5_ib_unbind_slave_port(ibdev, mpi);
5931 return false;
5932}
5933
5934static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5935{
5936 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5937 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5938 port_num + 1);
5939 struct mlx5_ib_multiport_info *mpi;
5940 int err;
5941 int i;
5942
5943 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5944 return 0;
5945
5946 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5947 &dev->sys_image_guid);
5948 if (err)
5949 return err;
5950
5951 err = mlx5_nic_vport_enable_roce(dev->mdev);
5952 if (err)
5953 return err;
5954
5955 mutex_lock(&mlx5_ib_multiport_mutex);
5956 for (i = 0; i < dev->num_ports; i++) {
5957 bool bound = false;
5958
5959 /* build a stub multiport info struct for the native port. */
5960 if (i == port_num) {
5961 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5962 if (!mpi) {
5963 mutex_unlock(&mlx5_ib_multiport_mutex);
5964 mlx5_nic_vport_disable_roce(dev->mdev);
5965 return -ENOMEM;
5966 }
5967
5968 mpi->is_master = true;
5969 mpi->mdev = dev->mdev;
5970 mpi->sys_image_guid = dev->sys_image_guid;
5971 dev->port[i].mp.mpi = mpi;
5972 mpi->ibdev = dev;
5973 mpi = NULL;
5974 continue;
5975 }
5976
5977 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5978 list) {
5979 if (dev->sys_image_guid == mpi->sys_image_guid &&
5980 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5981 bound = mlx5_ib_bind_slave_port(dev, mpi);
5982 }
5983
5984 if (bound) {
c42260f1
VP		 5985 dev_dbg(mpi->mdev->device,
5986 "removing port from unaffiliated list.\n");
32f69e4b
DJ		 5987 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5988 list_del(&mpi->list);
5989 break;
5990 }
5991 }
5992 if (!bound) {
5993 get_port_caps(dev, i + 1);
5994 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5995 i + 1);
5996 }
5997 }
5998
5999 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
6000 mutex_unlock(&mlx5_ib_multiport_mutex);
6001 return err;
6002}
6003
6004static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
6005{
6006 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6007 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
6008 port_num + 1);
6009 int i;
6010
6011 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
6012 return;
6013
6014 mutex_lock(&mlx5_ib_multiport_mutex);
6015 for (i = 0; i < dev->num_ports; i++) {
6016 if (dev->port[i].mp.mpi) {
6017 /* Destroy the native port stub */
6018 if (i == port_num) {
6019 kfree(dev->port[i].mp.mpi);
6020 dev->port[i].mp.mpi = NULL;
6021 } else {
6022 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
20257606
LR		 6023 list_add_tail(&dev->port[i].mp.mpi->list,
6024 &mlx5_ib_unaffiliated_port_list);
8b7f3e58 6025 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
32f69e4b
DJ		 6026 }
6027 }
6028 }
6029
6030 mlx5_ib_dbg(dev, "removing from devlist\n");
6031 list_del(&dev->ib_dev_list);
6032 mutex_unlock(&mlx5_ib_multiport_mutex);
6033
6034 mlx5_nic_vport_disable_roce(dev->mdev);
6035}
6036
9a119cd5
JG		 6037ADD_UVERBS_ATTRIBUTES_SIMPLE(
6038 mlx5_ib_dm,
6039 UVERBS_OBJECT_DM,
6040 UVERBS_METHOD_DM_ALLOC,
6041 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6042 UVERBS_ATTR_TYPE(u64),
83bb4442 6043 UA_MANDATORY),
9a119cd5
JG		 6044 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6045 UVERBS_ATTR_TYPE(u16),
3b113a1e
AL		 6046 UA_OPTIONAL),
6047 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6048 enum mlx5_ib_uapi_dm_type,
6049 UA_OPTIONAL));
9a119cd5
JG		 6050
6051ADD_UVERBS_ATTRIBUTES_SIMPLE(
6052 mlx5_ib_flow_action,
6053 UVERBS_OBJECT_FLOW_ACTION,
6054 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
bccd0622
JG		 6055 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6056 enum mlx5_ib_uapi_flow_action_flags));
c6475a0b 6057
0cbf432d
JG		 6058static const struct uapi_definition mlx5_ib_defs[] = {
6059#if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
36e235c8 6060 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
0cbf432d
JG		 6061 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6062#endif
8c84660b 6063
0cbf432d
JG		 6064 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6065 &mlx5_ib_flow_action),
6066 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6067 {}
6068};
8c84660b 6069
1a1e03dc
RS		 6070static int mlx5_ib_read_counters(struct ib_counters *counters,
6071 struct ib_counters_read_attr *read_attr,
6072 struct uverbs_attr_bundle *attrs)
6073{
6074 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6075 struct mlx5_read_counters_attr mread_attr = {};
6076 struct mlx5_ib_flow_counters_desc *desc;
6077 int ret, i;
6078
6079 mutex_lock(&mcounters->mcntrs_mutex);
6080 if (mcounters->cntrs_max_index > read_attr->ncounters) {
6081 ret = -EINVAL;
6082 goto err_bound;
6083 }
6084
6085 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6086 GFP_KERNEL);
6087 if (!mread_attr.out) {
6088 ret = -ENOMEM;
6089 goto err_bound;
6090 }
6091
6092 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6093 mread_attr.flags = read_attr->flags;
6094 ret = mcounters->read_counters(counters->device, &mread_attr);
6095 if (ret)
6096 goto err_read;
6097
6098 /* do the pass over the counters data array to assign according to the
6099 * descriptions and indexing pairs
6100 */
6101 desc = mcounters->counters_data;
6102 for (i = 0; i < mcounters->ncounters; i++)
6103 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6104
6105err_read:
6106 kfree(mread_attr.out);
6107err_bound:
6108 mutex_unlock(&mcounters->mcntrs_mutex);
6109 return ret;
6110}
6111
b29e2a13
RS		 6112static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6113{
6114 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6115
3b3233fb
RS		 6116 counters_clear_description(counters);
6117 if (mcounters->hw_cntrs_hndl)
6118 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6119 mcounters->hw_cntrs_hndl);
6120
b29e2a13
RS		 6121 kfree(mcounters);
6122
6123 return 0;
6124}
6125
6126static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6127 struct uverbs_attr_bundle *attrs)
6128{
6129 struct mlx5_ib_mcounters *mcounters;
6130
6131 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6132 if (!mcounters)
6133 return ERR_PTR(-ENOMEM);
6134
3b3233fb
RS		 6135 mutex_init(&mcounters->mcntrs_mutex);
6136
b29e2a13
RS		 6137 return &mcounters->ibcntrs;
6138}
6139
fb652d32 6140static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 6141{
32f69e4b 6142 mlx5_ib_cleanup_multiport_master(dev);
13859d5d 6143 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
534fd7aa 6144 srcu_barrier(&dev->mr_srcu);
13859d5d 6145 cleanup_srcu_struct(&dev->mr_srcu);
13859d5d 6146 }
4056b12e
AL		 6147
6148 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
16c1975f
MB		 6149}
6150
fb652d32 6151static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6152{
6153 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 6154 int err;
32f69e4b 6155 int i;
e126ba97 6156
32f69e4b
DJ		 6157 for (i = 0; i < dev->num_ports; i++) {
6158 spin_lock_init(&dev->port[i].mp.mpi_lock);
95579e78 6159 rwlock_init(&dev->port[i].roce.netdev_lock);
d3b5cc1c
MB		 6160 dev->port[i].roce.dev = dev;
6161 dev->port[i].roce.native_port_num = i + 1;
6162 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
32f69e4b
DJ		 6163 }
6164
00815752
MS		 6165 mlx5_ib_internal_fill_odp_caps(dev);
6166
32f69e4b 6167 err = mlx5_ib_init_multiport_master(dev);
e126ba97 6168 if (err)
da796ccb 6169 return err;
e126ba97 6170
a989ea01
MB		 6171 err = set_has_smi_cap(dev);
6172 if (err)
86ba70cd 6173 goto err_mp;
e126ba97 6174
32f69e4b 6175 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 6176 for (i = 1; i <= dev->num_ports; i++) {
6177 err = get_port_caps(dev, i);
6178 if (err)
6179 break;
6180 }
6181 } else {
6182 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6183 }
6184 if (err)
6185 goto err_mp;
6186
1b5daf11
MD		 6187 if (mlx5_use_mad_ifc(dev))
6188 get_ext_port_caps(dev);
e126ba97 6189
e126ba97 6190 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 6191 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 6192 dev->ib_dev.phys_port_cnt = dev->num_ports;
f2f3df55 6193 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
c42260f1 6194 dev->ib_dev.dev.parent = mdev->device;
e126ba97 6195
3cc297db
MB		 6196 mutex_init(&dev->cap_mask_mutex);
6197 INIT_LIST_HEAD(&dev->qp_list);
6198 spin_lock_init(&dev->reset_flow_resource_lock);
6199
3b113a1e
AL		 6200 spin_lock_init(&dev->dm.lock);
6201 dev->dm.dev = mdev;
24da0016 6202
13859d5d 6203 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
13859d5d 6204 err = init_srcu_struct(&dev->mr_srcu);
a6bc3875 6205 if (err)
c9b9dcb4 6206 goto err_mp;
623d1543 6207 }
3cc297db 6208
16c1975f 6209 return 0;
25c13324 6210
32f69e4b
DJ		 6211err_mp:
6212 mlx5_ib_cleanup_multiport_master(dev);
65d572d1 6213 return err;
16c1975f
MB		 6214}
6215
9a4ca38d
MB		 6216static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6217{
6218 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6219
6220 if (!dev->flow_db)
6221 return -ENOMEM;
6222
6223 mutex_init(&dev->flow_db->lock);
6224
6225 return 0;
6226}
6227
6228static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6229{
6230 kfree(dev->flow_db);
6231}
6232
96458233 6233static const struct ib_device_ops mlx5_ib_dev_ops = {
7a154142 6234 .owner = THIS_MODULE,
b9560a41 6235 .driver_id = RDMA_DRIVER_MLX5,
72c6ec18 6236 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
b9560a41 6237
96458233
KH		 6238 .add_gid = mlx5_ib_add_gid,
6239 .alloc_mr = mlx5_ib_alloc_mr,
6c984472 6240 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
96458233
KH		 6241 .alloc_pd = mlx5_ib_alloc_pd,
6242 .alloc_ucontext = mlx5_ib_alloc_ucontext,
6243 .attach_mcast = mlx5_ib_mcg_attach,
6244 .check_mr_status = mlx5_ib_check_mr_status,
6245 .create_ah = mlx5_ib_create_ah,
6246 .create_counters = mlx5_ib_create_counters,
6247 .create_cq = mlx5_ib_create_cq,
6248 .create_flow = mlx5_ib_create_flow,
6249 .create_qp = mlx5_ib_create_qp,
6250 .create_srq = mlx5_ib_create_srq,
6251 .dealloc_pd = mlx5_ib_dealloc_pd,
6252 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6253 .del_gid = mlx5_ib_del_gid,
6254 .dereg_mr = mlx5_ib_dereg_mr,
6255 .destroy_ah = mlx5_ib_destroy_ah,
6256 .destroy_counters = mlx5_ib_destroy_counters,
6257 .destroy_cq = mlx5_ib_destroy_cq,
6258 .destroy_flow = mlx5_ib_destroy_flow,
6259 .destroy_flow_action = mlx5_ib_destroy_flow_action,
6260 .destroy_qp = mlx5_ib_destroy_qp,
6261 .destroy_srq = mlx5_ib_destroy_srq,
6262 .detach_mcast = mlx5_ib_mcg_detach,
6263 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6264 .drain_rq = mlx5_ib_drain_rq,
6265 .drain_sq = mlx5_ib_drain_sq,
6266 .get_dev_fw_str = get_dev_fw_str,
6267 .get_dma_mr = mlx5_ib_get_dma_mr,
6268 .get_link_layer = mlx5_ib_port_link_layer,
6269 .map_mr_sg = mlx5_ib_map_mr_sg,
6c984472 6270 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
96458233
KH		 6271 .mmap = mlx5_ib_mmap,
6272 .modify_cq = mlx5_ib_modify_cq,
6273 .modify_device = mlx5_ib_modify_device,
6274 .modify_port = mlx5_ib_modify_port,
6275 .modify_qp = mlx5_ib_modify_qp,
6276 .modify_srq = mlx5_ib_modify_srq,
6277 .poll_cq = mlx5_ib_poll_cq,
6278 .post_recv = mlx5_ib_post_recv,
6279 .post_send = mlx5_ib_post_send,
6280 .post_srq_recv = mlx5_ib_post_srq_recv,
6281 .process_mad = mlx5_ib_process_mad,
6282 .query_ah = mlx5_ib_query_ah,
6283 .query_device = mlx5_ib_query_device,
6284 .query_gid = mlx5_ib_query_gid,
6285 .query_pkey = mlx5_ib_query_pkey,
6286 .query_qp = mlx5_ib_query_qp,
6287 .query_srq = mlx5_ib_query_srq,
6288 .read_counters = mlx5_ib_read_counters,
6289 .reg_user_mr = mlx5_ib_reg_user_mr,
6290 .req_notify_cq = mlx5_ib_arm_cq,
6291 .rereg_user_mr = mlx5_ib_rereg_user_mr,
6292 .resize_cq = mlx5_ib_resize_cq,
d3456914
LR		 6293
6294 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
e39afe3d 6295 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
21a428a0 6296 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
68e326de 6297 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
a2a074ef 6298 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
96458233
KH		 6299};
6300
6301static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6302 .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6303 .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6304};
6305
6306static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6307 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6308};
6309
6310static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6311 .get_vf_config = mlx5_ib_get_vf_config,
6312 .get_vf_stats = mlx5_ib_get_vf_stats,
6313 .set_vf_guid = mlx5_ib_set_vf_guid,
6314 .set_vf_link_state = mlx5_ib_set_vf_link_state,
6315};
6316
6317static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6318 .alloc_mw = mlx5_ib_alloc_mw,
6319 .dealloc_mw = mlx5_ib_dealloc_mw,
6320};
6321
6322static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6323 .alloc_xrcd = mlx5_ib_alloc_xrcd,
6324 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6325};
6326
6327static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6328 .alloc_dm = mlx5_ib_alloc_dm,
6329 .dealloc_dm = mlx5_ib_dealloc_dm,
6330 .reg_dm_mr = mlx5_ib_reg_dm_mr,
6331};
6332
fb652d32 6333static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6334{
6335 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 6336 int err;
6337
e126ba97
EC		 6338 dev->ib_dev.uverbs_cmd_mask =
6339 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
6340 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
6341 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
6342 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
6343 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 6344 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
6345 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 6346 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 6347 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 6348 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
6349 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6350 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
6351 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
6352 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
6353 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
6354 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
6355 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
6356 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
6357 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
6358 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
6359 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
6360 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
6361 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
6362 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
6363 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
6364 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 6365 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 6366 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
6367 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 6368 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d 6369 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
96458233
KH		 6370 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
6371 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
6372 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6373
f6a8a19b
DD		 6374 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6375 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
96458233
KH		 6376 ib_set_device_ops(&dev->ib_dev,
6377 &mlx5_ib_dev_ipoib_enhanced_ops);
8e959601 6378
96458233
KH		 6379 if (mlx5_core_is_pf(mdev))
6380 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
7c2344c3 6381
6e8484c5
MG		 6382 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6383
d2370e0a 6384 if (MLX5_CAP_GEN(mdev, imaicl)) {
d2370e0a
MB		 6385 dev->ib_dev.uverbs_cmd_mask |=
6386 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
6387 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
96458233 6388 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
d2370e0a
MB		 6389 }
6390
938fe83c 6391 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 6392 dev->ib_dev.uverbs_cmd_mask |=
6393 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6394 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
96458233 6395 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
e126ba97
EC		 6396 }
6397
25c13324
AL		 6398 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6399 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6400 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
96458233 6401 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
24da0016 6402
dfb631a1 6403 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
96458233
KH		 6404 MLX5_ACCEL_IPSEC_CAP_DEVICE)
6405 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
96458233 6406 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
81e30880 6407
36e235c8
JG		 6408 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6409 dev->ib_dev.driver_def = mlx5_ib_defs;
81e30880 6410
e126ba97
EC		 6411 err = init_node_data(dev);
6412 if (err)
16c1975f 6413 return err;
e126ba97 6414
c8b89924 6415 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 6416 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6417 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
a560f1d9 6418 mutex_init(&dev->lb.mutex);
c8b89924 6419
96e2fd73
LR		 6420 dev->ib_dev.use_cq_dim = true;
6421
16c1975f
MB		 6422 return 0;
6423}
6424
96458233
KH		 6425static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6426 .get_port_immutable = mlx5_port_immutable,
6427 .query_port = mlx5_ib_query_port,
6428};
6429
8e6efa3a
MB		 6430static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6431{
96458233 6432 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
8e6efa3a
MB		 6433 return 0;
6434}
6435
96458233
KH		 6436static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6437 .get_port_immutable = mlx5_port_rep_immutable,
6438 .query_port = mlx5_ib_rep_query_port,
6439};
6440
c1930153 6441static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a 6442{
96458233 6443 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
8e6efa3a
MB		 6444 return 0;
6445}
6446
96458233
KH		 6447static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6448 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6449 .create_wq = mlx5_ib_create_wq,
6450 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6451 .destroy_wq = mlx5_ib_destroy_wq,
6452 .get_netdev = mlx5_ib_get_netdev,
6453 .modify_wq = mlx5_ib_modify_wq,
6454};
6455
e3f1ed1f 6456static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a 6457{
e3f1ed1f 6458 u8 port_num;
8e6efa3a 6459
8e6efa3a
MB		 6460 dev->ib_dev.uverbs_ex_cmd_mask |=
6461 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6462 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6463 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6464 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6465 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
96458233 6466 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
8e6efa3a 6467
e3f1ed1f
LR		 6468 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6469
26628e2d 6470 /* Register only for native ports */
8e6efa3a
MB		 6471 return mlx5_add_netdev_notifier(dev, port_num);
6472}
6473
6474static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6475{
6476 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6477
6478 mlx5_remove_netdev_notifier(dev, port_num);
6479}
6480
c1930153 6481static int mlx5_ib_stage_raw_eth_roce_init(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6482{
6483 struct mlx5_core_dev *mdev = dev->mdev;
6484 enum rdma_link_layer ll;
6485 int port_type_cap;
6486 int err = 0;
8e6efa3a 6487
8e6efa3a
MB		 6488 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6489 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6490
6491 if (ll == IB_LINK_LAYER_ETHERNET)
e3f1ed1f 6492 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6493
6494 return err;
6495}
6496
c1930153 6497static void mlx5_ib_stage_raw_eth_roce_cleanup(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 6498{
6499 mlx5_ib_stage_common_roce_cleanup(dev);
6500}
6501
16c1975f
MB		 6502static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6503{
6504 struct mlx5_core_dev *mdev = dev->mdev;
6505 enum rdma_link_layer ll;
6506 int port_type_cap;
6507 int err;
6508
6509 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6510 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6511
fc24fc5e 6512 if (ll == IB_LINK_LAYER_ETHERNET) {
e3f1ed1f 6513 err = mlx5_ib_stage_common_roce_init(dev);
8e6efa3a
MB		 6514 if (err)
6515 return err;
7fd8aefb 6516
e3f1ed1f 6517 err = mlx5_enable_eth(dev);
fc24fc5e 6518 if (err)
8e6efa3a 6519 goto cleanup;
fc24fc5e
AS		 6520 }
6521
16c1975f 6522 return 0;
8e6efa3a
MB		 6523cleanup:
6524 mlx5_ib_stage_common_roce_cleanup(dev);
6525
6526 return err;
16c1975f 6527}
e126ba97 6528
16c1975f
MB		 6529static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6530{
6531 struct mlx5_core_dev *mdev = dev->mdev;
6532 enum rdma_link_layer ll;
6533 int port_type_cap;
e126ba97 6534
16c1975f
MB		 6535 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6536 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6537
6538 if (ll == IB_LINK_LAYER_ETHERNET) {
6539 mlx5_disable_eth(dev);
8e6efa3a 6540 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 6541 }
16c1975f 6542}
6aec21f6 6543
fb652d32 6544static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6545{
6546 return create_dev_resources(&dev->devr);
6547}
6548
fb652d32 6549static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6550{
6551 destroy_dev_resources(&dev->devr);
6552}
6553
6554static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6555{
6556 return mlx5_ib_odp_init_one(dev);
6557}
4a2da0b8 6558
f3ffed0c 6559static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
d5d284b8
SM		 6560{
6561 mlx5_ib_odp_cleanup_one(dev);
6562}
6563
96458233
KH		 6564static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6565 .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6566 .get_hw_stats = mlx5_ib_get_hw_stats,
45842fc6
MZ		 6567 .counter_bind_qp = mlx5_ib_counter_bind_qp,
6568 .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6569 .counter_dealloc = mlx5_ib_counter_dealloc,
18d422ce
MZ		 6570 .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6571 .counter_update_stats = mlx5_ib_counter_update_stats,
96458233
KH		 6572};
6573
fb652d32 6574static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 6575{
5e1e7612 6576 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
96458233 6577 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
5e1e7612
MB		 6578
6579 return mlx5_ib_alloc_counters(dev);
6580 }
16c1975f
MB		 6581
6582 return 0;
6583}
6584
fb652d32 6585static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6586{
6587 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6588 mlx5_ib_dealloc_counters(dev);
6589}
6590
6591static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6592{
73eb8f03
GKH		 6593 mlx5_ib_init_cong_debugfs(dev,
6594 mlx5_core_native_port_num(dev->mdev) - 1);
6595 return 0;
16c1975f
MB		 6596}
6597
6598static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6599{
a9e546e7
PP		 6600 mlx5_ib_cleanup_cong_debugfs(dev,
6601 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 6602}
6603
6604static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6605{
5fe9dec0 6606 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
444261ca 6607 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
16c1975f
MB		 6608}
6609
6610static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6611{
6612 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6613}
6614
fb652d32 6615static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 6616{
6617 int err;
5fe9dec0
EC		 6618
6619 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6620 if (err)
16c1975f 6621 return err;
5fe9dec0
EC		 6622
6623 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6624 if (err)
855ae031 6625 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5fe9dec0 6626
16c1975f
MB		 6627 return err;
6628}
0837e86a 6629
fb652d32 6630static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 6631{
6632 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6633 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6634}
e126ba97 6635
fb652d32 6636static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f 6637{
e349f858
JG		 6638 const char *name;
6639
508a523f 6640 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
7c34ec19 6641 if (!mlx5_lag_is_roce(dev->mdev))
e349f858
JG		 6642 name = "mlx5_%d";
6643 else
6644 name = "mlx5_bond_%d";
ea4baf7f 6645 return ib_register_device(&dev->ib_dev, name);
16c1975f
MB		 6646}
6647
fb652d32 6648static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6649{
42cea83f 6650 destroy_umrc_res(dev);
16c1975f
MB		 6651}
6652
fb652d32 6653static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 6654{
42cea83f 6655 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 6656}
6657
fb652d32 6658static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 6659{
42cea83f 6660 return create_umr_res(dev);
16c1975f
MB		 6661}
6662
6663static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6664{
03404e8a
MG		 6665 init_delay_drop(dev);
6666
16c1975f
MB		 6667 return 0;
6668}
6669
6670static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6671{
6672 cancel_delay_drop(dev);
6673}
6674
df097a27
SM		 6675static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6676{
6677 dev->mdev_events.notifier_call = mlx5_ib_event;
6678 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6679 return 0;
6680}
6681
6682static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6683{
6684 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6685}
6686
81773ce5
LR		 6687static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6688{
6689 int uid;
6690
fb98153b 6691 uid = mlx5_ib_devx_create(dev, false);
e337dd53 6692 if (uid > 0) {
81773ce5 6693 dev->devx_whitelist_uid = uid;
e337dd53
YH		 6694 mlx5_ib_devx_init_event_table(dev);
6695 }
81773ce5
LR		 6696
6697 return 0;
6698}
6699static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6700{
e337dd53
YH		 6701 if (dev->devx_whitelist_uid) {
6702 mlx5_ib_devx_cleanup_event_table(dev);
81773ce5 6703 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
e337dd53 6704 }
81773ce5
LR		 6705}
6706
b5ca15ad
MB		 6707void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6708 const struct mlx5_ib_profile *profile,
6709 int stage)
16c1975f 6710{
9a7280c1
PP		 6711 dev->ib_active = false;
6712
16c1975f
MB		 6713 /* Number of stages to cleanup */
6714 while (stage) {
6715 stage--;
6716 if (profile->stage[stage].cleanup)
6717 profile->stage[stage].cleanup(dev);
6718 }
4a6dc855 6719
da796ccb 6720 kfree(dev->port);
4a6dc855 6721 ib_dealloc_device(&dev->ib_dev);
16c1975f 6722}
e126ba97 6723
b5ca15ad
MB		 6724void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6725 const struct mlx5_ib_profile *profile)
16c1975f 6726{
16c1975f
MB		 6727 int err;
6728 int i;
5fe9dec0 6729
16c1975f
MB		 6730 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6731 if (profile->stage[i].init) {
6732 err = profile->stage[i].init(dev);
6733 if (err)
6734 goto err_out;
6735 }
6736 }
0837e86a 6737
16c1975f
MB		 6738 dev->profile = profile;
6739 dev->ib_active = true;
6aec21f6 6740
16c1975f 6741 return dev;
e126ba97 6742
16c1975f
MB		 6743err_out:
6744 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 6745
16c1975f
MB		 6746 return NULL;
6747}
0837e86a 6748
16c1975f
MB		 6749static const struct mlx5_ib_profile pf_profile = {
6750 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6751 mlx5_ib_stage_init_init,
6752 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 6753 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6754 mlx5_ib_stage_flow_db_init,
6755 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 6756 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6757 mlx5_ib_stage_caps_init,
6758 NULL),
8e6efa3a
MB		 6759 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6760 mlx5_ib_stage_non_default_cb,
6761 NULL),
16c1975f
MB		 6762 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6763 mlx5_ib_stage_roce_init,
6764 mlx5_ib_stage_roce_cleanup),
f3da6577
LR		 6765 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6766 mlx5_init_srq_table,
6767 mlx5_cleanup_srq_table),
16c1975f
MB		 6768 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6769 mlx5_ib_stage_dev_res_init,
6770 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6771 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6772 mlx5_ib_stage_dev_notifier_init,
6773 mlx5_ib_stage_dev_notifier_cleanup),
16c1975f
MB		 6774 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6775 mlx5_ib_stage_odp_init,
d5d284b8 6776 mlx5_ib_stage_odp_cleanup),
16c1975f
MB		 6777 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6778 mlx5_ib_stage_counters_init,
6779 mlx5_ib_stage_counters_cleanup),
6780 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6781 mlx5_ib_stage_cong_debugfs_init,
6782 mlx5_ib_stage_cong_debugfs_cleanup),
6783 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6784 mlx5_ib_stage_uar_init,
6785 mlx5_ib_stage_uar_cleanup),
6786 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6787 mlx5_ib_stage_bfrag_init,
6788 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 6789 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6790 NULL,
6791 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
81773ce5
LR		 6792 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6793 mlx5_ib_stage_devx_init,
6794 mlx5_ib_stage_devx_cleanup),
16c1975f
MB		 6795 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6796 mlx5_ib_stage_ib_reg_init,
6797 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 6798 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6799 mlx5_ib_stage_post_ib_reg_umr_init,
6800 NULL),
16c1975f
MB		 6801 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6802 mlx5_ib_stage_delay_drop_init,
6803 mlx5_ib_stage_delay_drop_cleanup),
16c1975f 6804};
e126ba97 6805
c1930153 6806const struct mlx5_ib_profile raw_eth_profile = {
b5ca15ad
MB		 6807 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6808 mlx5_ib_stage_init_init,
6809 mlx5_ib_stage_init_cleanup),
6810 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6811 mlx5_ib_stage_flow_db_init,
6812 mlx5_ib_stage_flow_db_cleanup),
6813 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6814 mlx5_ib_stage_caps_init,
6815 NULL),
6816 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
c1930153 6817 mlx5_ib_stage_raw_eth_non_default_cb,
b5ca15ad
MB		 6818 NULL),
6819 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
c1930153
MG		 6820 mlx5_ib_stage_raw_eth_roce_init,
6821 mlx5_ib_stage_raw_eth_roce_cleanup),
f3da6577
LR		 6822 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6823 mlx5_init_srq_table,
6824 mlx5_cleanup_srq_table),
b5ca15ad
MB		 6825 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6826 mlx5_ib_stage_dev_res_init,
6827 mlx5_ib_stage_dev_res_cleanup),
df097a27
SM		 6828 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6829 mlx5_ib_stage_dev_notifier_init,
6830 mlx5_ib_stage_dev_notifier_cleanup),
b5ca15ad
MB		 6831 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6832 mlx5_ib_stage_counters_init,
6833 mlx5_ib_stage_counters_cleanup),
6834 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6835 mlx5_ib_stage_uar_init,
6836 mlx5_ib_stage_uar_cleanup),
6837 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6838 mlx5_ib_stage_bfrag_init,
6839 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 6840 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6841 NULL,
6842 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
7f575103
MB		 6843 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6844 mlx5_ib_stage_devx_init,
6845 mlx5_ib_stage_devx_cleanup),
b5ca15ad
MB		 6846 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6847 mlx5_ib_stage_ib_reg_init,
6848 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 6849 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6850 mlx5_ib_stage_post_ib_reg_umr_init,
6851 NULL),
b5ca15ad
MB		 6852};
6853
e3f1ed1f 6854static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
32f69e4b
DJ		 6855{
6856 struct mlx5_ib_multiport_info *mpi;
6857 struct mlx5_ib_dev *dev;
6858 bool bound = false;
6859 int err;
6860
6861 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6862 if (!mpi)
6863 return NULL;
6864
6865 mpi->mdev = mdev;
6866
6867 err = mlx5_query_nic_vport_system_image_guid(mdev,
6868 &mpi->sys_image_guid);
6869 if (err) {
6870 kfree(mpi);
6871 return NULL;
6872 }
6873
6874 mutex_lock(&mlx5_ib_multiport_mutex);
6875 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6876 if (dev->sys_image_guid == mpi->sys_image_guid)
6877 bound = mlx5_ib_bind_slave_port(dev, mpi);
6878
6879 if (bound) {
6880 rdma_roce_rescan_device(&dev->ib_dev);
a839f1e8 6881 mpi->ibdev->ib_active = true;
32f69e4b
DJ		 6882 break;
6883 }
6884 }
6885
6886 if (!bound) {
6887 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
c42260f1
VP		 6888 dev_dbg(mdev->device,
6889 "no suitable IB device found to bind to, added to unaffiliated list.\n");
32f69e4b
DJ		 6890 }
6891 mutex_unlock(&mlx5_ib_multiport_mutex);
6892
6893 return mpi;
6894}
6895
16c1975f
MB		 6896static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6897{
0e73e016 6898 const struct mlx5_ib_profile *profile;
32f69e4b 6899 enum rdma_link_layer ll;
b5ca15ad 6900 struct mlx5_ib_dev *dev;
32f69e4b 6901 int port_type_cap;
da796ccb 6902 int num_ports;
32f69e4b 6903
b5ca15ad
MB		 6904 printk_once(KERN_INFO "%s", mlx5_version);
6905
f0666f1f 6906 if (MLX5_ESWITCH_MANAGER(mdev) &&
f6455de0 6907 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5fb58c9e
MB		 6908 if (!mlx5_core_mp_enabled(mdev))
6909 mlx5_ib_register_vport_reps(mdev);
f0666f1f
BW		 6910 return mdev;
6911 }
6912
32f69e4b
DJ		 6913 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6914 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6915
e3f1ed1f
LR		 6916 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6917 return mlx5_ib_add_slave_port(mdev);
32f69e4b 6918
da796ccb
MB		 6919 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6920 MLX5_CAP_GEN(mdev, num_vhca_ports));
459cc69f 6921 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
b5ca15ad
MB		 6922 if (!dev)
6923 return NULL;
da796ccb
MB		 6924 dev->port = kcalloc(num_ports, sizeof(*dev->port),
6925 GFP_KERNEL);
6926 if (!dev->port) {
a5c9c299 6927 ib_dealloc_device(&dev->ib_dev);
da796ccb
MB		 6928 return NULL;
6929 }
b5ca15ad
MB		 6930
6931 dev->mdev = mdev;
da796ccb 6932 dev->num_ports = num_ports;
b5ca15ad 6933
0e73e016
MG		 6934 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_enabled(mdev))
6935 profile = &raw_eth_profile;
6936 else
6937 profile = &pf_profile;
6938
6939 return __mlx5_ib_add(dev, profile);
e126ba97
EC		 6940}
6941
9603b61d 6942static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 6943{
32f69e4b
DJ		 6944 struct mlx5_ib_multiport_info *mpi;
6945 struct mlx5_ib_dev *dev;
6946
f0666f1f
BW		 6947 if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6948 mlx5_ib_unregister_vport_reps(mdev);
6949 return;
6950 }
6951
32f69e4b
DJ		 6952 if (mlx5_core_is_mp_slave(mdev)) {
6953 mpi = context;
6954 mutex_lock(&mlx5_ib_multiport_mutex);
6955 if (mpi->ibdev)
6956 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6957 list_del(&mpi->list);
6958 mutex_unlock(&mlx5_ib_multiport_mutex);
5d44adeb 6959 kfree(mpi);
32f69e4b
DJ		 6960 return;
6961 }
6aec21f6 6962
32f69e4b 6963 dev = context;
f0666f1f 6964 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 6965}
6966
9603b61d
JM		 6967static struct mlx5_interface mlx5_ib_interface = {
6968 .add = mlx5_ib_add,
6969 .remove = mlx5_ib_remove,
64613d94 6970 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 6971};
6972
c44ef998
IL		 6973unsigned long mlx5_ib_get_xlt_emergency_page(void)
6974{
6975 mutex_lock(&xlt_emergency_page_mutex);
6976 return xlt_emergency_page;
6977}
6978
6979void mlx5_ib_put_xlt_emergency_page(void)
6980{
6981 mutex_unlock(&xlt_emergency_page_mutex);
6982}
6983
e126ba97
EC		 6984static int __init mlx5_ib_init(void)
6985{
6aec21f6
HE		 6986 int err;
6987
c44ef998
IL		 6988 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6989 if (!xlt_emergency_page)
6990 return -ENOMEM;
6991
6992 mutex_init(&xlt_emergency_page_mutex);
6993
d69a24e0 6994 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 6995 if (!mlx5_ib_event_wq) {
6996 free_page(xlt_emergency_page);
d69a24e0 6997 return -ENOMEM;
c44ef998 6998 }
d69a24e0 6999
81713d37 7000 mlx5_ib_odp_init();
9603b61d 7001
6aec21f6 7002 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 7003
6aec21f6 7004 return err;
e126ba97
EC		 7005}
7006
7007static void __exit mlx5_ib_cleanup(void)
7008{
9603b61d 7009 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 7010 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 7011 mutex_destroy(&xlt_emergency_page_mutex);
7012 free_page(xlt_emergency_page);
e126ba97
EC		 7013}
7014
7015module_init(mlx5_ib_init);
7016module_exit(mlx5_ib_cleanup);
Ubuntu Focal Linux kernel mirror