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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_IB_H | |
34 | #define MLX5_IB_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/sched.h> | |
38 | #include <rdma/ib_verbs.h> | |
39 | #include <rdma/ib_smi.h> | |
40 | #include <linux/mlx5/driver.h> | |
41 | #include <linux/mlx5/cq.h> | |
b823dd6d | 42 | #include <linux/mlx5/fs.h> |
e126ba97 EC |
43 | #include <linux/mlx5/qp.h> |
44 | #include <linux/mlx5/srq.h> | |
2ea26203 | 45 | #include <linux/mlx5/fs.h> |
e126ba97 | 46 | #include <linux/types.h> |
146d2f1a | 47 | #include <linux/mlx5/transobj.h> |
d2370e0a | 48 | #include <rdma/ib_user_verbs.h> |
3085e29e | 49 | #include <rdma/mlx5-abi.h> |
24da0016 | 50 | #include <rdma/uverbs_ioctl.h> |
fd44e385 | 51 | #include <rdma/mlx5_user_ioctl_cmds.h> |
e126ba97 | 52 | |
5a738b5d JG |
53 | #define mlx5_ib_dbg(_dev, format, arg...) \ |
54 | dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ | |
55 | __LINE__, current->pid, ##arg) | |
e126ba97 | 56 | |
5a738b5d JG |
57 | #define mlx5_ib_err(_dev, format, arg...) \ |
58 | dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ | |
59 | __LINE__, current->pid, ##arg) | |
e126ba97 | 60 | |
5a738b5d JG |
61 | #define mlx5_ib_warn(_dev, format, arg...) \ |
62 | dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ | |
63 | __LINE__, current->pid, ##arg) | |
e126ba97 | 64 | |
b368d7cb MB |
65 | #define field_avail(type, fld, sz) (offsetof(type, fld) + \ |
66 | sizeof(((type *)0)->fld) <= (sz)) | |
cfb5e088 HA |
67 | #define MLX5_IB_DEFAULT_UIDX 0xffffff |
68 | #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) | |
b368d7cb | 69 | |
762f899a MD |
70 | #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) |
71 | ||
e126ba97 EC |
72 | enum { |
73 | MLX5_IB_MMAP_CMD_SHIFT = 8, | |
74 | MLX5_IB_MMAP_CMD_MASK = 0xff, | |
75 | }; | |
76 | ||
e126ba97 EC |
77 | enum { |
78 | MLX5_RES_SCAT_DATA32_CQE = 0x1, | |
79 | MLX5_RES_SCAT_DATA64_CQE = 0x2, | |
80 | MLX5_REQ_SCAT_DATA32_CQE = 0x11, | |
81 | MLX5_REQ_SCAT_DATA64_CQE = 0x22, | |
82 | }; | |
83 | ||
e126ba97 EC |
84 | enum mlx5_ib_mad_ifc_flags { |
85 | MLX5_MAD_IFC_IGNORE_MKEY = 1, | |
86 | MLX5_MAD_IFC_IGNORE_BKEY = 2, | |
87 | MLX5_MAD_IFC_NET_VIEW = 4, | |
88 | }; | |
89 | ||
051f2630 | 90 | enum { |
2f5ff264 | 91 | MLX5_CROSS_CHANNEL_BFREG = 0, |
051f2630 LR |
92 | }; |
93 | ||
cfb5e088 HA |
94 | enum { |
95 | MLX5_CQE_VERSION_V0, | |
96 | MLX5_CQE_VERSION_V1, | |
97 | }; | |
98 | ||
eb761894 AK |
99 | enum { |
100 | MLX5_TM_MAX_RNDV_MSG_SIZE = 64, | |
101 | MLX5_TM_MAX_SGE = 1, | |
102 | }; | |
103 | ||
4ed131d0 YH |
104 | enum { |
105 | MLX5_IB_INVALID_UAR_INDEX = BIT(31), | |
1ee47ab3 | 106 | MLX5_IB_INVALID_BFREG = BIT(31), |
4ed131d0 YH |
107 | }; |
108 | ||
24da0016 AL |
109 | enum { |
110 | MLX5_MAX_MEMIC_PAGES = 0x100, | |
111 | MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, | |
112 | }; | |
113 | ||
114 | enum { | |
115 | MLX5_MEMIC_BASE_ALIGN = 6, | |
116 | MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, | |
117 | }; | |
118 | ||
e126ba97 EC |
119 | struct mlx5_ib_ucontext { |
120 | struct ib_ucontext ibucontext; | |
121 | struct list_head db_page_list; | |
122 | ||
123 | /* protect doorbell record alloc/free | |
124 | */ | |
125 | struct mutex db_page_mutex; | |
2f5ff264 | 126 | struct mlx5_bfreg_info bfregi; |
cfb5e088 | 127 | u8 cqe_version; |
146d2f1a | 128 | /* Transport Domain number */ |
129 | u32 tdn; | |
7d0cc6ed | 130 | |
b037c29a | 131 | u64 lib_caps; |
24da0016 | 132 | DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES); |
a8b92ca1 | 133 | u16 devx_uid; |
c6a21c38 MD |
134 | /* For RoCE LAG TX affinity */ |
135 | atomic_t tx_port_affinity; | |
e126ba97 EC |
136 | }; |
137 | ||
138 | static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) | |
139 | { | |
140 | return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); | |
141 | } | |
142 | ||
143 | struct mlx5_ib_pd { | |
144 | struct ib_pd ibpd; | |
145 | u32 pdn; | |
a1069c1c | 146 | u16 uid; |
e126ba97 EC |
147 | }; |
148 | ||
b4749bf2 MB |
149 | enum { |
150 | MLX5_IB_FLOW_ACTION_MODIFY_HEADER, | |
a090d0d8 | 151 | MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, |
08aeb97c | 152 | MLX5_IB_FLOW_ACTION_DECAP, |
e126ba97 EC |
153 | }; |
154 | ||
038d2ef8 | 155 | #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) |
35d19011 | 156 | #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) |
038d2ef8 MG |
157 | #if (MLX5_IB_FLOW_LAST_PRIO <= 0) |
158 | #error "Invalid number of bypass priorities" | |
159 | #endif | |
160 | #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) | |
161 | ||
162 | #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) | |
cc0e5d42 | 163 | #define MLX5_IB_NUM_SNIFFER_FTS 2 |
802c2125 | 164 | #define MLX5_IB_NUM_EGRESS_FTS 1 |
038d2ef8 MG |
165 | struct mlx5_ib_flow_prio { |
166 | struct mlx5_flow_table *flow_table; | |
167 | unsigned int refcount; | |
168 | }; | |
169 | ||
170 | struct mlx5_ib_flow_handler { | |
171 | struct list_head list; | |
172 | struct ib_flow ibflow; | |
5497adc6 | 173 | struct mlx5_ib_flow_prio *prio; |
74491de9 | 174 | struct mlx5_flow_handle *rule; |
3b3233fb | 175 | struct ib_counters *ibcounters; |
d4be3f44 YH |
176 | struct mlx5_ib_dev *dev; |
177 | struct mlx5_ib_flow_matcher *flow_matcher; | |
038d2ef8 MG |
178 | }; |
179 | ||
fd44e385 YH |
180 | struct mlx5_ib_flow_matcher { |
181 | struct mlx5_ib_match_params matcher_mask; | |
182 | int mask_len; | |
183 | enum mlx5_ib_flow_type flow_type; | |
b47fd4ff | 184 | enum mlx5_flow_namespace_type ns_type; |
fd44e385 YH |
185 | u16 priority; |
186 | struct mlx5_core_dev *mdev; | |
187 | atomic_t usecnt; | |
188 | u8 match_criteria_enable; | |
189 | }; | |
190 | ||
038d2ef8 MG |
191 | struct mlx5_ib_flow_db { |
192 | struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; | |
78dd0c43 | 193 | struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; |
cc0e5d42 | 194 | struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; |
802c2125 | 195 | struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; |
9ef9c640 | 196 | struct mlx5_flow_table *lag_demux_ft; |
038d2ef8 MG |
197 | /* Protect flow steering bypass flow tables |
198 | * when add/del flow rules. | |
199 | * only single add/removal of flow steering rule could be done | |
200 | * simultaneously. | |
201 | */ | |
202 | struct mutex lock; | |
203 | }; | |
204 | ||
e126ba97 EC |
205 | /* Use macros here so that don't have to duplicate |
206 | * enum ib_send_flags and enum ib_qp_type for low-level driver | |
207 | */ | |
208 | ||
31616255 AK |
209 | #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) |
210 | #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) | |
211 | #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) | |
212 | #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) | |
213 | #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) | |
214 | #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END | |
56e11d62 | 215 | |
e126ba97 | 216 | #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 |
d16e91da HE |
217 | /* |
218 | * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI | |
219 | * creates the actual hardware QP. | |
220 | */ | |
221 | #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 | |
b4aaa1f0 MS |
222 | #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 |
223 | #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 | |
e126ba97 EC |
224 | #define MLX5_IB_WR_UMR IB_WR_RESERVED1 |
225 | ||
31616255 AK |
226 | #define MLX5_IB_UMR_OCTOWORD 16 |
227 | #define MLX5_IB_UMR_XLT_ALIGNMENT 64 | |
228 | ||
7d0cc6ed AK |
229 | #define MLX5_IB_UPD_XLT_ZAP BIT(0) |
230 | #define MLX5_IB_UPD_XLT_ENABLE BIT(1) | |
231 | #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) | |
232 | #define MLX5_IB_UPD_XLT_ADDR BIT(3) | |
233 | #define MLX5_IB_UPD_XLT_PD BIT(4) | |
234 | #define MLX5_IB_UPD_XLT_ACCESS BIT(5) | |
81713d37 | 235 | #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) |
7d0cc6ed | 236 | |
b11a4f9c HE |
237 | /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. |
238 | * | |
239 | * These flags are intended for internal use by the mlx5_ib driver, and they | |
240 | * rely on the range reserved for that use in the ib_qp_create_flags enum. | |
241 | */ | |
242 | ||
243 | /* Create a UD QP whose source QP number is 1 */ | |
244 | static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void) | |
245 | { | |
246 | return IB_QP_CREATE_RESERVED_START; | |
247 | } | |
248 | ||
e126ba97 EC |
249 | struct wr_list { |
250 | u16 opcode; | |
251 | u16 next; | |
252 | }; | |
253 | ||
e4cc4fa7 NO |
254 | enum mlx5_ib_rq_flags { |
255 | MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, | |
b1383aa6 | 256 | MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, |
e4cc4fa7 NO |
257 | }; |
258 | ||
e126ba97 EC |
259 | struct mlx5_ib_wq { |
260 | u64 *wrid; | |
261 | u32 *wr_data; | |
262 | struct wr_list *w_list; | |
263 | unsigned *wqe_head; | |
264 | u16 unsig_count; | |
265 | ||
266 | /* serialize post to the work queue | |
267 | */ | |
268 | spinlock_t lock; | |
269 | int wqe_cnt; | |
270 | int max_post; | |
271 | int max_gs; | |
272 | int offset; | |
273 | int wqe_shift; | |
274 | unsigned head; | |
275 | unsigned tail; | |
276 | u16 cur_post; | |
277 | u16 last_poll; | |
278 | void *qend; | |
279 | }; | |
280 | ||
03404e8a MG |
281 | enum mlx5_ib_wq_flags { |
282 | MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, | |
ccc87087 | 283 | MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, |
03404e8a MG |
284 | }; |
285 | ||
b4f34597 NO |
286 | #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 |
287 | #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 | |
288 | #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 | |
289 | #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 | |
290 | ||
79b20a6c YH |
291 | struct mlx5_ib_rwq { |
292 | struct ib_wq ibwq; | |
350d0e4c | 293 | struct mlx5_core_qp core_qp; |
79b20a6c YH |
294 | u32 rq_num_pas; |
295 | u32 log_rq_stride; | |
296 | u32 log_rq_size; | |
297 | u32 rq_page_offset; | |
298 | u32 log_page_size; | |
ccc87087 NO |
299 | u32 log_num_strides; |
300 | u32 two_byte_shift_en; | |
301 | u32 single_stride_log_num_of_bytes; | |
79b20a6c YH |
302 | struct ib_umem *umem; |
303 | size_t buf_size; | |
304 | unsigned int page_shift; | |
305 | int create_type; | |
306 | struct mlx5_db db; | |
307 | u32 user_index; | |
308 | u32 wqe_count; | |
309 | u32 wqe_shift; | |
310 | int wq_sig; | |
03404e8a | 311 | u32 create_flags; /* Use enum mlx5_ib_wq_flags */ |
79b20a6c YH |
312 | }; |
313 | ||
e126ba97 EC |
314 | enum { |
315 | MLX5_QP_USER, | |
316 | MLX5_QP_KERNEL, | |
317 | MLX5_QP_EMPTY | |
318 | }; | |
319 | ||
79b20a6c YH |
320 | enum { |
321 | MLX5_WQ_USER, | |
322 | MLX5_WQ_KERNEL | |
323 | }; | |
324 | ||
c5f90929 YH |
325 | struct mlx5_ib_rwq_ind_table { |
326 | struct ib_rwq_ind_table ib_rwq_ind_tbl; | |
327 | u32 rqtn; | |
5deba86e | 328 | u16 uid; |
c5f90929 YH |
329 | }; |
330 | ||
19098df2 | 331 | struct mlx5_ib_ubuffer { |
332 | struct ib_umem *umem; | |
333 | int buf_size; | |
334 | u64 buf_addr; | |
335 | }; | |
336 | ||
337 | struct mlx5_ib_qp_base { | |
338 | struct mlx5_ib_qp *container_mibqp; | |
339 | struct mlx5_core_qp mqp; | |
340 | struct mlx5_ib_ubuffer ubuffer; | |
341 | }; | |
342 | ||
343 | struct mlx5_ib_qp_trans { | |
344 | struct mlx5_ib_qp_base base; | |
345 | u16 xrcdn; | |
346 | u8 alt_port; | |
347 | u8 atomic_rd_en; | |
348 | u8 resp_depth; | |
349 | }; | |
350 | ||
28d61370 YH |
351 | struct mlx5_ib_rss_qp { |
352 | u32 tirn; | |
353 | }; | |
354 | ||
038d2ef8 | 355 | struct mlx5_ib_rq { |
0fb2ed66 | 356 | struct mlx5_ib_qp_base base; |
357 | struct mlx5_ib_wq *rq; | |
358 | struct mlx5_ib_ubuffer ubuffer; | |
359 | struct mlx5_db *doorbell; | |
038d2ef8 | 360 | u32 tirn; |
0fb2ed66 | 361 | u8 state; |
e4cc4fa7 | 362 | u32 flags; |
0fb2ed66 | 363 | }; |
364 | ||
365 | struct mlx5_ib_sq { | |
366 | struct mlx5_ib_qp_base base; | |
367 | struct mlx5_ib_wq *sq; | |
368 | struct mlx5_ib_ubuffer ubuffer; | |
369 | struct mlx5_db *doorbell; | |
b96c9dde | 370 | struct mlx5_flow_handle *flow_rule; |
0fb2ed66 | 371 | u32 tisn; |
372 | u8 state; | |
038d2ef8 MG |
373 | }; |
374 | ||
375 | struct mlx5_ib_raw_packet_qp { | |
0fb2ed66 | 376 | struct mlx5_ib_sq sq; |
038d2ef8 MG |
377 | struct mlx5_ib_rq rq; |
378 | }; | |
379 | ||
5fe9dec0 EC |
380 | struct mlx5_bf { |
381 | int buf_size; | |
382 | unsigned long offset; | |
383 | struct mlx5_sq_bfreg *bfreg; | |
384 | }; | |
385 | ||
b4aaa1f0 MS |
386 | struct mlx5_ib_dct { |
387 | struct mlx5_core_dct mdct; | |
388 | u32 *in; | |
389 | }; | |
390 | ||
e126ba97 EC |
391 | struct mlx5_ib_qp { |
392 | struct ib_qp ibqp; | |
038d2ef8 | 393 | union { |
0fb2ed66 | 394 | struct mlx5_ib_qp_trans trans_qp; |
395 | struct mlx5_ib_raw_packet_qp raw_packet_qp; | |
28d61370 | 396 | struct mlx5_ib_rss_qp rss_qp; |
b4aaa1f0 | 397 | struct mlx5_ib_dct dct; |
038d2ef8 | 398 | }; |
388ca8be | 399 | struct mlx5_frag_buf buf; |
e126ba97 EC |
400 | |
401 | struct mlx5_db db; | |
402 | struct mlx5_ib_wq rq; | |
403 | ||
e126ba97 | 404 | u8 sq_signal_bits; |
6e8484c5 | 405 | u8 next_fence; |
e126ba97 EC |
406 | struct mlx5_ib_wq sq; |
407 | ||
e126ba97 EC |
408 | /* serialize qp state modifications |
409 | */ | |
410 | struct mutex mutex; | |
e126ba97 EC |
411 | u32 flags; |
412 | u8 port; | |
e126ba97 | 413 | u8 state; |
e126ba97 EC |
414 | int wq_sig; |
415 | int scat_cqe; | |
416 | int max_inline_data; | |
5fe9dec0 | 417 | struct mlx5_bf bf; |
e126ba97 EC |
418 | int has_rq; |
419 | ||
420 | /* only for user space QPs. For kernel | |
421 | * we have it from the bf object | |
422 | */ | |
2f5ff264 | 423 | int bfregn; |
e126ba97 EC |
424 | |
425 | int create_type; | |
e1e66cc2 SG |
426 | |
427 | /* Store signature errors */ | |
428 | bool signature_en; | |
6aec21f6 | 429 | |
89ea94a7 MG |
430 | struct list_head qps_list; |
431 | struct list_head cq_recv_list; | |
432 | struct list_head cq_send_list; | |
61147f39 | 433 | struct mlx5_rate_limit rl; |
c2e53b2c | 434 | u32 underlay_qpn; |
175edba8 | 435 | u32 flags_en; |
b4aaa1f0 MS |
436 | /* storage for qp sub type when core qp type is IB_QPT_DRIVER */ |
437 | enum ib_qp_type qp_sub_type; | |
e126ba97 EC |
438 | }; |
439 | ||
440 | struct mlx5_ib_cq_buf { | |
388ca8be | 441 | struct mlx5_frag_buf_ctrl fbc; |
4972e6fa | 442 | struct mlx5_frag_buf frag_buf; |
e126ba97 EC |
443 | struct ib_umem *umem; |
444 | int cqe_size; | |
bde51583 | 445 | int nent; |
e126ba97 EC |
446 | }; |
447 | ||
448 | enum mlx5_ib_qp_flags { | |
f0313965 ES |
449 | MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, |
450 | MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, | |
451 | MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL, | |
452 | MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND, | |
453 | MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV, | |
454 | MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5, | |
b11a4f9c HE |
455 | /* QP uses 1 as its source QP number */ |
456 | MLX5_IB_QP_SQPN_QP1 = 1 << 6, | |
358e42ea | 457 | MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7, |
d9f88e5a | 458 | MLX5_IB_QP_RSS = 1 << 8, |
e4cc4fa7 | 459 | MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9, |
c2e53b2c | 460 | MLX5_IB_QP_UNDERLAY = 1 << 10, |
b1383aa6 | 461 | MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11, |
f95ef6cb | 462 | MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12, |
e126ba97 EC |
463 | }; |
464 | ||
968e78dd | 465 | struct mlx5_umr_wr { |
e622f2f4 | 466 | struct ib_send_wr wr; |
31616255 AK |
467 | u64 virt_addr; |
468 | u64 offset; | |
968e78dd HE |
469 | struct ib_pd *pd; |
470 | unsigned int page_shift; | |
31616255 | 471 | unsigned int xlt_size; |
b216af40 | 472 | u64 length; |
968e78dd HE |
473 | int access_flags; |
474 | u32 mkey; | |
475 | }; | |
476 | ||
f696bf6d | 477 | static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) |
e622f2f4 CH |
478 | { |
479 | return container_of(wr, struct mlx5_umr_wr, wr); | |
480 | } | |
481 | ||
e126ba97 EC |
482 | struct mlx5_shared_mr_info { |
483 | int mr_id; | |
484 | struct ib_umem *umem; | |
485 | }; | |
486 | ||
7a0c8f42 GL |
487 | enum mlx5_ib_cq_pr_flags { |
488 | MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, | |
489 | }; | |
490 | ||
e126ba97 EC |
491 | struct mlx5_ib_cq { |
492 | struct ib_cq ibcq; | |
493 | struct mlx5_core_cq mcq; | |
494 | struct mlx5_ib_cq_buf buf; | |
495 | struct mlx5_db db; | |
496 | ||
497 | /* serialize access to the CQ | |
498 | */ | |
499 | spinlock_t lock; | |
500 | ||
501 | /* protect resize cq | |
502 | */ | |
503 | struct mutex resize_mutex; | |
bde51583 | 504 | struct mlx5_ib_cq_buf *resize_buf; |
e126ba97 EC |
505 | struct ib_umem *resize_umem; |
506 | int cqe_size; | |
89ea94a7 MG |
507 | struct list_head list_send_qp; |
508 | struct list_head list_recv_qp; | |
051f2630 | 509 | u32 create_flags; |
25361e02 HE |
510 | struct list_head wc_list; |
511 | enum ib_cq_notify_flags notify_flags; | |
512 | struct work_struct notify_work; | |
7a0c8f42 | 513 | u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ |
25361e02 HE |
514 | }; |
515 | ||
516 | struct mlx5_ib_wc { | |
517 | struct ib_wc wc; | |
518 | struct list_head list; | |
e126ba97 EC |
519 | }; |
520 | ||
521 | struct mlx5_ib_srq { | |
522 | struct ib_srq ibsrq; | |
523 | struct mlx5_core_srq msrq; | |
388ca8be | 524 | struct mlx5_frag_buf buf; |
e126ba97 EC |
525 | struct mlx5_db db; |
526 | u64 *wrid; | |
527 | /* protect SRQ hanlding | |
528 | */ | |
529 | spinlock_t lock; | |
530 | int head; | |
531 | int tail; | |
532 | u16 wqe_ctr; | |
533 | struct ib_umem *umem; | |
534 | /* serialize arming a SRQ | |
535 | */ | |
536 | struct mutex mutex; | |
537 | int wq_sig; | |
538 | }; | |
539 | ||
540 | struct mlx5_ib_xrcd { | |
541 | struct ib_xrcd ibxrcd; | |
542 | u32 xrcdn; | |
d00614c0 | 543 | u16 uid; |
e126ba97 EC |
544 | }; |
545 | ||
cc149f75 HE |
546 | enum mlx5_ib_mtt_access_flags { |
547 | MLX5_IB_MTT_READ = (1 << 0), | |
548 | MLX5_IB_MTT_WRITE = (1 << 1), | |
549 | }; | |
550 | ||
24da0016 AL |
551 | struct mlx5_ib_dm { |
552 | struct ib_dm ibdm; | |
553 | phys_addr_t dev_addr; | |
554 | }; | |
555 | ||
cc149f75 HE |
556 | #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) |
557 | ||
6c29f57e AL |
558 | #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ |
559 | IB_ACCESS_REMOTE_WRITE |\ | |
560 | IB_ACCESS_REMOTE_READ |\ | |
561 | IB_ACCESS_REMOTE_ATOMIC |\ | |
562 | IB_ZERO_BASED) | |
563 | ||
e126ba97 EC |
564 | struct mlx5_ib_mr { |
565 | struct ib_mr ibmr; | |
8a187ee5 SG |
566 | void *descs; |
567 | dma_addr_t desc_map; | |
568 | int ndescs; | |
569 | int max_descs; | |
570 | int desc_size; | |
b005d316 | 571 | int access_mode; |
a606b0f6 | 572 | struct mlx5_core_mkey mmkey; |
e126ba97 EC |
573 | struct ib_umem *umem; |
574 | struct mlx5_shared_mr_info *smr_info; | |
575 | struct list_head list; | |
576 | int order; | |
8b7ff7f3 | 577 | bool allocated_from_cache; |
e126ba97 | 578 | int npages; |
746b5583 | 579 | struct mlx5_ib_dev *dev; |
ec22eb53 | 580 | u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; |
3121e3c4 | 581 | struct mlx5_core_sig_ctx *sig; |
b4cfe447 | 582 | int live; |
8a187ee5 | 583 | void *descs_alloc; |
56e11d62 | 584 | int access_flags; /* Needed for rereg MR */ |
81713d37 AK |
585 | |
586 | struct mlx5_ib_mr *parent; | |
587 | atomic_t num_leaf_free; | |
588 | wait_queue_head_t q_leaf_free; | |
e126ba97 EC |
589 | }; |
590 | ||
d2370e0a MB |
591 | struct mlx5_ib_mw { |
592 | struct ib_mw ibmw; | |
593 | struct mlx5_core_mkey mmkey; | |
db570d7d | 594 | int ndescs; |
e126ba97 EC |
595 | }; |
596 | ||
a74d2416 | 597 | struct mlx5_ib_umr_context { |
add08d76 | 598 | struct ib_cqe cqe; |
a74d2416 SR |
599 | enum ib_wc_status status; |
600 | struct completion done; | |
601 | }; | |
602 | ||
e126ba97 EC |
603 | struct umr_common { |
604 | struct ib_pd *pd; | |
605 | struct ib_cq *cq; | |
606 | struct ib_qp *qp; | |
e126ba97 EC |
607 | /* control access to UMR QP |
608 | */ | |
609 | struct semaphore sem; | |
610 | }; | |
611 | ||
612 | enum { | |
613 | MLX5_FMR_INVALID, | |
614 | MLX5_FMR_VALID, | |
615 | MLX5_FMR_BUSY, | |
616 | }; | |
617 | ||
e126ba97 EC |
618 | struct mlx5_cache_ent { |
619 | struct list_head head; | |
620 | /* sync access to the cahce entry | |
621 | */ | |
622 | spinlock_t lock; | |
623 | ||
624 | ||
625 | struct dentry *dir; | |
626 | char name[4]; | |
627 | u32 order; | |
49780d42 AK |
628 | u32 xlt; |
629 | u32 access_mode; | |
630 | u32 page; | |
631 | ||
e126ba97 EC |
632 | u32 size; |
633 | u32 cur; | |
634 | u32 miss; | |
635 | u32 limit; | |
636 | ||
637 | struct dentry *fsize; | |
638 | struct dentry *fcur; | |
639 | struct dentry *fmiss; | |
640 | struct dentry *flimit; | |
641 | ||
642 | struct mlx5_ib_dev *dev; | |
643 | struct work_struct work; | |
644 | struct delayed_work dwork; | |
746b5583 | 645 | int pending; |
49780d42 | 646 | struct completion compl; |
e126ba97 EC |
647 | }; |
648 | ||
649 | struct mlx5_mr_cache { | |
650 | struct workqueue_struct *wq; | |
651 | struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; | |
652 | int stopped; | |
653 | struct dentry *root; | |
654 | unsigned long last_add; | |
655 | }; | |
656 | ||
d16e91da HE |
657 | struct mlx5_ib_gsi_qp; |
658 | ||
659 | struct mlx5_ib_port_resources { | |
7722f47e | 660 | struct mlx5_ib_resources *devr; |
d16e91da | 661 | struct mlx5_ib_gsi_qp *gsi; |
7722f47e | 662 | struct work_struct pkey_change_work; |
d16e91da HE |
663 | }; |
664 | ||
e126ba97 EC |
665 | struct mlx5_ib_resources { |
666 | struct ib_cq *c0; | |
667 | struct ib_xrcd *x0; | |
668 | struct ib_xrcd *x1; | |
669 | struct ib_pd *p0; | |
670 | struct ib_srq *s0; | |
4aa17b28 | 671 | struct ib_srq *s1; |
d16e91da HE |
672 | struct mlx5_ib_port_resources ports[2]; |
673 | /* Protects changes to the port resources */ | |
674 | struct mutex mutex; | |
e126ba97 EC |
675 | }; |
676 | ||
e1f24a79 | 677 | struct mlx5_ib_counters { |
7c16f477 KH |
678 | const char **names; |
679 | size_t *offsets; | |
e1f24a79 PP |
680 | u32 num_q_counters; |
681 | u32 num_cong_counters; | |
9f876f3d | 682 | u32 num_ext_ppcnt_counters; |
7c16f477 | 683 | u16 set_id; |
aac4492e | 684 | bool set_id_valid; |
7c16f477 KH |
685 | }; |
686 | ||
32f69e4b DJ |
687 | struct mlx5_ib_multiport_info; |
688 | ||
689 | struct mlx5_ib_multiport { | |
690 | struct mlx5_ib_multiport_info *mpi; | |
691 | /* To be held when accessing the multiport info */ | |
692 | spinlock_t mpi_lock; | |
693 | }; | |
694 | ||
0837e86a | 695 | struct mlx5_ib_port { |
e1f24a79 | 696 | struct mlx5_ib_counters cnts; |
32f69e4b | 697 | struct mlx5_ib_multiport mp; |
a9e546e7 | 698 | struct mlx5_ib_dbg_cc_params *dbg_cc_params; |
0837e86a MB |
699 | }; |
700 | ||
fc24fc5e AS |
701 | struct mlx5_roce { |
702 | /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL | |
703 | * netdev pointer | |
704 | */ | |
705 | rwlock_t netdev_lock; | |
706 | struct net_device *netdev; | |
707 | struct notifier_block nb; | |
c6a21c38 | 708 | atomic_t tx_port_affinity; |
fd65f1b8 | 709 | enum ib_port_state last_port_state; |
7fd8aefb DJ |
710 | struct mlx5_ib_dev *dev; |
711 | u8 native_port_num; | |
fc24fc5e AS |
712 | }; |
713 | ||
4a2da0b8 PP |
714 | struct mlx5_ib_dbg_param { |
715 | int offset; | |
716 | struct mlx5_ib_dev *dev; | |
717 | struct dentry *dentry; | |
a9e546e7 | 718 | u8 port_num; |
4a2da0b8 PP |
719 | }; |
720 | ||
721 | enum mlx5_ib_dbg_cc_types { | |
722 | MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, | |
723 | MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, | |
724 | MLX5_IB_DBG_CC_RP_TIME_RESET, | |
725 | MLX5_IB_DBG_CC_RP_BYTE_RESET, | |
726 | MLX5_IB_DBG_CC_RP_THRESHOLD, | |
727 | MLX5_IB_DBG_CC_RP_AI_RATE, | |
728 | MLX5_IB_DBG_CC_RP_HAI_RATE, | |
729 | MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, | |
730 | MLX5_IB_DBG_CC_RP_MIN_RATE, | |
731 | MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, | |
732 | MLX5_IB_DBG_CC_RP_DCE_TCP_G, | |
733 | MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, | |
734 | MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, | |
735 | MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, | |
736 | MLX5_IB_DBG_CC_RP_GD, | |
737 | MLX5_IB_DBG_CC_NP_CNP_DSCP, | |
738 | MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, | |
739 | MLX5_IB_DBG_CC_NP_CNP_PRIO, | |
740 | MLX5_IB_DBG_CC_MAX, | |
741 | }; | |
742 | ||
743 | struct mlx5_ib_dbg_cc_params { | |
744 | struct dentry *root; | |
745 | struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; | |
746 | }; | |
747 | ||
03404e8a MG |
748 | enum { |
749 | MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, | |
750 | }; | |
751 | ||
fe248c3a MG |
752 | struct mlx5_ib_dbg_delay_drop { |
753 | struct dentry *dir_debugfs; | |
754 | struct dentry *rqs_cnt_debugfs; | |
755 | struct dentry *events_cnt_debugfs; | |
756 | struct dentry *timeout_debugfs; | |
757 | }; | |
758 | ||
03404e8a MG |
759 | struct mlx5_ib_delay_drop { |
760 | struct mlx5_ib_dev *dev; | |
761 | struct work_struct delay_drop_work; | |
762 | /* serialize setting of delay drop */ | |
763 | struct mutex lock; | |
764 | u32 timeout; | |
765 | bool activate; | |
fe248c3a MG |
766 | atomic_t events_cnt; |
767 | atomic_t rqs_cnt; | |
768 | struct mlx5_ib_dbg_delay_drop *dbg; | |
03404e8a MG |
769 | }; |
770 | ||
16c1975f MB |
771 | enum mlx5_ib_stages { |
772 | MLX5_IB_STAGE_INIT, | |
9a4ca38d | 773 | MLX5_IB_STAGE_FLOW_DB, |
16c1975f | 774 | MLX5_IB_STAGE_CAPS, |
8e6efa3a | 775 | MLX5_IB_STAGE_NON_DEFAULT_CB, |
16c1975f MB |
776 | MLX5_IB_STAGE_ROCE, |
777 | MLX5_IB_STAGE_DEVICE_RESOURCES, | |
778 | MLX5_IB_STAGE_ODP, | |
779 | MLX5_IB_STAGE_COUNTERS, | |
780 | MLX5_IB_STAGE_CONG_DEBUGFS, | |
781 | MLX5_IB_STAGE_UAR, | |
782 | MLX5_IB_STAGE_BFREG, | |
42cea83f | 783 | MLX5_IB_STAGE_PRE_IB_REG_UMR, |
8c84660b | 784 | MLX5_IB_STAGE_SPECS, |
16c1975f | 785 | MLX5_IB_STAGE_IB_REG, |
42cea83f | 786 | MLX5_IB_STAGE_POST_IB_REG_UMR, |
16c1975f MB |
787 | MLX5_IB_STAGE_DELAY_DROP, |
788 | MLX5_IB_STAGE_CLASS_ATTR, | |
fc385b7a | 789 | MLX5_IB_STAGE_REP_REG, |
16c1975f MB |
790 | MLX5_IB_STAGE_MAX, |
791 | }; | |
792 | ||
793 | struct mlx5_ib_stage { | |
794 | int (*init)(struct mlx5_ib_dev *dev); | |
795 | void (*cleanup)(struct mlx5_ib_dev *dev); | |
796 | }; | |
797 | ||
798 | #define STAGE_CREATE(_stage, _init, _cleanup) \ | |
799 | .stage[_stage] = {.init = _init, .cleanup = _cleanup} | |
800 | ||
801 | struct mlx5_ib_profile { | |
802 | struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; | |
803 | }; | |
804 | ||
32f69e4b DJ |
805 | struct mlx5_ib_multiport_info { |
806 | struct list_head list; | |
807 | struct mlx5_ib_dev *ibdev; | |
808 | struct mlx5_core_dev *mdev; | |
809 | struct completion unref_comp; | |
810 | u64 sys_image_guid; | |
811 | u32 mdev_refcnt; | |
812 | bool is_master; | |
813 | bool unaffiliate; | |
814 | }; | |
815 | ||
c6475a0b AY |
816 | struct mlx5_ib_flow_action { |
817 | struct ib_flow_action ib_action; | |
818 | union { | |
819 | struct { | |
820 | u64 ib_flags; | |
821 | struct mlx5_accel_esp_xfrm *ctx; | |
822 | } esp_aes_gcm; | |
b4749bf2 MB |
823 | struct { |
824 | struct mlx5_ib_dev *dev; | |
825 | u32 sub_type; | |
826 | u32 action_id; | |
827 | } flow_action_raw; | |
c6475a0b AY |
828 | }; |
829 | }; | |
830 | ||
24da0016 AL |
831 | struct mlx5_memic { |
832 | struct mlx5_core_dev *dev; | |
833 | spinlock_t memic_lock; | |
834 | DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); | |
835 | }; | |
836 | ||
5e95af5f RS |
837 | struct mlx5_read_counters_attr { |
838 | struct mlx5_fc *hw_cntrs_hndl; | |
839 | u64 *out; | |
840 | u32 flags; | |
841 | }; | |
842 | ||
3b3233fb RS |
843 | enum mlx5_ib_counters_type { |
844 | MLX5_IB_COUNTERS_FLOW, | |
845 | }; | |
846 | ||
b29e2a13 RS |
847 | struct mlx5_ib_mcounters { |
848 | struct ib_counters ibcntrs; | |
3b3233fb | 849 | enum mlx5_ib_counters_type type; |
5e95af5f RS |
850 | /* number of counters supported for this counters type */ |
851 | u32 counters_num; | |
852 | struct mlx5_fc *hw_cntrs_hndl; | |
853 | /* read function for this counters type */ | |
854 | int (*read_counters)(struct ib_device *ibdev, | |
855 | struct mlx5_read_counters_attr *read_attr); | |
3b3233fb RS |
856 | /* max index set as part of create_flow */ |
857 | u32 cntrs_max_index; | |
858 | /* number of counters data entries (<description,index> pair) */ | |
859 | u32 ncounters; | |
860 | /* counters data array for descriptions and indexes */ | |
861 | struct mlx5_ib_flow_counters_desc *counters_data; | |
862 | /* protects access to mcounters internal data */ | |
863 | struct mutex mcntrs_mutex; | |
b29e2a13 RS |
864 | }; |
865 | ||
866 | static inline struct mlx5_ib_mcounters * | |
867 | to_mcounters(struct ib_counters *ibcntrs) | |
868 | { | |
869 | return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); | |
870 | } | |
871 | ||
2ea26203 MB |
872 | int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, |
873 | bool is_egress, | |
874 | struct mlx5_flow_act *action); | |
a560f1d9 MB |
875 | struct mlx5_ib_lb_state { |
876 | /* protect the user_td */ | |
877 | struct mutex mutex; | |
878 | u32 user_td; | |
0042f9e4 MB |
879 | int qps; |
880 | bool enabled; | |
a560f1d9 MB |
881 | }; |
882 | ||
d5d284b8 SM |
883 | struct mlx5_ib_pf_eq { |
884 | struct mlx5_ib_dev *dev; | |
885 | struct mlx5_eq *core; | |
886 | struct work_struct work; | |
887 | spinlock_t lock; /* Pagefaults spinlock */ | |
888 | struct workqueue_struct *wq; | |
889 | mempool_t *pool; | |
890 | }; | |
891 | ||
e126ba97 EC |
892 | struct mlx5_ib_dev { |
893 | struct ib_device ib_dev; | |
0cbf432d | 894 | struct uapi_definition driver_defs[7]; |
9603b61d | 895 | struct mlx5_core_dev *mdev; |
7fd8aefb | 896 | struct mlx5_roce roce[MLX5_MAX_PORTS]; |
e126ba97 | 897 | int num_ports; |
e126ba97 EC |
898 | /* serialize update of capability mask |
899 | */ | |
900 | struct mutex cap_mask_mutex; | |
901 | bool ib_active; | |
902 | struct umr_common umrc; | |
903 | /* sync used page count stats | |
904 | */ | |
e126ba97 EC |
905 | struct mlx5_ib_resources devr; |
906 | struct mlx5_mr_cache cache; | |
746b5583 | 907 | struct timer_list delay_timer; |
6bc1a656 ML |
908 | /* Prevents soft lock on massive reg MRs */ |
909 | struct mutex slow_path_mutex; | |
746b5583 | 910 | int fill_delay; |
8cdd312c HE |
911 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
912 | struct ib_odp_caps odp_caps; | |
c438fde1 | 913 | u64 odp_max_size; |
d5d284b8 SM |
914 | struct mlx5_ib_pf_eq odp_pf_eq; |
915 | ||
6aec21f6 HE |
916 | /* |
917 | * Sleepable RCU that prevents destruction of MRs while they are still | |
918 | * being used by a page fault handler. | |
919 | */ | |
920 | struct srcu_struct mr_srcu; | |
81713d37 | 921 | u32 null_mkey; |
8cdd312c | 922 | #endif |
9a4ca38d | 923 | struct mlx5_ib_flow_db *flow_db; |
89ea94a7 MG |
924 | /* protect resources needed as part of reset flow */ |
925 | spinlock_t reset_flow_resource_lock; | |
926 | struct list_head qp_list; | |
0837e86a MB |
927 | /* Array with num_ports elements */ |
928 | struct mlx5_ib_port *port; | |
c85023e1 HN |
929 | struct mlx5_sq_bfreg bfreg; |
930 | struct mlx5_sq_bfreg fp_bfreg; | |
03404e8a | 931 | struct mlx5_ib_delay_drop delay_drop; |
16c1975f | 932 | const struct mlx5_ib_profile *profile; |
fc385b7a | 933 | struct mlx5_eswitch_rep *rep; |
c85023e1 | 934 | |
a560f1d9 | 935 | struct mlx5_ib_lb_state lb; |
c85023e1 | 936 | u8 umr_fence; |
32f69e4b DJ |
937 | struct list_head ib_dev_list; |
938 | u64 sys_image_guid; | |
24da0016 | 939 | struct mlx5_memic memic; |
76dc5a84 | 940 | u16 devx_whitelist_uid; |
e126ba97 EC |
941 | }; |
942 | ||
943 | static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) | |
944 | { | |
945 | return container_of(mcq, struct mlx5_ib_cq, mcq); | |
946 | } | |
947 | ||
948 | static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) | |
949 | { | |
950 | return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); | |
951 | } | |
952 | ||
953 | static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) | |
954 | { | |
955 | return container_of(ibdev, struct mlx5_ib_dev, ib_dev); | |
956 | } | |
957 | ||
e126ba97 EC |
958 | static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) |
959 | { | |
960 | return container_of(ibcq, struct mlx5_ib_cq, ibcq); | |
961 | } | |
962 | ||
963 | static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) | |
964 | { | |
19098df2 | 965 | return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; |
e126ba97 EC |
966 | } |
967 | ||
350d0e4c YH |
968 | static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) |
969 | { | |
970 | return container_of(core_qp, struct mlx5_ib_rwq, core_qp); | |
971 | } | |
972 | ||
a606b0f6 | 973 | static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey) |
d5436ba0 | 974 | { |
a606b0f6 | 975 | return container_of(mmkey, struct mlx5_ib_mr, mmkey); |
d5436ba0 SG |
976 | } |
977 | ||
e126ba97 EC |
978 | static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) |
979 | { | |
980 | return container_of(ibpd, struct mlx5_ib_pd, ibpd); | |
981 | } | |
982 | ||
983 | static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) | |
984 | { | |
985 | return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); | |
986 | } | |
987 | ||
988 | static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) | |
989 | { | |
990 | return container_of(ibqp, struct mlx5_ib_qp, ibqp); | |
991 | } | |
992 | ||
79b20a6c YH |
993 | static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) |
994 | { | |
995 | return container_of(ibwq, struct mlx5_ib_rwq, ibwq); | |
996 | } | |
997 | ||
c5f90929 YH |
998 | static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) |
999 | { | |
1000 | return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); | |
1001 | } | |
1002 | ||
e126ba97 EC |
1003 | static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) |
1004 | { | |
1005 | return container_of(msrq, struct mlx5_ib_srq, msrq); | |
1006 | } | |
1007 | ||
24da0016 AL |
1008 | static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) |
1009 | { | |
1010 | return container_of(ibdm, struct mlx5_ib_dm, ibdm); | |
1011 | } | |
1012 | ||
e126ba97 EC |
1013 | static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) |
1014 | { | |
1015 | return container_of(ibmr, struct mlx5_ib_mr, ibmr); | |
1016 | } | |
1017 | ||
d2370e0a MB |
1018 | static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) |
1019 | { | |
1020 | return container_of(ibmw, struct mlx5_ib_mw, ibmw); | |
1021 | } | |
1022 | ||
c6475a0b AY |
1023 | static inline struct mlx5_ib_flow_action * |
1024 | to_mflow_act(struct ib_flow_action *ibact) | |
1025 | { | |
1026 | return container_of(ibact, struct mlx5_ib_flow_action, ib_action); | |
1027 | } | |
1028 | ||
e126ba97 EC |
1029 | int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, |
1030 | struct mlx5_db *db); | |
1031 | void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); | |
1032 | void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
1033 | void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); | |
1034 | void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); | |
1035 | int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, | |
a97e2d86 IW |
1036 | u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
1037 | const void *in_mad, void *response_mad); | |
90898850 | 1038 | struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, |
477864c8 | 1039 | struct ib_udata *udata); |
90898850 | 1040 | int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
e126ba97 EC |
1041 | int mlx5_ib_destroy_ah(struct ib_ah *ah); |
1042 | struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, | |
1043 | struct ib_srq_init_attr *init_attr, | |
1044 | struct ib_udata *udata); | |
1045 | int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, | |
1046 | enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); | |
1047 | int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); | |
1048 | int mlx5_ib_destroy_srq(struct ib_srq *srq); | |
d34ac5cd BVA |
1049 | int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, |
1050 | const struct ib_recv_wr **bad_wr); | |
0042f9e4 MB |
1051 | int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); |
1052 | void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); | |
e126ba97 EC |
1053 | struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, |
1054 | struct ib_qp_init_attr *init_attr, | |
1055 | struct ib_udata *udata); | |
1056 | int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1057 | int attr_mask, struct ib_udata *udata); | |
1058 | int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
1059 | struct ib_qp_init_attr *qp_init_attr); | |
1060 | int mlx5_ib_destroy_qp(struct ib_qp *qp); | |
d0e84c0a YH |
1061 | void mlx5_ib_drain_sq(struct ib_qp *qp); |
1062 | void mlx5_ib_drain_rq(struct ib_qp *qp); | |
d34ac5cd BVA |
1063 | int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
1064 | const struct ib_send_wr **bad_wr); | |
1065 | int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, | |
1066 | const struct ib_recv_wr **bad_wr); | |
e126ba97 | 1067 | void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n); |
c1395a2a | 1068 | int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, |
19098df2 | 1069 | void *buffer, u32 length, |
1070 | struct mlx5_ib_qp_base *base); | |
bcf4c1ea MB |
1071 | struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev, |
1072 | const struct ib_cq_init_attr *attr, | |
1073 | struct ib_ucontext *context, | |
e126ba97 EC |
1074 | struct ib_udata *udata); |
1075 | int mlx5_ib_destroy_cq(struct ib_cq *cq); | |
1076 | int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); | |
1077 | int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); | |
1078 | int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); | |
1079 | int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); | |
1080 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); | |
1081 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
1082 | u64 virt_addr, int access_flags, | |
1083 | struct ib_udata *udata); | |
d2370e0a MB |
1084 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
1085 | struct ib_udata *udata); | |
1086 | int mlx5_ib_dealloc_mw(struct ib_mw *mw); | |
7d0cc6ed AK |
1087 | int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, |
1088 | int page_shift, int flags); | |
81713d37 AK |
1089 | struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, |
1090 | int access_flags); | |
1091 | void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); | |
56e11d62 NO |
1092 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, |
1093 | u64 length, u64 virt_addr, int access_flags, | |
1094 | struct ib_pd *pd, struct ib_udata *udata); | |
e126ba97 | 1095 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr); |
9bee178b SG |
1096 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
1097 | enum ib_mr_type mr_type, | |
1098 | u32 max_num_sg); | |
ff2ba993 | 1099 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 1100 | unsigned int *sg_offset); |
e126ba97 | 1101 | int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, |
a97e2d86 | 1102 | const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
4cd7c947 IW |
1103 | const struct ib_mad_hdr *in, size_t in_mad_size, |
1104 | struct ib_mad_hdr *out, size_t *out_mad_size, | |
1105 | u16 *out_mad_pkey_index); | |
e126ba97 EC |
1106 | struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, |
1107 | struct ib_ucontext *context, | |
1108 | struct ib_udata *udata); | |
1109 | int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd); | |
e126ba97 EC |
1110 | int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); |
1111 | int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); | |
1b5daf11 MD |
1112 | int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, |
1113 | struct ib_smp *out_mad); | |
1114 | int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, | |
1115 | __be64 *sys_image_guid); | |
1116 | int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, | |
1117 | u16 *max_pkeys); | |
1118 | int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, | |
1119 | u32 *vendor_id); | |
1120 | int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); | |
1121 | int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); | |
1122 | int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, | |
1123 | u16 *pkey); | |
1124 | int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, | |
1125 | union ib_gid *gid); | |
1126 | int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, | |
1127 | struct ib_port_attr *props); | |
e126ba97 EC |
1128 | int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, |
1129 | struct ib_port_attr *props); | |
1130 | int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); | |
1131 | void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); | |
762f899a MD |
1132 | void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, |
1133 | unsigned long max_page_shift, | |
1134 | int *count, int *shift, | |
e126ba97 | 1135 | int *ncont, int *order); |
832a6b06 HE |
1136 | void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
1137 | int page_shift, size_t offset, size_t num_pages, | |
1138 | __be64 *pas, int access_flags); | |
e126ba97 | 1139 | void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
cc149f75 | 1140 | int page_shift, __be64 *pas, int access_flags); |
e126ba97 | 1141 | void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); |
5d6ff1ba | 1142 | int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); |
e126ba97 EC |
1143 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); |
1144 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); | |
49780d42 AK |
1145 | |
1146 | struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry); | |
1147 | void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); | |
d5436ba0 SG |
1148 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
1149 | struct ib_mr_status *mr_status); | |
79b20a6c YH |
1150 | struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, |
1151 | struct ib_wq_init_attr *init_attr, | |
1152 | struct ib_udata *udata); | |
1153 | int mlx5_ib_destroy_wq(struct ib_wq *wq); | |
1154 | int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, | |
1155 | u32 wq_attr_mask, struct ib_udata *udata); | |
c5f90929 YH |
1156 | struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, |
1157 | struct ib_rwq_ind_table_init_attr *init_attr, | |
1158 | struct ib_udata *udata); | |
1159 | int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); | |
776a3906 | 1160 | bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev); |
24da0016 AL |
1161 | struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, |
1162 | struct ib_ucontext *context, | |
1163 | struct ib_dm_alloc_attr *attr, | |
1164 | struct uverbs_attr_bundle *attrs); | |
1165 | int mlx5_ib_dealloc_dm(struct ib_dm *ibdm); | |
6c29f57e AL |
1166 | struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, |
1167 | struct ib_dm_mr_attr *attr, | |
1168 | struct uverbs_attr_bundle *attrs); | |
e126ba97 | 1169 | |
8cdd312c | 1170 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
938fe83c | 1171 | void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); |
6aec21f6 | 1172 | int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); |
d5d284b8 | 1173 | void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); |
6aec21f6 HE |
1174 | int __init mlx5_ib_odp_init(void); |
1175 | void mlx5_ib_odp_cleanup(void); | |
b5231b01 | 1176 | void mlx5_ib_invalidate_range(struct ib_umem_odp *umem_odp, unsigned long start, |
b4cfe447 | 1177 | unsigned long end); |
81713d37 AK |
1178 | void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); |
1179 | void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, | |
1180 | size_t nentries, struct mlx5_ib_mr *mr, int flags); | |
6aec21f6 | 1181 | #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ |
938fe83c | 1182 | static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) |
8cdd312c | 1183 | { |
938fe83c | 1184 | return; |
8cdd312c | 1185 | } |
6aec21f6 | 1186 | |
6aec21f6 | 1187 | static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } |
d5d284b8 | 1188 | static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} |
6aec21f6 | 1189 | static inline int mlx5_ib_odp_init(void) { return 0; } |
81713d37 AK |
1190 | static inline void mlx5_ib_odp_cleanup(void) {} |
1191 | static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} | |
1192 | static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, | |
1193 | size_t nentries, struct mlx5_ib_mr *mr, | |
1194 | int flags) {} | |
6aec21f6 | 1195 | |
8cdd312c HE |
1196 | #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ |
1197 | ||
b5ca15ad MB |
1198 | /* Needed for rep profile */ |
1199 | int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev); | |
1200 | void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev); | |
1201 | int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev); | |
1202 | int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev); | |
1203 | int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev); | |
1204 | int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev); | |
1205 | void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev); | |
1206 | int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev); | |
1207 | void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev); | |
1208 | int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev); | |
1209 | void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev); | |
1210 | int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev); | |
1211 | void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev); | |
2d873449 | 1212 | void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev); |
b5ca15ad MB |
1213 | int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev); |
1214 | void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev); | |
2d873449 | 1215 | int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev); |
b5ca15ad MB |
1216 | void __mlx5_ib_remove(struct mlx5_ib_dev *dev, |
1217 | const struct mlx5_ib_profile *profile, | |
1218 | int stage); | |
1219 | void *__mlx5_ib_add(struct mlx5_ib_dev *dev, | |
1220 | const struct mlx5_ib_profile *profile); | |
1221 | ||
9967c70a AB |
1222 | int mlx5_ib_get_vf_config(struct ib_device *device, int vf, |
1223 | u8 port, struct ifla_vf_info *info); | |
1224 | int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, | |
1225 | u8 port, int state); | |
1226 | int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, | |
1227 | u8 port, struct ifla_vf_stats *stats); | |
1228 | int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, | |
1229 | u64 guid, int type); | |
1230 | ||
47ec3866 PP |
1231 | __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, |
1232 | const struct ib_gid_attr *attr); | |
2811ba51 | 1233 | |
a9e546e7 PP |
1234 | void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); |
1235 | int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); | |
4a2da0b8 | 1236 | |
d16e91da HE |
1237 | /* GSI QP helper functions */ |
1238 | struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, | |
1239 | struct ib_qp_init_attr *init_attr); | |
1240 | int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); | |
1241 | int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, | |
1242 | int attr_mask); | |
1243 | int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, | |
1244 | int qp_attr_mask, | |
1245 | struct ib_qp_init_attr *qp_init_attr); | |
d34ac5cd BVA |
1246 | int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, |
1247 | const struct ib_send_wr **bad_wr); | |
1248 | int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, | |
1249 | const struct ib_recv_wr **bad_wr); | |
7722f47e | 1250 | void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); |
d16e91da | 1251 | |
25361e02 HE |
1252 | int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); |
1253 | ||
4ed131d0 YH |
1254 | void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, |
1255 | int bfregn); | |
32f69e4b DJ |
1256 | struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); |
1257 | struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, | |
1258 | u8 ib_port_num, | |
1259 | u8 *native_port_num); | |
1260 | void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, | |
1261 | u8 port_num); | |
4ed131d0 | 1262 | |
a8b92ca1 | 1263 | #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS) |
76dc5a84 YH |
1264 | int mlx5_ib_devx_create(struct mlx5_ib_dev *dev); |
1265 | void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid); | |
c59450c4 | 1266 | const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void); |
0cbf432d JG |
1267 | extern const struct uapi_definition mlx5_ib_devx_defs[]; |
1268 | extern const struct uapi_definition mlx5_ib_flow_defs[]; | |
32269441 YH |
1269 | struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add( |
1270 | struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher, | |
b823dd6d MB |
1271 | struct mlx5_flow_act *flow_act, void *cmd_in, int inlen, |
1272 | int dest_id, int dest_type); | |
32269441 | 1273 | bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type); |
b4749bf2 | 1274 | void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction); |
a8b92ca1 YH |
1275 | #else |
1276 | static inline int | |
76dc5a84 YH |
1277 | mlx5_ib_devx_create(struct mlx5_ib_dev *dev) { return -EOPNOTSUPP; }; |
1278 | static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev, u16 uid) {} | |
32269441 YH |
1279 | static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, |
1280 | int *dest_type) | |
1281 | { | |
1282 | return false; | |
1283 | } | |
b4749bf2 MB |
1284 | static inline void |
1285 | mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction) | |
1286 | { | |
1287 | return; | |
1288 | }; | |
a8b92ca1 | 1289 | #endif |
e126ba97 EC |
1290 | static inline void init_query_mad(struct ib_smp *mad) |
1291 | { | |
1292 | mad->base_version = 1; | |
1293 | mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; | |
1294 | mad->class_version = 1; | |
1295 | mad->method = IB_MGMT_METHOD_GET; | |
1296 | } | |
1297 | ||
1298 | static inline u8 convert_access(int acc) | |
1299 | { | |
1300 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | | |
1301 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | | |
1302 | (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | | |
1303 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | | |
1304 | MLX5_PERM_LOCAL_READ; | |
1305 | } | |
1306 | ||
b636401f SG |
1307 | static inline int is_qp1(enum ib_qp_type qp_type) |
1308 | { | |
d16e91da | 1309 | return qp_type == MLX5_IB_QPT_HW_GSI; |
b636401f SG |
1310 | } |
1311 | ||
cc149f75 HE |
1312 | #define MLX5_MAX_UMR_SHIFT 16 |
1313 | #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) | |
1314 | ||
051f2630 LR |
1315 | static inline u32 check_cq_create_flags(u32 flags) |
1316 | { | |
1317 | /* | |
1318 | * It returns non-zero value for unsupported CQ | |
1319 | * create flags, otherwise it returns zero. | |
1320 | */ | |
beb801ac JG |
1321 | return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | |
1322 | IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); | |
051f2630 | 1323 | } |
cfb5e088 HA |
1324 | |
1325 | static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, | |
1326 | u32 *user_index) | |
1327 | { | |
1328 | if (cqe_version) { | |
1329 | if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || | |
1330 | (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) | |
1331 | return -EINVAL; | |
1332 | *user_index = cmd_uidx; | |
1333 | } else { | |
1334 | *user_index = MLX5_IB_DEFAULT_UIDX; | |
1335 | } | |
1336 | ||
1337 | return 0; | |
1338 | } | |
3085e29e LR |
1339 | |
1340 | static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, | |
1341 | struct mlx5_ib_create_qp *ucmd, | |
1342 | int inlen, | |
1343 | u32 *user_index) | |
1344 | { | |
1345 | u8 cqe_version = ucontext->cqe_version; | |
1346 | ||
1347 | if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) && | |
1348 | !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) | |
1349 | return 0; | |
1350 | ||
1351 | if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) != | |
1352 | !!cqe_version)) | |
1353 | return -EINVAL; | |
1354 | ||
1355 | return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); | |
1356 | } | |
1357 | ||
1358 | static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, | |
1359 | struct mlx5_ib_create_srq *ucmd, | |
1360 | int inlen, | |
1361 | u32 *user_index) | |
1362 | { | |
1363 | u8 cqe_version = ucontext->cqe_version; | |
1364 | ||
1365 | if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) && | |
1366 | !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) | |
1367 | return 0; | |
1368 | ||
1369 | if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) != | |
1370 | !!cqe_version)) | |
1371 | return -EINVAL; | |
1372 | ||
1373 | return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); | |
1374 | } | |
b037c29a EC |
1375 | |
1376 | static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) | |
1377 | { | |
1378 | return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? | |
1379 | MLX5_UARS_IN_PAGE : 1; | |
1380 | } | |
1381 | ||
31a78a5a YH |
1382 | static inline int get_num_static_uars(struct mlx5_ib_dev *dev, |
1383 | struct mlx5_bfreg_info *bfregi) | |
b037c29a | 1384 | { |
31a78a5a | 1385 | return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; |
b037c29a EC |
1386 | } |
1387 | ||
c44ef998 IL |
1388 | unsigned long mlx5_ib_get_xlt_emergency_page(void); |
1389 | void mlx5_ib_put_xlt_emergency_page(void); | |
1390 | ||
7c043e90 | 1391 | int bfregn_to_uar_index(struct mlx5_ib_dev *dev, |
05f58ceb | 1392 | struct mlx5_bfreg_info *bfregi, u32 bfregn, |
7c043e90 | 1393 | bool dyn_bfreg); |
e126ba97 | 1394 | #endif /* MLX5_IB_H */ |