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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | ||
34 | #include <linux/kref.h> | |
35 | #include <linux/random.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/export.h> | |
746b5583 | 38 | #include <linux/delay.h> |
e126ba97 | 39 | #include <rdma/ib_umem.h> |
b4cfe447 | 40 | #include <rdma/ib_umem_odp.h> |
968e78dd | 41 | #include <rdma/ib_verbs.h> |
e126ba97 EC |
42 | #include "mlx5_ib.h" |
43 | ||
44 | enum { | |
746b5583 | 45 | MAX_PENDING_REG_MR = 8, |
e126ba97 EC |
46 | }; |
47 | ||
832a6b06 HE |
48 | #define MLX5_UMR_ALIGN 2048 |
49 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
50 | static __be64 mlx5_ib_update_mtt_emergency_buffer[ | |
51 | MLX5_UMR_MTT_MIN_CHUNK_SIZE/sizeof(__be64)] | |
52 | __aligned(MLX5_UMR_ALIGN); | |
53 | static DEFINE_MUTEX(mlx5_ib_update_mtt_emergency_buffer_mutex); | |
54 | #endif | |
fe45f827 | 55 | |
6aec21f6 HE |
56 | static int clean_mr(struct mlx5_ib_mr *mr); |
57 | ||
b4cfe447 HE |
58 | static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
59 | { | |
a606b0f6 | 60 | int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
b4cfe447 HE |
61 | |
62 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
63 | /* Wait until all page fault handlers using the mr complete. */ | |
64 | synchronize_srcu(&dev->mr_srcu); | |
65 | #endif | |
66 | ||
67 | return err; | |
68 | } | |
69 | ||
e126ba97 EC |
70 | static int order2idx(struct mlx5_ib_dev *dev, int order) |
71 | { | |
72 | struct mlx5_mr_cache *cache = &dev->cache; | |
73 | ||
74 | if (order < cache->ent[0].order) | |
75 | return 0; | |
76 | else | |
77 | return order - cache->ent[0].order; | |
78 | } | |
79 | ||
56e11d62 NO |
80 | static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) |
81 | { | |
82 | return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= | |
83 | length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); | |
84 | } | |
85 | ||
395a8e4c NO |
86 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
87 | static void update_odp_mr(struct mlx5_ib_mr *mr) | |
88 | { | |
89 | if (mr->umem->odp_data) { | |
90 | /* | |
91 | * This barrier prevents the compiler from moving the | |
92 | * setting of umem->odp_data->private to point to our | |
93 | * MR, before reg_umr finished, to ensure that the MR | |
94 | * initialization have finished before starting to | |
95 | * handle invalidations. | |
96 | */ | |
97 | smp_wmb(); | |
98 | mr->umem->odp_data->private = mr; | |
99 | /* | |
100 | * Make sure we will see the new | |
101 | * umem->odp_data->private value in the invalidation | |
102 | * routines, before we can get page faults on the | |
103 | * MR. Page faults can happen once we put the MR in | |
104 | * the tree, below this line. Without the barrier, | |
105 | * there can be a fault handling and an invalidation | |
106 | * before umem->odp_data->private == mr is visible to | |
107 | * the invalidation handler. | |
108 | */ | |
109 | smp_wmb(); | |
110 | } | |
111 | } | |
112 | #endif | |
113 | ||
746b5583 EC |
114 | static void reg_mr_callback(int status, void *context) |
115 | { | |
116 | struct mlx5_ib_mr *mr = context; | |
117 | struct mlx5_ib_dev *dev = mr->dev; | |
118 | struct mlx5_mr_cache *cache = &dev->cache; | |
119 | int c = order2idx(dev, mr->order); | |
120 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
121 | u8 key; | |
746b5583 | 122 | unsigned long flags; |
a606b0f6 | 123 | struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table; |
8605933a | 124 | int err; |
746b5583 | 125 | |
746b5583 EC |
126 | spin_lock_irqsave(&ent->lock, flags); |
127 | ent->pending--; | |
128 | spin_unlock_irqrestore(&ent->lock, flags); | |
129 | if (status) { | |
130 | mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); | |
131 | kfree(mr); | |
132 | dev->fill_delay = 1; | |
133 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
134 | return; | |
135 | } | |
136 | ||
9603b61d JM |
137 | spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); |
138 | key = dev->mdev->priv.mkey_key++; | |
139 | spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); | |
ec22eb53 | 140 | mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key; |
746b5583 EC |
141 | |
142 | cache->last_add = jiffies; | |
143 | ||
144 | spin_lock_irqsave(&ent->lock, flags); | |
145 | list_add_tail(&mr->list, &ent->head); | |
146 | ent->cur++; | |
147 | ent->size++; | |
148 | spin_unlock_irqrestore(&ent->lock, flags); | |
8605933a HE |
149 | |
150 | write_lock_irqsave(&table->lock, flags); | |
a606b0f6 MB |
151 | err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key), |
152 | &mr->mmkey); | |
8605933a | 153 | if (err) |
a606b0f6 | 154 | pr_err("Error inserting to mkey tree. 0x%x\n", -err); |
8605933a | 155 | write_unlock_irqrestore(&table->lock, flags); |
746b5583 EC |
156 | } |
157 | ||
e126ba97 EC |
158 | static int add_keys(struct mlx5_ib_dev *dev, int c, int num) |
159 | { | |
e126ba97 EC |
160 | struct mlx5_mr_cache *cache = &dev->cache; |
161 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
ec22eb53 | 162 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
e126ba97 EC |
163 | struct mlx5_ib_mr *mr; |
164 | int npages = 1 << ent->order; | |
ec22eb53 SM |
165 | void *mkc; |
166 | u32 *in; | |
e126ba97 EC |
167 | int err = 0; |
168 | int i; | |
169 | ||
ec22eb53 | 170 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
171 | if (!in) |
172 | return -ENOMEM; | |
173 | ||
ec22eb53 | 174 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
e126ba97 | 175 | for (i = 0; i < num; i++) { |
746b5583 EC |
176 | if (ent->pending >= MAX_PENDING_REG_MR) { |
177 | err = -EAGAIN; | |
178 | break; | |
179 | } | |
180 | ||
e126ba97 EC |
181 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
182 | if (!mr) { | |
183 | err = -ENOMEM; | |
746b5583 | 184 | break; |
e126ba97 EC |
185 | } |
186 | mr->order = ent->order; | |
187 | mr->umred = 1; | |
746b5583 | 188 | mr->dev = dev; |
ec22eb53 SM |
189 | |
190 | MLX5_SET(mkc, mkc, free, 1); | |
191 | MLX5_SET(mkc, mkc, umr_en, 1); | |
192 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); | |
193 | ||
194 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
195 | MLX5_SET(mkc, mkc, translations_octword_size, (npages + 1) / 2); | |
196 | MLX5_SET(mkc, mkc, log_page_size, 12); | |
e126ba97 | 197 | |
746b5583 EC |
198 | spin_lock_irq(&ent->lock); |
199 | ent->pending++; | |
200 | spin_unlock_irq(&ent->lock); | |
ec22eb53 SM |
201 | err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey, |
202 | in, inlen, | |
203 | mr->out, sizeof(mr->out), | |
204 | reg_mr_callback, mr); | |
e126ba97 | 205 | if (err) { |
d14e7110 EC |
206 | spin_lock_irq(&ent->lock); |
207 | ent->pending--; | |
208 | spin_unlock_irq(&ent->lock); | |
e126ba97 | 209 | mlx5_ib_warn(dev, "create mkey failed %d\n", err); |
e126ba97 | 210 | kfree(mr); |
746b5583 | 211 | break; |
e126ba97 | 212 | } |
e126ba97 EC |
213 | } |
214 | ||
e126ba97 EC |
215 | kfree(in); |
216 | return err; | |
217 | } | |
218 | ||
219 | static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) | |
220 | { | |
e126ba97 EC |
221 | struct mlx5_mr_cache *cache = &dev->cache; |
222 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
223 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
224 | int err; |
225 | int i; | |
226 | ||
227 | for (i = 0; i < num; i++) { | |
746b5583 | 228 | spin_lock_irq(&ent->lock); |
e126ba97 | 229 | if (list_empty(&ent->head)) { |
746b5583 | 230 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
231 | return; |
232 | } | |
233 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
234 | list_del(&mr->list); | |
235 | ent->cur--; | |
236 | ent->size--; | |
746b5583 | 237 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 238 | err = destroy_mkey(dev, mr); |
203099fd | 239 | if (err) |
e126ba97 | 240 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 241 | else |
e126ba97 | 242 | kfree(mr); |
e126ba97 EC |
243 | } |
244 | } | |
245 | ||
246 | static ssize_t size_write(struct file *filp, const char __user *buf, | |
247 | size_t count, loff_t *pos) | |
248 | { | |
249 | struct mlx5_cache_ent *ent = filp->private_data; | |
250 | struct mlx5_ib_dev *dev = ent->dev; | |
251 | char lbuf[20]; | |
252 | u32 var; | |
253 | int err; | |
254 | int c; | |
255 | ||
256 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 257 | return -EFAULT; |
e126ba97 EC |
258 | |
259 | c = order2idx(dev, ent->order); | |
260 | lbuf[sizeof(lbuf) - 1] = 0; | |
261 | ||
262 | if (sscanf(lbuf, "%u", &var) != 1) | |
263 | return -EINVAL; | |
264 | ||
265 | if (var < ent->limit) | |
266 | return -EINVAL; | |
267 | ||
268 | if (var > ent->size) { | |
746b5583 EC |
269 | do { |
270 | err = add_keys(dev, c, var - ent->size); | |
271 | if (err && err != -EAGAIN) | |
272 | return err; | |
273 | ||
274 | usleep_range(3000, 5000); | |
275 | } while (err); | |
e126ba97 EC |
276 | } else if (var < ent->size) { |
277 | remove_keys(dev, c, ent->size - var); | |
278 | } | |
279 | ||
280 | return count; | |
281 | } | |
282 | ||
283 | static ssize_t size_read(struct file *filp, char __user *buf, size_t count, | |
284 | loff_t *pos) | |
285 | { | |
286 | struct mlx5_cache_ent *ent = filp->private_data; | |
287 | char lbuf[20]; | |
288 | int err; | |
289 | ||
290 | if (*pos) | |
291 | return 0; | |
292 | ||
293 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); | |
294 | if (err < 0) | |
295 | return err; | |
296 | ||
297 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 298 | return -EFAULT; |
e126ba97 EC |
299 | |
300 | *pos += err; | |
301 | ||
302 | return err; | |
303 | } | |
304 | ||
305 | static const struct file_operations size_fops = { | |
306 | .owner = THIS_MODULE, | |
307 | .open = simple_open, | |
308 | .write = size_write, | |
309 | .read = size_read, | |
310 | }; | |
311 | ||
312 | static ssize_t limit_write(struct file *filp, const char __user *buf, | |
313 | size_t count, loff_t *pos) | |
314 | { | |
315 | struct mlx5_cache_ent *ent = filp->private_data; | |
316 | struct mlx5_ib_dev *dev = ent->dev; | |
317 | char lbuf[20]; | |
318 | u32 var; | |
319 | int err; | |
320 | int c; | |
321 | ||
322 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 323 | return -EFAULT; |
e126ba97 EC |
324 | |
325 | c = order2idx(dev, ent->order); | |
326 | lbuf[sizeof(lbuf) - 1] = 0; | |
327 | ||
328 | if (sscanf(lbuf, "%u", &var) != 1) | |
329 | return -EINVAL; | |
330 | ||
331 | if (var > ent->size) | |
332 | return -EINVAL; | |
333 | ||
334 | ent->limit = var; | |
335 | ||
336 | if (ent->cur < ent->limit) { | |
337 | err = add_keys(dev, c, 2 * ent->limit - ent->cur); | |
338 | if (err) | |
339 | return err; | |
340 | } | |
341 | ||
342 | return count; | |
343 | } | |
344 | ||
345 | static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, | |
346 | loff_t *pos) | |
347 | { | |
348 | struct mlx5_cache_ent *ent = filp->private_data; | |
349 | char lbuf[20]; | |
350 | int err; | |
351 | ||
352 | if (*pos) | |
353 | return 0; | |
354 | ||
355 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); | |
356 | if (err < 0) | |
357 | return err; | |
358 | ||
359 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 360 | return -EFAULT; |
e126ba97 EC |
361 | |
362 | *pos += err; | |
363 | ||
364 | return err; | |
365 | } | |
366 | ||
367 | static const struct file_operations limit_fops = { | |
368 | .owner = THIS_MODULE, | |
369 | .open = simple_open, | |
370 | .write = limit_write, | |
371 | .read = limit_read, | |
372 | }; | |
373 | ||
374 | static int someone_adding(struct mlx5_mr_cache *cache) | |
375 | { | |
376 | int i; | |
377 | ||
378 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
379 | if (cache->ent[i].cur < cache->ent[i].limit) | |
380 | return 1; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static void __cache_work_func(struct mlx5_cache_ent *ent) | |
387 | { | |
388 | struct mlx5_ib_dev *dev = ent->dev; | |
389 | struct mlx5_mr_cache *cache = &dev->cache; | |
390 | int i = order2idx(dev, ent->order); | |
746b5583 | 391 | int err; |
e126ba97 EC |
392 | |
393 | if (cache->stopped) | |
394 | return; | |
395 | ||
396 | ent = &dev->cache.ent[i]; | |
746b5583 EC |
397 | if (ent->cur < 2 * ent->limit && !dev->fill_delay) { |
398 | err = add_keys(dev, i, 1); | |
399 | if (ent->cur < 2 * ent->limit) { | |
400 | if (err == -EAGAIN) { | |
401 | mlx5_ib_dbg(dev, "returned eagain, order %d\n", | |
402 | i + 2); | |
403 | queue_delayed_work(cache->wq, &ent->dwork, | |
404 | msecs_to_jiffies(3)); | |
405 | } else if (err) { | |
406 | mlx5_ib_warn(dev, "command failed order %d, err %d\n", | |
407 | i + 2, err); | |
408 | queue_delayed_work(cache->wq, &ent->dwork, | |
409 | msecs_to_jiffies(1000)); | |
410 | } else { | |
411 | queue_work(cache->wq, &ent->work); | |
412 | } | |
413 | } | |
e126ba97 | 414 | } else if (ent->cur > 2 * ent->limit) { |
ab5cdc31 LR |
415 | /* |
416 | * The remove_keys() logic is performed as garbage collection | |
417 | * task. Such task is intended to be run when no other active | |
418 | * processes are running. | |
419 | * | |
420 | * The need_resched() will return TRUE if there are user tasks | |
421 | * to be activated in near future. | |
422 | * | |
423 | * In such case, we don't execute remove_keys() and postpone | |
424 | * the garbage collection work to try to run in next cycle, | |
425 | * in order to free CPU resources to other tasks. | |
426 | */ | |
427 | if (!need_resched() && !someone_adding(cache) && | |
746b5583 | 428 | time_after(jiffies, cache->last_add + 300 * HZ)) { |
e126ba97 EC |
429 | remove_keys(dev, i, 1); |
430 | if (ent->cur > ent->limit) | |
431 | queue_work(cache->wq, &ent->work); | |
432 | } else { | |
746b5583 | 433 | queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); |
e126ba97 EC |
434 | } |
435 | } | |
436 | } | |
437 | ||
438 | static void delayed_cache_work_func(struct work_struct *work) | |
439 | { | |
440 | struct mlx5_cache_ent *ent; | |
441 | ||
442 | ent = container_of(work, struct mlx5_cache_ent, dwork.work); | |
443 | __cache_work_func(ent); | |
444 | } | |
445 | ||
446 | static void cache_work_func(struct work_struct *work) | |
447 | { | |
448 | struct mlx5_cache_ent *ent; | |
449 | ||
450 | ent = container_of(work, struct mlx5_cache_ent, work); | |
451 | __cache_work_func(ent); | |
452 | } | |
453 | ||
454 | static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) | |
455 | { | |
456 | struct mlx5_mr_cache *cache = &dev->cache; | |
457 | struct mlx5_ib_mr *mr = NULL; | |
458 | struct mlx5_cache_ent *ent; | |
459 | int c; | |
460 | int i; | |
461 | ||
462 | c = order2idx(dev, order); | |
463 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
464 | mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); | |
465 | return NULL; | |
466 | } | |
467 | ||
468 | for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) { | |
469 | ent = &cache->ent[i]; | |
470 | ||
471 | mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); | |
472 | ||
746b5583 | 473 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
474 | if (!list_empty(&ent->head)) { |
475 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
476 | list); | |
477 | list_del(&mr->list); | |
478 | ent->cur--; | |
746b5583 | 479 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
480 | if (ent->cur < ent->limit) |
481 | queue_work(cache->wq, &ent->work); | |
482 | break; | |
483 | } | |
746b5583 | 484 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
485 | |
486 | queue_work(cache->wq, &ent->work); | |
e126ba97 EC |
487 | } |
488 | ||
489 | if (!mr) | |
490 | cache->ent[c].miss++; | |
491 | ||
492 | return mr; | |
493 | } | |
494 | ||
495 | static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
496 | { | |
497 | struct mlx5_mr_cache *cache = &dev->cache; | |
498 | struct mlx5_cache_ent *ent; | |
499 | int shrink = 0; | |
500 | int c; | |
501 | ||
502 | c = order2idx(dev, mr->order); | |
503 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
504 | mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); | |
505 | return; | |
506 | } | |
507 | ent = &cache->ent[c]; | |
746b5583 | 508 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
509 | list_add_tail(&mr->list, &ent->head); |
510 | ent->cur++; | |
511 | if (ent->cur > 2 * ent->limit) | |
512 | shrink = 1; | |
746b5583 | 513 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
514 | |
515 | if (shrink) | |
516 | queue_work(cache->wq, &ent->work); | |
517 | } | |
518 | ||
519 | static void clean_keys(struct mlx5_ib_dev *dev, int c) | |
520 | { | |
e126ba97 EC |
521 | struct mlx5_mr_cache *cache = &dev->cache; |
522 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
523 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
524 | int err; |
525 | ||
3c461911 | 526 | cancel_delayed_work(&ent->dwork); |
e126ba97 | 527 | while (1) { |
746b5583 | 528 | spin_lock_irq(&ent->lock); |
e126ba97 | 529 | if (list_empty(&ent->head)) { |
746b5583 | 530 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
531 | return; |
532 | } | |
533 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
534 | list_del(&mr->list); | |
535 | ent->cur--; | |
536 | ent->size--; | |
746b5583 | 537 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 538 | err = destroy_mkey(dev, mr); |
203099fd | 539 | if (err) |
e126ba97 | 540 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 541 | else |
e126ba97 | 542 | kfree(mr); |
e126ba97 EC |
543 | } |
544 | } | |
545 | ||
546 | static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) | |
547 | { | |
548 | struct mlx5_mr_cache *cache = &dev->cache; | |
549 | struct mlx5_cache_ent *ent; | |
550 | int i; | |
551 | ||
552 | if (!mlx5_debugfs_root) | |
553 | return 0; | |
554 | ||
9603b61d | 555 | cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); |
e126ba97 EC |
556 | if (!cache->root) |
557 | return -ENOMEM; | |
558 | ||
559 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
560 | ent = &cache->ent[i]; | |
561 | sprintf(ent->name, "%d", ent->order); | |
562 | ent->dir = debugfs_create_dir(ent->name, cache->root); | |
563 | if (!ent->dir) | |
564 | return -ENOMEM; | |
565 | ||
566 | ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, | |
567 | &size_fops); | |
568 | if (!ent->fsize) | |
569 | return -ENOMEM; | |
570 | ||
571 | ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, | |
572 | &limit_fops); | |
573 | if (!ent->flimit) | |
574 | return -ENOMEM; | |
575 | ||
576 | ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, | |
577 | &ent->cur); | |
578 | if (!ent->fcur) | |
579 | return -ENOMEM; | |
580 | ||
581 | ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, | |
582 | &ent->miss); | |
583 | if (!ent->fmiss) | |
584 | return -ENOMEM; | |
585 | } | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) | |
591 | { | |
592 | if (!mlx5_debugfs_root) | |
593 | return; | |
594 | ||
595 | debugfs_remove_recursive(dev->cache.root); | |
596 | } | |
597 | ||
746b5583 EC |
598 | static void delay_time_func(unsigned long ctx) |
599 | { | |
600 | struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx; | |
601 | ||
602 | dev->fill_delay = 0; | |
603 | } | |
604 | ||
e126ba97 EC |
605 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) |
606 | { | |
607 | struct mlx5_mr_cache *cache = &dev->cache; | |
608 | struct mlx5_cache_ent *ent; | |
609 | int limit; | |
e126ba97 EC |
610 | int err; |
611 | int i; | |
612 | ||
3c856c82 | 613 | cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); |
e126ba97 EC |
614 | if (!cache->wq) { |
615 | mlx5_ib_warn(dev, "failed to create work queue\n"); | |
616 | return -ENOMEM; | |
617 | } | |
618 | ||
746b5583 | 619 | setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev); |
e126ba97 EC |
620 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { |
621 | INIT_LIST_HEAD(&cache->ent[i].head); | |
622 | spin_lock_init(&cache->ent[i].lock); | |
623 | ||
624 | ent = &cache->ent[i]; | |
625 | INIT_LIST_HEAD(&ent->head); | |
626 | spin_lock_init(&ent->lock); | |
627 | ent->order = i + 2; | |
628 | ent->dev = dev; | |
629 | ||
9603b61d JM |
630 | if (dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) |
631 | limit = dev->mdev->profile->mr_cache[i].limit; | |
2d036fad | 632 | else |
e126ba97 | 633 | limit = 0; |
2d036fad | 634 | |
e126ba97 EC |
635 | INIT_WORK(&ent->work, cache_work_func); |
636 | INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); | |
637 | ent->limit = limit; | |
638 | queue_work(cache->wq, &ent->work); | |
639 | } | |
640 | ||
641 | err = mlx5_mr_cache_debugfs_init(dev); | |
642 | if (err) | |
643 | mlx5_ib_warn(dev, "cache debugfs failure\n"); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) | |
649 | { | |
650 | int i; | |
651 | ||
652 | dev->cache.stopped = 1; | |
3c461911 | 653 | flush_workqueue(dev->cache.wq); |
e126ba97 EC |
654 | |
655 | mlx5_mr_cache_debugfs_cleanup(dev); | |
656 | ||
657 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) | |
658 | clean_keys(dev, i); | |
659 | ||
3c461911 | 660 | destroy_workqueue(dev->cache.wq); |
746b5583 | 661 | del_timer_sync(&dev->delay_timer); |
3c461911 | 662 | |
e126ba97 EC |
663 | return 0; |
664 | } | |
665 | ||
666 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) | |
667 | { | |
668 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 669 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
9603b61d | 670 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 | 671 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
672 | void *mkc; |
673 | u32 *in; | |
e126ba97 EC |
674 | int err; |
675 | ||
676 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
677 | if (!mr) | |
678 | return ERR_PTR(-ENOMEM); | |
679 | ||
ec22eb53 | 680 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
681 | if (!in) { |
682 | err = -ENOMEM; | |
683 | goto err_free; | |
684 | } | |
685 | ||
ec22eb53 SM |
686 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
687 | ||
688 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA); | |
689 | MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); | |
690 | MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); | |
691 | MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); | |
692 | MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); | |
693 | MLX5_SET(mkc, mkc, lr, 1); | |
e126ba97 | 694 | |
ec22eb53 SM |
695 | MLX5_SET(mkc, mkc, length64, 1); |
696 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
697 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
698 | MLX5_SET64(mkc, mkc, start_addr, 0); | |
699 | ||
700 | err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
701 | if (err) |
702 | goto err_in; | |
703 | ||
704 | kfree(in); | |
a606b0f6 MB |
705 | mr->ibmr.lkey = mr->mmkey.key; |
706 | mr->ibmr.rkey = mr->mmkey.key; | |
e126ba97 EC |
707 | mr->umem = NULL; |
708 | ||
709 | return &mr->ibmr; | |
710 | ||
711 | err_in: | |
712 | kfree(in); | |
713 | ||
714 | err_free: | |
715 | kfree(mr); | |
716 | ||
717 | return ERR_PTR(err); | |
718 | } | |
719 | ||
720 | static int get_octo_len(u64 addr, u64 len, int page_size) | |
721 | { | |
722 | u64 offset; | |
723 | int npages; | |
724 | ||
725 | offset = addr & (page_size - 1); | |
726 | npages = ALIGN(len + offset, page_size) >> ilog2(page_size); | |
727 | return (npages + 1) / 2; | |
728 | } | |
729 | ||
730 | static int use_umr(int order) | |
731 | { | |
cc149f75 | 732 | return order <= MLX5_MAX_UMR_SHIFT; |
e126ba97 EC |
733 | } |
734 | ||
395a8e4c NO |
735 | static int dma_map_mr_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, |
736 | int npages, int page_shift, int *size, | |
737 | __be64 **mr_pas, dma_addr_t *dma) | |
738 | { | |
739 | __be64 *pas; | |
740 | struct device *ddev = dev->ib_dev.dma_device; | |
741 | ||
742 | /* | |
743 | * UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes. | |
744 | * To avoid copying garbage after the pas array, we allocate | |
745 | * a little more. | |
746 | */ | |
747 | *size = ALIGN(sizeof(u64) * npages, MLX5_UMR_MTT_ALIGNMENT); | |
748 | *mr_pas = kmalloc(*size + MLX5_UMR_ALIGN - 1, GFP_KERNEL); | |
749 | if (!(*mr_pas)) | |
750 | return -ENOMEM; | |
751 | ||
752 | pas = PTR_ALIGN(*mr_pas, MLX5_UMR_ALIGN); | |
753 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, MLX5_IB_MTT_PRESENT); | |
754 | /* Clear padding after the actual pages. */ | |
755 | memset(pas + npages, 0, *size - npages * sizeof(u64)); | |
756 | ||
757 | *dma = dma_map_single(ddev, pas, *size, DMA_TO_DEVICE); | |
758 | if (dma_mapping_error(ddev, *dma)) { | |
759 | kfree(*mr_pas); | |
760 | return -ENOMEM; | |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | static void prep_umr_wqe_common(struct ib_pd *pd, struct ib_send_wr *wr, | |
767 | struct ib_sge *sg, u64 dma, int n, u32 key, | |
768 | int page_shift) | |
e126ba97 EC |
769 | { |
770 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e622f2f4 | 771 | struct mlx5_umr_wr *umrwr = umr_wr(wr); |
e126ba97 EC |
772 | |
773 | sg->addr = dma; | |
774 | sg->length = ALIGN(sizeof(u64) * n, 64); | |
b37c788f | 775 | sg->lkey = dev->umrc.pd->local_dma_lkey; |
e126ba97 EC |
776 | |
777 | wr->next = NULL; | |
e126ba97 EC |
778 | wr->sg_list = sg; |
779 | if (n) | |
780 | wr->num_sge = 1; | |
781 | else | |
782 | wr->num_sge = 0; | |
783 | ||
784 | wr->opcode = MLX5_IB_WR_UMR; | |
968e78dd HE |
785 | |
786 | umrwr->npages = n; | |
787 | umrwr->page_shift = page_shift; | |
788 | umrwr->mkey = key; | |
395a8e4c NO |
789 | } |
790 | ||
791 | static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr, | |
792 | struct ib_sge *sg, u64 dma, int n, u32 key, | |
793 | int page_shift, u64 virt_addr, u64 len, | |
794 | int access_flags) | |
795 | { | |
796 | struct mlx5_umr_wr *umrwr = umr_wr(wr); | |
797 | ||
798 | prep_umr_wqe_common(pd, wr, sg, dma, n, key, page_shift); | |
799 | ||
800 | wr->send_flags = 0; | |
801 | ||
968e78dd HE |
802 | umrwr->target.virt_addr = virt_addr; |
803 | umrwr->length = len; | |
804 | umrwr->access_flags = access_flags; | |
805 | umrwr->pd = pd; | |
e126ba97 EC |
806 | } |
807 | ||
808 | static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev, | |
809 | struct ib_send_wr *wr, u32 key) | |
810 | { | |
e622f2f4 | 811 | struct mlx5_umr_wr *umrwr = umr_wr(wr); |
968e78dd HE |
812 | |
813 | wr->send_flags = MLX5_IB_SEND_UMR_UNREG | MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
e126ba97 | 814 | wr->opcode = MLX5_IB_WR_UMR; |
968e78dd | 815 | umrwr->mkey = key; |
e126ba97 EC |
816 | } |
817 | ||
395a8e4c NO |
818 | static struct ib_umem *mr_umem_get(struct ib_pd *pd, u64 start, u64 length, |
819 | int access_flags, int *npages, | |
820 | int *page_shift, int *ncont, int *order) | |
821 | { | |
822 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
823 | struct ib_umem *umem = ib_umem_get(pd->uobject->context, start, length, | |
824 | access_flags, 0); | |
825 | if (IS_ERR(umem)) { | |
826 | mlx5_ib_err(dev, "umem get failed (%ld)\n", PTR_ERR(umem)); | |
827 | return (void *)umem; | |
828 | } | |
829 | ||
830 | mlx5_ib_cont_pages(umem, start, npages, page_shift, ncont, order); | |
831 | if (!*npages) { | |
832 | mlx5_ib_warn(dev, "avoid zero region\n"); | |
833 | ib_umem_release(umem); | |
834 | return ERR_PTR(-EINVAL); | |
835 | } | |
836 | ||
837 | mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", | |
838 | *npages, *ncont, *order, *page_shift); | |
839 | ||
840 | return umem; | |
841 | } | |
842 | ||
add08d76 | 843 | static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) |
e126ba97 | 844 | { |
add08d76 CH |
845 | struct mlx5_ib_umr_context *context = |
846 | container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); | |
e126ba97 | 847 | |
add08d76 CH |
848 | context->status = wc->status; |
849 | complete(&context->done); | |
850 | } | |
e126ba97 | 851 | |
add08d76 CH |
852 | static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) |
853 | { | |
854 | context->cqe.done = mlx5_ib_umr_done; | |
855 | context->status = -1; | |
856 | init_completion(&context->done); | |
e126ba97 EC |
857 | } |
858 | ||
859 | static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem, | |
860 | u64 virt_addr, u64 len, int npages, | |
861 | int page_shift, int order, int access_flags) | |
862 | { | |
863 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
203099fd | 864 | struct device *ddev = dev->ib_dev.dma_device; |
e126ba97 | 865 | struct umr_common *umrc = &dev->umrc; |
a74d2416 | 866 | struct mlx5_ib_umr_context umr_context; |
0025b0bd | 867 | struct mlx5_umr_wr umrwr = {}; |
e622f2f4 | 868 | struct ib_send_wr *bad; |
e126ba97 EC |
869 | struct mlx5_ib_mr *mr; |
870 | struct ib_sge sg; | |
cc149f75 | 871 | int size; |
21af2c3e HE |
872 | __be64 *mr_pas; |
873 | dma_addr_t dma; | |
096f7e72 | 874 | int err = 0; |
e126ba97 EC |
875 | int i; |
876 | ||
746b5583 | 877 | for (i = 0; i < 1; i++) { |
e126ba97 EC |
878 | mr = alloc_cached_mr(dev, order); |
879 | if (mr) | |
880 | break; | |
881 | ||
882 | err = add_keys(dev, order2idx(dev, order), 1); | |
746b5583 EC |
883 | if (err && err != -EAGAIN) { |
884 | mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); | |
e126ba97 EC |
885 | break; |
886 | } | |
887 | } | |
888 | ||
889 | if (!mr) | |
890 | return ERR_PTR(-EAGAIN); | |
891 | ||
395a8e4c NO |
892 | err = dma_map_mr_pas(dev, umem, npages, page_shift, &size, &mr_pas, |
893 | &dma); | |
894 | if (err) | |
096f7e72 | 895 | goto free_mr; |
203099fd | 896 | |
add08d76 CH |
897 | mlx5_ib_init_umr_context(&umr_context); |
898 | ||
add08d76 | 899 | umrwr.wr.wr_cqe = &umr_context.cqe; |
a606b0f6 | 900 | prep_umr_reg_wqe(pd, &umrwr.wr, &sg, dma, npages, mr->mmkey.key, |
e622f2f4 | 901 | page_shift, virt_addr, len, access_flags); |
e126ba97 | 902 | |
e126ba97 | 903 | down(&umrc->sem); |
e622f2f4 | 904 | err = ib_post_send(umrc->qp, &umrwr.wr, &bad); |
e126ba97 EC |
905 | if (err) { |
906 | mlx5_ib_warn(dev, "post send failed, err %d\n", err); | |
096f7e72 | 907 | goto unmap_dma; |
a74d2416 SR |
908 | } else { |
909 | wait_for_completion(&umr_context.done); | |
910 | if (umr_context.status != IB_WC_SUCCESS) { | |
911 | mlx5_ib_warn(dev, "reg umr failed\n"); | |
912 | err = -EFAULT; | |
913 | } | |
096f7e72 | 914 | } |
e126ba97 | 915 | |
a606b0f6 MB |
916 | mr->mmkey.iova = virt_addr; |
917 | mr->mmkey.size = len; | |
918 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
b475598a | 919 | |
b4cfe447 HE |
920 | mr->live = 1; |
921 | ||
096f7e72 HE |
922 | unmap_dma: |
923 | up(&umrc->sem); | |
21af2c3e | 924 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); |
096f7e72 | 925 | |
21af2c3e | 926 | kfree(mr_pas); |
203099fd | 927 | |
096f7e72 HE |
928 | free_mr: |
929 | if (err) { | |
930 | free_cached_mr(dev, mr); | |
931 | return ERR_PTR(err); | |
e126ba97 EC |
932 | } |
933 | ||
934 | return mr; | |
e126ba97 EC |
935 | } |
936 | ||
832a6b06 HE |
937 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
938 | int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, int npages, | |
939 | int zap) | |
940 | { | |
941 | struct mlx5_ib_dev *dev = mr->dev; | |
942 | struct device *ddev = dev->ib_dev.dma_device; | |
943 | struct umr_common *umrc = &dev->umrc; | |
944 | struct mlx5_ib_umr_context umr_context; | |
945 | struct ib_umem *umem = mr->umem; | |
946 | int size; | |
947 | __be64 *pas; | |
948 | dma_addr_t dma; | |
e622f2f4 CH |
949 | struct ib_send_wr *bad; |
950 | struct mlx5_umr_wr wr; | |
832a6b06 HE |
951 | struct ib_sge sg; |
952 | int err = 0; | |
953 | const int page_index_alignment = MLX5_UMR_MTT_ALIGNMENT / sizeof(u64); | |
954 | const int page_index_mask = page_index_alignment - 1; | |
955 | size_t pages_mapped = 0; | |
956 | size_t pages_to_map = 0; | |
957 | size_t pages_iter = 0; | |
958 | int use_emergency_buf = 0; | |
959 | ||
960 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, | |
961 | * so we need to align the offset and length accordingly */ | |
962 | if (start_page_index & page_index_mask) { | |
963 | npages += start_page_index & page_index_mask; | |
964 | start_page_index &= ~page_index_mask; | |
965 | } | |
966 | ||
967 | pages_to_map = ALIGN(npages, page_index_alignment); | |
968 | ||
969 | if (start_page_index + pages_to_map > MLX5_MAX_UMR_PAGES) | |
970 | return -EINVAL; | |
971 | ||
972 | size = sizeof(u64) * pages_to_map; | |
973 | size = min_t(int, PAGE_SIZE, size); | |
974 | /* We allocate with GFP_ATOMIC to avoid recursion into page-reclaim | |
975 | * code, when we are called from an invalidation. The pas buffer must | |
976 | * be 2k-aligned for Connect-IB. */ | |
977 | pas = (__be64 *)get_zeroed_page(GFP_ATOMIC); | |
978 | if (!pas) { | |
979 | mlx5_ib_warn(dev, "unable to allocate memory during MTT update, falling back to slower chunked mechanism.\n"); | |
980 | pas = mlx5_ib_update_mtt_emergency_buffer; | |
981 | size = MLX5_UMR_MTT_MIN_CHUNK_SIZE; | |
982 | use_emergency_buf = 1; | |
983 | mutex_lock(&mlx5_ib_update_mtt_emergency_buffer_mutex); | |
984 | memset(pas, 0, size); | |
985 | } | |
986 | pages_iter = size / sizeof(u64); | |
987 | dma = dma_map_single(ddev, pas, size, DMA_TO_DEVICE); | |
988 | if (dma_mapping_error(ddev, dma)) { | |
989 | mlx5_ib_err(dev, "unable to map DMA during MTT update.\n"); | |
990 | err = -ENOMEM; | |
991 | goto free_pas; | |
992 | } | |
993 | ||
994 | for (pages_mapped = 0; | |
995 | pages_mapped < pages_to_map && !err; | |
996 | pages_mapped += pages_iter, start_page_index += pages_iter) { | |
997 | dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); | |
998 | ||
999 | npages = min_t(size_t, | |
1000 | pages_iter, | |
1001 | ib_umem_num_pages(umem) - start_page_index); | |
1002 | ||
1003 | if (!zap) { | |
1004 | __mlx5_ib_populate_pas(dev, umem, PAGE_SHIFT, | |
1005 | start_page_index, npages, pas, | |
1006 | MLX5_IB_MTT_PRESENT); | |
1007 | /* Clear padding after the pages brought from the | |
1008 | * umem. */ | |
1009 | memset(pas + npages, 0, size - npages * sizeof(u64)); | |
1010 | } | |
1011 | ||
1012 | dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); | |
1013 | ||
add08d76 CH |
1014 | mlx5_ib_init_umr_context(&umr_context); |
1015 | ||
832a6b06 | 1016 | memset(&wr, 0, sizeof(wr)); |
add08d76 | 1017 | wr.wr.wr_cqe = &umr_context.cqe; |
832a6b06 HE |
1018 | |
1019 | sg.addr = dma; | |
1020 | sg.length = ALIGN(npages * sizeof(u64), | |
1021 | MLX5_UMR_MTT_ALIGNMENT); | |
b37c788f | 1022 | sg.lkey = dev->umrc.pd->local_dma_lkey; |
832a6b06 | 1023 | |
e622f2f4 | 1024 | wr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE | |
832a6b06 | 1025 | MLX5_IB_SEND_UMR_UPDATE_MTT; |
e622f2f4 CH |
1026 | wr.wr.sg_list = &sg; |
1027 | wr.wr.num_sge = 1; | |
1028 | wr.wr.opcode = MLX5_IB_WR_UMR; | |
1029 | wr.npages = sg.length / sizeof(u64); | |
1030 | wr.page_shift = PAGE_SHIFT; | |
a606b0f6 | 1031 | wr.mkey = mr->mmkey.key; |
e622f2f4 | 1032 | wr.target.offset = start_page_index; |
832a6b06 | 1033 | |
832a6b06 | 1034 | down(&umrc->sem); |
e622f2f4 | 1035 | err = ib_post_send(umrc->qp, &wr.wr, &bad); |
832a6b06 HE |
1036 | if (err) { |
1037 | mlx5_ib_err(dev, "UMR post send failed, err %d\n", err); | |
1038 | } else { | |
1039 | wait_for_completion(&umr_context.done); | |
1040 | if (umr_context.status != IB_WC_SUCCESS) { | |
1041 | mlx5_ib_err(dev, "UMR completion failed, code %d\n", | |
1042 | umr_context.status); | |
1043 | err = -EFAULT; | |
1044 | } | |
1045 | } | |
1046 | up(&umrc->sem); | |
1047 | } | |
1048 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
1049 | ||
1050 | free_pas: | |
1051 | if (!use_emergency_buf) | |
1052 | free_page((unsigned long)pas); | |
1053 | else | |
1054 | mutex_unlock(&mlx5_ib_update_mtt_emergency_buffer_mutex); | |
1055 | ||
1056 | return err; | |
1057 | } | |
1058 | #endif | |
1059 | ||
395a8e4c NO |
1060 | /* |
1061 | * If ibmr is NULL it will be allocated by reg_create. | |
1062 | * Else, the given ibmr will be used. | |
1063 | */ | |
1064 | static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, | |
1065 | u64 virt_addr, u64 length, | |
1066 | struct ib_umem *umem, int npages, | |
1067 | int page_shift, int access_flags) | |
e126ba97 EC |
1068 | { |
1069 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 1070 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
1071 | __be64 *pas; |
1072 | void *mkc; | |
e126ba97 | 1073 | int inlen; |
ec22eb53 | 1074 | u32 *in; |
e126ba97 | 1075 | int err; |
938fe83c | 1076 | bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); |
e126ba97 | 1077 | |
395a8e4c | 1078 | mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); |
e126ba97 EC |
1079 | if (!mr) |
1080 | return ERR_PTR(-ENOMEM); | |
1081 | ||
ec22eb53 SM |
1082 | inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + |
1083 | sizeof(*pas) * ((npages + 1) / 2) * 2; | |
e126ba97 EC |
1084 | in = mlx5_vzalloc(inlen); |
1085 | if (!in) { | |
1086 | err = -ENOMEM; | |
1087 | goto err_1; | |
1088 | } | |
ec22eb53 SM |
1089 | pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
1090 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, | |
cc149f75 | 1091 | pg_cap ? MLX5_IB_MTT_PRESENT : 0); |
e126ba97 | 1092 | |
ec22eb53 | 1093 | /* The pg_access bit allows setting the access flags |
cc149f75 | 1094 | * in the page list submitted with the command. */ |
ec22eb53 SM |
1095 | MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); |
1096 | ||
1097 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
1098 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); | |
1099 | MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
1100 | MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); | |
1101 | MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); | |
1102 | MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); | |
1103 | MLX5_SET(mkc, mkc, lr, 1); | |
1104 | ||
1105 | MLX5_SET64(mkc, mkc, start_addr, virt_addr); | |
1106 | MLX5_SET64(mkc, mkc, len, length); | |
1107 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1108 | MLX5_SET(mkc, mkc, bsf_octword_size, 0); | |
1109 | MLX5_SET(mkc, mkc, translations_octword_size, | |
1110 | get_octo_len(virt_addr, length, 1 << page_shift)); | |
1111 | MLX5_SET(mkc, mkc, log_page_size, page_shift); | |
1112 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1113 | MLX5_SET(create_mkey_in, in, translations_octword_actual_size, | |
1114 | get_octo_len(virt_addr, length, 1 << page_shift)); | |
1115 | ||
1116 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
1117 | if (err) { |
1118 | mlx5_ib_warn(dev, "create mkey failed\n"); | |
1119 | goto err_2; | |
1120 | } | |
1121 | mr->umem = umem; | |
7eae20db | 1122 | mr->dev = dev; |
b4cfe447 | 1123 | mr->live = 1; |
479163f4 | 1124 | kvfree(in); |
e126ba97 | 1125 | |
a606b0f6 | 1126 | mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1127 | |
1128 | return mr; | |
1129 | ||
1130 | err_2: | |
479163f4 | 1131 | kvfree(in); |
e126ba97 EC |
1132 | |
1133 | err_1: | |
395a8e4c NO |
1134 | if (!ibmr) |
1135 | kfree(mr); | |
e126ba97 EC |
1136 | |
1137 | return ERR_PTR(err); | |
1138 | } | |
1139 | ||
395a8e4c NO |
1140 | static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, |
1141 | int npages, u64 length, int access_flags) | |
1142 | { | |
1143 | mr->npages = npages; | |
1144 | atomic_add(npages, &dev->mdev->priv.reg_pages); | |
a606b0f6 MB |
1145 | mr->ibmr.lkey = mr->mmkey.key; |
1146 | mr->ibmr.rkey = mr->mmkey.key; | |
395a8e4c | 1147 | mr->ibmr.length = length; |
56e11d62 | 1148 | mr->access_flags = access_flags; |
395a8e4c NO |
1149 | } |
1150 | ||
e126ba97 EC |
1151 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, |
1152 | u64 virt_addr, int access_flags, | |
1153 | struct ib_udata *udata) | |
1154 | { | |
1155 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1156 | struct mlx5_ib_mr *mr = NULL; | |
1157 | struct ib_umem *umem; | |
1158 | int page_shift; | |
1159 | int npages; | |
1160 | int ncont; | |
1161 | int order; | |
1162 | int err; | |
1163 | ||
900a6d79 EC |
1164 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", |
1165 | start, virt_addr, length, access_flags); | |
395a8e4c NO |
1166 | umem = mr_umem_get(pd, start, length, access_flags, &npages, |
1167 | &page_shift, &ncont, &order); | |
e126ba97 | 1168 | |
395a8e4c NO |
1169 | if (IS_ERR(umem)) |
1170 | return (void *)umem; | |
e126ba97 EC |
1171 | |
1172 | if (use_umr(order)) { | |
1173 | mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift, | |
1174 | order, access_flags); | |
1175 | if (PTR_ERR(mr) == -EAGAIN) { | |
1176 | mlx5_ib_dbg(dev, "cache empty for order %d", order); | |
1177 | mr = NULL; | |
1178 | } | |
6aec21f6 HE |
1179 | } else if (access_flags & IB_ACCESS_ON_DEMAND) { |
1180 | err = -EINVAL; | |
1181 | pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB"); | |
1182 | goto error; | |
e126ba97 EC |
1183 | } |
1184 | ||
1185 | if (!mr) | |
395a8e4c NO |
1186 | mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, |
1187 | page_shift, access_flags); | |
e126ba97 EC |
1188 | |
1189 | if (IS_ERR(mr)) { | |
1190 | err = PTR_ERR(mr); | |
1191 | goto error; | |
1192 | } | |
1193 | ||
a606b0f6 | 1194 | mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1195 | |
1196 | mr->umem = umem; | |
395a8e4c | 1197 | set_mr_fileds(dev, mr, npages, length, access_flags); |
e126ba97 | 1198 | |
b4cfe447 | 1199 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
395a8e4c | 1200 | update_odp_mr(mr); |
b4cfe447 HE |
1201 | #endif |
1202 | ||
e126ba97 EC |
1203 | return &mr->ibmr; |
1204 | ||
1205 | error: | |
1206 | ib_umem_release(umem); | |
1207 | return ERR_PTR(err); | |
1208 | } | |
1209 | ||
1210 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
1211 | { | |
89ea94a7 | 1212 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 | 1213 | struct umr_common *umrc = &dev->umrc; |
a74d2416 | 1214 | struct mlx5_ib_umr_context umr_context; |
0025b0bd | 1215 | struct mlx5_umr_wr umrwr = {}; |
e622f2f4 | 1216 | struct ib_send_wr *bad; |
e126ba97 EC |
1217 | int err; |
1218 | ||
89ea94a7 MG |
1219 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) |
1220 | return 0; | |
1221 | ||
add08d76 CH |
1222 | mlx5_ib_init_umr_context(&umr_context); |
1223 | ||
add08d76 | 1224 | umrwr.wr.wr_cqe = &umr_context.cqe; |
a606b0f6 | 1225 | prep_umr_unreg_wqe(dev, &umrwr.wr, mr->mmkey.key); |
e126ba97 EC |
1226 | |
1227 | down(&umrc->sem); | |
e622f2f4 | 1228 | err = ib_post_send(umrc->qp, &umrwr.wr, &bad); |
e126ba97 EC |
1229 | if (err) { |
1230 | up(&umrc->sem); | |
1231 | mlx5_ib_dbg(dev, "err %d\n", err); | |
1232 | goto error; | |
a74d2416 SR |
1233 | } else { |
1234 | wait_for_completion(&umr_context.done); | |
1235 | up(&umrc->sem); | |
e126ba97 | 1236 | } |
a74d2416 | 1237 | if (umr_context.status != IB_WC_SUCCESS) { |
e126ba97 EC |
1238 | mlx5_ib_warn(dev, "unreg umr failed\n"); |
1239 | err = -EFAULT; | |
1240 | goto error; | |
1241 | } | |
1242 | return 0; | |
1243 | ||
1244 | error: | |
1245 | return err; | |
1246 | } | |
1247 | ||
56e11d62 NO |
1248 | static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, u64 virt_addr, |
1249 | u64 length, int npages, int page_shift, int order, | |
1250 | int access_flags, int flags) | |
1251 | { | |
1252 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1253 | struct device *ddev = dev->ib_dev.dma_device; | |
1254 | struct mlx5_ib_umr_context umr_context; | |
1255 | struct ib_send_wr *bad; | |
1256 | struct mlx5_umr_wr umrwr = {}; | |
1257 | struct ib_sge sg; | |
1258 | struct umr_common *umrc = &dev->umrc; | |
1259 | dma_addr_t dma = 0; | |
1260 | __be64 *mr_pas = NULL; | |
1261 | int size; | |
1262 | int err; | |
1263 | ||
add08d76 CH |
1264 | mlx5_ib_init_umr_context(&umr_context); |
1265 | ||
1266 | umrwr.wr.wr_cqe = &umr_context.cqe; | |
56e11d62 NO |
1267 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; |
1268 | ||
1269 | if (flags & IB_MR_REREG_TRANS) { | |
1270 | err = dma_map_mr_pas(dev, mr->umem, npages, page_shift, &size, | |
1271 | &mr_pas, &dma); | |
1272 | if (err) | |
1273 | return err; | |
1274 | ||
1275 | umrwr.target.virt_addr = virt_addr; | |
1276 | umrwr.length = length; | |
1277 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1278 | } | |
1279 | ||
a606b0f6 | 1280 | prep_umr_wqe_common(pd, &umrwr.wr, &sg, dma, npages, mr->mmkey.key, |
56e11d62 NO |
1281 | page_shift); |
1282 | ||
1283 | if (flags & IB_MR_REREG_PD) { | |
1284 | umrwr.pd = pd; | |
1285 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD; | |
1286 | } | |
1287 | ||
1288 | if (flags & IB_MR_REREG_ACCESS) { | |
1289 | umrwr.access_flags = access_flags; | |
1290 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_ACCESS; | |
1291 | } | |
1292 | ||
56e11d62 NO |
1293 | /* post send request to UMR QP */ |
1294 | down(&umrc->sem); | |
1295 | err = ib_post_send(umrc->qp, &umrwr.wr, &bad); | |
1296 | ||
1297 | if (err) { | |
1298 | mlx5_ib_warn(dev, "post send failed, err %d\n", err); | |
1299 | } else { | |
1300 | wait_for_completion(&umr_context.done); | |
1301 | if (umr_context.status != IB_WC_SUCCESS) { | |
1302 | mlx5_ib_warn(dev, "reg umr failed (%u)\n", | |
1303 | umr_context.status); | |
1304 | err = -EFAULT; | |
1305 | } | |
1306 | } | |
1307 | ||
1308 | up(&umrc->sem); | |
1309 | if (flags & IB_MR_REREG_TRANS) { | |
1310 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
1311 | kfree(mr_pas); | |
1312 | } | |
1313 | return err; | |
1314 | } | |
1315 | ||
1316 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, | |
1317 | u64 length, u64 virt_addr, int new_access_flags, | |
1318 | struct ib_pd *new_pd, struct ib_udata *udata) | |
1319 | { | |
1320 | struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); | |
1321 | struct mlx5_ib_mr *mr = to_mmr(ib_mr); | |
1322 | struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; | |
1323 | int access_flags = flags & IB_MR_REREG_ACCESS ? | |
1324 | new_access_flags : | |
1325 | mr->access_flags; | |
1326 | u64 addr = (flags & IB_MR_REREG_TRANS) ? virt_addr : mr->umem->address; | |
1327 | u64 len = (flags & IB_MR_REREG_TRANS) ? length : mr->umem->length; | |
1328 | int page_shift = 0; | |
1329 | int npages = 0; | |
1330 | int ncont = 0; | |
1331 | int order = 0; | |
1332 | int err; | |
1333 | ||
1334 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", | |
1335 | start, virt_addr, length, access_flags); | |
1336 | ||
1337 | if (flags != IB_MR_REREG_PD) { | |
1338 | /* | |
1339 | * Replace umem. This needs to be done whether or not UMR is | |
1340 | * used. | |
1341 | */ | |
1342 | flags |= IB_MR_REREG_TRANS; | |
1343 | ib_umem_release(mr->umem); | |
1344 | mr->umem = mr_umem_get(pd, addr, len, access_flags, &npages, | |
1345 | &page_shift, &ncont, &order); | |
1346 | if (IS_ERR(mr->umem)) { | |
1347 | err = PTR_ERR(mr->umem); | |
1348 | mr->umem = NULL; | |
1349 | return err; | |
1350 | } | |
1351 | } | |
1352 | ||
1353 | if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) { | |
1354 | /* | |
1355 | * UMR can't be used - MKey needs to be replaced. | |
1356 | */ | |
1357 | if (mr->umred) { | |
1358 | err = unreg_umr(dev, mr); | |
1359 | if (err) | |
1360 | mlx5_ib_warn(dev, "Failed to unregister MR\n"); | |
1361 | } else { | |
1362 | err = destroy_mkey(dev, mr); | |
1363 | if (err) | |
1364 | mlx5_ib_warn(dev, "Failed to destroy MKey\n"); | |
1365 | } | |
1366 | if (err) | |
1367 | return err; | |
1368 | ||
1369 | mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, | |
1370 | page_shift, access_flags); | |
1371 | ||
1372 | if (IS_ERR(mr)) | |
1373 | return PTR_ERR(mr); | |
1374 | ||
1375 | mr->umred = 0; | |
1376 | } else { | |
1377 | /* | |
1378 | * Send a UMR WQE | |
1379 | */ | |
1380 | err = rereg_umr(pd, mr, addr, len, npages, page_shift, | |
1381 | order, access_flags, flags); | |
1382 | if (err) { | |
1383 | mlx5_ib_warn(dev, "Failed to rereg UMR\n"); | |
1384 | return err; | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | if (flags & IB_MR_REREG_PD) { | |
1389 | ib_mr->pd = pd; | |
a606b0f6 | 1390 | mr->mmkey.pd = to_mpd(pd)->pdn; |
56e11d62 NO |
1391 | } |
1392 | ||
1393 | if (flags & IB_MR_REREG_ACCESS) | |
1394 | mr->access_flags = access_flags; | |
1395 | ||
1396 | if (flags & IB_MR_REREG_TRANS) { | |
1397 | atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); | |
1398 | set_mr_fileds(dev, mr, npages, len, access_flags); | |
a606b0f6 MB |
1399 | mr->mmkey.iova = addr; |
1400 | mr->mmkey.size = len; | |
56e11d62 NO |
1401 | } |
1402 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1403 | update_odp_mr(mr); | |
1404 | #endif | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
8a187ee5 SG |
1409 | static int |
1410 | mlx5_alloc_priv_descs(struct ib_device *device, | |
1411 | struct mlx5_ib_mr *mr, | |
1412 | int ndescs, | |
1413 | int desc_size) | |
1414 | { | |
1415 | int size = ndescs * desc_size; | |
1416 | int add_size; | |
1417 | int ret; | |
1418 | ||
1419 | add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); | |
1420 | ||
1421 | mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); | |
1422 | if (!mr->descs_alloc) | |
1423 | return -ENOMEM; | |
1424 | ||
1425 | mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); | |
1426 | ||
1427 | mr->desc_map = dma_map_single(device->dma_device, mr->descs, | |
1428 | size, DMA_TO_DEVICE); | |
1429 | if (dma_mapping_error(device->dma_device, mr->desc_map)) { | |
1430 | ret = -ENOMEM; | |
1431 | goto err; | |
1432 | } | |
1433 | ||
1434 | return 0; | |
1435 | err: | |
1436 | kfree(mr->descs_alloc); | |
1437 | ||
1438 | return ret; | |
1439 | } | |
1440 | ||
1441 | static void | |
1442 | mlx5_free_priv_descs(struct mlx5_ib_mr *mr) | |
1443 | { | |
1444 | if (mr->descs) { | |
1445 | struct ib_device *device = mr->ibmr.device; | |
1446 | int size = mr->max_descs * mr->desc_size; | |
1447 | ||
1448 | dma_unmap_single(device->dma_device, mr->desc_map, | |
1449 | size, DMA_TO_DEVICE); | |
1450 | kfree(mr->descs_alloc); | |
1451 | mr->descs = NULL; | |
1452 | } | |
1453 | } | |
1454 | ||
6aec21f6 | 1455 | static int clean_mr(struct mlx5_ib_mr *mr) |
e126ba97 | 1456 | { |
6aec21f6 | 1457 | struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); |
e126ba97 EC |
1458 | int umred = mr->umred; |
1459 | int err; | |
1460 | ||
8b91ffc1 SG |
1461 | if (mr->sig) { |
1462 | if (mlx5_core_destroy_psv(dev->mdev, | |
1463 | mr->sig->psv_memory.psv_idx)) | |
1464 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1465 | mr->sig->psv_memory.psv_idx); | |
1466 | if (mlx5_core_destroy_psv(dev->mdev, | |
1467 | mr->sig->psv_wire.psv_idx)) | |
1468 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1469 | mr->sig->psv_wire.psv_idx); | |
1470 | kfree(mr->sig); | |
1471 | mr->sig = NULL; | |
1472 | } | |
1473 | ||
8a187ee5 SG |
1474 | mlx5_free_priv_descs(mr); |
1475 | ||
e126ba97 | 1476 | if (!umred) { |
b4cfe447 | 1477 | err = destroy_mkey(dev, mr); |
e126ba97 EC |
1478 | if (err) { |
1479 | mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n", | |
a606b0f6 | 1480 | mr->mmkey.key, err); |
e126ba97 EC |
1481 | return err; |
1482 | } | |
1483 | } else { | |
1484 | err = unreg_umr(dev, mr); | |
1485 | if (err) { | |
1486 | mlx5_ib_warn(dev, "failed unregister\n"); | |
1487 | return err; | |
1488 | } | |
1489 | free_cached_mr(dev, mr); | |
1490 | } | |
1491 | ||
6aec21f6 HE |
1492 | if (!umred) |
1493 | kfree(mr); | |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr) | |
1499 | { | |
1500 | struct mlx5_ib_dev *dev = to_mdev(ibmr->device); | |
1501 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1502 | int npages = mr->npages; | |
1503 | struct ib_umem *umem = mr->umem; | |
1504 | ||
1505 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
b4cfe447 HE |
1506 | if (umem && umem->odp_data) { |
1507 | /* Prevent new page faults from succeeding */ | |
1508 | mr->live = 0; | |
6aec21f6 HE |
1509 | /* Wait for all running page-fault handlers to finish. */ |
1510 | synchronize_srcu(&dev->mr_srcu); | |
b4cfe447 HE |
1511 | /* Destroy all page mappings */ |
1512 | mlx5_ib_invalidate_range(umem, ib_umem_start(umem), | |
1513 | ib_umem_end(umem)); | |
1514 | /* | |
1515 | * We kill the umem before the MR for ODP, | |
1516 | * so that there will not be any invalidations in | |
1517 | * flight, looking at the *mr struct. | |
1518 | */ | |
1519 | ib_umem_release(umem); | |
1520 | atomic_sub(npages, &dev->mdev->priv.reg_pages); | |
1521 | ||
1522 | /* Avoid double-freeing the umem. */ | |
1523 | umem = NULL; | |
1524 | } | |
6aec21f6 HE |
1525 | #endif |
1526 | ||
1527 | clean_mr(mr); | |
1528 | ||
e126ba97 EC |
1529 | if (umem) { |
1530 | ib_umem_release(umem); | |
6aec21f6 | 1531 | atomic_sub(npages, &dev->mdev->priv.reg_pages); |
e126ba97 EC |
1532 | } |
1533 | ||
e126ba97 EC |
1534 | return 0; |
1535 | } | |
1536 | ||
9bee178b SG |
1537 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
1538 | enum ib_mr_type mr_type, | |
1539 | u32 max_num_sg) | |
3121e3c4 SG |
1540 | { |
1541 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1542 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
b005d316 | 1543 | int ndescs = ALIGN(max_num_sg, 4); |
ec22eb53 SM |
1544 | struct mlx5_ib_mr *mr; |
1545 | void *mkc; | |
1546 | u32 *in; | |
b005d316 | 1547 | int err; |
3121e3c4 SG |
1548 | |
1549 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1550 | if (!mr) | |
1551 | return ERR_PTR(-ENOMEM); | |
1552 | ||
ec22eb53 | 1553 | in = kzalloc(inlen, GFP_KERNEL); |
3121e3c4 SG |
1554 | if (!in) { |
1555 | err = -ENOMEM; | |
1556 | goto err_free; | |
1557 | } | |
1558 | ||
ec22eb53 SM |
1559 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1560 | MLX5_SET(mkc, mkc, free, 1); | |
1561 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1562 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1563 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
3121e3c4 | 1564 | |
9bee178b | 1565 | if (mr_type == IB_MR_TYPE_MEM_REG) { |
ec22eb53 SM |
1566 | mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT; |
1567 | MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); | |
8a187ee5 SG |
1568 | err = mlx5_alloc_priv_descs(pd->device, mr, |
1569 | ndescs, sizeof(u64)); | |
1570 | if (err) | |
1571 | goto err_free_in; | |
1572 | ||
1573 | mr->desc_size = sizeof(u64); | |
1574 | mr->max_descs = ndescs; | |
b005d316 | 1575 | } else if (mr_type == IB_MR_TYPE_SG_GAPS) { |
ec22eb53 | 1576 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
b005d316 SG |
1577 | |
1578 | err = mlx5_alloc_priv_descs(pd->device, mr, | |
1579 | ndescs, sizeof(struct mlx5_klm)); | |
1580 | if (err) | |
1581 | goto err_free_in; | |
1582 | mr->desc_size = sizeof(struct mlx5_klm); | |
1583 | mr->max_descs = ndescs; | |
9bee178b | 1584 | } else if (mr_type == IB_MR_TYPE_SIGNATURE) { |
3121e3c4 SG |
1585 | u32 psv_index[2]; |
1586 | ||
ec22eb53 SM |
1587 | MLX5_SET(mkc, mkc, bsf_en, 1); |
1588 | MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); | |
3121e3c4 SG |
1589 | mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); |
1590 | if (!mr->sig) { | |
1591 | err = -ENOMEM; | |
1592 | goto err_free_in; | |
1593 | } | |
1594 | ||
1595 | /* create mem & wire PSVs */ | |
9603b61d | 1596 | err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, |
3121e3c4 SG |
1597 | 2, psv_index); |
1598 | if (err) | |
1599 | goto err_free_sig; | |
1600 | ||
ec22eb53 | 1601 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
3121e3c4 SG |
1602 | mr->sig->psv_memory.psv_idx = psv_index[0]; |
1603 | mr->sig->psv_wire.psv_idx = psv_index[1]; | |
d5436ba0 SG |
1604 | |
1605 | mr->sig->sig_status_checked = true; | |
1606 | mr->sig->sig_err_exists = false; | |
1607 | /* Next UMR, Arm SIGERR */ | |
1608 | ++mr->sig->sigerr_count; | |
9bee178b SG |
1609 | } else { |
1610 | mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); | |
1611 | err = -EINVAL; | |
1612 | goto err_free_in; | |
3121e3c4 SG |
1613 | } |
1614 | ||
ec22eb53 SM |
1615 | MLX5_SET(mkc, mkc, access_mode, mr->access_mode); |
1616 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1617 | ||
1618 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
3121e3c4 SG |
1619 | if (err) |
1620 | goto err_destroy_psv; | |
1621 | ||
a606b0f6 MB |
1622 | mr->ibmr.lkey = mr->mmkey.key; |
1623 | mr->ibmr.rkey = mr->mmkey.key; | |
3121e3c4 SG |
1624 | mr->umem = NULL; |
1625 | kfree(in); | |
1626 | ||
1627 | return &mr->ibmr; | |
1628 | ||
1629 | err_destroy_psv: | |
1630 | if (mr->sig) { | |
9603b61d | 1631 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1632 | mr->sig->psv_memory.psv_idx)) |
1633 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1634 | mr->sig->psv_memory.psv_idx); | |
9603b61d | 1635 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1636 | mr->sig->psv_wire.psv_idx)) |
1637 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1638 | mr->sig->psv_wire.psv_idx); | |
1639 | } | |
8a187ee5 | 1640 | mlx5_free_priv_descs(mr); |
3121e3c4 SG |
1641 | err_free_sig: |
1642 | kfree(mr->sig); | |
1643 | err_free_in: | |
1644 | kfree(in); | |
1645 | err_free: | |
1646 | kfree(mr); | |
1647 | return ERR_PTR(err); | |
1648 | } | |
1649 | ||
d2370e0a MB |
1650 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
1651 | struct ib_udata *udata) | |
1652 | { | |
1653 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1654 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
d2370e0a | 1655 | struct mlx5_ib_mw *mw = NULL; |
ec22eb53 SM |
1656 | u32 *in = NULL; |
1657 | void *mkc; | |
d2370e0a MB |
1658 | int ndescs; |
1659 | int err; | |
1660 | struct mlx5_ib_alloc_mw req = {}; | |
1661 | struct { | |
1662 | __u32 comp_mask; | |
1663 | __u32 response_length; | |
1664 | } resp = {}; | |
1665 | ||
1666 | err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); | |
1667 | if (err) | |
1668 | return ERR_PTR(err); | |
1669 | ||
1670 | if (req.comp_mask || req.reserved1 || req.reserved2) | |
1671 | return ERR_PTR(-EOPNOTSUPP); | |
1672 | ||
1673 | if (udata->inlen > sizeof(req) && | |
1674 | !ib_is_udata_cleared(udata, sizeof(req), | |
1675 | udata->inlen - sizeof(req))) | |
1676 | return ERR_PTR(-EOPNOTSUPP); | |
1677 | ||
1678 | ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); | |
1679 | ||
1680 | mw = kzalloc(sizeof(*mw), GFP_KERNEL); | |
ec22eb53 | 1681 | in = kzalloc(inlen, GFP_KERNEL); |
d2370e0a MB |
1682 | if (!mw || !in) { |
1683 | err = -ENOMEM; | |
1684 | goto free; | |
1685 | } | |
1686 | ||
ec22eb53 SM |
1687 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1688 | ||
1689 | MLX5_SET(mkc, mkc, free, 1); | |
1690 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1691 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1692 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1693 | MLX5_SET(mkc, mkc, lr, 1); | |
1694 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS); | |
1695 | MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); | |
1696 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1697 | ||
1698 | err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen); | |
d2370e0a MB |
1699 | if (err) |
1700 | goto free; | |
1701 | ||
1702 | mw->ibmw.rkey = mw->mmkey.key; | |
1703 | ||
1704 | resp.response_length = min(offsetof(typeof(resp), response_length) + | |
1705 | sizeof(resp.response_length), udata->outlen); | |
1706 | if (resp.response_length) { | |
1707 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
1708 | if (err) { | |
1709 | mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); | |
1710 | goto free; | |
1711 | } | |
1712 | } | |
1713 | ||
1714 | kfree(in); | |
1715 | return &mw->ibmw; | |
1716 | ||
1717 | free: | |
1718 | kfree(mw); | |
1719 | kfree(in); | |
1720 | return ERR_PTR(err); | |
1721 | } | |
1722 | ||
1723 | int mlx5_ib_dealloc_mw(struct ib_mw *mw) | |
1724 | { | |
1725 | struct mlx5_ib_mw *mmw = to_mmw(mw); | |
1726 | int err; | |
1727 | ||
1728 | err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev, | |
1729 | &mmw->mmkey); | |
1730 | if (!err) | |
1731 | kfree(mmw); | |
1732 | return err; | |
1733 | } | |
1734 | ||
d5436ba0 SG |
1735 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
1736 | struct ib_mr_status *mr_status) | |
1737 | { | |
1738 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); | |
1739 | int ret = 0; | |
1740 | ||
1741 | if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { | |
1742 | pr_err("Invalid status check mask\n"); | |
1743 | ret = -EINVAL; | |
1744 | goto done; | |
1745 | } | |
1746 | ||
1747 | mr_status->fail_status = 0; | |
1748 | if (check_mask & IB_MR_CHECK_SIG_STATUS) { | |
1749 | if (!mmr->sig) { | |
1750 | ret = -EINVAL; | |
1751 | pr_err("signature status check requested on a non-signature enabled MR\n"); | |
1752 | goto done; | |
1753 | } | |
1754 | ||
1755 | mmr->sig->sig_status_checked = true; | |
1756 | if (!mmr->sig->sig_err_exists) | |
1757 | goto done; | |
1758 | ||
1759 | if (ibmr->lkey == mmr->sig->err_item.key) | |
1760 | memcpy(&mr_status->sig_err, &mmr->sig->err_item, | |
1761 | sizeof(mr_status->sig_err)); | |
1762 | else { | |
1763 | mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; | |
1764 | mr_status->sig_err.sig_err_offset = 0; | |
1765 | mr_status->sig_err.key = mmr->sig->err_item.key; | |
1766 | } | |
1767 | ||
1768 | mmr->sig->sig_err_exists = false; | |
1769 | mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; | |
1770 | } | |
1771 | ||
1772 | done: | |
1773 | return ret; | |
1774 | } | |
8a187ee5 | 1775 | |
b005d316 SG |
1776 | static int |
1777 | mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, | |
1778 | struct scatterlist *sgl, | |
ff2ba993 | 1779 | unsigned short sg_nents, |
9aa8b321 | 1780 | unsigned int *sg_offset_p) |
b005d316 SG |
1781 | { |
1782 | struct scatterlist *sg = sgl; | |
1783 | struct mlx5_klm *klms = mr->descs; | |
9aa8b321 | 1784 | unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; |
b005d316 SG |
1785 | u32 lkey = mr->ibmr.pd->local_dma_lkey; |
1786 | int i; | |
1787 | ||
ff2ba993 | 1788 | mr->ibmr.iova = sg_dma_address(sg) + sg_offset; |
b005d316 SG |
1789 | mr->ibmr.length = 0; |
1790 | mr->ndescs = sg_nents; | |
1791 | ||
1792 | for_each_sg(sgl, sg, sg_nents, i) { | |
1793 | if (unlikely(i > mr->max_descs)) | |
1794 | break; | |
ff2ba993 CH |
1795 | klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); |
1796 | klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); | |
b005d316 SG |
1797 | klms[i].key = cpu_to_be32(lkey); |
1798 | mr->ibmr.length += sg_dma_len(sg); | |
ff2ba993 CH |
1799 | |
1800 | sg_offset = 0; | |
b005d316 SG |
1801 | } |
1802 | ||
9aa8b321 BVA |
1803 | if (sg_offset_p) |
1804 | *sg_offset_p = sg_offset; | |
1805 | ||
b005d316 SG |
1806 | return i; |
1807 | } | |
1808 | ||
8a187ee5 SG |
1809 | static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) |
1810 | { | |
1811 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1812 | __be64 *descs; | |
1813 | ||
1814 | if (unlikely(mr->ndescs == mr->max_descs)) | |
1815 | return -ENOMEM; | |
1816 | ||
1817 | descs = mr->descs; | |
1818 | descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
ff2ba993 | 1823 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 1824 | unsigned int *sg_offset) |
8a187ee5 SG |
1825 | { |
1826 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1827 | int n; | |
1828 | ||
1829 | mr->ndescs = 0; | |
1830 | ||
1831 | ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, | |
1832 | mr->desc_size * mr->max_descs, | |
1833 | DMA_TO_DEVICE); | |
1834 | ||
ec22eb53 | 1835 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
ff2ba993 | 1836 | n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset); |
b005d316 | 1837 | else |
ff2ba993 CH |
1838 | n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, |
1839 | mlx5_set_page); | |
8a187ee5 SG |
1840 | |
1841 | ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, | |
1842 | mr->desc_size * mr->max_descs, | |
1843 | DMA_TO_DEVICE); | |
1844 | ||
1845 | return n; | |
1846 | } |