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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | ||
34 | #include <linux/kref.h> | |
35 | #include <linux/random.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/export.h> | |
746b5583 | 38 | #include <linux/delay.h> |
e126ba97 | 39 | #include <rdma/ib_umem.h> |
b4cfe447 | 40 | #include <rdma/ib_umem_odp.h> |
968e78dd | 41 | #include <rdma/ib_verbs.h> |
e126ba97 EC |
42 | #include "mlx5_ib.h" |
43 | ||
44 | enum { | |
746b5583 | 45 | MAX_PENDING_REG_MR = 8, |
e126ba97 EC |
46 | }; |
47 | ||
832a6b06 | 48 | #define MLX5_UMR_ALIGN 2048 |
fe45f827 | 49 | |
fbcd4983 IL |
50 | static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); |
51 | static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); | |
8b7ff7f3 | 52 | static int mr_cache_max_order(struct mlx5_ib_dev *dev); |
49780d42 | 53 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); |
6aec21f6 | 54 | |
b4cfe447 HE |
55 | static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
56 | { | |
a606b0f6 | 57 | int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
b4cfe447 HE |
58 | |
59 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
60 | /* Wait until all page fault handlers using the mr complete. */ | |
61 | synchronize_srcu(&dev->mr_srcu); | |
62 | #endif | |
63 | ||
64 | return err; | |
65 | } | |
66 | ||
e126ba97 EC |
67 | static int order2idx(struct mlx5_ib_dev *dev, int order) |
68 | { | |
69 | struct mlx5_mr_cache *cache = &dev->cache; | |
70 | ||
71 | if (order < cache->ent[0].order) | |
72 | return 0; | |
73 | else | |
74 | return order - cache->ent[0].order; | |
75 | } | |
76 | ||
56e11d62 NO |
77 | static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) |
78 | { | |
79 | return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= | |
80 | length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); | |
81 | } | |
82 | ||
395a8e4c NO |
83 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
84 | static void update_odp_mr(struct mlx5_ib_mr *mr) | |
85 | { | |
86 | if (mr->umem->odp_data) { | |
87 | /* | |
88 | * This barrier prevents the compiler from moving the | |
89 | * setting of umem->odp_data->private to point to our | |
90 | * MR, before reg_umr finished, to ensure that the MR | |
91 | * initialization have finished before starting to | |
92 | * handle invalidations. | |
93 | */ | |
94 | smp_wmb(); | |
95 | mr->umem->odp_data->private = mr; | |
96 | /* | |
97 | * Make sure we will see the new | |
98 | * umem->odp_data->private value in the invalidation | |
99 | * routines, before we can get page faults on the | |
100 | * MR. Page faults can happen once we put the MR in | |
101 | * the tree, below this line. Without the barrier, | |
102 | * there can be a fault handling and an invalidation | |
103 | * before umem->odp_data->private == mr is visible to | |
104 | * the invalidation handler. | |
105 | */ | |
106 | smp_wmb(); | |
107 | } | |
108 | } | |
109 | #endif | |
110 | ||
746b5583 EC |
111 | static void reg_mr_callback(int status, void *context) |
112 | { | |
113 | struct mlx5_ib_mr *mr = context; | |
114 | struct mlx5_ib_dev *dev = mr->dev; | |
115 | struct mlx5_mr_cache *cache = &dev->cache; | |
116 | int c = order2idx(dev, mr->order); | |
117 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
118 | u8 key; | |
746b5583 | 119 | unsigned long flags; |
a606b0f6 | 120 | struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table; |
8605933a | 121 | int err; |
746b5583 | 122 | |
746b5583 EC |
123 | spin_lock_irqsave(&ent->lock, flags); |
124 | ent->pending--; | |
125 | spin_unlock_irqrestore(&ent->lock, flags); | |
126 | if (status) { | |
127 | mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); | |
128 | kfree(mr); | |
129 | dev->fill_delay = 1; | |
130 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
131 | return; | |
132 | } | |
133 | ||
aa8e08d2 | 134 | mr->mmkey.type = MLX5_MKEY_MR; |
9603b61d JM |
135 | spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); |
136 | key = dev->mdev->priv.mkey_key++; | |
137 | spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); | |
ec22eb53 | 138 | mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key; |
746b5583 EC |
139 | |
140 | cache->last_add = jiffies; | |
141 | ||
142 | spin_lock_irqsave(&ent->lock, flags); | |
143 | list_add_tail(&mr->list, &ent->head); | |
144 | ent->cur++; | |
145 | ent->size++; | |
146 | spin_unlock_irqrestore(&ent->lock, flags); | |
8605933a HE |
147 | |
148 | write_lock_irqsave(&table->lock, flags); | |
a606b0f6 MB |
149 | err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key), |
150 | &mr->mmkey); | |
8605933a | 151 | if (err) |
a606b0f6 | 152 | pr_err("Error inserting to mkey tree. 0x%x\n", -err); |
8605933a | 153 | write_unlock_irqrestore(&table->lock, flags); |
49780d42 AK |
154 | |
155 | if (!completion_done(&ent->compl)) | |
156 | complete(&ent->compl); | |
746b5583 EC |
157 | } |
158 | ||
e126ba97 EC |
159 | static int add_keys(struct mlx5_ib_dev *dev, int c, int num) |
160 | { | |
e126ba97 EC |
161 | struct mlx5_mr_cache *cache = &dev->cache; |
162 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
ec22eb53 | 163 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
e126ba97 | 164 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
165 | void *mkc; |
166 | u32 *in; | |
e126ba97 EC |
167 | int err = 0; |
168 | int i; | |
169 | ||
ec22eb53 | 170 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
171 | if (!in) |
172 | return -ENOMEM; | |
173 | ||
ec22eb53 | 174 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
e126ba97 | 175 | for (i = 0; i < num; i++) { |
746b5583 EC |
176 | if (ent->pending >= MAX_PENDING_REG_MR) { |
177 | err = -EAGAIN; | |
178 | break; | |
179 | } | |
180 | ||
e126ba97 EC |
181 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
182 | if (!mr) { | |
183 | err = -ENOMEM; | |
746b5583 | 184 | break; |
e126ba97 EC |
185 | } |
186 | mr->order = ent->order; | |
8b7ff7f3 | 187 | mr->allocated_from_cache = 1; |
746b5583 | 188 | mr->dev = dev; |
ec22eb53 SM |
189 | |
190 | MLX5_SET(mkc, mkc, free, 1); | |
191 | MLX5_SET(mkc, mkc, umr_en, 1); | |
49780d42 | 192 | MLX5_SET(mkc, mkc, access_mode, ent->access_mode); |
ec22eb53 SM |
193 | |
194 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
49780d42 AK |
195 | MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt); |
196 | MLX5_SET(mkc, mkc, log_page_size, ent->page); | |
e126ba97 | 197 | |
746b5583 EC |
198 | spin_lock_irq(&ent->lock); |
199 | ent->pending++; | |
200 | spin_unlock_irq(&ent->lock); | |
ec22eb53 SM |
201 | err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey, |
202 | in, inlen, | |
203 | mr->out, sizeof(mr->out), | |
204 | reg_mr_callback, mr); | |
e126ba97 | 205 | if (err) { |
d14e7110 EC |
206 | spin_lock_irq(&ent->lock); |
207 | ent->pending--; | |
208 | spin_unlock_irq(&ent->lock); | |
e126ba97 | 209 | mlx5_ib_warn(dev, "create mkey failed %d\n", err); |
e126ba97 | 210 | kfree(mr); |
746b5583 | 211 | break; |
e126ba97 | 212 | } |
e126ba97 EC |
213 | } |
214 | ||
e126ba97 EC |
215 | kfree(in); |
216 | return err; | |
217 | } | |
218 | ||
219 | static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) | |
220 | { | |
e126ba97 EC |
221 | struct mlx5_mr_cache *cache = &dev->cache; |
222 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
223 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
224 | int err; |
225 | int i; | |
226 | ||
227 | for (i = 0; i < num; i++) { | |
746b5583 | 228 | spin_lock_irq(&ent->lock); |
e126ba97 | 229 | if (list_empty(&ent->head)) { |
746b5583 | 230 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
231 | return; |
232 | } | |
233 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
234 | list_del(&mr->list); | |
235 | ent->cur--; | |
236 | ent->size--; | |
746b5583 | 237 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 238 | err = destroy_mkey(dev, mr); |
203099fd | 239 | if (err) |
e126ba97 | 240 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 241 | else |
e126ba97 | 242 | kfree(mr); |
e126ba97 EC |
243 | } |
244 | } | |
245 | ||
246 | static ssize_t size_write(struct file *filp, const char __user *buf, | |
247 | size_t count, loff_t *pos) | |
248 | { | |
249 | struct mlx5_cache_ent *ent = filp->private_data; | |
250 | struct mlx5_ib_dev *dev = ent->dev; | |
251 | char lbuf[20]; | |
252 | u32 var; | |
253 | int err; | |
254 | int c; | |
255 | ||
256 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 257 | return -EFAULT; |
e126ba97 EC |
258 | |
259 | c = order2idx(dev, ent->order); | |
260 | lbuf[sizeof(lbuf) - 1] = 0; | |
261 | ||
262 | if (sscanf(lbuf, "%u", &var) != 1) | |
263 | return -EINVAL; | |
264 | ||
265 | if (var < ent->limit) | |
266 | return -EINVAL; | |
267 | ||
268 | if (var > ent->size) { | |
746b5583 EC |
269 | do { |
270 | err = add_keys(dev, c, var - ent->size); | |
271 | if (err && err != -EAGAIN) | |
272 | return err; | |
273 | ||
274 | usleep_range(3000, 5000); | |
275 | } while (err); | |
e126ba97 EC |
276 | } else if (var < ent->size) { |
277 | remove_keys(dev, c, ent->size - var); | |
278 | } | |
279 | ||
280 | return count; | |
281 | } | |
282 | ||
283 | static ssize_t size_read(struct file *filp, char __user *buf, size_t count, | |
284 | loff_t *pos) | |
285 | { | |
286 | struct mlx5_cache_ent *ent = filp->private_data; | |
287 | char lbuf[20]; | |
288 | int err; | |
289 | ||
290 | if (*pos) | |
291 | return 0; | |
292 | ||
293 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); | |
294 | if (err < 0) | |
295 | return err; | |
296 | ||
297 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 298 | return -EFAULT; |
e126ba97 EC |
299 | |
300 | *pos += err; | |
301 | ||
302 | return err; | |
303 | } | |
304 | ||
305 | static const struct file_operations size_fops = { | |
306 | .owner = THIS_MODULE, | |
307 | .open = simple_open, | |
308 | .write = size_write, | |
309 | .read = size_read, | |
310 | }; | |
311 | ||
312 | static ssize_t limit_write(struct file *filp, const char __user *buf, | |
313 | size_t count, loff_t *pos) | |
314 | { | |
315 | struct mlx5_cache_ent *ent = filp->private_data; | |
316 | struct mlx5_ib_dev *dev = ent->dev; | |
317 | char lbuf[20]; | |
318 | u32 var; | |
319 | int err; | |
320 | int c; | |
321 | ||
322 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 323 | return -EFAULT; |
e126ba97 EC |
324 | |
325 | c = order2idx(dev, ent->order); | |
326 | lbuf[sizeof(lbuf) - 1] = 0; | |
327 | ||
328 | if (sscanf(lbuf, "%u", &var) != 1) | |
329 | return -EINVAL; | |
330 | ||
331 | if (var > ent->size) | |
332 | return -EINVAL; | |
333 | ||
334 | ent->limit = var; | |
335 | ||
336 | if (ent->cur < ent->limit) { | |
337 | err = add_keys(dev, c, 2 * ent->limit - ent->cur); | |
338 | if (err) | |
339 | return err; | |
340 | } | |
341 | ||
342 | return count; | |
343 | } | |
344 | ||
345 | static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, | |
346 | loff_t *pos) | |
347 | { | |
348 | struct mlx5_cache_ent *ent = filp->private_data; | |
349 | char lbuf[20]; | |
350 | int err; | |
351 | ||
352 | if (*pos) | |
353 | return 0; | |
354 | ||
355 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); | |
356 | if (err < 0) | |
357 | return err; | |
358 | ||
359 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 360 | return -EFAULT; |
e126ba97 EC |
361 | |
362 | *pos += err; | |
363 | ||
364 | return err; | |
365 | } | |
366 | ||
367 | static const struct file_operations limit_fops = { | |
368 | .owner = THIS_MODULE, | |
369 | .open = simple_open, | |
370 | .write = limit_write, | |
371 | .read = limit_read, | |
372 | }; | |
373 | ||
374 | static int someone_adding(struct mlx5_mr_cache *cache) | |
375 | { | |
376 | int i; | |
377 | ||
378 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
379 | if (cache->ent[i].cur < cache->ent[i].limit) | |
380 | return 1; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static void __cache_work_func(struct mlx5_cache_ent *ent) | |
387 | { | |
388 | struct mlx5_ib_dev *dev = ent->dev; | |
389 | struct mlx5_mr_cache *cache = &dev->cache; | |
390 | int i = order2idx(dev, ent->order); | |
746b5583 | 391 | int err; |
e126ba97 EC |
392 | |
393 | if (cache->stopped) | |
394 | return; | |
395 | ||
396 | ent = &dev->cache.ent[i]; | |
746b5583 EC |
397 | if (ent->cur < 2 * ent->limit && !dev->fill_delay) { |
398 | err = add_keys(dev, i, 1); | |
399 | if (ent->cur < 2 * ent->limit) { | |
400 | if (err == -EAGAIN) { | |
401 | mlx5_ib_dbg(dev, "returned eagain, order %d\n", | |
402 | i + 2); | |
403 | queue_delayed_work(cache->wq, &ent->dwork, | |
404 | msecs_to_jiffies(3)); | |
405 | } else if (err) { | |
406 | mlx5_ib_warn(dev, "command failed order %d, err %d\n", | |
407 | i + 2, err); | |
408 | queue_delayed_work(cache->wq, &ent->dwork, | |
409 | msecs_to_jiffies(1000)); | |
410 | } else { | |
411 | queue_work(cache->wq, &ent->work); | |
412 | } | |
413 | } | |
e126ba97 | 414 | } else if (ent->cur > 2 * ent->limit) { |
ab5cdc31 LR |
415 | /* |
416 | * The remove_keys() logic is performed as garbage collection | |
417 | * task. Such task is intended to be run when no other active | |
418 | * processes are running. | |
419 | * | |
420 | * The need_resched() will return TRUE if there are user tasks | |
421 | * to be activated in near future. | |
422 | * | |
423 | * In such case, we don't execute remove_keys() and postpone | |
424 | * the garbage collection work to try to run in next cycle, | |
425 | * in order to free CPU resources to other tasks. | |
426 | */ | |
427 | if (!need_resched() && !someone_adding(cache) && | |
746b5583 | 428 | time_after(jiffies, cache->last_add + 300 * HZ)) { |
e126ba97 EC |
429 | remove_keys(dev, i, 1); |
430 | if (ent->cur > ent->limit) | |
431 | queue_work(cache->wq, &ent->work); | |
432 | } else { | |
746b5583 | 433 | queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); |
e126ba97 EC |
434 | } |
435 | } | |
436 | } | |
437 | ||
438 | static void delayed_cache_work_func(struct work_struct *work) | |
439 | { | |
440 | struct mlx5_cache_ent *ent; | |
441 | ||
442 | ent = container_of(work, struct mlx5_cache_ent, dwork.work); | |
443 | __cache_work_func(ent); | |
444 | } | |
445 | ||
446 | static void cache_work_func(struct work_struct *work) | |
447 | { | |
448 | struct mlx5_cache_ent *ent; | |
449 | ||
450 | ent = container_of(work, struct mlx5_cache_ent, work); | |
451 | __cache_work_func(ent); | |
452 | } | |
453 | ||
49780d42 AK |
454 | struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry) |
455 | { | |
456 | struct mlx5_mr_cache *cache = &dev->cache; | |
457 | struct mlx5_cache_ent *ent; | |
458 | struct mlx5_ib_mr *mr; | |
459 | int err; | |
460 | ||
461 | if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) { | |
462 | mlx5_ib_err(dev, "cache entry %d is out of range\n", entry); | |
463 | return NULL; | |
464 | } | |
465 | ||
466 | ent = &cache->ent[entry]; | |
467 | while (1) { | |
468 | spin_lock_irq(&ent->lock); | |
469 | if (list_empty(&ent->head)) { | |
470 | spin_unlock_irq(&ent->lock); | |
471 | ||
472 | err = add_keys(dev, entry, 1); | |
81713d37 | 473 | if (err && err != -EAGAIN) |
49780d42 AK |
474 | return ERR_PTR(err); |
475 | ||
476 | wait_for_completion(&ent->compl); | |
477 | } else { | |
478 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
479 | list); | |
480 | list_del(&mr->list); | |
481 | ent->cur--; | |
482 | spin_unlock_irq(&ent->lock); | |
483 | if (ent->cur < ent->limit) | |
484 | queue_work(cache->wq, &ent->work); | |
485 | return mr; | |
486 | } | |
487 | } | |
488 | } | |
489 | ||
e126ba97 EC |
490 | static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) |
491 | { | |
492 | struct mlx5_mr_cache *cache = &dev->cache; | |
493 | struct mlx5_ib_mr *mr = NULL; | |
494 | struct mlx5_cache_ent *ent; | |
4c25b7a3 | 495 | int last_umr_cache_entry; |
e126ba97 EC |
496 | int c; |
497 | int i; | |
498 | ||
499 | c = order2idx(dev, order); | |
8b7ff7f3 | 500 | last_umr_cache_entry = order2idx(dev, mr_cache_max_order(dev)); |
4c25b7a3 | 501 | if (c < 0 || c > last_umr_cache_entry) { |
e126ba97 EC |
502 | mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); |
503 | return NULL; | |
504 | } | |
505 | ||
4c25b7a3 | 506 | for (i = c; i <= last_umr_cache_entry; i++) { |
e126ba97 EC |
507 | ent = &cache->ent[i]; |
508 | ||
509 | mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); | |
510 | ||
746b5583 | 511 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
512 | if (!list_empty(&ent->head)) { |
513 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
514 | list); | |
515 | list_del(&mr->list); | |
516 | ent->cur--; | |
746b5583 | 517 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
518 | if (ent->cur < ent->limit) |
519 | queue_work(cache->wq, &ent->work); | |
520 | break; | |
521 | } | |
746b5583 | 522 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
523 | |
524 | queue_work(cache->wq, &ent->work); | |
e126ba97 EC |
525 | } |
526 | ||
527 | if (!mr) | |
528 | cache->ent[c].miss++; | |
529 | ||
530 | return mr; | |
531 | } | |
532 | ||
49780d42 | 533 | void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 EC |
534 | { |
535 | struct mlx5_mr_cache *cache = &dev->cache; | |
536 | struct mlx5_cache_ent *ent; | |
537 | int shrink = 0; | |
538 | int c; | |
539 | ||
540 | c = order2idx(dev, mr->order); | |
541 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
542 | mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); | |
543 | return; | |
544 | } | |
49780d42 AK |
545 | |
546 | if (unreg_umr(dev, mr)) | |
547 | return; | |
548 | ||
e126ba97 | 549 | ent = &cache->ent[c]; |
746b5583 | 550 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
551 | list_add_tail(&mr->list, &ent->head); |
552 | ent->cur++; | |
553 | if (ent->cur > 2 * ent->limit) | |
554 | shrink = 1; | |
746b5583 | 555 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
556 | |
557 | if (shrink) | |
558 | queue_work(cache->wq, &ent->work); | |
559 | } | |
560 | ||
561 | static void clean_keys(struct mlx5_ib_dev *dev, int c) | |
562 | { | |
e126ba97 EC |
563 | struct mlx5_mr_cache *cache = &dev->cache; |
564 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
565 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
566 | int err; |
567 | ||
3c461911 | 568 | cancel_delayed_work(&ent->dwork); |
e126ba97 | 569 | while (1) { |
746b5583 | 570 | spin_lock_irq(&ent->lock); |
e126ba97 | 571 | if (list_empty(&ent->head)) { |
746b5583 | 572 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
573 | return; |
574 | } | |
575 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
576 | list_del(&mr->list); | |
577 | ent->cur--; | |
578 | ent->size--; | |
746b5583 | 579 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 580 | err = destroy_mkey(dev, mr); |
203099fd | 581 | if (err) |
e126ba97 | 582 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 583 | else |
e126ba97 | 584 | kfree(mr); |
e126ba97 EC |
585 | } |
586 | } | |
587 | ||
12cc1a02 LR |
588 | static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) |
589 | { | |
590 | if (!mlx5_debugfs_root) | |
591 | return; | |
592 | ||
593 | debugfs_remove_recursive(dev->cache.root); | |
594 | dev->cache.root = NULL; | |
595 | } | |
596 | ||
e126ba97 EC |
597 | static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) |
598 | { | |
599 | struct mlx5_mr_cache *cache = &dev->cache; | |
600 | struct mlx5_cache_ent *ent; | |
601 | int i; | |
602 | ||
603 | if (!mlx5_debugfs_root) | |
604 | return 0; | |
605 | ||
9603b61d | 606 | cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); |
e126ba97 EC |
607 | if (!cache->root) |
608 | return -ENOMEM; | |
609 | ||
610 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
611 | ent = &cache->ent[i]; | |
612 | sprintf(ent->name, "%d", ent->order); | |
613 | ent->dir = debugfs_create_dir(ent->name, cache->root); | |
614 | if (!ent->dir) | |
12cc1a02 | 615 | goto err; |
e126ba97 EC |
616 | |
617 | ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, | |
618 | &size_fops); | |
619 | if (!ent->fsize) | |
12cc1a02 | 620 | goto err; |
e126ba97 EC |
621 | |
622 | ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, | |
623 | &limit_fops); | |
624 | if (!ent->flimit) | |
12cc1a02 | 625 | goto err; |
e126ba97 EC |
626 | |
627 | ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, | |
628 | &ent->cur); | |
629 | if (!ent->fcur) | |
12cc1a02 | 630 | goto err; |
e126ba97 EC |
631 | |
632 | ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, | |
633 | &ent->miss); | |
634 | if (!ent->fmiss) | |
12cc1a02 | 635 | goto err; |
e126ba97 EC |
636 | } |
637 | ||
638 | return 0; | |
12cc1a02 LR |
639 | err: |
640 | mlx5_mr_cache_debugfs_cleanup(dev); | |
e126ba97 | 641 | |
12cc1a02 | 642 | return -ENOMEM; |
e126ba97 EC |
643 | } |
644 | ||
746b5583 EC |
645 | static void delay_time_func(unsigned long ctx) |
646 | { | |
647 | struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx; | |
648 | ||
649 | dev->fill_delay = 0; | |
650 | } | |
651 | ||
e126ba97 EC |
652 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) |
653 | { | |
654 | struct mlx5_mr_cache *cache = &dev->cache; | |
655 | struct mlx5_cache_ent *ent; | |
e126ba97 EC |
656 | int err; |
657 | int i; | |
658 | ||
6bc1a656 | 659 | mutex_init(&dev->slow_path_mutex); |
3c856c82 | 660 | cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); |
e126ba97 EC |
661 | if (!cache->wq) { |
662 | mlx5_ib_warn(dev, "failed to create work queue\n"); | |
663 | return -ENOMEM; | |
664 | } | |
665 | ||
746b5583 | 666 | setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev); |
e126ba97 | 667 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { |
e126ba97 EC |
668 | ent = &cache->ent[i]; |
669 | INIT_LIST_HEAD(&ent->head); | |
670 | spin_lock_init(&ent->lock); | |
671 | ent->order = i + 2; | |
672 | ent->dev = dev; | |
49780d42 | 673 | ent->limit = 0; |
e126ba97 | 674 | |
49780d42 | 675 | init_completion(&ent->compl); |
e126ba97 EC |
676 | INIT_WORK(&ent->work, cache_work_func); |
677 | INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); | |
e126ba97 | 678 | queue_work(cache->wq, &ent->work); |
49780d42 | 679 | |
8b7ff7f3 | 680 | if (i > MR_CACHE_LAST_STD_ENTRY) { |
81713d37 | 681 | mlx5_odp_init_mr_cache_entry(ent); |
49780d42 | 682 | continue; |
81713d37 | 683 | } |
49780d42 | 684 | |
8b7ff7f3 | 685 | if (ent->order > mr_cache_max_order(dev)) |
49780d42 AK |
686 | continue; |
687 | ||
688 | ent->page = PAGE_SHIFT; | |
689 | ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) / | |
690 | MLX5_IB_UMR_OCTOWORD; | |
691 | ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; | |
692 | if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && | |
693 | mlx5_core_is_pf(dev->mdev)) | |
694 | ent->limit = dev->mdev->profile->mr_cache[i].limit; | |
695 | else | |
696 | ent->limit = 0; | |
e126ba97 EC |
697 | } |
698 | ||
699 | err = mlx5_mr_cache_debugfs_init(dev); | |
700 | if (err) | |
701 | mlx5_ib_warn(dev, "cache debugfs failure\n"); | |
702 | ||
12cc1a02 LR |
703 | /* |
704 | * We don't want to fail driver if debugfs failed to initialize, | |
705 | * so we are not forwarding error to the user. | |
706 | */ | |
707 | ||
e126ba97 EC |
708 | return 0; |
709 | } | |
710 | ||
acbda523 EC |
711 | static void wait_for_async_commands(struct mlx5_ib_dev *dev) |
712 | { | |
713 | struct mlx5_mr_cache *cache = &dev->cache; | |
714 | struct mlx5_cache_ent *ent; | |
715 | int total = 0; | |
716 | int i; | |
717 | int j; | |
718 | ||
719 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
720 | ent = &cache->ent[i]; | |
721 | for (j = 0 ; j < 1000; j++) { | |
722 | if (!ent->pending) | |
723 | break; | |
724 | msleep(50); | |
725 | } | |
726 | } | |
727 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
728 | ent = &cache->ent[i]; | |
729 | total += ent->pending; | |
730 | } | |
731 | ||
732 | if (total) | |
733 | mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total); | |
734 | else | |
735 | mlx5_ib_warn(dev, "done with all pending requests\n"); | |
736 | } | |
737 | ||
e126ba97 EC |
738 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) |
739 | { | |
740 | int i; | |
741 | ||
742 | dev->cache.stopped = 1; | |
3c461911 | 743 | flush_workqueue(dev->cache.wq); |
e126ba97 EC |
744 | |
745 | mlx5_mr_cache_debugfs_cleanup(dev); | |
746 | ||
747 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) | |
748 | clean_keys(dev, i); | |
749 | ||
3c461911 | 750 | destroy_workqueue(dev->cache.wq); |
acbda523 | 751 | wait_for_async_commands(dev); |
746b5583 | 752 | del_timer_sync(&dev->delay_timer); |
3c461911 | 753 | |
e126ba97 EC |
754 | return 0; |
755 | } | |
756 | ||
757 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) | |
758 | { | |
759 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 760 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
9603b61d | 761 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 | 762 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
763 | void *mkc; |
764 | u32 *in; | |
e126ba97 EC |
765 | int err; |
766 | ||
767 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
768 | if (!mr) | |
769 | return ERR_PTR(-ENOMEM); | |
770 | ||
ec22eb53 | 771 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
772 | if (!in) { |
773 | err = -ENOMEM; | |
774 | goto err_free; | |
775 | } | |
776 | ||
ec22eb53 SM |
777 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
778 | ||
779 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA); | |
780 | MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); | |
781 | MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); | |
782 | MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); | |
783 | MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); | |
784 | MLX5_SET(mkc, mkc, lr, 1); | |
e126ba97 | 785 | |
ec22eb53 SM |
786 | MLX5_SET(mkc, mkc, length64, 1); |
787 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
788 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
789 | MLX5_SET64(mkc, mkc, start_addr, 0); | |
790 | ||
791 | err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
792 | if (err) |
793 | goto err_in; | |
794 | ||
795 | kfree(in); | |
aa8e08d2 | 796 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
797 | mr->ibmr.lkey = mr->mmkey.key; |
798 | mr->ibmr.rkey = mr->mmkey.key; | |
e126ba97 EC |
799 | mr->umem = NULL; |
800 | ||
801 | return &mr->ibmr; | |
802 | ||
803 | err_in: | |
804 | kfree(in); | |
805 | ||
806 | err_free: | |
807 | kfree(mr); | |
808 | ||
809 | return ERR_PTR(err); | |
810 | } | |
811 | ||
7b4cdaae | 812 | static int get_octo_len(u64 addr, u64 len, int page_shift) |
e126ba97 | 813 | { |
7b4cdaae | 814 | u64 page_size = 1ULL << page_shift; |
e126ba97 EC |
815 | u64 offset; |
816 | int npages; | |
817 | ||
818 | offset = addr & (page_size - 1); | |
7b4cdaae | 819 | npages = ALIGN(len + offset, page_size) >> page_shift; |
e126ba97 EC |
820 | return (npages + 1) / 2; |
821 | } | |
822 | ||
8b7ff7f3 | 823 | static int mr_cache_max_order(struct mlx5_ib_dev *dev) |
e126ba97 | 824 | { |
7d0cc6ed | 825 | if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) |
8b7ff7f3 | 826 | return MR_CACHE_LAST_STD_ENTRY + 2; |
4c25b7a3 MD |
827 | return MLX5_MAX_UMR_SHIFT; |
828 | } | |
829 | ||
14ab8896 AB |
830 | static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length, |
831 | int access_flags, struct ib_umem **umem, | |
832 | int *npages, int *page_shift, int *ncont, | |
833 | int *order) | |
395a8e4c NO |
834 | { |
835 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
14ab8896 AB |
836 | int err; |
837 | ||
838 | *umem = ib_umem_get(pd->uobject->context, start, length, | |
839 | access_flags, 0); | |
840 | err = PTR_ERR_OR_ZERO(*umem); | |
841 | if (err < 0) { | |
396551eb | 842 | mlx5_ib_err(dev, "umem get failed (%d)\n", err); |
14ab8896 | 843 | return err; |
395a8e4c NO |
844 | } |
845 | ||
14ab8896 | 846 | mlx5_ib_cont_pages(*umem, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages, |
762f899a | 847 | page_shift, ncont, order); |
395a8e4c NO |
848 | if (!*npages) { |
849 | mlx5_ib_warn(dev, "avoid zero region\n"); | |
14ab8896 AB |
850 | ib_umem_release(*umem); |
851 | return -EINVAL; | |
395a8e4c NO |
852 | } |
853 | ||
854 | mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", | |
855 | *npages, *ncont, *order, *page_shift); | |
856 | ||
14ab8896 | 857 | return 0; |
395a8e4c NO |
858 | } |
859 | ||
add08d76 | 860 | static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) |
e126ba97 | 861 | { |
add08d76 CH |
862 | struct mlx5_ib_umr_context *context = |
863 | container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); | |
e126ba97 | 864 | |
add08d76 CH |
865 | context->status = wc->status; |
866 | complete(&context->done); | |
867 | } | |
e126ba97 | 868 | |
add08d76 CH |
869 | static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) |
870 | { | |
871 | context->cqe.done = mlx5_ib_umr_done; | |
872 | context->status = -1; | |
873 | init_completion(&context->done); | |
e126ba97 EC |
874 | } |
875 | ||
d5ea2df9 BJ |
876 | static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev, |
877 | struct mlx5_umr_wr *umrwr) | |
878 | { | |
879 | struct umr_common *umrc = &dev->umrc; | |
880 | struct ib_send_wr *bad; | |
881 | int err; | |
882 | struct mlx5_ib_umr_context umr_context; | |
883 | ||
884 | mlx5_ib_init_umr_context(&umr_context); | |
885 | umrwr->wr.wr_cqe = &umr_context.cqe; | |
886 | ||
887 | down(&umrc->sem); | |
888 | err = ib_post_send(umrc->qp, &umrwr->wr, &bad); | |
889 | if (err) { | |
890 | mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err); | |
891 | } else { | |
892 | wait_for_completion(&umr_context.done); | |
893 | if (umr_context.status != IB_WC_SUCCESS) { | |
894 | mlx5_ib_warn(dev, "reg umr failed (%u)\n", | |
895 | umr_context.status); | |
896 | err = -EFAULT; | |
897 | } | |
898 | } | |
899 | up(&umrc->sem); | |
900 | return err; | |
901 | } | |
902 | ||
ff740aef IL |
903 | static struct mlx5_ib_mr *alloc_mr_from_cache( |
904 | struct ib_pd *pd, struct ib_umem *umem, | |
e126ba97 EC |
905 | u64 virt_addr, u64 len, int npages, |
906 | int page_shift, int order, int access_flags) | |
907 | { | |
908 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 909 | struct mlx5_ib_mr *mr; |
096f7e72 | 910 | int err = 0; |
e126ba97 EC |
911 | int i; |
912 | ||
746b5583 | 913 | for (i = 0; i < 1; i++) { |
e126ba97 EC |
914 | mr = alloc_cached_mr(dev, order); |
915 | if (mr) | |
916 | break; | |
917 | ||
918 | err = add_keys(dev, order2idx(dev, order), 1); | |
746b5583 EC |
919 | if (err && err != -EAGAIN) { |
920 | mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); | |
e126ba97 EC |
921 | break; |
922 | } | |
923 | } | |
924 | ||
925 | if (!mr) | |
926 | return ERR_PTR(-EAGAIN); | |
927 | ||
7d0cc6ed AK |
928 | mr->ibmr.pd = pd; |
929 | mr->umem = umem; | |
930 | mr->access_flags = access_flags; | |
931 | mr->desc_size = sizeof(struct mlx5_mtt); | |
a606b0f6 MB |
932 | mr->mmkey.iova = virt_addr; |
933 | mr->mmkey.size = len; | |
934 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
b475598a | 935 | |
e126ba97 | 936 | return mr; |
e126ba97 EC |
937 | } |
938 | ||
7d0cc6ed AK |
939 | static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages, |
940 | void *xlt, int page_shift, size_t size, | |
941 | int flags) | |
832a6b06 HE |
942 | { |
943 | struct mlx5_ib_dev *dev = mr->dev; | |
832a6b06 | 944 | struct ib_umem *umem = mr->umem; |
81713d37 AK |
945 | if (flags & MLX5_IB_UPD_XLT_INDIRECT) { |
946 | mlx5_odp_populate_klm(xlt, idx, npages, mr, flags); | |
947 | return npages; | |
948 | } | |
7d0cc6ed AK |
949 | |
950 | npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx); | |
951 | ||
952 | if (!(flags & MLX5_IB_UPD_XLT_ZAP)) { | |
953 | __mlx5_ib_populate_pas(dev, umem, page_shift, | |
954 | idx, npages, xlt, | |
955 | MLX5_IB_MTT_PRESENT); | |
956 | /* Clear padding after the pages | |
957 | * brought from the umem. | |
958 | */ | |
959 | memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0, | |
960 | size - npages * sizeof(struct mlx5_mtt)); | |
961 | } | |
962 | ||
963 | return npages; | |
964 | } | |
965 | ||
966 | #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \ | |
967 | MLX5_UMR_MTT_ALIGNMENT) | |
968 | #define MLX5_SPARE_UMR_CHUNK 0x10000 | |
969 | ||
970 | int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, | |
971 | int page_shift, int flags) | |
972 | { | |
973 | struct mlx5_ib_dev *dev = mr->dev; | |
9b0c289e | 974 | struct device *ddev = dev->ib_dev.dev.parent; |
7d0cc6ed | 975 | struct mlx5_ib_ucontext *uctx = NULL; |
832a6b06 | 976 | int size; |
7d0cc6ed | 977 | void *xlt; |
832a6b06 | 978 | dma_addr_t dma; |
e622f2f4 | 979 | struct mlx5_umr_wr wr; |
832a6b06 HE |
980 | struct ib_sge sg; |
981 | int err = 0; | |
81713d37 AK |
982 | int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) |
983 | ? sizeof(struct mlx5_klm) | |
984 | : sizeof(struct mlx5_mtt); | |
7d0cc6ed AK |
985 | const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size; |
986 | const int page_mask = page_align - 1; | |
832a6b06 HE |
987 | size_t pages_mapped = 0; |
988 | size_t pages_to_map = 0; | |
989 | size_t pages_iter = 0; | |
7d0cc6ed | 990 | gfp_t gfp; |
832a6b06 HE |
991 | |
992 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, | |
7d0cc6ed AK |
993 | * so we need to align the offset and length accordingly |
994 | */ | |
995 | if (idx & page_mask) { | |
996 | npages += idx & page_mask; | |
997 | idx &= ~page_mask; | |
832a6b06 HE |
998 | } |
999 | ||
7d0cc6ed AK |
1000 | gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL; |
1001 | gfp |= __GFP_ZERO | __GFP_NOWARN; | |
832a6b06 | 1002 | |
7d0cc6ed AK |
1003 | pages_to_map = ALIGN(npages, page_align); |
1004 | size = desc_size * pages_to_map; | |
1005 | size = min_t(int, size, MLX5_MAX_UMR_CHUNK); | |
832a6b06 | 1006 | |
7d0cc6ed AK |
1007 | xlt = (void *)__get_free_pages(gfp, get_order(size)); |
1008 | if (!xlt && size > MLX5_SPARE_UMR_CHUNK) { | |
1009 | mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n", | |
1010 | size, get_order(size), MLX5_SPARE_UMR_CHUNK); | |
1011 | ||
1012 | size = MLX5_SPARE_UMR_CHUNK; | |
1013 | xlt = (void *)__get_free_pages(gfp, get_order(size)); | |
832a6b06 | 1014 | } |
7d0cc6ed AK |
1015 | |
1016 | if (!xlt) { | |
bd174fc2 | 1017 | uctx = to_mucontext(mr->ibmr.pd->uobject->context); |
7d0cc6ed AK |
1018 | mlx5_ib_warn(dev, "Using XLT emergency buffer\n"); |
1019 | size = PAGE_SIZE; | |
1020 | xlt = (void *)uctx->upd_xlt_page; | |
1021 | mutex_lock(&uctx->upd_xlt_page_mutex); | |
1022 | memset(xlt, 0, size); | |
1023 | } | |
1024 | pages_iter = size / desc_size; | |
1025 | dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE); | |
832a6b06 | 1026 | if (dma_mapping_error(ddev, dma)) { |
7d0cc6ed | 1027 | mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); |
832a6b06 | 1028 | err = -ENOMEM; |
7d0cc6ed | 1029 | goto free_xlt; |
832a6b06 HE |
1030 | } |
1031 | ||
7d0cc6ed AK |
1032 | sg.addr = dma; |
1033 | sg.lkey = dev->umrc.pd->local_dma_lkey; | |
1034 | ||
1035 | memset(&wr, 0, sizeof(wr)); | |
1036 | wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT; | |
1037 | if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) | |
1038 | wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1039 | wr.wr.sg_list = &sg; | |
1040 | wr.wr.num_sge = 1; | |
1041 | wr.wr.opcode = MLX5_IB_WR_UMR; | |
1042 | ||
1043 | wr.pd = mr->ibmr.pd; | |
1044 | wr.mkey = mr->mmkey.key; | |
1045 | wr.length = mr->mmkey.size; | |
1046 | wr.virt_addr = mr->mmkey.iova; | |
1047 | wr.access_flags = mr->access_flags; | |
1048 | wr.page_shift = page_shift; | |
1049 | ||
832a6b06 HE |
1050 | for (pages_mapped = 0; |
1051 | pages_mapped < pages_to_map && !err; | |
7d0cc6ed | 1052 | pages_mapped += pages_iter, idx += pages_iter) { |
438b228e | 1053 | npages = min_t(int, pages_iter, pages_to_map - pages_mapped); |
832a6b06 | 1054 | dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); |
438b228e | 1055 | npages = populate_xlt(mr, idx, npages, xlt, |
7d0cc6ed | 1056 | page_shift, size, flags); |
832a6b06 HE |
1057 | |
1058 | dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); | |
1059 | ||
7d0cc6ed AK |
1060 | sg.length = ALIGN(npages * desc_size, |
1061 | MLX5_UMR_MTT_ALIGNMENT); | |
1062 | ||
1063 | if (pages_mapped + pages_iter >= pages_to_map) { | |
1064 | if (flags & MLX5_IB_UPD_XLT_ENABLE) | |
1065 | wr.wr.send_flags |= | |
1066 | MLX5_IB_SEND_UMR_ENABLE_MR | | |
1067 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS | | |
1068 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1069 | if (flags & MLX5_IB_UPD_XLT_PD || | |
1070 | flags & MLX5_IB_UPD_XLT_ACCESS) | |
1071 | wr.wr.send_flags |= | |
1072 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; | |
1073 | if (flags & MLX5_IB_UPD_XLT_ADDR) | |
1074 | wr.wr.send_flags |= | |
1075 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1076 | } | |
832a6b06 | 1077 | |
7d0cc6ed | 1078 | wr.offset = idx * desc_size; |
31616255 | 1079 | wr.xlt_size = sg.length; |
832a6b06 | 1080 | |
d5ea2df9 | 1081 | err = mlx5_ib_post_send_wait(dev, &wr); |
832a6b06 HE |
1082 | } |
1083 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
1084 | ||
7d0cc6ed AK |
1085 | free_xlt: |
1086 | if (uctx) | |
1087 | mutex_unlock(&uctx->upd_xlt_page_mutex); | |
832a6b06 | 1088 | else |
7d0cc6ed | 1089 | free_pages((unsigned long)xlt, get_order(size)); |
832a6b06 HE |
1090 | |
1091 | return err; | |
1092 | } | |
832a6b06 | 1093 | |
395a8e4c NO |
1094 | /* |
1095 | * If ibmr is NULL it will be allocated by reg_create. | |
1096 | * Else, the given ibmr will be used. | |
1097 | */ | |
1098 | static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, | |
1099 | u64 virt_addr, u64 length, | |
1100 | struct ib_umem *umem, int npages, | |
ff740aef IL |
1101 | int page_shift, int access_flags, |
1102 | bool populate) | |
e126ba97 EC |
1103 | { |
1104 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 1105 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
1106 | __be64 *pas; |
1107 | void *mkc; | |
e126ba97 | 1108 | int inlen; |
ec22eb53 | 1109 | u32 *in; |
e126ba97 | 1110 | int err; |
938fe83c | 1111 | bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); |
e126ba97 | 1112 | |
395a8e4c | 1113 | mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); |
e126ba97 EC |
1114 | if (!mr) |
1115 | return ERR_PTR(-ENOMEM); | |
1116 | ||
ff740aef IL |
1117 | mr->ibmr.pd = pd; |
1118 | mr->access_flags = access_flags; | |
1119 | ||
1120 | inlen = MLX5_ST_SZ_BYTES(create_mkey_in); | |
1121 | if (populate) | |
1122 | inlen += sizeof(*pas) * roundup(npages, 2); | |
1b9a07ee | 1123 | in = kvzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
1124 | if (!in) { |
1125 | err = -ENOMEM; | |
1126 | goto err_1; | |
1127 | } | |
ec22eb53 | 1128 | pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
ff740aef | 1129 | if (populate && !(access_flags & IB_ACCESS_ON_DEMAND)) |
c438fde1 AK |
1130 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, |
1131 | pg_cap ? MLX5_IB_MTT_PRESENT : 0); | |
e126ba97 | 1132 | |
ec22eb53 | 1133 | /* The pg_access bit allows setting the access flags |
cc149f75 | 1134 | * in the page list submitted with the command. */ |
ec22eb53 SM |
1135 | MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); |
1136 | ||
1137 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
ff740aef | 1138 | MLX5_SET(mkc, mkc, free, !populate); |
ec22eb53 SM |
1139 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); |
1140 | MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
1141 | MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); | |
1142 | MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); | |
1143 | MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); | |
1144 | MLX5_SET(mkc, mkc, lr, 1); | |
8b7ff7f3 | 1145 | MLX5_SET(mkc, mkc, umr_en, 1); |
ec22eb53 SM |
1146 | |
1147 | MLX5_SET64(mkc, mkc, start_addr, virt_addr); | |
1148 | MLX5_SET64(mkc, mkc, len, length); | |
1149 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1150 | MLX5_SET(mkc, mkc, bsf_octword_size, 0); | |
1151 | MLX5_SET(mkc, mkc, translations_octword_size, | |
7b4cdaae | 1152 | get_octo_len(virt_addr, length, page_shift)); |
ec22eb53 SM |
1153 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
1154 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
ff740aef IL |
1155 | if (populate) { |
1156 | MLX5_SET(create_mkey_in, in, translations_octword_actual_size, | |
7b4cdaae | 1157 | get_octo_len(virt_addr, length, page_shift)); |
ff740aef | 1158 | } |
ec22eb53 SM |
1159 | |
1160 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
1161 | if (err) { |
1162 | mlx5_ib_warn(dev, "create mkey failed\n"); | |
1163 | goto err_2; | |
1164 | } | |
aa8e08d2 | 1165 | mr->mmkey.type = MLX5_MKEY_MR; |
49780d42 | 1166 | mr->desc_size = sizeof(struct mlx5_mtt); |
7eae20db | 1167 | mr->dev = dev; |
479163f4 | 1168 | kvfree(in); |
e126ba97 | 1169 | |
a606b0f6 | 1170 | mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1171 | |
1172 | return mr; | |
1173 | ||
1174 | err_2: | |
479163f4 | 1175 | kvfree(in); |
e126ba97 EC |
1176 | |
1177 | err_1: | |
395a8e4c NO |
1178 | if (!ibmr) |
1179 | kfree(mr); | |
e126ba97 EC |
1180 | |
1181 | return ERR_PTR(err); | |
1182 | } | |
1183 | ||
395a8e4c NO |
1184 | static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, |
1185 | int npages, u64 length, int access_flags) | |
1186 | { | |
1187 | mr->npages = npages; | |
1188 | atomic_add(npages, &dev->mdev->priv.reg_pages); | |
a606b0f6 MB |
1189 | mr->ibmr.lkey = mr->mmkey.key; |
1190 | mr->ibmr.rkey = mr->mmkey.key; | |
395a8e4c | 1191 | mr->ibmr.length = length; |
56e11d62 | 1192 | mr->access_flags = access_flags; |
395a8e4c NO |
1193 | } |
1194 | ||
e126ba97 EC |
1195 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, |
1196 | u64 virt_addr, int access_flags, | |
1197 | struct ib_udata *udata) | |
1198 | { | |
1199 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1200 | struct mlx5_ib_mr *mr = NULL; | |
1201 | struct ib_umem *umem; | |
1202 | int page_shift; | |
1203 | int npages; | |
1204 | int ncont; | |
1205 | int order; | |
1206 | int err; | |
ff740aef | 1207 | bool use_umr = true; |
e126ba97 | 1208 | |
900a6d79 EC |
1209 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", |
1210 | start, virt_addr, length, access_flags); | |
81713d37 AK |
1211 | |
1212 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1213 | if (!start && length == U64_MAX) { | |
1214 | if (!(access_flags & IB_ACCESS_ON_DEMAND) || | |
1215 | !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) | |
1216 | return ERR_PTR(-EINVAL); | |
1217 | ||
1218 | mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags); | |
1219 | return &mr->ibmr; | |
1220 | } | |
1221 | #endif | |
1222 | ||
14ab8896 | 1223 | err = mr_umem_get(pd, start, length, access_flags, &umem, &npages, |
395a8e4c | 1224 | &page_shift, &ncont, &order); |
e126ba97 | 1225 | |
ff740aef | 1226 | if (err < 0) |
14ab8896 | 1227 | return ERR_PTR(err); |
e126ba97 | 1228 | |
8b7ff7f3 | 1229 | if (order <= mr_cache_max_order(dev)) { |
ff740aef IL |
1230 | mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont, |
1231 | page_shift, order, access_flags); | |
e126ba97 | 1232 | if (PTR_ERR(mr) == -EAGAIN) { |
d23a8baf | 1233 | mlx5_ib_dbg(dev, "cache empty for order %d\n", order); |
e126ba97 EC |
1234 | mr = NULL; |
1235 | } | |
ff740aef IL |
1236 | } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { |
1237 | if (access_flags & IB_ACCESS_ON_DEMAND) { | |
1238 | err = -EINVAL; | |
d23a8baf | 1239 | pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n"); |
ff740aef IL |
1240 | goto error; |
1241 | } | |
1242 | use_umr = false; | |
e126ba97 EC |
1243 | } |
1244 | ||
6bc1a656 ML |
1245 | if (!mr) { |
1246 | mutex_lock(&dev->slow_path_mutex); | |
395a8e4c | 1247 | mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, |
ff740aef | 1248 | page_shift, access_flags, !use_umr); |
6bc1a656 ML |
1249 | mutex_unlock(&dev->slow_path_mutex); |
1250 | } | |
e126ba97 EC |
1251 | |
1252 | if (IS_ERR(mr)) { | |
1253 | err = PTR_ERR(mr); | |
1254 | goto error; | |
1255 | } | |
1256 | ||
a606b0f6 | 1257 | mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1258 | |
1259 | mr->umem = umem; | |
395a8e4c | 1260 | set_mr_fileds(dev, mr, npages, length, access_flags); |
e126ba97 | 1261 | |
b4cfe447 | 1262 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
395a8e4c | 1263 | update_odp_mr(mr); |
b4cfe447 HE |
1264 | #endif |
1265 | ||
ff740aef IL |
1266 | if (use_umr) { |
1267 | int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE; | |
1268 | ||
1269 | if (access_flags & IB_ACCESS_ON_DEMAND) | |
1270 | update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP; | |
e126ba97 | 1271 | |
ff740aef IL |
1272 | err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift, |
1273 | update_xlt_flags); | |
fbcd4983 | 1274 | |
ff740aef | 1275 | if (err) { |
fbcd4983 | 1276 | dereg_mr(dev, mr); |
ff740aef IL |
1277 | return ERR_PTR(err); |
1278 | } | |
1279 | } | |
1280 | ||
1281 | mr->live = 1; | |
1282 | return &mr->ibmr; | |
e126ba97 EC |
1283 | error: |
1284 | ib_umem_release(umem); | |
1285 | return ERR_PTR(err); | |
1286 | } | |
1287 | ||
1288 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
1289 | { | |
89ea94a7 | 1290 | struct mlx5_core_dev *mdev = dev->mdev; |
0025b0bd | 1291 | struct mlx5_umr_wr umrwr = {}; |
e126ba97 | 1292 | |
89ea94a7 MG |
1293 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) |
1294 | return 0; | |
1295 | ||
7d0cc6ed AK |
1296 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR | |
1297 | MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1298 | umrwr.wr.opcode = MLX5_IB_WR_UMR; | |
1299 | umrwr.mkey = mr->mmkey.key; | |
e126ba97 | 1300 | |
d5ea2df9 | 1301 | return mlx5_ib_post_send_wait(dev, &umrwr); |
e126ba97 EC |
1302 | } |
1303 | ||
7d0cc6ed | 1304 | static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, |
56e11d62 NO |
1305 | int access_flags, int flags) |
1306 | { | |
1307 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
56e11d62 | 1308 | struct mlx5_umr_wr umrwr = {}; |
56e11d62 NO |
1309 | int err; |
1310 | ||
56e11d62 NO |
1311 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; |
1312 | ||
7d0cc6ed AK |
1313 | umrwr.wr.opcode = MLX5_IB_WR_UMR; |
1314 | umrwr.mkey = mr->mmkey.key; | |
56e11d62 | 1315 | |
31616255 | 1316 | if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) { |
56e11d62 | 1317 | umrwr.pd = pd; |
56e11d62 | 1318 | umrwr.access_flags = access_flags; |
31616255 | 1319 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; |
56e11d62 NO |
1320 | } |
1321 | ||
d5ea2df9 | 1322 | err = mlx5_ib_post_send_wait(dev, &umrwr); |
56e11d62 | 1323 | |
56e11d62 NO |
1324 | return err; |
1325 | } | |
1326 | ||
1327 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, | |
1328 | u64 length, u64 virt_addr, int new_access_flags, | |
1329 | struct ib_pd *new_pd, struct ib_udata *udata) | |
1330 | { | |
1331 | struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); | |
1332 | struct mlx5_ib_mr *mr = to_mmr(ib_mr); | |
1333 | struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; | |
1334 | int access_flags = flags & IB_MR_REREG_ACCESS ? | |
1335 | new_access_flags : | |
1336 | mr->access_flags; | |
1337 | u64 addr = (flags & IB_MR_REREG_TRANS) ? virt_addr : mr->umem->address; | |
1338 | u64 len = (flags & IB_MR_REREG_TRANS) ? length : mr->umem->length; | |
1339 | int page_shift = 0; | |
7d0cc6ed | 1340 | int upd_flags = 0; |
56e11d62 NO |
1341 | int npages = 0; |
1342 | int ncont = 0; | |
1343 | int order = 0; | |
1344 | int err; | |
1345 | ||
1346 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", | |
1347 | start, virt_addr, length, access_flags); | |
1348 | ||
7d0cc6ed AK |
1349 | atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); |
1350 | ||
56e11d62 NO |
1351 | if (flags != IB_MR_REREG_PD) { |
1352 | /* | |
1353 | * Replace umem. This needs to be done whether or not UMR is | |
1354 | * used. | |
1355 | */ | |
1356 | flags |= IB_MR_REREG_TRANS; | |
1357 | ib_umem_release(mr->umem); | |
14ab8896 AB |
1358 | err = mr_umem_get(pd, addr, len, access_flags, &mr->umem, |
1359 | &npages, &page_shift, &ncont, &order); | |
1360 | if (err < 0) { | |
fbcd4983 | 1361 | clean_mr(dev, mr); |
56e11d62 NO |
1362 | return err; |
1363 | } | |
1364 | } | |
1365 | ||
1366 | if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) { | |
1367 | /* | |
1368 | * UMR can't be used - MKey needs to be replaced. | |
1369 | */ | |
8b7ff7f3 | 1370 | if (mr->allocated_from_cache) { |
56e11d62 NO |
1371 | err = unreg_umr(dev, mr); |
1372 | if (err) | |
1373 | mlx5_ib_warn(dev, "Failed to unregister MR\n"); | |
1374 | } else { | |
1375 | err = destroy_mkey(dev, mr); | |
1376 | if (err) | |
1377 | mlx5_ib_warn(dev, "Failed to destroy MKey\n"); | |
1378 | } | |
1379 | if (err) | |
1380 | return err; | |
1381 | ||
1382 | mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, | |
ff740aef | 1383 | page_shift, access_flags, true); |
56e11d62 NO |
1384 | |
1385 | if (IS_ERR(mr)) | |
1386 | return PTR_ERR(mr); | |
1387 | ||
8b7ff7f3 | 1388 | mr->allocated_from_cache = 0; |
ff740aef | 1389 | mr->live = 1; |
56e11d62 NO |
1390 | } else { |
1391 | /* | |
1392 | * Send a UMR WQE | |
1393 | */ | |
7d0cc6ed AK |
1394 | mr->ibmr.pd = pd; |
1395 | mr->access_flags = access_flags; | |
1396 | mr->mmkey.iova = addr; | |
1397 | mr->mmkey.size = len; | |
1398 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
1399 | ||
1400 | if (flags & IB_MR_REREG_TRANS) { | |
1401 | upd_flags = MLX5_IB_UPD_XLT_ADDR; | |
1402 | if (flags & IB_MR_REREG_PD) | |
1403 | upd_flags |= MLX5_IB_UPD_XLT_PD; | |
1404 | if (flags & IB_MR_REREG_ACCESS) | |
1405 | upd_flags |= MLX5_IB_UPD_XLT_ACCESS; | |
1406 | err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, | |
1407 | upd_flags); | |
1408 | } else { | |
1409 | err = rereg_umr(pd, mr, access_flags, flags); | |
1410 | } | |
1411 | ||
56e11d62 NO |
1412 | if (err) { |
1413 | mlx5_ib_warn(dev, "Failed to rereg UMR\n"); | |
7d0cc6ed | 1414 | ib_umem_release(mr->umem); |
fbcd4983 | 1415 | clean_mr(dev, mr); |
56e11d62 NO |
1416 | return err; |
1417 | } | |
1418 | } | |
1419 | ||
7d0cc6ed | 1420 | set_mr_fileds(dev, mr, npages, len, access_flags); |
56e11d62 | 1421 | |
56e11d62 NO |
1422 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1423 | update_odp_mr(mr); | |
1424 | #endif | |
56e11d62 NO |
1425 | return 0; |
1426 | } | |
1427 | ||
8a187ee5 SG |
1428 | static int |
1429 | mlx5_alloc_priv_descs(struct ib_device *device, | |
1430 | struct mlx5_ib_mr *mr, | |
1431 | int ndescs, | |
1432 | int desc_size) | |
1433 | { | |
1434 | int size = ndescs * desc_size; | |
1435 | int add_size; | |
1436 | int ret; | |
1437 | ||
1438 | add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); | |
1439 | ||
1440 | mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); | |
1441 | if (!mr->descs_alloc) | |
1442 | return -ENOMEM; | |
1443 | ||
1444 | mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); | |
1445 | ||
9b0c289e | 1446 | mr->desc_map = dma_map_single(device->dev.parent, mr->descs, |
8a187ee5 | 1447 | size, DMA_TO_DEVICE); |
9b0c289e | 1448 | if (dma_mapping_error(device->dev.parent, mr->desc_map)) { |
8a187ee5 SG |
1449 | ret = -ENOMEM; |
1450 | goto err; | |
1451 | } | |
1452 | ||
1453 | return 0; | |
1454 | err: | |
1455 | kfree(mr->descs_alloc); | |
1456 | ||
1457 | return ret; | |
1458 | } | |
1459 | ||
1460 | static void | |
1461 | mlx5_free_priv_descs(struct mlx5_ib_mr *mr) | |
1462 | { | |
1463 | if (mr->descs) { | |
1464 | struct ib_device *device = mr->ibmr.device; | |
1465 | int size = mr->max_descs * mr->desc_size; | |
1466 | ||
9b0c289e | 1467 | dma_unmap_single(device->dev.parent, mr->desc_map, |
8a187ee5 SG |
1468 | size, DMA_TO_DEVICE); |
1469 | kfree(mr->descs_alloc); | |
1470 | mr->descs = NULL; | |
1471 | } | |
1472 | } | |
1473 | ||
fbcd4983 | 1474 | static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 | 1475 | { |
8b7ff7f3 | 1476 | int allocated_from_cache = mr->allocated_from_cache; |
e126ba97 EC |
1477 | int err; |
1478 | ||
8b91ffc1 SG |
1479 | if (mr->sig) { |
1480 | if (mlx5_core_destroy_psv(dev->mdev, | |
1481 | mr->sig->psv_memory.psv_idx)) | |
1482 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1483 | mr->sig->psv_memory.psv_idx); | |
1484 | if (mlx5_core_destroy_psv(dev->mdev, | |
1485 | mr->sig->psv_wire.psv_idx)) | |
1486 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1487 | mr->sig->psv_wire.psv_idx); | |
1488 | kfree(mr->sig); | |
1489 | mr->sig = NULL; | |
1490 | } | |
1491 | ||
8a187ee5 SG |
1492 | mlx5_free_priv_descs(mr); |
1493 | ||
8b7ff7f3 | 1494 | if (!allocated_from_cache) { |
5942d8ae KH |
1495 | u32 key = mr->mmkey.key; |
1496 | ||
b4cfe447 | 1497 | err = destroy_mkey(dev, mr); |
5942d8ae | 1498 | kfree(mr); |
e126ba97 EC |
1499 | if (err) { |
1500 | mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n", | |
5942d8ae | 1501 | key, err); |
e126ba97 EC |
1502 | return err; |
1503 | } | |
1504 | } else { | |
49780d42 | 1505 | mlx5_mr_cache_free(dev, mr); |
e126ba97 EC |
1506 | } |
1507 | ||
6aec21f6 HE |
1508 | return 0; |
1509 | } | |
1510 | ||
fbcd4983 | 1511 | static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
6aec21f6 | 1512 | { |
6aec21f6 HE |
1513 | int npages = mr->npages; |
1514 | struct ib_umem *umem = mr->umem; | |
1515 | ||
1516 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
b4cfe447 HE |
1517 | if (umem && umem->odp_data) { |
1518 | /* Prevent new page faults from succeeding */ | |
1519 | mr->live = 0; | |
6aec21f6 HE |
1520 | /* Wait for all running page-fault handlers to finish. */ |
1521 | synchronize_srcu(&dev->mr_srcu); | |
b4cfe447 | 1522 | /* Destroy all page mappings */ |
81713d37 AK |
1523 | if (umem->odp_data->page_list) |
1524 | mlx5_ib_invalidate_range(umem, ib_umem_start(umem), | |
1525 | ib_umem_end(umem)); | |
1526 | else | |
1527 | mlx5_ib_free_implicit_mr(mr); | |
b4cfe447 HE |
1528 | /* |
1529 | * We kill the umem before the MR for ODP, | |
1530 | * so that there will not be any invalidations in | |
1531 | * flight, looking at the *mr struct. | |
1532 | */ | |
1533 | ib_umem_release(umem); | |
1534 | atomic_sub(npages, &dev->mdev->priv.reg_pages); | |
1535 | ||
1536 | /* Avoid double-freeing the umem. */ | |
1537 | umem = NULL; | |
1538 | } | |
6aec21f6 HE |
1539 | #endif |
1540 | ||
fbcd4983 | 1541 | clean_mr(dev, mr); |
6aec21f6 | 1542 | |
e126ba97 EC |
1543 | if (umem) { |
1544 | ib_umem_release(umem); | |
6aec21f6 | 1545 | atomic_sub(npages, &dev->mdev->priv.reg_pages); |
e126ba97 EC |
1546 | } |
1547 | ||
e126ba97 EC |
1548 | return 0; |
1549 | } | |
1550 | ||
fbcd4983 IL |
1551 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr) |
1552 | { | |
1553 | struct mlx5_ib_dev *dev = to_mdev(ibmr->device); | |
1554 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1555 | ||
1556 | return dereg_mr(dev, mr); | |
1557 | } | |
1558 | ||
9bee178b SG |
1559 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
1560 | enum ib_mr_type mr_type, | |
1561 | u32 max_num_sg) | |
3121e3c4 SG |
1562 | { |
1563 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1564 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
b005d316 | 1565 | int ndescs = ALIGN(max_num_sg, 4); |
ec22eb53 SM |
1566 | struct mlx5_ib_mr *mr; |
1567 | void *mkc; | |
1568 | u32 *in; | |
b005d316 | 1569 | int err; |
3121e3c4 SG |
1570 | |
1571 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1572 | if (!mr) | |
1573 | return ERR_PTR(-ENOMEM); | |
1574 | ||
ec22eb53 | 1575 | in = kzalloc(inlen, GFP_KERNEL); |
3121e3c4 SG |
1576 | if (!in) { |
1577 | err = -ENOMEM; | |
1578 | goto err_free; | |
1579 | } | |
1580 | ||
ec22eb53 SM |
1581 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1582 | MLX5_SET(mkc, mkc, free, 1); | |
1583 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1584 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1585 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
3121e3c4 | 1586 | |
9bee178b | 1587 | if (mr_type == IB_MR_TYPE_MEM_REG) { |
ec22eb53 SM |
1588 | mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT; |
1589 | MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); | |
8a187ee5 | 1590 | err = mlx5_alloc_priv_descs(pd->device, mr, |
31616255 | 1591 | ndescs, sizeof(struct mlx5_mtt)); |
8a187ee5 SG |
1592 | if (err) |
1593 | goto err_free_in; | |
1594 | ||
31616255 | 1595 | mr->desc_size = sizeof(struct mlx5_mtt); |
8a187ee5 | 1596 | mr->max_descs = ndescs; |
b005d316 | 1597 | } else if (mr_type == IB_MR_TYPE_SG_GAPS) { |
ec22eb53 | 1598 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
b005d316 SG |
1599 | |
1600 | err = mlx5_alloc_priv_descs(pd->device, mr, | |
1601 | ndescs, sizeof(struct mlx5_klm)); | |
1602 | if (err) | |
1603 | goto err_free_in; | |
1604 | mr->desc_size = sizeof(struct mlx5_klm); | |
1605 | mr->max_descs = ndescs; | |
9bee178b | 1606 | } else if (mr_type == IB_MR_TYPE_SIGNATURE) { |
3121e3c4 SG |
1607 | u32 psv_index[2]; |
1608 | ||
ec22eb53 SM |
1609 | MLX5_SET(mkc, mkc, bsf_en, 1); |
1610 | MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); | |
3121e3c4 SG |
1611 | mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); |
1612 | if (!mr->sig) { | |
1613 | err = -ENOMEM; | |
1614 | goto err_free_in; | |
1615 | } | |
1616 | ||
1617 | /* create mem & wire PSVs */ | |
9603b61d | 1618 | err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, |
3121e3c4 SG |
1619 | 2, psv_index); |
1620 | if (err) | |
1621 | goto err_free_sig; | |
1622 | ||
ec22eb53 | 1623 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
3121e3c4 SG |
1624 | mr->sig->psv_memory.psv_idx = psv_index[0]; |
1625 | mr->sig->psv_wire.psv_idx = psv_index[1]; | |
d5436ba0 SG |
1626 | |
1627 | mr->sig->sig_status_checked = true; | |
1628 | mr->sig->sig_err_exists = false; | |
1629 | /* Next UMR, Arm SIGERR */ | |
1630 | ++mr->sig->sigerr_count; | |
9bee178b SG |
1631 | } else { |
1632 | mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); | |
1633 | err = -EINVAL; | |
1634 | goto err_free_in; | |
3121e3c4 SG |
1635 | } |
1636 | ||
ec22eb53 SM |
1637 | MLX5_SET(mkc, mkc, access_mode, mr->access_mode); |
1638 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1639 | ||
1640 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
3121e3c4 SG |
1641 | if (err) |
1642 | goto err_destroy_psv; | |
1643 | ||
aa8e08d2 | 1644 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
1645 | mr->ibmr.lkey = mr->mmkey.key; |
1646 | mr->ibmr.rkey = mr->mmkey.key; | |
3121e3c4 SG |
1647 | mr->umem = NULL; |
1648 | kfree(in); | |
1649 | ||
1650 | return &mr->ibmr; | |
1651 | ||
1652 | err_destroy_psv: | |
1653 | if (mr->sig) { | |
9603b61d | 1654 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1655 | mr->sig->psv_memory.psv_idx)) |
1656 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1657 | mr->sig->psv_memory.psv_idx); | |
9603b61d | 1658 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1659 | mr->sig->psv_wire.psv_idx)) |
1660 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1661 | mr->sig->psv_wire.psv_idx); | |
1662 | } | |
8a187ee5 | 1663 | mlx5_free_priv_descs(mr); |
3121e3c4 SG |
1664 | err_free_sig: |
1665 | kfree(mr->sig); | |
1666 | err_free_in: | |
1667 | kfree(in); | |
1668 | err_free: | |
1669 | kfree(mr); | |
1670 | return ERR_PTR(err); | |
1671 | } | |
1672 | ||
d2370e0a MB |
1673 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
1674 | struct ib_udata *udata) | |
1675 | { | |
1676 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1677 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
d2370e0a | 1678 | struct mlx5_ib_mw *mw = NULL; |
ec22eb53 SM |
1679 | u32 *in = NULL; |
1680 | void *mkc; | |
d2370e0a MB |
1681 | int ndescs; |
1682 | int err; | |
1683 | struct mlx5_ib_alloc_mw req = {}; | |
1684 | struct { | |
1685 | __u32 comp_mask; | |
1686 | __u32 response_length; | |
1687 | } resp = {}; | |
1688 | ||
1689 | err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); | |
1690 | if (err) | |
1691 | return ERR_PTR(err); | |
1692 | ||
1693 | if (req.comp_mask || req.reserved1 || req.reserved2) | |
1694 | return ERR_PTR(-EOPNOTSUPP); | |
1695 | ||
1696 | if (udata->inlen > sizeof(req) && | |
1697 | !ib_is_udata_cleared(udata, sizeof(req), | |
1698 | udata->inlen - sizeof(req))) | |
1699 | return ERR_PTR(-EOPNOTSUPP); | |
1700 | ||
1701 | ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); | |
1702 | ||
1703 | mw = kzalloc(sizeof(*mw), GFP_KERNEL); | |
ec22eb53 | 1704 | in = kzalloc(inlen, GFP_KERNEL); |
d2370e0a MB |
1705 | if (!mw || !in) { |
1706 | err = -ENOMEM; | |
1707 | goto free; | |
1708 | } | |
1709 | ||
ec22eb53 SM |
1710 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1711 | ||
1712 | MLX5_SET(mkc, mkc, free, 1); | |
1713 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1714 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1715 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1716 | MLX5_SET(mkc, mkc, lr, 1); | |
1717 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS); | |
1718 | MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); | |
1719 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1720 | ||
1721 | err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen); | |
d2370e0a MB |
1722 | if (err) |
1723 | goto free; | |
1724 | ||
aa8e08d2 | 1725 | mw->mmkey.type = MLX5_MKEY_MW; |
d2370e0a | 1726 | mw->ibmw.rkey = mw->mmkey.key; |
db570d7d | 1727 | mw->ndescs = ndescs; |
d2370e0a MB |
1728 | |
1729 | resp.response_length = min(offsetof(typeof(resp), response_length) + | |
1730 | sizeof(resp.response_length), udata->outlen); | |
1731 | if (resp.response_length) { | |
1732 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
1733 | if (err) { | |
1734 | mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); | |
1735 | goto free; | |
1736 | } | |
1737 | } | |
1738 | ||
1739 | kfree(in); | |
1740 | return &mw->ibmw; | |
1741 | ||
1742 | free: | |
1743 | kfree(mw); | |
1744 | kfree(in); | |
1745 | return ERR_PTR(err); | |
1746 | } | |
1747 | ||
1748 | int mlx5_ib_dealloc_mw(struct ib_mw *mw) | |
1749 | { | |
1750 | struct mlx5_ib_mw *mmw = to_mmw(mw); | |
1751 | int err; | |
1752 | ||
1753 | err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev, | |
1754 | &mmw->mmkey); | |
1755 | if (!err) | |
1756 | kfree(mmw); | |
1757 | return err; | |
1758 | } | |
1759 | ||
d5436ba0 SG |
1760 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
1761 | struct ib_mr_status *mr_status) | |
1762 | { | |
1763 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); | |
1764 | int ret = 0; | |
1765 | ||
1766 | if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { | |
1767 | pr_err("Invalid status check mask\n"); | |
1768 | ret = -EINVAL; | |
1769 | goto done; | |
1770 | } | |
1771 | ||
1772 | mr_status->fail_status = 0; | |
1773 | if (check_mask & IB_MR_CHECK_SIG_STATUS) { | |
1774 | if (!mmr->sig) { | |
1775 | ret = -EINVAL; | |
1776 | pr_err("signature status check requested on a non-signature enabled MR\n"); | |
1777 | goto done; | |
1778 | } | |
1779 | ||
1780 | mmr->sig->sig_status_checked = true; | |
1781 | if (!mmr->sig->sig_err_exists) | |
1782 | goto done; | |
1783 | ||
1784 | if (ibmr->lkey == mmr->sig->err_item.key) | |
1785 | memcpy(&mr_status->sig_err, &mmr->sig->err_item, | |
1786 | sizeof(mr_status->sig_err)); | |
1787 | else { | |
1788 | mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; | |
1789 | mr_status->sig_err.sig_err_offset = 0; | |
1790 | mr_status->sig_err.key = mmr->sig->err_item.key; | |
1791 | } | |
1792 | ||
1793 | mmr->sig->sig_err_exists = false; | |
1794 | mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; | |
1795 | } | |
1796 | ||
1797 | done: | |
1798 | return ret; | |
1799 | } | |
8a187ee5 | 1800 | |
b005d316 SG |
1801 | static int |
1802 | mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, | |
1803 | struct scatterlist *sgl, | |
ff2ba993 | 1804 | unsigned short sg_nents, |
9aa8b321 | 1805 | unsigned int *sg_offset_p) |
b005d316 SG |
1806 | { |
1807 | struct scatterlist *sg = sgl; | |
1808 | struct mlx5_klm *klms = mr->descs; | |
9aa8b321 | 1809 | unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; |
b005d316 SG |
1810 | u32 lkey = mr->ibmr.pd->local_dma_lkey; |
1811 | int i; | |
1812 | ||
ff2ba993 | 1813 | mr->ibmr.iova = sg_dma_address(sg) + sg_offset; |
b005d316 SG |
1814 | mr->ibmr.length = 0; |
1815 | mr->ndescs = sg_nents; | |
1816 | ||
1817 | for_each_sg(sgl, sg, sg_nents, i) { | |
99975cd4 | 1818 | if (unlikely(i >= mr->max_descs)) |
b005d316 | 1819 | break; |
ff2ba993 CH |
1820 | klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); |
1821 | klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); | |
b005d316 | 1822 | klms[i].key = cpu_to_be32(lkey); |
0a49f2c3 | 1823 | mr->ibmr.length += sg_dma_len(sg) - sg_offset; |
ff2ba993 CH |
1824 | |
1825 | sg_offset = 0; | |
b005d316 SG |
1826 | } |
1827 | ||
9aa8b321 BVA |
1828 | if (sg_offset_p) |
1829 | *sg_offset_p = sg_offset; | |
1830 | ||
b005d316 SG |
1831 | return i; |
1832 | } | |
1833 | ||
8a187ee5 SG |
1834 | static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) |
1835 | { | |
1836 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1837 | __be64 *descs; | |
1838 | ||
1839 | if (unlikely(mr->ndescs == mr->max_descs)) | |
1840 | return -ENOMEM; | |
1841 | ||
1842 | descs = mr->descs; | |
1843 | descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); | |
1844 | ||
1845 | return 0; | |
1846 | } | |
1847 | ||
ff2ba993 | 1848 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 1849 | unsigned int *sg_offset) |
8a187ee5 SG |
1850 | { |
1851 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1852 | int n; | |
1853 | ||
1854 | mr->ndescs = 0; | |
1855 | ||
1856 | ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, | |
1857 | mr->desc_size * mr->max_descs, | |
1858 | DMA_TO_DEVICE); | |
1859 | ||
ec22eb53 | 1860 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
ff2ba993 | 1861 | n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset); |
b005d316 | 1862 | else |
ff2ba993 CH |
1863 | n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, |
1864 | mlx5_set_page); | |
8a187ee5 SG |
1865 | |
1866 | ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, | |
1867 | mr->desc_size * mr->max_descs, | |
1868 | DMA_TO_DEVICE); | |
1869 | ||
1870 | return n; | |
1871 | } |