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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | ||
34 | #include <linux/kref.h> | |
35 | #include <linux/random.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/export.h> | |
746b5583 | 38 | #include <linux/delay.h> |
e126ba97 | 39 | #include <rdma/ib_umem.h> |
b4cfe447 | 40 | #include <rdma/ib_umem_odp.h> |
968e78dd | 41 | #include <rdma/ib_verbs.h> |
e126ba97 EC |
42 | #include "mlx5_ib.h" |
43 | ||
44 | enum { | |
746b5583 | 45 | MAX_PENDING_REG_MR = 8, |
e126ba97 EC |
46 | }; |
47 | ||
832a6b06 | 48 | #define MLX5_UMR_ALIGN 2048 |
fe45f827 | 49 | |
6aec21f6 | 50 | static int clean_mr(struct mlx5_ib_mr *mr); |
7d0cc6ed | 51 | static int use_umr(struct mlx5_ib_dev *dev, int order); |
49780d42 | 52 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); |
6aec21f6 | 53 | |
b4cfe447 HE |
54 | static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
55 | { | |
a606b0f6 | 56 | int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey); |
b4cfe447 HE |
57 | |
58 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
59 | /* Wait until all page fault handlers using the mr complete. */ | |
60 | synchronize_srcu(&dev->mr_srcu); | |
61 | #endif | |
62 | ||
63 | return err; | |
64 | } | |
65 | ||
e126ba97 EC |
66 | static int order2idx(struct mlx5_ib_dev *dev, int order) |
67 | { | |
68 | struct mlx5_mr_cache *cache = &dev->cache; | |
69 | ||
70 | if (order < cache->ent[0].order) | |
71 | return 0; | |
72 | else | |
73 | return order - cache->ent[0].order; | |
74 | } | |
75 | ||
56e11d62 NO |
76 | static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length) |
77 | { | |
78 | return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >= | |
79 | length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1)); | |
80 | } | |
81 | ||
395a8e4c NO |
82 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
83 | static void update_odp_mr(struct mlx5_ib_mr *mr) | |
84 | { | |
85 | if (mr->umem->odp_data) { | |
86 | /* | |
87 | * This barrier prevents the compiler from moving the | |
88 | * setting of umem->odp_data->private to point to our | |
89 | * MR, before reg_umr finished, to ensure that the MR | |
90 | * initialization have finished before starting to | |
91 | * handle invalidations. | |
92 | */ | |
93 | smp_wmb(); | |
94 | mr->umem->odp_data->private = mr; | |
95 | /* | |
96 | * Make sure we will see the new | |
97 | * umem->odp_data->private value in the invalidation | |
98 | * routines, before we can get page faults on the | |
99 | * MR. Page faults can happen once we put the MR in | |
100 | * the tree, below this line. Without the barrier, | |
101 | * there can be a fault handling and an invalidation | |
102 | * before umem->odp_data->private == mr is visible to | |
103 | * the invalidation handler. | |
104 | */ | |
105 | smp_wmb(); | |
106 | } | |
107 | } | |
108 | #endif | |
109 | ||
746b5583 EC |
110 | static void reg_mr_callback(int status, void *context) |
111 | { | |
112 | struct mlx5_ib_mr *mr = context; | |
113 | struct mlx5_ib_dev *dev = mr->dev; | |
114 | struct mlx5_mr_cache *cache = &dev->cache; | |
115 | int c = order2idx(dev, mr->order); | |
116 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
117 | u8 key; | |
746b5583 | 118 | unsigned long flags; |
a606b0f6 | 119 | struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table; |
8605933a | 120 | int err; |
746b5583 | 121 | |
746b5583 EC |
122 | spin_lock_irqsave(&ent->lock, flags); |
123 | ent->pending--; | |
124 | spin_unlock_irqrestore(&ent->lock, flags); | |
125 | if (status) { | |
126 | mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status); | |
127 | kfree(mr); | |
128 | dev->fill_delay = 1; | |
129 | mod_timer(&dev->delay_timer, jiffies + HZ); | |
130 | return; | |
131 | } | |
132 | ||
aa8e08d2 | 133 | mr->mmkey.type = MLX5_MKEY_MR; |
9603b61d JM |
134 | spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags); |
135 | key = dev->mdev->priv.mkey_key++; | |
136 | spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags); | |
ec22eb53 | 137 | mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key; |
746b5583 EC |
138 | |
139 | cache->last_add = jiffies; | |
140 | ||
141 | spin_lock_irqsave(&ent->lock, flags); | |
142 | list_add_tail(&mr->list, &ent->head); | |
143 | ent->cur++; | |
144 | ent->size++; | |
145 | spin_unlock_irqrestore(&ent->lock, flags); | |
8605933a HE |
146 | |
147 | write_lock_irqsave(&table->lock, flags); | |
a606b0f6 MB |
148 | err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key), |
149 | &mr->mmkey); | |
8605933a | 150 | if (err) |
a606b0f6 | 151 | pr_err("Error inserting to mkey tree. 0x%x\n", -err); |
8605933a | 152 | write_unlock_irqrestore(&table->lock, flags); |
49780d42 AK |
153 | |
154 | if (!completion_done(&ent->compl)) | |
155 | complete(&ent->compl); | |
746b5583 EC |
156 | } |
157 | ||
e126ba97 EC |
158 | static int add_keys(struct mlx5_ib_dev *dev, int c, int num) |
159 | { | |
e126ba97 EC |
160 | struct mlx5_mr_cache *cache = &dev->cache; |
161 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
ec22eb53 | 162 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
e126ba97 | 163 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
164 | void *mkc; |
165 | u32 *in; | |
e126ba97 EC |
166 | int err = 0; |
167 | int i; | |
168 | ||
ec22eb53 | 169 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
170 | if (!in) |
171 | return -ENOMEM; | |
172 | ||
ec22eb53 | 173 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
e126ba97 | 174 | for (i = 0; i < num; i++) { |
746b5583 EC |
175 | if (ent->pending >= MAX_PENDING_REG_MR) { |
176 | err = -EAGAIN; | |
177 | break; | |
178 | } | |
179 | ||
e126ba97 EC |
180 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); |
181 | if (!mr) { | |
182 | err = -ENOMEM; | |
746b5583 | 183 | break; |
e126ba97 EC |
184 | } |
185 | mr->order = ent->order; | |
186 | mr->umred = 1; | |
746b5583 | 187 | mr->dev = dev; |
ec22eb53 SM |
188 | |
189 | MLX5_SET(mkc, mkc, free, 1); | |
190 | MLX5_SET(mkc, mkc, umr_en, 1); | |
49780d42 | 191 | MLX5_SET(mkc, mkc, access_mode, ent->access_mode); |
ec22eb53 SM |
192 | |
193 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
49780d42 AK |
194 | MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt); |
195 | MLX5_SET(mkc, mkc, log_page_size, ent->page); | |
e126ba97 | 196 | |
746b5583 EC |
197 | spin_lock_irq(&ent->lock); |
198 | ent->pending++; | |
199 | spin_unlock_irq(&ent->lock); | |
ec22eb53 SM |
200 | err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey, |
201 | in, inlen, | |
202 | mr->out, sizeof(mr->out), | |
203 | reg_mr_callback, mr); | |
e126ba97 | 204 | if (err) { |
d14e7110 EC |
205 | spin_lock_irq(&ent->lock); |
206 | ent->pending--; | |
207 | spin_unlock_irq(&ent->lock); | |
e126ba97 | 208 | mlx5_ib_warn(dev, "create mkey failed %d\n", err); |
e126ba97 | 209 | kfree(mr); |
746b5583 | 210 | break; |
e126ba97 | 211 | } |
e126ba97 EC |
212 | } |
213 | ||
e126ba97 EC |
214 | kfree(in); |
215 | return err; | |
216 | } | |
217 | ||
218 | static void remove_keys(struct mlx5_ib_dev *dev, int c, int num) | |
219 | { | |
e126ba97 EC |
220 | struct mlx5_mr_cache *cache = &dev->cache; |
221 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
222 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
223 | int err; |
224 | int i; | |
225 | ||
226 | for (i = 0; i < num; i++) { | |
746b5583 | 227 | spin_lock_irq(&ent->lock); |
e126ba97 | 228 | if (list_empty(&ent->head)) { |
746b5583 | 229 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
230 | return; |
231 | } | |
232 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
233 | list_del(&mr->list); | |
234 | ent->cur--; | |
235 | ent->size--; | |
746b5583 | 236 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 237 | err = destroy_mkey(dev, mr); |
203099fd | 238 | if (err) |
e126ba97 | 239 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 240 | else |
e126ba97 | 241 | kfree(mr); |
e126ba97 EC |
242 | } |
243 | } | |
244 | ||
245 | static ssize_t size_write(struct file *filp, const char __user *buf, | |
246 | size_t count, loff_t *pos) | |
247 | { | |
248 | struct mlx5_cache_ent *ent = filp->private_data; | |
249 | struct mlx5_ib_dev *dev = ent->dev; | |
250 | char lbuf[20]; | |
251 | u32 var; | |
252 | int err; | |
253 | int c; | |
254 | ||
255 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 256 | return -EFAULT; |
e126ba97 EC |
257 | |
258 | c = order2idx(dev, ent->order); | |
259 | lbuf[sizeof(lbuf) - 1] = 0; | |
260 | ||
261 | if (sscanf(lbuf, "%u", &var) != 1) | |
262 | return -EINVAL; | |
263 | ||
264 | if (var < ent->limit) | |
265 | return -EINVAL; | |
266 | ||
267 | if (var > ent->size) { | |
746b5583 EC |
268 | do { |
269 | err = add_keys(dev, c, var - ent->size); | |
270 | if (err && err != -EAGAIN) | |
271 | return err; | |
272 | ||
273 | usleep_range(3000, 5000); | |
274 | } while (err); | |
e126ba97 EC |
275 | } else if (var < ent->size) { |
276 | remove_keys(dev, c, ent->size - var); | |
277 | } | |
278 | ||
279 | return count; | |
280 | } | |
281 | ||
282 | static ssize_t size_read(struct file *filp, char __user *buf, size_t count, | |
283 | loff_t *pos) | |
284 | { | |
285 | struct mlx5_cache_ent *ent = filp->private_data; | |
286 | char lbuf[20]; | |
287 | int err; | |
288 | ||
289 | if (*pos) | |
290 | return 0; | |
291 | ||
292 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size); | |
293 | if (err < 0) | |
294 | return err; | |
295 | ||
296 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 297 | return -EFAULT; |
e126ba97 EC |
298 | |
299 | *pos += err; | |
300 | ||
301 | return err; | |
302 | } | |
303 | ||
304 | static const struct file_operations size_fops = { | |
305 | .owner = THIS_MODULE, | |
306 | .open = simple_open, | |
307 | .write = size_write, | |
308 | .read = size_read, | |
309 | }; | |
310 | ||
311 | static ssize_t limit_write(struct file *filp, const char __user *buf, | |
312 | size_t count, loff_t *pos) | |
313 | { | |
314 | struct mlx5_cache_ent *ent = filp->private_data; | |
315 | struct mlx5_ib_dev *dev = ent->dev; | |
316 | char lbuf[20]; | |
317 | u32 var; | |
318 | int err; | |
319 | int c; | |
320 | ||
321 | if (copy_from_user(lbuf, buf, sizeof(lbuf))) | |
5e631a03 | 322 | return -EFAULT; |
e126ba97 EC |
323 | |
324 | c = order2idx(dev, ent->order); | |
325 | lbuf[sizeof(lbuf) - 1] = 0; | |
326 | ||
327 | if (sscanf(lbuf, "%u", &var) != 1) | |
328 | return -EINVAL; | |
329 | ||
330 | if (var > ent->size) | |
331 | return -EINVAL; | |
332 | ||
333 | ent->limit = var; | |
334 | ||
335 | if (ent->cur < ent->limit) { | |
336 | err = add_keys(dev, c, 2 * ent->limit - ent->cur); | |
337 | if (err) | |
338 | return err; | |
339 | } | |
340 | ||
341 | return count; | |
342 | } | |
343 | ||
344 | static ssize_t limit_read(struct file *filp, char __user *buf, size_t count, | |
345 | loff_t *pos) | |
346 | { | |
347 | struct mlx5_cache_ent *ent = filp->private_data; | |
348 | char lbuf[20]; | |
349 | int err; | |
350 | ||
351 | if (*pos) | |
352 | return 0; | |
353 | ||
354 | err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit); | |
355 | if (err < 0) | |
356 | return err; | |
357 | ||
358 | if (copy_to_user(buf, lbuf, err)) | |
5e631a03 | 359 | return -EFAULT; |
e126ba97 EC |
360 | |
361 | *pos += err; | |
362 | ||
363 | return err; | |
364 | } | |
365 | ||
366 | static const struct file_operations limit_fops = { | |
367 | .owner = THIS_MODULE, | |
368 | .open = simple_open, | |
369 | .write = limit_write, | |
370 | .read = limit_read, | |
371 | }; | |
372 | ||
373 | static int someone_adding(struct mlx5_mr_cache *cache) | |
374 | { | |
375 | int i; | |
376 | ||
377 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
378 | if (cache->ent[i].cur < cache->ent[i].limit) | |
379 | return 1; | |
380 | } | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | static void __cache_work_func(struct mlx5_cache_ent *ent) | |
386 | { | |
387 | struct mlx5_ib_dev *dev = ent->dev; | |
388 | struct mlx5_mr_cache *cache = &dev->cache; | |
389 | int i = order2idx(dev, ent->order); | |
746b5583 | 390 | int err; |
e126ba97 EC |
391 | |
392 | if (cache->stopped) | |
393 | return; | |
394 | ||
395 | ent = &dev->cache.ent[i]; | |
746b5583 EC |
396 | if (ent->cur < 2 * ent->limit && !dev->fill_delay) { |
397 | err = add_keys(dev, i, 1); | |
398 | if (ent->cur < 2 * ent->limit) { | |
399 | if (err == -EAGAIN) { | |
400 | mlx5_ib_dbg(dev, "returned eagain, order %d\n", | |
401 | i + 2); | |
402 | queue_delayed_work(cache->wq, &ent->dwork, | |
403 | msecs_to_jiffies(3)); | |
404 | } else if (err) { | |
405 | mlx5_ib_warn(dev, "command failed order %d, err %d\n", | |
406 | i + 2, err); | |
407 | queue_delayed_work(cache->wq, &ent->dwork, | |
408 | msecs_to_jiffies(1000)); | |
409 | } else { | |
410 | queue_work(cache->wq, &ent->work); | |
411 | } | |
412 | } | |
e126ba97 | 413 | } else if (ent->cur > 2 * ent->limit) { |
ab5cdc31 LR |
414 | /* |
415 | * The remove_keys() logic is performed as garbage collection | |
416 | * task. Such task is intended to be run when no other active | |
417 | * processes are running. | |
418 | * | |
419 | * The need_resched() will return TRUE if there are user tasks | |
420 | * to be activated in near future. | |
421 | * | |
422 | * In such case, we don't execute remove_keys() and postpone | |
423 | * the garbage collection work to try to run in next cycle, | |
424 | * in order to free CPU resources to other tasks. | |
425 | */ | |
426 | if (!need_resched() && !someone_adding(cache) && | |
746b5583 | 427 | time_after(jiffies, cache->last_add + 300 * HZ)) { |
e126ba97 EC |
428 | remove_keys(dev, i, 1); |
429 | if (ent->cur > ent->limit) | |
430 | queue_work(cache->wq, &ent->work); | |
431 | } else { | |
746b5583 | 432 | queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ); |
e126ba97 EC |
433 | } |
434 | } | |
435 | } | |
436 | ||
437 | static void delayed_cache_work_func(struct work_struct *work) | |
438 | { | |
439 | struct mlx5_cache_ent *ent; | |
440 | ||
441 | ent = container_of(work, struct mlx5_cache_ent, dwork.work); | |
442 | __cache_work_func(ent); | |
443 | } | |
444 | ||
445 | static void cache_work_func(struct work_struct *work) | |
446 | { | |
447 | struct mlx5_cache_ent *ent; | |
448 | ||
449 | ent = container_of(work, struct mlx5_cache_ent, work); | |
450 | __cache_work_func(ent); | |
451 | } | |
452 | ||
49780d42 AK |
453 | struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry) |
454 | { | |
455 | struct mlx5_mr_cache *cache = &dev->cache; | |
456 | struct mlx5_cache_ent *ent; | |
457 | struct mlx5_ib_mr *mr; | |
458 | int err; | |
459 | ||
460 | if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) { | |
461 | mlx5_ib_err(dev, "cache entry %d is out of range\n", entry); | |
462 | return NULL; | |
463 | } | |
464 | ||
465 | ent = &cache->ent[entry]; | |
466 | while (1) { | |
467 | spin_lock_irq(&ent->lock); | |
468 | if (list_empty(&ent->head)) { | |
469 | spin_unlock_irq(&ent->lock); | |
470 | ||
471 | err = add_keys(dev, entry, 1); | |
81713d37 | 472 | if (err && err != -EAGAIN) |
49780d42 AK |
473 | return ERR_PTR(err); |
474 | ||
475 | wait_for_completion(&ent->compl); | |
476 | } else { | |
477 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
478 | list); | |
479 | list_del(&mr->list); | |
480 | ent->cur--; | |
481 | spin_unlock_irq(&ent->lock); | |
482 | if (ent->cur < ent->limit) | |
483 | queue_work(cache->wq, &ent->work); | |
484 | return mr; | |
485 | } | |
486 | } | |
487 | } | |
488 | ||
e126ba97 EC |
489 | static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order) |
490 | { | |
491 | struct mlx5_mr_cache *cache = &dev->cache; | |
492 | struct mlx5_ib_mr *mr = NULL; | |
493 | struct mlx5_cache_ent *ent; | |
494 | int c; | |
495 | int i; | |
496 | ||
497 | c = order2idx(dev, order); | |
49780d42 | 498 | if (c < 0 || c > MAX_UMR_CACHE_ENTRY) { |
e126ba97 EC |
499 | mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c); |
500 | return NULL; | |
501 | } | |
502 | ||
49780d42 | 503 | for (i = c; i < MAX_UMR_CACHE_ENTRY; i++) { |
e126ba97 EC |
504 | ent = &cache->ent[i]; |
505 | ||
506 | mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i); | |
507 | ||
746b5583 | 508 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
509 | if (!list_empty(&ent->head)) { |
510 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, | |
511 | list); | |
512 | list_del(&mr->list); | |
513 | ent->cur--; | |
746b5583 | 514 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
515 | if (ent->cur < ent->limit) |
516 | queue_work(cache->wq, &ent->work); | |
517 | break; | |
518 | } | |
746b5583 | 519 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
520 | |
521 | queue_work(cache->wq, &ent->work); | |
e126ba97 EC |
522 | } |
523 | ||
524 | if (!mr) | |
525 | cache->ent[c].miss++; | |
526 | ||
527 | return mr; | |
528 | } | |
529 | ||
49780d42 | 530 | void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) |
e126ba97 EC |
531 | { |
532 | struct mlx5_mr_cache *cache = &dev->cache; | |
533 | struct mlx5_cache_ent *ent; | |
534 | int shrink = 0; | |
535 | int c; | |
536 | ||
537 | c = order2idx(dev, mr->order); | |
538 | if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) { | |
539 | mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c); | |
540 | return; | |
541 | } | |
49780d42 AK |
542 | |
543 | if (unreg_umr(dev, mr)) | |
544 | return; | |
545 | ||
e126ba97 | 546 | ent = &cache->ent[c]; |
746b5583 | 547 | spin_lock_irq(&ent->lock); |
e126ba97 EC |
548 | list_add_tail(&mr->list, &ent->head); |
549 | ent->cur++; | |
550 | if (ent->cur > 2 * ent->limit) | |
551 | shrink = 1; | |
746b5583 | 552 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
553 | |
554 | if (shrink) | |
555 | queue_work(cache->wq, &ent->work); | |
556 | } | |
557 | ||
558 | static void clean_keys(struct mlx5_ib_dev *dev, int c) | |
559 | { | |
e126ba97 EC |
560 | struct mlx5_mr_cache *cache = &dev->cache; |
561 | struct mlx5_cache_ent *ent = &cache->ent[c]; | |
562 | struct mlx5_ib_mr *mr; | |
e126ba97 EC |
563 | int err; |
564 | ||
3c461911 | 565 | cancel_delayed_work(&ent->dwork); |
e126ba97 | 566 | while (1) { |
746b5583 | 567 | spin_lock_irq(&ent->lock); |
e126ba97 | 568 | if (list_empty(&ent->head)) { |
746b5583 | 569 | spin_unlock_irq(&ent->lock); |
e126ba97 EC |
570 | return; |
571 | } | |
572 | mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list); | |
573 | list_del(&mr->list); | |
574 | ent->cur--; | |
575 | ent->size--; | |
746b5583 | 576 | spin_unlock_irq(&ent->lock); |
b4cfe447 | 577 | err = destroy_mkey(dev, mr); |
203099fd | 578 | if (err) |
e126ba97 | 579 | mlx5_ib_warn(dev, "failed destroy mkey\n"); |
203099fd | 580 | else |
e126ba97 | 581 | kfree(mr); |
e126ba97 EC |
582 | } |
583 | } | |
584 | ||
12cc1a02 LR |
585 | static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev) |
586 | { | |
587 | if (!mlx5_debugfs_root) | |
588 | return; | |
589 | ||
590 | debugfs_remove_recursive(dev->cache.root); | |
591 | dev->cache.root = NULL; | |
592 | } | |
593 | ||
e126ba97 EC |
594 | static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev) |
595 | { | |
596 | struct mlx5_mr_cache *cache = &dev->cache; | |
597 | struct mlx5_cache_ent *ent; | |
598 | int i; | |
599 | ||
600 | if (!mlx5_debugfs_root) | |
601 | return 0; | |
602 | ||
9603b61d | 603 | cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root); |
e126ba97 EC |
604 | if (!cache->root) |
605 | return -ENOMEM; | |
606 | ||
607 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
608 | ent = &cache->ent[i]; | |
609 | sprintf(ent->name, "%d", ent->order); | |
610 | ent->dir = debugfs_create_dir(ent->name, cache->root); | |
611 | if (!ent->dir) | |
12cc1a02 | 612 | goto err; |
e126ba97 EC |
613 | |
614 | ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent, | |
615 | &size_fops); | |
616 | if (!ent->fsize) | |
12cc1a02 | 617 | goto err; |
e126ba97 EC |
618 | |
619 | ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent, | |
620 | &limit_fops); | |
621 | if (!ent->flimit) | |
12cc1a02 | 622 | goto err; |
e126ba97 EC |
623 | |
624 | ent->fcur = debugfs_create_u32("cur", 0400, ent->dir, | |
625 | &ent->cur); | |
626 | if (!ent->fcur) | |
12cc1a02 | 627 | goto err; |
e126ba97 EC |
628 | |
629 | ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, | |
630 | &ent->miss); | |
631 | if (!ent->fmiss) | |
12cc1a02 | 632 | goto err; |
e126ba97 EC |
633 | } |
634 | ||
635 | return 0; | |
12cc1a02 LR |
636 | err: |
637 | mlx5_mr_cache_debugfs_cleanup(dev); | |
e126ba97 | 638 | |
12cc1a02 | 639 | return -ENOMEM; |
e126ba97 EC |
640 | } |
641 | ||
746b5583 EC |
642 | static void delay_time_func(unsigned long ctx) |
643 | { | |
644 | struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx; | |
645 | ||
646 | dev->fill_delay = 0; | |
647 | } | |
648 | ||
e126ba97 EC |
649 | int mlx5_mr_cache_init(struct mlx5_ib_dev *dev) |
650 | { | |
651 | struct mlx5_mr_cache *cache = &dev->cache; | |
652 | struct mlx5_cache_ent *ent; | |
e126ba97 EC |
653 | int err; |
654 | int i; | |
655 | ||
6bc1a656 | 656 | mutex_init(&dev->slow_path_mutex); |
3c856c82 | 657 | cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM); |
e126ba97 EC |
658 | if (!cache->wq) { |
659 | mlx5_ib_warn(dev, "failed to create work queue\n"); | |
660 | return -ENOMEM; | |
661 | } | |
662 | ||
746b5583 | 663 | setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev); |
e126ba97 | 664 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { |
e126ba97 EC |
665 | ent = &cache->ent[i]; |
666 | INIT_LIST_HEAD(&ent->head); | |
667 | spin_lock_init(&ent->lock); | |
668 | ent->order = i + 2; | |
669 | ent->dev = dev; | |
49780d42 | 670 | ent->limit = 0; |
e126ba97 | 671 | |
49780d42 | 672 | init_completion(&ent->compl); |
e126ba97 EC |
673 | INIT_WORK(&ent->work, cache_work_func); |
674 | INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); | |
e126ba97 | 675 | queue_work(cache->wq, &ent->work); |
49780d42 | 676 | |
81713d37 AK |
677 | if (i > MAX_UMR_CACHE_ENTRY) { |
678 | mlx5_odp_init_mr_cache_entry(ent); | |
49780d42 | 679 | continue; |
81713d37 | 680 | } |
49780d42 AK |
681 | |
682 | if (!use_umr(dev, ent->order)) | |
683 | continue; | |
684 | ||
685 | ent->page = PAGE_SHIFT; | |
686 | ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) / | |
687 | MLX5_IB_UMR_OCTOWORD; | |
688 | ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; | |
689 | if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && | |
690 | mlx5_core_is_pf(dev->mdev)) | |
691 | ent->limit = dev->mdev->profile->mr_cache[i].limit; | |
692 | else | |
693 | ent->limit = 0; | |
e126ba97 EC |
694 | } |
695 | ||
696 | err = mlx5_mr_cache_debugfs_init(dev); | |
697 | if (err) | |
698 | mlx5_ib_warn(dev, "cache debugfs failure\n"); | |
699 | ||
12cc1a02 LR |
700 | /* |
701 | * We don't want to fail driver if debugfs failed to initialize, | |
702 | * so we are not forwarding error to the user. | |
703 | */ | |
704 | ||
e126ba97 EC |
705 | return 0; |
706 | } | |
707 | ||
acbda523 EC |
708 | static void wait_for_async_commands(struct mlx5_ib_dev *dev) |
709 | { | |
710 | struct mlx5_mr_cache *cache = &dev->cache; | |
711 | struct mlx5_cache_ent *ent; | |
712 | int total = 0; | |
713 | int i; | |
714 | int j; | |
715 | ||
716 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
717 | ent = &cache->ent[i]; | |
718 | for (j = 0 ; j < 1000; j++) { | |
719 | if (!ent->pending) | |
720 | break; | |
721 | msleep(50); | |
722 | } | |
723 | } | |
724 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) { | |
725 | ent = &cache->ent[i]; | |
726 | total += ent->pending; | |
727 | } | |
728 | ||
729 | if (total) | |
730 | mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total); | |
731 | else | |
732 | mlx5_ib_warn(dev, "done with all pending requests\n"); | |
733 | } | |
734 | ||
e126ba97 EC |
735 | int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) |
736 | { | |
737 | int i; | |
738 | ||
739 | dev->cache.stopped = 1; | |
3c461911 | 740 | flush_workqueue(dev->cache.wq); |
e126ba97 EC |
741 | |
742 | mlx5_mr_cache_debugfs_cleanup(dev); | |
743 | ||
744 | for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) | |
745 | clean_keys(dev, i); | |
746 | ||
3c461911 | 747 | destroy_workqueue(dev->cache.wq); |
acbda523 | 748 | wait_for_async_commands(dev); |
746b5583 | 749 | del_timer_sync(&dev->delay_timer); |
3c461911 | 750 | |
e126ba97 EC |
751 | return 0; |
752 | } | |
753 | ||
754 | struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc) | |
755 | { | |
756 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 757 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
9603b61d | 758 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 | 759 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
760 | void *mkc; |
761 | u32 *in; | |
e126ba97 EC |
762 | int err; |
763 | ||
764 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
765 | if (!mr) | |
766 | return ERR_PTR(-ENOMEM); | |
767 | ||
ec22eb53 | 768 | in = kzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
769 | if (!in) { |
770 | err = -ENOMEM; | |
771 | goto err_free; | |
772 | } | |
773 | ||
ec22eb53 SM |
774 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
775 | ||
776 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA); | |
777 | MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC)); | |
778 | MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE)); | |
779 | MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ)); | |
780 | MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE)); | |
781 | MLX5_SET(mkc, mkc, lr, 1); | |
e126ba97 | 782 | |
ec22eb53 SM |
783 | MLX5_SET(mkc, mkc, length64, 1); |
784 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
785 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
786 | MLX5_SET64(mkc, mkc, start_addr, 0); | |
787 | ||
788 | err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
789 | if (err) |
790 | goto err_in; | |
791 | ||
792 | kfree(in); | |
aa8e08d2 | 793 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
794 | mr->ibmr.lkey = mr->mmkey.key; |
795 | mr->ibmr.rkey = mr->mmkey.key; | |
e126ba97 EC |
796 | mr->umem = NULL; |
797 | ||
798 | return &mr->ibmr; | |
799 | ||
800 | err_in: | |
801 | kfree(in); | |
802 | ||
803 | err_free: | |
804 | kfree(mr); | |
805 | ||
806 | return ERR_PTR(err); | |
807 | } | |
808 | ||
809 | static int get_octo_len(u64 addr, u64 len, int page_size) | |
810 | { | |
811 | u64 offset; | |
812 | int npages; | |
813 | ||
814 | offset = addr & (page_size - 1); | |
815 | npages = ALIGN(len + offset, page_size) >> ilog2(page_size); | |
816 | return (npages + 1) / 2; | |
817 | } | |
818 | ||
7d0cc6ed | 819 | static int use_umr(struct mlx5_ib_dev *dev, int order) |
e126ba97 | 820 | { |
7d0cc6ed | 821 | if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) |
49780d42 | 822 | return order <= MAX_UMR_CACHE_ENTRY + 2; |
cc149f75 | 823 | return order <= MLX5_MAX_UMR_SHIFT; |
e126ba97 EC |
824 | } |
825 | ||
14ab8896 AB |
826 | static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length, |
827 | int access_flags, struct ib_umem **umem, | |
828 | int *npages, int *page_shift, int *ncont, | |
829 | int *order) | |
395a8e4c NO |
830 | { |
831 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
14ab8896 AB |
832 | int err; |
833 | ||
834 | *umem = ib_umem_get(pd->uobject->context, start, length, | |
835 | access_flags, 0); | |
836 | err = PTR_ERR_OR_ZERO(*umem); | |
837 | if (err < 0) { | |
396551eb | 838 | mlx5_ib_err(dev, "umem get failed (%d)\n", err); |
14ab8896 | 839 | return err; |
395a8e4c NO |
840 | } |
841 | ||
14ab8896 | 842 | mlx5_ib_cont_pages(*umem, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages, |
762f899a | 843 | page_shift, ncont, order); |
395a8e4c NO |
844 | if (!*npages) { |
845 | mlx5_ib_warn(dev, "avoid zero region\n"); | |
14ab8896 AB |
846 | ib_umem_release(*umem); |
847 | return -EINVAL; | |
395a8e4c NO |
848 | } |
849 | ||
850 | mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", | |
851 | *npages, *ncont, *order, *page_shift); | |
852 | ||
14ab8896 | 853 | return 0; |
395a8e4c NO |
854 | } |
855 | ||
add08d76 | 856 | static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) |
e126ba97 | 857 | { |
add08d76 CH |
858 | struct mlx5_ib_umr_context *context = |
859 | container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe); | |
e126ba97 | 860 | |
add08d76 CH |
861 | context->status = wc->status; |
862 | complete(&context->done); | |
863 | } | |
e126ba97 | 864 | |
add08d76 CH |
865 | static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context) |
866 | { | |
867 | context->cqe.done = mlx5_ib_umr_done; | |
868 | context->status = -1; | |
869 | init_completion(&context->done); | |
e126ba97 EC |
870 | } |
871 | ||
d5ea2df9 BJ |
872 | static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev, |
873 | struct mlx5_umr_wr *umrwr) | |
874 | { | |
875 | struct umr_common *umrc = &dev->umrc; | |
876 | struct ib_send_wr *bad; | |
877 | int err; | |
878 | struct mlx5_ib_umr_context umr_context; | |
879 | ||
880 | mlx5_ib_init_umr_context(&umr_context); | |
881 | umrwr->wr.wr_cqe = &umr_context.cqe; | |
882 | ||
883 | down(&umrc->sem); | |
884 | err = ib_post_send(umrc->qp, &umrwr->wr, &bad); | |
885 | if (err) { | |
886 | mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err); | |
887 | } else { | |
888 | wait_for_completion(&umr_context.done); | |
889 | if (umr_context.status != IB_WC_SUCCESS) { | |
890 | mlx5_ib_warn(dev, "reg umr failed (%u)\n", | |
891 | umr_context.status); | |
892 | err = -EFAULT; | |
893 | } | |
894 | } | |
895 | up(&umrc->sem); | |
896 | return err; | |
897 | } | |
898 | ||
e126ba97 EC |
899 | static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem, |
900 | u64 virt_addr, u64 len, int npages, | |
901 | int page_shift, int order, int access_flags) | |
902 | { | |
903 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 904 | struct mlx5_ib_mr *mr; |
096f7e72 | 905 | int err = 0; |
e126ba97 EC |
906 | int i; |
907 | ||
746b5583 | 908 | for (i = 0; i < 1; i++) { |
e126ba97 EC |
909 | mr = alloc_cached_mr(dev, order); |
910 | if (mr) | |
911 | break; | |
912 | ||
913 | err = add_keys(dev, order2idx(dev, order), 1); | |
746b5583 EC |
914 | if (err && err != -EAGAIN) { |
915 | mlx5_ib_warn(dev, "add_keys failed, err %d\n", err); | |
e126ba97 EC |
916 | break; |
917 | } | |
918 | } | |
919 | ||
920 | if (!mr) | |
921 | return ERR_PTR(-EAGAIN); | |
922 | ||
7d0cc6ed AK |
923 | mr->ibmr.pd = pd; |
924 | mr->umem = umem; | |
925 | mr->access_flags = access_flags; | |
926 | mr->desc_size = sizeof(struct mlx5_mtt); | |
a606b0f6 MB |
927 | mr->mmkey.iova = virt_addr; |
928 | mr->mmkey.size = len; | |
929 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
b475598a | 930 | |
7d0cc6ed AK |
931 | err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, |
932 | MLX5_IB_UPD_XLT_ENABLE); | |
096f7e72 | 933 | |
096f7e72 | 934 | if (err) { |
49780d42 | 935 | mlx5_mr_cache_free(dev, mr); |
096f7e72 | 936 | return ERR_PTR(err); |
e126ba97 EC |
937 | } |
938 | ||
7d0cc6ed AK |
939 | mr->live = 1; |
940 | ||
e126ba97 | 941 | return mr; |
e126ba97 EC |
942 | } |
943 | ||
7d0cc6ed AK |
944 | static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages, |
945 | void *xlt, int page_shift, size_t size, | |
946 | int flags) | |
832a6b06 HE |
947 | { |
948 | struct mlx5_ib_dev *dev = mr->dev; | |
832a6b06 | 949 | struct ib_umem *umem = mr->umem; |
81713d37 AK |
950 | if (flags & MLX5_IB_UPD_XLT_INDIRECT) { |
951 | mlx5_odp_populate_klm(xlt, idx, npages, mr, flags); | |
952 | return npages; | |
953 | } | |
7d0cc6ed AK |
954 | |
955 | npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx); | |
956 | ||
957 | if (!(flags & MLX5_IB_UPD_XLT_ZAP)) { | |
958 | __mlx5_ib_populate_pas(dev, umem, page_shift, | |
959 | idx, npages, xlt, | |
960 | MLX5_IB_MTT_PRESENT); | |
961 | /* Clear padding after the pages | |
962 | * brought from the umem. | |
963 | */ | |
964 | memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0, | |
965 | size - npages * sizeof(struct mlx5_mtt)); | |
966 | } | |
967 | ||
968 | return npages; | |
969 | } | |
970 | ||
971 | #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \ | |
972 | MLX5_UMR_MTT_ALIGNMENT) | |
973 | #define MLX5_SPARE_UMR_CHUNK 0x10000 | |
974 | ||
975 | int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, | |
976 | int page_shift, int flags) | |
977 | { | |
978 | struct mlx5_ib_dev *dev = mr->dev; | |
9b0c289e | 979 | struct device *ddev = dev->ib_dev.dev.parent; |
7d0cc6ed | 980 | struct mlx5_ib_ucontext *uctx = NULL; |
832a6b06 | 981 | int size; |
7d0cc6ed | 982 | void *xlt; |
832a6b06 | 983 | dma_addr_t dma; |
e622f2f4 | 984 | struct mlx5_umr_wr wr; |
832a6b06 HE |
985 | struct ib_sge sg; |
986 | int err = 0; | |
81713d37 AK |
987 | int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT) |
988 | ? sizeof(struct mlx5_klm) | |
989 | : sizeof(struct mlx5_mtt); | |
7d0cc6ed AK |
990 | const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size; |
991 | const int page_mask = page_align - 1; | |
832a6b06 HE |
992 | size_t pages_mapped = 0; |
993 | size_t pages_to_map = 0; | |
994 | size_t pages_iter = 0; | |
7d0cc6ed | 995 | gfp_t gfp; |
832a6b06 HE |
996 | |
997 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes, | |
7d0cc6ed AK |
998 | * so we need to align the offset and length accordingly |
999 | */ | |
1000 | if (idx & page_mask) { | |
1001 | npages += idx & page_mask; | |
1002 | idx &= ~page_mask; | |
832a6b06 HE |
1003 | } |
1004 | ||
7d0cc6ed AK |
1005 | gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL; |
1006 | gfp |= __GFP_ZERO | __GFP_NOWARN; | |
832a6b06 | 1007 | |
7d0cc6ed AK |
1008 | pages_to_map = ALIGN(npages, page_align); |
1009 | size = desc_size * pages_to_map; | |
1010 | size = min_t(int, size, MLX5_MAX_UMR_CHUNK); | |
832a6b06 | 1011 | |
7d0cc6ed AK |
1012 | xlt = (void *)__get_free_pages(gfp, get_order(size)); |
1013 | if (!xlt && size > MLX5_SPARE_UMR_CHUNK) { | |
1014 | mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n", | |
1015 | size, get_order(size), MLX5_SPARE_UMR_CHUNK); | |
1016 | ||
1017 | size = MLX5_SPARE_UMR_CHUNK; | |
1018 | xlt = (void *)__get_free_pages(gfp, get_order(size)); | |
832a6b06 | 1019 | } |
7d0cc6ed AK |
1020 | |
1021 | if (!xlt) { | |
bd174fc2 | 1022 | uctx = to_mucontext(mr->ibmr.pd->uobject->context); |
7d0cc6ed AK |
1023 | mlx5_ib_warn(dev, "Using XLT emergency buffer\n"); |
1024 | size = PAGE_SIZE; | |
1025 | xlt = (void *)uctx->upd_xlt_page; | |
1026 | mutex_lock(&uctx->upd_xlt_page_mutex); | |
1027 | memset(xlt, 0, size); | |
1028 | } | |
1029 | pages_iter = size / desc_size; | |
1030 | dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE); | |
832a6b06 | 1031 | if (dma_mapping_error(ddev, dma)) { |
7d0cc6ed | 1032 | mlx5_ib_err(dev, "unable to map DMA during XLT update.\n"); |
832a6b06 | 1033 | err = -ENOMEM; |
7d0cc6ed | 1034 | goto free_xlt; |
832a6b06 HE |
1035 | } |
1036 | ||
7d0cc6ed AK |
1037 | sg.addr = dma; |
1038 | sg.lkey = dev->umrc.pd->local_dma_lkey; | |
1039 | ||
1040 | memset(&wr, 0, sizeof(wr)); | |
1041 | wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT; | |
1042 | if (!(flags & MLX5_IB_UPD_XLT_ENABLE)) | |
1043 | wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1044 | wr.wr.sg_list = &sg; | |
1045 | wr.wr.num_sge = 1; | |
1046 | wr.wr.opcode = MLX5_IB_WR_UMR; | |
1047 | ||
1048 | wr.pd = mr->ibmr.pd; | |
1049 | wr.mkey = mr->mmkey.key; | |
1050 | wr.length = mr->mmkey.size; | |
1051 | wr.virt_addr = mr->mmkey.iova; | |
1052 | wr.access_flags = mr->access_flags; | |
1053 | wr.page_shift = page_shift; | |
1054 | ||
832a6b06 HE |
1055 | for (pages_mapped = 0; |
1056 | pages_mapped < pages_to_map && !err; | |
7d0cc6ed | 1057 | pages_mapped += pages_iter, idx += pages_iter) { |
438b228e | 1058 | npages = min_t(int, pages_iter, pages_to_map - pages_mapped); |
832a6b06 | 1059 | dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE); |
438b228e | 1060 | npages = populate_xlt(mr, idx, npages, xlt, |
7d0cc6ed | 1061 | page_shift, size, flags); |
832a6b06 HE |
1062 | |
1063 | dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE); | |
1064 | ||
7d0cc6ed AK |
1065 | sg.length = ALIGN(npages * desc_size, |
1066 | MLX5_UMR_MTT_ALIGNMENT); | |
1067 | ||
1068 | if (pages_mapped + pages_iter >= pages_to_map) { | |
1069 | if (flags & MLX5_IB_UPD_XLT_ENABLE) | |
1070 | wr.wr.send_flags |= | |
1071 | MLX5_IB_SEND_UMR_ENABLE_MR | | |
1072 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS | | |
1073 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1074 | if (flags & MLX5_IB_UPD_XLT_PD || | |
1075 | flags & MLX5_IB_UPD_XLT_ACCESS) | |
1076 | wr.wr.send_flags |= | |
1077 | MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; | |
1078 | if (flags & MLX5_IB_UPD_XLT_ADDR) | |
1079 | wr.wr.send_flags |= | |
1080 | MLX5_IB_SEND_UMR_UPDATE_TRANSLATION; | |
1081 | } | |
832a6b06 | 1082 | |
7d0cc6ed | 1083 | wr.offset = idx * desc_size; |
31616255 | 1084 | wr.xlt_size = sg.length; |
832a6b06 | 1085 | |
d5ea2df9 | 1086 | err = mlx5_ib_post_send_wait(dev, &wr); |
832a6b06 HE |
1087 | } |
1088 | dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); | |
1089 | ||
7d0cc6ed AK |
1090 | free_xlt: |
1091 | if (uctx) | |
1092 | mutex_unlock(&uctx->upd_xlt_page_mutex); | |
832a6b06 | 1093 | else |
7d0cc6ed | 1094 | free_pages((unsigned long)xlt, get_order(size)); |
832a6b06 HE |
1095 | |
1096 | return err; | |
1097 | } | |
832a6b06 | 1098 | |
395a8e4c NO |
1099 | /* |
1100 | * If ibmr is NULL it will be allocated by reg_create. | |
1101 | * Else, the given ibmr will be used. | |
1102 | */ | |
1103 | static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd, | |
1104 | u64 virt_addr, u64 length, | |
1105 | struct ib_umem *umem, int npages, | |
1106 | int page_shift, int access_flags) | |
e126ba97 EC |
1107 | { |
1108 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
e126ba97 | 1109 | struct mlx5_ib_mr *mr; |
ec22eb53 SM |
1110 | __be64 *pas; |
1111 | void *mkc; | |
e126ba97 | 1112 | int inlen; |
ec22eb53 | 1113 | u32 *in; |
e126ba97 | 1114 | int err; |
938fe83c | 1115 | bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg)); |
e126ba97 | 1116 | |
395a8e4c | 1117 | mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL); |
e126ba97 EC |
1118 | if (!mr) |
1119 | return ERR_PTR(-ENOMEM); | |
1120 | ||
ec22eb53 SM |
1121 | inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + |
1122 | sizeof(*pas) * ((npages + 1) / 2) * 2; | |
1b9a07ee | 1123 | in = kvzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
1124 | if (!in) { |
1125 | err = -ENOMEM; | |
1126 | goto err_1; | |
1127 | } | |
ec22eb53 | 1128 | pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); |
c438fde1 AK |
1129 | if (!(access_flags & IB_ACCESS_ON_DEMAND)) |
1130 | mlx5_ib_populate_pas(dev, umem, page_shift, pas, | |
1131 | pg_cap ? MLX5_IB_MTT_PRESENT : 0); | |
e126ba97 | 1132 | |
ec22eb53 | 1133 | /* The pg_access bit allows setting the access flags |
cc149f75 | 1134 | * in the page list submitted with the command. */ |
ec22eb53 SM |
1135 | MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap)); |
1136 | ||
1137 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
1138 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); | |
1139 | MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
1140 | MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE)); | |
1141 | MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); | |
1142 | MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); | |
1143 | MLX5_SET(mkc, mkc, lr, 1); | |
1144 | ||
1145 | MLX5_SET64(mkc, mkc, start_addr, virt_addr); | |
1146 | MLX5_SET64(mkc, mkc, len, length); | |
1147 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1148 | MLX5_SET(mkc, mkc, bsf_octword_size, 0); | |
1149 | MLX5_SET(mkc, mkc, translations_octword_size, | |
1150 | get_octo_len(virt_addr, length, 1 << page_shift)); | |
1151 | MLX5_SET(mkc, mkc, log_page_size, page_shift); | |
1152 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1153 | MLX5_SET(create_mkey_in, in, translations_octword_actual_size, | |
1154 | get_octo_len(virt_addr, length, 1 << page_shift)); | |
1155 | ||
1156 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
e126ba97 EC |
1157 | if (err) { |
1158 | mlx5_ib_warn(dev, "create mkey failed\n"); | |
1159 | goto err_2; | |
1160 | } | |
aa8e08d2 | 1161 | mr->mmkey.type = MLX5_MKEY_MR; |
49780d42 | 1162 | mr->desc_size = sizeof(struct mlx5_mtt); |
e126ba97 | 1163 | mr->umem = umem; |
7eae20db | 1164 | mr->dev = dev; |
b4cfe447 | 1165 | mr->live = 1; |
479163f4 | 1166 | kvfree(in); |
e126ba97 | 1167 | |
a606b0f6 | 1168 | mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1169 | |
1170 | return mr; | |
1171 | ||
1172 | err_2: | |
479163f4 | 1173 | kvfree(in); |
e126ba97 EC |
1174 | |
1175 | err_1: | |
395a8e4c NO |
1176 | if (!ibmr) |
1177 | kfree(mr); | |
e126ba97 EC |
1178 | |
1179 | return ERR_PTR(err); | |
1180 | } | |
1181 | ||
395a8e4c NO |
1182 | static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr, |
1183 | int npages, u64 length, int access_flags) | |
1184 | { | |
1185 | mr->npages = npages; | |
1186 | atomic_add(npages, &dev->mdev->priv.reg_pages); | |
a606b0f6 MB |
1187 | mr->ibmr.lkey = mr->mmkey.key; |
1188 | mr->ibmr.rkey = mr->mmkey.key; | |
395a8e4c | 1189 | mr->ibmr.length = length; |
56e11d62 | 1190 | mr->access_flags = access_flags; |
395a8e4c NO |
1191 | } |
1192 | ||
e126ba97 EC |
1193 | struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, |
1194 | u64 virt_addr, int access_flags, | |
1195 | struct ib_udata *udata) | |
1196 | { | |
1197 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
1198 | struct mlx5_ib_mr *mr = NULL; | |
1199 | struct ib_umem *umem; | |
1200 | int page_shift; | |
1201 | int npages; | |
1202 | int ncont; | |
1203 | int order; | |
1204 | int err; | |
1205 | ||
900a6d79 EC |
1206 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", |
1207 | start, virt_addr, length, access_flags); | |
81713d37 AK |
1208 | |
1209 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1210 | if (!start && length == U64_MAX) { | |
1211 | if (!(access_flags & IB_ACCESS_ON_DEMAND) || | |
1212 | !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) | |
1213 | return ERR_PTR(-EINVAL); | |
1214 | ||
1215 | mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags); | |
1216 | return &mr->ibmr; | |
1217 | } | |
1218 | #endif | |
1219 | ||
14ab8896 | 1220 | err = mr_umem_get(pd, start, length, access_flags, &umem, &npages, |
395a8e4c | 1221 | &page_shift, &ncont, &order); |
e126ba97 | 1222 | |
14ab8896 AB |
1223 | if (err < 0) |
1224 | return ERR_PTR(err); | |
e126ba97 | 1225 | |
7d0cc6ed | 1226 | if (use_umr(dev, order)) { |
e126ba97 EC |
1227 | mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift, |
1228 | order, access_flags); | |
1229 | if (PTR_ERR(mr) == -EAGAIN) { | |
1230 | mlx5_ib_dbg(dev, "cache empty for order %d", order); | |
1231 | mr = NULL; | |
1232 | } | |
c438fde1 AK |
1233 | } else if (access_flags & IB_ACCESS_ON_DEMAND && |
1234 | !MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) { | |
6aec21f6 HE |
1235 | err = -EINVAL; |
1236 | pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB"); | |
1237 | goto error; | |
e126ba97 EC |
1238 | } |
1239 | ||
6bc1a656 ML |
1240 | if (!mr) { |
1241 | mutex_lock(&dev->slow_path_mutex); | |
395a8e4c NO |
1242 | mr = reg_create(NULL, pd, virt_addr, length, umem, ncont, |
1243 | page_shift, access_flags); | |
6bc1a656 ML |
1244 | mutex_unlock(&dev->slow_path_mutex); |
1245 | } | |
e126ba97 EC |
1246 | |
1247 | if (IS_ERR(mr)) { | |
1248 | err = PTR_ERR(mr); | |
1249 | goto error; | |
1250 | } | |
1251 | ||
a606b0f6 | 1252 | mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key); |
e126ba97 EC |
1253 | |
1254 | mr->umem = umem; | |
395a8e4c | 1255 | set_mr_fileds(dev, mr, npages, length, access_flags); |
e126ba97 | 1256 | |
b4cfe447 | 1257 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
395a8e4c | 1258 | update_odp_mr(mr); |
b4cfe447 HE |
1259 | #endif |
1260 | ||
e126ba97 EC |
1261 | return &mr->ibmr; |
1262 | ||
1263 | error: | |
1264 | ib_umem_release(umem); | |
1265 | return ERR_PTR(err); | |
1266 | } | |
1267 | ||
1268 | static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) | |
1269 | { | |
89ea94a7 | 1270 | struct mlx5_core_dev *mdev = dev->mdev; |
0025b0bd | 1271 | struct mlx5_umr_wr umrwr = {}; |
e126ba97 | 1272 | |
89ea94a7 MG |
1273 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) |
1274 | return 0; | |
1275 | ||
7d0cc6ed AK |
1276 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR | |
1277 | MLX5_IB_SEND_UMR_FAIL_IF_FREE; | |
1278 | umrwr.wr.opcode = MLX5_IB_WR_UMR; | |
1279 | umrwr.mkey = mr->mmkey.key; | |
e126ba97 | 1280 | |
d5ea2df9 | 1281 | return mlx5_ib_post_send_wait(dev, &umrwr); |
e126ba97 EC |
1282 | } |
1283 | ||
7d0cc6ed | 1284 | static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, |
56e11d62 NO |
1285 | int access_flags, int flags) |
1286 | { | |
1287 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
56e11d62 | 1288 | struct mlx5_umr_wr umrwr = {}; |
56e11d62 NO |
1289 | int err; |
1290 | ||
56e11d62 NO |
1291 | umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE; |
1292 | ||
7d0cc6ed AK |
1293 | umrwr.wr.opcode = MLX5_IB_WR_UMR; |
1294 | umrwr.mkey = mr->mmkey.key; | |
56e11d62 | 1295 | |
31616255 | 1296 | if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) { |
56e11d62 | 1297 | umrwr.pd = pd; |
56e11d62 | 1298 | umrwr.access_flags = access_flags; |
31616255 | 1299 | umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS; |
56e11d62 NO |
1300 | } |
1301 | ||
d5ea2df9 | 1302 | err = mlx5_ib_post_send_wait(dev, &umrwr); |
56e11d62 | 1303 | |
56e11d62 NO |
1304 | return err; |
1305 | } | |
1306 | ||
1307 | int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, | |
1308 | u64 length, u64 virt_addr, int new_access_flags, | |
1309 | struct ib_pd *new_pd, struct ib_udata *udata) | |
1310 | { | |
1311 | struct mlx5_ib_dev *dev = to_mdev(ib_mr->device); | |
1312 | struct mlx5_ib_mr *mr = to_mmr(ib_mr); | |
1313 | struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd; | |
1314 | int access_flags = flags & IB_MR_REREG_ACCESS ? | |
1315 | new_access_flags : | |
1316 | mr->access_flags; | |
1317 | u64 addr = (flags & IB_MR_REREG_TRANS) ? virt_addr : mr->umem->address; | |
1318 | u64 len = (flags & IB_MR_REREG_TRANS) ? length : mr->umem->length; | |
1319 | int page_shift = 0; | |
7d0cc6ed | 1320 | int upd_flags = 0; |
56e11d62 NO |
1321 | int npages = 0; |
1322 | int ncont = 0; | |
1323 | int order = 0; | |
1324 | int err; | |
1325 | ||
1326 | mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", | |
1327 | start, virt_addr, length, access_flags); | |
1328 | ||
7d0cc6ed AK |
1329 | atomic_sub(mr->npages, &dev->mdev->priv.reg_pages); |
1330 | ||
56e11d62 NO |
1331 | if (flags != IB_MR_REREG_PD) { |
1332 | /* | |
1333 | * Replace umem. This needs to be done whether or not UMR is | |
1334 | * used. | |
1335 | */ | |
1336 | flags |= IB_MR_REREG_TRANS; | |
1337 | ib_umem_release(mr->umem); | |
14ab8896 AB |
1338 | err = mr_umem_get(pd, addr, len, access_flags, &mr->umem, |
1339 | &npages, &page_shift, &ncont, &order); | |
1340 | if (err < 0) { | |
7d0cc6ed | 1341 | clean_mr(mr); |
56e11d62 NO |
1342 | return err; |
1343 | } | |
1344 | } | |
1345 | ||
1346 | if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) { | |
1347 | /* | |
1348 | * UMR can't be used - MKey needs to be replaced. | |
1349 | */ | |
1350 | if (mr->umred) { | |
1351 | err = unreg_umr(dev, mr); | |
1352 | if (err) | |
1353 | mlx5_ib_warn(dev, "Failed to unregister MR\n"); | |
1354 | } else { | |
1355 | err = destroy_mkey(dev, mr); | |
1356 | if (err) | |
1357 | mlx5_ib_warn(dev, "Failed to destroy MKey\n"); | |
1358 | } | |
1359 | if (err) | |
1360 | return err; | |
1361 | ||
1362 | mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont, | |
1363 | page_shift, access_flags); | |
1364 | ||
1365 | if (IS_ERR(mr)) | |
1366 | return PTR_ERR(mr); | |
1367 | ||
1368 | mr->umred = 0; | |
1369 | } else { | |
1370 | /* | |
1371 | * Send a UMR WQE | |
1372 | */ | |
7d0cc6ed AK |
1373 | mr->ibmr.pd = pd; |
1374 | mr->access_flags = access_flags; | |
1375 | mr->mmkey.iova = addr; | |
1376 | mr->mmkey.size = len; | |
1377 | mr->mmkey.pd = to_mpd(pd)->pdn; | |
1378 | ||
1379 | if (flags & IB_MR_REREG_TRANS) { | |
1380 | upd_flags = MLX5_IB_UPD_XLT_ADDR; | |
1381 | if (flags & IB_MR_REREG_PD) | |
1382 | upd_flags |= MLX5_IB_UPD_XLT_PD; | |
1383 | if (flags & IB_MR_REREG_ACCESS) | |
1384 | upd_flags |= MLX5_IB_UPD_XLT_ACCESS; | |
1385 | err = mlx5_ib_update_xlt(mr, 0, npages, page_shift, | |
1386 | upd_flags); | |
1387 | } else { | |
1388 | err = rereg_umr(pd, mr, access_flags, flags); | |
1389 | } | |
1390 | ||
56e11d62 NO |
1391 | if (err) { |
1392 | mlx5_ib_warn(dev, "Failed to rereg UMR\n"); | |
7d0cc6ed AK |
1393 | ib_umem_release(mr->umem); |
1394 | clean_mr(mr); | |
56e11d62 NO |
1395 | return err; |
1396 | } | |
1397 | } | |
1398 | ||
7d0cc6ed | 1399 | set_mr_fileds(dev, mr, npages, len, access_flags); |
56e11d62 | 1400 | |
56e11d62 NO |
1401 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1402 | update_odp_mr(mr); | |
1403 | #endif | |
56e11d62 NO |
1404 | return 0; |
1405 | } | |
1406 | ||
8a187ee5 SG |
1407 | static int |
1408 | mlx5_alloc_priv_descs(struct ib_device *device, | |
1409 | struct mlx5_ib_mr *mr, | |
1410 | int ndescs, | |
1411 | int desc_size) | |
1412 | { | |
1413 | int size = ndescs * desc_size; | |
1414 | int add_size; | |
1415 | int ret; | |
1416 | ||
1417 | add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0); | |
1418 | ||
1419 | mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL); | |
1420 | if (!mr->descs_alloc) | |
1421 | return -ENOMEM; | |
1422 | ||
1423 | mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN); | |
1424 | ||
9b0c289e | 1425 | mr->desc_map = dma_map_single(device->dev.parent, mr->descs, |
8a187ee5 | 1426 | size, DMA_TO_DEVICE); |
9b0c289e | 1427 | if (dma_mapping_error(device->dev.parent, mr->desc_map)) { |
8a187ee5 SG |
1428 | ret = -ENOMEM; |
1429 | goto err; | |
1430 | } | |
1431 | ||
1432 | return 0; | |
1433 | err: | |
1434 | kfree(mr->descs_alloc); | |
1435 | ||
1436 | return ret; | |
1437 | } | |
1438 | ||
1439 | static void | |
1440 | mlx5_free_priv_descs(struct mlx5_ib_mr *mr) | |
1441 | { | |
1442 | if (mr->descs) { | |
1443 | struct ib_device *device = mr->ibmr.device; | |
1444 | int size = mr->max_descs * mr->desc_size; | |
1445 | ||
9b0c289e | 1446 | dma_unmap_single(device->dev.parent, mr->desc_map, |
8a187ee5 SG |
1447 | size, DMA_TO_DEVICE); |
1448 | kfree(mr->descs_alloc); | |
1449 | mr->descs = NULL; | |
1450 | } | |
1451 | } | |
1452 | ||
6aec21f6 | 1453 | static int clean_mr(struct mlx5_ib_mr *mr) |
e126ba97 | 1454 | { |
6aec21f6 | 1455 | struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); |
e126ba97 EC |
1456 | int umred = mr->umred; |
1457 | int err; | |
1458 | ||
8b91ffc1 SG |
1459 | if (mr->sig) { |
1460 | if (mlx5_core_destroy_psv(dev->mdev, | |
1461 | mr->sig->psv_memory.psv_idx)) | |
1462 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1463 | mr->sig->psv_memory.psv_idx); | |
1464 | if (mlx5_core_destroy_psv(dev->mdev, | |
1465 | mr->sig->psv_wire.psv_idx)) | |
1466 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1467 | mr->sig->psv_wire.psv_idx); | |
1468 | kfree(mr->sig); | |
1469 | mr->sig = NULL; | |
1470 | } | |
1471 | ||
8a187ee5 SG |
1472 | mlx5_free_priv_descs(mr); |
1473 | ||
e126ba97 | 1474 | if (!umred) { |
b4cfe447 | 1475 | err = destroy_mkey(dev, mr); |
e126ba97 EC |
1476 | if (err) { |
1477 | mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n", | |
a606b0f6 | 1478 | mr->mmkey.key, err); |
e126ba97 EC |
1479 | return err; |
1480 | } | |
1481 | } else { | |
49780d42 | 1482 | mlx5_mr_cache_free(dev, mr); |
e126ba97 EC |
1483 | } |
1484 | ||
6aec21f6 HE |
1485 | if (!umred) |
1486 | kfree(mr); | |
1487 | ||
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | int mlx5_ib_dereg_mr(struct ib_mr *ibmr) | |
1492 | { | |
1493 | struct mlx5_ib_dev *dev = to_mdev(ibmr->device); | |
1494 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1495 | int npages = mr->npages; | |
1496 | struct ib_umem *umem = mr->umem; | |
1497 | ||
1498 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
b4cfe447 HE |
1499 | if (umem && umem->odp_data) { |
1500 | /* Prevent new page faults from succeeding */ | |
1501 | mr->live = 0; | |
6aec21f6 HE |
1502 | /* Wait for all running page-fault handlers to finish. */ |
1503 | synchronize_srcu(&dev->mr_srcu); | |
b4cfe447 | 1504 | /* Destroy all page mappings */ |
81713d37 AK |
1505 | if (umem->odp_data->page_list) |
1506 | mlx5_ib_invalidate_range(umem, ib_umem_start(umem), | |
1507 | ib_umem_end(umem)); | |
1508 | else | |
1509 | mlx5_ib_free_implicit_mr(mr); | |
b4cfe447 HE |
1510 | /* |
1511 | * We kill the umem before the MR for ODP, | |
1512 | * so that there will not be any invalidations in | |
1513 | * flight, looking at the *mr struct. | |
1514 | */ | |
1515 | ib_umem_release(umem); | |
1516 | atomic_sub(npages, &dev->mdev->priv.reg_pages); | |
1517 | ||
1518 | /* Avoid double-freeing the umem. */ | |
1519 | umem = NULL; | |
1520 | } | |
6aec21f6 HE |
1521 | #endif |
1522 | ||
1523 | clean_mr(mr); | |
1524 | ||
e126ba97 EC |
1525 | if (umem) { |
1526 | ib_umem_release(umem); | |
6aec21f6 | 1527 | atomic_sub(npages, &dev->mdev->priv.reg_pages); |
e126ba97 EC |
1528 | } |
1529 | ||
e126ba97 EC |
1530 | return 0; |
1531 | } | |
1532 | ||
9bee178b SG |
1533 | struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, |
1534 | enum ib_mr_type mr_type, | |
1535 | u32 max_num_sg) | |
3121e3c4 SG |
1536 | { |
1537 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1538 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
b005d316 | 1539 | int ndescs = ALIGN(max_num_sg, 4); |
ec22eb53 SM |
1540 | struct mlx5_ib_mr *mr; |
1541 | void *mkc; | |
1542 | u32 *in; | |
b005d316 | 1543 | int err; |
3121e3c4 SG |
1544 | |
1545 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1546 | if (!mr) | |
1547 | return ERR_PTR(-ENOMEM); | |
1548 | ||
ec22eb53 | 1549 | in = kzalloc(inlen, GFP_KERNEL); |
3121e3c4 SG |
1550 | if (!in) { |
1551 | err = -ENOMEM; | |
1552 | goto err_free; | |
1553 | } | |
1554 | ||
ec22eb53 SM |
1555 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1556 | MLX5_SET(mkc, mkc, free, 1); | |
1557 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1558 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1559 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
3121e3c4 | 1560 | |
9bee178b | 1561 | if (mr_type == IB_MR_TYPE_MEM_REG) { |
ec22eb53 SM |
1562 | mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT; |
1563 | MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); | |
8a187ee5 | 1564 | err = mlx5_alloc_priv_descs(pd->device, mr, |
31616255 | 1565 | ndescs, sizeof(struct mlx5_mtt)); |
8a187ee5 SG |
1566 | if (err) |
1567 | goto err_free_in; | |
1568 | ||
31616255 | 1569 | mr->desc_size = sizeof(struct mlx5_mtt); |
8a187ee5 | 1570 | mr->max_descs = ndescs; |
b005d316 | 1571 | } else if (mr_type == IB_MR_TYPE_SG_GAPS) { |
ec22eb53 | 1572 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
b005d316 SG |
1573 | |
1574 | err = mlx5_alloc_priv_descs(pd->device, mr, | |
1575 | ndescs, sizeof(struct mlx5_klm)); | |
1576 | if (err) | |
1577 | goto err_free_in; | |
1578 | mr->desc_size = sizeof(struct mlx5_klm); | |
1579 | mr->max_descs = ndescs; | |
9bee178b | 1580 | } else if (mr_type == IB_MR_TYPE_SIGNATURE) { |
3121e3c4 SG |
1581 | u32 psv_index[2]; |
1582 | ||
ec22eb53 SM |
1583 | MLX5_SET(mkc, mkc, bsf_en, 1); |
1584 | MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE); | |
3121e3c4 SG |
1585 | mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL); |
1586 | if (!mr->sig) { | |
1587 | err = -ENOMEM; | |
1588 | goto err_free_in; | |
1589 | } | |
1590 | ||
1591 | /* create mem & wire PSVs */ | |
9603b61d | 1592 | err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, |
3121e3c4 SG |
1593 | 2, psv_index); |
1594 | if (err) | |
1595 | goto err_free_sig; | |
1596 | ||
ec22eb53 | 1597 | mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS; |
3121e3c4 SG |
1598 | mr->sig->psv_memory.psv_idx = psv_index[0]; |
1599 | mr->sig->psv_wire.psv_idx = psv_index[1]; | |
d5436ba0 SG |
1600 | |
1601 | mr->sig->sig_status_checked = true; | |
1602 | mr->sig->sig_err_exists = false; | |
1603 | /* Next UMR, Arm SIGERR */ | |
1604 | ++mr->sig->sigerr_count; | |
9bee178b SG |
1605 | } else { |
1606 | mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type); | |
1607 | err = -EINVAL; | |
1608 | goto err_free_in; | |
3121e3c4 SG |
1609 | } |
1610 | ||
ec22eb53 SM |
1611 | MLX5_SET(mkc, mkc, access_mode, mr->access_mode); |
1612 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1613 | ||
1614 | err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen); | |
3121e3c4 SG |
1615 | if (err) |
1616 | goto err_destroy_psv; | |
1617 | ||
aa8e08d2 | 1618 | mr->mmkey.type = MLX5_MKEY_MR; |
a606b0f6 MB |
1619 | mr->ibmr.lkey = mr->mmkey.key; |
1620 | mr->ibmr.rkey = mr->mmkey.key; | |
3121e3c4 SG |
1621 | mr->umem = NULL; |
1622 | kfree(in); | |
1623 | ||
1624 | return &mr->ibmr; | |
1625 | ||
1626 | err_destroy_psv: | |
1627 | if (mr->sig) { | |
9603b61d | 1628 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1629 | mr->sig->psv_memory.psv_idx)) |
1630 | mlx5_ib_warn(dev, "failed to destroy mem psv %d\n", | |
1631 | mr->sig->psv_memory.psv_idx); | |
9603b61d | 1632 | if (mlx5_core_destroy_psv(dev->mdev, |
3121e3c4 SG |
1633 | mr->sig->psv_wire.psv_idx)) |
1634 | mlx5_ib_warn(dev, "failed to destroy wire psv %d\n", | |
1635 | mr->sig->psv_wire.psv_idx); | |
1636 | } | |
8a187ee5 | 1637 | mlx5_free_priv_descs(mr); |
3121e3c4 SG |
1638 | err_free_sig: |
1639 | kfree(mr->sig); | |
1640 | err_free_in: | |
1641 | kfree(in); | |
1642 | err_free: | |
1643 | kfree(mr); | |
1644 | return ERR_PTR(err); | |
1645 | } | |
1646 | ||
d2370e0a MB |
1647 | struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
1648 | struct ib_udata *udata) | |
1649 | { | |
1650 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
ec22eb53 | 1651 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
d2370e0a | 1652 | struct mlx5_ib_mw *mw = NULL; |
ec22eb53 SM |
1653 | u32 *in = NULL; |
1654 | void *mkc; | |
d2370e0a MB |
1655 | int ndescs; |
1656 | int err; | |
1657 | struct mlx5_ib_alloc_mw req = {}; | |
1658 | struct { | |
1659 | __u32 comp_mask; | |
1660 | __u32 response_length; | |
1661 | } resp = {}; | |
1662 | ||
1663 | err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); | |
1664 | if (err) | |
1665 | return ERR_PTR(err); | |
1666 | ||
1667 | if (req.comp_mask || req.reserved1 || req.reserved2) | |
1668 | return ERR_PTR(-EOPNOTSUPP); | |
1669 | ||
1670 | if (udata->inlen > sizeof(req) && | |
1671 | !ib_is_udata_cleared(udata, sizeof(req), | |
1672 | udata->inlen - sizeof(req))) | |
1673 | return ERR_PTR(-EOPNOTSUPP); | |
1674 | ||
1675 | ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4); | |
1676 | ||
1677 | mw = kzalloc(sizeof(*mw), GFP_KERNEL); | |
ec22eb53 | 1678 | in = kzalloc(inlen, GFP_KERNEL); |
d2370e0a MB |
1679 | if (!mw || !in) { |
1680 | err = -ENOMEM; | |
1681 | goto free; | |
1682 | } | |
1683 | ||
ec22eb53 SM |
1684 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); |
1685 | ||
1686 | MLX5_SET(mkc, mkc, free, 1); | |
1687 | MLX5_SET(mkc, mkc, translations_octword_size, ndescs); | |
1688 | MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); | |
1689 | MLX5_SET(mkc, mkc, umr_en, 1); | |
1690 | MLX5_SET(mkc, mkc, lr, 1); | |
1691 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS); | |
1692 | MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2))); | |
1693 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
1694 | ||
1695 | err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen); | |
d2370e0a MB |
1696 | if (err) |
1697 | goto free; | |
1698 | ||
aa8e08d2 | 1699 | mw->mmkey.type = MLX5_MKEY_MW; |
d2370e0a | 1700 | mw->ibmw.rkey = mw->mmkey.key; |
db570d7d | 1701 | mw->ndescs = ndescs; |
d2370e0a MB |
1702 | |
1703 | resp.response_length = min(offsetof(typeof(resp), response_length) + | |
1704 | sizeof(resp.response_length), udata->outlen); | |
1705 | if (resp.response_length) { | |
1706 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
1707 | if (err) { | |
1708 | mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey); | |
1709 | goto free; | |
1710 | } | |
1711 | } | |
1712 | ||
1713 | kfree(in); | |
1714 | return &mw->ibmw; | |
1715 | ||
1716 | free: | |
1717 | kfree(mw); | |
1718 | kfree(in); | |
1719 | return ERR_PTR(err); | |
1720 | } | |
1721 | ||
1722 | int mlx5_ib_dealloc_mw(struct ib_mw *mw) | |
1723 | { | |
1724 | struct mlx5_ib_mw *mmw = to_mmw(mw); | |
1725 | int err; | |
1726 | ||
1727 | err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev, | |
1728 | &mmw->mmkey); | |
1729 | if (!err) | |
1730 | kfree(mmw); | |
1731 | return err; | |
1732 | } | |
1733 | ||
d5436ba0 SG |
1734 | int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, |
1735 | struct ib_mr_status *mr_status) | |
1736 | { | |
1737 | struct mlx5_ib_mr *mmr = to_mmr(ibmr); | |
1738 | int ret = 0; | |
1739 | ||
1740 | if (check_mask & ~IB_MR_CHECK_SIG_STATUS) { | |
1741 | pr_err("Invalid status check mask\n"); | |
1742 | ret = -EINVAL; | |
1743 | goto done; | |
1744 | } | |
1745 | ||
1746 | mr_status->fail_status = 0; | |
1747 | if (check_mask & IB_MR_CHECK_SIG_STATUS) { | |
1748 | if (!mmr->sig) { | |
1749 | ret = -EINVAL; | |
1750 | pr_err("signature status check requested on a non-signature enabled MR\n"); | |
1751 | goto done; | |
1752 | } | |
1753 | ||
1754 | mmr->sig->sig_status_checked = true; | |
1755 | if (!mmr->sig->sig_err_exists) | |
1756 | goto done; | |
1757 | ||
1758 | if (ibmr->lkey == mmr->sig->err_item.key) | |
1759 | memcpy(&mr_status->sig_err, &mmr->sig->err_item, | |
1760 | sizeof(mr_status->sig_err)); | |
1761 | else { | |
1762 | mr_status->sig_err.err_type = IB_SIG_BAD_GUARD; | |
1763 | mr_status->sig_err.sig_err_offset = 0; | |
1764 | mr_status->sig_err.key = mmr->sig->err_item.key; | |
1765 | } | |
1766 | ||
1767 | mmr->sig->sig_err_exists = false; | |
1768 | mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; | |
1769 | } | |
1770 | ||
1771 | done: | |
1772 | return ret; | |
1773 | } | |
8a187ee5 | 1774 | |
b005d316 SG |
1775 | static int |
1776 | mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr, | |
1777 | struct scatterlist *sgl, | |
ff2ba993 | 1778 | unsigned short sg_nents, |
9aa8b321 | 1779 | unsigned int *sg_offset_p) |
b005d316 SG |
1780 | { |
1781 | struct scatterlist *sg = sgl; | |
1782 | struct mlx5_klm *klms = mr->descs; | |
9aa8b321 | 1783 | unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0; |
b005d316 SG |
1784 | u32 lkey = mr->ibmr.pd->local_dma_lkey; |
1785 | int i; | |
1786 | ||
ff2ba993 | 1787 | mr->ibmr.iova = sg_dma_address(sg) + sg_offset; |
b005d316 SG |
1788 | mr->ibmr.length = 0; |
1789 | mr->ndescs = sg_nents; | |
1790 | ||
1791 | for_each_sg(sgl, sg, sg_nents, i) { | |
99975cd4 | 1792 | if (unlikely(i >= mr->max_descs)) |
b005d316 | 1793 | break; |
ff2ba993 CH |
1794 | klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset); |
1795 | klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset); | |
b005d316 | 1796 | klms[i].key = cpu_to_be32(lkey); |
0a49f2c3 | 1797 | mr->ibmr.length += sg_dma_len(sg) - sg_offset; |
ff2ba993 CH |
1798 | |
1799 | sg_offset = 0; | |
b005d316 SG |
1800 | } |
1801 | ||
9aa8b321 BVA |
1802 | if (sg_offset_p) |
1803 | *sg_offset_p = sg_offset; | |
1804 | ||
b005d316 SG |
1805 | return i; |
1806 | } | |
1807 | ||
8a187ee5 SG |
1808 | static int mlx5_set_page(struct ib_mr *ibmr, u64 addr) |
1809 | { | |
1810 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1811 | __be64 *descs; | |
1812 | ||
1813 | if (unlikely(mr->ndescs == mr->max_descs)) | |
1814 | return -ENOMEM; | |
1815 | ||
1816 | descs = mr->descs; | |
1817 | descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR); | |
1818 | ||
1819 | return 0; | |
1820 | } | |
1821 | ||
ff2ba993 | 1822 | int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 1823 | unsigned int *sg_offset) |
8a187ee5 SG |
1824 | { |
1825 | struct mlx5_ib_mr *mr = to_mmr(ibmr); | |
1826 | int n; | |
1827 | ||
1828 | mr->ndescs = 0; | |
1829 | ||
1830 | ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map, | |
1831 | mr->desc_size * mr->max_descs, | |
1832 | DMA_TO_DEVICE); | |
1833 | ||
ec22eb53 | 1834 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
ff2ba993 | 1835 | n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset); |
b005d316 | 1836 | else |
ff2ba993 CH |
1837 | n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, |
1838 | mlx5_set_page); | |
8a187ee5 SG |
1839 | |
1840 | ib_dma_sync_single_for_device(ibmr->device, mr->desc_map, | |
1841 | mr->desc_size * mr->max_descs, | |
1842 | DMA_TO_DEVICE); | |
1843 | ||
1844 | return n; | |
1845 | } |