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8cdd312c | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
8cdd312c HE |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
7bdf65d4 HE |
33 | #include <rdma/ib_umem.h> |
34 | #include <rdma/ib_umem_odp.h> | |
35 | ||
8cdd312c | 36 | #include "mlx5_ib.h" |
81713d37 | 37 | #include "cmd.h" |
8cdd312c | 38 | |
eab668a6 HE |
39 | #define MAX_PREFETCH_LEN (4*1024*1024U) |
40 | ||
b4cfe447 HE |
41 | /* Timeout in ms to wait for an active mmu notifier to complete when handling |
42 | * a pagefault. */ | |
43 | #define MMU_NOTIFIER_TIMEOUT 1000 | |
44 | ||
81713d37 AK |
45 | #define MLX5_IMR_MTT_BITS (30 - PAGE_SHIFT) |
46 | #define MLX5_IMR_MTT_SHIFT (MLX5_IMR_MTT_BITS + PAGE_SHIFT) | |
47 | #define MLX5_IMR_MTT_ENTRIES BIT_ULL(MLX5_IMR_MTT_BITS) | |
48 | #define MLX5_IMR_MTT_SIZE BIT_ULL(MLX5_IMR_MTT_SHIFT) | |
49 | #define MLX5_IMR_MTT_MASK (~(MLX5_IMR_MTT_SIZE - 1)) | |
50 | ||
51 | #define MLX5_KSM_PAGE_SHIFT MLX5_IMR_MTT_SHIFT | |
52 | ||
53 | static u64 mlx5_imr_ksm_entries; | |
54 | ||
55 | static int check_parent(struct ib_umem_odp *odp, | |
56 | struct mlx5_ib_mr *parent) | |
57 | { | |
58 | struct mlx5_ib_mr *mr = odp->private; | |
59 | ||
523791d7 | 60 | return mr && mr->parent == parent && !odp->dying; |
81713d37 AK |
61 | } |
62 | ||
63 | static struct ib_umem_odp *odp_next(struct ib_umem_odp *odp) | |
64 | { | |
65 | struct mlx5_ib_mr *mr = odp->private, *parent = mr->parent; | |
66 | struct ib_ucontext *ctx = odp->umem->context; | |
67 | struct rb_node *rb; | |
68 | ||
69 | down_read(&ctx->umem_rwsem); | |
70 | while (1) { | |
71 | rb = rb_next(&odp->interval_tree.rb); | |
72 | if (!rb) | |
73 | goto not_found; | |
74 | odp = rb_entry(rb, struct ib_umem_odp, interval_tree.rb); | |
75 | if (check_parent(odp, parent)) | |
76 | goto end; | |
77 | } | |
78 | not_found: | |
79 | odp = NULL; | |
80 | end: | |
81 | up_read(&ctx->umem_rwsem); | |
82 | return odp; | |
83 | } | |
84 | ||
85 | static struct ib_umem_odp *odp_lookup(struct ib_ucontext *ctx, | |
86 | u64 start, u64 length, | |
87 | struct mlx5_ib_mr *parent) | |
88 | { | |
89 | struct ib_umem_odp *odp; | |
90 | struct rb_node *rb; | |
91 | ||
92 | down_read(&ctx->umem_rwsem); | |
93 | odp = rbt_ib_umem_lookup(&ctx->umem_tree, start, length); | |
94 | if (!odp) | |
95 | goto end; | |
96 | ||
97 | while (1) { | |
98 | if (check_parent(odp, parent)) | |
99 | goto end; | |
100 | rb = rb_next(&odp->interval_tree.rb); | |
101 | if (!rb) | |
102 | goto not_found; | |
103 | odp = rb_entry(rb, struct ib_umem_odp, interval_tree.rb); | |
104 | if (ib_umem_start(odp->umem) > start + length) | |
105 | goto not_found; | |
106 | } | |
107 | not_found: | |
108 | odp = NULL; | |
109 | end: | |
110 | up_read(&ctx->umem_rwsem); | |
111 | return odp; | |
112 | } | |
113 | ||
114 | void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset, | |
115 | size_t nentries, struct mlx5_ib_mr *mr, int flags) | |
116 | { | |
117 | struct ib_pd *pd = mr->ibmr.pd; | |
118 | struct ib_ucontext *ctx = pd->uobject->context; | |
119 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
120 | struct ib_umem_odp *odp; | |
121 | unsigned long va; | |
122 | int i; | |
123 | ||
124 | if (flags & MLX5_IB_UPD_XLT_ZAP) { | |
125 | for (i = 0; i < nentries; i++, pklm++) { | |
126 | pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE); | |
127 | pklm->key = cpu_to_be32(dev->null_mkey); | |
128 | pklm->va = 0; | |
129 | } | |
130 | return; | |
131 | } | |
132 | ||
133 | odp = odp_lookup(ctx, offset * MLX5_IMR_MTT_SIZE, | |
134 | nentries * MLX5_IMR_MTT_SIZE, mr); | |
135 | ||
136 | for (i = 0; i < nentries; i++, pklm++) { | |
137 | pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE); | |
138 | va = (offset + i) * MLX5_IMR_MTT_SIZE; | |
139 | if (odp && odp->umem->address == va) { | |
140 | struct mlx5_ib_mr *mtt = odp->private; | |
141 | ||
142 | pklm->key = cpu_to_be32(mtt->ibmr.lkey); | |
143 | odp = odp_next(odp); | |
144 | } else { | |
145 | pklm->key = cpu_to_be32(dev->null_mkey); | |
146 | } | |
147 | mlx5_ib_dbg(dev, "[%d] va %lx key %x\n", | |
148 | i, va, be32_to_cpu(pklm->key)); | |
149 | } | |
150 | } | |
151 | ||
152 | static void mr_leaf_free_action(struct work_struct *work) | |
153 | { | |
154 | struct ib_umem_odp *odp = container_of(work, struct ib_umem_odp, work); | |
155 | int idx = ib_umem_start(odp->umem) >> MLX5_IMR_MTT_SHIFT; | |
156 | struct mlx5_ib_mr *mr = odp->private, *imr = mr->parent; | |
157 | ||
158 | mr->parent = NULL; | |
159 | synchronize_srcu(&mr->dev->mr_srcu); | |
160 | ||
81713d37 AK |
161 | ib_umem_release(odp->umem); |
162 | if (imr->live) | |
163 | mlx5_ib_update_xlt(imr, idx, 1, 0, | |
164 | MLX5_IB_UPD_XLT_INDIRECT | | |
165 | MLX5_IB_UPD_XLT_ATOMIC); | |
166 | mlx5_mr_cache_free(mr->dev, mr); | |
167 | ||
168 | if (atomic_dec_and_test(&imr->num_leaf_free)) | |
169 | wake_up(&imr->q_leaf_free); | |
170 | } | |
171 | ||
b4cfe447 HE |
172 | void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start, |
173 | unsigned long end) | |
174 | { | |
175 | struct mlx5_ib_mr *mr; | |
31616255 AK |
176 | const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT / |
177 | sizeof(struct mlx5_mtt)) - 1; | |
b4cfe447 HE |
178 | u64 idx = 0, blk_start_idx = 0; |
179 | int in_block = 0; | |
180 | u64 addr; | |
181 | ||
182 | if (!umem || !umem->odp_data) { | |
183 | pr_err("invalidation called on NULL umem or non-ODP umem\n"); | |
184 | return; | |
185 | } | |
186 | ||
187 | mr = umem->odp_data->private; | |
188 | ||
189 | if (!mr || !mr->ibmr.pd) | |
190 | return; | |
191 | ||
192 | start = max_t(u64, ib_umem_start(umem), start); | |
193 | end = min_t(u64, ib_umem_end(umem), end); | |
194 | ||
195 | /* | |
196 | * Iteration one - zap the HW's MTTs. The notifiers_count ensures that | |
197 | * while we are doing the invalidation, no page fault will attempt to | |
198 | * overwrite the same MTTs. Concurent invalidations might race us, | |
199 | * but they will write 0s as well, so no difference in the end result. | |
200 | */ | |
201 | ||
3e7e1193 | 202 | for (addr = start; addr < end; addr += BIT(umem->page_shift)) { |
b4cfe447 HE |
203 | idx = (addr - ib_umem_start(umem)) / PAGE_SIZE; |
204 | /* | |
205 | * Strive to write the MTTs in chunks, but avoid overwriting | |
206 | * non-existing MTTs. The huristic here can be improved to | |
207 | * estimate the cost of another UMR vs. the cost of bigger | |
208 | * UMR. | |
209 | */ | |
210 | if (umem->odp_data->dma_list[idx] & | |
211 | (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) { | |
212 | if (!in_block) { | |
213 | blk_start_idx = idx; | |
214 | in_block = 1; | |
215 | } | |
216 | } else { | |
217 | u64 umr_offset = idx & umr_block_mask; | |
218 | ||
219 | if (in_block && umr_offset == 0) { | |
7d0cc6ed AK |
220 | mlx5_ib_update_xlt(mr, blk_start_idx, |
221 | idx - blk_start_idx, | |
222 | PAGE_SHIFT, | |
223 | MLX5_IB_UPD_XLT_ZAP | | |
224 | MLX5_IB_UPD_XLT_ATOMIC); | |
b4cfe447 HE |
225 | in_block = 0; |
226 | } | |
227 | } | |
228 | } | |
229 | if (in_block) | |
7d0cc6ed AK |
230 | mlx5_ib_update_xlt(mr, blk_start_idx, |
231 | idx - blk_start_idx + 1, | |
232 | PAGE_SHIFT, | |
233 | MLX5_IB_UPD_XLT_ZAP | | |
234 | MLX5_IB_UPD_XLT_ATOMIC); | |
b4cfe447 HE |
235 | /* |
236 | * We are now sure that the device will not access the | |
237 | * memory. We can safely unmap it, and mark it as dirty if | |
238 | * needed. | |
239 | */ | |
240 | ||
241 | ib_umem_odp_unmap_dma_pages(umem, start, end); | |
81713d37 AK |
242 | |
243 | if (unlikely(!umem->npages && mr->parent && | |
244 | !umem->odp_data->dying)) { | |
245 | WRITE_ONCE(umem->odp_data->dying, 1); | |
246 | atomic_inc(&mr->parent->num_leaf_free); | |
247 | schedule_work(&umem->odp_data->work); | |
248 | } | |
b4cfe447 HE |
249 | } |
250 | ||
938fe83c | 251 | void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) |
8cdd312c | 252 | { |
8cdd312c HE |
253 | struct ib_odp_caps *caps = &dev->odp_caps; |
254 | ||
255 | memset(caps, 0, sizeof(*caps)); | |
256 | ||
938fe83c SM |
257 | if (!MLX5_CAP_GEN(dev->mdev, pg)) |
258 | return; | |
8cdd312c | 259 | |
b4cfe447 | 260 | caps->general_caps = IB_ODP_SUPPORT; |
938fe83c | 261 | |
c438fde1 AK |
262 | if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) |
263 | dev->odp_max_size = U64_MAX; | |
264 | else | |
265 | dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT); | |
266 | ||
938fe83c SM |
267 | if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send)) |
268 | caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND; | |
269 | ||
270 | if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send)) | |
271 | caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND; | |
272 | ||
273 | if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive)) | |
274 | caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV; | |
275 | ||
276 | if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write)) | |
277 | caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE; | |
278 | ||
279 | if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read)) | |
280 | caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ; | |
281 | ||
17d2f88f AK |
282 | if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.atomic)) |
283 | caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_ATOMIC; | |
284 | ||
81713d37 AK |
285 | if (MLX5_CAP_GEN(dev->mdev, fixed_buffer_size) && |
286 | MLX5_CAP_GEN(dev->mdev, null_mkey) && | |
287 | MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) | |
288 | caps->general_caps |= IB_ODP_SUPPORT_IMPLICIT; | |
289 | ||
938fe83c | 290 | return; |
8cdd312c | 291 | } |
6aec21f6 HE |
292 | |
293 | static struct mlx5_ib_mr *mlx5_ib_odp_find_mr_lkey(struct mlx5_ib_dev *dev, | |
294 | u32 key) | |
295 | { | |
296 | u32 base_key = mlx5_base_mkey(key); | |
a606b0f6 | 297 | struct mlx5_core_mkey *mmkey = __mlx5_mr_lookup(dev->mdev, base_key); |
aa8e08d2 AK |
298 | struct mlx5_ib_mr *mr; |
299 | ||
300 | if (!mmkey || mmkey->key != key || mmkey->type != MLX5_MKEY_MR) | |
301 | return NULL; | |
302 | ||
303 | mr = container_of(mmkey, struct mlx5_ib_mr, mmkey); | |
6aec21f6 | 304 | |
aa8e08d2 | 305 | if (!mr->live) |
6aec21f6 HE |
306 | return NULL; |
307 | ||
a606b0f6 | 308 | return container_of(mmkey, struct mlx5_ib_mr, mmkey); |
6aec21f6 HE |
309 | } |
310 | ||
d9aaed83 AK |
311 | static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev, |
312 | struct mlx5_pagefault *pfault, | |
19098df2 | 313 | int error) |
314 | { | |
d9aaed83 AK |
315 | int wq_num = pfault->event_subtype == MLX5_PFAULT_SUBTYPE_WQE ? |
316 | pfault->wqe.wq_num : pfault->token; | |
19098df2 | 317 | int ret = mlx5_core_page_fault_resume(dev->mdev, |
d9aaed83 AK |
318 | pfault->token, |
319 | wq_num, | |
320 | pfault->type, | |
6aec21f6 HE |
321 | error); |
322 | if (ret) | |
d9aaed83 AK |
323 | mlx5_ib_err(dev, "Failed to resolve the page fault on WQ 0x%x\n", |
324 | wq_num); | |
6aec21f6 HE |
325 | } |
326 | ||
81713d37 AK |
327 | static struct mlx5_ib_mr *implicit_mr_alloc(struct ib_pd *pd, |
328 | struct ib_umem *umem, | |
329 | bool ksm, int access_flags) | |
330 | { | |
331 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
332 | struct mlx5_ib_mr *mr; | |
333 | int err; | |
334 | ||
335 | mr = mlx5_mr_cache_alloc(dev, ksm ? MLX5_IMR_KSM_CACHE_ENTRY : | |
336 | MLX5_IMR_MTT_CACHE_ENTRY); | |
337 | ||
338 | if (IS_ERR(mr)) | |
339 | return mr; | |
340 | ||
341 | mr->ibmr.pd = pd; | |
342 | ||
343 | mr->dev = dev; | |
344 | mr->access_flags = access_flags; | |
345 | mr->mmkey.iova = 0; | |
346 | mr->umem = umem; | |
347 | ||
348 | if (ksm) { | |
349 | err = mlx5_ib_update_xlt(mr, 0, | |
350 | mlx5_imr_ksm_entries, | |
351 | MLX5_KSM_PAGE_SHIFT, | |
352 | MLX5_IB_UPD_XLT_INDIRECT | | |
353 | MLX5_IB_UPD_XLT_ZAP | | |
354 | MLX5_IB_UPD_XLT_ENABLE); | |
355 | ||
356 | } else { | |
357 | err = mlx5_ib_update_xlt(mr, 0, | |
358 | MLX5_IMR_MTT_ENTRIES, | |
359 | PAGE_SHIFT, | |
360 | MLX5_IB_UPD_XLT_ZAP | | |
361 | MLX5_IB_UPD_XLT_ENABLE | | |
362 | MLX5_IB_UPD_XLT_ATOMIC); | |
363 | } | |
364 | ||
365 | if (err) | |
366 | goto fail; | |
367 | ||
368 | mr->ibmr.lkey = mr->mmkey.key; | |
369 | mr->ibmr.rkey = mr->mmkey.key; | |
370 | ||
371 | mr->live = 1; | |
372 | ||
373 | mlx5_ib_dbg(dev, "key %x dev %p mr %p\n", | |
374 | mr->mmkey.key, dev->mdev, mr); | |
375 | ||
376 | return mr; | |
377 | ||
378 | fail: | |
379 | mlx5_ib_err(dev, "Failed to register MKEY %d\n", err); | |
380 | mlx5_mr_cache_free(dev, mr); | |
381 | ||
382 | return ERR_PTR(err); | |
383 | } | |
384 | ||
385 | static struct ib_umem_odp *implicit_mr_get_data(struct mlx5_ib_mr *mr, | |
386 | u64 io_virt, size_t bcnt) | |
387 | { | |
388 | struct ib_ucontext *ctx = mr->ibmr.pd->uobject->context; | |
389 | struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.pd->device); | |
390 | struct ib_umem_odp *odp, *result = NULL; | |
391 | u64 addr = io_virt & MLX5_IMR_MTT_MASK; | |
392 | int nentries = 0, start_idx = 0, ret; | |
393 | struct mlx5_ib_mr *mtt; | |
394 | struct ib_umem *umem; | |
395 | ||
396 | mutex_lock(&mr->umem->odp_data->umem_mutex); | |
397 | odp = odp_lookup(ctx, addr, 1, mr); | |
398 | ||
399 | mlx5_ib_dbg(dev, "io_virt:%llx bcnt:%zx addr:%llx odp:%p\n", | |
400 | io_virt, bcnt, addr, odp); | |
401 | ||
402 | next_mr: | |
403 | if (likely(odp)) { | |
404 | if (nentries) | |
405 | nentries++; | |
406 | } else { | |
407 | umem = ib_alloc_odp_umem(ctx, addr, MLX5_IMR_MTT_SIZE); | |
408 | if (IS_ERR(umem)) { | |
409 | mutex_unlock(&mr->umem->odp_data->umem_mutex); | |
410 | return ERR_CAST(umem); | |
411 | } | |
412 | ||
413 | mtt = implicit_mr_alloc(mr->ibmr.pd, umem, 0, mr->access_flags); | |
414 | if (IS_ERR(mtt)) { | |
415 | mutex_unlock(&mr->umem->odp_data->umem_mutex); | |
416 | ib_umem_release(umem); | |
417 | return ERR_CAST(mtt); | |
418 | } | |
419 | ||
420 | odp = umem->odp_data; | |
421 | odp->private = mtt; | |
422 | mtt->umem = umem; | |
423 | mtt->mmkey.iova = addr; | |
424 | mtt->parent = mr; | |
425 | INIT_WORK(&odp->work, mr_leaf_free_action); | |
426 | ||
427 | if (!nentries) | |
428 | start_idx = addr >> MLX5_IMR_MTT_SHIFT; | |
429 | nentries++; | |
430 | } | |
431 | ||
81713d37 AK |
432 | /* Return first odp if region not covered by single one */ |
433 | if (likely(!result)) | |
434 | result = odp; | |
435 | ||
436 | addr += MLX5_IMR_MTT_SIZE; | |
437 | if (unlikely(addr < io_virt + bcnt)) { | |
438 | odp = odp_next(odp); | |
439 | if (odp && odp->umem->address != addr) | |
440 | odp = NULL; | |
441 | goto next_mr; | |
442 | } | |
443 | ||
444 | if (unlikely(nentries)) { | |
445 | ret = mlx5_ib_update_xlt(mr, start_idx, nentries, 0, | |
446 | MLX5_IB_UPD_XLT_INDIRECT | | |
447 | MLX5_IB_UPD_XLT_ATOMIC); | |
448 | if (ret) { | |
449 | mlx5_ib_err(dev, "Failed to update PAS\n"); | |
450 | result = ERR_PTR(ret); | |
451 | } | |
452 | } | |
453 | ||
454 | mutex_unlock(&mr->umem->odp_data->umem_mutex); | |
455 | return result; | |
456 | } | |
457 | ||
458 | struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, | |
459 | int access_flags) | |
460 | { | |
461 | struct ib_ucontext *ctx = pd->ibpd.uobject->context; | |
462 | struct mlx5_ib_mr *imr; | |
463 | struct ib_umem *umem; | |
464 | ||
465 | umem = ib_umem_get(ctx, 0, 0, IB_ACCESS_ON_DEMAND, 0); | |
466 | if (IS_ERR(umem)) | |
467 | return ERR_CAST(umem); | |
468 | ||
469 | imr = implicit_mr_alloc(&pd->ibpd, umem, 1, access_flags); | |
470 | if (IS_ERR(imr)) { | |
471 | ib_umem_release(umem); | |
472 | return ERR_CAST(imr); | |
473 | } | |
474 | ||
475 | imr->umem = umem; | |
476 | init_waitqueue_head(&imr->q_leaf_free); | |
477 | atomic_set(&imr->num_leaf_free, 0); | |
478 | ||
479 | return imr; | |
480 | } | |
481 | ||
482 | static int mr_leaf_free(struct ib_umem *umem, u64 start, | |
483 | u64 end, void *cookie) | |
484 | { | |
485 | struct mlx5_ib_mr *mr = umem->odp_data->private, *imr = cookie; | |
486 | ||
487 | if (mr->parent != imr) | |
488 | return 0; | |
489 | ||
490 | ib_umem_odp_unmap_dma_pages(umem, | |
491 | ib_umem_start(umem), | |
492 | ib_umem_end(umem)); | |
493 | ||
494 | if (umem->odp_data->dying) | |
495 | return 0; | |
496 | ||
497 | WRITE_ONCE(umem->odp_data->dying, 1); | |
498 | atomic_inc(&imr->num_leaf_free); | |
499 | schedule_work(&umem->odp_data->work); | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *imr) | |
505 | { | |
506 | struct ib_ucontext *ctx = imr->ibmr.pd->uobject->context; | |
507 | ||
508 | down_read(&ctx->umem_rwsem); | |
509 | rbt_ib_umem_for_each_in_range(&ctx->umem_tree, 0, ULLONG_MAX, | |
510 | mr_leaf_free, imr); | |
511 | up_read(&ctx->umem_rwsem); | |
512 | ||
513 | wait_event(imr->q_leaf_free, !atomic_read(&imr->num_leaf_free)); | |
514 | } | |
515 | ||
7bdf65d4 | 516 | /* |
d9aaed83 | 517 | * Handle a single data segment in a page-fault WQE or RDMA region. |
7bdf65d4 | 518 | * |
d9aaed83 | 519 | * Returns number of pages retrieved on success. The caller may continue to |
7bdf65d4 HE |
520 | * the next data segment. |
521 | * Can return the following error codes: | |
522 | * -EAGAIN to designate a temporary error. The caller will abort handling the | |
523 | * page fault and resolve it. | |
524 | * -EFAULT when there's an error mapping the requested pages. The caller will | |
d9aaed83 | 525 | * abort the page fault handling. |
7bdf65d4 | 526 | */ |
81713d37 | 527 | static int pagefault_single_data_segment(struct mlx5_ib_dev *dev, |
7bdf65d4 | 528 | u32 key, u64 io_virt, size_t bcnt, |
d9aaed83 | 529 | u32 *bytes_committed, |
7bdf65d4 HE |
530 | u32 *bytes_mapped) |
531 | { | |
7bdf65d4 | 532 | int srcu_key; |
81713d37 | 533 | unsigned int current_seq = 0; |
7bdf65d4 HE |
534 | u64 start_idx; |
535 | int npages = 0, ret = 0; | |
536 | struct mlx5_ib_mr *mr; | |
537 | u64 access_mask = ODP_READ_ALLOWED_BIT; | |
81713d37 AK |
538 | struct ib_umem_odp *odp; |
539 | int implicit = 0; | |
540 | size_t size; | |
7bdf65d4 | 541 | |
81713d37 AK |
542 | srcu_key = srcu_read_lock(&dev->mr_srcu); |
543 | mr = mlx5_ib_odp_find_mr_lkey(dev, key); | |
7bdf65d4 HE |
544 | /* |
545 | * If we didn't find the MR, it means the MR was closed while we were | |
546 | * handling the ODP event. In this case we return -EFAULT so that the | |
547 | * QP will be closed. | |
548 | */ | |
549 | if (!mr || !mr->ibmr.pd) { | |
81713d37 AK |
550 | mlx5_ib_dbg(dev, "Failed to find relevant mr for lkey=0x%06x, probably the MR was destroyed\n", |
551 | key); | |
7bdf65d4 HE |
552 | ret = -EFAULT; |
553 | goto srcu_unlock; | |
554 | } | |
555 | if (!mr->umem->odp_data) { | |
81713d37 AK |
556 | mlx5_ib_dbg(dev, "skipping non ODP MR (lkey=0x%06x) in page fault handler.\n", |
557 | key); | |
7bdf65d4 HE |
558 | if (bytes_mapped) |
559 | *bytes_mapped += | |
d9aaed83 | 560 | (bcnt - *bytes_committed); |
7bdf65d4 HE |
561 | goto srcu_unlock; |
562 | } | |
563 | ||
7bdf65d4 HE |
564 | /* |
565 | * Avoid branches - this code will perform correctly | |
566 | * in all iterations (in iteration 2 and above, | |
567 | * bytes_committed == 0). | |
568 | */ | |
d9aaed83 AK |
569 | io_virt += *bytes_committed; |
570 | bcnt -= *bytes_committed; | |
7bdf65d4 | 571 | |
81713d37 AK |
572 | if (!mr->umem->odp_data->page_list) { |
573 | odp = implicit_mr_get_data(mr, io_virt, bcnt); | |
574 | ||
575 | if (IS_ERR(odp)) { | |
576 | ret = PTR_ERR(odp); | |
577 | goto srcu_unlock; | |
578 | } | |
579 | mr = odp->private; | |
580 | implicit = 1; | |
581 | ||
582 | } else { | |
583 | odp = mr->umem->odp_data; | |
584 | } | |
585 | ||
586 | next_mr: | |
587 | current_seq = READ_ONCE(odp->notifiers_seq); | |
588 | /* | |
589 | * Ensure the sequence number is valid for some time before we call | |
590 | * gup. | |
591 | */ | |
592 | smp_rmb(); | |
593 | ||
594 | size = min_t(size_t, bcnt, ib_umem_end(odp->umem) - io_virt); | |
a606b0f6 | 595 | start_idx = (io_virt - (mr->mmkey.iova & PAGE_MASK)) >> PAGE_SHIFT; |
7bdf65d4 HE |
596 | |
597 | if (mr->umem->writable) | |
598 | access_mask |= ODP_WRITE_ALLOWED_BIT; | |
81713d37 AK |
599 | |
600 | ret = ib_umem_odp_map_dma_pages(mr->umem, io_virt, size, | |
601 | access_mask, current_seq); | |
602 | ||
603 | if (ret < 0) | |
7bdf65d4 | 604 | goto srcu_unlock; |
7bdf65d4 | 605 | |
81713d37 AK |
606 | if (ret > 0) { |
607 | int np = ret; | |
608 | ||
609 | mutex_lock(&odp->umem_mutex); | |
b4cfe447 HE |
610 | if (!ib_umem_mmu_notifier_retry(mr->umem, current_seq)) { |
611 | /* | |
612 | * No need to check whether the MTTs really belong to | |
613 | * this MR, since ib_umem_odp_map_dma_pages already | |
614 | * checks this. | |
615 | */ | |
81713d37 | 616 | ret = mlx5_ib_update_xlt(mr, start_idx, np, |
7d0cc6ed AK |
617 | PAGE_SHIFT, |
618 | MLX5_IB_UPD_XLT_ATOMIC); | |
b4cfe447 HE |
619 | } else { |
620 | ret = -EAGAIN; | |
621 | } | |
81713d37 | 622 | mutex_unlock(&odp->umem_mutex); |
7bdf65d4 | 623 | if (ret < 0) { |
b4cfe447 | 624 | if (ret != -EAGAIN) |
81713d37 | 625 | mlx5_ib_err(dev, "Failed to update mkey page tables\n"); |
7bdf65d4 HE |
626 | goto srcu_unlock; |
627 | } | |
628 | ||
629 | if (bytes_mapped) { | |
81713d37 | 630 | u32 new_mappings = np * PAGE_SIZE - |
7bdf65d4 | 631 | (io_virt - round_down(io_virt, PAGE_SIZE)); |
81713d37 | 632 | *bytes_mapped += min_t(u32, new_mappings, size); |
7bdf65d4 | 633 | } |
81713d37 AK |
634 | |
635 | npages += np; | |
636 | } | |
637 | ||
638 | bcnt -= size; | |
639 | if (unlikely(bcnt)) { | |
640 | struct ib_umem_odp *next; | |
641 | ||
642 | io_virt += size; | |
643 | next = odp_next(odp); | |
644 | if (unlikely(!next || next->umem->address != io_virt)) { | |
645 | mlx5_ib_dbg(dev, "next implicit leaf removed at 0x%llx. got %p\n", | |
646 | io_virt, next); | |
647 | ret = -EAGAIN; | |
648 | goto srcu_unlock_no_wait; | |
649 | } | |
650 | odp = next; | |
651 | mr = odp->private; | |
652 | goto next_mr; | |
7bdf65d4 HE |
653 | } |
654 | ||
655 | srcu_unlock: | |
b4cfe447 | 656 | if (ret == -EAGAIN) { |
81713d37 | 657 | if (implicit || !odp->dying) { |
b4cfe447 HE |
658 | unsigned long timeout = |
659 | msecs_to_jiffies(MMU_NOTIFIER_TIMEOUT); | |
660 | ||
661 | if (!wait_for_completion_timeout( | |
81713d37 | 662 | &odp->notifier_completion, |
b4cfe447 | 663 | timeout)) { |
81713d37 AK |
664 | mlx5_ib_warn(dev, "timeout waiting for mmu notifier. seq %d against %d\n", |
665 | current_seq, odp->notifiers_seq); | |
b4cfe447 HE |
666 | } |
667 | } else { | |
668 | /* The MR is being killed, kill the QP as well. */ | |
669 | ret = -EFAULT; | |
670 | } | |
671 | } | |
81713d37 AK |
672 | |
673 | srcu_unlock_no_wait: | |
674 | srcu_read_unlock(&dev->mr_srcu, srcu_key); | |
d9aaed83 | 675 | *bytes_committed = 0; |
7bdf65d4 HE |
676 | return ret ? ret : npages; |
677 | } | |
678 | ||
679 | /** | |
680 | * Parse a series of data segments for page fault handling. | |
681 | * | |
682 | * @qp the QP on which the fault occurred. | |
683 | * @pfault contains page fault information. | |
684 | * @wqe points at the first data segment in the WQE. | |
685 | * @wqe_end points after the end of the WQE. | |
686 | * @bytes_mapped receives the number of bytes that the function was able to | |
687 | * map. This allows the caller to decide intelligently whether | |
688 | * enough memory was mapped to resolve the page fault | |
689 | * successfully (e.g. enough for the next MTU, or the entire | |
690 | * WQE). | |
691 | * @total_wqe_bytes receives the total data size of this WQE in bytes (minus | |
692 | * the committed bytes). | |
693 | * | |
694 | * Returns the number of pages loaded if positive, zero for an empty WQE, or a | |
695 | * negative error code. | |
696 | */ | |
d9aaed83 AK |
697 | static int pagefault_data_segments(struct mlx5_ib_dev *dev, |
698 | struct mlx5_pagefault *pfault, | |
699 | struct mlx5_ib_qp *qp, void *wqe, | |
7bdf65d4 HE |
700 | void *wqe_end, u32 *bytes_mapped, |
701 | u32 *total_wqe_bytes, int receive_queue) | |
702 | { | |
703 | int ret = 0, npages = 0; | |
704 | u64 io_virt; | |
705 | u32 key; | |
706 | u32 byte_count; | |
707 | size_t bcnt; | |
708 | int inline_segment; | |
709 | ||
710 | /* Skip SRQ next-WQE segment. */ | |
711 | if (receive_queue && qp->ibqp.srq) | |
712 | wqe += sizeof(struct mlx5_wqe_srq_next_seg); | |
713 | ||
714 | if (bytes_mapped) | |
715 | *bytes_mapped = 0; | |
716 | if (total_wqe_bytes) | |
717 | *total_wqe_bytes = 0; | |
718 | ||
719 | while (wqe < wqe_end) { | |
720 | struct mlx5_wqe_data_seg *dseg = wqe; | |
721 | ||
722 | io_virt = be64_to_cpu(dseg->addr); | |
723 | key = be32_to_cpu(dseg->lkey); | |
724 | byte_count = be32_to_cpu(dseg->byte_count); | |
725 | inline_segment = !!(byte_count & MLX5_INLINE_SEG); | |
726 | bcnt = byte_count & ~MLX5_INLINE_SEG; | |
727 | ||
728 | if (inline_segment) { | |
729 | bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK; | |
730 | wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt, | |
731 | 16); | |
732 | } else { | |
733 | wqe += sizeof(*dseg); | |
734 | } | |
735 | ||
736 | /* receive WQE end of sg list. */ | |
737 | if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY && | |
738 | io_virt == 0) | |
739 | break; | |
740 | ||
741 | if (!inline_segment && total_wqe_bytes) { | |
742 | *total_wqe_bytes += bcnt - min_t(size_t, bcnt, | |
d9aaed83 | 743 | pfault->bytes_committed); |
7bdf65d4 HE |
744 | } |
745 | ||
746 | /* A zero length data segment designates a length of 2GB. */ | |
747 | if (bcnt == 0) | |
748 | bcnt = 1U << 31; | |
749 | ||
d9aaed83 AK |
750 | if (inline_segment || bcnt <= pfault->bytes_committed) { |
751 | pfault->bytes_committed -= | |
7bdf65d4 | 752 | min_t(size_t, bcnt, |
d9aaed83 | 753 | pfault->bytes_committed); |
7bdf65d4 HE |
754 | continue; |
755 | } | |
756 | ||
d9aaed83 AK |
757 | ret = pagefault_single_data_segment(dev, key, io_virt, bcnt, |
758 | &pfault->bytes_committed, | |
759 | bytes_mapped); | |
7bdf65d4 HE |
760 | if (ret < 0) |
761 | break; | |
762 | npages += ret; | |
763 | } | |
764 | ||
765 | return ret < 0 ? ret : npages; | |
766 | } | |
767 | ||
17d2f88f AK |
768 | static const u32 mlx5_ib_odp_opcode_cap[] = { |
769 | [MLX5_OPCODE_SEND] = IB_ODP_SUPPORT_SEND, | |
770 | [MLX5_OPCODE_SEND_IMM] = IB_ODP_SUPPORT_SEND, | |
771 | [MLX5_OPCODE_SEND_INVAL] = IB_ODP_SUPPORT_SEND, | |
772 | [MLX5_OPCODE_RDMA_WRITE] = IB_ODP_SUPPORT_WRITE, | |
773 | [MLX5_OPCODE_RDMA_WRITE_IMM] = IB_ODP_SUPPORT_WRITE, | |
774 | [MLX5_OPCODE_RDMA_READ] = IB_ODP_SUPPORT_READ, | |
775 | [MLX5_OPCODE_ATOMIC_CS] = IB_ODP_SUPPORT_ATOMIC, | |
776 | [MLX5_OPCODE_ATOMIC_FA] = IB_ODP_SUPPORT_ATOMIC, | |
777 | }; | |
778 | ||
7bdf65d4 HE |
779 | /* |
780 | * Parse initiator WQE. Advances the wqe pointer to point at the | |
781 | * scatter-gather list, and set wqe_end to the end of the WQE. | |
782 | */ | |
783 | static int mlx5_ib_mr_initiator_pfault_handler( | |
d9aaed83 AK |
784 | struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault, |
785 | struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length) | |
7bdf65d4 | 786 | { |
7bdf65d4 | 787 | struct mlx5_wqe_ctrl_seg *ctrl = *wqe; |
d9aaed83 | 788 | u16 wqe_index = pfault->wqe.wqe_index; |
17d2f88f AK |
789 | u32 transport_caps; |
790 | struct mlx5_base_av *av; | |
7bdf65d4 HE |
791 | unsigned ds, opcode; |
792 | #if defined(DEBUG) | |
793 | u32 ctrl_wqe_index, ctrl_qpn; | |
794 | #endif | |
19098df2 | 795 | u32 qpn = qp->trans_qp.base.mqp.qpn; |
7bdf65d4 HE |
796 | |
797 | ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; | |
798 | if (ds * MLX5_WQE_DS_UNITS > wqe_length) { | |
799 | mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n", | |
800 | ds, wqe_length); | |
801 | return -EFAULT; | |
802 | } | |
803 | ||
804 | if (ds == 0) { | |
805 | mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n", | |
19098df2 | 806 | wqe_index, qpn); |
7bdf65d4 HE |
807 | return -EFAULT; |
808 | } | |
809 | ||
810 | #if defined(DEBUG) | |
811 | ctrl_wqe_index = (be32_to_cpu(ctrl->opmod_idx_opcode) & | |
812 | MLX5_WQE_CTRL_WQE_INDEX_MASK) >> | |
813 | MLX5_WQE_CTRL_WQE_INDEX_SHIFT; | |
814 | if (wqe_index != ctrl_wqe_index) { | |
815 | mlx5_ib_err(dev, "Got WQE with invalid wqe_index. wqe_index=0x%x, qpn=0x%x ctrl->wqe_index=0x%x\n", | |
19098df2 | 816 | wqe_index, qpn, |
7bdf65d4 HE |
817 | ctrl_wqe_index); |
818 | return -EFAULT; | |
819 | } | |
820 | ||
821 | ctrl_qpn = (be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_QPN_MASK) >> | |
822 | MLX5_WQE_CTRL_QPN_SHIFT; | |
19098df2 | 823 | if (qpn != ctrl_qpn) { |
7bdf65d4 | 824 | mlx5_ib_err(dev, "Got WQE with incorrect QP number. wqe_index=0x%x, qpn=0x%x ctrl->qpn=0x%x\n", |
19098df2 | 825 | wqe_index, qpn, |
7bdf65d4 HE |
826 | ctrl_qpn); |
827 | return -EFAULT; | |
828 | } | |
829 | #endif /* DEBUG */ | |
830 | ||
831 | *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS; | |
832 | *wqe += sizeof(*ctrl); | |
833 | ||
834 | opcode = be32_to_cpu(ctrl->opmod_idx_opcode) & | |
835 | MLX5_WQE_CTRL_OPCODE_MASK; | |
17d2f88f | 836 | |
7bdf65d4 HE |
837 | switch (qp->ibqp.qp_type) { |
838 | case IB_QPT_RC: | |
17d2f88f | 839 | transport_caps = dev->odp_caps.per_transport_caps.rc_odp_caps; |
7bdf65d4 HE |
840 | break; |
841 | case IB_QPT_UD: | |
17d2f88f | 842 | transport_caps = dev->odp_caps.per_transport_caps.ud_odp_caps; |
7bdf65d4 HE |
843 | break; |
844 | default: | |
17d2f88f AK |
845 | mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport 0x%x\n", |
846 | qp->ibqp.qp_type); | |
7bdf65d4 HE |
847 | return -EFAULT; |
848 | } | |
849 | ||
17d2f88f AK |
850 | if (unlikely(opcode >= sizeof(mlx5_ib_odp_opcode_cap) / |
851 | sizeof(mlx5_ib_odp_opcode_cap[0]) || | |
852 | !(transport_caps & mlx5_ib_odp_opcode_cap[opcode]))) { | |
853 | mlx5_ib_err(dev, "ODP fault on QP of an unsupported opcode 0x%x\n", | |
854 | opcode); | |
855 | return -EFAULT; | |
856 | } | |
857 | ||
858 | if (qp->ibqp.qp_type != IB_QPT_RC) { | |
859 | av = *wqe; | |
860 | if (av->dqp_dct & be32_to_cpu(MLX5_WQE_AV_EXT)) | |
861 | *wqe += sizeof(struct mlx5_av); | |
862 | else | |
863 | *wqe += sizeof(struct mlx5_base_av); | |
864 | } | |
865 | ||
866 | switch (opcode) { | |
867 | case MLX5_OPCODE_RDMA_WRITE: | |
868 | case MLX5_OPCODE_RDMA_WRITE_IMM: | |
869 | case MLX5_OPCODE_RDMA_READ: | |
870 | *wqe += sizeof(struct mlx5_wqe_raddr_seg); | |
871 | break; | |
872 | case MLX5_OPCODE_ATOMIC_CS: | |
873 | case MLX5_OPCODE_ATOMIC_FA: | |
874 | *wqe += sizeof(struct mlx5_wqe_raddr_seg); | |
875 | *wqe += sizeof(struct mlx5_wqe_atomic_seg); | |
876 | break; | |
877 | } | |
878 | ||
7bdf65d4 HE |
879 | return 0; |
880 | } | |
881 | ||
882 | /* | |
883 | * Parse responder WQE. Advances the wqe pointer to point at the | |
884 | * scatter-gather list, and set wqe_end to the end of the WQE. | |
885 | */ | |
886 | static int mlx5_ib_mr_responder_pfault_handler( | |
d9aaed83 AK |
887 | struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault, |
888 | struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length) | |
7bdf65d4 | 889 | { |
7bdf65d4 HE |
890 | struct mlx5_ib_wq *wq = &qp->rq; |
891 | int wqe_size = 1 << wq->wqe_shift; | |
892 | ||
893 | if (qp->ibqp.srq) { | |
894 | mlx5_ib_err(dev, "ODP fault on SRQ is not supported\n"); | |
895 | return -EFAULT; | |
896 | } | |
897 | ||
898 | if (qp->wq_sig) { | |
899 | mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n"); | |
900 | return -EFAULT; | |
901 | } | |
902 | ||
903 | if (wqe_size > wqe_length) { | |
904 | mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n"); | |
905 | return -EFAULT; | |
906 | } | |
907 | ||
908 | switch (qp->ibqp.qp_type) { | |
909 | case IB_QPT_RC: | |
910 | if (!(dev->odp_caps.per_transport_caps.rc_odp_caps & | |
911 | IB_ODP_SUPPORT_RECV)) | |
912 | goto invalid_transport_or_opcode; | |
913 | break; | |
914 | default: | |
915 | invalid_transport_or_opcode: | |
916 | mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport. transport: 0x%x\n", | |
917 | qp->ibqp.qp_type); | |
918 | return -EFAULT; | |
919 | } | |
920 | ||
921 | *wqe_end = *wqe + wqe_size; | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
d9aaed83 AK |
926 | static struct mlx5_ib_qp *mlx5_ib_odp_find_qp(struct mlx5_ib_dev *dev, |
927 | u32 wq_num) | |
928 | { | |
929 | struct mlx5_core_qp *mqp = __mlx5_qp_lookup(dev->mdev, wq_num); | |
930 | ||
931 | if (!mqp) { | |
932 | mlx5_ib_err(dev, "QPN 0x%6x not found\n", wq_num); | |
933 | return NULL; | |
934 | } | |
935 | ||
936 | return to_mibqp(mqp); | |
937 | } | |
938 | ||
939 | static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev *dev, | |
940 | struct mlx5_pagefault *pfault) | |
7bdf65d4 | 941 | { |
7bdf65d4 HE |
942 | int ret; |
943 | void *wqe, *wqe_end; | |
944 | u32 bytes_mapped, total_wqe_bytes; | |
945 | char *buffer = NULL; | |
d9aaed83 AK |
946 | int resume_with_error = 1; |
947 | u16 wqe_index = pfault->wqe.wqe_index; | |
948 | int requestor = pfault->type & MLX5_PFAULT_REQUESTOR; | |
949 | struct mlx5_ib_qp *qp; | |
7bdf65d4 HE |
950 | |
951 | buffer = (char *)__get_free_page(GFP_KERNEL); | |
952 | if (!buffer) { | |
953 | mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n"); | |
7bdf65d4 HE |
954 | goto resolve_page_fault; |
955 | } | |
956 | ||
d9aaed83 AK |
957 | qp = mlx5_ib_odp_find_qp(dev, pfault->wqe.wq_num); |
958 | if (!qp) | |
959 | goto resolve_page_fault; | |
960 | ||
7bdf65d4 | 961 | ret = mlx5_ib_read_user_wqe(qp, requestor, wqe_index, buffer, |
19098df2 | 962 | PAGE_SIZE, &qp->trans_qp.base); |
7bdf65d4 | 963 | if (ret < 0) { |
d9aaed83 AK |
964 | mlx5_ib_err(dev, "Failed reading a WQE following page fault, error=%d, wqe_index=%x, qpn=%x\n", |
965 | ret, wqe_index, pfault->token); | |
7bdf65d4 HE |
966 | goto resolve_page_fault; |
967 | } | |
968 | ||
969 | wqe = buffer; | |
970 | if (requestor) | |
d9aaed83 | 971 | ret = mlx5_ib_mr_initiator_pfault_handler(dev, pfault, qp, &wqe, |
7bdf65d4 HE |
972 | &wqe_end, ret); |
973 | else | |
d9aaed83 | 974 | ret = mlx5_ib_mr_responder_pfault_handler(dev, pfault, qp, &wqe, |
7bdf65d4 | 975 | &wqe_end, ret); |
d9aaed83 | 976 | if (ret < 0) |
7bdf65d4 | 977 | goto resolve_page_fault; |
7bdf65d4 HE |
978 | |
979 | if (wqe >= wqe_end) { | |
980 | mlx5_ib_err(dev, "ODP fault on invalid WQE.\n"); | |
7bdf65d4 HE |
981 | goto resolve_page_fault; |
982 | } | |
983 | ||
d9aaed83 AK |
984 | ret = pagefault_data_segments(dev, pfault, qp, wqe, wqe_end, |
985 | &bytes_mapped, &total_wqe_bytes, | |
986 | !requestor); | |
7bdf65d4 | 987 | if (ret == -EAGAIN) { |
d9aaed83 | 988 | resume_with_error = 0; |
7bdf65d4 HE |
989 | goto resolve_page_fault; |
990 | } else if (ret < 0 || total_wqe_bytes > bytes_mapped) { | |
7bdf65d4 HE |
991 | goto resolve_page_fault; |
992 | } | |
993 | ||
d9aaed83 | 994 | resume_with_error = 0; |
7bdf65d4 | 995 | resolve_page_fault: |
d9aaed83 AK |
996 | mlx5_ib_page_fault_resume(dev, pfault, resume_with_error); |
997 | mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, type: 0x%x\n", | |
81713d37 | 998 | pfault->wqe.wq_num, resume_with_error, |
d9aaed83 | 999 | pfault->type); |
7bdf65d4 HE |
1000 | free_page((unsigned long)buffer); |
1001 | } | |
1002 | ||
eab668a6 HE |
1003 | static int pages_in_range(u64 address, u32 length) |
1004 | { | |
1005 | return (ALIGN(address + length, PAGE_SIZE) - | |
1006 | (address & PAGE_MASK)) >> PAGE_SHIFT; | |
1007 | } | |
1008 | ||
d9aaed83 AK |
1009 | static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev, |
1010 | struct mlx5_pagefault *pfault) | |
eab668a6 | 1011 | { |
eab668a6 HE |
1012 | u64 address; |
1013 | u32 length; | |
d9aaed83 | 1014 | u32 prefetch_len = pfault->bytes_committed; |
eab668a6 | 1015 | int prefetch_activated = 0; |
d9aaed83 | 1016 | u32 rkey = pfault->rdma.r_key; |
eab668a6 HE |
1017 | int ret; |
1018 | ||
1019 | /* The RDMA responder handler handles the page fault in two parts. | |
1020 | * First it brings the necessary pages for the current packet | |
1021 | * (and uses the pfault context), and then (after resuming the QP) | |
1022 | * prefetches more pages. The second operation cannot use the pfault | |
1023 | * context and therefore uses the dummy_pfault context allocated on | |
1024 | * the stack */ | |
d9aaed83 AK |
1025 | pfault->rdma.rdma_va += pfault->bytes_committed; |
1026 | pfault->rdma.rdma_op_len -= min(pfault->bytes_committed, | |
1027 | pfault->rdma.rdma_op_len); | |
1028 | pfault->bytes_committed = 0; | |
eab668a6 | 1029 | |
d9aaed83 AK |
1030 | address = pfault->rdma.rdma_va; |
1031 | length = pfault->rdma.rdma_op_len; | |
eab668a6 HE |
1032 | |
1033 | /* For some operations, the hardware cannot tell the exact message | |
1034 | * length, and in those cases it reports zero. Use prefetch | |
1035 | * logic. */ | |
1036 | if (length == 0) { | |
1037 | prefetch_activated = 1; | |
d9aaed83 | 1038 | length = pfault->rdma.packet_size; |
eab668a6 HE |
1039 | prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len); |
1040 | } | |
1041 | ||
d9aaed83 AK |
1042 | ret = pagefault_single_data_segment(dev, rkey, address, length, |
1043 | &pfault->bytes_committed, NULL); | |
eab668a6 HE |
1044 | if (ret == -EAGAIN) { |
1045 | /* We're racing with an invalidation, don't prefetch */ | |
1046 | prefetch_activated = 0; | |
1047 | } else if (ret < 0 || pages_in_range(address, length) > ret) { | |
d9aaed83 AK |
1048 | mlx5_ib_page_fault_resume(dev, pfault, 1); |
1049 | if (ret != -ENOENT) | |
4df4a5ba AK |
1050 | mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n", |
1051 | ret, pfault->token, pfault->type); | |
eab668a6 HE |
1052 | return; |
1053 | } | |
1054 | ||
d9aaed83 AK |
1055 | mlx5_ib_page_fault_resume(dev, pfault, 0); |
1056 | mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x, type: 0x%x, prefetch_activated: %d\n", | |
1057 | pfault->token, pfault->type, | |
1058 | prefetch_activated); | |
eab668a6 HE |
1059 | |
1060 | /* At this point, there might be a new pagefault already arriving in | |
1061 | * the eq, switch to the dummy pagefault for the rest of the | |
1062 | * processing. We're still OK with the objects being alive as the | |
1063 | * work-queue is being fenced. */ | |
1064 | ||
1065 | if (prefetch_activated) { | |
d9aaed83 AK |
1066 | u32 bytes_committed = 0; |
1067 | ||
1068 | ret = pagefault_single_data_segment(dev, rkey, address, | |
eab668a6 | 1069 | prefetch_len, |
d9aaed83 | 1070 | &bytes_committed, NULL); |
81713d37 | 1071 | if (ret < 0 && ret != -EAGAIN) { |
4df4a5ba AK |
1072 | mlx5_ib_dbg(dev, "Prefetch failed. ret: %d, QP 0x%x, address: 0x%.16llx, length = 0x%.16x\n", |
1073 | ret, pfault->token, address, prefetch_len); | |
eab668a6 HE |
1074 | } |
1075 | } | |
1076 | } | |
1077 | ||
d9aaed83 AK |
1078 | void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context, |
1079 | struct mlx5_pagefault *pfault) | |
6aec21f6 | 1080 | { |
d9aaed83 AK |
1081 | struct mlx5_ib_dev *dev = context; |
1082 | u8 event_subtype = pfault->event_subtype; | |
6aec21f6 HE |
1083 | |
1084 | switch (event_subtype) { | |
7bdf65d4 | 1085 | case MLX5_PFAULT_SUBTYPE_WQE: |
d9aaed83 | 1086 | mlx5_ib_mr_wqe_pfault_handler(dev, pfault); |
7bdf65d4 | 1087 | break; |
eab668a6 | 1088 | case MLX5_PFAULT_SUBTYPE_RDMA: |
d9aaed83 | 1089 | mlx5_ib_mr_rdma_pfault_handler(dev, pfault); |
eab668a6 | 1090 | break; |
6aec21f6 | 1091 | default: |
d9aaed83 AK |
1092 | mlx5_ib_err(dev, "Invalid page fault event subtype: 0x%x\n", |
1093 | event_subtype); | |
1094 | mlx5_ib_page_fault_resume(dev, pfault, 1); | |
6aec21f6 HE |
1095 | } |
1096 | } | |
1097 | ||
81713d37 AK |
1098 | void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) |
1099 | { | |
1100 | if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT)) | |
1101 | return; | |
1102 | ||
1103 | switch (ent->order - 2) { | |
1104 | case MLX5_IMR_MTT_CACHE_ENTRY: | |
1105 | ent->page = PAGE_SHIFT; | |
1106 | ent->xlt = MLX5_IMR_MTT_ENTRIES * | |
1107 | sizeof(struct mlx5_mtt) / | |
1108 | MLX5_IB_UMR_OCTOWORD; | |
1109 | ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; | |
1110 | ent->limit = 0; | |
1111 | break; | |
1112 | ||
1113 | case MLX5_IMR_KSM_CACHE_ENTRY: | |
1114 | ent->page = MLX5_KSM_PAGE_SHIFT; | |
1115 | ent->xlt = mlx5_imr_ksm_entries * | |
1116 | sizeof(struct mlx5_klm) / | |
1117 | MLX5_IB_UMR_OCTOWORD; | |
1118 | ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM; | |
1119 | ent->limit = 0; | |
1120 | break; | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | int mlx5_ib_odp_init_one(struct mlx5_ib_dev *dev) | |
6aec21f6 HE |
1125 | { |
1126 | int ret; | |
1127 | ||
81713d37 | 1128 | ret = init_srcu_struct(&dev->mr_srcu); |
6aec21f6 HE |
1129 | if (ret) |
1130 | return ret; | |
1131 | ||
81713d37 AK |
1132 | if (dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT) { |
1133 | ret = mlx5_cmd_null_mkey(dev->mdev, &dev->null_mkey); | |
1134 | if (ret) { | |
1135 | mlx5_ib_err(dev, "Error getting null_mkey %d\n", ret); | |
1136 | return ret; | |
1137 | } | |
1138 | } | |
1139 | ||
6aec21f6 HE |
1140 | return 0; |
1141 | } | |
1142 | ||
81713d37 AK |
1143 | void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *dev) |
1144 | { | |
1145 | cleanup_srcu_struct(&dev->mr_srcu); | |
1146 | } | |
1147 | ||
1148 | int mlx5_ib_odp_init(void) | |
6aec21f6 | 1149 | { |
81713d37 AK |
1150 | mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) - |
1151 | MLX5_IMR_MTT_BITS); | |
1152 | ||
1153 | return 0; | |
6aec21f6 HE |
1154 | } |
1155 |