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mlx5_core: Fix PowerPC support
[mirror_ubuntu-zesty-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
35#include "mlx5_ib.h"
36#include "user.h"
37
38/* not supported currently */
39static int wq_signature;
40
41enum {
42 MLX5_IB_ACK_REQ_FREQ = 8,
43};
44
45enum {
46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
48 MLX5_IB_LINK_TYPE_IB = 0,
49 MLX5_IB_LINK_TYPE_ETH = 1
50};
51
52enum {
53 MLX5_IB_SQ_STRIDE = 6,
54 MLX5_IB_CACHE_LINE_SIZE = 64,
55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR,
68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
71};
72
73struct umr_wr {
74 u64 virt_addr;
75 struct ib_pd *pd;
76 unsigned int page_shift;
77 unsigned int npages;
78 u32 length;
79 int access_flags;
80 u32 mkey;
81};
82
83static int is_qp0(enum ib_qp_type qp_type)
84{
85 return qp_type == IB_QPT_SMI;
86}
87
88static int is_qp1(enum ib_qp_type qp_type)
89{
90 return qp_type == IB_QPT_GSI;
91}
92
93static int is_sqp(enum ib_qp_type qp_type)
94{
95 return is_qp0(qp_type) || is_qp1(qp_type);
96}
97
98static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99{
100 return mlx5_buf_offset(&qp->buf, offset);
101}
102
103static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104{
105 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106}
107
108void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109{
110 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111}
112
113static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
114{
115 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
116 struct ib_event event;
117
118 if (type == MLX5_EVENT_TYPE_PATH_MIG)
119 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
120
121 if (ibqp->event_handler) {
122 event.device = ibqp->device;
123 event.element.qp = ibqp;
124 switch (type) {
125 case MLX5_EVENT_TYPE_PATH_MIG:
126 event.event = IB_EVENT_PATH_MIG;
127 break;
128 case MLX5_EVENT_TYPE_COMM_EST:
129 event.event = IB_EVENT_COMM_EST;
130 break;
131 case MLX5_EVENT_TYPE_SQ_DRAINED:
132 event.event = IB_EVENT_SQ_DRAINED;
133 break;
134 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
135 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
136 break;
137 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
138 event.event = IB_EVENT_QP_FATAL;
139 break;
140 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
141 event.event = IB_EVENT_PATH_MIG_ERR;
142 break;
143 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
144 event.event = IB_EVENT_QP_REQ_ERR;
145 break;
146 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
147 event.event = IB_EVENT_QP_ACCESS_ERR;
148 break;
149 default:
150 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
151 return;
152 }
153
154 ibqp->event_handler(&event, ibqp->qp_context);
155 }
156}
157
158static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
159 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
160{
161 int wqe_size;
162 int wq_size;
163
164 /* Sanity check RQ size before proceeding */
165 if (cap->max_recv_wr > dev->mdev.caps.max_wqes)
166 return -EINVAL;
167
168 if (!has_rq) {
169 qp->rq.max_gs = 0;
170 qp->rq.wqe_cnt = 0;
171 qp->rq.wqe_shift = 0;
172 } else {
173 if (ucmd) {
174 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
175 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
176 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
177 qp->rq.max_post = qp->rq.wqe_cnt;
178 } else {
179 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
180 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
181 wqe_size = roundup_pow_of_two(wqe_size);
182 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
183 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
184 qp->rq.wqe_cnt = wq_size / wqe_size;
185 if (wqe_size > dev->mdev.caps.max_rq_desc_sz) {
186 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
187 wqe_size,
188 dev->mdev.caps.max_rq_desc_sz);
189 return -EINVAL;
190 }
191 qp->rq.wqe_shift = ilog2(wqe_size);
192 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
193 qp->rq.max_post = qp->rq.wqe_cnt;
194 }
195 }
196
197 return 0;
198}
199
200static int sq_overhead(enum ib_qp_type qp_type)
201{
618af384 202 int size = 0;
e126ba97
EC		 203
204 switch (qp_type) {
205 case IB_QPT_XRC_INI:
b125a54b 206 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 207 /* fall through */
208 case IB_QPT_RC:
209 size += sizeof(struct mlx5_wqe_ctrl_seg) +
210 sizeof(struct mlx5_wqe_atomic_seg) +
211 sizeof(struct mlx5_wqe_raddr_seg);
212 break;
213
b125a54b
EC		 214 case IB_QPT_XRC_TGT:
215 return 0;
216
e126ba97 217 case IB_QPT_UC:
b125a54b 218 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 219 sizeof(struct mlx5_wqe_raddr_seg);
220 break;
221
222 case IB_QPT_UD:
223 case IB_QPT_SMI:
224 case IB_QPT_GSI:
b125a54b 225 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 226 sizeof(struct mlx5_wqe_datagram_seg);
227 break;
228
229 case MLX5_IB_QPT_REG_UMR:
b125a54b 230 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 231 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
232 sizeof(struct mlx5_mkey_seg);
233 break;
234
235 default:
236 return -EINVAL;
237 }
238
239 return size;
240}
241
242static int calc_send_wqe(struct ib_qp_init_attr *attr)
243{
244 int inl_size = 0;
245 int size;
246
247 size = sq_overhead(attr->qp_type);
248 if (size < 0)
249 return size;
250
251 if (attr->cap.max_inline_data) {
252 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
253 attr->cap.max_inline_data;
254 }
255
256 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
257
258 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
259}
260
261static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
262 struct mlx5_ib_qp *qp)
263{
264 int wqe_size;
265 int wq_size;
266
267 if (!attr->cap.max_send_wr)
268 return 0;
269
270 wqe_size = calc_send_wqe(attr);
271 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
272 if (wqe_size < 0)
273 return wqe_size;
274
275 if (wqe_size > dev->mdev.caps.max_sq_desc_sz) {
b125a54b
EC		 276 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
277 wqe_size, dev->mdev.caps.max_sq_desc_sz);
e126ba97
EC		 278 return -EINVAL;
279 }
280
281 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
282 sizeof(struct mlx5_wqe_inline_seg);
283 attr->cap.max_inline_data = qp->max_inline_data;
284
285 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
286 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
b125a54b
EC		 287 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
288 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
289 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
290 return -ENOMEM;
291 }
e126ba97
EC		 292 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
293 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 294 qp->sq.max_post = wq_size / wqe_size;
295 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 296
297 return wq_size;
298}
299
300static int set_user_buf_size(struct mlx5_ib_dev *dev,
301 struct mlx5_ib_qp *qp,
302 struct mlx5_ib_create_qp *ucmd)
303{
304 int desc_sz = 1 << qp->sq.wqe_shift;
305
306 if (desc_sz > dev->mdev.caps.max_sq_desc_sz) {
307 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
308 desc_sz, dev->mdev.caps.max_sq_desc_sz);
309 return -EINVAL;
310 }
311
312 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
313 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
314 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
315 return -EINVAL;
316 }
317
318 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
319
320 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
321 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
322 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
323 return -EINVAL;
324 }
325
326 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
327 (qp->sq.wqe_cnt << 6);
328
329 return 0;
330}
331
332static int qp_has_rq(struct ib_qp_init_attr *attr)
333{
334 if (attr->qp_type == IB_QPT_XRC_INI ||
335 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
336 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
337 !attr->cap.max_recv_wr)
338 return 0;
339
340 return 1;
341}
342
c1be5232
EC		 343static int first_med_uuar(void)
344{
345 return 1;
346}
347
348static int next_uuar(int n)
349{
350 n++;
351
352 while (((n % 4) & 2))
353 n++;
354
355 return n;
356}
357
358static int num_med_uuar(struct mlx5_uuar_info *uuari)
359{
360 int n;
361
362 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
363 uuari->num_low_latency_uuars - 1;
364
365 return n >= 0 ? n : 0;
366}
367
368static int max_uuari(struct mlx5_uuar_info *uuari)
369{
370 return uuari->num_uars * 4;
371}
372
373static int first_hi_uuar(struct mlx5_uuar_info *uuari)
374{
375 int med;
376 int i;
377 int t;
378
379 med = num_med_uuar(uuari);
380 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
381 t++;
382 if (t == med)
383 return next_uuar(i);
384 }
385
386 return 0;
387}
388
e126ba97
EC		 389static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
390{
e126ba97
EC		 391 int i;
392
c1be5232 393 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 394 if (!test_bit(i, uuari->bitmap)) {
395 set_bit(i, uuari->bitmap);
396 uuari->count[i]++;
397 return i;
398 }
399 }
400
401 return -ENOMEM;
402}
403
404static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
405{
c1be5232 406 int minidx = first_med_uuar();
e126ba97
EC		 407 int i;
408
c1be5232 409 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 410 if (uuari->count[i] < uuari->count[minidx])
411 minidx = i;
412 }
413
414 uuari->count[minidx]++;
415 return minidx;
416}
417
418static int alloc_uuar(struct mlx5_uuar_info *uuari,
419 enum mlx5_ib_latency_class lat)
420{
421 int uuarn = -EINVAL;
422
423 mutex_lock(&uuari->lock);
424 switch (lat) {
425 case MLX5_IB_LATENCY_CLASS_LOW:
426 uuarn = 0;
427 uuari->count[uuarn]++;
428 break;
429
430 case MLX5_IB_LATENCY_CLASS_MEDIUM:
431 uuarn = alloc_med_class_uuar(uuari);
432 break;
433
434 case MLX5_IB_LATENCY_CLASS_HIGH:
435 uuarn = alloc_high_class_uuar(uuari);
436 break;
437
438 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
439 uuarn = 2;
440 break;
441 }
442 mutex_unlock(&uuari->lock);
443
444 return uuarn;
445}
446
447static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
448{
449 clear_bit(uuarn, uuari->bitmap);
450 --uuari->count[uuarn];
451}
452
453static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
454{
455 clear_bit(uuarn, uuari->bitmap);
456 --uuari->count[uuarn];
457}
458
459static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
460{
461 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
462 int high_uuar = nuuars - uuari->num_low_latency_uuars;
463
464 mutex_lock(&uuari->lock);
465 if (uuarn == 0) {
466 --uuari->count[uuarn];
467 goto out;
468 }
469
470 if (uuarn < high_uuar) {
471 free_med_class_uuar(uuari, uuarn);
472 goto out;
473 }
474
475 free_high_class_uuar(uuari, uuarn);
476
477out:
478 mutex_unlock(&uuari->lock);
479}
480
481static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
482{
483 switch (state) {
484 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
485 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
486 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
487 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
488 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
489 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
490 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
491 default: return -1;
492 }
493}
494
495static int to_mlx5_st(enum ib_qp_type type)
496{
497 switch (type) {
498 case IB_QPT_RC: return MLX5_QP_ST_RC;
499 case IB_QPT_UC: return MLX5_QP_ST_UC;
500 case IB_QPT_UD: return MLX5_QP_ST_UD;
501 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
502 case IB_QPT_XRC_INI:
503 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
504 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
505 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
506 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
507 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
508 case IB_QPT_RAW_PACKET:
509 case IB_QPT_MAX:
510 default: return -EINVAL;
511 }
512}
513
514static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
515{
516 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
517}
518
519static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
520 struct mlx5_ib_qp *qp, struct ib_udata *udata,
521 struct mlx5_create_qp_mbox_in **in,
522 struct mlx5_ib_create_qp_resp *resp, int *inlen)
523{
524 struct mlx5_ib_ucontext *context;
525 struct mlx5_ib_create_qp ucmd;
526 int page_shift;
527 int uar_index;
528 int npages;
529 u32 offset;
530 int uuarn;
531 int ncont;
532 int err;
533
534 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
535 if (err) {
536 mlx5_ib_dbg(dev, "copy failed\n");
537 return err;
538 }
539
540 context = to_mucontext(pd->uobject->context);
541 /*
542 * TBD: should come from the verbs when we have the API
543 */
544 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
545 if (uuarn < 0) {
546 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
c1be5232
EC		 547 mlx5_ib_dbg(dev, "reverting to medium latency\n");
548 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
e126ba97 549 if (uuarn < 0) {
c1be5232
EC		 550 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
551 mlx5_ib_dbg(dev, "reverting to high latency\n");
552 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
553 if (uuarn < 0) {
554 mlx5_ib_warn(dev, "uuar allocation failed\n");
555 return uuarn;
556 }
e126ba97
EC		 557 }
558 }
559
560 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
561 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
562
563 err = set_user_buf_size(dev, qp, &ucmd);
564 if (err)
565 goto err_uuar;
566
567 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
568 qp->buf_size, 0, 0);
569 if (IS_ERR(qp->umem)) {
570 mlx5_ib_dbg(dev, "umem_get failed\n");
571 err = PTR_ERR(qp->umem);
572 goto err_uuar;
573 }
574
575 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
576 &ncont, NULL);
577 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
578 if (err) {
579 mlx5_ib_warn(dev, "bad offset\n");
580 goto err_umem;
581 }
582 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
583 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
584
585 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
586 *in = mlx5_vzalloc(*inlen);
587 if (!*in) {
588 err = -ENOMEM;
589 goto err_umem;
590 }
591 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
592 (*in)->ctx.log_pg_sz_remote_qpn =
1b77d2bd 593 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 594 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
595
596 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
597 resp->uuar_index = uuarn;
598 qp->uuarn = uuarn;
599
600 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
601 if (err) {
602 mlx5_ib_dbg(dev, "map failed\n");
603 goto err_free;
604 }
605
606 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
607 if (err) {
608 mlx5_ib_dbg(dev, "copy failed\n");
609 goto err_unmap;
610 }
611 qp->create_type = MLX5_QP_USER;
612
613 return 0;
614
615err_unmap:
616 mlx5_ib_db_unmap_user(context, &qp->db);
617
618err_free:
619 mlx5_vfree(*in);
620
621err_umem:
622 ib_umem_release(qp->umem);
623
624err_uuar:
625 free_uuar(&context->uuari, uuarn);
626 return err;
627}
628
629static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
630{
631 struct mlx5_ib_ucontext *context;
632
633 context = to_mucontext(pd->uobject->context);
634 mlx5_ib_db_unmap_user(context, &qp->db);
635 ib_umem_release(qp->umem);
636 free_uuar(&context->uuari, qp->uuarn);
637}
638
639static int create_kernel_qp(struct mlx5_ib_dev *dev,
640 struct ib_qp_init_attr *init_attr,
641 struct mlx5_ib_qp *qp,
642 struct mlx5_create_qp_mbox_in **in, int *inlen)
643{
644 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
645 struct mlx5_uuar_info *uuari;
646 int uar_index;
647 int uuarn;
648 int err;
649
650 uuari = &dev->mdev.priv.uuari;
651 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
652 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
653
654 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
655 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
656
657 uuarn = alloc_uuar(uuari, lc);
658 if (uuarn < 0) {
659 mlx5_ib_dbg(dev, "\n");
660 return -ENOMEM;
661 }
662
663 qp->bf = &uuari->bfs[uuarn];
664 uar_index = qp->bf->uar->index;
665
666 err = calc_sq_size(dev, init_attr, qp);
667 if (err < 0) {
668 mlx5_ib_dbg(dev, "err %d\n", err);
669 goto err_uuar;
670 }
671
672 qp->rq.offset = 0;
673 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
674 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
675
676 err = mlx5_buf_alloc(&dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf);
677 if (err) {
678 mlx5_ib_dbg(dev, "err %d\n", err);
679 goto err_uuar;
680 }
681
682 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
683 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
684 *in = mlx5_vzalloc(*inlen);
685 if (!*in) {
686 err = -ENOMEM;
687 goto err_buf;
688 }
689 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
1b77d2bd
EC		 690 (*in)->ctx.log_pg_sz_remote_qpn =
691 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 692 /* Set "fast registration enabled" for all kernel QPs */
693 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
694 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
695
696 mlx5_fill_page_array(&qp->buf, (*in)->pas);
697
698 err = mlx5_db_alloc(&dev->mdev, &qp->db);
699 if (err) {
700 mlx5_ib_dbg(dev, "err %d\n", err);
701 goto err_free;
702 }
703
704 qp->db.db[0] = 0;
705 qp->db.db[1] = 0;
706
707 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
708 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
709 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
710 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
711 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
712
713 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
714 !qp->sq.w_list || !qp->sq.wqe_head) {
715 err = -ENOMEM;
716 goto err_wrid;
717 }
718 qp->create_type = MLX5_QP_KERNEL;
719
720 return 0;
721
722err_wrid:
723 mlx5_db_free(&dev->mdev, &qp->db);
724 kfree(qp->sq.wqe_head);
725 kfree(qp->sq.w_list);
726 kfree(qp->sq.wrid);
727 kfree(qp->sq.wr_data);
728 kfree(qp->rq.wrid);
729
730err_free:
731 mlx5_vfree(*in);
732
733err_buf:
734 mlx5_buf_free(&dev->mdev, &qp->buf);
735
736err_uuar:
737 free_uuar(&dev->mdev.priv.uuari, uuarn);
738 return err;
739}
740
741static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
742{
743 mlx5_db_free(&dev->mdev, &qp->db);
744 kfree(qp->sq.wqe_head);
745 kfree(qp->sq.w_list);
746 kfree(qp->sq.wrid);
747 kfree(qp->sq.wr_data);
748 kfree(qp->rq.wrid);
749 mlx5_buf_free(&dev->mdev, &qp->buf);
750 free_uuar(&dev->mdev.priv.uuari, qp->bf->uuarn);
751}
752
753static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
754{
755 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
756 (attr->qp_type == IB_QPT_XRC_INI))
757 return cpu_to_be32(MLX5_SRQ_RQ);
758 else if (!qp->has_rq)
759 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
760 else
761 return cpu_to_be32(MLX5_NON_ZERO_RQ);
762}
763
764static int is_connected(enum ib_qp_type qp_type)
765{
766 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
767 return 1;
768
769 return 0;
770}
771
772static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
773 struct ib_qp_init_attr *init_attr,
774 struct ib_udata *udata, struct mlx5_ib_qp *qp)
775{
776 struct mlx5_ib_resources *devr = &dev->devr;
777 struct mlx5_ib_create_qp_resp resp;
778 struct mlx5_create_qp_mbox_in *in;
779 struct mlx5_ib_create_qp ucmd;
780 int inlen = sizeof(*in);
781 int err;
782
783 mutex_init(&qp->mutex);
784 spin_lock_init(&qp->sq.lock);
785 spin_lock_init(&qp->rq.lock);
786
787 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
788 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
789
790 if (pd && pd->uobject) {
791 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
792 mlx5_ib_dbg(dev, "copy failed\n");
793 return -EFAULT;
794 }
795
796 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
797 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
798 } else {
799 qp->wq_sig = !!wq_signature;
800 }
801
802 qp->has_rq = qp_has_rq(init_attr);
803 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
804 qp, (pd && pd->uobject) ? &ucmd : NULL);
805 if (err) {
806 mlx5_ib_dbg(dev, "err %d\n", err);
807 return err;
808 }
809
810 if (pd) {
811 if (pd->uobject) {
812 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
813 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
814 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
815 mlx5_ib_dbg(dev, "invalid rq params\n");
816 return -EINVAL;
817 }
818 if (ucmd.sq_wqe_count > dev->mdev.caps.max_wqes) {
819 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
820 ucmd.sq_wqe_count, dev->mdev.caps.max_wqes);
821 return -EINVAL;
822 }
823 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
824 if (err)
825 mlx5_ib_dbg(dev, "err %d\n", err);
826 } else {
827 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
828 if (err)
829 mlx5_ib_dbg(dev, "err %d\n", err);
830 else
831 qp->pa_lkey = to_mpd(pd)->pa_lkey;
832 }
833
834 if (err)
835 return err;
836 } else {
837 in = mlx5_vzalloc(sizeof(*in));
838 if (!in)
839 return -ENOMEM;
840
841 qp->create_type = MLX5_QP_EMPTY;
842 }
843
844 if (is_sqp(init_attr->qp_type))
845 qp->port = init_attr->port_num;
846
847 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
848 MLX5_QP_PM_MIGRATED << 11);
849
850 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
851 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
852 else
853 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
854
855 if (qp->wq_sig)
856 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
857
858 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
859 int rcqe_sz;
860 int scqe_sz;
861
862 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
863 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
864
865 if (rcqe_sz == 128)
866 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
867 else
868 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
869
870 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
871 if (scqe_sz == 128)
872 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
873 else
874 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
875 }
876 }
877
878 if (qp->rq.wqe_cnt) {
879 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
880 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
881 }
882
883 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
884
885 if (qp->sq.wqe_cnt)
886 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
887 else
888 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
889
890 /* Set default resources */
891 switch (init_attr->qp_type) {
892 case IB_QPT_XRC_TGT:
893 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
894 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
895 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
896 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
897 break;
898 case IB_QPT_XRC_INI:
899 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
900 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
901 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
902 break;
903 default:
904 if (init_attr->srq) {
905 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
906 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
907 } else {
908 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
909 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
910 }
911 }
912
913 if (init_attr->send_cq)
914 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
915
916 if (init_attr->recv_cq)
917 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
918
919 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
920
921 err = mlx5_core_create_qp(&dev->mdev, &qp->mqp, in, inlen);
922 if (err) {
923 mlx5_ib_dbg(dev, "create qp failed\n");
924 goto err_create;
925 }
926
927 mlx5_vfree(in);
928 /* Hardware wants QPN written in big-endian order (after
929 * shifting) for send doorbell. Precompute this value to save
930 * a little bit when posting sends.
931 */
932 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
933
934 qp->mqp.event = mlx5_ib_qp_event;
935
936 return 0;
937
938err_create:
939 if (qp->create_type == MLX5_QP_USER)
940 destroy_qp_user(pd, qp);
941 else if (qp->create_type == MLX5_QP_KERNEL)
942 destroy_qp_kernel(dev, qp);
943
944 mlx5_vfree(in);
945 return err;
946}
947
948static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
949 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
950{
951 if (send_cq) {
952 if (recv_cq) {
953 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
954 spin_lock_irq(&send_cq->lock);
955 spin_lock_nested(&recv_cq->lock,
956 SINGLE_DEPTH_NESTING);
957 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
958 spin_lock_irq(&send_cq->lock);
959 __acquire(&recv_cq->lock);
960 } else {
961 spin_lock_irq(&recv_cq->lock);
962 spin_lock_nested(&send_cq->lock,
963 SINGLE_DEPTH_NESTING);
964 }
965 } else {
966 spin_lock_irq(&send_cq->lock);
967 }
968 } else if (recv_cq) {
969 spin_lock_irq(&recv_cq->lock);
970 }
971}
972
973static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
974 __releases(&send_cq->lock) __releases(&recv_cq->lock)
975{
976 if (send_cq) {
977 if (recv_cq) {
978 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
979 spin_unlock(&recv_cq->lock);
980 spin_unlock_irq(&send_cq->lock);
981 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
982 __release(&recv_cq->lock);
983 spin_unlock_irq(&send_cq->lock);
984 } else {
985 spin_unlock(&send_cq->lock);
986 spin_unlock_irq(&recv_cq->lock);
987 }
988 } else {
989 spin_unlock_irq(&send_cq->lock);
990 }
991 } else if (recv_cq) {
992 spin_unlock_irq(&recv_cq->lock);
993 }
994}
995
996static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
997{
998 return to_mpd(qp->ibqp.pd);
999}
1000
1001static void get_cqs(struct mlx5_ib_qp *qp,
1002 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1003{
1004 switch (qp->ibqp.qp_type) {
1005 case IB_QPT_XRC_TGT:
1006 *send_cq = NULL;
1007 *recv_cq = NULL;
1008 break;
1009 case MLX5_IB_QPT_REG_UMR:
1010 case IB_QPT_XRC_INI:
1011 *send_cq = to_mcq(qp->ibqp.send_cq);
1012 *recv_cq = NULL;
1013 break;
1014
1015 case IB_QPT_SMI:
1016 case IB_QPT_GSI:
1017 case IB_QPT_RC:
1018 case IB_QPT_UC:
1019 case IB_QPT_UD:
1020 case IB_QPT_RAW_IPV6:
1021 case IB_QPT_RAW_ETHERTYPE:
1022 *send_cq = to_mcq(qp->ibqp.send_cq);
1023 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1024 break;
1025
1026 case IB_QPT_RAW_PACKET:
1027 case IB_QPT_MAX:
1028 default:
1029 *send_cq = NULL;
1030 *recv_cq = NULL;
1031 break;
1032 }
1033}
1034
1035static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1036{
1037 struct mlx5_ib_cq *send_cq, *recv_cq;
1038 struct mlx5_modify_qp_mbox_in *in;
1039 int err;
1040
1041 in = kzalloc(sizeof(*in), GFP_KERNEL);
1042 if (!in)
1043 return;
1044 if (qp->state != IB_QPS_RESET)
1045 if (mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(qp->state),
1046 MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp))
1047 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1048 qp->mqp.qpn);
1049
1050 get_cqs(qp, &send_cq, &recv_cq);
1051
1052 if (qp->create_type == MLX5_QP_KERNEL) {
1053 mlx5_ib_lock_cqs(send_cq, recv_cq);
1054 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1055 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1056 if (send_cq != recv_cq)
1057 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1058 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1059 }
1060
1061 err = mlx5_core_destroy_qp(&dev->mdev, &qp->mqp);
1062 if (err)
1063 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1064 kfree(in);
1065
1066
1067 if (qp->create_type == MLX5_QP_KERNEL)
1068 destroy_qp_kernel(dev, qp);
1069 else if (qp->create_type == MLX5_QP_USER)
1070 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1071}
1072
1073static const char *ib_qp_type_str(enum ib_qp_type type)
1074{
1075 switch (type) {
1076 case IB_QPT_SMI:
1077 return "IB_QPT_SMI";
1078 case IB_QPT_GSI:
1079 return "IB_QPT_GSI";
1080 case IB_QPT_RC:
1081 return "IB_QPT_RC";
1082 case IB_QPT_UC:
1083 return "IB_QPT_UC";
1084 case IB_QPT_UD:
1085 return "IB_QPT_UD";
1086 case IB_QPT_RAW_IPV6:
1087 return "IB_QPT_RAW_IPV6";
1088 case IB_QPT_RAW_ETHERTYPE:
1089 return "IB_QPT_RAW_ETHERTYPE";
1090 case IB_QPT_XRC_INI:
1091 return "IB_QPT_XRC_INI";
1092 case IB_QPT_XRC_TGT:
1093 return "IB_QPT_XRC_TGT";
1094 case IB_QPT_RAW_PACKET:
1095 return "IB_QPT_RAW_PACKET";
1096 case MLX5_IB_QPT_REG_UMR:
1097 return "MLX5_IB_QPT_REG_UMR";
1098 case IB_QPT_MAX:
1099 default:
1100 return "Invalid QP type";
1101 }
1102}
1103
1104struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1105 struct ib_qp_init_attr *init_attr,
1106 struct ib_udata *udata)
1107{
1108 struct mlx5_ib_dev *dev;
1109 struct mlx5_ib_qp *qp;
1110 u16 xrcdn = 0;
1111 int err;
1112
1113 if (pd) {
1114 dev = to_mdev(pd->device);
1115 } else {
1116 /* being cautious here */
1117 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1118 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1119 pr_warn("%s: no PD for transport %s\n", __func__,
1120 ib_qp_type_str(init_attr->qp_type));
1121 return ERR_PTR(-EINVAL);
1122 }
1123 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1124 }
1125
1126 switch (init_attr->qp_type) {
1127 case IB_QPT_XRC_TGT:
1128 case IB_QPT_XRC_INI:
1129 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC)) {
1130 mlx5_ib_dbg(dev, "XRC not supported\n");
1131 return ERR_PTR(-ENOSYS);
1132 }
1133 init_attr->recv_cq = NULL;
1134 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1135 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1136 init_attr->send_cq = NULL;
1137 }
1138
1139 /* fall through */
1140 case IB_QPT_RC:
1141 case IB_QPT_UC:
1142 case IB_QPT_UD:
1143 case IB_QPT_SMI:
1144 case IB_QPT_GSI:
1145 case MLX5_IB_QPT_REG_UMR:
1146 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1147 if (!qp)
1148 return ERR_PTR(-ENOMEM);
1149
1150 err = create_qp_common(dev, pd, init_attr, udata, qp);
1151 if (err) {
1152 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1153 kfree(qp);
1154 return ERR_PTR(err);
1155 }
1156
1157 if (is_qp0(init_attr->qp_type))
1158 qp->ibqp.qp_num = 0;
1159 else if (is_qp1(init_attr->qp_type))
1160 qp->ibqp.qp_num = 1;
1161 else
1162 qp->ibqp.qp_num = qp->mqp.qpn;
1163
1164 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1165 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1166 to_mcq(init_attr->send_cq)->mcq.cqn);
1167
1168 qp->xrcdn = xrcdn;
1169
1170 break;
1171
1172 case IB_QPT_RAW_IPV6:
1173 case IB_QPT_RAW_ETHERTYPE:
1174 case IB_QPT_RAW_PACKET:
1175 case IB_QPT_MAX:
1176 default:
1177 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1178 init_attr->qp_type);
1179 /* Don't support raw QPs */
1180 return ERR_PTR(-EINVAL);
1181 }
1182
1183 return &qp->ibqp;
1184}
1185
1186int mlx5_ib_destroy_qp(struct ib_qp *qp)
1187{
1188 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1189 struct mlx5_ib_qp *mqp = to_mqp(qp);
1190
1191 destroy_qp_common(dev, mqp);
1192
1193 kfree(mqp);
1194
1195 return 0;
1196}
1197
1198static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1199 int attr_mask)
1200{
1201 u32 hw_access_flags = 0;
1202 u8 dest_rd_atomic;
1203 u32 access_flags;
1204
1205 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1206 dest_rd_atomic = attr->max_dest_rd_atomic;
1207 else
1208 dest_rd_atomic = qp->resp_depth;
1209
1210 if (attr_mask & IB_QP_ACCESS_FLAGS)
1211 access_flags = attr->qp_access_flags;
1212 else
1213 access_flags = qp->atomic_rd_en;
1214
1215 if (!dest_rd_atomic)
1216 access_flags &= IB_ACCESS_REMOTE_WRITE;
1217
1218 if (access_flags & IB_ACCESS_REMOTE_READ)
1219 hw_access_flags |= MLX5_QP_BIT_RRE;
1220 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1221 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1222 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1223 hw_access_flags |= MLX5_QP_BIT_RWE;
1224
1225 return cpu_to_be32(hw_access_flags);
1226}
1227
1228enum {
1229 MLX5_PATH_FLAG_FL = 1 << 0,
1230 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1231 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1232};
1233
1234static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1235{
1236 if (rate == IB_RATE_PORT_CURRENT) {
1237 return 0;
1238 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1239 return -EINVAL;
1240 } else {
1241 while (rate != IB_RATE_2_5_GBPS &&
1242 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1243 dev->mdev.caps.stat_rate_support))
1244 --rate;
1245 }
1246
1247 return rate + MLX5_STAT_RATE_OFFSET;
1248}
1249
1250static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1251 struct mlx5_qp_path *path, u8 port, int attr_mask,
1252 u32 path_flags, const struct ib_qp_attr *attr)
1253{
1254 int err;
1255
1256 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1257 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1258
1259 if (attr_mask & IB_QP_PKEY_INDEX)
1260 path->pkey_index = attr->pkey_index;
1261
1262 path->grh_mlid = ah->src_path_bits & 0x7f;
1263 path->rlid = cpu_to_be16(ah->dlid);
1264
1265 if (ah->ah_flags & IB_AH_GRH) {
1266 path->grh_mlid |= 1 << 7;
1267 path->mgid_index = ah->grh.sgid_index;
1268 path->hop_limit = ah->grh.hop_limit;
1269 path->tclass_flowlabel =
1270 cpu_to_be32((ah->grh.traffic_class << 20) |
1271 (ah->grh.flow_label));
1272 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1273 }
1274
1275 err = ib_rate_to_mlx5(dev, ah->static_rate);
1276 if (err < 0)
1277 return err;
1278 path->static_rate = err;
1279 path->port = port;
1280
1281 if (ah->ah_flags & IB_AH_GRH) {
1282 if (ah->grh.sgid_index >= dev->mdev.caps.port[port - 1].gid_table_len) {
1283 pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n",
1284 ah->grh.sgid_index, dev->mdev.caps.port[port - 1].gid_table_len);
1285 return -EINVAL;
1286 }
1287
1288 path->grh_mlid |= 1 << 7;
1289 path->mgid_index = ah->grh.sgid_index;
1290 path->hop_limit = ah->grh.hop_limit;
1291 path->tclass_flowlabel =
1292 cpu_to_be32((ah->grh.traffic_class << 20) |
1293 (ah->grh.flow_label));
1294 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1295 }
1296
1297 if (attr_mask & IB_QP_TIMEOUT)
1298 path->ackto_lt = attr->timeout << 3;
1299
1300 path->sl = ah->sl & 0xf;
1301
1302 return 0;
1303}
1304
1305static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1306 [MLX5_QP_STATE_INIT] = {
1307 [MLX5_QP_STATE_INIT] = {
1308 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1309 MLX5_QP_OPTPAR_RAE |
1310 MLX5_QP_OPTPAR_RWE |
1311 MLX5_QP_OPTPAR_PKEY_INDEX |
1312 MLX5_QP_OPTPAR_PRI_PORT,
1313 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1314 MLX5_QP_OPTPAR_PKEY_INDEX |
1315 MLX5_QP_OPTPAR_PRI_PORT,
1316 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1317 MLX5_QP_OPTPAR_Q_KEY |
1318 MLX5_QP_OPTPAR_PRI_PORT,
1319 },
1320 [MLX5_QP_STATE_RTR] = {
1321 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1322 MLX5_QP_OPTPAR_RRE |
1323 MLX5_QP_OPTPAR_RAE |
1324 MLX5_QP_OPTPAR_RWE |
1325 MLX5_QP_OPTPAR_PKEY_INDEX,
1326 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1327 MLX5_QP_OPTPAR_RWE |
1328 MLX5_QP_OPTPAR_PKEY_INDEX,
1329 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1330 MLX5_QP_OPTPAR_Q_KEY,
1331 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1332 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 1333 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1334 MLX5_QP_OPTPAR_RRE |
1335 MLX5_QP_OPTPAR_RAE |
1336 MLX5_QP_OPTPAR_RWE |
1337 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 1338 },
1339 },
1340 [MLX5_QP_STATE_RTR] = {
1341 [MLX5_QP_STATE_RTS] = {
1342 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1343 MLX5_QP_OPTPAR_RRE |
1344 MLX5_QP_OPTPAR_RAE |
1345 MLX5_QP_OPTPAR_RWE |
1346 MLX5_QP_OPTPAR_PM_STATE |
1347 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1348 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1349 MLX5_QP_OPTPAR_RWE |
1350 MLX5_QP_OPTPAR_PM_STATE,
1351 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1352 },
1353 },
1354 [MLX5_QP_STATE_RTS] = {
1355 [MLX5_QP_STATE_RTS] = {
1356 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1357 MLX5_QP_OPTPAR_RAE |
1358 MLX5_QP_OPTPAR_RWE |
1359 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 1360 MLX5_QP_OPTPAR_PM_STATE |
1361 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 1362 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 1363 MLX5_QP_OPTPAR_PM_STATE |
1364 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 1365 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1366 MLX5_QP_OPTPAR_SRQN |
1367 MLX5_QP_OPTPAR_CQN_RCV,
1368 },
1369 },
1370 [MLX5_QP_STATE_SQER] = {
1371 [MLX5_QP_STATE_RTS] = {
1372 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1373 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 1374 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 1375 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1376 MLX5_QP_OPTPAR_RWE |
1377 MLX5_QP_OPTPAR_RAE |
1378 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 1379 },
1380 },
1381};
1382
1383static int ib_nr_to_mlx5_nr(int ib_mask)
1384{
1385 switch (ib_mask) {
1386 case IB_QP_STATE:
1387 return 0;
1388 case IB_QP_CUR_STATE:
1389 return 0;
1390 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1391 return 0;
1392 case IB_QP_ACCESS_FLAGS:
1393 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1394 MLX5_QP_OPTPAR_RAE;
1395 case IB_QP_PKEY_INDEX:
1396 return MLX5_QP_OPTPAR_PKEY_INDEX;
1397 case IB_QP_PORT:
1398 return MLX5_QP_OPTPAR_PRI_PORT;
1399 case IB_QP_QKEY:
1400 return MLX5_QP_OPTPAR_Q_KEY;
1401 case IB_QP_AV:
1402 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1403 MLX5_QP_OPTPAR_PRI_PORT;
1404 case IB_QP_PATH_MTU:
1405 return 0;
1406 case IB_QP_TIMEOUT:
1407 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1408 case IB_QP_RETRY_CNT:
1409 return MLX5_QP_OPTPAR_RETRY_COUNT;
1410 case IB_QP_RNR_RETRY:
1411 return MLX5_QP_OPTPAR_RNR_RETRY;
1412 case IB_QP_RQ_PSN:
1413 return 0;
1414 case IB_QP_MAX_QP_RD_ATOMIC:
1415 return MLX5_QP_OPTPAR_SRA_MAX;
1416 case IB_QP_ALT_PATH:
1417 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1418 case IB_QP_MIN_RNR_TIMER:
1419 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1420 case IB_QP_SQ_PSN:
1421 return 0;
1422 case IB_QP_MAX_DEST_RD_ATOMIC:
1423 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1424 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1425 case IB_QP_PATH_MIG_STATE:
1426 return MLX5_QP_OPTPAR_PM_STATE;
1427 case IB_QP_CAP:
1428 return 0;
1429 case IB_QP_DEST_QPN:
1430 return 0;
1431 }
1432 return 0;
1433}
1434
1435static int ib_mask_to_mlx5_opt(int ib_mask)
1436{
1437 int result = 0;
1438 int i;
1439
1440 for (i = 0; i < 8 * sizeof(int); i++) {
1441 if ((1 << i) & ib_mask)
1442 result |= ib_nr_to_mlx5_nr(1 << i);
1443 }
1444
1445 return result;
1446}
1447
1448static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1449 const struct ib_qp_attr *attr, int attr_mask,
1450 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1451{
1452 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1453 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1454 struct mlx5_ib_cq *send_cq, *recv_cq;
1455 struct mlx5_qp_context *context;
1456 struct mlx5_modify_qp_mbox_in *in;
1457 struct mlx5_ib_pd *pd;
1458 enum mlx5_qp_state mlx5_cur, mlx5_new;
1459 enum mlx5_qp_optpar optpar;
1460 int sqd_event;
1461 int mlx5_st;
1462 int err;
1463
1464 in = kzalloc(sizeof(*in), GFP_KERNEL);
1465 if (!in)
1466 return -ENOMEM;
1467
1468 context = &in->ctx;
1469 err = to_mlx5_st(ibqp->qp_type);
1470 if (err < 0)
1471 goto out;
1472
1473 context->flags = cpu_to_be32(err << 16);
1474
1475 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1476 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1477 } else {
1478 switch (attr->path_mig_state) {
1479 case IB_MIG_MIGRATED:
1480 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1481 break;
1482 case IB_MIG_REARM:
1483 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1484 break;
1485 case IB_MIG_ARMED:
1486 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1487 break;
1488 }
1489 }
1490
1491 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1492 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1493 } else if (ibqp->qp_type == IB_QPT_UD ||
1494 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1495 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1496 } else if (attr_mask & IB_QP_PATH_MTU) {
1497 if (attr->path_mtu < IB_MTU_256 ||
1498 attr->path_mtu > IB_MTU_4096) {
1499 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1500 err = -EINVAL;
1501 goto out;
1502 }
1503 context->mtu_msgmax = (attr->path_mtu << 5) | dev->mdev.caps.log_max_msg;
1504 }
1505
1506 if (attr_mask & IB_QP_DEST_QPN)
1507 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1508
1509 if (attr_mask & IB_QP_PKEY_INDEX)
1510 context->pri_path.pkey_index = attr->pkey_index;
1511
1512 /* todo implement counter_index functionality */
1513
1514 if (is_sqp(ibqp->qp_type))
1515 context->pri_path.port = qp->port;
1516
1517 if (attr_mask & IB_QP_PORT)
1518 context->pri_path.port = attr->port_num;
1519
1520 if (attr_mask & IB_QP_AV) {
1521 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1522 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1523 attr_mask, 0, attr);
1524 if (err)
1525 goto out;
1526 }
1527
1528 if (attr_mask & IB_QP_TIMEOUT)
1529 context->pri_path.ackto_lt |= attr->timeout << 3;
1530
1531 if (attr_mask & IB_QP_ALT_PATH) {
1532 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1533 attr->alt_port_num, attr_mask, 0, attr);
1534 if (err)
1535 goto out;
1536 }
1537
1538 pd = get_pd(qp);
1539 get_cqs(qp, &send_cq, &recv_cq);
1540
1541 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1542 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1543 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1544 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1545
1546 if (attr_mask & IB_QP_RNR_RETRY)
1547 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1548
1549 if (attr_mask & IB_QP_RETRY_CNT)
1550 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1551
1552 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1553 if (attr->max_rd_atomic)
1554 context->params1 |=
1555 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1556 }
1557
1558 if (attr_mask & IB_QP_SQ_PSN)
1559 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1560
1561 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1562 if (attr->max_dest_rd_atomic)
1563 context->params2 |=
1564 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1565 }
1566
1567 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1568 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1569
1570 if (attr_mask & IB_QP_MIN_RNR_TIMER)
1571 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1572
1573 if (attr_mask & IB_QP_RQ_PSN)
1574 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1575
1576 if (attr_mask & IB_QP_QKEY)
1577 context->qkey = cpu_to_be32(attr->qkey);
1578
1579 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1580 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1581
1582 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1583 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1584 sqd_event = 1;
1585 else
1586 sqd_event = 0;
1587
1588 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1589 context->sq_crq_size |= cpu_to_be16(1 << 4);
1590
1591
1592 mlx5_cur = to_mlx5_state(cur_state);
1593 mlx5_new = to_mlx5_state(new_state);
1594 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 1595 if (mlx5_st < 0)
e126ba97
EC		 1596 goto out;
1597
1598 optpar = ib_mask_to_mlx5_opt(attr_mask);
1599 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1600 in->optparam = cpu_to_be32(optpar);
1601 err = mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(cur_state),
1602 to_mlx5_state(new_state), in, sqd_event,
1603 &qp->mqp);
1604 if (err)
1605 goto out;
1606
1607 qp->state = new_state;
1608
1609 if (attr_mask & IB_QP_ACCESS_FLAGS)
1610 qp->atomic_rd_en = attr->qp_access_flags;
1611 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1612 qp->resp_depth = attr->max_dest_rd_atomic;
1613 if (attr_mask & IB_QP_PORT)
1614 qp->port = attr->port_num;
1615 if (attr_mask & IB_QP_ALT_PATH)
1616 qp->alt_port = attr->alt_port_num;
1617
1618 /*
1619 * If we moved a kernel QP to RESET, clean up all old CQ
1620 * entries and reinitialize the QP.
1621 */
1622 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1623 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1624 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1625 if (send_cq != recv_cq)
1626 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1627
1628 qp->rq.head = 0;
1629 qp->rq.tail = 0;
1630 qp->sq.head = 0;
1631 qp->sq.tail = 0;
1632 qp->sq.cur_post = 0;
1633 qp->sq.last_poll = 0;
1634 qp->db.db[MLX5_RCV_DBR] = 0;
1635 qp->db.db[MLX5_SND_DBR] = 0;
1636 }
1637
1638out:
1639 kfree(in);
1640 return err;
1641}
1642
1643int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1644 int attr_mask, struct ib_udata *udata)
1645{
1646 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1647 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1648 enum ib_qp_state cur_state, new_state;
1649 int err = -EINVAL;
1650 int port;
1651
1652 mutex_lock(&qp->mutex);
1653
1654 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1655 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1656
1657 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1658 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1659 goto out;
1660
1661 if ((attr_mask & IB_QP_PORT) &&
1662 (attr->port_num == 0 || attr->port_num > dev->mdev.caps.num_ports))
1663 goto out;
1664
1665 if (attr_mask & IB_QP_PKEY_INDEX) {
1666 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1667 if (attr->pkey_index >= dev->mdev.caps.port[port - 1].pkey_table_len)
1668 goto out;
1669 }
1670
1671 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1672 attr->max_rd_atomic > dev->mdev.caps.max_ra_res_qp)
1673 goto out;
1674
1675 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1676 attr->max_dest_rd_atomic > dev->mdev.caps.max_ra_req_qp)
1677 goto out;
1678
1679 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1680 err = 0;
1681 goto out;
1682 }
1683
1684 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1685
1686out:
1687 mutex_unlock(&qp->mutex);
1688 return err;
1689}
1690
1691static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1692{
1693 struct mlx5_ib_cq *cq;
1694 unsigned cur;
1695
1696 cur = wq->head - wq->tail;
1697 if (likely(cur + nreq < wq->max_post))
1698 return 0;
1699
1700 cq = to_mcq(ib_cq);
1701 spin_lock(&cq->lock);
1702 cur = wq->head - wq->tail;
1703 spin_unlock(&cq->lock);
1704
1705 return cur + nreq >= wq->max_post;
1706}
1707
1708static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1709 u64 remote_addr, u32 rkey)
1710{
1711 rseg->raddr = cpu_to_be64(remote_addr);
1712 rseg->rkey = cpu_to_be32(rkey);
1713 rseg->reserved = 0;
1714}
1715
e126ba97
EC		 1716static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1717 struct ib_send_wr *wr)
1718{
1719 memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1720 dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1721 dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1722}
1723
1724static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1725{
1726 dseg->byte_count = cpu_to_be32(sg->length);
1727 dseg->lkey = cpu_to_be32(sg->lkey);
1728 dseg->addr = cpu_to_be64(sg->addr);
1729}
1730
1731static __be16 get_klm_octo(int npages)
1732{
1733 return cpu_to_be16(ALIGN(npages, 8) / 2);
1734}
1735
1736static __be64 frwr_mkey_mask(void)
1737{
1738 u64 result;
1739
1740 result = MLX5_MKEY_MASK_LEN |
1741 MLX5_MKEY_MASK_PAGE_SIZE |
1742 MLX5_MKEY_MASK_START_ADDR |
1743 MLX5_MKEY_MASK_EN_RINVAL |
1744 MLX5_MKEY_MASK_KEY |
1745 MLX5_MKEY_MASK_LR |
1746 MLX5_MKEY_MASK_LW |
1747 MLX5_MKEY_MASK_RR |
1748 MLX5_MKEY_MASK_RW |
1749 MLX5_MKEY_MASK_A |
1750 MLX5_MKEY_MASK_SMALL_FENCE |
1751 MLX5_MKEY_MASK_FREE;
1752
1753 return cpu_to_be64(result);
1754}
1755
1756static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1757 struct ib_send_wr *wr, int li)
1758{
1759 memset(umr, 0, sizeof(*umr));
1760
1761 if (li) {
1762 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1763 umr->flags = 1 << 7;
1764 return;
1765 }
1766
1767 umr->flags = (1 << 5); /* fail if not free */
1768 umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1769 umr->mkey_mask = frwr_mkey_mask();
1770}
1771
1772static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1773 struct ib_send_wr *wr)
1774{
1775 struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg;
1776 u64 mask;
1777
1778 memset(umr, 0, sizeof(*umr));
1779
1780 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1781 umr->flags = 1 << 5; /* fail if not free */
1782 umr->klm_octowords = get_klm_octo(umrwr->npages);
1783 mask = MLX5_MKEY_MASK_LEN |
1784 MLX5_MKEY_MASK_PAGE_SIZE |
1785 MLX5_MKEY_MASK_START_ADDR |
1786 MLX5_MKEY_MASK_PD |
1787 MLX5_MKEY_MASK_LR |
1788 MLX5_MKEY_MASK_LW |
746b5583 1789 MLX5_MKEY_MASK_KEY |
e126ba97
EC		 1790 MLX5_MKEY_MASK_RR |
1791 MLX5_MKEY_MASK_RW |
1792 MLX5_MKEY_MASK_A |
1793 MLX5_MKEY_MASK_FREE;
1794 umr->mkey_mask = cpu_to_be64(mask);
1795 } else {
1796 umr->flags = 2 << 5; /* fail if free */
1797 mask = MLX5_MKEY_MASK_FREE;
1798 umr->mkey_mask = cpu_to_be64(mask);
1799 }
1800
1801 if (!wr->num_sge)
1802 umr->flags |= (1 << 7); /* inline */
1803}
1804
1805static u8 get_umr_flags(int acc)
1806{
1807 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1808 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1809 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1810 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1811 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
1812}
1813
1814static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1815 int li, int *writ)
1816{
1817 memset(seg, 0, sizeof(*seg));
1818 if (li) {
1819 seg->status = 1 << 6;
1820 return;
1821 }
1822
1823 seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags);
1824 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
1825 seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
1826 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
1827 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1828 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1829 seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
1830 seg->log2_page_size = wr->wr.fast_reg.page_shift;
1831}
1832
1833static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
1834{
1835 memset(seg, 0, sizeof(*seg));
1836 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
1837 seg->status = 1 << 6;
1838 return;
1839 }
1840
1841 seg->flags = convert_access(wr->wr.fast_reg.access_flags);
1842 seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn);
1843 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1844 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1845 seg->log2_page_size = wr->wr.fast_reg.page_shift;
746b5583
EC		 1846 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
1847 mlx5_mkey_variant(wr->wr.fast_reg.rkey));
e126ba97
EC		 1848}
1849
1850static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
1851 struct ib_send_wr *wr,
1852 struct mlx5_core_dev *mdev,
1853 struct mlx5_ib_pd *pd,
1854 int writ)
1855{
1856 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1857 u64 *page_list = wr->wr.fast_reg.page_list->page_list;
1858 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
1859 int i;
1860
1861 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
1862 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
1863 dseg->addr = cpu_to_be64(mfrpl->map);
1864 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
1865 dseg->lkey = cpu_to_be32(pd->pa_lkey);
1866}
1867
1868static __be32 send_ieth(struct ib_send_wr *wr)
1869{
1870 switch (wr->opcode) {
1871 case IB_WR_SEND_WITH_IMM:
1872 case IB_WR_RDMA_WRITE_WITH_IMM:
1873 return wr->ex.imm_data;
1874
1875 case IB_WR_SEND_WITH_INV:
1876 return cpu_to_be32(wr->ex.invalidate_rkey);
1877
1878 default:
1879 return 0;
1880 }
1881}
1882
1883static u8 calc_sig(void *wqe, int size)
1884{
1885 u8 *p = wqe;
1886 u8 res = 0;
1887 int i;
1888
1889 for (i = 0; i < size; i++)
1890 res ^= p[i];
1891
1892 return ~res;
1893}
1894
1895static u8 wq_sig(void *wqe)
1896{
1897 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
1898}
1899
1900static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
1901 void *wqe, int *sz)
1902{
1903 struct mlx5_wqe_inline_seg *seg;
1904 void *qend = qp->sq.qend;
1905 void *addr;
1906 int inl = 0;
1907 int copy;
1908 int len;
1909 int i;
1910
1911 seg = wqe;
1912 wqe += sizeof(*seg);
1913 for (i = 0; i < wr->num_sge; i++) {
1914 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
1915 len = wr->sg_list[i].length;
1916 inl += len;
1917
1918 if (unlikely(inl > qp->max_inline_data))
1919 return -ENOMEM;
1920
1921 if (unlikely(wqe + len > qend)) {
1922 copy = qend - wqe;
1923 memcpy(wqe, addr, copy);
1924 addr += copy;
1925 len -= copy;
1926 wqe = mlx5_get_send_wqe(qp, 0);
1927 }
1928 memcpy(wqe, addr, len);
1929 wqe += len;
1930 }
1931
1932 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
1933
1934 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
1935
1936 return 0;
1937}
1938
1939static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
1940 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
1941{
1942 int writ = 0;
1943 int li;
1944
1945 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
1946 if (unlikely(wr->send_flags & IB_SEND_INLINE))
1947 return -EINVAL;
1948
1949 set_frwr_umr_segment(*seg, wr, li);
1950 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
1951 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
1952 if (unlikely((*seg == qp->sq.qend)))
1953 *seg = mlx5_get_send_wqe(qp, 0);
1954 set_mkey_segment(*seg, wr, li, &writ);
1955 *seg += sizeof(struct mlx5_mkey_seg);
1956 *size += sizeof(struct mlx5_mkey_seg) / 16;
1957 if (unlikely((*seg == qp->sq.qend)))
1958 *seg = mlx5_get_send_wqe(qp, 0);
1959 if (!li) {
9641b74e
EC		 1960 if (unlikely(wr->wr.fast_reg.page_list_len >
1961 wr->wr.fast_reg.page_list->max_page_list_len))
1962 return -ENOMEM;
1963
e126ba97
EC		 1964 set_frwr_pages(*seg, wr, mdev, pd, writ);
1965 *seg += sizeof(struct mlx5_wqe_data_seg);
1966 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
1967 }
1968 return 0;
1969}
1970
1971static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
1972{
1973 __be32 *p = NULL;
1974 int tidx = idx;
1975 int i, j;
1976
1977 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
1978 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
1979 if ((i & 0xf) == 0) {
1980 void *buf = mlx5_get_send_wqe(qp, tidx);
1981 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
1982 p = buf;
1983 j = 0;
1984 }
1985 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
1986 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
1987 be32_to_cpu(p[j + 3]));
1988 }
1989}
1990
1991static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
1992 unsigned bytecnt, struct mlx5_ib_qp *qp)
1993{
1994 while (bytecnt > 0) {
1995 __iowrite64_copy(dst++, src++, 8);
1996 __iowrite64_copy(dst++, src++, 8);
1997 __iowrite64_copy(dst++, src++, 8);
1998 __iowrite64_copy(dst++, src++, 8);
1999 __iowrite64_copy(dst++, src++, 8);
2000 __iowrite64_copy(dst++, src++, 8);
2001 __iowrite64_copy(dst++, src++, 8);
2002 __iowrite64_copy(dst++, src++, 8);
2003 bytecnt -= 64;
2004 if (unlikely(src == qp->sq.qend))
2005 src = mlx5_get_send_wqe(qp, 0);
2006 }
2007}
2008
2009static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2010{
2011 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2012 wr->send_flags & IB_SEND_FENCE))
2013 return MLX5_FENCE_MODE_STRONG_ORDERING;
2014
2015 if (unlikely(fence)) {
2016 if (wr->send_flags & IB_SEND_FENCE)
2017 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2018 else
2019 return fence;
2020
2021 } else {
2022 return 0;
2023 }
2024}
2025
2026int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2027 struct ib_send_wr **bad_wr)
2028{
2029 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
2030 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2031 struct mlx5_core_dev *mdev = &dev->mdev;
2032 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2033 struct mlx5_wqe_data_seg *dpseg;
2034 struct mlx5_wqe_xrc_seg *xrc;
2035 struct mlx5_bf *bf = qp->bf;
2036 int uninitialized_var(size);
2037 void *qend = qp->sq.qend;
2038 unsigned long flags;
2039 u32 mlx5_opcode;
2040 unsigned idx;
2041 int err = 0;
2042 int inl = 0;
2043 int num_sge;
2044 void *seg;
2045 int nreq;
2046 int i;
2047 u8 next_fence = 0;
2048 u8 opmod = 0;
2049 u8 fence;
2050
2051 spin_lock_irqsave(&qp->sq.lock, flags);
2052
2053 for (nreq = 0; wr; nreq++, wr = wr->next) {
2054 if (unlikely(wr->opcode >= sizeof(mlx5_ib_opcode) / sizeof(mlx5_ib_opcode[0]))) {
2055 mlx5_ib_warn(dev, "\n");
2056 err = -EINVAL;
2057 *bad_wr = wr;
2058 goto out;
2059 }
2060
2061 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2062 mlx5_ib_warn(dev, "\n");
2063 err = -ENOMEM;
2064 *bad_wr = wr;
2065 goto out;
2066 }
2067
2068 fence = qp->fm_cache;
2069 num_sge = wr->num_sge;
2070 if (unlikely(num_sge > qp->sq.max_gs)) {
2071 mlx5_ib_warn(dev, "\n");
2072 err = -ENOMEM;
2073 *bad_wr = wr;
2074 goto out;
2075 }
2076
2077 idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2078 seg = mlx5_get_send_wqe(qp, idx);
2079 ctrl = seg;
2080 *(uint32_t *)(seg + 8) = 0;
2081 ctrl->imm = send_ieth(wr);
2082 ctrl->fm_ce_se = qp->sq_signal_bits |
2083 (wr->send_flags & IB_SEND_SIGNALED ?
2084 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2085 (wr->send_flags & IB_SEND_SOLICITED ?
2086 MLX5_WQE_CTRL_SOLICITED : 0);
2087
2088 seg += sizeof(*ctrl);
2089 size = sizeof(*ctrl) / 16;
2090
2091 switch (ibqp->qp_type) {
2092 case IB_QPT_XRC_INI:
2093 xrc = seg;
2094 xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2095 seg += sizeof(*xrc);
2096 size += sizeof(*xrc) / 16;
2097 /* fall through */
2098 case IB_QPT_RC:
2099 switch (wr->opcode) {
2100 case IB_WR_RDMA_READ:
2101 case IB_WR_RDMA_WRITE:
2102 case IB_WR_RDMA_WRITE_WITH_IMM:
2103 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2104 wr->wr.rdma.rkey);
2105 seg += sizeof(struct mlx5_wqe_raddr_seg);
2106 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2107 break;
2108
2109 case IB_WR_ATOMIC_CMP_AND_SWP:
2110 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 2111 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 2112 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2113 err = -ENOSYS;
2114 *bad_wr = wr;
2115 goto out;
e126ba97
EC		 2116
2117 case IB_WR_LOCAL_INV:
2118 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2119 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2120 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2121 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2122 if (err) {
2123 mlx5_ib_warn(dev, "\n");
2124 *bad_wr = wr;
2125 goto out;
2126 }
2127 num_sge = 0;
2128 break;
2129
2130 case IB_WR_FAST_REG_MR:
2131 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2132 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2133 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2134 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2135 if (err) {
2136 mlx5_ib_warn(dev, "\n");
2137 *bad_wr = wr;
2138 goto out;
2139 }
2140 num_sge = 0;
2141 break;
2142
2143 default:
2144 break;
2145 }
2146 break;
2147
2148 case IB_QPT_UC:
2149 switch (wr->opcode) {
2150 case IB_WR_RDMA_WRITE:
2151 case IB_WR_RDMA_WRITE_WITH_IMM:
2152 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2153 wr->wr.rdma.rkey);
2154 seg += sizeof(struct mlx5_wqe_raddr_seg);
2155 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2156 break;
2157
2158 default:
2159 break;
2160 }
2161 break;
2162
2163 case IB_QPT_UD:
2164 case IB_QPT_SMI:
2165 case IB_QPT_GSI:
2166 set_datagram_seg(seg, wr);
2167 seg += sizeof(struct mlx5_wqe_datagram_seg);
2168 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2169 if (unlikely((seg == qend)))
2170 seg = mlx5_get_send_wqe(qp, 0);
2171 break;
2172
2173 case MLX5_IB_QPT_REG_UMR:
2174 if (wr->opcode != MLX5_IB_WR_UMR) {
2175 err = -EINVAL;
2176 mlx5_ib_warn(dev, "bad opcode\n");
2177 goto out;
2178 }
2179 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2180 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2181 set_reg_umr_segment(seg, wr);
2182 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2183 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2184 if (unlikely((seg == qend)))
2185 seg = mlx5_get_send_wqe(qp, 0);
2186 set_reg_mkey_segment(seg, wr);
2187 seg += sizeof(struct mlx5_mkey_seg);
2188 size += sizeof(struct mlx5_mkey_seg) / 16;
2189 if (unlikely((seg == qend)))
2190 seg = mlx5_get_send_wqe(qp, 0);
2191 break;
2192
2193 default:
2194 break;
2195 }
2196
2197 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2198 int uninitialized_var(sz);
2199
2200 err = set_data_inl_seg(qp, wr, seg, &sz);
2201 if (unlikely(err)) {
2202 mlx5_ib_warn(dev, "\n");
2203 *bad_wr = wr;
2204 goto out;
2205 }
2206 inl = 1;
2207 size += sz;
2208 } else {
2209 dpseg = seg;
2210 for (i = 0; i < num_sge; i++) {
2211 if (unlikely(dpseg == qend)) {
2212 seg = mlx5_get_send_wqe(qp, 0);
2213 dpseg = seg;
2214 }
2215 if (likely(wr->sg_list[i].length)) {
2216 set_data_ptr_seg(dpseg, wr->sg_list + i);
2217 size += sizeof(struct mlx5_wqe_data_seg) / 16;
2218 dpseg++;
2219 }
2220 }
2221 }
2222
2223 mlx5_opcode = mlx5_ib_opcode[wr->opcode];
2224 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2225 mlx5_opcode |
2226 ((u32)opmod << 24));
2227 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2228 ctrl->fm_ce_se |= get_fence(fence, wr);
2229 qp->fm_cache = next_fence;
2230 if (unlikely(qp->wq_sig))
2231 ctrl->signature = wq_sig(ctrl);
2232
2233 qp->sq.wrid[idx] = wr->wr_id;
2234 qp->sq.w_list[idx].opcode = mlx5_opcode;
2235 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2236 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2237 qp->sq.w_list[idx].next = qp->sq.cur_post;
2238
2239 if (0)
2240 dump_wqe(qp, idx, size);
2241 }
2242
2243out:
2244 if (likely(nreq)) {
2245 qp->sq.head += nreq;
2246
2247 /* Make sure that descriptors are written before
2248 * updating doorbell record and ringing the doorbell
2249 */
2250 wmb();
2251
2252 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2253
ada388f7
EC		 2254 /* Make sure doorbell record is visible to the HCA before
2255 * we hit doorbell */
2256 wmb();
2257
e126ba97
EC		 2258 if (bf->need_lock)
2259 spin_lock(&bf->lock);
2260
2261 /* TBD enable WC */
2262 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2263 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2264 /* wc_wmb(); */
2265 } else {
2266 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2267 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2268 /* Make sure doorbells don't leak out of SQ spinlock
2269 * and reach the HCA out of order.
2270 */
2271 mmiowb();
2272 }
2273 bf->offset ^= bf->buf_size;
2274 if (bf->need_lock)
2275 spin_unlock(&bf->lock);
2276 }
2277
2278 spin_unlock_irqrestore(&qp->sq.lock, flags);
2279
2280 return err;
2281}
2282
2283static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2284{
2285 sig->signature = calc_sig(sig, size);
2286}
2287
2288int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2289 struct ib_recv_wr **bad_wr)
2290{
2291 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2292 struct mlx5_wqe_data_seg *scat;
2293 struct mlx5_rwqe_sig *sig;
2294 unsigned long flags;
2295 int err = 0;
2296 int nreq;
2297 int ind;
2298 int i;
2299
2300 spin_lock_irqsave(&qp->rq.lock, flags);
2301
2302 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2303
2304 for (nreq = 0; wr; nreq++, wr = wr->next) {
2305 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2306 err = -ENOMEM;
2307 *bad_wr = wr;
2308 goto out;
2309 }
2310
2311 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2312 err = -EINVAL;
2313 *bad_wr = wr;
2314 goto out;
2315 }
2316
2317 scat = get_recv_wqe(qp, ind);
2318 if (qp->wq_sig)
2319 scat++;
2320
2321 for (i = 0; i < wr->num_sge; i++)
2322 set_data_ptr_seg(scat + i, wr->sg_list + i);
2323
2324 if (i < qp->rq.max_gs) {
2325 scat[i].byte_count = 0;
2326 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
2327 scat[i].addr = 0;
2328 }
2329
2330 if (qp->wq_sig) {
2331 sig = (struct mlx5_rwqe_sig *)scat;
2332 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2333 }
2334
2335 qp->rq.wrid[ind] = wr->wr_id;
2336
2337 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2338 }
2339
2340out:
2341 if (likely(nreq)) {
2342 qp->rq.head += nreq;
2343
2344 /* Make sure that descriptors are written before
2345 * doorbell record.
2346 */
2347 wmb();
2348
2349 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2350 }
2351
2352 spin_unlock_irqrestore(&qp->rq.lock, flags);
2353
2354 return err;
2355}
2356
2357static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2358{
2359 switch (mlx5_state) {
2360 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
2361 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
2362 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
2363 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
2364 case MLX5_QP_STATE_SQ_DRAINING:
2365 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
2366 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
2367 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
2368 default: return -1;
2369 }
2370}
2371
2372static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2373{
2374 switch (mlx5_mig_state) {
2375 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
2376 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
2377 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
2378 default: return -1;
2379 }
2380}
2381
2382static int to_ib_qp_access_flags(int mlx5_flags)
2383{
2384 int ib_flags = 0;
2385
2386 if (mlx5_flags & MLX5_QP_BIT_RRE)
2387 ib_flags |= IB_ACCESS_REMOTE_READ;
2388 if (mlx5_flags & MLX5_QP_BIT_RWE)
2389 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2390 if (mlx5_flags & MLX5_QP_BIT_RAE)
2391 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2392
2393 return ib_flags;
2394}
2395
2396static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2397 struct mlx5_qp_path *path)
2398{
2399 struct mlx5_core_dev *dev = &ibdev->mdev;
2400
2401 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
2402 ib_ah_attr->port_num = path->port;
2403
2404 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2405 return;
2406
2407 ib_ah_attr->sl = path->sl & 0xf;
2408
2409 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
2410 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
2411 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
2412 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
2413 if (ib_ah_attr->ah_flags) {
2414 ib_ah_attr->grh.sgid_index = path->mgid_index;
2415 ib_ah_attr->grh.hop_limit = path->hop_limit;
2416 ib_ah_attr->grh.traffic_class =
2417 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2418 ib_ah_attr->grh.flow_label =
2419 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2420 memcpy(ib_ah_attr->grh.dgid.raw,
2421 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
2422 }
2423}
2424
2425int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2426 struct ib_qp_init_attr *qp_init_attr)
2427{
2428 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2429 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2430 struct mlx5_query_qp_mbox_out *outb;
2431 struct mlx5_qp_context *context;
2432 int mlx5_state;
2433 int err = 0;
2434
2435 mutex_lock(&qp->mutex);
2436 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
2437 if (!outb) {
2438 err = -ENOMEM;
2439 goto out;
2440 }
2441 context = &outb->ctx;
2442 err = mlx5_core_qp_query(&dev->mdev, &qp->mqp, outb, sizeof(*outb));
2443 if (err)
2444 goto out_free;
2445
2446 mlx5_state = be32_to_cpu(context->flags) >> 28;
2447
2448 qp->state = to_ib_qp_state(mlx5_state);
2449 qp_attr->qp_state = qp->state;
2450 qp_attr->path_mtu = context->mtu_msgmax >> 5;
2451 qp_attr->path_mig_state =
2452 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
2453 qp_attr->qkey = be32_to_cpu(context->qkey);
2454 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
2455 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
2456 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
2457 qp_attr->qp_access_flags =
2458 to_ib_qp_access_flags(be32_to_cpu(context->params2));
2459
2460 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2461 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
2462 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
2463 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
2464 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
2465 }
2466
2467 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
2468 qp_attr->port_num = context->pri_path.port;
2469
2470 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2471 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
2472
2473 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
2474
2475 qp_attr->max_dest_rd_atomic =
2476 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
2477 qp_attr->min_rnr_timer =
2478 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
2479 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
2480 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
2481 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
2482 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
2483 qp_attr->cur_qp_state = qp_attr->qp_state;
2484 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
2485 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
2486
2487 if (!ibqp->uobject) {
2488 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
2489 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2490 } else {
2491 qp_attr->cap.max_send_wr = 0;
2492 qp_attr->cap.max_send_sge = 0;
2493 }
2494
2495 /* We don't support inline sends for kernel QPs (yet), and we
2496 * don't know what userspace's value should be.
2497 */
2498 qp_attr->cap.max_inline_data = 0;
2499
2500 qp_init_attr->cap = qp_attr->cap;
2501
2502 qp_init_attr->create_flags = 0;
2503 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2504 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2505
2506 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
2507 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2508
2509out_free:
2510 kfree(outb);
2511
2512out:
2513 mutex_unlock(&qp->mutex);
2514 return err;
2515}
2516
2517struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
2518 struct ib_ucontext *context,
2519 struct ib_udata *udata)
2520{
2521 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2522 struct mlx5_ib_xrcd *xrcd;
2523 int err;
2524
2525 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC))
2526 return ERR_PTR(-ENOSYS);
2527
2528 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
2529 if (!xrcd)
2530 return ERR_PTR(-ENOMEM);
2531
2532 err = mlx5_core_xrcd_alloc(&dev->mdev, &xrcd->xrcdn);
2533 if (err) {
2534 kfree(xrcd);
2535 return ERR_PTR(-ENOMEM);
2536 }
2537
2538 return &xrcd->ibxrcd;
2539}
2540
2541int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
2542{
2543 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
2544 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
2545 int err;
2546
2547 err = mlx5_core_xrcd_dealloc(&dev->mdev, xrcdn);
2548 if (err) {
2549 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
2550 return err;
2551 }
2552
2553 kfree(xrcd);
2554
2555 return 0;
2556}
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