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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <rdma/ib_umem.h> | |
2811ba51 | 35 | #include <rdma/ib_cache.h> |
cfb5e088 | 36 | #include <rdma/ib_user_verbs.h> |
c2e53b2c | 37 | #include <linux/mlx5/fs.h> |
e126ba97 | 38 | #include "mlx5_ib.h" |
b96c9dde | 39 | #include "ib_rep.h" |
e126ba97 EC |
40 | |
41 | /* not supported currently */ | |
42 | static int wq_signature; | |
43 | ||
44 | enum { | |
45 | MLX5_IB_ACK_REQ_FREQ = 8, | |
46 | }; | |
47 | ||
48 | enum { | |
49 | MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, | |
50 | MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, | |
51 | MLX5_IB_LINK_TYPE_IB = 0, | |
52 | MLX5_IB_LINK_TYPE_ETH = 1 | |
53 | }; | |
54 | ||
55 | enum { | |
56 | MLX5_IB_SQ_STRIDE = 6, | |
064e5262 | 57 | MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, |
e126ba97 EC |
58 | }; |
59 | ||
60 | static const u32 mlx5_ib_opcode[] = { | |
61 | [IB_WR_SEND] = MLX5_OPCODE_SEND, | |
f0313965 | 62 | [IB_WR_LSO] = MLX5_OPCODE_LSO, |
e126ba97 EC |
63 | [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, |
64 | [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, | |
65 | [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, | |
66 | [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, | |
67 | [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, | |
68 | [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, | |
69 | [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, | |
70 | [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, | |
8a187ee5 | 71 | [IB_WR_REG_MR] = MLX5_OPCODE_UMR, |
e126ba97 EC |
72 | [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, |
73 | [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, | |
74 | [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, | |
75 | }; | |
76 | ||
f0313965 ES |
77 | struct mlx5_wqe_eth_pad { |
78 | u8 rsvd0[16]; | |
79 | }; | |
e126ba97 | 80 | |
eb49ab0c AV |
81 | enum raw_qp_set_mask_map { |
82 | MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, | |
7d29f349 | 83 | MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, |
eb49ab0c AV |
84 | }; |
85 | ||
0680efa2 AV |
86 | struct mlx5_modify_raw_qp_param { |
87 | u16 operation; | |
eb49ab0c AV |
88 | |
89 | u32 set_mask; /* raw_qp_set_mask_map */ | |
61147f39 BW |
90 | |
91 | struct mlx5_rate_limit rl; | |
92 | ||
eb49ab0c | 93 | u8 rq_q_ctr_id; |
0680efa2 AV |
94 | }; |
95 | ||
89ea94a7 MG |
96 | static void get_cqs(enum ib_qp_type qp_type, |
97 | struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, | |
98 | struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); | |
99 | ||
e126ba97 EC |
100 | static int is_qp0(enum ib_qp_type qp_type) |
101 | { | |
102 | return qp_type == IB_QPT_SMI; | |
103 | } | |
104 | ||
e126ba97 EC |
105 | static int is_sqp(enum ib_qp_type qp_type) |
106 | { | |
107 | return is_qp0(qp_type) || is_qp1(qp_type); | |
108 | } | |
109 | ||
110 | static void *get_wqe(struct mlx5_ib_qp *qp, int offset) | |
111 | { | |
112 | return mlx5_buf_offset(&qp->buf, offset); | |
113 | } | |
114 | ||
115 | static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) | |
116 | { | |
117 | return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); | |
118 | } | |
119 | ||
120 | void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) | |
121 | { | |
122 | return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); | |
123 | } | |
124 | ||
c1395a2a HE |
125 | /** |
126 | * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. | |
127 | * | |
128 | * @qp: QP to copy from. | |
129 | * @send: copy from the send queue when non-zero, use the receive queue | |
130 | * otherwise. | |
131 | * @wqe_index: index to start copying from. For send work queues, the | |
132 | * wqe_index is in units of MLX5_SEND_WQE_BB. | |
133 | * For receive work queue, it is the number of work queue | |
134 | * element in the queue. | |
135 | * @buffer: destination buffer. | |
136 | * @length: maximum number of bytes to copy. | |
137 | * | |
138 | * Copies at least a single WQE, but may copy more data. | |
139 | * | |
140 | * Return: the number of bytes copied, or an error code. | |
141 | */ | |
142 | int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, | |
19098df2 | 143 | void *buffer, u32 length, |
144 | struct mlx5_ib_qp_base *base) | |
c1395a2a HE |
145 | { |
146 | struct ib_device *ibdev = qp->ibqp.device; | |
147 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
148 | struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; | |
149 | size_t offset; | |
150 | size_t wq_end; | |
19098df2 | 151 | struct ib_umem *umem = base->ubuffer.umem; |
c1395a2a HE |
152 | u32 first_copy_length; |
153 | int wqe_length; | |
154 | int ret; | |
155 | ||
156 | if (wq->wqe_cnt == 0) { | |
157 | mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", | |
158 | qp->ibqp.qp_type); | |
159 | return -EINVAL; | |
160 | } | |
161 | ||
162 | offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); | |
163 | wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); | |
164 | ||
165 | if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) | |
166 | return -EINVAL; | |
167 | ||
168 | if (offset > umem->length || | |
169 | (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) | |
170 | return -EINVAL; | |
171 | ||
172 | first_copy_length = min_t(u32, offset + length, wq_end) - offset; | |
173 | ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); | |
174 | if (ret) | |
175 | return ret; | |
176 | ||
177 | if (send) { | |
178 | struct mlx5_wqe_ctrl_seg *ctrl = buffer; | |
179 | int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; | |
180 | ||
181 | wqe_length = ds * MLX5_WQE_DS_UNITS; | |
182 | } else { | |
183 | wqe_length = 1 << wq->wqe_shift; | |
184 | } | |
185 | ||
186 | if (wqe_length <= first_copy_length) | |
187 | return first_copy_length; | |
188 | ||
189 | ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, | |
190 | wqe_length - first_copy_length); | |
191 | if (ret) | |
192 | return ret; | |
193 | ||
194 | return wqe_length; | |
195 | } | |
196 | ||
e126ba97 EC |
197 | static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) |
198 | { | |
199 | struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; | |
200 | struct ib_event event; | |
201 | ||
19098df2 | 202 | if (type == MLX5_EVENT_TYPE_PATH_MIG) { |
203 | /* This event is only valid for trans_qps */ | |
204 | to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; | |
205 | } | |
e126ba97 EC |
206 | |
207 | if (ibqp->event_handler) { | |
208 | event.device = ibqp->device; | |
209 | event.element.qp = ibqp; | |
210 | switch (type) { | |
211 | case MLX5_EVENT_TYPE_PATH_MIG: | |
212 | event.event = IB_EVENT_PATH_MIG; | |
213 | break; | |
214 | case MLX5_EVENT_TYPE_COMM_EST: | |
215 | event.event = IB_EVENT_COMM_EST; | |
216 | break; | |
217 | case MLX5_EVENT_TYPE_SQ_DRAINED: | |
218 | event.event = IB_EVENT_SQ_DRAINED; | |
219 | break; | |
220 | case MLX5_EVENT_TYPE_SRQ_LAST_WQE: | |
221 | event.event = IB_EVENT_QP_LAST_WQE_REACHED; | |
222 | break; | |
223 | case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: | |
224 | event.event = IB_EVENT_QP_FATAL; | |
225 | break; | |
226 | case MLX5_EVENT_TYPE_PATH_MIG_FAILED: | |
227 | event.event = IB_EVENT_PATH_MIG_ERR; | |
228 | break; | |
229 | case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: | |
230 | event.event = IB_EVENT_QP_REQ_ERR; | |
231 | break; | |
232 | case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: | |
233 | event.event = IB_EVENT_QP_ACCESS_ERR; | |
234 | break; | |
235 | default: | |
236 | pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); | |
237 | return; | |
238 | } | |
239 | ||
240 | ibqp->event_handler(&event, ibqp->qp_context); | |
241 | } | |
242 | } | |
243 | ||
244 | static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, | |
245 | int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) | |
246 | { | |
247 | int wqe_size; | |
248 | int wq_size; | |
249 | ||
250 | /* Sanity check RQ size before proceeding */ | |
938fe83c | 251 | if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) |
e126ba97 EC |
252 | return -EINVAL; |
253 | ||
254 | if (!has_rq) { | |
255 | qp->rq.max_gs = 0; | |
256 | qp->rq.wqe_cnt = 0; | |
257 | qp->rq.wqe_shift = 0; | |
0540d814 NO |
258 | cap->max_recv_wr = 0; |
259 | cap->max_recv_sge = 0; | |
e126ba97 EC |
260 | } else { |
261 | if (ucmd) { | |
262 | qp->rq.wqe_cnt = ucmd->rq_wqe_count; | |
002bf228 LR |
263 | if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) |
264 | return -EINVAL; | |
e126ba97 | 265 | qp->rq.wqe_shift = ucmd->rq_wqe_shift; |
002bf228 LR |
266 | if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) |
267 | return -EINVAL; | |
e126ba97 EC |
268 | qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; |
269 | qp->rq.max_post = qp->rq.wqe_cnt; | |
270 | } else { | |
271 | wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; | |
272 | wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); | |
273 | wqe_size = roundup_pow_of_two(wqe_size); | |
274 | wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; | |
275 | wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); | |
276 | qp->rq.wqe_cnt = wq_size / wqe_size; | |
938fe83c | 277 | if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { |
e126ba97 EC |
278 | mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", |
279 | wqe_size, | |
938fe83c SM |
280 | MLX5_CAP_GEN(dev->mdev, |
281 | max_wqe_sz_rq)); | |
e126ba97 EC |
282 | return -EINVAL; |
283 | } | |
284 | qp->rq.wqe_shift = ilog2(wqe_size); | |
285 | qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; | |
286 | qp->rq.max_post = qp->rq.wqe_cnt; | |
287 | } | |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
f0313965 | 293 | static int sq_overhead(struct ib_qp_init_attr *attr) |
e126ba97 | 294 | { |
618af384 | 295 | int size = 0; |
e126ba97 | 296 | |
f0313965 | 297 | switch (attr->qp_type) { |
e126ba97 | 298 | case IB_QPT_XRC_INI: |
b125a54b | 299 | size += sizeof(struct mlx5_wqe_xrc_seg); |
e126ba97 EC |
300 | /* fall through */ |
301 | case IB_QPT_RC: | |
302 | size += sizeof(struct mlx5_wqe_ctrl_seg) + | |
75c1657e LR |
303 | max(sizeof(struct mlx5_wqe_atomic_seg) + |
304 | sizeof(struct mlx5_wqe_raddr_seg), | |
305 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + | |
064e5262 IB |
306 | sizeof(struct mlx5_mkey_seg) + |
307 | MLX5_IB_SQ_UMR_INLINE_THRESHOLD / | |
308 | MLX5_IB_UMR_OCTOWORD); | |
e126ba97 EC |
309 | break; |
310 | ||
b125a54b EC |
311 | case IB_QPT_XRC_TGT: |
312 | return 0; | |
313 | ||
e126ba97 | 314 | case IB_QPT_UC: |
b125a54b | 315 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
75c1657e LR |
316 | max(sizeof(struct mlx5_wqe_raddr_seg), |
317 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + | |
318 | sizeof(struct mlx5_mkey_seg)); | |
e126ba97 EC |
319 | break; |
320 | ||
321 | case IB_QPT_UD: | |
f0313965 ES |
322 | if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) |
323 | size += sizeof(struct mlx5_wqe_eth_pad) + | |
324 | sizeof(struct mlx5_wqe_eth_seg); | |
325 | /* fall through */ | |
e126ba97 | 326 | case IB_QPT_SMI: |
d16e91da | 327 | case MLX5_IB_QPT_HW_GSI: |
b125a54b | 328 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
e126ba97 EC |
329 | sizeof(struct mlx5_wqe_datagram_seg); |
330 | break; | |
331 | ||
332 | case MLX5_IB_QPT_REG_UMR: | |
b125a54b | 333 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
e126ba97 EC |
334 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + |
335 | sizeof(struct mlx5_mkey_seg); | |
336 | break; | |
337 | ||
338 | default: | |
339 | return -EINVAL; | |
340 | } | |
341 | ||
342 | return size; | |
343 | } | |
344 | ||
345 | static int calc_send_wqe(struct ib_qp_init_attr *attr) | |
346 | { | |
347 | int inl_size = 0; | |
348 | int size; | |
349 | ||
f0313965 | 350 | size = sq_overhead(attr); |
e126ba97 EC |
351 | if (size < 0) |
352 | return size; | |
353 | ||
354 | if (attr->cap.max_inline_data) { | |
355 | inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + | |
356 | attr->cap.max_inline_data; | |
357 | } | |
358 | ||
359 | size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); | |
e1e66cc2 SG |
360 | if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && |
361 | ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) | |
362 | return MLX5_SIG_WQE_SIZE; | |
363 | else | |
364 | return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); | |
e126ba97 EC |
365 | } |
366 | ||
288c01b7 EC |
367 | static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) |
368 | { | |
369 | int max_sge; | |
370 | ||
371 | if (attr->qp_type == IB_QPT_RC) | |
372 | max_sge = (min_t(int, wqe_size, 512) - | |
373 | sizeof(struct mlx5_wqe_ctrl_seg) - | |
374 | sizeof(struct mlx5_wqe_raddr_seg)) / | |
375 | sizeof(struct mlx5_wqe_data_seg); | |
376 | else if (attr->qp_type == IB_QPT_XRC_INI) | |
377 | max_sge = (min_t(int, wqe_size, 512) - | |
378 | sizeof(struct mlx5_wqe_ctrl_seg) - | |
379 | sizeof(struct mlx5_wqe_xrc_seg) - | |
380 | sizeof(struct mlx5_wqe_raddr_seg)) / | |
381 | sizeof(struct mlx5_wqe_data_seg); | |
382 | else | |
383 | max_sge = (wqe_size - sq_overhead(attr)) / | |
384 | sizeof(struct mlx5_wqe_data_seg); | |
385 | ||
386 | return min_t(int, max_sge, wqe_size - sq_overhead(attr) / | |
387 | sizeof(struct mlx5_wqe_data_seg)); | |
388 | } | |
389 | ||
e126ba97 EC |
390 | static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, |
391 | struct mlx5_ib_qp *qp) | |
392 | { | |
393 | int wqe_size; | |
394 | int wq_size; | |
395 | ||
396 | if (!attr->cap.max_send_wr) | |
397 | return 0; | |
398 | ||
399 | wqe_size = calc_send_wqe(attr); | |
400 | mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); | |
401 | if (wqe_size < 0) | |
402 | return wqe_size; | |
403 | ||
938fe83c | 404 | if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { |
b125a54b | 405 | mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", |
938fe83c | 406 | wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); |
e126ba97 EC |
407 | return -EINVAL; |
408 | } | |
409 | ||
f0313965 ES |
410 | qp->max_inline_data = wqe_size - sq_overhead(attr) - |
411 | sizeof(struct mlx5_wqe_inline_seg); | |
e126ba97 EC |
412 | attr->cap.max_inline_data = qp->max_inline_data; |
413 | ||
e1e66cc2 SG |
414 | if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) |
415 | qp->signature_en = true; | |
416 | ||
e126ba97 EC |
417 | wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); |
418 | qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; | |
938fe83c | 419 | if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { |
1974ab9d BVA |
420 | mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", |
421 | attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, | |
938fe83c SM |
422 | qp->sq.wqe_cnt, |
423 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); | |
b125a54b EC |
424 | return -ENOMEM; |
425 | } | |
e126ba97 | 426 | qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); |
288c01b7 EC |
427 | qp->sq.max_gs = get_send_sge(attr, wqe_size); |
428 | if (qp->sq.max_gs < attr->cap.max_send_sge) | |
429 | return -ENOMEM; | |
430 | ||
431 | attr->cap.max_send_sge = qp->sq.max_gs; | |
b125a54b EC |
432 | qp->sq.max_post = wq_size / wqe_size; |
433 | attr->cap.max_send_wr = qp->sq.max_post; | |
e126ba97 EC |
434 | |
435 | return wq_size; | |
436 | } | |
437 | ||
438 | static int set_user_buf_size(struct mlx5_ib_dev *dev, | |
439 | struct mlx5_ib_qp *qp, | |
19098df2 | 440 | struct mlx5_ib_create_qp *ucmd, |
0fb2ed66 | 441 | struct mlx5_ib_qp_base *base, |
442 | struct ib_qp_init_attr *attr) | |
e126ba97 EC |
443 | { |
444 | int desc_sz = 1 << qp->sq.wqe_shift; | |
445 | ||
938fe83c | 446 | if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { |
e126ba97 | 447 | mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", |
938fe83c | 448 | desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); |
e126ba97 EC |
449 | return -EINVAL; |
450 | } | |
451 | ||
452 | if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { | |
453 | mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", | |
454 | ucmd->sq_wqe_count, ucmd->sq_wqe_count); | |
455 | return -EINVAL; | |
456 | } | |
457 | ||
458 | qp->sq.wqe_cnt = ucmd->sq_wqe_count; | |
459 | ||
938fe83c | 460 | if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { |
e126ba97 | 461 | mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", |
938fe83c SM |
462 | qp->sq.wqe_cnt, |
463 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); | |
e126ba97 EC |
464 | return -EINVAL; |
465 | } | |
466 | ||
c2e53b2c YH |
467 | if (attr->qp_type == IB_QPT_RAW_PACKET || |
468 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 469 | base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; |
470 | qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; | |
471 | } else { | |
472 | base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + | |
473 | (qp->sq.wqe_cnt << 6); | |
474 | } | |
e126ba97 EC |
475 | |
476 | return 0; | |
477 | } | |
478 | ||
479 | static int qp_has_rq(struct ib_qp_init_attr *attr) | |
480 | { | |
481 | if (attr->qp_type == IB_QPT_XRC_INI || | |
482 | attr->qp_type == IB_QPT_XRC_TGT || attr->srq || | |
483 | attr->qp_type == MLX5_IB_QPT_REG_UMR || | |
484 | !attr->cap.max_recv_wr) | |
485 | return 0; | |
486 | ||
487 | return 1; | |
488 | } | |
489 | ||
0b80c14f EC |
490 | enum { |
491 | /* this is the first blue flame register in the array of bfregs assigned | |
492 | * to a processes. Since we do not use it for blue flame but rather | |
493 | * regular 64 bit doorbells, we do not need a lock for maintaiing | |
494 | * "odd/even" order | |
495 | */ | |
496 | NUM_NON_BLUE_FLAME_BFREGS = 1, | |
497 | }; | |
498 | ||
b037c29a EC |
499 | static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) |
500 | { | |
31a78a5a | 501 | return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; |
b037c29a EC |
502 | } |
503 | ||
504 | static int num_med_bfreg(struct mlx5_ib_dev *dev, | |
505 | struct mlx5_bfreg_info *bfregi) | |
c1be5232 EC |
506 | { |
507 | int n; | |
508 | ||
b037c29a EC |
509 | n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - |
510 | NUM_NON_BLUE_FLAME_BFREGS; | |
c1be5232 EC |
511 | |
512 | return n >= 0 ? n : 0; | |
513 | } | |
514 | ||
18b0362e YH |
515 | static int first_med_bfreg(struct mlx5_ib_dev *dev, |
516 | struct mlx5_bfreg_info *bfregi) | |
517 | { | |
518 | return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; | |
519 | } | |
520 | ||
b037c29a EC |
521 | static int first_hi_bfreg(struct mlx5_ib_dev *dev, |
522 | struct mlx5_bfreg_info *bfregi) | |
c1be5232 EC |
523 | { |
524 | int med; | |
c1be5232 | 525 | |
b037c29a EC |
526 | med = num_med_bfreg(dev, bfregi); |
527 | return ++med; | |
c1be5232 EC |
528 | } |
529 | ||
b037c29a EC |
530 | static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, |
531 | struct mlx5_bfreg_info *bfregi) | |
e126ba97 | 532 | { |
e126ba97 EC |
533 | int i; |
534 | ||
b037c29a EC |
535 | for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { |
536 | if (!bfregi->count[i]) { | |
2f5ff264 | 537 | bfregi->count[i]++; |
e126ba97 EC |
538 | return i; |
539 | } | |
540 | } | |
541 | ||
542 | return -ENOMEM; | |
543 | } | |
544 | ||
b037c29a EC |
545 | static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, |
546 | struct mlx5_bfreg_info *bfregi) | |
e126ba97 | 547 | { |
18b0362e | 548 | int minidx = first_med_bfreg(dev, bfregi); |
e126ba97 EC |
549 | int i; |
550 | ||
18b0362e YH |
551 | if (minidx < 0) |
552 | return minidx; | |
553 | ||
554 | for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { | |
2f5ff264 | 555 | if (bfregi->count[i] < bfregi->count[minidx]) |
e126ba97 | 556 | minidx = i; |
0b80c14f EC |
557 | if (!bfregi->count[minidx]) |
558 | break; | |
e126ba97 EC |
559 | } |
560 | ||
2f5ff264 | 561 | bfregi->count[minidx]++; |
e126ba97 EC |
562 | return minidx; |
563 | } | |
564 | ||
b037c29a | 565 | static int alloc_bfreg(struct mlx5_ib_dev *dev, |
ffaf58de | 566 | struct mlx5_bfreg_info *bfregi) |
e126ba97 | 567 | { |
ffaf58de | 568 | int bfregn = -ENOMEM; |
e126ba97 | 569 | |
2f5ff264 | 570 | mutex_lock(&bfregi->lock); |
ffaf58de LR |
571 | if (bfregi->ver >= 2) { |
572 | bfregn = alloc_high_class_bfreg(dev, bfregi); | |
573 | if (bfregn < 0) | |
574 | bfregn = alloc_med_class_bfreg(dev, bfregi); | |
575 | } | |
576 | ||
577 | if (bfregn < 0) { | |
0b80c14f | 578 | BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); |
2f5ff264 EC |
579 | bfregn = 0; |
580 | bfregi->count[bfregn]++; | |
e126ba97 | 581 | } |
2f5ff264 | 582 | mutex_unlock(&bfregi->lock); |
e126ba97 | 583 | |
2f5ff264 | 584 | return bfregn; |
e126ba97 EC |
585 | } |
586 | ||
4ed131d0 | 587 | void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) |
e126ba97 | 588 | { |
2f5ff264 | 589 | mutex_lock(&bfregi->lock); |
b037c29a | 590 | bfregi->count[bfregn]--; |
2f5ff264 | 591 | mutex_unlock(&bfregi->lock); |
e126ba97 EC |
592 | } |
593 | ||
594 | static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) | |
595 | { | |
596 | switch (state) { | |
597 | case IB_QPS_RESET: return MLX5_QP_STATE_RST; | |
598 | case IB_QPS_INIT: return MLX5_QP_STATE_INIT; | |
599 | case IB_QPS_RTR: return MLX5_QP_STATE_RTR; | |
600 | case IB_QPS_RTS: return MLX5_QP_STATE_RTS; | |
601 | case IB_QPS_SQD: return MLX5_QP_STATE_SQD; | |
602 | case IB_QPS_SQE: return MLX5_QP_STATE_SQER; | |
603 | case IB_QPS_ERR: return MLX5_QP_STATE_ERR; | |
604 | default: return -1; | |
605 | } | |
606 | } | |
607 | ||
608 | static int to_mlx5_st(enum ib_qp_type type) | |
609 | { | |
610 | switch (type) { | |
611 | case IB_QPT_RC: return MLX5_QP_ST_RC; | |
612 | case IB_QPT_UC: return MLX5_QP_ST_UC; | |
613 | case IB_QPT_UD: return MLX5_QP_ST_UD; | |
614 | case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; | |
615 | case IB_QPT_XRC_INI: | |
616 | case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; | |
617 | case IB_QPT_SMI: return MLX5_QP_ST_QP0; | |
d16e91da | 618 | case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; |
c32a4f29 | 619 | case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; |
e126ba97 | 620 | case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; |
e126ba97 | 621 | case IB_QPT_RAW_PACKET: |
0fb2ed66 | 622 | case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; |
e126ba97 EC |
623 | case IB_QPT_MAX: |
624 | default: return -EINVAL; | |
625 | } | |
626 | } | |
627 | ||
89ea94a7 MG |
628 | static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, |
629 | struct mlx5_ib_cq *recv_cq); | |
630 | static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, | |
631 | struct mlx5_ib_cq *recv_cq); | |
632 | ||
7c043e90 | 633 | int bfregn_to_uar_index(struct mlx5_ib_dev *dev, |
05f58ceb | 634 | struct mlx5_bfreg_info *bfregi, u32 bfregn, |
7c043e90 | 635 | bool dyn_bfreg) |
e126ba97 | 636 | { |
05f58ceb LR |
637 | unsigned int bfregs_per_sys_page; |
638 | u32 index_of_sys_page; | |
639 | u32 offset; | |
b037c29a EC |
640 | |
641 | bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * | |
642 | MLX5_NON_FP_BFREGS_PER_UAR; | |
643 | index_of_sys_page = bfregn / bfregs_per_sys_page; | |
644 | ||
1ee47ab3 YH |
645 | if (dyn_bfreg) { |
646 | index_of_sys_page += bfregi->num_static_sys_pages; | |
05f58ceb LR |
647 | |
648 | if (index_of_sys_page >= bfregi->num_sys_pages) | |
649 | return -EINVAL; | |
650 | ||
1ee47ab3 YH |
651 | if (bfregn > bfregi->num_dyn_bfregs || |
652 | bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { | |
653 | mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); | |
654 | return -EINVAL; | |
655 | } | |
656 | } | |
b037c29a | 657 | |
1ee47ab3 | 658 | offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; |
b037c29a | 659 | return bfregi->sys_pages[index_of_sys_page] + offset; |
e126ba97 EC |
660 | } |
661 | ||
19098df2 | 662 | static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, |
663 | struct ib_pd *pd, | |
664 | unsigned long addr, size_t size, | |
665 | struct ib_umem **umem, | |
666 | int *npages, int *page_shift, int *ncont, | |
667 | u32 *offset) | |
668 | { | |
669 | int err; | |
670 | ||
671 | *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); | |
672 | if (IS_ERR(*umem)) { | |
673 | mlx5_ib_dbg(dev, "umem_get failed\n"); | |
674 | return PTR_ERR(*umem); | |
675 | } | |
676 | ||
762f899a | 677 | mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); |
19098df2 | 678 | |
679 | err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); | |
680 | if (err) { | |
681 | mlx5_ib_warn(dev, "bad offset\n"); | |
682 | goto err_umem; | |
683 | } | |
684 | ||
685 | mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", | |
686 | addr, size, *npages, *page_shift, *ncont, *offset); | |
687 | ||
688 | return 0; | |
689 | ||
690 | err_umem: | |
691 | ib_umem_release(*umem); | |
692 | *umem = NULL; | |
693 | ||
694 | return err; | |
695 | } | |
696 | ||
fe248c3a MG |
697 | static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
698 | struct mlx5_ib_rwq *rwq) | |
79b20a6c YH |
699 | { |
700 | struct mlx5_ib_ucontext *context; | |
701 | ||
fe248c3a MG |
702 | if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) |
703 | atomic_dec(&dev->delay_drop.rqs_cnt); | |
704 | ||
79b20a6c YH |
705 | context = to_mucontext(pd->uobject->context); |
706 | mlx5_ib_db_unmap_user(context, &rwq->db); | |
707 | if (rwq->umem) | |
708 | ib_umem_release(rwq->umem); | |
709 | } | |
710 | ||
711 | static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, | |
712 | struct mlx5_ib_rwq *rwq, | |
713 | struct mlx5_ib_create_wq *ucmd) | |
714 | { | |
715 | struct mlx5_ib_ucontext *context; | |
716 | int page_shift = 0; | |
717 | int npages; | |
718 | u32 offset = 0; | |
719 | int ncont = 0; | |
720 | int err; | |
721 | ||
722 | if (!ucmd->buf_addr) | |
723 | return -EINVAL; | |
724 | ||
725 | context = to_mucontext(pd->uobject->context); | |
726 | rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, | |
727 | rwq->buf_size, 0, 0); | |
728 | if (IS_ERR(rwq->umem)) { | |
729 | mlx5_ib_dbg(dev, "umem_get failed\n"); | |
730 | err = PTR_ERR(rwq->umem); | |
731 | return err; | |
732 | } | |
733 | ||
762f899a | 734 | mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, |
79b20a6c YH |
735 | &ncont, NULL); |
736 | err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, | |
737 | &rwq->rq_page_offset); | |
738 | if (err) { | |
739 | mlx5_ib_warn(dev, "bad offset\n"); | |
740 | goto err_umem; | |
741 | } | |
742 | ||
743 | rwq->rq_num_pas = ncont; | |
744 | rwq->page_shift = page_shift; | |
745 | rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; | |
746 | rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); | |
747 | ||
748 | mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", | |
749 | (unsigned long long)ucmd->buf_addr, rwq->buf_size, | |
750 | npages, page_shift, ncont, offset); | |
751 | ||
752 | err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); | |
753 | if (err) { | |
754 | mlx5_ib_dbg(dev, "map failed\n"); | |
755 | goto err_umem; | |
756 | } | |
757 | ||
758 | rwq->create_type = MLX5_WQ_USER; | |
759 | return 0; | |
760 | ||
761 | err_umem: | |
762 | ib_umem_release(rwq->umem); | |
763 | return err; | |
764 | } | |
765 | ||
b037c29a EC |
766 | static int adjust_bfregn(struct mlx5_ib_dev *dev, |
767 | struct mlx5_bfreg_info *bfregi, int bfregn) | |
768 | { | |
769 | return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + | |
770 | bfregn % MLX5_NON_FP_BFREGS_PER_UAR; | |
771 | } | |
772 | ||
e126ba97 EC |
773 | static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
774 | struct mlx5_ib_qp *qp, struct ib_udata *udata, | |
0fb2ed66 | 775 | struct ib_qp_init_attr *attr, |
09a7d9ec | 776 | u32 **in, |
19098df2 | 777 | struct mlx5_ib_create_qp_resp *resp, int *inlen, |
778 | struct mlx5_ib_qp_base *base) | |
e126ba97 EC |
779 | { |
780 | struct mlx5_ib_ucontext *context; | |
781 | struct mlx5_ib_create_qp ucmd; | |
19098df2 | 782 | struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; |
9e9c47d0 | 783 | int page_shift = 0; |
1ee47ab3 | 784 | int uar_index = 0; |
e126ba97 | 785 | int npages; |
9e9c47d0 | 786 | u32 offset = 0; |
2f5ff264 | 787 | int bfregn; |
9e9c47d0 | 788 | int ncont = 0; |
09a7d9ec SM |
789 | __be64 *pas; |
790 | void *qpc; | |
e126ba97 EC |
791 | int err; |
792 | ||
793 | err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); | |
794 | if (err) { | |
795 | mlx5_ib_dbg(dev, "copy failed\n"); | |
796 | return err; | |
797 | } | |
798 | ||
799 | context = to_mucontext(pd->uobject->context); | |
1ee47ab3 YH |
800 | if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { |
801 | uar_index = bfregn_to_uar_index(dev, &context->bfregi, | |
802 | ucmd.bfreg_index, true); | |
803 | if (uar_index < 0) | |
804 | return uar_index; | |
805 | ||
806 | bfregn = MLX5_IB_INVALID_BFREG; | |
807 | } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { | |
808 | /* | |
809 | * TBD: should come from the verbs when we have the API | |
810 | */ | |
051f2630 | 811 | /* In CROSS_CHANNEL CQ and QP must use the same UAR */ |
2f5ff264 | 812 | bfregn = MLX5_CROSS_CHANNEL_BFREG; |
1ee47ab3 | 813 | } |
051f2630 | 814 | else { |
ffaf58de LR |
815 | bfregn = alloc_bfreg(dev, &context->bfregi); |
816 | if (bfregn < 0) | |
817 | return bfregn; | |
e126ba97 EC |
818 | } |
819 | ||
2f5ff264 | 820 | mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); |
1ee47ab3 YH |
821 | if (bfregn != MLX5_IB_INVALID_BFREG) |
822 | uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, | |
823 | false); | |
e126ba97 | 824 | |
48fea837 HE |
825 | qp->rq.offset = 0; |
826 | qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); | |
827 | qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; | |
828 | ||
0fb2ed66 | 829 | err = set_user_buf_size(dev, qp, &ucmd, base, attr); |
e126ba97 | 830 | if (err) |
2f5ff264 | 831 | goto err_bfreg; |
e126ba97 | 832 | |
19098df2 | 833 | if (ucmd.buf_addr && ubuffer->buf_size) { |
834 | ubuffer->buf_addr = ucmd.buf_addr; | |
835 | err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, | |
836 | ubuffer->buf_size, | |
837 | &ubuffer->umem, &npages, &page_shift, | |
838 | &ncont, &offset); | |
839 | if (err) | |
2f5ff264 | 840 | goto err_bfreg; |
9e9c47d0 | 841 | } else { |
19098df2 | 842 | ubuffer->umem = NULL; |
e126ba97 | 843 | } |
e126ba97 | 844 | |
09a7d9ec SM |
845 | *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + |
846 | MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; | |
1b9a07ee | 847 | *in = kvzalloc(*inlen, GFP_KERNEL); |
e126ba97 EC |
848 | if (!*in) { |
849 | err = -ENOMEM; | |
850 | goto err_umem; | |
851 | } | |
09a7d9ec SM |
852 | |
853 | pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); | |
19098df2 | 854 | if (ubuffer->umem) |
09a7d9ec SM |
855 | mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); |
856 | ||
857 | qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); | |
858 | ||
859 | MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
860 | MLX5_SET(qpc, qpc, page_offset, offset); | |
e126ba97 | 861 | |
09a7d9ec | 862 | MLX5_SET(qpc, qpc, uar_page, uar_index); |
1ee47ab3 YH |
863 | if (bfregn != MLX5_IB_INVALID_BFREG) |
864 | resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); | |
865 | else | |
866 | resp->bfreg_index = MLX5_IB_INVALID_BFREG; | |
2f5ff264 | 867 | qp->bfregn = bfregn; |
e126ba97 EC |
868 | |
869 | err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); | |
870 | if (err) { | |
871 | mlx5_ib_dbg(dev, "map failed\n"); | |
872 | goto err_free; | |
873 | } | |
874 | ||
41d902cb | 875 | err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); |
e126ba97 EC |
876 | if (err) { |
877 | mlx5_ib_dbg(dev, "copy failed\n"); | |
878 | goto err_unmap; | |
879 | } | |
880 | qp->create_type = MLX5_QP_USER; | |
881 | ||
882 | return 0; | |
883 | ||
884 | err_unmap: | |
885 | mlx5_ib_db_unmap_user(context, &qp->db); | |
886 | ||
887 | err_free: | |
479163f4 | 888 | kvfree(*in); |
e126ba97 EC |
889 | |
890 | err_umem: | |
19098df2 | 891 | if (ubuffer->umem) |
892 | ib_umem_release(ubuffer->umem); | |
e126ba97 | 893 | |
2f5ff264 | 894 | err_bfreg: |
1ee47ab3 YH |
895 | if (bfregn != MLX5_IB_INVALID_BFREG) |
896 | mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); | |
e126ba97 EC |
897 | return err; |
898 | } | |
899 | ||
b037c29a EC |
900 | static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
901 | struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) | |
e126ba97 EC |
902 | { |
903 | struct mlx5_ib_ucontext *context; | |
904 | ||
905 | context = to_mucontext(pd->uobject->context); | |
906 | mlx5_ib_db_unmap_user(context, &qp->db); | |
19098df2 | 907 | if (base->ubuffer.umem) |
908 | ib_umem_release(base->ubuffer.umem); | |
1ee47ab3 YH |
909 | |
910 | /* | |
911 | * Free only the BFREGs which are handled by the kernel. | |
912 | * BFREGs of UARs allocated dynamically are handled by user. | |
913 | */ | |
914 | if (qp->bfregn != MLX5_IB_INVALID_BFREG) | |
915 | mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); | |
e126ba97 EC |
916 | } |
917 | ||
918 | static int create_kernel_qp(struct mlx5_ib_dev *dev, | |
919 | struct ib_qp_init_attr *init_attr, | |
920 | struct mlx5_ib_qp *qp, | |
09a7d9ec | 921 | u32 **in, int *inlen, |
19098df2 | 922 | struct mlx5_ib_qp_base *base) |
e126ba97 | 923 | { |
e126ba97 | 924 | int uar_index; |
09a7d9ec | 925 | void *qpc; |
e126ba97 EC |
926 | int err; |
927 | ||
f0313965 ES |
928 | if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | |
929 | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | | |
b11a4f9c | 930 | IB_QP_CREATE_IPOIB_UD_LSO | |
93d576af | 931 | IB_QP_CREATE_NETIF_QP | |
b11a4f9c | 932 | mlx5_ib_create_qp_sqpn_qp1())) |
1a4c3a3d | 933 | return -EINVAL; |
e126ba97 EC |
934 | |
935 | if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) | |
5fe9dec0 EC |
936 | qp->bf.bfreg = &dev->fp_bfreg; |
937 | else | |
938 | qp->bf.bfreg = &dev->bfreg; | |
e126ba97 | 939 | |
d8030b0d EC |
940 | /* We need to divide by two since each register is comprised of |
941 | * two buffers of identical size, namely odd and even | |
942 | */ | |
943 | qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; | |
5fe9dec0 | 944 | uar_index = qp->bf.bfreg->index; |
e126ba97 EC |
945 | |
946 | err = calc_sq_size(dev, init_attr, qp); | |
947 | if (err < 0) { | |
948 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5fe9dec0 | 949 | return err; |
e126ba97 EC |
950 | } |
951 | ||
952 | qp->rq.offset = 0; | |
953 | qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; | |
19098df2 | 954 | base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); |
e126ba97 | 955 | |
19098df2 | 956 | err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf); |
e126ba97 EC |
957 | if (err) { |
958 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5fe9dec0 | 959 | return err; |
e126ba97 EC |
960 | } |
961 | ||
962 | qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); | |
09a7d9ec SM |
963 | *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + |
964 | MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; | |
1b9a07ee | 965 | *in = kvzalloc(*inlen, GFP_KERNEL); |
e126ba97 EC |
966 | if (!*in) { |
967 | err = -ENOMEM; | |
968 | goto err_buf; | |
969 | } | |
09a7d9ec SM |
970 | |
971 | qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); | |
972 | MLX5_SET(qpc, qpc, uar_page, uar_index); | |
973 | MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
974 | ||
e126ba97 | 975 | /* Set "fast registration enabled" for all kernel QPs */ |
09a7d9ec SM |
976 | MLX5_SET(qpc, qpc, fre, 1); |
977 | MLX5_SET(qpc, qpc, rlky, 1); | |
e126ba97 | 978 | |
b11a4f9c | 979 | if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { |
09a7d9ec | 980 | MLX5_SET(qpc, qpc, deth_sqpn, 1); |
b11a4f9c HE |
981 | qp->flags |= MLX5_IB_QP_SQPN_QP1; |
982 | } | |
983 | ||
09a7d9ec SM |
984 | mlx5_fill_page_array(&qp->buf, |
985 | (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); | |
e126ba97 | 986 | |
9603b61d | 987 | err = mlx5_db_alloc(dev->mdev, &qp->db); |
e126ba97 EC |
988 | if (err) { |
989 | mlx5_ib_dbg(dev, "err %d\n", err); | |
990 | goto err_free; | |
991 | } | |
992 | ||
b5883008 LD |
993 | qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, |
994 | sizeof(*qp->sq.wrid), GFP_KERNEL); | |
995 | qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, | |
996 | sizeof(*qp->sq.wr_data), GFP_KERNEL); | |
997 | qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, | |
998 | sizeof(*qp->rq.wrid), GFP_KERNEL); | |
999 | qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, | |
1000 | sizeof(*qp->sq.w_list), GFP_KERNEL); | |
1001 | qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, | |
1002 | sizeof(*qp->sq.wqe_head), GFP_KERNEL); | |
e126ba97 EC |
1003 | |
1004 | if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || | |
1005 | !qp->sq.w_list || !qp->sq.wqe_head) { | |
1006 | err = -ENOMEM; | |
1007 | goto err_wrid; | |
1008 | } | |
1009 | qp->create_type = MLX5_QP_KERNEL; | |
1010 | ||
1011 | return 0; | |
1012 | ||
1013 | err_wrid: | |
b5883008 LD |
1014 | kvfree(qp->sq.wqe_head); |
1015 | kvfree(qp->sq.w_list); | |
1016 | kvfree(qp->sq.wrid); | |
1017 | kvfree(qp->sq.wr_data); | |
1018 | kvfree(qp->rq.wrid); | |
f4044dac | 1019 | mlx5_db_free(dev->mdev, &qp->db); |
e126ba97 EC |
1020 | |
1021 | err_free: | |
479163f4 | 1022 | kvfree(*in); |
e126ba97 EC |
1023 | |
1024 | err_buf: | |
9603b61d | 1025 | mlx5_buf_free(dev->mdev, &qp->buf); |
e126ba97 EC |
1026 | return err; |
1027 | } | |
1028 | ||
1029 | static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) | |
1030 | { | |
b5883008 LD |
1031 | kvfree(qp->sq.wqe_head); |
1032 | kvfree(qp->sq.w_list); | |
1033 | kvfree(qp->sq.wrid); | |
1034 | kvfree(qp->sq.wr_data); | |
1035 | kvfree(qp->rq.wrid); | |
f4044dac | 1036 | mlx5_db_free(dev->mdev, &qp->db); |
9603b61d | 1037 | mlx5_buf_free(dev->mdev, &qp->buf); |
e126ba97 EC |
1038 | } |
1039 | ||
09a7d9ec | 1040 | static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) |
e126ba97 EC |
1041 | { |
1042 | if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || | |
c32a4f29 | 1043 | (attr->qp_type == MLX5_IB_QPT_DCI) || |
e126ba97 | 1044 | (attr->qp_type == IB_QPT_XRC_INI)) |
09a7d9ec | 1045 | return MLX5_SRQ_RQ; |
e126ba97 | 1046 | else if (!qp->has_rq) |
09a7d9ec | 1047 | return MLX5_ZERO_LEN_RQ; |
e126ba97 | 1048 | else |
09a7d9ec | 1049 | return MLX5_NON_ZERO_RQ; |
e126ba97 EC |
1050 | } |
1051 | ||
1052 | static int is_connected(enum ib_qp_type qp_type) | |
1053 | { | |
1054 | if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) | |
1055 | return 1; | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
0fb2ed66 | 1060 | static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, |
c2e53b2c | 1061 | struct mlx5_ib_qp *qp, |
0fb2ed66 | 1062 | struct mlx5_ib_sq *sq, u32 tdn) |
1063 | { | |
c4f287c4 | 1064 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; |
0fb2ed66 | 1065 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
1066 | ||
0fb2ed66 | 1067 | MLX5_SET(tisc, tisc, transport_domain, tdn); |
c2e53b2c YH |
1068 | if (qp->flags & MLX5_IB_QP_UNDERLAY) |
1069 | MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); | |
1070 | ||
0fb2ed66 | 1071 | return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); |
1072 | } | |
1073 | ||
1074 | static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, | |
1075 | struct mlx5_ib_sq *sq) | |
1076 | { | |
1077 | mlx5_core_destroy_tis(dev->mdev, sq->tisn); | |
1078 | } | |
1079 | ||
b96c9dde MB |
1080 | static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, |
1081 | struct mlx5_ib_sq *sq) | |
1082 | { | |
1083 | if (sq->flow_rule) | |
1084 | mlx5_del_flow_rules(sq->flow_rule); | |
1085 | } | |
1086 | ||
0fb2ed66 | 1087 | static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, |
1088 | struct mlx5_ib_sq *sq, void *qpin, | |
1089 | struct ib_pd *pd) | |
1090 | { | |
1091 | struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; | |
1092 | __be64 *pas; | |
1093 | void *in; | |
1094 | void *sqc; | |
1095 | void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); | |
1096 | void *wq; | |
1097 | int inlen; | |
1098 | int err; | |
1099 | int page_shift = 0; | |
1100 | int npages; | |
1101 | int ncont = 0; | |
1102 | u32 offset = 0; | |
1103 | ||
1104 | err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, | |
1105 | &sq->ubuffer.umem, &npages, &page_shift, | |
1106 | &ncont, &offset); | |
1107 | if (err) | |
1108 | return err; | |
1109 | ||
1110 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; | |
1b9a07ee | 1111 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1112 | if (!in) { |
1113 | err = -ENOMEM; | |
1114 | goto err_umem; | |
1115 | } | |
1116 | ||
1117 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
1118 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); | |
795b609c BW |
1119 | if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) |
1120 | MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); | |
0fb2ed66 | 1121 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
1122 | MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); | |
1123 | MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); | |
1124 | MLX5_SET(sqc, sqc, tis_lst_sz, 1); | |
1125 | MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); | |
96dc3fc5 NO |
1126 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && |
1127 | MLX5_CAP_ETH(dev->mdev, swp)) | |
1128 | MLX5_SET(sqc, sqc, allow_swp, 1); | |
0fb2ed66 | 1129 | |
1130 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1131 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
1132 | MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); | |
1133 | MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); | |
1134 | MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); | |
1135 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); | |
1136 | MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); | |
1137 | MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
1138 | MLX5_SET(wq, wq, page_offset, offset); | |
1139 | ||
1140 | pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); | |
1141 | mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); | |
1142 | ||
1143 | err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); | |
1144 | ||
1145 | kvfree(in); | |
1146 | ||
1147 | if (err) | |
1148 | goto err_umem; | |
1149 | ||
b96c9dde MB |
1150 | err = create_flow_rule_vport_sq(dev, sq); |
1151 | if (err) | |
1152 | goto err_flow; | |
1153 | ||
0fb2ed66 | 1154 | return 0; |
1155 | ||
b96c9dde MB |
1156 | err_flow: |
1157 | mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); | |
1158 | ||
0fb2ed66 | 1159 | err_umem: |
1160 | ib_umem_release(sq->ubuffer.umem); | |
1161 | sq->ubuffer.umem = NULL; | |
1162 | ||
1163 | return err; | |
1164 | } | |
1165 | ||
1166 | static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, | |
1167 | struct mlx5_ib_sq *sq) | |
1168 | { | |
b96c9dde | 1169 | destroy_flow_rule_vport_sq(dev, sq); |
0fb2ed66 | 1170 | mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); |
1171 | ib_umem_release(sq->ubuffer.umem); | |
1172 | } | |
1173 | ||
2c292dbb | 1174 | static size_t get_rq_pas_size(void *qpc) |
0fb2ed66 | 1175 | { |
1176 | u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; | |
1177 | u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); | |
1178 | u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); | |
1179 | u32 page_offset = MLX5_GET(qpc, qpc, page_offset); | |
1180 | u32 po_quanta = 1 << (log_page_size - 6); | |
1181 | u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); | |
1182 | u32 page_size = 1 << log_page_size; | |
1183 | u32 rq_sz_po = rq_sz + (page_offset * po_quanta); | |
1184 | u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; | |
1185 | ||
1186 | return rq_num_pas * sizeof(u64); | |
1187 | } | |
1188 | ||
1189 | static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, | |
2c292dbb BP |
1190 | struct mlx5_ib_rq *rq, void *qpin, |
1191 | size_t qpinlen) | |
0fb2ed66 | 1192 | { |
358e42ea | 1193 | struct mlx5_ib_qp *mqp = rq->base.container_mibqp; |
0fb2ed66 | 1194 | __be64 *pas; |
1195 | __be64 *qp_pas; | |
1196 | void *in; | |
1197 | void *rqc; | |
1198 | void *wq; | |
1199 | void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); | |
2c292dbb BP |
1200 | size_t rq_pas_size = get_rq_pas_size(qpc); |
1201 | size_t inlen; | |
0fb2ed66 | 1202 | int err; |
2c292dbb BP |
1203 | |
1204 | if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) | |
1205 | return -EINVAL; | |
0fb2ed66 | 1206 | |
1207 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; | |
1b9a07ee | 1208 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1209 | if (!in) |
1210 | return -ENOMEM; | |
1211 | ||
1212 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
e4cc4fa7 NO |
1213 | if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) |
1214 | MLX5_SET(rqc, rqc, vsd, 1); | |
0fb2ed66 | 1215 | MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); |
1216 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); | |
1217 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
1218 | MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); | |
1219 | MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); | |
1220 | ||
358e42ea MD |
1221 | if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) |
1222 | MLX5_SET(rqc, rqc, scatter_fcs, 1); | |
1223 | ||
0fb2ed66 | 1224 | wq = MLX5_ADDR_OF(rqc, rqc, wq); |
1225 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
b1383aa6 NO |
1226 | if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) |
1227 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
0fb2ed66 | 1228 | MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); |
1229 | MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); | |
1230 | MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); | |
1231 | MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); | |
1232 | MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); | |
1233 | MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); | |
1234 | ||
1235 | pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); | |
1236 | qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); | |
1237 | memcpy(pas, qp_pas, rq_pas_size); | |
1238 | ||
1239 | err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); | |
1240 | ||
1241 | kvfree(in); | |
1242 | ||
1243 | return err; | |
1244 | } | |
1245 | ||
1246 | static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, | |
1247 | struct mlx5_ib_rq *rq) | |
1248 | { | |
1249 | mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); | |
1250 | } | |
1251 | ||
f95ef6cb MG |
1252 | static bool tunnel_offload_supported(struct mlx5_core_dev *dev) |
1253 | { | |
1254 | return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || | |
1255 | MLX5_CAP_ETH(dev, tunnel_stateless_gre) || | |
1256 | MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); | |
1257 | } | |
1258 | ||
0fb2ed66 | 1259 | static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, |
f95ef6cb | 1260 | struct mlx5_ib_rq *rq, u32 tdn, |
175edba8 | 1261 | u32 *qp_flags_en) |
0fb2ed66 | 1262 | { |
175edba8 | 1263 | u8 lb_flag = 0; |
0fb2ed66 | 1264 | u32 *in; |
1265 | void *tirc; | |
1266 | int inlen; | |
1267 | int err; | |
1268 | ||
1269 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 1270 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1271 | if (!in) |
1272 | return -ENOMEM; | |
1273 | ||
1274 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
1275 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); | |
1276 | MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); | |
1277 | MLX5_SET(tirc, tirc, transport_domain, tdn); | |
175edba8 | 1278 | if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) |
f95ef6cb | 1279 | MLX5_SET(tirc, tirc, tunneled_offload_en, 1); |
0fb2ed66 | 1280 | |
175edba8 MB |
1281 | if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) |
1282 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; | |
1283 | ||
1284 | if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) | |
1285 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; | |
1286 | ||
1287 | if (dev->rep) { | |
1288 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; | |
1289 | *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
1290 | } | |
1291 | ||
1292 | MLX5_SET(tirc, tirc, self_lb_block, lb_flag); | |
ec9c2fb8 | 1293 | |
0fb2ed66 | 1294 | err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); |
1295 | ||
1296 | kvfree(in); | |
1297 | ||
1298 | return err; | |
1299 | } | |
1300 | ||
1301 | static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, | |
1302 | struct mlx5_ib_rq *rq) | |
1303 | { | |
1304 | mlx5_core_destroy_tir(dev->mdev, rq->tirn); | |
1305 | } | |
1306 | ||
1307 | static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
2c292dbb | 1308 | u32 *in, size_t inlen, |
0fb2ed66 | 1309 | struct ib_pd *pd) |
1310 | { | |
1311 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
1312 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1313 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
1314 | struct ib_uobject *uobj = pd->uobject; | |
1315 | struct ib_ucontext *ucontext = uobj->context; | |
1316 | struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); | |
1317 | int err; | |
1318 | u32 tdn = mucontext->tdn; | |
1319 | ||
1320 | if (qp->sq.wqe_cnt) { | |
c2e53b2c | 1321 | err = create_raw_packet_qp_tis(dev, qp, sq, tdn); |
0fb2ed66 | 1322 | if (err) |
1323 | return err; | |
1324 | ||
1325 | err = create_raw_packet_qp_sq(dev, sq, in, pd); | |
1326 | if (err) | |
1327 | goto err_destroy_tis; | |
1328 | ||
1329 | sq->base.container_mibqp = qp; | |
1d31e9c0 | 1330 | sq->base.mqp.event = mlx5_ib_qp_event; |
0fb2ed66 | 1331 | } |
1332 | ||
1333 | if (qp->rq.wqe_cnt) { | |
358e42ea MD |
1334 | rq->base.container_mibqp = qp; |
1335 | ||
e4cc4fa7 NO |
1336 | if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) |
1337 | rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; | |
b1383aa6 NO |
1338 | if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) |
1339 | rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; | |
2c292dbb | 1340 | err = create_raw_packet_qp_rq(dev, rq, in, inlen); |
0fb2ed66 | 1341 | if (err) |
1342 | goto err_destroy_sq; | |
1343 | ||
0fb2ed66 | 1344 | |
175edba8 | 1345 | err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en); |
0fb2ed66 | 1346 | if (err) |
1347 | goto err_destroy_rq; | |
1348 | } | |
1349 | ||
1350 | qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : | |
1351 | rq->base.mqp.qpn; | |
1352 | ||
1353 | return 0; | |
1354 | ||
1355 | err_destroy_rq: | |
1356 | destroy_raw_packet_qp_rq(dev, rq); | |
1357 | err_destroy_sq: | |
1358 | if (!qp->sq.wqe_cnt) | |
1359 | return err; | |
1360 | destroy_raw_packet_qp_sq(dev, sq); | |
1361 | err_destroy_tis: | |
1362 | destroy_raw_packet_qp_tis(dev, sq); | |
1363 | ||
1364 | return err; | |
1365 | } | |
1366 | ||
1367 | static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, | |
1368 | struct mlx5_ib_qp *qp) | |
1369 | { | |
1370 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
1371 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1372 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
1373 | ||
1374 | if (qp->rq.wqe_cnt) { | |
1375 | destroy_raw_packet_qp_tir(dev, rq); | |
1376 | destroy_raw_packet_qp_rq(dev, rq); | |
1377 | } | |
1378 | ||
1379 | if (qp->sq.wqe_cnt) { | |
1380 | destroy_raw_packet_qp_sq(dev, sq); | |
1381 | destroy_raw_packet_qp_tis(dev, sq); | |
1382 | } | |
1383 | } | |
1384 | ||
1385 | static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, | |
1386 | struct mlx5_ib_raw_packet_qp *raw_packet_qp) | |
1387 | { | |
1388 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1389 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
1390 | ||
1391 | sq->sq = &qp->sq; | |
1392 | rq->rq = &qp->rq; | |
1393 | sq->doorbell = &qp->db; | |
1394 | rq->doorbell = &qp->db; | |
1395 | } | |
1396 | ||
28d61370 YH |
1397 | static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) |
1398 | { | |
1399 | mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn); | |
1400 | } | |
1401 | ||
1402 | static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
1403 | struct ib_pd *pd, | |
1404 | struct ib_qp_init_attr *init_attr, | |
1405 | struct ib_udata *udata) | |
1406 | { | |
1407 | struct ib_uobject *uobj = pd->uobject; | |
1408 | struct ib_ucontext *ucontext = uobj->context; | |
1409 | struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); | |
1410 | struct mlx5_ib_create_qp_resp resp = {}; | |
1411 | int inlen; | |
1412 | int err; | |
1413 | u32 *in; | |
1414 | void *tirc; | |
1415 | void *hfso; | |
1416 | u32 selected_fields = 0; | |
2d93fc85 | 1417 | u32 outer_l4; |
28d61370 YH |
1418 | size_t min_resp_len; |
1419 | u32 tdn = mucontext->tdn; | |
1420 | struct mlx5_ib_create_qp_rss ucmd = {}; | |
1421 | size_t required_cmd_sz; | |
175edba8 | 1422 | u8 lb_flag = 0; |
28d61370 YH |
1423 | |
1424 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) | |
1425 | return -EOPNOTSUPP; | |
1426 | ||
1427 | if (init_attr->create_flags || init_attr->send_cq) | |
1428 | return -EINVAL; | |
1429 | ||
2f5ff264 | 1430 | min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); |
28d61370 YH |
1431 | if (udata->outlen < min_resp_len) |
1432 | return -EINVAL; | |
1433 | ||
f95ef6cb | 1434 | required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); |
28d61370 YH |
1435 | if (udata->inlen < required_cmd_sz) { |
1436 | mlx5_ib_dbg(dev, "invalid inlen\n"); | |
1437 | return -EINVAL; | |
1438 | } | |
1439 | ||
1440 | if (udata->inlen > sizeof(ucmd) && | |
1441 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
1442 | udata->inlen - sizeof(ucmd))) { | |
1443 | mlx5_ib_dbg(dev, "inlen is not supported\n"); | |
1444 | return -EOPNOTSUPP; | |
1445 | } | |
1446 | ||
1447 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { | |
1448 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1449 | return -EFAULT; | |
1450 | } | |
1451 | ||
1452 | if (ucmd.comp_mask) { | |
1453 | mlx5_ib_dbg(dev, "invalid comp mask\n"); | |
1454 | return -EOPNOTSUPP; | |
1455 | } | |
1456 | ||
175edba8 MB |
1457 | if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | |
1458 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | | |
1459 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { | |
f95ef6cb MG |
1460 | mlx5_ib_dbg(dev, "invalid flags\n"); |
1461 | return -EOPNOTSUPP; | |
1462 | } | |
1463 | ||
1464 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && | |
1465 | !tunnel_offload_supported(dev->mdev)) { | |
1466 | mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); | |
28d61370 YH |
1467 | return -EOPNOTSUPP; |
1468 | } | |
1469 | ||
309fa347 MG |
1470 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && |
1471 | !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { | |
1472 | mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); | |
1473 | return -EOPNOTSUPP; | |
1474 | } | |
1475 | ||
175edba8 MB |
1476 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) { |
1477 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; | |
1478 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
1479 | } | |
1480 | ||
1481 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { | |
1482 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; | |
1483 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; | |
1484 | } | |
1485 | ||
41d902cb | 1486 | err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); |
28d61370 YH |
1487 | if (err) { |
1488 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1489 | return -EINVAL; | |
1490 | } | |
1491 | ||
1492 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 1493 | in = kvzalloc(inlen, GFP_KERNEL); |
28d61370 YH |
1494 | if (!in) |
1495 | return -ENOMEM; | |
1496 | ||
1497 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
1498 | MLX5_SET(tirc, tirc, disp_type, | |
1499 | MLX5_TIRC_DISP_TYPE_INDIRECT); | |
1500 | MLX5_SET(tirc, tirc, indirect_table, | |
1501 | init_attr->rwq_ind_tbl->ind_tbl_num); | |
1502 | MLX5_SET(tirc, tirc, transport_domain, tdn); | |
1503 | ||
1504 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
f95ef6cb MG |
1505 | |
1506 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) | |
1507 | MLX5_SET(tirc, tirc, tunneled_offload_en, 1); | |
1508 | ||
175edba8 MB |
1509 | MLX5_SET(tirc, tirc, self_lb_block, lb_flag); |
1510 | ||
309fa347 MG |
1511 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) |
1512 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); | |
1513 | else | |
1514 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1515 | ||
28d61370 YH |
1516 | switch (ucmd.rx_hash_function) { |
1517 | case MLX5_RX_HASH_FUNC_TOEPLITZ: | |
1518 | { | |
1519 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); | |
1520 | size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); | |
1521 | ||
1522 | if (len != ucmd.rx_key_len) { | |
1523 | err = -EINVAL; | |
1524 | goto err; | |
1525 | } | |
1526 | ||
1527 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); | |
1528 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
1529 | memcpy(rss_key, ucmd.rx_hash_key, len); | |
1530 | break; | |
1531 | } | |
1532 | default: | |
1533 | err = -EOPNOTSUPP; | |
1534 | goto err; | |
1535 | } | |
1536 | ||
1537 | if (!ucmd.rx_hash_fields_mask) { | |
1538 | /* special case when this TIR serves as steering entry without hashing */ | |
1539 | if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) | |
1540 | goto create_tir; | |
1541 | err = -EINVAL; | |
1542 | goto err; | |
1543 | } | |
1544 | ||
1545 | if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1546 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && | |
1547 | ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || | |
1548 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { | |
1549 | err = -EINVAL; | |
1550 | goto err; | |
1551 | } | |
1552 | ||
1553 | /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ | |
1554 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1555 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) | |
1556 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1557 | MLX5_L3_PROT_TYPE_IPV4); | |
1558 | else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || | |
1559 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) | |
1560 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1561 | MLX5_L3_PROT_TYPE_IPV6); | |
1562 | ||
2d93fc85 MB |
1563 | outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || |
1564 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | | |
1565 | ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || | |
1566 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | | |
1567 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; | |
1568 | ||
1569 | /* Check that only one l4 protocol is set */ | |
1570 | if (outer_l4 & (outer_l4 - 1)) { | |
28d61370 YH |
1571 | err = -EINVAL; |
1572 | goto err; | |
1573 | } | |
1574 | ||
1575 | /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ | |
1576 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || | |
1577 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) | |
1578 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1579 | MLX5_L4_PROT_TYPE_TCP); | |
1580 | else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || | |
1581 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) | |
1582 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1583 | MLX5_L4_PROT_TYPE_UDP); | |
1584 | ||
1585 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1586 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) | |
1587 | selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; | |
1588 | ||
1589 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || | |
1590 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) | |
1591 | selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; | |
1592 | ||
1593 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || | |
1594 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) | |
1595 | selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; | |
1596 | ||
1597 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || | |
1598 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) | |
1599 | selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; | |
1600 | ||
2d93fc85 MB |
1601 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) |
1602 | selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; | |
1603 | ||
28d61370 YH |
1604 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); |
1605 | ||
1606 | create_tir: | |
1607 | err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); | |
1608 | ||
1609 | if (err) | |
1610 | goto err; | |
1611 | ||
1612 | kvfree(in); | |
1613 | /* qpn is reserved for that QP */ | |
1614 | qp->trans_qp.base.mqp.qpn = 0; | |
d9f88e5a | 1615 | qp->flags |= MLX5_IB_QP_RSS; |
28d61370 YH |
1616 | return 0; |
1617 | ||
1618 | err: | |
1619 | kvfree(in); | |
1620 | return err; | |
1621 | } | |
1622 | ||
e126ba97 EC |
1623 | static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
1624 | struct ib_qp_init_attr *init_attr, | |
1625 | struct ib_udata *udata, struct mlx5_ib_qp *qp) | |
1626 | { | |
1627 | struct mlx5_ib_resources *devr = &dev->devr; | |
09a7d9ec | 1628 | int inlen = MLX5_ST_SZ_BYTES(create_qp_in); |
938fe83c | 1629 | struct mlx5_core_dev *mdev = dev->mdev; |
0625b4ba | 1630 | struct mlx5_ib_create_qp_resp resp = {}; |
89ea94a7 MG |
1631 | struct mlx5_ib_cq *send_cq; |
1632 | struct mlx5_ib_cq *recv_cq; | |
1633 | unsigned long flags; | |
cfb5e088 | 1634 | u32 uidx = MLX5_IB_DEFAULT_UIDX; |
09a7d9ec SM |
1635 | struct mlx5_ib_create_qp ucmd; |
1636 | struct mlx5_ib_qp_base *base; | |
e7b169f3 | 1637 | int mlx5_st; |
cfb5e088 | 1638 | void *qpc; |
09a7d9ec SM |
1639 | u32 *in; |
1640 | int err; | |
e126ba97 EC |
1641 | |
1642 | mutex_init(&qp->mutex); | |
1643 | spin_lock_init(&qp->sq.lock); | |
1644 | spin_lock_init(&qp->rq.lock); | |
1645 | ||
e7b169f3 NO |
1646 | mlx5_st = to_mlx5_st(init_attr->qp_type); |
1647 | if (mlx5_st < 0) | |
1648 | return -EINVAL; | |
1649 | ||
28d61370 YH |
1650 | if (init_attr->rwq_ind_tbl) { |
1651 | if (!udata) | |
1652 | return -ENOSYS; | |
1653 | ||
1654 | err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); | |
1655 | return err; | |
1656 | } | |
1657 | ||
f360d88a | 1658 | if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { |
938fe83c | 1659 | if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { |
f360d88a EC |
1660 | mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); |
1661 | return -EINVAL; | |
1662 | } else { | |
1663 | qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; | |
1664 | } | |
1665 | } | |
1666 | ||
051f2630 LR |
1667 | if (init_attr->create_flags & |
1668 | (IB_QP_CREATE_CROSS_CHANNEL | | |
1669 | IB_QP_CREATE_MANAGED_SEND | | |
1670 | IB_QP_CREATE_MANAGED_RECV)) { | |
1671 | if (!MLX5_CAP_GEN(mdev, cd)) { | |
1672 | mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); | |
1673 | return -EINVAL; | |
1674 | } | |
1675 | if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) | |
1676 | qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; | |
1677 | if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) | |
1678 | qp->flags |= MLX5_IB_QP_MANAGED_SEND; | |
1679 | if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) | |
1680 | qp->flags |= MLX5_IB_QP_MANAGED_RECV; | |
1681 | } | |
f0313965 ES |
1682 | |
1683 | if (init_attr->qp_type == IB_QPT_UD && | |
1684 | (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) | |
1685 | if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { | |
1686 | mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); | |
1687 | return -EOPNOTSUPP; | |
1688 | } | |
1689 | ||
358e42ea MD |
1690 | if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { |
1691 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
1692 | mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); | |
1693 | return -EOPNOTSUPP; | |
1694 | } | |
1695 | if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || | |
1696 | !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { | |
1697 | mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); | |
1698 | return -EOPNOTSUPP; | |
1699 | } | |
1700 | qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; | |
1701 | } | |
1702 | ||
e126ba97 EC |
1703 | if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) |
1704 | qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; | |
1705 | ||
e4cc4fa7 NO |
1706 | if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { |
1707 | if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && | |
1708 | MLX5_CAP_ETH(dev->mdev, vlan_cap)) || | |
1709 | (init_attr->qp_type != IB_QPT_RAW_PACKET)) | |
1710 | return -EOPNOTSUPP; | |
1711 | qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; | |
1712 | } | |
1713 | ||
e126ba97 EC |
1714 | if (pd && pd->uobject) { |
1715 | if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { | |
1716 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1717 | return -EFAULT; | |
1718 | } | |
1719 | ||
cfb5e088 HA |
1720 | err = get_qp_user_index(to_mucontext(pd->uobject->context), |
1721 | &ucmd, udata->inlen, &uidx); | |
1722 | if (err) | |
1723 | return err; | |
1724 | ||
e126ba97 EC |
1725 | qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); |
1726 | qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); | |
f95ef6cb MG |
1727 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { |
1728 | if (init_attr->qp_type != IB_QPT_RAW_PACKET || | |
1729 | !tunnel_offload_supported(mdev)) { | |
1730 | mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); | |
1731 | return -EOPNOTSUPP; | |
1732 | } | |
175edba8 MB |
1733 | qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; |
1734 | } | |
1735 | ||
1736 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { | |
1737 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
1738 | mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); | |
1739 | return -EOPNOTSUPP; | |
1740 | } | |
1741 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
1742 | } | |
1743 | ||
1744 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { | |
1745 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
1746 | mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); | |
1747 | return -EOPNOTSUPP; | |
1748 | } | |
1749 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; | |
f95ef6cb | 1750 | } |
c2e53b2c YH |
1751 | |
1752 | if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { | |
1753 | if (init_attr->qp_type != IB_QPT_UD || | |
1754 | (MLX5_CAP_GEN(dev->mdev, port_type) != | |
1755 | MLX5_CAP_PORT_TYPE_IB) || | |
1756 | !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { | |
1757 | mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); | |
1758 | return -EOPNOTSUPP; | |
1759 | } | |
1760 | ||
1761 | qp->flags |= MLX5_IB_QP_UNDERLAY; | |
1762 | qp->underlay_qpn = init_attr->source_qpn; | |
1763 | } | |
e126ba97 EC |
1764 | } else { |
1765 | qp->wq_sig = !!wq_signature; | |
1766 | } | |
1767 | ||
c2e53b2c YH |
1768 | base = (init_attr->qp_type == IB_QPT_RAW_PACKET || |
1769 | qp->flags & MLX5_IB_QP_UNDERLAY) ? | |
1770 | &qp->raw_packet_qp.rq.base : | |
1771 | &qp->trans_qp.base; | |
1772 | ||
e126ba97 EC |
1773 | qp->has_rq = qp_has_rq(init_attr); |
1774 | err = set_rq_size(dev, &init_attr->cap, qp->has_rq, | |
1775 | qp, (pd && pd->uobject) ? &ucmd : NULL); | |
1776 | if (err) { | |
1777 | mlx5_ib_dbg(dev, "err %d\n", err); | |
1778 | return err; | |
1779 | } | |
1780 | ||
1781 | if (pd) { | |
1782 | if (pd->uobject) { | |
938fe83c SM |
1783 | __u32 max_wqes = |
1784 | 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); | |
e126ba97 EC |
1785 | mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); |
1786 | if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || | |
1787 | ucmd.rq_wqe_count != qp->rq.wqe_cnt) { | |
1788 | mlx5_ib_dbg(dev, "invalid rq params\n"); | |
1789 | return -EINVAL; | |
1790 | } | |
938fe83c | 1791 | if (ucmd.sq_wqe_count > max_wqes) { |
e126ba97 | 1792 | mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", |
938fe83c | 1793 | ucmd.sq_wqe_count, max_wqes); |
e126ba97 EC |
1794 | return -EINVAL; |
1795 | } | |
b11a4f9c HE |
1796 | if (init_attr->create_flags & |
1797 | mlx5_ib_create_qp_sqpn_qp1()) { | |
1798 | mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); | |
1799 | return -EINVAL; | |
1800 | } | |
0fb2ed66 | 1801 | err = create_user_qp(dev, pd, qp, udata, init_attr, &in, |
1802 | &resp, &inlen, base); | |
e126ba97 EC |
1803 | if (err) |
1804 | mlx5_ib_dbg(dev, "err %d\n", err); | |
1805 | } else { | |
19098df2 | 1806 | err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, |
1807 | base); | |
e126ba97 EC |
1808 | if (err) |
1809 | mlx5_ib_dbg(dev, "err %d\n", err); | |
e126ba97 EC |
1810 | } |
1811 | ||
1812 | if (err) | |
1813 | return err; | |
1814 | } else { | |
1b9a07ee | 1815 | in = kvzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
1816 | if (!in) |
1817 | return -ENOMEM; | |
1818 | ||
1819 | qp->create_type = MLX5_QP_EMPTY; | |
1820 | } | |
1821 | ||
1822 | if (is_sqp(init_attr->qp_type)) | |
1823 | qp->port = init_attr->port_num; | |
1824 | ||
09a7d9ec SM |
1825 | qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); |
1826 | ||
e7b169f3 | 1827 | MLX5_SET(qpc, qpc, st, mlx5_st); |
09a7d9ec | 1828 | MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); |
e126ba97 EC |
1829 | |
1830 | if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) | |
09a7d9ec | 1831 | MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); |
e126ba97 | 1832 | else |
09a7d9ec SM |
1833 | MLX5_SET(qpc, qpc, latency_sensitive, 1); |
1834 | ||
e126ba97 EC |
1835 | |
1836 | if (qp->wq_sig) | |
09a7d9ec | 1837 | MLX5_SET(qpc, qpc, wq_signature, 1); |
e126ba97 | 1838 | |
f360d88a | 1839 | if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) |
09a7d9ec | 1840 | MLX5_SET(qpc, qpc, block_lb_mc, 1); |
f360d88a | 1841 | |
051f2630 | 1842 | if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) |
09a7d9ec | 1843 | MLX5_SET(qpc, qpc, cd_master, 1); |
051f2630 | 1844 | if (qp->flags & MLX5_IB_QP_MANAGED_SEND) |
09a7d9ec | 1845 | MLX5_SET(qpc, qpc, cd_slave_send, 1); |
051f2630 | 1846 | if (qp->flags & MLX5_IB_QP_MANAGED_RECV) |
09a7d9ec | 1847 | MLX5_SET(qpc, qpc, cd_slave_receive, 1); |
051f2630 | 1848 | |
e126ba97 EC |
1849 | if (qp->scat_cqe && is_connected(init_attr->qp_type)) { |
1850 | int rcqe_sz; | |
1851 | int scqe_sz; | |
1852 | ||
1853 | rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); | |
1854 | scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); | |
1855 | ||
1856 | if (rcqe_sz == 128) | |
09a7d9ec | 1857 | MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); |
e126ba97 | 1858 | else |
09a7d9ec | 1859 | MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); |
e126ba97 EC |
1860 | |
1861 | if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { | |
1862 | if (scqe_sz == 128) | |
09a7d9ec | 1863 | MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); |
e126ba97 | 1864 | else |
09a7d9ec | 1865 | MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); |
e126ba97 EC |
1866 | } |
1867 | } | |
1868 | ||
1869 | if (qp->rq.wqe_cnt) { | |
09a7d9ec SM |
1870 | MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); |
1871 | MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); | |
e126ba97 EC |
1872 | } |
1873 | ||
09a7d9ec | 1874 | MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); |
e126ba97 | 1875 | |
3fd3307e | 1876 | if (qp->sq.wqe_cnt) { |
09a7d9ec | 1877 | MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); |
3fd3307e | 1878 | } else { |
09a7d9ec | 1879 | MLX5_SET(qpc, qpc, no_sq, 1); |
3fd3307e AK |
1880 | if (init_attr->srq && |
1881 | init_attr->srq->srq_type == IB_SRQT_TM) | |
1882 | MLX5_SET(qpc, qpc, offload_type, | |
1883 | MLX5_QPC_OFFLOAD_TYPE_RNDV); | |
1884 | } | |
e126ba97 EC |
1885 | |
1886 | /* Set default resources */ | |
1887 | switch (init_attr->qp_type) { | |
1888 | case IB_QPT_XRC_TGT: | |
09a7d9ec SM |
1889 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); |
1890 | MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); | |
1891 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); | |
1892 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); | |
e126ba97 EC |
1893 | break; |
1894 | case IB_QPT_XRC_INI: | |
09a7d9ec SM |
1895 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); |
1896 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); | |
1897 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); | |
e126ba97 EC |
1898 | break; |
1899 | default: | |
1900 | if (init_attr->srq) { | |
09a7d9ec SM |
1901 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); |
1902 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); | |
e126ba97 | 1903 | } else { |
09a7d9ec SM |
1904 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); |
1905 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); | |
e126ba97 EC |
1906 | } |
1907 | } | |
1908 | ||
1909 | if (init_attr->send_cq) | |
09a7d9ec | 1910 | MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); |
e126ba97 EC |
1911 | |
1912 | if (init_attr->recv_cq) | |
09a7d9ec | 1913 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); |
e126ba97 | 1914 | |
09a7d9ec | 1915 | MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); |
e126ba97 | 1916 | |
09a7d9ec SM |
1917 | /* 0xffffff means we ask to work with cqe version 0 */ |
1918 | if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) | |
cfb5e088 | 1919 | MLX5_SET(qpc, qpc, user_index, uidx); |
09a7d9ec | 1920 | |
f0313965 ES |
1921 | /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ |
1922 | if (init_attr->qp_type == IB_QPT_UD && | |
1923 | (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { | |
f0313965 ES |
1924 | MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); |
1925 | qp->flags |= MLX5_IB_QP_LSO; | |
1926 | } | |
cfb5e088 | 1927 | |
b1383aa6 NO |
1928 | if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { |
1929 | if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { | |
1930 | mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); | |
1931 | err = -EOPNOTSUPP; | |
1932 | goto err; | |
1933 | } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
1934 | MLX5_SET(qpc, qpc, end_padding_mode, | |
1935 | MLX5_WQ_END_PAD_MODE_ALIGN); | |
1936 | } else { | |
1937 | qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; | |
1938 | } | |
1939 | } | |
1940 | ||
2c292dbb BP |
1941 | if (inlen < 0) { |
1942 | err = -EINVAL; | |
1943 | goto err; | |
1944 | } | |
1945 | ||
c2e53b2c YH |
1946 | if (init_attr->qp_type == IB_QPT_RAW_PACKET || |
1947 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 1948 | qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; |
1949 | raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); | |
2c292dbb | 1950 | err = create_raw_packet_qp(dev, qp, in, inlen, pd); |
0fb2ed66 | 1951 | } else { |
1952 | err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); | |
1953 | } | |
1954 | ||
e126ba97 EC |
1955 | if (err) { |
1956 | mlx5_ib_dbg(dev, "create qp failed\n"); | |
1957 | goto err_create; | |
1958 | } | |
1959 | ||
479163f4 | 1960 | kvfree(in); |
e126ba97 | 1961 | |
19098df2 | 1962 | base->container_mibqp = qp; |
1963 | base->mqp.event = mlx5_ib_qp_event; | |
e126ba97 | 1964 | |
89ea94a7 MG |
1965 | get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, |
1966 | &send_cq, &recv_cq); | |
1967 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
1968 | mlx5_ib_lock_cqs(send_cq, recv_cq); | |
1969 | /* Maintain device to QPs access, needed for further handling via reset | |
1970 | * flow | |
1971 | */ | |
1972 | list_add_tail(&qp->qps_list, &dev->qp_list); | |
1973 | /* Maintain CQ to QPs access, needed for further handling via reset flow | |
1974 | */ | |
1975 | if (send_cq) | |
1976 | list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); | |
1977 | if (recv_cq) | |
1978 | list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); | |
1979 | mlx5_ib_unlock_cqs(send_cq, recv_cq); | |
1980 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
1981 | ||
e126ba97 EC |
1982 | return 0; |
1983 | ||
1984 | err_create: | |
1985 | if (qp->create_type == MLX5_QP_USER) | |
b037c29a | 1986 | destroy_qp_user(dev, pd, qp, base); |
e126ba97 EC |
1987 | else if (qp->create_type == MLX5_QP_KERNEL) |
1988 | destroy_qp_kernel(dev, qp); | |
1989 | ||
b1383aa6 | 1990 | err: |
479163f4 | 1991 | kvfree(in); |
e126ba97 EC |
1992 | return err; |
1993 | } | |
1994 | ||
1995 | static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) | |
1996 | __acquires(&send_cq->lock) __acquires(&recv_cq->lock) | |
1997 | { | |
1998 | if (send_cq) { | |
1999 | if (recv_cq) { | |
2000 | if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
89ea94a7 | 2001 | spin_lock(&send_cq->lock); |
e126ba97 EC |
2002 | spin_lock_nested(&recv_cq->lock, |
2003 | SINGLE_DEPTH_NESTING); | |
2004 | } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { | |
89ea94a7 | 2005 | spin_lock(&send_cq->lock); |
e126ba97 EC |
2006 | __acquire(&recv_cq->lock); |
2007 | } else { | |
89ea94a7 | 2008 | spin_lock(&recv_cq->lock); |
e126ba97 EC |
2009 | spin_lock_nested(&send_cq->lock, |
2010 | SINGLE_DEPTH_NESTING); | |
2011 | } | |
2012 | } else { | |
89ea94a7 | 2013 | spin_lock(&send_cq->lock); |
6a4f139a | 2014 | __acquire(&recv_cq->lock); |
e126ba97 EC |
2015 | } |
2016 | } else if (recv_cq) { | |
89ea94a7 | 2017 | spin_lock(&recv_cq->lock); |
6a4f139a EC |
2018 | __acquire(&send_cq->lock); |
2019 | } else { | |
2020 | __acquire(&send_cq->lock); | |
2021 | __acquire(&recv_cq->lock); | |
e126ba97 EC |
2022 | } |
2023 | } | |
2024 | ||
2025 | static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) | |
2026 | __releases(&send_cq->lock) __releases(&recv_cq->lock) | |
2027 | { | |
2028 | if (send_cq) { | |
2029 | if (recv_cq) { | |
2030 | if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
2031 | spin_unlock(&recv_cq->lock); | |
89ea94a7 | 2032 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2033 | } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { |
2034 | __release(&recv_cq->lock); | |
89ea94a7 | 2035 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2036 | } else { |
2037 | spin_unlock(&send_cq->lock); | |
89ea94a7 | 2038 | spin_unlock(&recv_cq->lock); |
e126ba97 EC |
2039 | } |
2040 | } else { | |
6a4f139a | 2041 | __release(&recv_cq->lock); |
89ea94a7 | 2042 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2043 | } |
2044 | } else if (recv_cq) { | |
6a4f139a | 2045 | __release(&send_cq->lock); |
89ea94a7 | 2046 | spin_unlock(&recv_cq->lock); |
6a4f139a EC |
2047 | } else { |
2048 | __release(&recv_cq->lock); | |
2049 | __release(&send_cq->lock); | |
e126ba97 EC |
2050 | } |
2051 | } | |
2052 | ||
2053 | static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) | |
2054 | { | |
2055 | return to_mpd(qp->ibqp.pd); | |
2056 | } | |
2057 | ||
89ea94a7 MG |
2058 | static void get_cqs(enum ib_qp_type qp_type, |
2059 | struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, | |
e126ba97 EC |
2060 | struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) |
2061 | { | |
89ea94a7 | 2062 | switch (qp_type) { |
e126ba97 EC |
2063 | case IB_QPT_XRC_TGT: |
2064 | *send_cq = NULL; | |
2065 | *recv_cq = NULL; | |
2066 | break; | |
2067 | case MLX5_IB_QPT_REG_UMR: | |
2068 | case IB_QPT_XRC_INI: | |
89ea94a7 | 2069 | *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; |
e126ba97 EC |
2070 | *recv_cq = NULL; |
2071 | break; | |
2072 | ||
2073 | case IB_QPT_SMI: | |
d16e91da | 2074 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 EC |
2075 | case IB_QPT_RC: |
2076 | case IB_QPT_UC: | |
2077 | case IB_QPT_UD: | |
2078 | case IB_QPT_RAW_IPV6: | |
2079 | case IB_QPT_RAW_ETHERTYPE: | |
0fb2ed66 | 2080 | case IB_QPT_RAW_PACKET: |
89ea94a7 MG |
2081 | *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; |
2082 | *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; | |
e126ba97 EC |
2083 | break; |
2084 | ||
e126ba97 EC |
2085 | case IB_QPT_MAX: |
2086 | default: | |
2087 | *send_cq = NULL; | |
2088 | *recv_cq = NULL; | |
2089 | break; | |
2090 | } | |
2091 | } | |
2092 | ||
ad5f8e96 | 2093 | static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
13eab21f AH |
2094 | const struct mlx5_modify_raw_qp_param *raw_qp_param, |
2095 | u8 lag_tx_affinity); | |
ad5f8e96 | 2096 | |
e126ba97 EC |
2097 | static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) |
2098 | { | |
2099 | struct mlx5_ib_cq *send_cq, *recv_cq; | |
c2e53b2c | 2100 | struct mlx5_ib_qp_base *base; |
89ea94a7 | 2101 | unsigned long flags; |
e126ba97 EC |
2102 | int err; |
2103 | ||
28d61370 YH |
2104 | if (qp->ibqp.rwq_ind_tbl) { |
2105 | destroy_rss_raw_qp_tir(dev, qp); | |
2106 | return; | |
2107 | } | |
2108 | ||
c2e53b2c YH |
2109 | base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
2110 | qp->flags & MLX5_IB_QP_UNDERLAY) ? | |
0fb2ed66 | 2111 | &qp->raw_packet_qp.rq.base : |
2112 | &qp->trans_qp.base; | |
2113 | ||
6aec21f6 | 2114 | if (qp->state != IB_QPS_RESET) { |
c2e53b2c YH |
2115 | if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && |
2116 | !(qp->flags & MLX5_IB_QP_UNDERLAY)) { | |
ad5f8e96 | 2117 | err = mlx5_core_qp_modify(dev->mdev, |
1a412fb1 SM |
2118 | MLX5_CMD_OP_2RST_QP, 0, |
2119 | NULL, &base->mqp); | |
ad5f8e96 | 2120 | } else { |
0680efa2 AV |
2121 | struct mlx5_modify_raw_qp_param raw_qp_param = { |
2122 | .operation = MLX5_CMD_OP_2RST_QP | |
2123 | }; | |
2124 | ||
13eab21f | 2125 | err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); |
ad5f8e96 | 2126 | } |
2127 | if (err) | |
427c1e7b | 2128 | mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", |
19098df2 | 2129 | base->mqp.qpn); |
6aec21f6 | 2130 | } |
e126ba97 | 2131 | |
89ea94a7 MG |
2132 | get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, |
2133 | &send_cq, &recv_cq); | |
2134 | ||
2135 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
2136 | mlx5_ib_lock_cqs(send_cq, recv_cq); | |
2137 | /* del from lists under both locks above to protect reset flow paths */ | |
2138 | list_del(&qp->qps_list); | |
2139 | if (send_cq) | |
2140 | list_del(&qp->cq_send_list); | |
2141 | ||
2142 | if (recv_cq) | |
2143 | list_del(&qp->cq_recv_list); | |
e126ba97 EC |
2144 | |
2145 | if (qp->create_type == MLX5_QP_KERNEL) { | |
19098df2 | 2146 | __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, |
e126ba97 EC |
2147 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); |
2148 | if (send_cq != recv_cq) | |
19098df2 | 2149 | __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, |
2150 | NULL); | |
e126ba97 | 2151 | } |
89ea94a7 MG |
2152 | mlx5_ib_unlock_cqs(send_cq, recv_cq); |
2153 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
e126ba97 | 2154 | |
c2e53b2c YH |
2155 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
2156 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 2157 | destroy_raw_packet_qp(dev, qp); |
2158 | } else { | |
2159 | err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); | |
2160 | if (err) | |
2161 | mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", | |
2162 | base->mqp.qpn); | |
2163 | } | |
e126ba97 | 2164 | |
e126ba97 EC |
2165 | if (qp->create_type == MLX5_QP_KERNEL) |
2166 | destroy_qp_kernel(dev, qp); | |
2167 | else if (qp->create_type == MLX5_QP_USER) | |
b037c29a | 2168 | destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); |
e126ba97 EC |
2169 | } |
2170 | ||
2171 | static const char *ib_qp_type_str(enum ib_qp_type type) | |
2172 | { | |
2173 | switch (type) { | |
2174 | case IB_QPT_SMI: | |
2175 | return "IB_QPT_SMI"; | |
2176 | case IB_QPT_GSI: | |
2177 | return "IB_QPT_GSI"; | |
2178 | case IB_QPT_RC: | |
2179 | return "IB_QPT_RC"; | |
2180 | case IB_QPT_UC: | |
2181 | return "IB_QPT_UC"; | |
2182 | case IB_QPT_UD: | |
2183 | return "IB_QPT_UD"; | |
2184 | case IB_QPT_RAW_IPV6: | |
2185 | return "IB_QPT_RAW_IPV6"; | |
2186 | case IB_QPT_RAW_ETHERTYPE: | |
2187 | return "IB_QPT_RAW_ETHERTYPE"; | |
2188 | case IB_QPT_XRC_INI: | |
2189 | return "IB_QPT_XRC_INI"; | |
2190 | case IB_QPT_XRC_TGT: | |
2191 | return "IB_QPT_XRC_TGT"; | |
2192 | case IB_QPT_RAW_PACKET: | |
2193 | return "IB_QPT_RAW_PACKET"; | |
2194 | case MLX5_IB_QPT_REG_UMR: | |
2195 | return "MLX5_IB_QPT_REG_UMR"; | |
b4aaa1f0 MS |
2196 | case IB_QPT_DRIVER: |
2197 | return "IB_QPT_DRIVER"; | |
e126ba97 EC |
2198 | case IB_QPT_MAX: |
2199 | default: | |
2200 | return "Invalid QP type"; | |
2201 | } | |
2202 | } | |
2203 | ||
b4aaa1f0 MS |
2204 | static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, |
2205 | struct ib_qp_init_attr *attr, | |
2206 | struct mlx5_ib_create_qp *ucmd) | |
2207 | { | |
b4aaa1f0 MS |
2208 | struct mlx5_ib_qp *qp; |
2209 | int err = 0; | |
2210 | u32 uidx = MLX5_IB_DEFAULT_UIDX; | |
2211 | void *dctc; | |
2212 | ||
2213 | if (!attr->srq || !attr->recv_cq) | |
2214 | return ERR_PTR(-EINVAL); | |
2215 | ||
b4aaa1f0 MS |
2216 | err = get_qp_user_index(to_mucontext(pd->uobject->context), |
2217 | ucmd, sizeof(*ucmd), &uidx); | |
2218 | if (err) | |
2219 | return ERR_PTR(err); | |
2220 | ||
2221 | qp = kzalloc(sizeof(*qp), GFP_KERNEL); | |
2222 | if (!qp) | |
2223 | return ERR_PTR(-ENOMEM); | |
2224 | ||
2225 | qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); | |
2226 | if (!qp->dct.in) { | |
2227 | err = -ENOMEM; | |
2228 | goto err_free; | |
2229 | } | |
2230 | ||
2231 | dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); | |
776a3906 | 2232 | qp->qp_sub_type = MLX5_IB_QPT_DCT; |
b4aaa1f0 MS |
2233 | MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); |
2234 | MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); | |
2235 | MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); | |
2236 | MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); | |
2237 | MLX5_SET(dctc, dctc, user_index, uidx); | |
2238 | ||
2239 | qp->state = IB_QPS_RESET; | |
2240 | ||
2241 | return &qp->ibqp; | |
2242 | err_free: | |
2243 | kfree(qp); | |
2244 | return ERR_PTR(err); | |
2245 | } | |
2246 | ||
2247 | static int set_mlx_qp_type(struct mlx5_ib_dev *dev, | |
2248 | struct ib_qp_init_attr *init_attr, | |
2249 | struct mlx5_ib_create_qp *ucmd, | |
2250 | struct ib_udata *udata) | |
2251 | { | |
2252 | enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; | |
2253 | int err; | |
2254 | ||
2255 | if (!udata) | |
2256 | return -EINVAL; | |
2257 | ||
2258 | if (udata->inlen < sizeof(*ucmd)) { | |
2259 | mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); | |
2260 | return -EINVAL; | |
2261 | } | |
2262 | err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); | |
2263 | if (err) | |
2264 | return err; | |
2265 | ||
2266 | if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { | |
2267 | init_attr->qp_type = MLX5_IB_QPT_DCI; | |
2268 | } else { | |
2269 | if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { | |
2270 | init_attr->qp_type = MLX5_IB_QPT_DCT; | |
2271 | } else { | |
2272 | mlx5_ib_dbg(dev, "Invalid QP flags\n"); | |
2273 | return -EINVAL; | |
2274 | } | |
2275 | } | |
2276 | ||
2277 | if (!MLX5_CAP_GEN(dev->mdev, dct)) { | |
2278 | mlx5_ib_dbg(dev, "DC transport is not supported\n"); | |
2279 | return -EOPNOTSUPP; | |
2280 | } | |
2281 | ||
2282 | return 0; | |
2283 | } | |
2284 | ||
e126ba97 | 2285 | struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, |
b4aaa1f0 | 2286 | struct ib_qp_init_attr *verbs_init_attr, |
e126ba97 EC |
2287 | struct ib_udata *udata) |
2288 | { | |
2289 | struct mlx5_ib_dev *dev; | |
2290 | struct mlx5_ib_qp *qp; | |
2291 | u16 xrcdn = 0; | |
2292 | int err; | |
b4aaa1f0 MS |
2293 | struct ib_qp_init_attr mlx_init_attr; |
2294 | struct ib_qp_init_attr *init_attr = verbs_init_attr; | |
e126ba97 EC |
2295 | |
2296 | if (pd) { | |
2297 | dev = to_mdev(pd->device); | |
0fb2ed66 | 2298 | |
2299 | if (init_attr->qp_type == IB_QPT_RAW_PACKET) { | |
2300 | if (!pd->uobject) { | |
2301 | mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); | |
2302 | return ERR_PTR(-EINVAL); | |
2303 | } else if (!to_mucontext(pd->uobject->context)->cqe_version) { | |
2304 | mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); | |
2305 | return ERR_PTR(-EINVAL); | |
2306 | } | |
2307 | } | |
09f16cf5 MD |
2308 | } else { |
2309 | /* being cautious here */ | |
2310 | if (init_attr->qp_type != IB_QPT_XRC_TGT && | |
2311 | init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { | |
2312 | pr_warn("%s: no PD for transport %s\n", __func__, | |
2313 | ib_qp_type_str(init_attr->qp_type)); | |
2314 | return ERR_PTR(-EINVAL); | |
2315 | } | |
2316 | dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); | |
e126ba97 EC |
2317 | } |
2318 | ||
b4aaa1f0 MS |
2319 | if (init_attr->qp_type == IB_QPT_DRIVER) { |
2320 | struct mlx5_ib_create_qp ucmd; | |
2321 | ||
2322 | init_attr = &mlx_init_attr; | |
2323 | memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); | |
2324 | err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); | |
2325 | if (err) | |
2326 | return ERR_PTR(err); | |
c32a4f29 MS |
2327 | |
2328 | if (init_attr->qp_type == MLX5_IB_QPT_DCI) { | |
2329 | if (init_attr->cap.max_recv_wr || | |
2330 | init_attr->cap.max_recv_sge) { | |
2331 | mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); | |
2332 | return ERR_PTR(-EINVAL); | |
2333 | } | |
776a3906 MS |
2334 | } else { |
2335 | return mlx5_ib_create_dct(pd, init_attr, &ucmd); | |
c32a4f29 | 2336 | } |
b4aaa1f0 MS |
2337 | } |
2338 | ||
e126ba97 EC |
2339 | switch (init_attr->qp_type) { |
2340 | case IB_QPT_XRC_TGT: | |
2341 | case IB_QPT_XRC_INI: | |
938fe83c | 2342 | if (!MLX5_CAP_GEN(dev->mdev, xrc)) { |
e126ba97 EC |
2343 | mlx5_ib_dbg(dev, "XRC not supported\n"); |
2344 | return ERR_PTR(-ENOSYS); | |
2345 | } | |
2346 | init_attr->recv_cq = NULL; | |
2347 | if (init_attr->qp_type == IB_QPT_XRC_TGT) { | |
2348 | xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; | |
2349 | init_attr->send_cq = NULL; | |
2350 | } | |
2351 | ||
2352 | /* fall through */ | |
0fb2ed66 | 2353 | case IB_QPT_RAW_PACKET: |
e126ba97 EC |
2354 | case IB_QPT_RC: |
2355 | case IB_QPT_UC: | |
2356 | case IB_QPT_UD: | |
2357 | case IB_QPT_SMI: | |
d16e91da | 2358 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 | 2359 | case MLX5_IB_QPT_REG_UMR: |
c32a4f29 | 2360 | case MLX5_IB_QPT_DCI: |
e126ba97 EC |
2361 | qp = kzalloc(sizeof(*qp), GFP_KERNEL); |
2362 | if (!qp) | |
2363 | return ERR_PTR(-ENOMEM); | |
2364 | ||
2365 | err = create_qp_common(dev, pd, init_attr, udata, qp); | |
2366 | if (err) { | |
2367 | mlx5_ib_dbg(dev, "create_qp_common failed\n"); | |
2368 | kfree(qp); | |
2369 | return ERR_PTR(err); | |
2370 | } | |
2371 | ||
2372 | if (is_qp0(init_attr->qp_type)) | |
2373 | qp->ibqp.qp_num = 0; | |
2374 | else if (is_qp1(init_attr->qp_type)) | |
2375 | qp->ibqp.qp_num = 1; | |
2376 | else | |
19098df2 | 2377 | qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; |
e126ba97 EC |
2378 | |
2379 | mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", | |
19098df2 | 2380 | qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, |
a1ab8402 EC |
2381 | init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, |
2382 | init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); | |
e126ba97 | 2383 | |
19098df2 | 2384 | qp->trans_qp.xrcdn = xrcdn; |
e126ba97 EC |
2385 | |
2386 | break; | |
2387 | ||
d16e91da HE |
2388 | case IB_QPT_GSI: |
2389 | return mlx5_ib_gsi_create_qp(pd, init_attr); | |
2390 | ||
e126ba97 EC |
2391 | case IB_QPT_RAW_IPV6: |
2392 | case IB_QPT_RAW_ETHERTYPE: | |
e126ba97 EC |
2393 | case IB_QPT_MAX: |
2394 | default: | |
2395 | mlx5_ib_dbg(dev, "unsupported qp type %d\n", | |
2396 | init_attr->qp_type); | |
2397 | /* Don't support raw QPs */ | |
2398 | return ERR_PTR(-EINVAL); | |
2399 | } | |
2400 | ||
b4aaa1f0 MS |
2401 | if (verbs_init_attr->qp_type == IB_QPT_DRIVER) |
2402 | qp->qp_sub_type = init_attr->qp_type; | |
2403 | ||
e126ba97 EC |
2404 | return &qp->ibqp; |
2405 | } | |
2406 | ||
776a3906 MS |
2407 | static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) |
2408 | { | |
2409 | struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); | |
2410 | ||
2411 | if (mqp->state == IB_QPS_RTR) { | |
2412 | int err; | |
2413 | ||
2414 | err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); | |
2415 | if (err) { | |
2416 | mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); | |
2417 | return err; | |
2418 | } | |
2419 | } | |
2420 | ||
2421 | kfree(mqp->dct.in); | |
2422 | kfree(mqp); | |
2423 | return 0; | |
2424 | } | |
2425 | ||
e126ba97 EC |
2426 | int mlx5_ib_destroy_qp(struct ib_qp *qp) |
2427 | { | |
2428 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
2429 | struct mlx5_ib_qp *mqp = to_mqp(qp); | |
2430 | ||
d16e91da HE |
2431 | if (unlikely(qp->qp_type == IB_QPT_GSI)) |
2432 | return mlx5_ib_gsi_destroy_qp(qp); | |
2433 | ||
776a3906 MS |
2434 | if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) |
2435 | return mlx5_ib_destroy_dct(mqp); | |
2436 | ||
e126ba97 EC |
2437 | destroy_qp_common(dev, mqp); |
2438 | ||
2439 | kfree(mqp); | |
2440 | ||
2441 | return 0; | |
2442 | } | |
2443 | ||
2444 | static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr, | |
2445 | int attr_mask) | |
2446 | { | |
2447 | u32 hw_access_flags = 0; | |
2448 | u8 dest_rd_atomic; | |
2449 | u32 access_flags; | |
2450 | ||
2451 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) | |
2452 | dest_rd_atomic = attr->max_dest_rd_atomic; | |
2453 | else | |
19098df2 | 2454 | dest_rd_atomic = qp->trans_qp.resp_depth; |
e126ba97 EC |
2455 | |
2456 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
2457 | access_flags = attr->qp_access_flags; | |
2458 | else | |
19098df2 | 2459 | access_flags = qp->trans_qp.atomic_rd_en; |
e126ba97 EC |
2460 | |
2461 | if (!dest_rd_atomic) | |
2462 | access_flags &= IB_ACCESS_REMOTE_WRITE; | |
2463 | ||
2464 | if (access_flags & IB_ACCESS_REMOTE_READ) | |
2465 | hw_access_flags |= MLX5_QP_BIT_RRE; | |
2466 | if (access_flags & IB_ACCESS_REMOTE_ATOMIC) | |
2467 | hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX); | |
2468 | if (access_flags & IB_ACCESS_REMOTE_WRITE) | |
2469 | hw_access_flags |= MLX5_QP_BIT_RWE; | |
2470 | ||
2471 | return cpu_to_be32(hw_access_flags); | |
2472 | } | |
2473 | ||
2474 | enum { | |
2475 | MLX5_PATH_FLAG_FL = 1 << 0, | |
2476 | MLX5_PATH_FLAG_FREE_AR = 1 << 1, | |
2477 | MLX5_PATH_FLAG_COUNTER = 1 << 2, | |
2478 | }; | |
2479 | ||
2480 | static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) | |
2481 | { | |
4f32ac2e | 2482 | if (rate == IB_RATE_PORT_CURRENT) |
e126ba97 | 2483 | return 0; |
4f32ac2e DG |
2484 | |
2485 | if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) | |
e126ba97 | 2486 | return -EINVAL; |
e126ba97 | 2487 | |
4f32ac2e DG |
2488 | while (rate != IB_RATE_PORT_CURRENT && |
2489 | !(1 << (rate + MLX5_STAT_RATE_OFFSET) & | |
2490 | MLX5_CAP_GEN(dev->mdev, stat_rate_support))) | |
2491 | --rate; | |
2492 | ||
2493 | return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; | |
e126ba97 EC |
2494 | } |
2495 | ||
75850d0b | 2496 | static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, |
2497 | struct mlx5_ib_sq *sq, u8 sl) | |
2498 | { | |
2499 | void *in; | |
2500 | void *tisc; | |
2501 | int inlen; | |
2502 | int err; | |
2503 | ||
2504 | inlen = MLX5_ST_SZ_BYTES(modify_tis_in); | |
1b9a07ee | 2505 | in = kvzalloc(inlen, GFP_KERNEL); |
75850d0b | 2506 | if (!in) |
2507 | return -ENOMEM; | |
2508 | ||
2509 | MLX5_SET(modify_tis_in, in, bitmask.prio, 1); | |
2510 | ||
2511 | tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); | |
2512 | MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); | |
2513 | ||
2514 | err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); | |
2515 | ||
2516 | kvfree(in); | |
2517 | ||
2518 | return err; | |
2519 | } | |
2520 | ||
13eab21f AH |
2521 | static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, |
2522 | struct mlx5_ib_sq *sq, u8 tx_affinity) | |
2523 | { | |
2524 | void *in; | |
2525 | void *tisc; | |
2526 | int inlen; | |
2527 | int err; | |
2528 | ||
2529 | inlen = MLX5_ST_SZ_BYTES(modify_tis_in); | |
1b9a07ee | 2530 | in = kvzalloc(inlen, GFP_KERNEL); |
13eab21f AH |
2531 | if (!in) |
2532 | return -ENOMEM; | |
2533 | ||
2534 | MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); | |
2535 | ||
2536 | tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); | |
2537 | MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); | |
2538 | ||
2539 | err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); | |
2540 | ||
2541 | kvfree(in); | |
2542 | ||
2543 | return err; | |
2544 | } | |
2545 | ||
75850d0b | 2546 | static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
90898850 | 2547 | const struct rdma_ah_attr *ah, |
e126ba97 | 2548 | struct mlx5_qp_path *path, u8 port, int attr_mask, |
f879ee8d AS |
2549 | u32 path_flags, const struct ib_qp_attr *attr, |
2550 | bool alt) | |
e126ba97 | 2551 | { |
d8966fcd | 2552 | const struct ib_global_route *grh = rdma_ah_read_grh(ah); |
e126ba97 | 2553 | int err; |
ed88451e | 2554 | enum ib_gid_type gid_type; |
d8966fcd DC |
2555 | u8 ah_flags = rdma_ah_get_ah_flags(ah); |
2556 | u8 sl = rdma_ah_get_sl(ah); | |
e126ba97 | 2557 | |
e126ba97 | 2558 | if (attr_mask & IB_QP_PKEY_INDEX) |
f879ee8d AS |
2559 | path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : |
2560 | attr->pkey_index); | |
e126ba97 | 2561 | |
d8966fcd DC |
2562 | if (ah_flags & IB_AH_GRH) { |
2563 | if (grh->sgid_index >= | |
938fe83c | 2564 | dev->mdev->port_caps[port - 1].gid_table_len) { |
f4f01b54 | 2565 | pr_err("sgid_index (%u) too large. max is %d\n", |
d8966fcd | 2566 | grh->sgid_index, |
938fe83c | 2567 | dev->mdev->port_caps[port - 1].gid_table_len); |
f83b4263 EC |
2568 | return -EINVAL; |
2569 | } | |
2811ba51 | 2570 | } |
44c58487 DC |
2571 | |
2572 | if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { | |
d8966fcd | 2573 | if (!(ah_flags & IB_AH_GRH)) |
2811ba51 | 2574 | return -EINVAL; |
47ec3866 | 2575 | |
44c58487 | 2576 | memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); |
2b621851 MD |
2577 | if (qp->ibqp.qp_type == IB_QPT_RC || |
2578 | qp->ibqp.qp_type == IB_QPT_UC || | |
2579 | qp->ibqp.qp_type == IB_QPT_XRC_INI || | |
2580 | qp->ibqp.qp_type == IB_QPT_XRC_TGT) | |
47ec3866 PP |
2581 | path->udp_sport = |
2582 | mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); | |
d8966fcd | 2583 | path->dci_cfi_prio_sl = (sl & 0x7) << 4; |
47ec3866 | 2584 | gid_type = ah->grh.sgid_attr->gid_type; |
ed88451e | 2585 | if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) |
d8966fcd | 2586 | path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; |
2811ba51 | 2587 | } else { |
d3ae2bde NO |
2588 | path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; |
2589 | path->fl_free_ar |= | |
2590 | (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; | |
d8966fcd DC |
2591 | path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); |
2592 | path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; | |
2593 | if (ah_flags & IB_AH_GRH) | |
2811ba51 | 2594 | path->grh_mlid |= 1 << 7; |
d8966fcd | 2595 | path->dci_cfi_prio_sl = sl & 0xf; |
2811ba51 AS |
2596 | } |
2597 | ||
d8966fcd DC |
2598 | if (ah_flags & IB_AH_GRH) { |
2599 | path->mgid_index = grh->sgid_index; | |
2600 | path->hop_limit = grh->hop_limit; | |
e126ba97 | 2601 | path->tclass_flowlabel = |
d8966fcd DC |
2602 | cpu_to_be32((grh->traffic_class << 20) | |
2603 | (grh->flow_label)); | |
2604 | memcpy(path->rgid, grh->dgid.raw, 16); | |
e126ba97 EC |
2605 | } |
2606 | ||
d8966fcd | 2607 | err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); |
e126ba97 EC |
2608 | if (err < 0) |
2609 | return err; | |
2610 | path->static_rate = err; | |
2611 | path->port = port; | |
2612 | ||
e126ba97 | 2613 | if (attr_mask & IB_QP_TIMEOUT) |
f879ee8d | 2614 | path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; |
e126ba97 | 2615 | |
75850d0b | 2616 | if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) |
2617 | return modify_raw_packet_eth_prio(dev->mdev, | |
2618 | &qp->raw_packet_qp.sq, | |
d8966fcd | 2619 | sl & 0xf); |
75850d0b | 2620 | |
e126ba97 EC |
2621 | return 0; |
2622 | } | |
2623 | ||
2624 | static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { | |
2625 | [MLX5_QP_STATE_INIT] = { | |
2626 | [MLX5_QP_STATE_INIT] = { | |
2627 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | | |
2628 | MLX5_QP_OPTPAR_RAE | | |
2629 | MLX5_QP_OPTPAR_RWE | | |
2630 | MLX5_QP_OPTPAR_PKEY_INDEX | | |
2631 | MLX5_QP_OPTPAR_PRI_PORT, | |
2632 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | | |
2633 | MLX5_QP_OPTPAR_PKEY_INDEX | | |
2634 | MLX5_QP_OPTPAR_PRI_PORT, | |
2635 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
2636 | MLX5_QP_OPTPAR_Q_KEY | | |
2637 | MLX5_QP_OPTPAR_PRI_PORT, | |
2638 | }, | |
2639 | [MLX5_QP_STATE_RTR] = { | |
2640 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2641 | MLX5_QP_OPTPAR_RRE | | |
2642 | MLX5_QP_OPTPAR_RAE | | |
2643 | MLX5_QP_OPTPAR_RWE | | |
2644 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
2645 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2646 | MLX5_QP_OPTPAR_RWE | | |
2647 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
2648 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
2649 | MLX5_QP_OPTPAR_Q_KEY, | |
2650 | [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
2651 | MLX5_QP_OPTPAR_Q_KEY, | |
a4774e90 EC |
2652 | [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | |
2653 | MLX5_QP_OPTPAR_RRE | | |
2654 | MLX5_QP_OPTPAR_RAE | | |
2655 | MLX5_QP_OPTPAR_RWE | | |
2656 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
e126ba97 EC |
2657 | }, |
2658 | }, | |
2659 | [MLX5_QP_STATE_RTR] = { | |
2660 | [MLX5_QP_STATE_RTS] = { | |
2661 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2662 | MLX5_QP_OPTPAR_RRE | | |
2663 | MLX5_QP_OPTPAR_RAE | | |
2664 | MLX5_QP_OPTPAR_RWE | | |
2665 | MLX5_QP_OPTPAR_PM_STATE | | |
2666 | MLX5_QP_OPTPAR_RNR_TIMEOUT, | |
2667 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2668 | MLX5_QP_OPTPAR_RWE | | |
2669 | MLX5_QP_OPTPAR_PM_STATE, | |
2670 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, | |
2671 | }, | |
2672 | }, | |
2673 | [MLX5_QP_STATE_RTS] = { | |
2674 | [MLX5_QP_STATE_RTS] = { | |
2675 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | | |
2676 | MLX5_QP_OPTPAR_RAE | | |
2677 | MLX5_QP_OPTPAR_RWE | | |
2678 | MLX5_QP_OPTPAR_RNR_TIMEOUT | | |
c2a3431e EC |
2679 | MLX5_QP_OPTPAR_PM_STATE | |
2680 | MLX5_QP_OPTPAR_ALT_ADDR_PATH, | |
e126ba97 | 2681 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | |
c2a3431e EC |
2682 | MLX5_QP_OPTPAR_PM_STATE | |
2683 | MLX5_QP_OPTPAR_ALT_ADDR_PATH, | |
e126ba97 EC |
2684 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | |
2685 | MLX5_QP_OPTPAR_SRQN | | |
2686 | MLX5_QP_OPTPAR_CQN_RCV, | |
2687 | }, | |
2688 | }, | |
2689 | [MLX5_QP_STATE_SQER] = { | |
2690 | [MLX5_QP_STATE_RTS] = { | |
2691 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, | |
2692 | [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, | |
75959f56 | 2693 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, |
a4774e90 EC |
2694 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | |
2695 | MLX5_QP_OPTPAR_RWE | | |
2696 | MLX5_QP_OPTPAR_RAE | | |
2697 | MLX5_QP_OPTPAR_RRE, | |
e126ba97 EC |
2698 | }, |
2699 | }, | |
2700 | }; | |
2701 | ||
2702 | static int ib_nr_to_mlx5_nr(int ib_mask) | |
2703 | { | |
2704 | switch (ib_mask) { | |
2705 | case IB_QP_STATE: | |
2706 | return 0; | |
2707 | case IB_QP_CUR_STATE: | |
2708 | return 0; | |
2709 | case IB_QP_EN_SQD_ASYNC_NOTIFY: | |
2710 | return 0; | |
2711 | case IB_QP_ACCESS_FLAGS: | |
2712 | return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | | |
2713 | MLX5_QP_OPTPAR_RAE; | |
2714 | case IB_QP_PKEY_INDEX: | |
2715 | return MLX5_QP_OPTPAR_PKEY_INDEX; | |
2716 | case IB_QP_PORT: | |
2717 | return MLX5_QP_OPTPAR_PRI_PORT; | |
2718 | case IB_QP_QKEY: | |
2719 | return MLX5_QP_OPTPAR_Q_KEY; | |
2720 | case IB_QP_AV: | |
2721 | return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | | |
2722 | MLX5_QP_OPTPAR_PRI_PORT; | |
2723 | case IB_QP_PATH_MTU: | |
2724 | return 0; | |
2725 | case IB_QP_TIMEOUT: | |
2726 | return MLX5_QP_OPTPAR_ACK_TIMEOUT; | |
2727 | case IB_QP_RETRY_CNT: | |
2728 | return MLX5_QP_OPTPAR_RETRY_COUNT; | |
2729 | case IB_QP_RNR_RETRY: | |
2730 | return MLX5_QP_OPTPAR_RNR_RETRY; | |
2731 | case IB_QP_RQ_PSN: | |
2732 | return 0; | |
2733 | case IB_QP_MAX_QP_RD_ATOMIC: | |
2734 | return MLX5_QP_OPTPAR_SRA_MAX; | |
2735 | case IB_QP_ALT_PATH: | |
2736 | return MLX5_QP_OPTPAR_ALT_ADDR_PATH; | |
2737 | case IB_QP_MIN_RNR_TIMER: | |
2738 | return MLX5_QP_OPTPAR_RNR_TIMEOUT; | |
2739 | case IB_QP_SQ_PSN: | |
2740 | return 0; | |
2741 | case IB_QP_MAX_DEST_RD_ATOMIC: | |
2742 | return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | | |
2743 | MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; | |
2744 | case IB_QP_PATH_MIG_STATE: | |
2745 | return MLX5_QP_OPTPAR_PM_STATE; | |
2746 | case IB_QP_CAP: | |
2747 | return 0; | |
2748 | case IB_QP_DEST_QPN: | |
2749 | return 0; | |
2750 | } | |
2751 | return 0; | |
2752 | } | |
2753 | ||
2754 | static int ib_mask_to_mlx5_opt(int ib_mask) | |
2755 | { | |
2756 | int result = 0; | |
2757 | int i; | |
2758 | ||
2759 | for (i = 0; i < 8 * sizeof(int); i++) { | |
2760 | if ((1 << i) & ib_mask) | |
2761 | result |= ib_nr_to_mlx5_nr(1 << i); | |
2762 | } | |
2763 | ||
2764 | return result; | |
2765 | } | |
2766 | ||
eb49ab0c AV |
2767 | static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev, |
2768 | struct mlx5_ib_rq *rq, int new_state, | |
2769 | const struct mlx5_modify_raw_qp_param *raw_qp_param) | |
ad5f8e96 | 2770 | { |
2771 | void *in; | |
2772 | void *rqc; | |
2773 | int inlen; | |
2774 | int err; | |
2775 | ||
2776 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 2777 | in = kvzalloc(inlen, GFP_KERNEL); |
ad5f8e96 | 2778 | if (!in) |
2779 | return -ENOMEM; | |
2780 | ||
2781 | MLX5_SET(modify_rq_in, in, rq_state, rq->state); | |
2782 | ||
2783 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
2784 | MLX5_SET(rqc, rqc, state, new_state); | |
2785 | ||
eb49ab0c AV |
2786 | if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { |
2787 | if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { | |
2788 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
23a6964e | 2789 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); |
eb49ab0c AV |
2790 | MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); |
2791 | } else | |
2792 | pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", | |
2793 | dev->ib_dev.name); | |
2794 | } | |
2795 | ||
2796 | err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); | |
ad5f8e96 | 2797 | if (err) |
2798 | goto out; | |
2799 | ||
2800 | rq->state = new_state; | |
2801 | ||
2802 | out: | |
2803 | kvfree(in); | |
2804 | return err; | |
2805 | } | |
2806 | ||
2807 | static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, | |
7d29f349 BW |
2808 | struct mlx5_ib_sq *sq, |
2809 | int new_state, | |
2810 | const struct mlx5_modify_raw_qp_param *raw_qp_param) | |
ad5f8e96 | 2811 | { |
7d29f349 | 2812 | struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; |
61147f39 BW |
2813 | struct mlx5_rate_limit old_rl = ibqp->rl; |
2814 | struct mlx5_rate_limit new_rl = old_rl; | |
2815 | bool new_rate_added = false; | |
7d29f349 | 2816 | u16 rl_index = 0; |
ad5f8e96 | 2817 | void *in; |
2818 | void *sqc; | |
2819 | int inlen; | |
2820 | int err; | |
2821 | ||
2822 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 2823 | in = kvzalloc(inlen, GFP_KERNEL); |
ad5f8e96 | 2824 | if (!in) |
2825 | return -ENOMEM; | |
2826 | ||
2827 | MLX5_SET(modify_sq_in, in, sq_state, sq->state); | |
2828 | ||
2829 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
2830 | MLX5_SET(sqc, sqc, state, new_state); | |
2831 | ||
7d29f349 BW |
2832 | if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { |
2833 | if (new_state != MLX5_SQC_STATE_RDY) | |
2834 | pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", | |
2835 | __func__); | |
2836 | else | |
61147f39 | 2837 | new_rl = raw_qp_param->rl; |
7d29f349 BW |
2838 | } |
2839 | ||
61147f39 BW |
2840 | if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { |
2841 | if (new_rl.rate) { | |
2842 | err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); | |
7d29f349 | 2843 | if (err) { |
61147f39 BW |
2844 | pr_err("Failed configuring rate limit(err %d): \ |
2845 | rate %u, max_burst_sz %u, typical_pkt_sz %u\n", | |
2846 | err, new_rl.rate, new_rl.max_burst_sz, | |
2847 | new_rl.typical_pkt_sz); | |
2848 | ||
7d29f349 BW |
2849 | goto out; |
2850 | } | |
61147f39 | 2851 | new_rate_added = true; |
7d29f349 BW |
2852 | } |
2853 | ||
2854 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); | |
61147f39 | 2855 | /* index 0 means no limit */ |
7d29f349 BW |
2856 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); |
2857 | } | |
2858 | ||
ad5f8e96 | 2859 | err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); |
7d29f349 BW |
2860 | if (err) { |
2861 | /* Remove new rate from table if failed */ | |
61147f39 BW |
2862 | if (new_rate_added) |
2863 | mlx5_rl_remove_rate(dev, &new_rl); | |
ad5f8e96 | 2864 | goto out; |
7d29f349 BW |
2865 | } |
2866 | ||
2867 | /* Only remove the old rate after new rate was set */ | |
61147f39 BW |
2868 | if ((old_rl.rate && |
2869 | !mlx5_rl_are_equal(&old_rl, &new_rl)) || | |
7d29f349 | 2870 | (new_state != MLX5_SQC_STATE_RDY)) |
61147f39 | 2871 | mlx5_rl_remove_rate(dev, &old_rl); |
ad5f8e96 | 2872 | |
61147f39 | 2873 | ibqp->rl = new_rl; |
ad5f8e96 | 2874 | sq->state = new_state; |
2875 | ||
2876 | out: | |
2877 | kvfree(in); | |
2878 | return err; | |
2879 | } | |
2880 | ||
2881 | static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
13eab21f AH |
2882 | const struct mlx5_modify_raw_qp_param *raw_qp_param, |
2883 | u8 tx_affinity) | |
ad5f8e96 | 2884 | { |
2885 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
2886 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
2887 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
7d29f349 BW |
2888 | int modify_rq = !!qp->rq.wqe_cnt; |
2889 | int modify_sq = !!qp->sq.wqe_cnt; | |
ad5f8e96 | 2890 | int rq_state; |
2891 | int sq_state; | |
2892 | int err; | |
2893 | ||
0680efa2 | 2894 | switch (raw_qp_param->operation) { |
ad5f8e96 | 2895 | case MLX5_CMD_OP_RST2INIT_QP: |
2896 | rq_state = MLX5_RQC_STATE_RDY; | |
2897 | sq_state = MLX5_SQC_STATE_RDY; | |
2898 | break; | |
2899 | case MLX5_CMD_OP_2ERR_QP: | |
2900 | rq_state = MLX5_RQC_STATE_ERR; | |
2901 | sq_state = MLX5_SQC_STATE_ERR; | |
2902 | break; | |
2903 | case MLX5_CMD_OP_2RST_QP: | |
2904 | rq_state = MLX5_RQC_STATE_RST; | |
2905 | sq_state = MLX5_SQC_STATE_RST; | |
2906 | break; | |
ad5f8e96 | 2907 | case MLX5_CMD_OP_RTR2RTS_QP: |
2908 | case MLX5_CMD_OP_RTS2RTS_QP: | |
7d29f349 BW |
2909 | if (raw_qp_param->set_mask == |
2910 | MLX5_RAW_QP_RATE_LIMIT) { | |
2911 | modify_rq = 0; | |
2912 | sq_state = sq->state; | |
2913 | } else { | |
2914 | return raw_qp_param->set_mask ? -EINVAL : 0; | |
2915 | } | |
2916 | break; | |
2917 | case MLX5_CMD_OP_INIT2INIT_QP: | |
2918 | case MLX5_CMD_OP_INIT2RTR_QP: | |
eb49ab0c AV |
2919 | if (raw_qp_param->set_mask) |
2920 | return -EINVAL; | |
2921 | else | |
2922 | return 0; | |
ad5f8e96 | 2923 | default: |
2924 | WARN_ON(1); | |
2925 | return -EINVAL; | |
2926 | } | |
2927 | ||
7d29f349 BW |
2928 | if (modify_rq) { |
2929 | err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); | |
ad5f8e96 | 2930 | if (err) |
2931 | return err; | |
2932 | } | |
2933 | ||
7d29f349 | 2934 | if (modify_sq) { |
13eab21f AH |
2935 | if (tx_affinity) { |
2936 | err = modify_raw_packet_tx_affinity(dev->mdev, sq, | |
2937 | tx_affinity); | |
2938 | if (err) | |
2939 | return err; | |
2940 | } | |
2941 | ||
7d29f349 | 2942 | return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param); |
13eab21f | 2943 | } |
ad5f8e96 | 2944 | |
2945 | return 0; | |
2946 | } | |
2947 | ||
e126ba97 EC |
2948 | static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, |
2949 | const struct ib_qp_attr *attr, int attr_mask, | |
61147f39 BW |
2950 | enum ib_qp_state cur_state, enum ib_qp_state new_state, |
2951 | const struct mlx5_ib_modify_qp *ucmd) | |
e126ba97 | 2952 | { |
427c1e7b | 2953 | static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { |
2954 | [MLX5_QP_STATE_RST] = { | |
2955 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
2956 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
2957 | [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, | |
2958 | }, | |
2959 | [MLX5_QP_STATE_INIT] = { | |
2960 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
2961 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
2962 | [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, | |
2963 | [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, | |
2964 | }, | |
2965 | [MLX5_QP_STATE_RTR] = { | |
2966 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
2967 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
2968 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, | |
2969 | }, | |
2970 | [MLX5_QP_STATE_RTS] = { | |
2971 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
2972 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
2973 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, | |
2974 | }, | |
2975 | [MLX5_QP_STATE_SQD] = { | |
2976 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
2977 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
2978 | }, | |
2979 | [MLX5_QP_STATE_SQER] = { | |
2980 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
2981 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
2982 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, | |
2983 | }, | |
2984 | [MLX5_QP_STATE_ERR] = { | |
2985 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
2986 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
2987 | } | |
2988 | }; | |
2989 | ||
e126ba97 EC |
2990 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); |
2991 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
19098df2 | 2992 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; |
e126ba97 EC |
2993 | struct mlx5_ib_cq *send_cq, *recv_cq; |
2994 | struct mlx5_qp_context *context; | |
e126ba97 | 2995 | struct mlx5_ib_pd *pd; |
eb49ab0c | 2996 | struct mlx5_ib_port *mibport = NULL; |
e126ba97 EC |
2997 | enum mlx5_qp_state mlx5_cur, mlx5_new; |
2998 | enum mlx5_qp_optpar optpar; | |
e126ba97 EC |
2999 | int mlx5_st; |
3000 | int err; | |
427c1e7b | 3001 | u16 op; |
13eab21f | 3002 | u8 tx_affinity = 0; |
e126ba97 | 3003 | |
55de9a77 LR |
3004 | mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? |
3005 | qp->qp_sub_type : ibqp->qp_type); | |
3006 | if (mlx5_st < 0) | |
3007 | return -EINVAL; | |
3008 | ||
1a412fb1 SM |
3009 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
3010 | if (!context) | |
e126ba97 EC |
3011 | return -ENOMEM; |
3012 | ||
55de9a77 | 3013 | context->flags = cpu_to_be32(mlx5_st << 16); |
e126ba97 EC |
3014 | |
3015 | if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { | |
3016 | context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); | |
3017 | } else { | |
3018 | switch (attr->path_mig_state) { | |
3019 | case IB_MIG_MIGRATED: | |
3020 | context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); | |
3021 | break; | |
3022 | case IB_MIG_REARM: | |
3023 | context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); | |
3024 | break; | |
3025 | case IB_MIG_ARMED: | |
3026 | context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); | |
3027 | break; | |
3028 | } | |
3029 | } | |
3030 | ||
13eab21f AH |
3031 | if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { |
3032 | if ((ibqp->qp_type == IB_QPT_RC) || | |
3033 | (ibqp->qp_type == IB_QPT_UD && | |
3034 | !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || | |
3035 | (ibqp->qp_type == IB_QPT_UC) || | |
3036 | (ibqp->qp_type == IB_QPT_RAW_PACKET) || | |
3037 | (ibqp->qp_type == IB_QPT_XRC_INI) || | |
3038 | (ibqp->qp_type == IB_QPT_XRC_TGT)) { | |
3039 | if (mlx5_lag_is_active(dev->mdev)) { | |
7fd8aefb | 3040 | u8 p = mlx5_core_native_port_num(dev->mdev); |
13eab21f | 3041 | tx_affinity = (unsigned int)atomic_add_return(1, |
7fd8aefb | 3042 | &dev->roce[p].next_port) % |
13eab21f AH |
3043 | MLX5_MAX_PORTS + 1; |
3044 | context->flags |= cpu_to_be32(tx_affinity << 24); | |
3045 | } | |
3046 | } | |
3047 | } | |
3048 | ||
d16e91da | 3049 | if (is_sqp(ibqp->qp_type)) { |
e126ba97 | 3050 | context->mtu_msgmax = (IB_MTU_256 << 5) | 8; |
c2e53b2c YH |
3051 | } else if ((ibqp->qp_type == IB_QPT_UD && |
3052 | !(qp->flags & MLX5_IB_QP_UNDERLAY)) || | |
e126ba97 EC |
3053 | ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { |
3054 | context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; | |
3055 | } else if (attr_mask & IB_QP_PATH_MTU) { | |
3056 | if (attr->path_mtu < IB_MTU_256 || | |
3057 | attr->path_mtu > IB_MTU_4096) { | |
3058 | mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); | |
3059 | err = -EINVAL; | |
3060 | goto out; | |
3061 | } | |
938fe83c SM |
3062 | context->mtu_msgmax = (attr->path_mtu << 5) | |
3063 | (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); | |
e126ba97 EC |
3064 | } |
3065 | ||
3066 | if (attr_mask & IB_QP_DEST_QPN) | |
3067 | context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); | |
3068 | ||
3069 | if (attr_mask & IB_QP_PKEY_INDEX) | |
d3ae2bde | 3070 | context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); |
e126ba97 EC |
3071 | |
3072 | /* todo implement counter_index functionality */ | |
3073 | ||
3074 | if (is_sqp(ibqp->qp_type)) | |
3075 | context->pri_path.port = qp->port; | |
3076 | ||
3077 | if (attr_mask & IB_QP_PORT) | |
3078 | context->pri_path.port = attr->port_num; | |
3079 | ||
3080 | if (attr_mask & IB_QP_AV) { | |
75850d0b | 3081 | err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, |
e126ba97 | 3082 | attr_mask & IB_QP_PORT ? attr->port_num : qp->port, |
f879ee8d | 3083 | attr_mask, 0, attr, false); |
e126ba97 EC |
3084 | if (err) |
3085 | goto out; | |
3086 | } | |
3087 | ||
3088 | if (attr_mask & IB_QP_TIMEOUT) | |
3089 | context->pri_path.ackto_lt |= attr->timeout << 3; | |
3090 | ||
3091 | if (attr_mask & IB_QP_ALT_PATH) { | |
75850d0b | 3092 | err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, |
3093 | &context->alt_path, | |
f879ee8d AS |
3094 | attr->alt_port_num, |
3095 | attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, | |
3096 | 0, attr, true); | |
e126ba97 EC |
3097 | if (err) |
3098 | goto out; | |
3099 | } | |
3100 | ||
3101 | pd = get_pd(qp); | |
89ea94a7 MG |
3102 | get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, |
3103 | &send_cq, &recv_cq); | |
e126ba97 EC |
3104 | |
3105 | context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); | |
3106 | context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; | |
3107 | context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; | |
3108 | context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); | |
3109 | ||
3110 | if (attr_mask & IB_QP_RNR_RETRY) | |
3111 | context->params1 |= cpu_to_be32(attr->rnr_retry << 13); | |
3112 | ||
3113 | if (attr_mask & IB_QP_RETRY_CNT) | |
3114 | context->params1 |= cpu_to_be32(attr->retry_cnt << 16); | |
3115 | ||
3116 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { | |
3117 | if (attr->max_rd_atomic) | |
3118 | context->params1 |= | |
3119 | cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); | |
3120 | } | |
3121 | ||
3122 | if (attr_mask & IB_QP_SQ_PSN) | |
3123 | context->next_send_psn = cpu_to_be32(attr->sq_psn); | |
3124 | ||
3125 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { | |
3126 | if (attr->max_dest_rd_atomic) | |
3127 | context->params2 |= | |
3128 | cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); | |
3129 | } | |
3130 | ||
3131 | if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) | |
3132 | context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask); | |
3133 | ||
3134 | if (attr_mask & IB_QP_MIN_RNR_TIMER) | |
3135 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); | |
3136 | ||
3137 | if (attr_mask & IB_QP_RQ_PSN) | |
3138 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); | |
3139 | ||
3140 | if (attr_mask & IB_QP_QKEY) | |
3141 | context->qkey = cpu_to_be32(attr->qkey); | |
3142 | ||
3143 | if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) | |
3144 | context->db_rec_addr = cpu_to_be64(qp->db.dma); | |
3145 | ||
0837e86a MB |
3146 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { |
3147 | u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : | |
3148 | qp->port) - 1; | |
c2e53b2c YH |
3149 | |
3150 | /* Underlay port should be used - index 0 function per port */ | |
3151 | if (qp->flags & MLX5_IB_QP_UNDERLAY) | |
3152 | port_num = 0; | |
3153 | ||
eb49ab0c | 3154 | mibport = &dev->port[port_num]; |
0837e86a | 3155 | context->qp_counter_set_usr_page |= |
e1f24a79 | 3156 | cpu_to_be32((u32)(mibport->cnts.set_id) << 24); |
0837e86a MB |
3157 | } |
3158 | ||
e126ba97 EC |
3159 | if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) |
3160 | context->sq_crq_size |= cpu_to_be16(1 << 4); | |
3161 | ||
b11a4f9c HE |
3162 | if (qp->flags & MLX5_IB_QP_SQPN_QP1) |
3163 | context->deth_sqpn = cpu_to_be32(1); | |
e126ba97 EC |
3164 | |
3165 | mlx5_cur = to_mlx5_state(cur_state); | |
3166 | mlx5_new = to_mlx5_state(new_state); | |
e126ba97 | 3167 | |
427c1e7b | 3168 | if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || |
5d414b17 DC |
3169 | !optab[mlx5_cur][mlx5_new]) { |
3170 | err = -EINVAL; | |
427c1e7b | 3171 | goto out; |
5d414b17 | 3172 | } |
427c1e7b | 3173 | |
3174 | op = optab[mlx5_cur][mlx5_new]; | |
e126ba97 EC |
3175 | optpar = ib_mask_to_mlx5_opt(attr_mask); |
3176 | optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; | |
ad5f8e96 | 3177 | |
c2e53b2c YH |
3178 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
3179 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0680efa2 AV |
3180 | struct mlx5_modify_raw_qp_param raw_qp_param = {}; |
3181 | ||
3182 | raw_qp_param.operation = op; | |
eb49ab0c | 3183 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { |
e1f24a79 | 3184 | raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; |
eb49ab0c AV |
3185 | raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; |
3186 | } | |
7d29f349 BW |
3187 | |
3188 | if (attr_mask & IB_QP_RATE_LIMIT) { | |
61147f39 BW |
3189 | raw_qp_param.rl.rate = attr->rate_limit; |
3190 | ||
3191 | if (ucmd->burst_info.max_burst_sz) { | |
3192 | if (attr->rate_limit && | |
3193 | MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { | |
3194 | raw_qp_param.rl.max_burst_sz = | |
3195 | ucmd->burst_info.max_burst_sz; | |
3196 | } else { | |
3197 | err = -EINVAL; | |
3198 | goto out; | |
3199 | } | |
3200 | } | |
3201 | ||
3202 | if (ucmd->burst_info.typical_pkt_sz) { | |
3203 | if (attr->rate_limit && | |
3204 | MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { | |
3205 | raw_qp_param.rl.typical_pkt_sz = | |
3206 | ucmd->burst_info.typical_pkt_sz; | |
3207 | } else { | |
3208 | err = -EINVAL; | |
3209 | goto out; | |
3210 | } | |
3211 | } | |
3212 | ||
7d29f349 BW |
3213 | raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; |
3214 | } | |
3215 | ||
13eab21f | 3216 | err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); |
0680efa2 | 3217 | } else { |
1a412fb1 | 3218 | err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, |
ad5f8e96 | 3219 | &base->mqp); |
0680efa2 AV |
3220 | } |
3221 | ||
e126ba97 EC |
3222 | if (err) |
3223 | goto out; | |
3224 | ||
3225 | qp->state = new_state; | |
3226 | ||
3227 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
19098df2 | 3228 | qp->trans_qp.atomic_rd_en = attr->qp_access_flags; |
e126ba97 | 3229 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) |
19098df2 | 3230 | qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; |
e126ba97 EC |
3231 | if (attr_mask & IB_QP_PORT) |
3232 | qp->port = attr->port_num; | |
3233 | if (attr_mask & IB_QP_ALT_PATH) | |
19098df2 | 3234 | qp->trans_qp.alt_port = attr->alt_port_num; |
e126ba97 EC |
3235 | |
3236 | /* | |
3237 | * If we moved a kernel QP to RESET, clean up all old CQ | |
3238 | * entries and reinitialize the QP. | |
3239 | */ | |
75a45982 LR |
3240 | if (new_state == IB_QPS_RESET && |
3241 | !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { | |
19098df2 | 3242 | mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, |
e126ba97 EC |
3243 | ibqp->srq ? to_msrq(ibqp->srq) : NULL); |
3244 | if (send_cq != recv_cq) | |
19098df2 | 3245 | mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); |
e126ba97 EC |
3246 | |
3247 | qp->rq.head = 0; | |
3248 | qp->rq.tail = 0; | |
3249 | qp->sq.head = 0; | |
3250 | qp->sq.tail = 0; | |
3251 | qp->sq.cur_post = 0; | |
3252 | qp->sq.last_poll = 0; | |
3253 | qp->db.db[MLX5_RCV_DBR] = 0; | |
3254 | qp->db.db[MLX5_SND_DBR] = 0; | |
3255 | } | |
3256 | ||
3257 | out: | |
1a412fb1 | 3258 | kfree(context); |
e126ba97 EC |
3259 | return err; |
3260 | } | |
3261 | ||
c32a4f29 MS |
3262 | static inline bool is_valid_mask(int mask, int req, int opt) |
3263 | { | |
3264 | if ((mask & req) != req) | |
3265 | return false; | |
3266 | ||
3267 | if (mask & ~(req | opt)) | |
3268 | return false; | |
3269 | ||
3270 | return true; | |
3271 | } | |
3272 | ||
3273 | /* check valid transition for driver QP types | |
3274 | * for now the only QP type that this function supports is DCI | |
3275 | */ | |
3276 | static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, | |
3277 | enum ib_qp_attr_mask attr_mask) | |
3278 | { | |
3279 | int req = IB_QP_STATE; | |
3280 | int opt = 0; | |
3281 | ||
3282 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { | |
3283 | req |= IB_QP_PKEY_INDEX | IB_QP_PORT; | |
3284 | return is_valid_mask(attr_mask, req, opt); | |
3285 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { | |
3286 | opt = IB_QP_PKEY_INDEX | IB_QP_PORT; | |
3287 | return is_valid_mask(attr_mask, req, opt); | |
3288 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { | |
3289 | req |= IB_QP_PATH_MTU; | |
3290 | opt = IB_QP_PKEY_INDEX; | |
3291 | return is_valid_mask(attr_mask, req, opt); | |
3292 | } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { | |
3293 | req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | | |
3294 | IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; | |
3295 | opt = IB_QP_MIN_RNR_TIMER; | |
3296 | return is_valid_mask(attr_mask, req, opt); | |
3297 | } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { | |
3298 | opt = IB_QP_MIN_RNR_TIMER; | |
3299 | return is_valid_mask(attr_mask, req, opt); | |
3300 | } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { | |
3301 | return is_valid_mask(attr_mask, req, opt); | |
3302 | } | |
3303 | return false; | |
3304 | } | |
3305 | ||
776a3906 MS |
3306 | /* mlx5_ib_modify_dct: modify a DCT QP |
3307 | * valid transitions are: | |
3308 | * RESET to INIT: must set access_flags, pkey_index and port | |
3309 | * INIT to RTR : must set min_rnr_timer, tclass, flow_label, | |
3310 | * mtu, gid_index and hop_limit | |
3311 | * Other transitions and attributes are illegal | |
3312 | */ | |
3313 | static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
3314 | int attr_mask, struct ib_udata *udata) | |
3315 | { | |
3316 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
3317 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
3318 | enum ib_qp_state cur_state, new_state; | |
3319 | int err = 0; | |
3320 | int required = IB_QP_STATE; | |
3321 | void *dctc; | |
3322 | ||
3323 | if (!(attr_mask & IB_QP_STATE)) | |
3324 | return -EINVAL; | |
3325 | ||
3326 | cur_state = qp->state; | |
3327 | new_state = attr->qp_state; | |
3328 | ||
3329 | dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); | |
3330 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { | |
3331 | required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; | |
3332 | if (!is_valid_mask(attr_mask, required, 0)) | |
3333 | return -EINVAL; | |
3334 | ||
3335 | if (attr->port_num == 0 || | |
3336 | attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { | |
3337 | mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", | |
3338 | attr->port_num, dev->num_ports); | |
3339 | return -EINVAL; | |
3340 | } | |
3341 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) | |
3342 | MLX5_SET(dctc, dctc, rre, 1); | |
3343 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) | |
3344 | MLX5_SET(dctc, dctc, rwe, 1); | |
3345 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { | |
3346 | if (!mlx5_ib_dc_atomic_is_supported(dev)) | |
3347 | return -EOPNOTSUPP; | |
3348 | MLX5_SET(dctc, dctc, rae, 1); | |
3349 | MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX); | |
3350 | } | |
3351 | MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); | |
3352 | MLX5_SET(dctc, dctc, port, attr->port_num); | |
3353 | MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); | |
3354 | ||
3355 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { | |
3356 | struct mlx5_ib_modify_qp_resp resp = {}; | |
3357 | u32 min_resp_len = offsetof(typeof(resp), dctn) + | |
3358 | sizeof(resp.dctn); | |
3359 | ||
3360 | if (udata->outlen < min_resp_len) | |
3361 | return -EINVAL; | |
3362 | resp.response_length = min_resp_len; | |
3363 | ||
3364 | required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; | |
3365 | if (!is_valid_mask(attr_mask, required, 0)) | |
3366 | return -EINVAL; | |
3367 | MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); | |
3368 | MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); | |
3369 | MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); | |
3370 | MLX5_SET(dctc, dctc, mtu, attr->path_mtu); | |
3371 | MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); | |
3372 | MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); | |
3373 | ||
3374 | err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, | |
3375 | MLX5_ST_SZ_BYTES(create_dct_in)); | |
3376 | if (err) | |
3377 | return err; | |
3378 | resp.dctn = qp->dct.mdct.mqp.qpn; | |
3379 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
3380 | if (err) { | |
3381 | mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); | |
3382 | return err; | |
3383 | } | |
3384 | } else { | |
3385 | mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); | |
3386 | return -EINVAL; | |
3387 | } | |
3388 | if (err) | |
3389 | qp->state = IB_QPS_ERR; | |
3390 | else | |
3391 | qp->state = new_state; | |
3392 | return err; | |
3393 | } | |
3394 | ||
e126ba97 EC |
3395 | int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
3396 | int attr_mask, struct ib_udata *udata) | |
3397 | { | |
3398 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
3399 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
61147f39 | 3400 | struct mlx5_ib_modify_qp ucmd = {}; |
d16e91da | 3401 | enum ib_qp_type qp_type; |
e126ba97 | 3402 | enum ib_qp_state cur_state, new_state; |
61147f39 | 3403 | size_t required_cmd_sz; |
e126ba97 EC |
3404 | int err = -EINVAL; |
3405 | int port; | |
2811ba51 | 3406 | enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED; |
e126ba97 | 3407 | |
28d61370 YH |
3408 | if (ibqp->rwq_ind_tbl) |
3409 | return -ENOSYS; | |
3410 | ||
61147f39 BW |
3411 | if (udata && udata->inlen) { |
3412 | required_cmd_sz = offsetof(typeof(ucmd), reserved) + | |
3413 | sizeof(ucmd.reserved); | |
3414 | if (udata->inlen < required_cmd_sz) | |
3415 | return -EINVAL; | |
3416 | ||
3417 | if (udata->inlen > sizeof(ucmd) && | |
3418 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
3419 | udata->inlen - sizeof(ucmd))) | |
3420 | return -EOPNOTSUPP; | |
3421 | ||
3422 | if (ib_copy_from_udata(&ucmd, udata, | |
3423 | min(udata->inlen, sizeof(ucmd)))) | |
3424 | return -EFAULT; | |
3425 | ||
3426 | if (ucmd.comp_mask || | |
3427 | memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || | |
3428 | memchr_inv(&ucmd.burst_info.reserved, 0, | |
3429 | sizeof(ucmd.burst_info.reserved))) | |
3430 | return -EOPNOTSUPP; | |
3431 | } | |
3432 | ||
d16e91da HE |
3433 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
3434 | return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); | |
3435 | ||
c32a4f29 MS |
3436 | if (ibqp->qp_type == IB_QPT_DRIVER) |
3437 | qp_type = qp->qp_sub_type; | |
3438 | else | |
3439 | qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? | |
3440 | IB_QPT_GSI : ibqp->qp_type; | |
3441 | ||
776a3906 MS |
3442 | if (qp_type == MLX5_IB_QPT_DCT) |
3443 | return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); | |
d16e91da | 3444 | |
e126ba97 EC |
3445 | mutex_lock(&qp->mutex); |
3446 | ||
3447 | cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; | |
3448 | new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; | |
3449 | ||
2811ba51 AS |
3450 | if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { |
3451 | port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; | |
3452 | ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port); | |
3453 | } | |
3454 | ||
c2e53b2c YH |
3455 | if (qp->flags & MLX5_IB_QP_UNDERLAY) { |
3456 | if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { | |
3457 | mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", | |
3458 | attr_mask); | |
3459 | goto out; | |
3460 | } | |
3461 | } else if (qp_type != MLX5_IB_QPT_REG_UMR && | |
c32a4f29 MS |
3462 | qp_type != MLX5_IB_QPT_DCI && |
3463 | !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) { | |
158abf86 HE |
3464 | mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", |
3465 | cur_state, new_state, ibqp->qp_type, attr_mask); | |
e126ba97 | 3466 | goto out; |
c32a4f29 MS |
3467 | } else if (qp_type == MLX5_IB_QPT_DCI && |
3468 | !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { | |
3469 | mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", | |
3470 | cur_state, new_state, qp_type, attr_mask); | |
3471 | goto out; | |
158abf86 | 3472 | } |
e126ba97 EC |
3473 | |
3474 | if ((attr_mask & IB_QP_PORT) && | |
938fe83c | 3475 | (attr->port_num == 0 || |
508562d6 | 3476 | attr->port_num > dev->num_ports)) { |
158abf86 HE |
3477 | mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", |
3478 | attr->port_num, dev->num_ports); | |
e126ba97 | 3479 | goto out; |
158abf86 | 3480 | } |
e126ba97 EC |
3481 | |
3482 | if (attr_mask & IB_QP_PKEY_INDEX) { | |
3483 | port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; | |
938fe83c | 3484 | if (attr->pkey_index >= |
158abf86 HE |
3485 | dev->mdev->port_caps[port - 1].pkey_table_len) { |
3486 | mlx5_ib_dbg(dev, "invalid pkey index %d\n", | |
3487 | attr->pkey_index); | |
e126ba97 | 3488 | goto out; |
158abf86 | 3489 | } |
e126ba97 EC |
3490 | } |
3491 | ||
3492 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && | |
938fe83c | 3493 | attr->max_rd_atomic > |
158abf86 HE |
3494 | (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { |
3495 | mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", | |
3496 | attr->max_rd_atomic); | |
e126ba97 | 3497 | goto out; |
158abf86 | 3498 | } |
e126ba97 EC |
3499 | |
3500 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && | |
938fe83c | 3501 | attr->max_dest_rd_atomic > |
158abf86 HE |
3502 | (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { |
3503 | mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", | |
3504 | attr->max_dest_rd_atomic); | |
e126ba97 | 3505 | goto out; |
158abf86 | 3506 | } |
e126ba97 EC |
3507 | |
3508 | if (cur_state == new_state && cur_state == IB_QPS_RESET) { | |
3509 | err = 0; | |
3510 | goto out; | |
3511 | } | |
3512 | ||
61147f39 BW |
3513 | err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, |
3514 | new_state, &ucmd); | |
e126ba97 EC |
3515 | |
3516 | out: | |
3517 | mutex_unlock(&qp->mutex); | |
3518 | return err; | |
3519 | } | |
3520 | ||
3521 | static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) | |
3522 | { | |
3523 | struct mlx5_ib_cq *cq; | |
3524 | unsigned cur; | |
3525 | ||
3526 | cur = wq->head - wq->tail; | |
3527 | if (likely(cur + nreq < wq->max_post)) | |
3528 | return 0; | |
3529 | ||
3530 | cq = to_mcq(ib_cq); | |
3531 | spin_lock(&cq->lock); | |
3532 | cur = wq->head - wq->tail; | |
3533 | spin_unlock(&cq->lock); | |
3534 | ||
3535 | return cur + nreq >= wq->max_post; | |
3536 | } | |
3537 | ||
3538 | static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, | |
3539 | u64 remote_addr, u32 rkey) | |
3540 | { | |
3541 | rseg->raddr = cpu_to_be64(remote_addr); | |
3542 | rseg->rkey = cpu_to_be32(rkey); | |
3543 | rseg->reserved = 0; | |
3544 | } | |
3545 | ||
f0313965 | 3546 | static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, |
f696bf6d | 3547 | const struct ib_send_wr *wr, void *qend, |
f0313965 ES |
3548 | struct mlx5_ib_qp *qp, int *size) |
3549 | { | |
3550 | void *seg = eseg; | |
3551 | ||
3552 | memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); | |
3553 | ||
3554 | if (wr->send_flags & IB_SEND_IP_CSUM) | |
3555 | eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | | |
3556 | MLX5_ETH_WQE_L4_CSUM; | |
3557 | ||
3558 | seg += sizeof(struct mlx5_wqe_eth_seg); | |
3559 | *size += sizeof(struct mlx5_wqe_eth_seg) / 16; | |
3560 | ||
3561 | if (wr->opcode == IB_WR_LSO) { | |
3562 | struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); | |
2b31f7ae | 3563 | int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start); |
f0313965 ES |
3564 | u64 left, leftlen, copysz; |
3565 | void *pdata = ud_wr->header; | |
3566 | ||
3567 | left = ud_wr->hlen; | |
3568 | eseg->mss = cpu_to_be16(ud_wr->mss); | |
2b31f7ae | 3569 | eseg->inline_hdr.sz = cpu_to_be16(left); |
f0313965 ES |
3570 | |
3571 | /* | |
3572 | * check if there is space till the end of queue, if yes, | |
3573 | * copy all in one shot, otherwise copy till the end of queue, | |
3574 | * rollback and than the copy the left | |
3575 | */ | |
2b31f7ae | 3576 | leftlen = qend - (void *)eseg->inline_hdr.start; |
f0313965 ES |
3577 | copysz = min_t(u64, leftlen, left); |
3578 | ||
3579 | memcpy(seg - size_of_inl_hdr_start, pdata, copysz); | |
3580 | ||
3581 | if (likely(copysz > size_of_inl_hdr_start)) { | |
3582 | seg += ALIGN(copysz - size_of_inl_hdr_start, 16); | |
3583 | *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; | |
3584 | } | |
3585 | ||
3586 | if (unlikely(copysz < left)) { /* the last wqe in the queue */ | |
3587 | seg = mlx5_get_send_wqe(qp, 0); | |
3588 | left -= copysz; | |
3589 | pdata += copysz; | |
3590 | memcpy(seg, pdata, left); | |
3591 | seg += ALIGN(left, 16); | |
3592 | *size += ALIGN(left, 16) / 16; | |
3593 | } | |
3594 | } | |
3595 | ||
3596 | return seg; | |
3597 | } | |
3598 | ||
e126ba97 | 3599 | static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, |
f696bf6d | 3600 | const struct ib_send_wr *wr) |
e126ba97 | 3601 | { |
e622f2f4 CH |
3602 | memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); |
3603 | dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); | |
3604 | dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); | |
e126ba97 EC |
3605 | } |
3606 | ||
3607 | static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) | |
3608 | { | |
3609 | dseg->byte_count = cpu_to_be32(sg->length); | |
3610 | dseg->lkey = cpu_to_be32(sg->lkey); | |
3611 | dseg->addr = cpu_to_be64(sg->addr); | |
3612 | } | |
3613 | ||
31616255 | 3614 | static u64 get_xlt_octo(u64 bytes) |
e126ba97 | 3615 | { |
31616255 AK |
3616 | return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / |
3617 | MLX5_IB_UMR_OCTOWORD; | |
e126ba97 EC |
3618 | } |
3619 | ||
3620 | static __be64 frwr_mkey_mask(void) | |
3621 | { | |
3622 | u64 result; | |
3623 | ||
3624 | result = MLX5_MKEY_MASK_LEN | | |
3625 | MLX5_MKEY_MASK_PAGE_SIZE | | |
3626 | MLX5_MKEY_MASK_START_ADDR | | |
3627 | MLX5_MKEY_MASK_EN_RINVAL | | |
3628 | MLX5_MKEY_MASK_KEY | | |
3629 | MLX5_MKEY_MASK_LR | | |
3630 | MLX5_MKEY_MASK_LW | | |
3631 | MLX5_MKEY_MASK_RR | | |
3632 | MLX5_MKEY_MASK_RW | | |
3633 | MLX5_MKEY_MASK_A | | |
3634 | MLX5_MKEY_MASK_SMALL_FENCE | | |
3635 | MLX5_MKEY_MASK_FREE; | |
3636 | ||
3637 | return cpu_to_be64(result); | |
3638 | } | |
3639 | ||
e6631814 SG |
3640 | static __be64 sig_mkey_mask(void) |
3641 | { | |
3642 | u64 result; | |
3643 | ||
3644 | result = MLX5_MKEY_MASK_LEN | | |
3645 | MLX5_MKEY_MASK_PAGE_SIZE | | |
3646 | MLX5_MKEY_MASK_START_ADDR | | |
d5436ba0 | 3647 | MLX5_MKEY_MASK_EN_SIGERR | |
e6631814 SG |
3648 | MLX5_MKEY_MASK_EN_RINVAL | |
3649 | MLX5_MKEY_MASK_KEY | | |
3650 | MLX5_MKEY_MASK_LR | | |
3651 | MLX5_MKEY_MASK_LW | | |
3652 | MLX5_MKEY_MASK_RR | | |
3653 | MLX5_MKEY_MASK_RW | | |
3654 | MLX5_MKEY_MASK_SMALL_FENCE | | |
3655 | MLX5_MKEY_MASK_FREE | | |
3656 | MLX5_MKEY_MASK_BSF_EN; | |
3657 | ||
3658 | return cpu_to_be64(result); | |
3659 | } | |
3660 | ||
8a187ee5 | 3661 | static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, |
064e5262 | 3662 | struct mlx5_ib_mr *mr, bool umr_inline) |
8a187ee5 | 3663 | { |
31616255 | 3664 | int size = mr->ndescs * mr->desc_size; |
8a187ee5 SG |
3665 | |
3666 | memset(umr, 0, sizeof(*umr)); | |
b005d316 | 3667 | |
8a187ee5 | 3668 | umr->flags = MLX5_UMR_CHECK_NOT_FREE; |
064e5262 IB |
3669 | if (umr_inline) |
3670 | umr->flags |= MLX5_UMR_INLINE; | |
31616255 | 3671 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); |
8a187ee5 SG |
3672 | umr->mkey_mask = frwr_mkey_mask(); |
3673 | } | |
3674 | ||
dd01e66a | 3675 | static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) |
e126ba97 EC |
3676 | { |
3677 | memset(umr, 0, sizeof(*umr)); | |
dd01e66a | 3678 | umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); |
2d221588 | 3679 | umr->flags = MLX5_UMR_INLINE; |
e126ba97 EC |
3680 | } |
3681 | ||
31616255 | 3682 | static __be64 get_umr_enable_mr_mask(void) |
968e78dd HE |
3683 | { |
3684 | u64 result; | |
3685 | ||
31616255 | 3686 | result = MLX5_MKEY_MASK_KEY | |
968e78dd HE |
3687 | MLX5_MKEY_MASK_FREE; |
3688 | ||
968e78dd HE |
3689 | return cpu_to_be64(result); |
3690 | } | |
3691 | ||
31616255 | 3692 | static __be64 get_umr_disable_mr_mask(void) |
968e78dd HE |
3693 | { |
3694 | u64 result; | |
3695 | ||
3696 | result = MLX5_MKEY_MASK_FREE; | |
3697 | ||
3698 | return cpu_to_be64(result); | |
3699 | } | |
3700 | ||
56e11d62 NO |
3701 | static __be64 get_umr_update_translation_mask(void) |
3702 | { | |
3703 | u64 result; | |
3704 | ||
3705 | result = MLX5_MKEY_MASK_LEN | | |
3706 | MLX5_MKEY_MASK_PAGE_SIZE | | |
31616255 | 3707 | MLX5_MKEY_MASK_START_ADDR; |
56e11d62 NO |
3708 | |
3709 | return cpu_to_be64(result); | |
3710 | } | |
3711 | ||
31616255 | 3712 | static __be64 get_umr_update_access_mask(int atomic) |
56e11d62 NO |
3713 | { |
3714 | u64 result; | |
3715 | ||
31616255 AK |
3716 | result = MLX5_MKEY_MASK_LR | |
3717 | MLX5_MKEY_MASK_LW | | |
56e11d62 | 3718 | MLX5_MKEY_MASK_RR | |
31616255 AK |
3719 | MLX5_MKEY_MASK_RW; |
3720 | ||
3721 | if (atomic) | |
3722 | result |= MLX5_MKEY_MASK_A; | |
56e11d62 NO |
3723 | |
3724 | return cpu_to_be64(result); | |
3725 | } | |
3726 | ||
3727 | static __be64 get_umr_update_pd_mask(void) | |
3728 | { | |
3729 | u64 result; | |
3730 | ||
31616255 | 3731 | result = MLX5_MKEY_MASK_PD; |
56e11d62 NO |
3732 | |
3733 | return cpu_to_be64(result); | |
3734 | } | |
3735 | ||
c8d75a98 MD |
3736 | static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) |
3737 | { | |
3738 | if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && | |
3739 | MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || | |
3740 | (mask & MLX5_MKEY_MASK_A && | |
3741 | MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) | |
3742 | return -EPERM; | |
3743 | return 0; | |
3744 | } | |
3745 | ||
3746 | static int set_reg_umr_segment(struct mlx5_ib_dev *dev, | |
3747 | struct mlx5_wqe_umr_ctrl_seg *umr, | |
f696bf6d | 3748 | const struct ib_send_wr *wr, int atomic) |
e126ba97 | 3749 | { |
f696bf6d | 3750 | const struct mlx5_umr_wr *umrwr = umr_wr(wr); |
e126ba97 EC |
3751 | |
3752 | memset(umr, 0, sizeof(*umr)); | |
3753 | ||
968e78dd HE |
3754 | if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) |
3755 | umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ | |
3756 | else | |
3757 | umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ | |
3758 | ||
31616255 AK |
3759 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); |
3760 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { | |
3761 | u64 offset = get_xlt_octo(umrwr->offset); | |
3762 | ||
3763 | umr->xlt_offset = cpu_to_be16(offset & 0xffff); | |
3764 | umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); | |
3765 | umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; | |
e126ba97 | 3766 | } |
31616255 AK |
3767 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) |
3768 | umr->mkey_mask |= get_umr_update_translation_mask(); | |
3769 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { | |
3770 | umr->mkey_mask |= get_umr_update_access_mask(atomic); | |
3771 | umr->mkey_mask |= get_umr_update_pd_mask(); | |
3772 | } | |
3773 | if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) | |
3774 | umr->mkey_mask |= get_umr_enable_mr_mask(); | |
3775 | if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) | |
3776 | umr->mkey_mask |= get_umr_disable_mr_mask(); | |
e126ba97 EC |
3777 | |
3778 | if (!wr->num_sge) | |
968e78dd | 3779 | umr->flags |= MLX5_UMR_INLINE; |
c8d75a98 MD |
3780 | |
3781 | return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); | |
e126ba97 EC |
3782 | } |
3783 | ||
3784 | static u8 get_umr_flags(int acc) | |
3785 | { | |
3786 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | | |
3787 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | | |
3788 | (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | | |
3789 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | | |
2ac45934 | 3790 | MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; |
e126ba97 EC |
3791 | } |
3792 | ||
8a187ee5 SG |
3793 | static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, |
3794 | struct mlx5_ib_mr *mr, | |
3795 | u32 key, int access) | |
3796 | { | |
3797 | int ndescs = ALIGN(mr->ndescs, 8) >> 1; | |
3798 | ||
3799 | memset(seg, 0, sizeof(*seg)); | |
b005d316 | 3800 | |
ec22eb53 | 3801 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) |
b005d316 | 3802 | seg->log2_page_size = ilog2(mr->ibmr.page_size); |
ec22eb53 | 3803 | else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
b005d316 SG |
3804 | /* KLMs take twice the size of MTTs */ |
3805 | ndescs *= 2; | |
3806 | ||
3807 | seg->flags = get_umr_flags(access) | mr->access_mode; | |
8a187ee5 SG |
3808 | seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); |
3809 | seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); | |
3810 | seg->start_addr = cpu_to_be64(mr->ibmr.iova); | |
3811 | seg->len = cpu_to_be64(mr->ibmr.length); | |
3812 | seg->xlt_oct_size = cpu_to_be32(ndescs); | |
8a187ee5 SG |
3813 | } |
3814 | ||
dd01e66a | 3815 | static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) |
e126ba97 EC |
3816 | { |
3817 | memset(seg, 0, sizeof(*seg)); | |
dd01e66a | 3818 | seg->status = MLX5_MKEY_STATUS_FREE; |
e126ba97 EC |
3819 | } |
3820 | ||
f696bf6d BVA |
3821 | static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, |
3822 | const struct ib_send_wr *wr) | |
e126ba97 | 3823 | { |
f696bf6d | 3824 | const struct mlx5_umr_wr *umrwr = umr_wr(wr); |
968e78dd | 3825 | |
e126ba97 | 3826 | memset(seg, 0, sizeof(*seg)); |
31616255 | 3827 | if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) |
968e78dd | 3828 | seg->status = MLX5_MKEY_STATUS_FREE; |
e126ba97 | 3829 | |
968e78dd | 3830 | seg->flags = convert_access(umrwr->access_flags); |
31616255 AK |
3831 | if (umrwr->pd) |
3832 | seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); | |
3833 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && | |
3834 | !umrwr->length) | |
3835 | seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); | |
3836 | ||
3837 | seg->start_addr = cpu_to_be64(umrwr->virt_addr); | |
968e78dd HE |
3838 | seg->len = cpu_to_be64(umrwr->length); |
3839 | seg->log2_page_size = umrwr->page_shift; | |
746b5583 | 3840 | seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | |
968e78dd | 3841 | mlx5_mkey_variant(umrwr->mkey)); |
e126ba97 EC |
3842 | } |
3843 | ||
8a187ee5 SG |
3844 | static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, |
3845 | struct mlx5_ib_mr *mr, | |
3846 | struct mlx5_ib_pd *pd) | |
3847 | { | |
3848 | int bcount = mr->desc_size * mr->ndescs; | |
3849 | ||
3850 | dseg->addr = cpu_to_be64(mr->desc_map); | |
3851 | dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); | |
3852 | dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); | |
3853 | } | |
3854 | ||
064e5262 IB |
3855 | static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp, |
3856 | struct mlx5_ib_mr *mr, int mr_list_size) | |
3857 | { | |
3858 | void *qend = qp->sq.qend; | |
3859 | void *addr = mr->descs; | |
3860 | int copy; | |
3861 | ||
3862 | if (unlikely(seg + mr_list_size > qend)) { | |
3863 | copy = qend - seg; | |
3864 | memcpy(seg, addr, copy); | |
3865 | addr += copy; | |
3866 | mr_list_size -= copy; | |
3867 | seg = mlx5_get_send_wqe(qp, 0); | |
3868 | } | |
3869 | memcpy(seg, addr, mr_list_size); | |
3870 | seg += mr_list_size; | |
3871 | } | |
3872 | ||
f696bf6d | 3873 | static __be32 send_ieth(const struct ib_send_wr *wr) |
e126ba97 EC |
3874 | { |
3875 | switch (wr->opcode) { | |
3876 | case IB_WR_SEND_WITH_IMM: | |
3877 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
3878 | return wr->ex.imm_data; | |
3879 | ||
3880 | case IB_WR_SEND_WITH_INV: | |
3881 | return cpu_to_be32(wr->ex.invalidate_rkey); | |
3882 | ||
3883 | default: | |
3884 | return 0; | |
3885 | } | |
3886 | } | |
3887 | ||
3888 | static u8 calc_sig(void *wqe, int size) | |
3889 | { | |
3890 | u8 *p = wqe; | |
3891 | u8 res = 0; | |
3892 | int i; | |
3893 | ||
3894 | for (i = 0; i < size; i++) | |
3895 | res ^= p[i]; | |
3896 | ||
3897 | return ~res; | |
3898 | } | |
3899 | ||
3900 | static u8 wq_sig(void *wqe) | |
3901 | { | |
3902 | return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); | |
3903 | } | |
3904 | ||
f696bf6d | 3905 | static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, |
e126ba97 EC |
3906 | void *wqe, int *sz) |
3907 | { | |
3908 | struct mlx5_wqe_inline_seg *seg; | |
3909 | void *qend = qp->sq.qend; | |
3910 | void *addr; | |
3911 | int inl = 0; | |
3912 | int copy; | |
3913 | int len; | |
3914 | int i; | |
3915 | ||
3916 | seg = wqe; | |
3917 | wqe += sizeof(*seg); | |
3918 | for (i = 0; i < wr->num_sge; i++) { | |
3919 | addr = (void *)(unsigned long)(wr->sg_list[i].addr); | |
3920 | len = wr->sg_list[i].length; | |
3921 | inl += len; | |
3922 | ||
3923 | if (unlikely(inl > qp->max_inline_data)) | |
3924 | return -ENOMEM; | |
3925 | ||
3926 | if (unlikely(wqe + len > qend)) { | |
3927 | copy = qend - wqe; | |
3928 | memcpy(wqe, addr, copy); | |
3929 | addr += copy; | |
3930 | len -= copy; | |
3931 | wqe = mlx5_get_send_wqe(qp, 0); | |
3932 | } | |
3933 | memcpy(wqe, addr, len); | |
3934 | wqe += len; | |
3935 | } | |
3936 | ||
3937 | seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); | |
3938 | ||
3939 | *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; | |
3940 | ||
3941 | return 0; | |
3942 | } | |
3943 | ||
e6631814 SG |
3944 | static u16 prot_field_size(enum ib_signature_type type) |
3945 | { | |
3946 | switch (type) { | |
3947 | case IB_SIG_TYPE_T10_DIF: | |
3948 | return MLX5_DIF_SIZE; | |
3949 | default: | |
3950 | return 0; | |
3951 | } | |
3952 | } | |
3953 | ||
3954 | static u8 bs_selector(int block_size) | |
3955 | { | |
3956 | switch (block_size) { | |
3957 | case 512: return 0x1; | |
3958 | case 520: return 0x2; | |
3959 | case 4096: return 0x3; | |
3960 | case 4160: return 0x4; | |
3961 | case 1073741824: return 0x5; | |
3962 | default: return 0; | |
3963 | } | |
3964 | } | |
3965 | ||
78eda2bb SG |
3966 | static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, |
3967 | struct mlx5_bsf_inl *inl) | |
e6631814 | 3968 | { |
142537f4 SG |
3969 | /* Valid inline section and allow BSF refresh */ |
3970 | inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | | |
3971 | MLX5_BSF_REFRESH_DIF); | |
3972 | inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); | |
3973 | inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); | |
78eda2bb SG |
3974 | /* repeating block */ |
3975 | inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; | |
3976 | inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? | |
3977 | MLX5_DIF_CRC : MLX5_DIF_IPCS; | |
e6631814 | 3978 | |
78eda2bb SG |
3979 | if (domain->sig.dif.ref_remap) |
3980 | inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; | |
e6631814 | 3981 | |
78eda2bb SG |
3982 | if (domain->sig.dif.app_escape) { |
3983 | if (domain->sig.dif.ref_escape) | |
3984 | inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; | |
3985 | else | |
3986 | inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; | |
e6631814 SG |
3987 | } |
3988 | ||
78eda2bb SG |
3989 | inl->dif_app_bitmask_check = |
3990 | cpu_to_be16(domain->sig.dif.apptag_check_mask); | |
e6631814 SG |
3991 | } |
3992 | ||
3993 | static int mlx5_set_bsf(struct ib_mr *sig_mr, | |
3994 | struct ib_sig_attrs *sig_attrs, | |
3995 | struct mlx5_bsf *bsf, u32 data_size) | |
3996 | { | |
3997 | struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; | |
3998 | struct mlx5_bsf_basic *basic = &bsf->basic; | |
3999 | struct ib_sig_domain *mem = &sig_attrs->mem; | |
4000 | struct ib_sig_domain *wire = &sig_attrs->wire; | |
e6631814 | 4001 | |
c7f44fbd | 4002 | memset(bsf, 0, sizeof(*bsf)); |
78eda2bb SG |
4003 | |
4004 | /* Basic + Extended + Inline */ | |
4005 | basic->bsf_size_sbs = 1 << 7; | |
4006 | /* Input domain check byte mask */ | |
4007 | basic->check_byte_mask = sig_attrs->check_mask; | |
4008 | basic->raw_data_size = cpu_to_be32(data_size); | |
4009 | ||
4010 | /* Memory domain */ | |
e6631814 | 4011 | switch (sig_attrs->mem.sig_type) { |
78eda2bb SG |
4012 | case IB_SIG_TYPE_NONE: |
4013 | break; | |
e6631814 | 4014 | case IB_SIG_TYPE_T10_DIF: |
78eda2bb SG |
4015 | basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); |
4016 | basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); | |
4017 | mlx5_fill_inl_bsf(mem, &bsf->m_inl); | |
4018 | break; | |
4019 | default: | |
4020 | return -EINVAL; | |
4021 | } | |
e6631814 | 4022 | |
78eda2bb SG |
4023 | /* Wire domain */ |
4024 | switch (sig_attrs->wire.sig_type) { | |
4025 | case IB_SIG_TYPE_NONE: | |
4026 | break; | |
4027 | case IB_SIG_TYPE_T10_DIF: | |
e6631814 | 4028 | if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && |
78eda2bb | 4029 | mem->sig_type == wire->sig_type) { |
e6631814 | 4030 | /* Same block structure */ |
142537f4 | 4031 | basic->bsf_size_sbs |= 1 << 4; |
e6631814 | 4032 | if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) |
fd22f78c | 4033 | basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; |
c7f44fbd | 4034 | if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) |
fd22f78c | 4035 | basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; |
c7f44fbd | 4036 | if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) |
fd22f78c | 4037 | basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; |
e6631814 SG |
4038 | } else |
4039 | basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); | |
4040 | ||
142537f4 | 4041 | basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); |
78eda2bb | 4042 | mlx5_fill_inl_bsf(wire, &bsf->w_inl); |
e6631814 | 4043 | break; |
e6631814 SG |
4044 | default: |
4045 | return -EINVAL; | |
4046 | } | |
4047 | ||
4048 | return 0; | |
4049 | } | |
4050 | ||
f696bf6d | 4051 | static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, |
e622f2f4 | 4052 | struct mlx5_ib_qp *qp, void **seg, int *size) |
e6631814 | 4053 | { |
e622f2f4 CH |
4054 | struct ib_sig_attrs *sig_attrs = wr->sig_attrs; |
4055 | struct ib_mr *sig_mr = wr->sig_mr; | |
e6631814 | 4056 | struct mlx5_bsf *bsf; |
e622f2f4 CH |
4057 | u32 data_len = wr->wr.sg_list->length; |
4058 | u32 data_key = wr->wr.sg_list->lkey; | |
4059 | u64 data_va = wr->wr.sg_list->addr; | |
e6631814 SG |
4060 | int ret; |
4061 | int wqe_size; | |
4062 | ||
e622f2f4 CH |
4063 | if (!wr->prot || |
4064 | (data_key == wr->prot->lkey && | |
4065 | data_va == wr->prot->addr && | |
4066 | data_len == wr->prot->length)) { | |
e6631814 SG |
4067 | /** |
4068 | * Source domain doesn't contain signature information | |
5c273b16 | 4069 | * or data and protection are interleaved in memory. |
e6631814 SG |
4070 | * So need construct: |
4071 | * ------------------ | |
4072 | * | data_klm | | |
4073 | * ------------------ | |
4074 | * | BSF | | |
4075 | * ------------------ | |
4076 | **/ | |
4077 | struct mlx5_klm *data_klm = *seg; | |
4078 | ||
4079 | data_klm->bcount = cpu_to_be32(data_len); | |
4080 | data_klm->key = cpu_to_be32(data_key); | |
4081 | data_klm->va = cpu_to_be64(data_va); | |
4082 | wqe_size = ALIGN(sizeof(*data_klm), 64); | |
4083 | } else { | |
4084 | /** | |
4085 | * Source domain contains signature information | |
4086 | * So need construct a strided block format: | |
4087 | * --------------------------- | |
4088 | * | stride_block_ctrl | | |
4089 | * --------------------------- | |
4090 | * | data_klm | | |
4091 | * --------------------------- | |
4092 | * | prot_klm | | |
4093 | * --------------------------- | |
4094 | * | BSF | | |
4095 | * --------------------------- | |
4096 | **/ | |
4097 | struct mlx5_stride_block_ctrl_seg *sblock_ctrl; | |
4098 | struct mlx5_stride_block_entry *data_sentry; | |
4099 | struct mlx5_stride_block_entry *prot_sentry; | |
e622f2f4 CH |
4100 | u32 prot_key = wr->prot->lkey; |
4101 | u64 prot_va = wr->prot->addr; | |
e6631814 SG |
4102 | u16 block_size = sig_attrs->mem.sig.dif.pi_interval; |
4103 | int prot_size; | |
4104 | ||
4105 | sblock_ctrl = *seg; | |
4106 | data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); | |
4107 | prot_sentry = (void *)data_sentry + sizeof(*data_sentry); | |
4108 | ||
4109 | prot_size = prot_field_size(sig_attrs->mem.sig_type); | |
4110 | if (!prot_size) { | |
4111 | pr_err("Bad block size given: %u\n", block_size); | |
4112 | return -EINVAL; | |
4113 | } | |
4114 | sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + | |
4115 | prot_size); | |
4116 | sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); | |
4117 | sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); | |
4118 | sblock_ctrl->num_entries = cpu_to_be16(2); | |
4119 | ||
4120 | data_sentry->bcount = cpu_to_be16(block_size); | |
4121 | data_sentry->key = cpu_to_be32(data_key); | |
4122 | data_sentry->va = cpu_to_be64(data_va); | |
5c273b16 SG |
4123 | data_sentry->stride = cpu_to_be16(block_size); |
4124 | ||
e6631814 SG |
4125 | prot_sentry->bcount = cpu_to_be16(prot_size); |
4126 | prot_sentry->key = cpu_to_be32(prot_key); | |
5c273b16 SG |
4127 | prot_sentry->va = cpu_to_be64(prot_va); |
4128 | prot_sentry->stride = cpu_to_be16(prot_size); | |
e6631814 | 4129 | |
e6631814 SG |
4130 | wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + |
4131 | sizeof(*prot_sentry), 64); | |
4132 | } | |
4133 | ||
4134 | *seg += wqe_size; | |
4135 | *size += wqe_size / 16; | |
4136 | if (unlikely((*seg == qp->sq.qend))) | |
4137 | *seg = mlx5_get_send_wqe(qp, 0); | |
4138 | ||
4139 | bsf = *seg; | |
4140 | ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); | |
4141 | if (ret) | |
4142 | return -EINVAL; | |
4143 | ||
4144 | *seg += sizeof(*bsf); | |
4145 | *size += sizeof(*bsf) / 16; | |
4146 | if (unlikely((*seg == qp->sq.qend))) | |
4147 | *seg = mlx5_get_send_wqe(qp, 0); | |
4148 | ||
4149 | return 0; | |
4150 | } | |
4151 | ||
4152 | static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, | |
f696bf6d | 4153 | const struct ib_sig_handover_wr *wr, u32 size, |
e6631814 SG |
4154 | u32 length, u32 pdn) |
4155 | { | |
e622f2f4 | 4156 | struct ib_mr *sig_mr = wr->sig_mr; |
e6631814 | 4157 | u32 sig_key = sig_mr->rkey; |
d5436ba0 | 4158 | u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; |
e6631814 SG |
4159 | |
4160 | memset(seg, 0, sizeof(*seg)); | |
4161 | ||
e622f2f4 | 4162 | seg->flags = get_umr_flags(wr->access_flags) | |
ec22eb53 | 4163 | MLX5_MKC_ACCESS_MODE_KLMS; |
e6631814 | 4164 | seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); |
d5436ba0 | 4165 | seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | |
e6631814 SG |
4166 | MLX5_MKEY_BSF_EN | pdn); |
4167 | seg->len = cpu_to_be64(length); | |
31616255 | 4168 | seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); |
e6631814 SG |
4169 | seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); |
4170 | } | |
4171 | ||
4172 | static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, | |
31616255 | 4173 | u32 size) |
e6631814 SG |
4174 | { |
4175 | memset(umr, 0, sizeof(*umr)); | |
4176 | ||
4177 | umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; | |
31616255 | 4178 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); |
e6631814 SG |
4179 | umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); |
4180 | umr->mkey_mask = sig_mkey_mask(); | |
4181 | } | |
4182 | ||
4183 | ||
f696bf6d BVA |
4184 | static int set_sig_umr_wr(const struct ib_send_wr *send_wr, |
4185 | struct mlx5_ib_qp *qp, void **seg, int *size) | |
e6631814 | 4186 | { |
f696bf6d | 4187 | const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); |
e622f2f4 | 4188 | struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); |
e6631814 | 4189 | u32 pdn = get_pd(qp)->pdn; |
31616255 | 4190 | u32 xlt_size; |
e6631814 SG |
4191 | int region_len, ret; |
4192 | ||
e622f2f4 CH |
4193 | if (unlikely(wr->wr.num_sge != 1) || |
4194 | unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || | |
d5436ba0 SG |
4195 | unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || |
4196 | unlikely(!sig_mr->sig->sig_status_checked)) | |
e6631814 SG |
4197 | return -EINVAL; |
4198 | ||
4199 | /* length of the protected region, data + protection */ | |
e622f2f4 CH |
4200 | region_len = wr->wr.sg_list->length; |
4201 | if (wr->prot && | |
4202 | (wr->prot->lkey != wr->wr.sg_list->lkey || | |
4203 | wr->prot->addr != wr->wr.sg_list->addr || | |
4204 | wr->prot->length != wr->wr.sg_list->length)) | |
4205 | region_len += wr->prot->length; | |
e6631814 SG |
4206 | |
4207 | /** | |
4208 | * KLM octoword size - if protection was provided | |
4209 | * then we use strided block format (3 octowords), | |
4210 | * else we use single KLM (1 octoword) | |
4211 | **/ | |
31616255 | 4212 | xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); |
e6631814 | 4213 | |
31616255 | 4214 | set_sig_umr_segment(*seg, xlt_size); |
e6631814 SG |
4215 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4216 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
4217 | if (unlikely((*seg == qp->sq.qend))) | |
4218 | *seg = mlx5_get_send_wqe(qp, 0); | |
4219 | ||
31616255 | 4220 | set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); |
e6631814 SG |
4221 | *seg += sizeof(struct mlx5_mkey_seg); |
4222 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
4223 | if (unlikely((*seg == qp->sq.qend))) | |
4224 | *seg = mlx5_get_send_wqe(qp, 0); | |
4225 | ||
4226 | ret = set_sig_data_segment(wr, qp, seg, size); | |
4227 | if (ret) | |
4228 | return ret; | |
4229 | ||
d5436ba0 | 4230 | sig_mr->sig->sig_status_checked = false; |
e6631814 SG |
4231 | return 0; |
4232 | } | |
4233 | ||
4234 | static int set_psv_wr(struct ib_sig_domain *domain, | |
4235 | u32 psv_idx, void **seg, int *size) | |
4236 | { | |
4237 | struct mlx5_seg_set_psv *psv_seg = *seg; | |
4238 | ||
4239 | memset(psv_seg, 0, sizeof(*psv_seg)); | |
4240 | psv_seg->psv_num = cpu_to_be32(psv_idx); | |
4241 | switch (domain->sig_type) { | |
78eda2bb SG |
4242 | case IB_SIG_TYPE_NONE: |
4243 | break; | |
e6631814 SG |
4244 | case IB_SIG_TYPE_T10_DIF: |
4245 | psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | | |
4246 | domain->sig.dif.app_tag); | |
4247 | psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); | |
e6631814 | 4248 | break; |
e6631814 | 4249 | default: |
12bbf1ea LR |
4250 | pr_err("Bad signature type (%d) is given.\n", |
4251 | domain->sig_type); | |
4252 | return -EINVAL; | |
e6631814 SG |
4253 | } |
4254 | ||
78eda2bb SG |
4255 | *seg += sizeof(*psv_seg); |
4256 | *size += sizeof(*psv_seg) / 16; | |
4257 | ||
e6631814 SG |
4258 | return 0; |
4259 | } | |
4260 | ||
8a187ee5 | 4261 | static int set_reg_wr(struct mlx5_ib_qp *qp, |
f696bf6d | 4262 | const struct ib_reg_wr *wr, |
8a187ee5 SG |
4263 | void **seg, int *size) |
4264 | { | |
4265 | struct mlx5_ib_mr *mr = to_mmr(wr->mr); | |
4266 | struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); | |
064e5262 IB |
4267 | int mr_list_size = mr->ndescs * mr->desc_size; |
4268 | bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; | |
8a187ee5 SG |
4269 | |
4270 | if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { | |
4271 | mlx5_ib_warn(to_mdev(qp->ibqp.device), | |
4272 | "Invalid IB_SEND_INLINE send flag\n"); | |
4273 | return -EINVAL; | |
4274 | } | |
4275 | ||
064e5262 | 4276 | set_reg_umr_seg(*seg, mr, umr_inline); |
8a187ee5 SG |
4277 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4278 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
4279 | if (unlikely((*seg == qp->sq.qend))) | |
4280 | *seg = mlx5_get_send_wqe(qp, 0); | |
4281 | ||
4282 | set_reg_mkey_seg(*seg, mr, wr->key, wr->access); | |
4283 | *seg += sizeof(struct mlx5_mkey_seg); | |
4284 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
4285 | if (unlikely((*seg == qp->sq.qend))) | |
4286 | *seg = mlx5_get_send_wqe(qp, 0); | |
4287 | ||
064e5262 IB |
4288 | if (umr_inline) { |
4289 | set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size); | |
4290 | *size += get_xlt_octo(mr_list_size); | |
4291 | } else { | |
4292 | set_reg_data_seg(*seg, mr, pd); | |
4293 | *seg += sizeof(struct mlx5_wqe_data_seg); | |
4294 | *size += (sizeof(struct mlx5_wqe_data_seg) / 16); | |
4295 | } | |
8a187ee5 SG |
4296 | return 0; |
4297 | } | |
4298 | ||
dd01e66a | 4299 | static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) |
e126ba97 | 4300 | { |
dd01e66a | 4301 | set_linv_umr_seg(*seg); |
e126ba97 EC |
4302 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4303 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
4304 | if (unlikely((*seg == qp->sq.qend))) | |
4305 | *seg = mlx5_get_send_wqe(qp, 0); | |
dd01e66a | 4306 | set_linv_mkey_seg(*seg); |
e126ba97 EC |
4307 | *seg += sizeof(struct mlx5_mkey_seg); |
4308 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
4309 | if (unlikely((*seg == qp->sq.qend))) | |
4310 | *seg = mlx5_get_send_wqe(qp, 0); | |
e126ba97 EC |
4311 | } |
4312 | ||
4313 | static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) | |
4314 | { | |
4315 | __be32 *p = NULL; | |
4316 | int tidx = idx; | |
4317 | int i, j; | |
4318 | ||
4319 | pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); | |
4320 | for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { | |
4321 | if ((i & 0xf) == 0) { | |
4322 | void *buf = mlx5_get_send_wqe(qp, tidx); | |
4323 | tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); | |
4324 | p = buf; | |
4325 | j = 0; | |
4326 | } | |
4327 | pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), | |
4328 | be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), | |
4329 | be32_to_cpu(p[j + 3])); | |
4330 | } | |
4331 | } | |
4332 | ||
7bb1fafc | 4333 | static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, |
6e5eadac | 4334 | struct mlx5_wqe_ctrl_seg **ctrl, |
f696bf6d | 4335 | const struct ib_send_wr *wr, unsigned *idx, |
7bb1fafc | 4336 | int *size, int nreq, bool send_signaled, bool solicited) |
6e5eadac | 4337 | { |
b2a232d2 LR |
4338 | if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) |
4339 | return -ENOMEM; | |
6e5eadac SG |
4340 | |
4341 | *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); | |
4342 | *seg = mlx5_get_send_wqe(qp, *idx); | |
4343 | *ctrl = *seg; | |
4344 | *(uint32_t *)(*seg + 8) = 0; | |
4345 | (*ctrl)->imm = send_ieth(wr); | |
4346 | (*ctrl)->fm_ce_se = qp->sq_signal_bits | | |
7bb1fafc BVA |
4347 | (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | |
4348 | (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); | |
6e5eadac SG |
4349 | |
4350 | *seg += sizeof(**ctrl); | |
4351 | *size = sizeof(**ctrl) / 16; | |
4352 | ||
b2a232d2 | 4353 | return 0; |
6e5eadac SG |
4354 | } |
4355 | ||
7bb1fafc BVA |
4356 | static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, |
4357 | struct mlx5_wqe_ctrl_seg **ctrl, | |
4358 | const struct ib_send_wr *wr, unsigned *idx, | |
4359 | int *size, int nreq) | |
4360 | { | |
4361 | return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq, | |
4362 | wr->send_flags & IB_SEND_SIGNALED, | |
4363 | wr->send_flags & IB_SEND_SOLICITED); | |
4364 | } | |
4365 | ||
6e5eadac SG |
4366 | static void finish_wqe(struct mlx5_ib_qp *qp, |
4367 | struct mlx5_wqe_ctrl_seg *ctrl, | |
4368 | u8 size, unsigned idx, u64 wr_id, | |
6e8484c5 | 4369 | int nreq, u8 fence, u32 mlx5_opcode) |
6e5eadac SG |
4370 | { |
4371 | u8 opmod = 0; | |
4372 | ||
4373 | ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | | |
4374 | mlx5_opcode | ((u32)opmod << 24)); | |
19098df2 | 4375 | ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); |
6e5eadac | 4376 | ctrl->fm_ce_se |= fence; |
6e5eadac SG |
4377 | if (unlikely(qp->wq_sig)) |
4378 | ctrl->signature = wq_sig(ctrl); | |
4379 | ||
4380 | qp->sq.wrid[idx] = wr_id; | |
4381 | qp->sq.w_list[idx].opcode = mlx5_opcode; | |
4382 | qp->sq.wqe_head[idx] = qp->sq.head + nreq; | |
4383 | qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); | |
4384 | qp->sq.w_list[idx].next = qp->sq.cur_post; | |
4385 | } | |
4386 | ||
d34ac5cd BVA |
4387 | static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
4388 | const struct ib_send_wr **bad_wr, bool drain) | |
e126ba97 EC |
4389 | { |
4390 | struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ | |
4391 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
89ea94a7 | 4392 | struct mlx5_core_dev *mdev = dev->mdev; |
d16e91da | 4393 | struct mlx5_ib_qp *qp; |
e6631814 | 4394 | struct mlx5_ib_mr *mr; |
e126ba97 EC |
4395 | struct mlx5_wqe_data_seg *dpseg; |
4396 | struct mlx5_wqe_xrc_seg *xrc; | |
d16e91da | 4397 | struct mlx5_bf *bf; |
e126ba97 | 4398 | int uninitialized_var(size); |
d16e91da | 4399 | void *qend; |
e126ba97 | 4400 | unsigned long flags; |
e126ba97 EC |
4401 | unsigned idx; |
4402 | int err = 0; | |
e126ba97 EC |
4403 | int num_sge; |
4404 | void *seg; | |
4405 | int nreq; | |
4406 | int i; | |
4407 | u8 next_fence = 0; | |
e126ba97 EC |
4408 | u8 fence; |
4409 | ||
d16e91da HE |
4410 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
4411 | return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); | |
4412 | ||
4413 | qp = to_mqp(ibqp); | |
5fe9dec0 | 4414 | bf = &qp->bf; |
d16e91da HE |
4415 | qend = qp->sq.qend; |
4416 | ||
e126ba97 EC |
4417 | spin_lock_irqsave(&qp->sq.lock, flags); |
4418 | ||
d0e84c0a | 4419 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && !drain) { |
89ea94a7 MG |
4420 | err = -EIO; |
4421 | *bad_wr = wr; | |
4422 | nreq = 0; | |
4423 | goto out; | |
4424 | } | |
4425 | ||
e126ba97 | 4426 | for (nreq = 0; wr; nreq++, wr = wr->next) { |
a8f731eb | 4427 | if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { |
e126ba97 EC |
4428 | mlx5_ib_warn(dev, "\n"); |
4429 | err = -EINVAL; | |
4430 | *bad_wr = wr; | |
4431 | goto out; | |
4432 | } | |
4433 | ||
6e5eadac SG |
4434 | num_sge = wr->num_sge; |
4435 | if (unlikely(num_sge > qp->sq.max_gs)) { | |
e126ba97 | 4436 | mlx5_ib_warn(dev, "\n"); |
24be409b | 4437 | err = -EINVAL; |
e126ba97 EC |
4438 | *bad_wr = wr; |
4439 | goto out; | |
4440 | } | |
4441 | ||
6e5eadac SG |
4442 | err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq); |
4443 | if (err) { | |
e126ba97 EC |
4444 | mlx5_ib_warn(dev, "\n"); |
4445 | err = -ENOMEM; | |
4446 | *bad_wr = wr; | |
4447 | goto out; | |
4448 | } | |
4449 | ||
6e8484c5 MG |
4450 | if (wr->opcode == IB_WR_LOCAL_INV || |
4451 | wr->opcode == IB_WR_REG_MR) { | |
4452 | fence = dev->umr_fence; | |
4453 | next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | |
4454 | } else if (wr->send_flags & IB_SEND_FENCE) { | |
4455 | if (qp->next_fence) | |
4456 | fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; | |
4457 | else | |
4458 | fence = MLX5_FENCE_MODE_FENCE; | |
4459 | } else { | |
4460 | fence = qp->next_fence; | |
4461 | } | |
4462 | ||
e126ba97 EC |
4463 | switch (ibqp->qp_type) { |
4464 | case IB_QPT_XRC_INI: | |
4465 | xrc = seg; | |
e126ba97 EC |
4466 | seg += sizeof(*xrc); |
4467 | size += sizeof(*xrc) / 16; | |
4468 | /* fall through */ | |
4469 | case IB_QPT_RC: | |
4470 | switch (wr->opcode) { | |
4471 | case IB_WR_RDMA_READ: | |
4472 | case IB_WR_RDMA_WRITE: | |
4473 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
e622f2f4 CH |
4474 | set_raddr_seg(seg, rdma_wr(wr)->remote_addr, |
4475 | rdma_wr(wr)->rkey); | |
f241e749 | 4476 | seg += sizeof(struct mlx5_wqe_raddr_seg); |
e126ba97 EC |
4477 | size += sizeof(struct mlx5_wqe_raddr_seg) / 16; |
4478 | break; | |
4479 | ||
4480 | case IB_WR_ATOMIC_CMP_AND_SWP: | |
4481 | case IB_WR_ATOMIC_FETCH_AND_ADD: | |
e126ba97 | 4482 | case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: |
81bea28f EC |
4483 | mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); |
4484 | err = -ENOSYS; | |
4485 | *bad_wr = wr; | |
4486 | goto out; | |
e126ba97 EC |
4487 | |
4488 | case IB_WR_LOCAL_INV: | |
e126ba97 EC |
4489 | qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; |
4490 | ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); | |
dd01e66a | 4491 | set_linv_wr(qp, &seg, &size); |
e126ba97 EC |
4492 | num_sge = 0; |
4493 | break; | |
4494 | ||
8a187ee5 | 4495 | case IB_WR_REG_MR: |
8a187ee5 SG |
4496 | qp->sq.wr_data[idx] = IB_WR_REG_MR; |
4497 | ctrl->imm = cpu_to_be32(reg_wr(wr)->key); | |
4498 | err = set_reg_wr(qp, reg_wr(wr), &seg, &size); | |
4499 | if (err) { | |
4500 | *bad_wr = wr; | |
4501 | goto out; | |
4502 | } | |
4503 | num_sge = 0; | |
4504 | break; | |
4505 | ||
e6631814 SG |
4506 | case IB_WR_REG_SIG_MR: |
4507 | qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; | |
e622f2f4 | 4508 | mr = to_mmr(sig_handover_wr(wr)->sig_mr); |
e6631814 SG |
4509 | |
4510 | ctrl->imm = cpu_to_be32(mr->ibmr.rkey); | |
4511 | err = set_sig_umr_wr(wr, qp, &seg, &size); | |
4512 | if (err) { | |
4513 | mlx5_ib_warn(dev, "\n"); | |
4514 | *bad_wr = wr; | |
4515 | goto out; | |
4516 | } | |
4517 | ||
6e8484c5 MG |
4518 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, |
4519 | fence, MLX5_OPCODE_UMR); | |
e6631814 SG |
4520 | /* |
4521 | * SET_PSV WQEs are not signaled and solicited | |
4522 | * on error | |
4523 | */ | |
7bb1fafc BVA |
4524 | err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, |
4525 | &size, nreq, false, true); | |
e6631814 SG |
4526 | if (err) { |
4527 | mlx5_ib_warn(dev, "\n"); | |
4528 | err = -ENOMEM; | |
4529 | *bad_wr = wr; | |
4530 | goto out; | |
4531 | } | |
4532 | ||
e622f2f4 | 4533 | err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, |
e6631814 SG |
4534 | mr->sig->psv_memory.psv_idx, &seg, |
4535 | &size); | |
4536 | if (err) { | |
4537 | mlx5_ib_warn(dev, "\n"); | |
4538 | *bad_wr = wr; | |
4539 | goto out; | |
4540 | } | |
4541 | ||
6e8484c5 MG |
4542 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, |
4543 | fence, MLX5_OPCODE_SET_PSV); | |
7bb1fafc BVA |
4544 | err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, |
4545 | &size, nreq, false, true); | |
e6631814 SG |
4546 | if (err) { |
4547 | mlx5_ib_warn(dev, "\n"); | |
4548 | err = -ENOMEM; | |
4549 | *bad_wr = wr; | |
4550 | goto out; | |
4551 | } | |
4552 | ||
e622f2f4 | 4553 | err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, |
e6631814 SG |
4554 | mr->sig->psv_wire.psv_idx, &seg, |
4555 | &size); | |
4556 | if (err) { | |
4557 | mlx5_ib_warn(dev, "\n"); | |
4558 | *bad_wr = wr; | |
4559 | goto out; | |
4560 | } | |
4561 | ||
6e8484c5 MG |
4562 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, |
4563 | fence, MLX5_OPCODE_SET_PSV); | |
4564 | qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | |
e6631814 SG |
4565 | num_sge = 0; |
4566 | goto skip_psv; | |
4567 | ||
e126ba97 EC |
4568 | default: |
4569 | break; | |
4570 | } | |
4571 | break; | |
4572 | ||
4573 | case IB_QPT_UC: | |
4574 | switch (wr->opcode) { | |
4575 | case IB_WR_RDMA_WRITE: | |
4576 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
e622f2f4 CH |
4577 | set_raddr_seg(seg, rdma_wr(wr)->remote_addr, |
4578 | rdma_wr(wr)->rkey); | |
e126ba97 EC |
4579 | seg += sizeof(struct mlx5_wqe_raddr_seg); |
4580 | size += sizeof(struct mlx5_wqe_raddr_seg) / 16; | |
4581 | break; | |
4582 | ||
4583 | default: | |
4584 | break; | |
4585 | } | |
4586 | break; | |
4587 | ||
e126ba97 | 4588 | case IB_QPT_SMI: |
1e0e50b6 MG |
4589 | if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { |
4590 | mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); | |
4591 | err = -EPERM; | |
4592 | *bad_wr = wr; | |
4593 | goto out; | |
4594 | } | |
f6b1ee34 | 4595 | /* fall through */ |
d16e91da | 4596 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 | 4597 | set_datagram_seg(seg, wr); |
f241e749 | 4598 | seg += sizeof(struct mlx5_wqe_datagram_seg); |
e126ba97 EC |
4599 | size += sizeof(struct mlx5_wqe_datagram_seg) / 16; |
4600 | if (unlikely((seg == qend))) | |
4601 | seg = mlx5_get_send_wqe(qp, 0); | |
4602 | break; | |
f0313965 ES |
4603 | case IB_QPT_UD: |
4604 | set_datagram_seg(seg, wr); | |
4605 | seg += sizeof(struct mlx5_wqe_datagram_seg); | |
4606 | size += sizeof(struct mlx5_wqe_datagram_seg) / 16; | |
4607 | ||
4608 | if (unlikely((seg == qend))) | |
4609 | seg = mlx5_get_send_wqe(qp, 0); | |
4610 | ||
4611 | /* handle qp that supports ud offload */ | |
4612 | if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { | |
4613 | struct mlx5_wqe_eth_pad *pad; | |
e126ba97 | 4614 | |
f0313965 ES |
4615 | pad = seg; |
4616 | memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); | |
4617 | seg += sizeof(struct mlx5_wqe_eth_pad); | |
4618 | size += sizeof(struct mlx5_wqe_eth_pad) / 16; | |
4619 | ||
4620 | seg = set_eth_seg(seg, wr, qend, qp, &size); | |
4621 | ||
4622 | if (unlikely((seg == qend))) | |
4623 | seg = mlx5_get_send_wqe(qp, 0); | |
4624 | } | |
4625 | break; | |
e126ba97 EC |
4626 | case MLX5_IB_QPT_REG_UMR: |
4627 | if (wr->opcode != MLX5_IB_WR_UMR) { | |
4628 | err = -EINVAL; | |
4629 | mlx5_ib_warn(dev, "bad opcode\n"); | |
4630 | goto out; | |
4631 | } | |
4632 | qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; | |
e622f2f4 | 4633 | ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); |
c8d75a98 MD |
4634 | err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); |
4635 | if (unlikely(err)) | |
4636 | goto out; | |
e126ba97 EC |
4637 | seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4638 | size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
4639 | if (unlikely((seg == qend))) | |
4640 | seg = mlx5_get_send_wqe(qp, 0); | |
4641 | set_reg_mkey_segment(seg, wr); | |
4642 | seg += sizeof(struct mlx5_mkey_seg); | |
4643 | size += sizeof(struct mlx5_mkey_seg) / 16; | |
4644 | if (unlikely((seg == qend))) | |
4645 | seg = mlx5_get_send_wqe(qp, 0); | |
4646 | break; | |
4647 | ||
4648 | default: | |
4649 | break; | |
4650 | } | |
4651 | ||
4652 | if (wr->send_flags & IB_SEND_INLINE && num_sge) { | |
4653 | int uninitialized_var(sz); | |
4654 | ||
4655 | err = set_data_inl_seg(qp, wr, seg, &sz); | |
4656 | if (unlikely(err)) { | |
4657 | mlx5_ib_warn(dev, "\n"); | |
4658 | *bad_wr = wr; | |
4659 | goto out; | |
4660 | } | |
e126ba97 EC |
4661 | size += sz; |
4662 | } else { | |
4663 | dpseg = seg; | |
4664 | for (i = 0; i < num_sge; i++) { | |
4665 | if (unlikely(dpseg == qend)) { | |
4666 | seg = mlx5_get_send_wqe(qp, 0); | |
4667 | dpseg = seg; | |
4668 | } | |
4669 | if (likely(wr->sg_list[i].length)) { | |
4670 | set_data_ptr_seg(dpseg, wr->sg_list + i); | |
4671 | size += sizeof(struct mlx5_wqe_data_seg) / 16; | |
4672 | dpseg++; | |
4673 | } | |
4674 | } | |
4675 | } | |
4676 | ||
6e8484c5 MG |
4677 | qp->next_fence = next_fence; |
4678 | finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence, | |
6e5eadac | 4679 | mlx5_ib_opcode[wr->opcode]); |
e6631814 | 4680 | skip_psv: |
e126ba97 EC |
4681 | if (0) |
4682 | dump_wqe(qp, idx, size); | |
4683 | } | |
4684 | ||
4685 | out: | |
4686 | if (likely(nreq)) { | |
4687 | qp->sq.head += nreq; | |
4688 | ||
4689 | /* Make sure that descriptors are written before | |
4690 | * updating doorbell record and ringing the doorbell | |
4691 | */ | |
4692 | wmb(); | |
4693 | ||
4694 | qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); | |
4695 | ||
ada388f7 EC |
4696 | /* Make sure doorbell record is visible to the HCA before |
4697 | * we hit doorbell */ | |
4698 | wmb(); | |
4699 | ||
5fe9dec0 EC |
4700 | /* currently we support only regular doorbells */ |
4701 | mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); | |
4702 | /* Make sure doorbells don't leak out of SQ spinlock | |
4703 | * and reach the HCA out of order. | |
4704 | */ | |
4705 | mmiowb(); | |
e126ba97 | 4706 | bf->offset ^= bf->buf_size; |
e126ba97 EC |
4707 | } |
4708 | ||
4709 | spin_unlock_irqrestore(&qp->sq.lock, flags); | |
4710 | ||
4711 | return err; | |
4712 | } | |
4713 | ||
d34ac5cd BVA |
4714 | int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
4715 | const struct ib_send_wr **bad_wr) | |
d0e84c0a YH |
4716 | { |
4717 | return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); | |
4718 | } | |
4719 | ||
e126ba97 EC |
4720 | static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) |
4721 | { | |
4722 | sig->signature = calc_sig(sig, size); | |
4723 | } | |
4724 | ||
d34ac5cd BVA |
4725 | static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, |
4726 | const struct ib_recv_wr **bad_wr, bool drain) | |
e126ba97 EC |
4727 | { |
4728 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
4729 | struct mlx5_wqe_data_seg *scat; | |
4730 | struct mlx5_rwqe_sig *sig; | |
89ea94a7 MG |
4731 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); |
4732 | struct mlx5_core_dev *mdev = dev->mdev; | |
e126ba97 EC |
4733 | unsigned long flags; |
4734 | int err = 0; | |
4735 | int nreq; | |
4736 | int ind; | |
4737 | int i; | |
4738 | ||
d16e91da HE |
4739 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
4740 | return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); | |
4741 | ||
e126ba97 EC |
4742 | spin_lock_irqsave(&qp->rq.lock, flags); |
4743 | ||
d0e84c0a | 4744 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && !drain) { |
89ea94a7 MG |
4745 | err = -EIO; |
4746 | *bad_wr = wr; | |
4747 | nreq = 0; | |
4748 | goto out; | |
4749 | } | |
4750 | ||
e126ba97 EC |
4751 | ind = qp->rq.head & (qp->rq.wqe_cnt - 1); |
4752 | ||
4753 | for (nreq = 0; wr; nreq++, wr = wr->next) { | |
4754 | if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { | |
4755 | err = -ENOMEM; | |
4756 | *bad_wr = wr; | |
4757 | goto out; | |
4758 | } | |
4759 | ||
4760 | if (unlikely(wr->num_sge > qp->rq.max_gs)) { | |
4761 | err = -EINVAL; | |
4762 | *bad_wr = wr; | |
4763 | goto out; | |
4764 | } | |
4765 | ||
4766 | scat = get_recv_wqe(qp, ind); | |
4767 | if (qp->wq_sig) | |
4768 | scat++; | |
4769 | ||
4770 | for (i = 0; i < wr->num_sge; i++) | |
4771 | set_data_ptr_seg(scat + i, wr->sg_list + i); | |
4772 | ||
4773 | if (i < qp->rq.max_gs) { | |
4774 | scat[i].byte_count = 0; | |
4775 | scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); | |
4776 | scat[i].addr = 0; | |
4777 | } | |
4778 | ||
4779 | if (qp->wq_sig) { | |
4780 | sig = (struct mlx5_rwqe_sig *)scat; | |
4781 | set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); | |
4782 | } | |
4783 | ||
4784 | qp->rq.wrid[ind] = wr->wr_id; | |
4785 | ||
4786 | ind = (ind + 1) & (qp->rq.wqe_cnt - 1); | |
4787 | } | |
4788 | ||
4789 | out: | |
4790 | if (likely(nreq)) { | |
4791 | qp->rq.head += nreq; | |
4792 | ||
4793 | /* Make sure that descriptors are written before | |
4794 | * doorbell record. | |
4795 | */ | |
4796 | wmb(); | |
4797 | ||
4798 | *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); | |
4799 | } | |
4800 | ||
4801 | spin_unlock_irqrestore(&qp->rq.lock, flags); | |
4802 | ||
4803 | return err; | |
4804 | } | |
4805 | ||
d34ac5cd BVA |
4806 | int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, |
4807 | const struct ib_recv_wr **bad_wr) | |
d0e84c0a YH |
4808 | { |
4809 | return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); | |
4810 | } | |
4811 | ||
e126ba97 EC |
4812 | static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) |
4813 | { | |
4814 | switch (mlx5_state) { | |
4815 | case MLX5_QP_STATE_RST: return IB_QPS_RESET; | |
4816 | case MLX5_QP_STATE_INIT: return IB_QPS_INIT; | |
4817 | case MLX5_QP_STATE_RTR: return IB_QPS_RTR; | |
4818 | case MLX5_QP_STATE_RTS: return IB_QPS_RTS; | |
4819 | case MLX5_QP_STATE_SQ_DRAINING: | |
4820 | case MLX5_QP_STATE_SQD: return IB_QPS_SQD; | |
4821 | case MLX5_QP_STATE_SQER: return IB_QPS_SQE; | |
4822 | case MLX5_QP_STATE_ERR: return IB_QPS_ERR; | |
4823 | default: return -1; | |
4824 | } | |
4825 | } | |
4826 | ||
4827 | static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) | |
4828 | { | |
4829 | switch (mlx5_mig_state) { | |
4830 | case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; | |
4831 | case MLX5_QP_PM_REARM: return IB_MIG_REARM; | |
4832 | case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; | |
4833 | default: return -1; | |
4834 | } | |
4835 | } | |
4836 | ||
4837 | static int to_ib_qp_access_flags(int mlx5_flags) | |
4838 | { | |
4839 | int ib_flags = 0; | |
4840 | ||
4841 | if (mlx5_flags & MLX5_QP_BIT_RRE) | |
4842 | ib_flags |= IB_ACCESS_REMOTE_READ; | |
4843 | if (mlx5_flags & MLX5_QP_BIT_RWE) | |
4844 | ib_flags |= IB_ACCESS_REMOTE_WRITE; | |
4845 | if (mlx5_flags & MLX5_QP_BIT_RAE) | |
4846 | ib_flags |= IB_ACCESS_REMOTE_ATOMIC; | |
4847 | ||
4848 | return ib_flags; | |
4849 | } | |
4850 | ||
38349389 | 4851 | static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, |
d8966fcd | 4852 | struct rdma_ah_attr *ah_attr, |
38349389 | 4853 | struct mlx5_qp_path *path) |
e126ba97 | 4854 | { |
e126ba97 | 4855 | |
d8966fcd | 4856 | memset(ah_attr, 0, sizeof(*ah_attr)); |
e126ba97 | 4857 | |
e7996a9a | 4858 | if (!path->port || path->port > ibdev->num_ports) |
e126ba97 EC |
4859 | return; |
4860 | ||
ae59c3f0 LR |
4861 | ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); |
4862 | ||
d8966fcd DC |
4863 | rdma_ah_set_port_num(ah_attr, path->port); |
4864 | rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); | |
4865 | ||
4866 | rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); | |
4867 | rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); | |
4868 | rdma_ah_set_static_rate(ah_attr, | |
4869 | path->static_rate ? path->static_rate - 5 : 0); | |
4870 | if (path->grh_mlid & (1 << 7)) { | |
4871 | u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); | |
4872 | ||
4873 | rdma_ah_set_grh(ah_attr, NULL, | |
4874 | tc_fl & 0xfffff, | |
4875 | path->mgid_index, | |
4876 | path->hop_limit, | |
4877 | (tc_fl >> 20) & 0xff); | |
4878 | rdma_ah_set_dgid_raw(ah_attr, path->rgid); | |
e126ba97 EC |
4879 | } |
4880 | } | |
4881 | ||
6d2f89df | 4882 | static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, |
4883 | struct mlx5_ib_sq *sq, | |
4884 | u8 *sq_state) | |
4885 | { | |
6d2f89df | 4886 | int err; |
4887 | ||
28160771 | 4888 | err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); |
6d2f89df | 4889 | if (err) |
4890 | goto out; | |
6d2f89df | 4891 | sq->state = *sq_state; |
4892 | ||
4893 | out: | |
6d2f89df | 4894 | return err; |
4895 | } | |
4896 | ||
4897 | static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, | |
4898 | struct mlx5_ib_rq *rq, | |
4899 | u8 *rq_state) | |
4900 | { | |
4901 | void *out; | |
4902 | void *rqc; | |
4903 | int inlen; | |
4904 | int err; | |
4905 | ||
4906 | inlen = MLX5_ST_SZ_BYTES(query_rq_out); | |
1b9a07ee | 4907 | out = kvzalloc(inlen, GFP_KERNEL); |
6d2f89df | 4908 | if (!out) |
4909 | return -ENOMEM; | |
4910 | ||
4911 | err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); | |
4912 | if (err) | |
4913 | goto out; | |
4914 | ||
4915 | rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); | |
4916 | *rq_state = MLX5_GET(rqc, rqc, state); | |
4917 | rq->state = *rq_state; | |
4918 | ||
4919 | out: | |
4920 | kvfree(out); | |
4921 | return err; | |
4922 | } | |
4923 | ||
4924 | static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, | |
4925 | struct mlx5_ib_qp *qp, u8 *qp_state) | |
4926 | { | |
4927 | static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { | |
4928 | [MLX5_RQC_STATE_RST] = { | |
4929 | [MLX5_SQC_STATE_RST] = IB_QPS_RESET, | |
4930 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, | |
4931 | [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, | |
4932 | [MLX5_SQ_STATE_NA] = IB_QPS_RESET, | |
4933 | }, | |
4934 | [MLX5_RQC_STATE_RDY] = { | |
4935 | [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, | |
4936 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, | |
4937 | [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, | |
4938 | [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, | |
4939 | }, | |
4940 | [MLX5_RQC_STATE_ERR] = { | |
4941 | [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, | |
4942 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, | |
4943 | [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, | |
4944 | [MLX5_SQ_STATE_NA] = IB_QPS_ERR, | |
4945 | }, | |
4946 | [MLX5_RQ_STATE_NA] = { | |
4947 | [MLX5_SQC_STATE_RST] = IB_QPS_RESET, | |
4948 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, | |
4949 | [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, | |
4950 | [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, | |
4951 | }, | |
4952 | }; | |
4953 | ||
4954 | *qp_state = sqrq_trans[rq_state][sq_state]; | |
4955 | ||
4956 | if (*qp_state == MLX5_QP_STATE_BAD) { | |
4957 | WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", | |
4958 | qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, | |
4959 | qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); | |
4960 | return -EINVAL; | |
4961 | } | |
4962 | ||
4963 | if (*qp_state == MLX5_QP_STATE) | |
4964 | *qp_state = qp->state; | |
4965 | ||
4966 | return 0; | |
4967 | } | |
4968 | ||
4969 | static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, | |
4970 | struct mlx5_ib_qp *qp, | |
4971 | u8 *raw_packet_qp_state) | |
4972 | { | |
4973 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
4974 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
4975 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
4976 | int err; | |
4977 | u8 sq_state = MLX5_SQ_STATE_NA; | |
4978 | u8 rq_state = MLX5_RQ_STATE_NA; | |
4979 | ||
4980 | if (qp->sq.wqe_cnt) { | |
4981 | err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); | |
4982 | if (err) | |
4983 | return err; | |
4984 | } | |
4985 | ||
4986 | if (qp->rq.wqe_cnt) { | |
4987 | err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); | |
4988 | if (err) | |
4989 | return err; | |
4990 | } | |
4991 | ||
4992 | return sqrq_state_to_qp_state(sq_state, rq_state, qp, | |
4993 | raw_packet_qp_state); | |
4994 | } | |
4995 | ||
4996 | static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
4997 | struct ib_qp_attr *qp_attr) | |
e126ba97 | 4998 | { |
09a7d9ec | 4999 | int outlen = MLX5_ST_SZ_BYTES(query_qp_out); |
e126ba97 EC |
5000 | struct mlx5_qp_context *context; |
5001 | int mlx5_state; | |
09a7d9ec | 5002 | u32 *outb; |
e126ba97 EC |
5003 | int err = 0; |
5004 | ||
09a7d9ec | 5005 | outb = kzalloc(outlen, GFP_KERNEL); |
6d2f89df | 5006 | if (!outb) |
5007 | return -ENOMEM; | |
5008 | ||
19098df2 | 5009 | err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, |
09a7d9ec | 5010 | outlen); |
e126ba97 | 5011 | if (err) |
6d2f89df | 5012 | goto out; |
e126ba97 | 5013 | |
09a7d9ec SM |
5014 | /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ |
5015 | context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); | |
5016 | ||
e126ba97 EC |
5017 | mlx5_state = be32_to_cpu(context->flags) >> 28; |
5018 | ||
5019 | qp->state = to_ib_qp_state(mlx5_state); | |
e126ba97 EC |
5020 | qp_attr->path_mtu = context->mtu_msgmax >> 5; |
5021 | qp_attr->path_mig_state = | |
5022 | to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); | |
5023 | qp_attr->qkey = be32_to_cpu(context->qkey); | |
5024 | qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; | |
5025 | qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; | |
5026 | qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; | |
5027 | qp_attr->qp_access_flags = | |
5028 | to_ib_qp_access_flags(be32_to_cpu(context->params2)); | |
5029 | ||
5030 | if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { | |
38349389 DC |
5031 | to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); |
5032 | to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); | |
d3ae2bde NO |
5033 | qp_attr->alt_pkey_index = |
5034 | be16_to_cpu(context->alt_path.pkey_index); | |
d8966fcd DC |
5035 | qp_attr->alt_port_num = |
5036 | rdma_ah_get_port_num(&qp_attr->alt_ah_attr); | |
e126ba97 EC |
5037 | } |
5038 | ||
d3ae2bde | 5039 | qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); |
e126ba97 EC |
5040 | qp_attr->port_num = context->pri_path.port; |
5041 | ||
5042 | /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ | |
5043 | qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; | |
5044 | ||
5045 | qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); | |
5046 | ||
5047 | qp_attr->max_dest_rd_atomic = | |
5048 | 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); | |
5049 | qp_attr->min_rnr_timer = | |
5050 | (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; | |
5051 | qp_attr->timeout = context->pri_path.ackto_lt >> 3; | |
5052 | qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; | |
5053 | qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; | |
5054 | qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; | |
6d2f89df | 5055 | |
5056 | out: | |
5057 | kfree(outb); | |
5058 | return err; | |
5059 | } | |
5060 | ||
776a3906 MS |
5061 | static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, |
5062 | struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
5063 | struct ib_qp_init_attr *qp_init_attr) | |
5064 | { | |
5065 | struct mlx5_core_dct *dct = &mqp->dct.mdct; | |
5066 | u32 *out; | |
5067 | u32 access_flags = 0; | |
5068 | int outlen = MLX5_ST_SZ_BYTES(query_dct_out); | |
5069 | void *dctc; | |
5070 | int err; | |
5071 | int supported_mask = IB_QP_STATE | | |
5072 | IB_QP_ACCESS_FLAGS | | |
5073 | IB_QP_PORT | | |
5074 | IB_QP_MIN_RNR_TIMER | | |
5075 | IB_QP_AV | | |
5076 | IB_QP_PATH_MTU | | |
5077 | IB_QP_PKEY_INDEX; | |
5078 | ||
5079 | if (qp_attr_mask & ~supported_mask) | |
5080 | return -EINVAL; | |
5081 | if (mqp->state != IB_QPS_RTR) | |
5082 | return -EINVAL; | |
5083 | ||
5084 | out = kzalloc(outlen, GFP_KERNEL); | |
5085 | if (!out) | |
5086 | return -ENOMEM; | |
5087 | ||
5088 | err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); | |
5089 | if (err) | |
5090 | goto out; | |
5091 | ||
5092 | dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); | |
5093 | ||
5094 | if (qp_attr_mask & IB_QP_STATE) | |
5095 | qp_attr->qp_state = IB_QPS_RTR; | |
5096 | ||
5097 | if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { | |
5098 | if (MLX5_GET(dctc, dctc, rre)) | |
5099 | access_flags |= IB_ACCESS_REMOTE_READ; | |
5100 | if (MLX5_GET(dctc, dctc, rwe)) | |
5101 | access_flags |= IB_ACCESS_REMOTE_WRITE; | |
5102 | if (MLX5_GET(dctc, dctc, rae)) | |
5103 | access_flags |= IB_ACCESS_REMOTE_ATOMIC; | |
5104 | qp_attr->qp_access_flags = access_flags; | |
5105 | } | |
5106 | ||
5107 | if (qp_attr_mask & IB_QP_PORT) | |
5108 | qp_attr->port_num = MLX5_GET(dctc, dctc, port); | |
5109 | if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) | |
5110 | qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); | |
5111 | if (qp_attr_mask & IB_QP_AV) { | |
5112 | qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); | |
5113 | qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); | |
5114 | qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); | |
5115 | qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); | |
5116 | } | |
5117 | if (qp_attr_mask & IB_QP_PATH_MTU) | |
5118 | qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); | |
5119 | if (qp_attr_mask & IB_QP_PKEY_INDEX) | |
5120 | qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); | |
5121 | out: | |
5122 | kfree(out); | |
5123 | return err; | |
5124 | } | |
5125 | ||
6d2f89df | 5126 | int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, |
5127 | int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) | |
5128 | { | |
5129 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
5130 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
5131 | int err = 0; | |
5132 | u8 raw_packet_qp_state; | |
5133 | ||
28d61370 YH |
5134 | if (ibqp->rwq_ind_tbl) |
5135 | return -ENOSYS; | |
5136 | ||
d16e91da HE |
5137 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
5138 | return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, | |
5139 | qp_init_attr); | |
5140 | ||
c2e53b2c YH |
5141 | /* Not all of output fields are applicable, make sure to zero them */ |
5142 | memset(qp_init_attr, 0, sizeof(*qp_init_attr)); | |
5143 | memset(qp_attr, 0, sizeof(*qp_attr)); | |
5144 | ||
776a3906 MS |
5145 | if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) |
5146 | return mlx5_ib_dct_query_qp(dev, qp, qp_attr, | |
5147 | qp_attr_mask, qp_init_attr); | |
5148 | ||
6d2f89df | 5149 | mutex_lock(&qp->mutex); |
5150 | ||
c2e53b2c YH |
5151 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
5152 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
6d2f89df | 5153 | err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); |
5154 | if (err) | |
5155 | goto out; | |
5156 | qp->state = raw_packet_qp_state; | |
5157 | qp_attr->port_num = 1; | |
5158 | } else { | |
5159 | err = query_qp_attr(dev, qp, qp_attr); | |
5160 | if (err) | |
5161 | goto out; | |
5162 | } | |
5163 | ||
5164 | qp_attr->qp_state = qp->state; | |
e126ba97 EC |
5165 | qp_attr->cur_qp_state = qp_attr->qp_state; |
5166 | qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; | |
5167 | qp_attr->cap.max_recv_sge = qp->rq.max_gs; | |
5168 | ||
5169 | if (!ibqp->uobject) { | |
0540d814 | 5170 | qp_attr->cap.max_send_wr = qp->sq.max_post; |
e126ba97 | 5171 | qp_attr->cap.max_send_sge = qp->sq.max_gs; |
0540d814 | 5172 | qp_init_attr->qp_context = ibqp->qp_context; |
e126ba97 EC |
5173 | } else { |
5174 | qp_attr->cap.max_send_wr = 0; | |
5175 | qp_attr->cap.max_send_sge = 0; | |
5176 | } | |
5177 | ||
0540d814 NO |
5178 | qp_init_attr->qp_type = ibqp->qp_type; |
5179 | qp_init_attr->recv_cq = ibqp->recv_cq; | |
5180 | qp_init_attr->send_cq = ibqp->send_cq; | |
5181 | qp_init_attr->srq = ibqp->srq; | |
5182 | qp_attr->cap.max_inline_data = qp->max_inline_data; | |
e126ba97 EC |
5183 | |
5184 | qp_init_attr->cap = qp_attr->cap; | |
5185 | ||
5186 | qp_init_attr->create_flags = 0; | |
5187 | if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) | |
5188 | qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; | |
5189 | ||
051f2630 LR |
5190 | if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) |
5191 | qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; | |
5192 | if (qp->flags & MLX5_IB_QP_MANAGED_SEND) | |
5193 | qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; | |
5194 | if (qp->flags & MLX5_IB_QP_MANAGED_RECV) | |
5195 | qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; | |
b11a4f9c HE |
5196 | if (qp->flags & MLX5_IB_QP_SQPN_QP1) |
5197 | qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); | |
051f2630 | 5198 | |
e126ba97 EC |
5199 | qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? |
5200 | IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; | |
5201 | ||
e126ba97 EC |
5202 | out: |
5203 | mutex_unlock(&qp->mutex); | |
5204 | return err; | |
5205 | } | |
5206 | ||
5207 | struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, | |
5208 | struct ib_ucontext *context, | |
5209 | struct ib_udata *udata) | |
5210 | { | |
5211 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
5212 | struct mlx5_ib_xrcd *xrcd; | |
5213 | int err; | |
5214 | ||
938fe83c | 5215 | if (!MLX5_CAP_GEN(dev->mdev, xrc)) |
e126ba97 EC |
5216 | return ERR_PTR(-ENOSYS); |
5217 | ||
5218 | xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); | |
5219 | if (!xrcd) | |
5220 | return ERR_PTR(-ENOMEM); | |
5221 | ||
9603b61d | 5222 | err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); |
e126ba97 EC |
5223 | if (err) { |
5224 | kfree(xrcd); | |
5225 | return ERR_PTR(-ENOMEM); | |
5226 | } | |
5227 | ||
5228 | return &xrcd->ibxrcd; | |
5229 | } | |
5230 | ||
5231 | int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) | |
5232 | { | |
5233 | struct mlx5_ib_dev *dev = to_mdev(xrcd->device); | |
5234 | u32 xrcdn = to_mxrcd(xrcd)->xrcdn; | |
5235 | int err; | |
5236 | ||
9603b61d | 5237 | err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); |
b081808a | 5238 | if (err) |
e126ba97 | 5239 | mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); |
e126ba97 EC |
5240 | |
5241 | kfree(xrcd); | |
e126ba97 EC |
5242 | return 0; |
5243 | } | |
79b20a6c | 5244 | |
350d0e4c YH |
5245 | static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) |
5246 | { | |
5247 | struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); | |
5248 | struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); | |
5249 | struct ib_event event; | |
5250 | ||
5251 | if (rwq->ibwq.event_handler) { | |
5252 | event.device = rwq->ibwq.device; | |
5253 | event.element.wq = &rwq->ibwq; | |
5254 | switch (type) { | |
5255 | case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: | |
5256 | event.event = IB_EVENT_WQ_FATAL; | |
5257 | break; | |
5258 | default: | |
5259 | mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); | |
5260 | return; | |
5261 | } | |
5262 | ||
5263 | rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); | |
5264 | } | |
5265 | } | |
5266 | ||
03404e8a MG |
5267 | static int set_delay_drop(struct mlx5_ib_dev *dev) |
5268 | { | |
5269 | int err = 0; | |
5270 | ||
5271 | mutex_lock(&dev->delay_drop.lock); | |
5272 | if (dev->delay_drop.activate) | |
5273 | goto out; | |
5274 | ||
5275 | err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); | |
5276 | if (err) | |
5277 | goto out; | |
5278 | ||
5279 | dev->delay_drop.activate = true; | |
5280 | out: | |
5281 | mutex_unlock(&dev->delay_drop.lock); | |
fe248c3a MG |
5282 | |
5283 | if (!err) | |
5284 | atomic_inc(&dev->delay_drop.rqs_cnt); | |
03404e8a MG |
5285 | return err; |
5286 | } | |
5287 | ||
79b20a6c YH |
5288 | static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, |
5289 | struct ib_wq_init_attr *init_attr) | |
5290 | { | |
5291 | struct mlx5_ib_dev *dev; | |
4be6da1e | 5292 | int has_net_offloads; |
79b20a6c YH |
5293 | __be64 *rq_pas0; |
5294 | void *in; | |
5295 | void *rqc; | |
5296 | void *wq; | |
5297 | int inlen; | |
5298 | int err; | |
5299 | ||
5300 | dev = to_mdev(pd->device); | |
5301 | ||
5302 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; | |
1b9a07ee | 5303 | in = kvzalloc(inlen, GFP_KERNEL); |
79b20a6c YH |
5304 | if (!in) |
5305 | return -ENOMEM; | |
5306 | ||
5307 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
5308 | MLX5_SET(rqc, rqc, mem_rq_type, | |
5309 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); | |
5310 | MLX5_SET(rqc, rqc, user_index, rwq->user_index); | |
5311 | MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); | |
5312 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); | |
5313 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
5314 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
ccc87087 NO |
5315 | MLX5_SET(wq, wq, wq_type, |
5316 | rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? | |
5317 | MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); | |
b1383aa6 NO |
5318 | if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { |
5319 | if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { | |
5320 | mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); | |
5321 | err = -EOPNOTSUPP; | |
5322 | goto out; | |
5323 | } else { | |
5324 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
5325 | } | |
5326 | } | |
79b20a6c | 5327 | MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); |
ccc87087 NO |
5328 | if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { |
5329 | MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); | |
5330 | MLX5_SET(wq, wq, log_wqe_stride_size, | |
5331 | rwq->single_stride_log_num_of_bytes - | |
5332 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); | |
5333 | MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - | |
5334 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); | |
5335 | } | |
79b20a6c YH |
5336 | MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); |
5337 | MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); | |
5338 | MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); | |
5339 | MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); | |
5340 | MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); | |
5341 | MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); | |
4be6da1e | 5342 | has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); |
b1f74a84 | 5343 | if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { |
4be6da1e | 5344 | if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { |
b1f74a84 NO |
5345 | mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); |
5346 | err = -EOPNOTSUPP; | |
5347 | goto out; | |
5348 | } | |
5349 | } else { | |
5350 | MLX5_SET(rqc, rqc, vsd, 1); | |
5351 | } | |
4be6da1e NO |
5352 | if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { |
5353 | if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { | |
5354 | mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); | |
5355 | err = -EOPNOTSUPP; | |
5356 | goto out; | |
5357 | } | |
5358 | MLX5_SET(rqc, rqc, scatter_fcs, 1); | |
5359 | } | |
03404e8a MG |
5360 | if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { |
5361 | if (!(dev->ib_dev.attrs.raw_packet_caps & | |
5362 | IB_RAW_PACKET_CAP_DELAY_DROP)) { | |
5363 | mlx5_ib_dbg(dev, "Delay drop is not supported\n"); | |
5364 | err = -EOPNOTSUPP; | |
5365 | goto out; | |
5366 | } | |
5367 | MLX5_SET(rqc, rqc, delay_drop_en, 1); | |
5368 | } | |
79b20a6c YH |
5369 | rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); |
5370 | mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); | |
350d0e4c | 5371 | err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); |
03404e8a MG |
5372 | if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { |
5373 | err = set_delay_drop(dev); | |
5374 | if (err) { | |
5375 | mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", | |
5376 | err); | |
5377 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); | |
5378 | } else { | |
5379 | rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; | |
5380 | } | |
5381 | } | |
b1f74a84 | 5382 | out: |
79b20a6c YH |
5383 | kvfree(in); |
5384 | return err; | |
5385 | } | |
5386 | ||
5387 | static int set_user_rq_size(struct mlx5_ib_dev *dev, | |
5388 | struct ib_wq_init_attr *wq_init_attr, | |
5389 | struct mlx5_ib_create_wq *ucmd, | |
5390 | struct mlx5_ib_rwq *rwq) | |
5391 | { | |
5392 | /* Sanity check RQ size before proceeding */ | |
5393 | if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) | |
5394 | return -EINVAL; | |
5395 | ||
5396 | if (!ucmd->rq_wqe_count) | |
5397 | return -EINVAL; | |
5398 | ||
5399 | rwq->wqe_count = ucmd->rq_wqe_count; | |
5400 | rwq->wqe_shift = ucmd->rq_wqe_shift; | |
0dfe4522 LR |
5401 | if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) |
5402 | return -EINVAL; | |
5403 | ||
79b20a6c YH |
5404 | rwq->log_rq_stride = rwq->wqe_shift; |
5405 | rwq->log_rq_size = ilog2(rwq->wqe_count); | |
5406 | return 0; | |
5407 | } | |
5408 | ||
5409 | static int prepare_user_rq(struct ib_pd *pd, | |
5410 | struct ib_wq_init_attr *init_attr, | |
5411 | struct ib_udata *udata, | |
5412 | struct mlx5_ib_rwq *rwq) | |
5413 | { | |
5414 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
5415 | struct mlx5_ib_create_wq ucmd = {}; | |
5416 | int err; | |
5417 | size_t required_cmd_sz; | |
5418 | ||
ccc87087 NO |
5419 | required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) |
5420 | + sizeof(ucmd.single_stride_log_num_of_bytes); | |
79b20a6c YH |
5421 | if (udata->inlen < required_cmd_sz) { |
5422 | mlx5_ib_dbg(dev, "invalid inlen\n"); | |
5423 | return -EINVAL; | |
5424 | } | |
5425 | ||
5426 | if (udata->inlen > sizeof(ucmd) && | |
5427 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
5428 | udata->inlen - sizeof(ucmd))) { | |
5429 | mlx5_ib_dbg(dev, "inlen is not supported\n"); | |
5430 | return -EOPNOTSUPP; | |
5431 | } | |
5432 | ||
5433 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { | |
5434 | mlx5_ib_dbg(dev, "copy failed\n"); | |
5435 | return -EFAULT; | |
5436 | } | |
5437 | ||
ccc87087 | 5438 | if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { |
79b20a6c YH |
5439 | mlx5_ib_dbg(dev, "invalid comp mask\n"); |
5440 | return -EOPNOTSUPP; | |
ccc87087 NO |
5441 | } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { |
5442 | if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { | |
5443 | mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); | |
5444 | return -EOPNOTSUPP; | |
5445 | } | |
5446 | if ((ucmd.single_stride_log_num_of_bytes < | |
5447 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || | |
5448 | (ucmd.single_stride_log_num_of_bytes > | |
5449 | MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { | |
5450 | mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", | |
5451 | ucmd.single_stride_log_num_of_bytes, | |
5452 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, | |
5453 | MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); | |
5454 | return -EINVAL; | |
5455 | } | |
5456 | if ((ucmd.single_wqe_log_num_of_strides > | |
5457 | MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || | |
5458 | (ucmd.single_wqe_log_num_of_strides < | |
5459 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { | |
5460 | mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", | |
5461 | ucmd.single_wqe_log_num_of_strides, | |
5462 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, | |
5463 | MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); | |
5464 | return -EINVAL; | |
5465 | } | |
5466 | rwq->single_stride_log_num_of_bytes = | |
5467 | ucmd.single_stride_log_num_of_bytes; | |
5468 | rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; | |
5469 | rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; | |
5470 | rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; | |
79b20a6c YH |
5471 | } |
5472 | ||
5473 | err = set_user_rq_size(dev, init_attr, &ucmd, rwq); | |
5474 | if (err) { | |
5475 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5476 | return err; | |
5477 | } | |
5478 | ||
5479 | err = create_user_rq(dev, pd, rwq, &ucmd); | |
5480 | if (err) { | |
5481 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5482 | if (err) | |
5483 | return err; | |
5484 | } | |
5485 | ||
5486 | rwq->user_index = ucmd.user_index; | |
5487 | return 0; | |
5488 | } | |
5489 | ||
5490 | struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, | |
5491 | struct ib_wq_init_attr *init_attr, | |
5492 | struct ib_udata *udata) | |
5493 | { | |
5494 | struct mlx5_ib_dev *dev; | |
5495 | struct mlx5_ib_rwq *rwq; | |
5496 | struct mlx5_ib_create_wq_resp resp = {}; | |
5497 | size_t min_resp_len; | |
5498 | int err; | |
5499 | ||
5500 | if (!udata) | |
5501 | return ERR_PTR(-ENOSYS); | |
5502 | ||
5503 | min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); | |
5504 | if (udata->outlen && udata->outlen < min_resp_len) | |
5505 | return ERR_PTR(-EINVAL); | |
5506 | ||
5507 | dev = to_mdev(pd->device); | |
5508 | switch (init_attr->wq_type) { | |
5509 | case IB_WQT_RQ: | |
5510 | rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); | |
5511 | if (!rwq) | |
5512 | return ERR_PTR(-ENOMEM); | |
5513 | err = prepare_user_rq(pd, init_attr, udata, rwq); | |
5514 | if (err) | |
5515 | goto err; | |
5516 | err = create_rq(rwq, pd, init_attr); | |
5517 | if (err) | |
5518 | goto err_user_rq; | |
5519 | break; | |
5520 | default: | |
5521 | mlx5_ib_dbg(dev, "unsupported wq type %d\n", | |
5522 | init_attr->wq_type); | |
5523 | return ERR_PTR(-EINVAL); | |
5524 | } | |
5525 | ||
350d0e4c | 5526 | rwq->ibwq.wq_num = rwq->core_qp.qpn; |
79b20a6c YH |
5527 | rwq->ibwq.state = IB_WQS_RESET; |
5528 | if (udata->outlen) { | |
5529 | resp.response_length = offsetof(typeof(resp), response_length) + | |
5530 | sizeof(resp.response_length); | |
5531 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
5532 | if (err) | |
5533 | goto err_copy; | |
5534 | } | |
5535 | ||
350d0e4c YH |
5536 | rwq->core_qp.event = mlx5_ib_wq_event; |
5537 | rwq->ibwq.event_handler = init_attr->event_handler; | |
79b20a6c YH |
5538 | return &rwq->ibwq; |
5539 | ||
5540 | err_copy: | |
350d0e4c | 5541 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); |
79b20a6c | 5542 | err_user_rq: |
fe248c3a | 5543 | destroy_user_rq(dev, pd, rwq); |
79b20a6c YH |
5544 | err: |
5545 | kfree(rwq); | |
5546 | return ERR_PTR(err); | |
5547 | } | |
5548 | ||
5549 | int mlx5_ib_destroy_wq(struct ib_wq *wq) | |
5550 | { | |
5551 | struct mlx5_ib_dev *dev = to_mdev(wq->device); | |
5552 | struct mlx5_ib_rwq *rwq = to_mrwq(wq); | |
5553 | ||
350d0e4c | 5554 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); |
fe248c3a | 5555 | destroy_user_rq(dev, wq->pd, rwq); |
79b20a6c YH |
5556 | kfree(rwq); |
5557 | ||
5558 | return 0; | |
5559 | } | |
5560 | ||
c5f90929 YH |
5561 | struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, |
5562 | struct ib_rwq_ind_table_init_attr *init_attr, | |
5563 | struct ib_udata *udata) | |
5564 | { | |
5565 | struct mlx5_ib_dev *dev = to_mdev(device); | |
5566 | struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; | |
5567 | int sz = 1 << init_attr->log_ind_tbl_size; | |
5568 | struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; | |
5569 | size_t min_resp_len; | |
5570 | int inlen; | |
5571 | int err; | |
5572 | int i; | |
5573 | u32 *in; | |
5574 | void *rqtc; | |
5575 | ||
5576 | if (udata->inlen > 0 && | |
5577 | !ib_is_udata_cleared(udata, 0, | |
5578 | udata->inlen)) | |
5579 | return ERR_PTR(-EOPNOTSUPP); | |
5580 | ||
efd7f400 MG |
5581 | if (init_attr->log_ind_tbl_size > |
5582 | MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { | |
5583 | mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", | |
5584 | init_attr->log_ind_tbl_size, | |
5585 | MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); | |
5586 | return ERR_PTR(-EINVAL); | |
5587 | } | |
5588 | ||
c5f90929 YH |
5589 | min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); |
5590 | if (udata->outlen && udata->outlen < min_resp_len) | |
5591 | return ERR_PTR(-EINVAL); | |
5592 | ||
5593 | rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); | |
5594 | if (!rwq_ind_tbl) | |
5595 | return ERR_PTR(-ENOMEM); | |
5596 | ||
5597 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; | |
1b9a07ee | 5598 | in = kvzalloc(inlen, GFP_KERNEL); |
c5f90929 YH |
5599 | if (!in) { |
5600 | err = -ENOMEM; | |
5601 | goto err; | |
5602 | } | |
5603 | ||
5604 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
5605 | ||
5606 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
5607 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
5608 | ||
5609 | for (i = 0; i < sz; i++) | |
5610 | MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); | |
5611 | ||
5612 | err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); | |
5613 | kvfree(in); | |
5614 | ||
5615 | if (err) | |
5616 | goto err; | |
5617 | ||
5618 | rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; | |
5619 | if (udata->outlen) { | |
5620 | resp.response_length = offsetof(typeof(resp), response_length) + | |
5621 | sizeof(resp.response_length); | |
5622 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
5623 | if (err) | |
5624 | goto err_copy; | |
5625 | } | |
5626 | ||
5627 | return &rwq_ind_tbl->ib_rwq_ind_tbl; | |
5628 | ||
5629 | err_copy: | |
5630 | mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); | |
5631 | err: | |
5632 | kfree(rwq_ind_tbl); | |
5633 | return ERR_PTR(err); | |
5634 | } | |
5635 | ||
5636 | int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) | |
5637 | { | |
5638 | struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); | |
5639 | struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); | |
5640 | ||
5641 | mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn); | |
5642 | ||
5643 | kfree(rwq_ind_tbl); | |
5644 | return 0; | |
5645 | } | |
5646 | ||
79b20a6c YH |
5647 | int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, |
5648 | u32 wq_attr_mask, struct ib_udata *udata) | |
5649 | { | |
5650 | struct mlx5_ib_dev *dev = to_mdev(wq->device); | |
5651 | struct mlx5_ib_rwq *rwq = to_mrwq(wq); | |
5652 | struct mlx5_ib_modify_wq ucmd = {}; | |
5653 | size_t required_cmd_sz; | |
5654 | int curr_wq_state; | |
5655 | int wq_state; | |
5656 | int inlen; | |
5657 | int err; | |
5658 | void *rqc; | |
5659 | void *in; | |
5660 | ||
5661 | required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); | |
5662 | if (udata->inlen < required_cmd_sz) | |
5663 | return -EINVAL; | |
5664 | ||
5665 | if (udata->inlen > sizeof(ucmd) && | |
5666 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
5667 | udata->inlen - sizeof(ucmd))) | |
5668 | return -EOPNOTSUPP; | |
5669 | ||
5670 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) | |
5671 | return -EFAULT; | |
5672 | ||
5673 | if (ucmd.comp_mask || ucmd.reserved) | |
5674 | return -EOPNOTSUPP; | |
5675 | ||
5676 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 5677 | in = kvzalloc(inlen, GFP_KERNEL); |
79b20a6c YH |
5678 | if (!in) |
5679 | return -ENOMEM; | |
5680 | ||
5681 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
5682 | ||
5683 | curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? | |
5684 | wq_attr->curr_wq_state : wq->state; | |
5685 | wq_state = (wq_attr_mask & IB_WQ_STATE) ? | |
5686 | wq_attr->wq_state : curr_wq_state; | |
5687 | if (curr_wq_state == IB_WQS_ERR) | |
5688 | curr_wq_state = MLX5_RQC_STATE_ERR; | |
5689 | if (wq_state == IB_WQS_ERR) | |
5690 | wq_state = MLX5_RQC_STATE_ERR; | |
5691 | MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); | |
5692 | MLX5_SET(rqc, rqc, state, wq_state); | |
5693 | ||
b1f74a84 NO |
5694 | if (wq_attr_mask & IB_WQ_FLAGS) { |
5695 | if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { | |
5696 | if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && | |
5697 | MLX5_CAP_ETH(dev->mdev, vlan_cap))) { | |
5698 | mlx5_ib_dbg(dev, "VLAN offloads are not " | |
5699 | "supported\n"); | |
5700 | err = -EOPNOTSUPP; | |
5701 | goto out; | |
5702 | } | |
5703 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
5704 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
5705 | MLX5_SET(rqc, rqc, vsd, | |
5706 | (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); | |
5707 | } | |
b1383aa6 NO |
5708 | |
5709 | if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { | |
5710 | mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); | |
5711 | err = -EOPNOTSUPP; | |
5712 | goto out; | |
5713 | } | |
b1f74a84 NO |
5714 | } |
5715 | ||
23a6964e MD |
5716 | if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { |
5717 | if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { | |
5718 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
5719 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); | |
e1f24a79 PP |
5720 | MLX5_SET(rqc, rqc, counter_set_id, |
5721 | dev->port->cnts.set_id); | |
23a6964e MD |
5722 | } else |
5723 | pr_info_once("%s: Receive WQ counters are not supported on current FW\n", | |
5724 | dev->ib_dev.name); | |
5725 | } | |
5726 | ||
350d0e4c | 5727 | err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); |
79b20a6c YH |
5728 | if (!err) |
5729 | rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; | |
5730 | ||
b1f74a84 NO |
5731 | out: |
5732 | kvfree(in); | |
79b20a6c YH |
5733 | return err; |
5734 | } | |
d0e84c0a YH |
5735 | |
5736 | struct mlx5_ib_drain_cqe { | |
5737 | struct ib_cqe cqe; | |
5738 | struct completion done; | |
5739 | }; | |
5740 | ||
5741 | static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) | |
5742 | { | |
5743 | struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, | |
5744 | struct mlx5_ib_drain_cqe, | |
5745 | cqe); | |
5746 | ||
5747 | complete(&cqe->done); | |
5748 | } | |
5749 | ||
5750 | /* This function returns only once the drained WR was completed */ | |
5751 | static void handle_drain_completion(struct ib_cq *cq, | |
5752 | struct mlx5_ib_drain_cqe *sdrain, | |
5753 | struct mlx5_ib_dev *dev) | |
5754 | { | |
5755 | struct mlx5_core_dev *mdev = dev->mdev; | |
5756 | ||
5757 | if (cq->poll_ctx == IB_POLL_DIRECT) { | |
5758 | while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) | |
5759 | ib_process_cq_direct(cq, -1); | |
5760 | return; | |
5761 | } | |
5762 | ||
5763 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
5764 | struct mlx5_ib_cq *mcq = to_mcq(cq); | |
5765 | bool triggered = false; | |
5766 | unsigned long flags; | |
5767 | ||
5768 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
5769 | /* Make sure that the CQ handler won't run if wasn't run yet */ | |
5770 | if (!mcq->mcq.reset_notify_added) | |
5771 | mcq->mcq.reset_notify_added = 1; | |
5772 | else | |
5773 | triggered = true; | |
5774 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
5775 | ||
5776 | if (triggered) { | |
5777 | /* Wait for any scheduled/running task to be ended */ | |
5778 | switch (cq->poll_ctx) { | |
5779 | case IB_POLL_SOFTIRQ: | |
5780 | irq_poll_disable(&cq->iop); | |
5781 | irq_poll_enable(&cq->iop); | |
5782 | break; | |
5783 | case IB_POLL_WORKQUEUE: | |
5784 | cancel_work_sync(&cq->work); | |
5785 | break; | |
5786 | default: | |
5787 | WARN_ON_ONCE(1); | |
5788 | } | |
5789 | } | |
5790 | ||
5791 | /* Run the CQ handler - this makes sure that the drain WR will | |
5792 | * be processed if wasn't processed yet. | |
5793 | */ | |
5794 | mcq->mcq.comp(&mcq->mcq); | |
5795 | } | |
5796 | ||
5797 | wait_for_completion(&sdrain->done); | |
5798 | } | |
5799 | ||
5800 | void mlx5_ib_drain_sq(struct ib_qp *qp) | |
5801 | { | |
5802 | struct ib_cq *cq = qp->send_cq; | |
5803 | struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; | |
5804 | struct mlx5_ib_drain_cqe sdrain; | |
d34ac5cd | 5805 | const struct ib_send_wr *bad_swr; |
d0e84c0a YH |
5806 | struct ib_rdma_wr swr = { |
5807 | .wr = { | |
5808 | .next = NULL, | |
5809 | { .wr_cqe = &sdrain.cqe, }, | |
5810 | .opcode = IB_WR_RDMA_WRITE, | |
5811 | }, | |
5812 | }; | |
5813 | int ret; | |
5814 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
5815 | struct mlx5_core_dev *mdev = dev->mdev; | |
5816 | ||
5817 | ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | |
5818 | if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
5819 | WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); | |
5820 | return; | |
5821 | } | |
5822 | ||
5823 | sdrain.cqe.done = mlx5_ib_drain_qp_done; | |
5824 | init_completion(&sdrain.done); | |
5825 | ||
5826 | ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); | |
5827 | if (ret) { | |
5828 | WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); | |
5829 | return; | |
5830 | } | |
5831 | ||
5832 | handle_drain_completion(cq, &sdrain, dev); | |
5833 | } | |
5834 | ||
5835 | void mlx5_ib_drain_rq(struct ib_qp *qp) | |
5836 | { | |
5837 | struct ib_cq *cq = qp->recv_cq; | |
5838 | struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; | |
5839 | struct mlx5_ib_drain_cqe rdrain; | |
d34ac5cd BVA |
5840 | struct ib_recv_wr rwr = {}; |
5841 | const struct ib_recv_wr *bad_rwr; | |
d0e84c0a YH |
5842 | int ret; |
5843 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
5844 | struct mlx5_core_dev *mdev = dev->mdev; | |
5845 | ||
5846 | ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | |
5847 | if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
5848 | WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); | |
5849 | return; | |
5850 | } | |
5851 | ||
5852 | rwr.wr_cqe = &rdrain.cqe; | |
5853 | rdrain.cqe.done = mlx5_ib_drain_qp_done; | |
5854 | init_completion(&rdrain.done); | |
5855 | ||
5856 | ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); | |
5857 | if (ret) { | |
5858 | WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); | |
5859 | return; | |
5860 | } | |
5861 | ||
5862 | handle_drain_completion(cq, &rdrain, dev); | |
5863 | } |