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IB/mlx5: Set uid as part of RQ commands
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
b96c9dde 39#include "ib_rep.h"
e126ba97
EC		 40
41/* not supported currently */
42static int wq_signature;
43
44enum {
45 MLX5_IB_ACK_REQ_FREQ = 8,
46};
47
48enum {
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
53};
54
55enum {
56 MLX5_IB_SQ_STRIDE = 6,
064e5262 57 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
e126ba97
EC		 58};
59
60static const u32 mlx5_ib_opcode[] = {
61 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 62 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 63 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
64 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
65 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
66 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
67 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
68 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
69 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
70 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 71 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 72 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
73 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
74 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
75};
76
f0313965
ES		 77struct mlx5_wqe_eth_pad {
78 u8 rsvd0[16];
79};
e126ba97 80
eb49ab0c
AV		 81enum raw_qp_set_mask_map {
82 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 83 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 84};
85
0680efa2
AV		 86struct mlx5_modify_raw_qp_param {
87 u16 operation;
eb49ab0c
AV		 88
89 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 90
91 struct mlx5_rate_limit rl;
92
eb49ab0c 93 u8 rq_q_ctr_id;
0680efa2
AV		 94};
95
89ea94a7
MG		 96static void get_cqs(enum ib_qp_type qp_type,
97 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
98 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
99
e126ba97
EC		 100static int is_qp0(enum ib_qp_type qp_type)
101{
102 return qp_type == IB_QPT_SMI;
103}
104
e126ba97
EC		 105static int is_sqp(enum ib_qp_type qp_type)
106{
107 return is_qp0(qp_type) || is_qp1(qp_type);
108}
109
110static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
111{
112 return mlx5_buf_offset(&qp->buf, offset);
113}
114
115static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
116{
117 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
118}
119
120void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
121{
122 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
123}
124
c1395a2a
HE		 125/**
126 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
127 *
128 * @qp: QP to copy from.
129 * @send: copy from the send queue when non-zero, use the receive queue
130 * otherwise.
131 * @wqe_index: index to start copying from. For send work queues, the
132 * wqe_index is in units of MLX5_SEND_WQE_BB.
133 * For receive work queue, it is the number of work queue
134 * element in the queue.
135 * @buffer: destination buffer.
136 * @length: maximum number of bytes to copy.
137 *
138 * Copies at least a single WQE, but may copy more data.
139 *
140 * Return: the number of bytes copied, or an error code.
141 */
142int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 143 void *buffer, u32 length,
144 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 145{
146 struct ib_device *ibdev = qp->ibqp.device;
147 struct mlx5_ib_dev *dev = to_mdev(ibdev);
148 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
149 size_t offset;
150 size_t wq_end;
19098df2 151 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 152 u32 first_copy_length;
153 int wqe_length;
154 int ret;
155
156 if (wq->wqe_cnt == 0) {
157 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
158 qp->ibqp.qp_type);
159 return -EINVAL;
160 }
161
162 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
163 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
164
165 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
166 return -EINVAL;
167
168 if (offset > umem->length ||
169 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
170 return -EINVAL;
171
172 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
173 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
174 if (ret)
175 return ret;
176
177 if (send) {
178 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
179 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
180
181 wqe_length = ds * MLX5_WQE_DS_UNITS;
182 } else {
183 wqe_length = 1 << wq->wqe_shift;
184 }
185
186 if (wqe_length <= first_copy_length)
187 return first_copy_length;
188
189 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
190 wqe_length - first_copy_length);
191 if (ret)
192 return ret;
193
194 return wqe_length;
195}
196
e126ba97
EC		 197static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
198{
199 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
200 struct ib_event event;
201
19098df2 202 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
203 /* This event is only valid for trans_qps */
204 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
205 }
e126ba97
EC		 206
207 if (ibqp->event_handler) {
208 event.device = ibqp->device;
209 event.element.qp = ibqp;
210 switch (type) {
211 case MLX5_EVENT_TYPE_PATH_MIG:
212 event.event = IB_EVENT_PATH_MIG;
213 break;
214 case MLX5_EVENT_TYPE_COMM_EST:
215 event.event = IB_EVENT_COMM_EST;
216 break;
217 case MLX5_EVENT_TYPE_SQ_DRAINED:
218 event.event = IB_EVENT_SQ_DRAINED;
219 break;
220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
221 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
222 break;
223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
224 event.event = IB_EVENT_QP_FATAL;
225 break;
226 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
227 event.event = IB_EVENT_PATH_MIG_ERR;
228 break;
229 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
230 event.event = IB_EVENT_QP_REQ_ERR;
231 break;
232 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
233 event.event = IB_EVENT_QP_ACCESS_ERR;
234 break;
235 default:
236 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
237 return;
238 }
239
240 ibqp->event_handler(&event, ibqp->qp_context);
241 }
242}
243
244static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
245 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
246{
247 int wqe_size;
248 int wq_size;
249
250 /* Sanity check RQ size before proceeding */
938fe83c 251 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 252 return -EINVAL;
253
254 if (!has_rq) {
255 qp->rq.max_gs = 0;
256 qp->rq.wqe_cnt = 0;
257 qp->rq.wqe_shift = 0;
0540d814
NO		 258 cap->max_recv_wr = 0;
259 cap->max_recv_sge = 0;
e126ba97
EC		 260 } else {
261 if (ucmd) {
262 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
002bf228
LR		 263 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
264 return -EINVAL;
e126ba97 265 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
002bf228
LR		 266 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
267 return -EINVAL;
e126ba97
EC		 268 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
269 qp->rq.max_post = qp->rq.wqe_cnt;
270 } else {
271 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
272 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
273 wqe_size = roundup_pow_of_two(wqe_size);
274 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
275 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
276 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 277 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 278 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
279 wqe_size,
938fe83c
SM		 280 MLX5_CAP_GEN(dev->mdev,
281 max_wqe_sz_rq));
e126ba97
EC		 282 return -EINVAL;
283 }
284 qp->rq.wqe_shift = ilog2(wqe_size);
285 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
286 qp->rq.max_post = qp->rq.wqe_cnt;
287 }
288 }
289
290 return 0;
291}
292
f0313965 293static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 294{
618af384 295 int size = 0;
e126ba97 296
f0313965 297 switch (attr->qp_type) {
e126ba97 298 case IB_QPT_XRC_INI:
b125a54b 299 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 300 /* fall through */
301 case IB_QPT_RC:
302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 303 max(sizeof(struct mlx5_wqe_atomic_seg) +
304 sizeof(struct mlx5_wqe_raddr_seg),
305 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
064e5262
IB		 306 sizeof(struct mlx5_mkey_seg) +
307 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
308 MLX5_IB_UMR_OCTOWORD);
e126ba97
EC		 309 break;
310
b125a54b
EC		 311 case IB_QPT_XRC_TGT:
312 return 0;
313
e126ba97 314 case IB_QPT_UC:
b125a54b 315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 316 max(sizeof(struct mlx5_wqe_raddr_seg),
317 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
318 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 319 break;
320
321 case IB_QPT_UD:
f0313965
ES		 322 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
323 size += sizeof(struct mlx5_wqe_eth_pad) +
324 sizeof(struct mlx5_wqe_eth_seg);
325 /* fall through */
e126ba97 326 case IB_QPT_SMI:
d16e91da 327 case MLX5_IB_QPT_HW_GSI:
b125a54b 328 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 329 sizeof(struct mlx5_wqe_datagram_seg);
330 break;
331
332 case MLX5_IB_QPT_REG_UMR:
b125a54b 333 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 334 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
335 sizeof(struct mlx5_mkey_seg);
336 break;
337
338 default:
339 return -EINVAL;
340 }
341
342 return size;
343}
344
345static int calc_send_wqe(struct ib_qp_init_attr *attr)
346{
347 int inl_size = 0;
348 int size;
349
f0313965 350 size = sq_overhead(attr);
e126ba97
EC		 351 if (size < 0)
352 return size;
353
354 if (attr->cap.max_inline_data) {
355 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
356 attr->cap.max_inline_data;
357 }
358
359 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 360 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
361 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
362 return MLX5_SIG_WQE_SIZE;
363 else
364 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 365}
366
288c01b7
EC		 367static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
368{
369 int max_sge;
370
371 if (attr->qp_type == IB_QPT_RC)
372 max_sge = (min_t(int, wqe_size, 512) -
373 sizeof(struct mlx5_wqe_ctrl_seg) -
374 sizeof(struct mlx5_wqe_raddr_seg)) /
375 sizeof(struct mlx5_wqe_data_seg);
376 else if (attr->qp_type == IB_QPT_XRC_INI)
377 max_sge = (min_t(int, wqe_size, 512) -
378 sizeof(struct mlx5_wqe_ctrl_seg) -
379 sizeof(struct mlx5_wqe_xrc_seg) -
380 sizeof(struct mlx5_wqe_raddr_seg)) /
381 sizeof(struct mlx5_wqe_data_seg);
382 else
383 max_sge = (wqe_size - sq_overhead(attr)) /
384 sizeof(struct mlx5_wqe_data_seg);
385
386 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
387 sizeof(struct mlx5_wqe_data_seg));
388}
389
e126ba97
EC		 390static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
391 struct mlx5_ib_qp *qp)
392{
393 int wqe_size;
394 int wq_size;
395
396 if (!attr->cap.max_send_wr)
397 return 0;
398
399 wqe_size = calc_send_wqe(attr);
400 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
401 if (wqe_size < 0)
402 return wqe_size;
403
938fe83c 404 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 405 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 406 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 407 return -EINVAL;
408 }
409
f0313965
ES		 410 qp->max_inline_data = wqe_size - sq_overhead(attr) -
411 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 412 attr->cap.max_inline_data = qp->max_inline_data;
413
e1e66cc2
SG		 414 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
415 qp->signature_en = true;
416
e126ba97
EC		 417 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
418 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 420 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
421 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 422 qp->sq.wqe_cnt,
423 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 424 return -ENOMEM;
425 }
e126ba97 426 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 427 qp->sq.max_gs = get_send_sge(attr, wqe_size);
428 if (qp->sq.max_gs < attr->cap.max_send_sge)
429 return -ENOMEM;
430
431 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 432 qp->sq.max_post = wq_size / wqe_size;
433 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 434
435 return wq_size;
436}
437
438static int set_user_buf_size(struct mlx5_ib_dev *dev,
439 struct mlx5_ib_qp *qp,
19098df2 440 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 441 struct mlx5_ib_qp_base *base,
442 struct ib_qp_init_attr *attr)
e126ba97
EC		 443{
444 int desc_sz = 1 << qp->sq.wqe_shift;
445
938fe83c 446 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 447 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 448 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 449 return -EINVAL;
450 }
451
452 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
453 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
454 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
455 return -EINVAL;
456 }
457
458 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
459
938fe83c 460 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 461 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 462 qp->sq.wqe_cnt,
463 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 464 return -EINVAL;
465 }
466
c2e53b2c
YH		 467 if (attr->qp_type == IB_QPT_RAW_PACKET ||
468 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 469 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
470 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
471 } else {
472 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
473 (qp->sq.wqe_cnt << 6);
474 }
e126ba97
EC		 475
476 return 0;
477}
478
479static int qp_has_rq(struct ib_qp_init_attr *attr)
480{
481 if (attr->qp_type == IB_QPT_XRC_INI ||
482 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
483 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
484 !attr->cap.max_recv_wr)
485 return 0;
486
487 return 1;
488}
489
0b80c14f
EC		 490enum {
491 /* this is the first blue flame register in the array of bfregs assigned
492 * to a processes. Since we do not use it for blue flame but rather
493 * regular 64 bit doorbells, we do not need a lock for maintaiing
494 * "odd/even" order
495 */
496 NUM_NON_BLUE_FLAME_BFREGS = 1,
497};
498
b037c29a
EC		 499static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
500{
31a78a5a 501 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 502}
503
504static int num_med_bfreg(struct mlx5_ib_dev *dev,
505 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 506{
507 int n;
508
b037c29a
EC		 509 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
510 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 511
512 return n >= 0 ? n : 0;
513}
514
18b0362e
YH		 515static int first_med_bfreg(struct mlx5_ib_dev *dev,
516 struct mlx5_bfreg_info *bfregi)
517{
518 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
519}
520
b037c29a
EC		 521static int first_hi_bfreg(struct mlx5_ib_dev *dev,
522 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 523{
524 int med;
c1be5232 525
b037c29a
EC		 526 med = num_med_bfreg(dev, bfregi);
527 return ++med;
c1be5232
EC		 528}
529
b037c29a
EC		 530static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
531 struct mlx5_bfreg_info *bfregi)
e126ba97 532{
e126ba97
EC		 533 int i;
534
b037c29a
EC		 535 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
536 if (!bfregi->count[i]) {
2f5ff264 537 bfregi->count[i]++;
e126ba97
EC		 538 return i;
539 }
540 }
541
542 return -ENOMEM;
543}
544
b037c29a
EC		 545static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
546 struct mlx5_bfreg_info *bfregi)
e126ba97 547{
18b0362e 548 int minidx = first_med_bfreg(dev, bfregi);
e126ba97
EC		 549 int i;
550
18b0362e
YH		 551 if (minidx < 0)
552 return minidx;
553
554 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 555 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 556 minidx = i;
0b80c14f
EC		 557 if (!bfregi->count[minidx])
558 break;
e126ba97
EC		 559 }
560
2f5ff264 561 bfregi->count[minidx]++;
e126ba97
EC		 562 return minidx;
563}
564
b037c29a 565static int alloc_bfreg(struct mlx5_ib_dev *dev,
ffaf58de 566 struct mlx5_bfreg_info *bfregi)
e126ba97 567{
ffaf58de 568 int bfregn = -ENOMEM;
e126ba97 569
2f5ff264 570 mutex_lock(&bfregi->lock);
ffaf58de
LR		 571 if (bfregi->ver >= 2) {
572 bfregn = alloc_high_class_bfreg(dev, bfregi);
573 if (bfregn < 0)
574 bfregn = alloc_med_class_bfreg(dev, bfregi);
575 }
576
577 if (bfregn < 0) {
0b80c14f 578 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 579 bfregn = 0;
580 bfregi->count[bfregn]++;
e126ba97 581 }
2f5ff264 582 mutex_unlock(&bfregi->lock);
e126ba97 583
2f5ff264 584 return bfregn;
e126ba97
EC		 585}
586
4ed131d0 587void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 588{
2f5ff264 589 mutex_lock(&bfregi->lock);
b037c29a 590 bfregi->count[bfregn]--;
2f5ff264 591 mutex_unlock(&bfregi->lock);
e126ba97
EC		 592}
593
594static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
595{
596 switch (state) {
597 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
598 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
599 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
600 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
601 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
602 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
603 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
604 default: return -1;
605 }
606}
607
608static int to_mlx5_st(enum ib_qp_type type)
609{
610 switch (type) {
611 case IB_QPT_RC: return MLX5_QP_ST_RC;
612 case IB_QPT_UC: return MLX5_QP_ST_UC;
613 case IB_QPT_UD: return MLX5_QP_ST_UD;
614 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
615 case IB_QPT_XRC_INI:
616 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
617 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 618 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 619 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 620 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 621 case IB_QPT_RAW_PACKET:
0fb2ed66 622 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 623 case IB_QPT_MAX:
624 default: return -EINVAL;
625 }
626}
627
89ea94a7
MG		 628static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
629 struct mlx5_ib_cq *recv_cq);
630static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
631 struct mlx5_ib_cq *recv_cq);
632
7c043e90 633int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
05f58ceb 634 struct mlx5_bfreg_info *bfregi, u32 bfregn,
7c043e90 635 bool dyn_bfreg)
e126ba97 636{
05f58ceb
LR		 637 unsigned int bfregs_per_sys_page;
638 u32 index_of_sys_page;
639 u32 offset;
b037c29a
EC		 640
641 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
642 MLX5_NON_FP_BFREGS_PER_UAR;
643 index_of_sys_page = bfregn / bfregs_per_sys_page;
644
1ee47ab3
YH		 645 if (dyn_bfreg) {
646 index_of_sys_page += bfregi->num_static_sys_pages;
05f58ceb
LR		 647
648 if (index_of_sys_page >= bfregi->num_sys_pages)
649 return -EINVAL;
650
1ee47ab3
YH		 651 if (bfregn > bfregi->num_dyn_bfregs ||
652 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
653 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
654 return -EINVAL;
655 }
656 }
b037c29a 657
1ee47ab3 658 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 659 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 660}
661
19098df2 662static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
663 struct ib_pd *pd,
664 unsigned long addr, size_t size,
665 struct ib_umem **umem,
666 int *npages, int *page_shift, int *ncont,
667 u32 *offset)
668{
669 int err;
670
671 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
672 if (IS_ERR(*umem)) {
673 mlx5_ib_dbg(dev, "umem_get failed\n");
674 return PTR_ERR(*umem);
675 }
676
762f899a 677 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 678
679 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
680 if (err) {
681 mlx5_ib_warn(dev, "bad offset\n");
682 goto err_umem;
683 }
684
685 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
686 addr, size, *npages, *page_shift, *ncont, *offset);
687
688 return 0;
689
690err_umem:
691 ib_umem_release(*umem);
692 *umem = NULL;
693
694 return err;
695}
696
fe248c3a
MG		 697static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
698 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 699{
700 struct mlx5_ib_ucontext *context;
701
fe248c3a
MG		 702 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
703 atomic_dec(&dev->delay_drop.rqs_cnt);
704
79b20a6c
YH		 705 context = to_mucontext(pd->uobject->context);
706 mlx5_ib_db_unmap_user(context, &rwq->db);
707 if (rwq->umem)
708 ib_umem_release(rwq->umem);
709}
710
711static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
712 struct mlx5_ib_rwq *rwq,
713 struct mlx5_ib_create_wq *ucmd)
714{
715 struct mlx5_ib_ucontext *context;
716 int page_shift = 0;
717 int npages;
718 u32 offset = 0;
719 int ncont = 0;
720 int err;
721
722 if (!ucmd->buf_addr)
723 return -EINVAL;
724
725 context = to_mucontext(pd->uobject->context);
726 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
727 rwq->buf_size, 0, 0);
728 if (IS_ERR(rwq->umem)) {
729 mlx5_ib_dbg(dev, "umem_get failed\n");
730 err = PTR_ERR(rwq->umem);
731 return err;
732 }
733
762f899a 734 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 735 &ncont, NULL);
736 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
737 &rwq->rq_page_offset);
738 if (err) {
739 mlx5_ib_warn(dev, "bad offset\n");
740 goto err_umem;
741 }
742
743 rwq->rq_num_pas = ncont;
744 rwq->page_shift = page_shift;
745 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
746 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
747
748 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
749 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
750 npages, page_shift, ncont, offset);
751
752 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
753 if (err) {
754 mlx5_ib_dbg(dev, "map failed\n");
755 goto err_umem;
756 }
757
758 rwq->create_type = MLX5_WQ_USER;
759 return 0;
760
761err_umem:
762 ib_umem_release(rwq->umem);
763 return err;
764}
765
b037c29a
EC		 766static int adjust_bfregn(struct mlx5_ib_dev *dev,
767 struct mlx5_bfreg_info *bfregi, int bfregn)
768{
769 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
770 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
771}
772
e126ba97
EC		 773static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
774 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 775 struct ib_qp_init_attr *attr,
09a7d9ec 776 u32 **in,
19098df2 777 struct mlx5_ib_create_qp_resp *resp, int *inlen,
778 struct mlx5_ib_qp_base *base)
e126ba97
EC		 779{
780 struct mlx5_ib_ucontext *context;
781 struct mlx5_ib_create_qp ucmd;
19098df2 782 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 783 int page_shift = 0;
1ee47ab3 784 int uar_index = 0;
e126ba97 785 int npages;
9e9c47d0 786 u32 offset = 0;
2f5ff264 787 int bfregn;
9e9c47d0 788 int ncont = 0;
09a7d9ec
SM		 789 __be64 *pas;
790 void *qpc;
e126ba97
EC		 791 int err;
792
793 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
794 if (err) {
795 mlx5_ib_dbg(dev, "copy failed\n");
796 return err;
797 }
798
799 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 800 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
801 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
802 ucmd.bfreg_index, true);
803 if (uar_index < 0)
804 return uar_index;
805
806 bfregn = MLX5_IB_INVALID_BFREG;
807 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
808 /*
809 * TBD: should come from the verbs when we have the API
810 */
051f2630 811 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 812 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 813 }
051f2630 814 else {
ffaf58de
LR		 815 bfregn = alloc_bfreg(dev, &context->bfregi);
816 if (bfregn < 0)
817 return bfregn;
e126ba97
EC		 818 }
819
2f5ff264 820 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 821 if (bfregn != MLX5_IB_INVALID_BFREG)
822 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
823 false);
e126ba97 824
48fea837
HE		 825 qp->rq.offset = 0;
826 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
827 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
828
0fb2ed66 829 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 830 if (err)
2f5ff264 831 goto err_bfreg;
e126ba97 832
19098df2 833 if (ucmd.buf_addr && ubuffer->buf_size) {
834 ubuffer->buf_addr = ucmd.buf_addr;
835 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
836 ubuffer->buf_size,
837 &ubuffer->umem, &npages, &page_shift,
838 &ncont, &offset);
839 if (err)
2f5ff264 840 goto err_bfreg;
9e9c47d0 841 } else {
19098df2 842 ubuffer->umem = NULL;
e126ba97 843 }
e126ba97 844
09a7d9ec
SM		 845 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
846 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 847 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 848 if (!*in) {
849 err = -ENOMEM;
850 goto err_umem;
851 }
09a7d9ec 852
991d2198 853 MLX5_SET(create_qp_in, *in, uid, to_mpd(pd)->uid);
09a7d9ec 854 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 855 if (ubuffer->umem)
09a7d9ec
SM		 856 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
857
858 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
859
860 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
861 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 862
09a7d9ec 863 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 864 if (bfregn != MLX5_IB_INVALID_BFREG)
865 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
866 else
867 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 868 qp->bfregn = bfregn;
e126ba97
EC		 869
870 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
871 if (err) {
872 mlx5_ib_dbg(dev, "map failed\n");
873 goto err_free;
874 }
875
41d902cb 876 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
e126ba97
EC		 877 if (err) {
878 mlx5_ib_dbg(dev, "copy failed\n");
879 goto err_unmap;
880 }
881 qp->create_type = MLX5_QP_USER;
882
883 return 0;
884
885err_unmap:
886 mlx5_ib_db_unmap_user(context, &qp->db);
887
888err_free:
479163f4 889 kvfree(*in);
e126ba97
EC		 890
891err_umem:
19098df2 892 if (ubuffer->umem)
893 ib_umem_release(ubuffer->umem);
e126ba97 894
2f5ff264 895err_bfreg:
1ee47ab3
YH		 896 if (bfregn != MLX5_IB_INVALID_BFREG)
897 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 898 return err;
899}
900
b037c29a
EC		 901static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
902 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 903{
904 struct mlx5_ib_ucontext *context;
905
906 context = to_mucontext(pd->uobject->context);
907 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 908 if (base->ubuffer.umem)
909 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 910
911 /*
912 * Free only the BFREGs which are handled by the kernel.
913 * BFREGs of UARs allocated dynamically are handled by user.
914 */
915 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
916 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 917}
918
919static int create_kernel_qp(struct mlx5_ib_dev *dev,
920 struct ib_qp_init_attr *init_attr,
921 struct mlx5_ib_qp *qp,
09a7d9ec 922 u32 **in, int *inlen,
19098df2 923 struct mlx5_ib_qp_base *base)
e126ba97 924{
e126ba97 925 int uar_index;
09a7d9ec 926 void *qpc;
e126ba97
EC		 927 int err;
928
f0313965
ES		 929 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
930 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 931 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 932 IB_QP_CREATE_NETIF_QP |
b11a4f9c 933 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 934 return -EINVAL;
e126ba97
EC		 935
936 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 937 qp->bf.bfreg = &dev->fp_bfreg;
938 else
939 qp->bf.bfreg = &dev->bfreg;
e126ba97 940
d8030b0d
EC		 941 /* We need to divide by two since each register is comprised of
942 * two buffers of identical size, namely odd and even
943 */
944 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 945 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 946
947 err = calc_sq_size(dev, init_attr, qp);
948 if (err < 0) {
949 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 950 return err;
e126ba97
EC		 951 }
952
953 qp->rq.offset = 0;
954 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 955 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 956
19098df2 957 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 958 if (err) {
959 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 960 return err;
e126ba97
EC		 961 }
962
963 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 964 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
965 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 966 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 967 if (!*in) {
968 err = -ENOMEM;
969 goto err_buf;
970 }
09a7d9ec
SM		 971
972 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
973 MLX5_SET(qpc, qpc, uar_page, uar_index);
974 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
975
e126ba97 976 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 977 MLX5_SET(qpc, qpc, fre, 1);
978 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 979
b11a4f9c 980 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 981 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 982 qp->flags |= MLX5_IB_QP_SQPN_QP1;
983 }
984
09a7d9ec
SM		 985 mlx5_fill_page_array(&qp->buf,
986 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 987
9603b61d 988 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 989 if (err) {
990 mlx5_ib_dbg(dev, "err %d\n", err);
991 goto err_free;
992 }
993
b5883008
LD		 994 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
995 sizeof(*qp->sq.wrid), GFP_KERNEL);
996 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
997 sizeof(*qp->sq.wr_data), GFP_KERNEL);
998 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
999 sizeof(*qp->rq.wrid), GFP_KERNEL);
1000 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1001 sizeof(*qp->sq.w_list), GFP_KERNEL);
1002 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1003 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1004
1005 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1006 !qp->sq.w_list || !qp->sq.wqe_head) {
1007 err = -ENOMEM;
1008 goto err_wrid;
1009 }
1010 qp->create_type = MLX5_QP_KERNEL;
1011
1012 return 0;
1013
1014err_wrid:
b5883008
LD		 1015 kvfree(qp->sq.wqe_head);
1016 kvfree(qp->sq.w_list);
1017 kvfree(qp->sq.wrid);
1018 kvfree(qp->sq.wr_data);
1019 kvfree(qp->rq.wrid);
f4044dac 1020 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1021
1022err_free:
479163f4 1023 kvfree(*in);
e126ba97
EC		 1024
1025err_buf:
9603b61d 1026 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1027 return err;
1028}
1029
1030static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1031{
b5883008
LD		 1032 kvfree(qp->sq.wqe_head);
1033 kvfree(qp->sq.w_list);
1034 kvfree(qp->sq.wrid);
1035 kvfree(qp->sq.wr_data);
1036 kvfree(qp->rq.wrid);
f4044dac 1037 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1038 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1039}
1040
09a7d9ec 1041static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1042{
1043 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1044 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1045 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1046 return MLX5_SRQ_RQ;
e126ba97 1047 else if (!qp->has_rq)
09a7d9ec 1048 return MLX5_ZERO_LEN_RQ;
e126ba97 1049 else
09a7d9ec 1050 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1051}
1052
1053static int is_connected(enum ib_qp_type qp_type)
1054{
1055 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1056 return 1;
1057
1058 return 0;
1059}
1060
0fb2ed66 1061static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1062 struct mlx5_ib_qp *qp,
0fb2ed66 1063 struct mlx5_ib_sq *sq, u32 tdn)
1064{
c4f287c4 1065 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1066 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1067
0fb2ed66 1068 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1069 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1070 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1071
0fb2ed66 1072 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1073}
1074
1075static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1076 struct mlx5_ib_sq *sq)
1077{
1078 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1079}
1080
b96c9dde
MB		 1081static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1082 struct mlx5_ib_sq *sq)
1083{
1084 if (sq->flow_rule)
1085 mlx5_del_flow_rules(sq->flow_rule);
1086}
1087
0fb2ed66 1088static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1089 struct mlx5_ib_sq *sq, void *qpin,
1090 struct ib_pd *pd)
1091{
1092 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1093 __be64 *pas;
1094 void *in;
1095 void *sqc;
1096 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1097 void *wq;
1098 int inlen;
1099 int err;
1100 int page_shift = 0;
1101 int npages;
1102 int ncont = 0;
1103 u32 offset = 0;
1104
1105 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1106 &sq->ubuffer.umem, &npages, &page_shift,
1107 &ncont, &offset);
1108 if (err)
1109 return err;
1110
1111 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1112 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1113 if (!in) {
1114 err = -ENOMEM;
1115 goto err_umem;
1116 }
1117
1118 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1119 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1120 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1121 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1122 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1123 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1124 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1125 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1126 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1127 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1128 MLX5_CAP_ETH(dev->mdev, swp))
1129 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1130
1131 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1132 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1133 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1134 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1135 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1136 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1137 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1138 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1139 MLX5_SET(wq, wq, page_offset, offset);
1140
1141 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1142 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1143
1144 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1145
1146 kvfree(in);
1147
1148 if (err)
1149 goto err_umem;
1150
b96c9dde
MB		 1151 err = create_flow_rule_vport_sq(dev, sq);
1152 if (err)
1153 goto err_flow;
1154
0fb2ed66 1155 return 0;
1156
b96c9dde
MB		 1157err_flow:
1158 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1159
0fb2ed66 1160err_umem:
1161 ib_umem_release(sq->ubuffer.umem);
1162 sq->ubuffer.umem = NULL;
1163
1164 return err;
1165}
1166
1167static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1168 struct mlx5_ib_sq *sq)
1169{
b96c9dde 1170 destroy_flow_rule_vport_sq(dev, sq);
0fb2ed66 1171 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1172 ib_umem_release(sq->ubuffer.umem);
1173}
1174
2c292dbb 1175static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1176{
1177 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1178 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1179 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1180 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1181 u32 po_quanta = 1 << (log_page_size - 6);
1182 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1183 u32 page_size = 1 << log_page_size;
1184 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1185 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1186
1187 return rq_num_pas * sizeof(u64);
1188}
1189
1190static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb 1191 struct mlx5_ib_rq *rq, void *qpin,
34d57585 1192 size_t qpinlen, struct ib_pd *pd)
0fb2ed66 1193{
358e42ea 1194 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1195 __be64 *pas;
1196 __be64 *qp_pas;
1197 void *in;
1198 void *rqc;
1199 void *wq;
1200 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1201 size_t rq_pas_size = get_rq_pas_size(qpc);
1202 size_t inlen;
0fb2ed66 1203 int err;
2c292dbb
BP		 1204
1205 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1206 return -EINVAL;
0fb2ed66 1207
1208 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1209 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1210 if (!in)
1211 return -ENOMEM;
1212
34d57585 1213 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1214 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1215 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1216 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1217 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1218 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1219 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1220 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1221 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1222
358e42ea
MD		 1223 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1224 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1225
0fb2ed66 1226 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1227 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1228 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1229 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1230 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1231 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1232 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1233 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1234 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1235 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1236
1237 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1238 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1239 memcpy(pas, qp_pas, rq_pas_size);
1240
1241 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1242
1243 kvfree(in);
1244
1245 return err;
1246}
1247
1248static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1249 struct mlx5_ib_rq *rq)
1250{
1251 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1252}
1253
f95ef6cb
MG		 1254static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1255{
1256 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1257 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1258 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1259}
1260
0042f9e4
MB		 1261static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1262 struct mlx5_ib_rq *rq,
1263 u32 qp_flags_en)
1264{
1265 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1266 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1267 mlx5_ib_disable_lb(dev, false, true);
1268 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1269}
1270
0fb2ed66 1271static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb 1272 struct mlx5_ib_rq *rq, u32 tdn,
175edba8 1273 u32 *qp_flags_en)
0fb2ed66 1274{
175edba8 1275 u8 lb_flag = 0;
0fb2ed66 1276 u32 *in;
1277 void *tirc;
1278 int inlen;
1279 int err;
1280
1281 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1282 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1283 if (!in)
1284 return -ENOMEM;
1285
1286 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1287 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1288 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1289 MLX5_SET(tirc, tirc, transport_domain, tdn);
175edba8 1290 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb 1291 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1292
175edba8
MB		 1293 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1294 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1295
1296 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1297 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1298
1299 if (dev->rep) {
1300 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1301 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1302 }
1303
1304 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
ec9c2fb8 1305
0fb2ed66 1306 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1307
0042f9e4
MB		 1308 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1309 err = mlx5_ib_enable_lb(dev, false, true);
1310
1311 if (err)
1312 destroy_raw_packet_qp_tir(dev, rq, 0);
1313 }
0fb2ed66 1314 kvfree(in);
1315
1316 return err;
1317}
1318
0fb2ed66 1319static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1320 u32 *in, size_t inlen,
0fb2ed66 1321 struct ib_pd *pd)
1322{
1323 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1324 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1325 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1326 struct ib_uobject *uobj = pd->uobject;
1327 struct ib_ucontext *ucontext = uobj->context;
1328 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1329 int err;
1330 u32 tdn = mucontext->tdn;
1331
1332 if (qp->sq.wqe_cnt) {
c2e53b2c 1333 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
0fb2ed66 1334 if (err)
1335 return err;
1336
1337 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1338 if (err)
1339 goto err_destroy_tis;
1340
1341 sq->base.container_mibqp = qp;
1d31e9c0 1342 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1343 }
1344
1345 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1346 rq->base.container_mibqp = qp;
1347
e4cc4fa7
NO		 1348 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1349 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1350 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1351 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
34d57585 1352 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
0fb2ed66 1353 if (err)
1354 goto err_destroy_sq;
1355
0fb2ed66 1356
175edba8 1357 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en);
0fb2ed66 1358 if (err)
1359 goto err_destroy_rq;
1360 }
1361
1362 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1363 rq->base.mqp.qpn;
1364
1365 return 0;
1366
1367err_destroy_rq:
1368 destroy_raw_packet_qp_rq(dev, rq);
1369err_destroy_sq:
1370 if (!qp->sq.wqe_cnt)
1371 return err;
1372 destroy_raw_packet_qp_sq(dev, sq);
1373err_destroy_tis:
1374 destroy_raw_packet_qp_tis(dev, sq);
1375
1376 return err;
1377}
1378
1379static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1380 struct mlx5_ib_qp *qp)
1381{
1382 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1383 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1384 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1385
1386 if (qp->rq.wqe_cnt) {
0042f9e4 1387 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en);
0fb2ed66 1388 destroy_raw_packet_qp_rq(dev, rq);
1389 }
1390
1391 if (qp->sq.wqe_cnt) {
1392 destroy_raw_packet_qp_sq(dev, sq);
1393 destroy_raw_packet_qp_tis(dev, sq);
1394 }
1395}
1396
1397static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1398 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1399{
1400 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1401 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1402
1403 sq->sq = &qp->sq;
1404 rq->rq = &qp->rq;
1405 sq->doorbell = &qp->db;
1406 rq->doorbell = &qp->db;
1407}
1408
28d61370
YH		 1409static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1410{
0042f9e4
MB		 1411 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1412 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1413 mlx5_ib_disable_lb(dev, false, true);
28d61370
YH		 1414 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1415}
1416
1417static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1418 struct ib_pd *pd,
1419 struct ib_qp_init_attr *init_attr,
1420 struct ib_udata *udata)
1421{
1422 struct ib_uobject *uobj = pd->uobject;
1423 struct ib_ucontext *ucontext = uobj->context;
1424 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1425 struct mlx5_ib_create_qp_resp resp = {};
1426 int inlen;
1427 int err;
1428 u32 *in;
1429 void *tirc;
1430 void *hfso;
1431 u32 selected_fields = 0;
2d93fc85 1432 u32 outer_l4;
28d61370
YH		 1433 size_t min_resp_len;
1434 u32 tdn = mucontext->tdn;
1435 struct mlx5_ib_create_qp_rss ucmd = {};
1436 size_t required_cmd_sz;
175edba8 1437 u8 lb_flag = 0;
28d61370
YH		 1438
1439 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1440 return -EOPNOTSUPP;
1441
1442 if (init_attr->create_flags || init_attr->send_cq)
1443 return -EINVAL;
1444
2f5ff264 1445 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1446 if (udata->outlen < min_resp_len)
1447 return -EINVAL;
1448
f95ef6cb 1449 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1450 if (udata->inlen < required_cmd_sz) {
1451 mlx5_ib_dbg(dev, "invalid inlen\n");
1452 return -EINVAL;
1453 }
1454
1455 if (udata->inlen > sizeof(ucmd) &&
1456 !ib_is_udata_cleared(udata, sizeof(ucmd),
1457 udata->inlen - sizeof(ucmd))) {
1458 mlx5_ib_dbg(dev, "inlen is not supported\n");
1459 return -EOPNOTSUPP;
1460 }
1461
1462 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1463 mlx5_ib_dbg(dev, "copy failed\n");
1464 return -EFAULT;
1465 }
1466
1467 if (ucmd.comp_mask) {
1468 mlx5_ib_dbg(dev, "invalid comp mask\n");
1469 return -EOPNOTSUPP;
1470 }
1471
175edba8
MB		 1472 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1473 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1474 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
f95ef6cb
MG		 1475 mlx5_ib_dbg(dev, "invalid flags\n");
1476 return -EOPNOTSUPP;
1477 }
1478
1479 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1480 !tunnel_offload_supported(dev->mdev)) {
1481 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1482 return -EOPNOTSUPP;
1483 }
1484
309fa347
MG		 1485 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1486 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1487 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1488 return -EOPNOTSUPP;
1489 }
1490
175edba8
MB		 1491 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1492 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1493 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1494 }
1495
1496 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1497 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1498 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1499 }
1500
41d902cb 1501 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
28d61370
YH		 1502 if (err) {
1503 mlx5_ib_dbg(dev, "copy failed\n");
1504 return -EINVAL;
1505 }
1506
1507 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1508 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1509 if (!in)
1510 return -ENOMEM;
1511
1512 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1513 MLX5_SET(tirc, tirc, disp_type,
1514 MLX5_TIRC_DISP_TYPE_INDIRECT);
1515 MLX5_SET(tirc, tirc, indirect_table,
1516 init_attr->rwq_ind_tbl->ind_tbl_num);
1517 MLX5_SET(tirc, tirc, transport_domain, tdn);
1518
1519 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1520
1521 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1522 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1523
175edba8
MB		 1524 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1525
309fa347
MG		 1526 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1527 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1528 else
1529 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1530
28d61370
YH		 1531 switch (ucmd.rx_hash_function) {
1532 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1533 {
1534 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1535 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1536
1537 if (len != ucmd.rx_key_len) {
1538 err = -EINVAL;
1539 goto err;
1540 }
1541
1542 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1543 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1544 memcpy(rss_key, ucmd.rx_hash_key, len);
1545 break;
1546 }
1547 default:
1548 err = -EOPNOTSUPP;
1549 goto err;
1550 }
1551
1552 if (!ucmd.rx_hash_fields_mask) {
1553 /* special case when this TIR serves as steering entry without hashing */
1554 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1555 goto create_tir;
1556 err = -EINVAL;
1557 goto err;
1558 }
1559
1560 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1561 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1562 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1563 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1564 err = -EINVAL;
1565 goto err;
1566 }
1567
1568 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1569 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1570 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1571 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1572 MLX5_L3_PROT_TYPE_IPV4);
1573 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1574 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1575 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1576 MLX5_L3_PROT_TYPE_IPV6);
1577
2d93fc85
MB		 1578 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1579 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1580 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1581 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1582 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1583
1584 /* Check that only one l4 protocol is set */
1585 if (outer_l4 & (outer_l4 - 1)) {
28d61370
YH		 1586 err = -EINVAL;
1587 goto err;
1588 }
1589
1590 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1591 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1592 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1593 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1594 MLX5_L4_PROT_TYPE_TCP);
1595 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1596 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1597 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1598 MLX5_L4_PROT_TYPE_UDP);
1599
1600 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1601 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1602 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1603
1604 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1605 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1606 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1607
1608 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1609 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1610 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1611
1612 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1613 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1614 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1615
2d93fc85
MB		 1616 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1617 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1618
28d61370
YH		 1619 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1620
1621create_tir:
1622 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1623
0042f9e4
MB		 1624 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1625 err = mlx5_ib_enable_lb(dev, false, true);
1626
1627 if (err)
1628 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1629 }
1630
28d61370
YH		 1631 if (err)
1632 goto err;
1633
1634 kvfree(in);
1635 /* qpn is reserved for that QP */
1636 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1637 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1638 return 0;
1639
1640err:
1641 kvfree(in);
1642 return err;
1643}
1644
e126ba97
EC		 1645static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1646 struct ib_qp_init_attr *init_attr,
1647 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1648{
1649 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1650 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1651 struct mlx5_core_dev *mdev = dev->mdev;
0625b4ba 1652 struct mlx5_ib_create_qp_resp resp = {};
89ea94a7
MG		 1653 struct mlx5_ib_cq *send_cq;
1654 struct mlx5_ib_cq *recv_cq;
1655 unsigned long flags;
cfb5e088 1656 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1657 struct mlx5_ib_create_qp ucmd;
1658 struct mlx5_ib_qp_base *base;
e7b169f3 1659 int mlx5_st;
cfb5e088 1660 void *qpc;
09a7d9ec
SM		 1661 u32 *in;
1662 int err;
e126ba97
EC		 1663
1664 mutex_init(&qp->mutex);
1665 spin_lock_init(&qp->sq.lock);
1666 spin_lock_init(&qp->rq.lock);
1667
e7b169f3
NO		 1668 mlx5_st = to_mlx5_st(init_attr->qp_type);
1669 if (mlx5_st < 0)
1670 return -EINVAL;
1671
28d61370
YH		 1672 if (init_attr->rwq_ind_tbl) {
1673 if (!udata)
1674 return -ENOSYS;
1675
1676 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1677 return err;
1678 }
1679
f360d88a 1680 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1681 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1682 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1683 return -EINVAL;
1684 } else {
1685 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1686 }
1687 }
1688
051f2630
LR		 1689 if (init_attr->create_flags &
1690 (IB_QP_CREATE_CROSS_CHANNEL |
1691 IB_QP_CREATE_MANAGED_SEND |
1692 IB_QP_CREATE_MANAGED_RECV)) {
1693 if (!MLX5_CAP_GEN(mdev, cd)) {
1694 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1695 return -EINVAL;
1696 }
1697 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1698 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1699 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1700 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1701 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1702 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1703 }
f0313965
ES		 1704
1705 if (init_attr->qp_type == IB_QPT_UD &&
1706 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1707 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1708 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1709 return -EOPNOTSUPP;
1710 }
1711
358e42ea
MD		 1712 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1713 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1714 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1715 return -EOPNOTSUPP;
1716 }
1717 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1718 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1719 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1720 return -EOPNOTSUPP;
1721 }
1722 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1723 }
1724
e126ba97
EC		 1725 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1726 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1727
e4cc4fa7
NO		 1728 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1729 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1730 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1731 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1732 return -EOPNOTSUPP;
1733 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1734 }
1735
e126ba97
EC		 1736 if (pd && pd->uobject) {
1737 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1738 mlx5_ib_dbg(dev, "copy failed\n");
1739 return -EFAULT;
1740 }
1741
cfb5e088
HA		 1742 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1743 &ucmd, udata->inlen, &uidx);
1744 if (err)
1745 return err;
1746
e126ba97
EC		 1747 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1748 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1749 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1750 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1751 !tunnel_offload_supported(mdev)) {
1752 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1753 return -EOPNOTSUPP;
1754 }
175edba8
MB		 1755 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1756 }
1757
1758 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1759 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1760 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1761 return -EOPNOTSUPP;
1762 }
1763 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1764 }
1765
1766 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1767 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1768 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1769 return -EOPNOTSUPP;
1770 }
1771 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
f95ef6cb 1772 }
c2e53b2c
YH		 1773
1774 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1775 if (init_attr->qp_type != IB_QPT_UD ||
1776 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1777 MLX5_CAP_PORT_TYPE_IB) ||
1778 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1779 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1780 return -EOPNOTSUPP;
1781 }
1782
1783 qp->flags |= MLX5_IB_QP_UNDERLAY;
1784 qp->underlay_qpn = init_attr->source_qpn;
1785 }
e126ba97
EC		 1786 } else {
1787 qp->wq_sig = !!wq_signature;
1788 }
1789
c2e53b2c
YH		 1790 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1791 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1792 &qp->raw_packet_qp.rq.base :
1793 &qp->trans_qp.base;
1794
e126ba97
EC		 1795 qp->has_rq = qp_has_rq(init_attr);
1796 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1797 qp, (pd && pd->uobject) ? &ucmd : NULL);
1798 if (err) {
1799 mlx5_ib_dbg(dev, "err %d\n", err);
1800 return err;
1801 }
1802
1803 if (pd) {
1804 if (pd->uobject) {
938fe83c
SM		 1805 __u32 max_wqes =
1806 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1807 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1808 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1809 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1810 mlx5_ib_dbg(dev, "invalid rq params\n");
1811 return -EINVAL;
1812 }
938fe83c 1813 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1814 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1815 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1816 return -EINVAL;
1817 }
b11a4f9c
HE		 1818 if (init_attr->create_flags &
1819 mlx5_ib_create_qp_sqpn_qp1()) {
1820 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1821 return -EINVAL;
1822 }
0fb2ed66 1823 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1824 &resp, &inlen, base);
e126ba97
EC		 1825 if (err)
1826 mlx5_ib_dbg(dev, "err %d\n", err);
1827 } else {
19098df2 1828 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1829 base);
e126ba97
EC		 1830 if (err)
1831 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1832 }
1833
1834 if (err)
1835 return err;
1836 } else {
1b9a07ee 1837 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1838 if (!in)
1839 return -ENOMEM;
1840
1841 qp->create_type = MLX5_QP_EMPTY;
1842 }
1843
1844 if (is_sqp(init_attr->qp_type))
1845 qp->port = init_attr->port_num;
1846
09a7d9ec
SM		 1847 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1848
e7b169f3 1849 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 1850 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1851
1852 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1853 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1854 else
09a7d9ec
SM		 1855 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1856
e126ba97
EC		 1857
1858 if (qp->wq_sig)
09a7d9ec 1859 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1860
f360d88a 1861 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1862 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1863
051f2630 1864 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1865 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1866 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1867 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1868 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1869 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1870
e126ba97
EC		 1871 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1872 int rcqe_sz;
1873 int scqe_sz;
1874
1875 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1876 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1877
1878 if (rcqe_sz == 128)
09a7d9ec 1879 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1880 else
09a7d9ec 1881 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1882
1883 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1884 if (scqe_sz == 128)
09a7d9ec 1885 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1886 else
09a7d9ec 1887 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1888 }
1889 }
1890
1891 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1892 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1893 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1894 }
1895
09a7d9ec 1896 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 1897
3fd3307e 1898 if (qp->sq.wqe_cnt) {
09a7d9ec 1899 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 1900 } else {
09a7d9ec 1901 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 1902 if (init_attr->srq &&
1903 init_attr->srq->srq_type == IB_SRQT_TM)
1904 MLX5_SET(qpc, qpc, offload_type,
1905 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1906 }
e126ba97
EC		 1907
1908 /* Set default resources */
1909 switch (init_attr->qp_type) {
1910 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1911 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1912 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1913 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1914 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1915 break;
1916 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1917 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1918 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1919 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1920 break;
1921 default:
1922 if (init_attr->srq) {
09a7d9ec
SM		 1923 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1924 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1925 } else {
09a7d9ec
SM		 1926 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1927 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1928 }
1929 }
1930
1931 if (init_attr->send_cq)
09a7d9ec 1932 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1933
1934 if (init_attr->recv_cq)
09a7d9ec 1935 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1936
09a7d9ec 1937 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1938
09a7d9ec
SM		 1939 /* 0xffffff means we ask to work with cqe version 0 */
1940 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1941 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1942
f0313965
ES		 1943 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1944 if (init_attr->qp_type == IB_QPT_UD &&
1945 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1946 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1947 qp->flags |= MLX5_IB_QP_LSO;
1948 }
cfb5e088 1949
b1383aa6
NO		 1950 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1951 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1952 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1953 err = -EOPNOTSUPP;
1954 goto err;
1955 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1956 MLX5_SET(qpc, qpc, end_padding_mode,
1957 MLX5_WQ_END_PAD_MODE_ALIGN);
1958 } else {
1959 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1960 }
1961 }
1962
2c292dbb
BP		 1963 if (inlen < 0) {
1964 err = -EINVAL;
1965 goto err;
1966 }
1967
c2e53b2c
YH		 1968 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1969 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 1970 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1971 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2c292dbb 1972 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
0fb2ed66 1973 } else {
1974 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1975 }
1976
e126ba97
EC		 1977 if (err) {
1978 mlx5_ib_dbg(dev, "create qp failed\n");
1979 goto err_create;
1980 }
1981
479163f4 1982 kvfree(in);
e126ba97 1983
19098df2 1984 base->container_mibqp = qp;
1985 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1986
89ea94a7
MG		 1987 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1988 &send_cq, &recv_cq);
1989 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1990 mlx5_ib_lock_cqs(send_cq, recv_cq);
1991 /* Maintain device to QPs access, needed for further handling via reset
1992 * flow
1993 */
1994 list_add_tail(&qp->qps_list, &dev->qp_list);
1995 /* Maintain CQ to QPs access, needed for further handling via reset flow
1996 */
1997 if (send_cq)
1998 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1999 if (recv_cq)
2000 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2001 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2002 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2003
e126ba97
EC		 2004 return 0;
2005
2006err_create:
2007 if (qp->create_type == MLX5_QP_USER)
b037c29a 2008 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 2009 else if (qp->create_type == MLX5_QP_KERNEL)
2010 destroy_qp_kernel(dev, qp);
2011
b1383aa6 2012err:
479163f4 2013 kvfree(in);
e126ba97
EC		 2014 return err;
2015}
2016
2017static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2018 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2019{
2020 if (send_cq) {
2021 if (recv_cq) {
2022 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 2023 spin_lock(&send_cq->lock);
e126ba97
EC		 2024 spin_lock_nested(&recv_cq->lock,
2025 SINGLE_DEPTH_NESTING);
2026 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 2027 spin_lock(&send_cq->lock);
e126ba97
EC		 2028 __acquire(&recv_cq->lock);
2029 } else {
89ea94a7 2030 spin_lock(&recv_cq->lock);
e126ba97
EC		 2031 spin_lock_nested(&send_cq->lock,
2032 SINGLE_DEPTH_NESTING);
2033 }
2034 } else {
89ea94a7 2035 spin_lock(&send_cq->lock);
6a4f139a 2036 __acquire(&recv_cq->lock);
e126ba97
EC		 2037 }
2038 } else if (recv_cq) {
89ea94a7 2039 spin_lock(&recv_cq->lock);
6a4f139a
EC		 2040 __acquire(&send_cq->lock);
2041 } else {
2042 __acquire(&send_cq->lock);
2043 __acquire(&recv_cq->lock);
e126ba97
EC		 2044 }
2045}
2046
2047static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2048 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2049{
2050 if (send_cq) {
2051 if (recv_cq) {
2052 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2053 spin_unlock(&recv_cq->lock);
89ea94a7 2054 spin_unlock(&send_cq->lock);
e126ba97
EC		 2055 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2056 __release(&recv_cq->lock);
89ea94a7 2057 spin_unlock(&send_cq->lock);
e126ba97
EC		 2058 } else {
2059 spin_unlock(&send_cq->lock);
89ea94a7 2060 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2061 }
2062 } else {
6a4f139a 2063 __release(&recv_cq->lock);
89ea94a7 2064 spin_unlock(&send_cq->lock);
e126ba97
EC		 2065 }
2066 } else if (recv_cq) {
6a4f139a 2067 __release(&send_cq->lock);
89ea94a7 2068 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2069 } else {
2070 __release(&recv_cq->lock);
2071 __release(&send_cq->lock);
e126ba97
EC		 2072 }
2073}
2074
2075static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2076{
2077 return to_mpd(qp->ibqp.pd);
2078}
2079
89ea94a7
MG		 2080static void get_cqs(enum ib_qp_type qp_type,
2081 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2082 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2083{
89ea94a7 2084 switch (qp_type) {
e126ba97
EC		 2085 case IB_QPT_XRC_TGT:
2086 *send_cq = NULL;
2087 *recv_cq = NULL;
2088 break;
2089 case MLX5_IB_QPT_REG_UMR:
2090 case IB_QPT_XRC_INI:
89ea94a7 2091 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2092 *recv_cq = NULL;
2093 break;
2094
2095 case IB_QPT_SMI:
d16e91da 2096 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2097 case IB_QPT_RC:
2098 case IB_QPT_UC:
2099 case IB_QPT_UD:
2100 case IB_QPT_RAW_IPV6:
2101 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2102 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2103 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2104 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2105 break;
2106
e126ba97
EC		 2107 case IB_QPT_MAX:
2108 default:
2109 *send_cq = NULL;
2110 *recv_cq = NULL;
2111 break;
2112 }
2113}
2114
ad5f8e96 2115static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2116 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2117 u8 lag_tx_affinity);
ad5f8e96 2118
e126ba97
EC		 2119static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2120{
2121 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2122 struct mlx5_ib_qp_base *base;
89ea94a7 2123 unsigned long flags;
e126ba97
EC		 2124 int err;
2125
28d61370
YH		 2126 if (qp->ibqp.rwq_ind_tbl) {
2127 destroy_rss_raw_qp_tir(dev, qp);
2128 return;
2129 }
2130
c2e53b2c
YH		 2131 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2132 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2133 &qp->raw_packet_qp.rq.base :
2134 &qp->trans_qp.base;
2135
6aec21f6 2136 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2137 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2138 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2139 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2140 MLX5_CMD_OP_2RST_QP, 0,
2141 NULL, &base->mqp);
ad5f8e96 2142 } else {
0680efa2
AV		 2143 struct mlx5_modify_raw_qp_param raw_qp_param = {
2144 .operation = MLX5_CMD_OP_2RST_QP
2145 };
2146
13eab21f 2147 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2148 }
2149 if (err)
427c1e7b 2150 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2151 base->mqp.qpn);
6aec21f6 2152 }
e126ba97 2153
89ea94a7
MG		 2154 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2155 &send_cq, &recv_cq);
2156
2157 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2158 mlx5_ib_lock_cqs(send_cq, recv_cq);
2159 /* del from lists under both locks above to protect reset flow paths */
2160 list_del(&qp->qps_list);
2161 if (send_cq)
2162 list_del(&qp->cq_send_list);
2163
2164 if (recv_cq)
2165 list_del(&qp->cq_recv_list);
e126ba97
EC		 2166
2167 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2168 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2169 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2170 if (send_cq != recv_cq)
19098df2 2171 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2172 NULL);
e126ba97 2173 }
89ea94a7
MG		 2174 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2175 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2176
c2e53b2c
YH		 2177 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2178 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2179 destroy_raw_packet_qp(dev, qp);
2180 } else {
2181 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2182 if (err)
2183 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2184 base->mqp.qpn);
2185 }
e126ba97 2186
e126ba97
EC		 2187 if (qp->create_type == MLX5_QP_KERNEL)
2188 destroy_qp_kernel(dev, qp);
2189 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2190 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2191}
2192
2193static const char *ib_qp_type_str(enum ib_qp_type type)
2194{
2195 switch (type) {
2196 case IB_QPT_SMI:
2197 return "IB_QPT_SMI";
2198 case IB_QPT_GSI:
2199 return "IB_QPT_GSI";
2200 case IB_QPT_RC:
2201 return "IB_QPT_RC";
2202 case IB_QPT_UC:
2203 return "IB_QPT_UC";
2204 case IB_QPT_UD:
2205 return "IB_QPT_UD";
2206 case IB_QPT_RAW_IPV6:
2207 return "IB_QPT_RAW_IPV6";
2208 case IB_QPT_RAW_ETHERTYPE:
2209 return "IB_QPT_RAW_ETHERTYPE";
2210 case IB_QPT_XRC_INI:
2211 return "IB_QPT_XRC_INI";
2212 case IB_QPT_XRC_TGT:
2213 return "IB_QPT_XRC_TGT";
2214 case IB_QPT_RAW_PACKET:
2215 return "IB_QPT_RAW_PACKET";
2216 case MLX5_IB_QPT_REG_UMR:
2217 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2218 case IB_QPT_DRIVER:
2219 return "IB_QPT_DRIVER";
e126ba97
EC		 2220 case IB_QPT_MAX:
2221 default:
2222 return "Invalid QP type";
2223 }
2224}
2225
b4aaa1f0
MS		 2226static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2227 struct ib_qp_init_attr *attr,
2228 struct mlx5_ib_create_qp *ucmd)
2229{
b4aaa1f0
MS		 2230 struct mlx5_ib_qp *qp;
2231 int err = 0;
2232 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2233 void *dctc;
2234
2235 if (!attr->srq || !attr->recv_cq)
2236 return ERR_PTR(-EINVAL);
2237
b4aaa1f0
MS		 2238 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2239 ucmd, sizeof(*ucmd), &uidx);
2240 if (err)
2241 return ERR_PTR(err);
2242
2243 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2244 if (!qp)
2245 return ERR_PTR(-ENOMEM);
2246
2247 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2248 if (!qp->dct.in) {
2249 err = -ENOMEM;
2250 goto err_free;
2251 }
2252
2253 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
776a3906 2254 qp->qp_sub_type = MLX5_IB_QPT_DCT;
b4aaa1f0
MS		 2255 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2256 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2257 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2258 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2259 MLX5_SET(dctc, dctc, user_index, uidx);
2260
2261 qp->state = IB_QPS_RESET;
2262
2263 return &qp->ibqp;
2264err_free:
2265 kfree(qp);
2266 return ERR_PTR(err);
2267}
2268
2269static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2270 struct ib_qp_init_attr *init_attr,
2271 struct mlx5_ib_create_qp *ucmd,
2272 struct ib_udata *udata)
2273{
2274 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2275 int err;
2276
2277 if (!udata)
2278 return -EINVAL;
2279
2280 if (udata->inlen < sizeof(*ucmd)) {
2281 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2282 return -EINVAL;
2283 }
2284 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2285 if (err)
2286 return err;
2287
2288 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2289 init_attr->qp_type = MLX5_IB_QPT_DCI;
2290 } else {
2291 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2292 init_attr->qp_type = MLX5_IB_QPT_DCT;
2293 } else {
2294 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2295 return -EINVAL;
2296 }
2297 }
2298
2299 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2300 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2301 return -EOPNOTSUPP;
2302 }
2303
2304 return 0;
2305}
2306
e126ba97 2307struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2308 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2309 struct ib_udata *udata)
2310{
2311 struct mlx5_ib_dev *dev;
2312 struct mlx5_ib_qp *qp;
2313 u16 xrcdn = 0;
2314 int err;
b4aaa1f0
MS		 2315 struct ib_qp_init_attr mlx_init_attr;
2316 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2317
2318 if (pd) {
2319 dev = to_mdev(pd->device);
0fb2ed66 2320
2321 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2322 if (!pd->uobject) {
2323 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2324 return ERR_PTR(-EINVAL);
2325 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2326 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2327 return ERR_PTR(-EINVAL);
2328 }
2329 }
09f16cf5
MD		 2330 } else {
2331 /* being cautious here */
2332 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2333 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2334 pr_warn("%s: no PD for transport %s\n", __func__,
2335 ib_qp_type_str(init_attr->qp_type));
2336 return ERR_PTR(-EINVAL);
2337 }
2338 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2339 }
2340
b4aaa1f0
MS		 2341 if (init_attr->qp_type == IB_QPT_DRIVER) {
2342 struct mlx5_ib_create_qp ucmd;
2343
2344 init_attr = &mlx_init_attr;
2345 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2346 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2347 if (err)
2348 return ERR_PTR(err);
c32a4f29
MS		 2349
2350 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2351 if (init_attr->cap.max_recv_wr ||
2352 init_attr->cap.max_recv_sge) {
2353 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2354 return ERR_PTR(-EINVAL);
2355 }
776a3906
MS		 2356 } else {
2357 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
c32a4f29 2358 }
b4aaa1f0
MS		 2359 }
2360
e126ba97
EC		 2361 switch (init_attr->qp_type) {
2362 case IB_QPT_XRC_TGT:
2363 case IB_QPT_XRC_INI:
938fe83c 2364 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2365 mlx5_ib_dbg(dev, "XRC not supported\n");
2366 return ERR_PTR(-ENOSYS);
2367 }
2368 init_attr->recv_cq = NULL;
2369 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2370 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2371 init_attr->send_cq = NULL;
2372 }
2373
2374 /* fall through */
0fb2ed66 2375 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2376 case IB_QPT_RC:
2377 case IB_QPT_UC:
2378 case IB_QPT_UD:
2379 case IB_QPT_SMI:
d16e91da 2380 case MLX5_IB_QPT_HW_GSI:
e126ba97 2381 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2382 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2383 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2384 if (!qp)
2385 return ERR_PTR(-ENOMEM);
2386
2387 err = create_qp_common(dev, pd, init_attr, udata, qp);
2388 if (err) {
2389 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2390 kfree(qp);
2391 return ERR_PTR(err);
2392 }
2393
2394 if (is_qp0(init_attr->qp_type))
2395 qp->ibqp.qp_num = 0;
2396 else if (is_qp1(init_attr->qp_type))
2397 qp->ibqp.qp_num = 1;
2398 else
19098df2 2399 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2400
2401 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2402 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2403 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2404 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2405
19098df2 2406 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2407
2408 break;
2409
d16e91da
HE		 2410 case IB_QPT_GSI:
2411 return mlx5_ib_gsi_create_qp(pd, init_attr);
2412
e126ba97
EC		 2413 case IB_QPT_RAW_IPV6:
2414 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2415 case IB_QPT_MAX:
2416 default:
2417 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2418 init_attr->qp_type);
2419 /* Don't support raw QPs */
2420 return ERR_PTR(-EINVAL);
2421 }
2422
b4aaa1f0
MS		 2423 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2424 qp->qp_sub_type = init_attr->qp_type;
2425
e126ba97
EC		 2426 return &qp->ibqp;
2427}
2428
776a3906
MS		 2429static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2430{
2431 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2432
2433 if (mqp->state == IB_QPS_RTR) {
2434 int err;
2435
2436 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2437 if (err) {
2438 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2439 return err;
2440 }
2441 }
2442
2443 kfree(mqp->dct.in);
2444 kfree(mqp);
2445 return 0;
2446}
2447
e126ba97
EC		 2448int mlx5_ib_destroy_qp(struct ib_qp *qp)
2449{
2450 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2451 struct mlx5_ib_qp *mqp = to_mqp(qp);
2452
d16e91da
HE		 2453 if (unlikely(qp->qp_type == IB_QPT_GSI))
2454 return mlx5_ib_gsi_destroy_qp(qp);
2455
776a3906
MS		 2456 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2457 return mlx5_ib_destroy_dct(mqp);
2458
e126ba97
EC		 2459 destroy_qp_common(dev, mqp);
2460
2461 kfree(mqp);
2462
2463 return 0;
2464}
2465
2466static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2467 int attr_mask)
2468{
2469 u32 hw_access_flags = 0;
2470 u8 dest_rd_atomic;
2471 u32 access_flags;
2472
2473 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2474 dest_rd_atomic = attr->max_dest_rd_atomic;
2475 else
19098df2 2476 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2477
2478 if (attr_mask & IB_QP_ACCESS_FLAGS)
2479 access_flags = attr->qp_access_flags;
2480 else
19098df2 2481 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2482
2483 if (!dest_rd_atomic)
2484 access_flags &= IB_ACCESS_REMOTE_WRITE;
2485
2486 if (access_flags & IB_ACCESS_REMOTE_READ)
2487 hw_access_flags |= MLX5_QP_BIT_RRE;
2488 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2489 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2490 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2491 hw_access_flags |= MLX5_QP_BIT_RWE;
2492
2493 return cpu_to_be32(hw_access_flags);
2494}
2495
2496enum {
2497 MLX5_PATH_FLAG_FL = 1 << 0,
2498 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2499 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2500};
2501
2502static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2503{
4f32ac2e 2504 if (rate == IB_RATE_PORT_CURRENT)
e126ba97 2505 return 0;
4f32ac2e
DG		 2506
2507 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
e126ba97 2508 return -EINVAL;
e126ba97 2509
4f32ac2e
DG		 2510 while (rate != IB_RATE_PORT_CURRENT &&
2511 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2512 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2513 --rate;
2514
2515 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
e126ba97
EC		 2516}
2517
75850d0b 2518static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2519 struct mlx5_ib_sq *sq, u8 sl)
2520{
2521 void *in;
2522 void *tisc;
2523 int inlen;
2524 int err;
2525
2526 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2527 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2528 if (!in)
2529 return -ENOMEM;
2530
2531 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2532
2533 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2534 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2535
2536 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2537
2538 kvfree(in);
2539
2540 return err;
2541}
2542
13eab21f
AH		 2543static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2544 struct mlx5_ib_sq *sq, u8 tx_affinity)
2545{
2546 void *in;
2547 void *tisc;
2548 int inlen;
2549 int err;
2550
2551 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2552 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2553 if (!in)
2554 return -ENOMEM;
2555
2556 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2557
2558 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2559 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2560
2561 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2562
2563 kvfree(in);
2564
2565 return err;
2566}
2567
75850d0b 2568static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2569 const struct rdma_ah_attr *ah,
e126ba97 2570 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2571 u32 path_flags, const struct ib_qp_attr *attr,
2572 bool alt)
e126ba97 2573{
d8966fcd 2574 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2575 int err;
ed88451e 2576 enum ib_gid_type gid_type;
d8966fcd
DC		 2577 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2578 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2579
e126ba97 2580 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2581 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2582 attr->pkey_index);
e126ba97 2583
d8966fcd
DC		 2584 if (ah_flags & IB_AH_GRH) {
2585 if (grh->sgid_index >=
938fe83c 2586 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2587 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2588 grh->sgid_index,
938fe83c 2589 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2590 return -EINVAL;
2591 }
2811ba51 2592 }
44c58487
DC		 2593
2594 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2595 if (!(ah_flags & IB_AH_GRH))
2811ba51 2596 return -EINVAL;
47ec3866 2597
44c58487 2598 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2599 if (qp->ibqp.qp_type == IB_QPT_RC ||
2600 qp->ibqp.qp_type == IB_QPT_UC ||
2601 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2602 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
47ec3866
PP		 2603 path->udp_sport =
2604 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
d8966fcd 2605 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
47ec3866 2606 gid_type = ah->grh.sgid_attr->gid_type;
ed88451e 2607 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2608 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2609 } else {
d3ae2bde
NO		 2610 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2611 path->fl_free_ar |=
2612 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2613 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2614 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2615 if (ah_flags & IB_AH_GRH)
2811ba51 2616 path->grh_mlid |= 1 << 7;
d8966fcd 2617 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2618 }
2619
d8966fcd
DC		 2620 if (ah_flags & IB_AH_GRH) {
2621 path->mgid_index = grh->sgid_index;
2622 path->hop_limit = grh->hop_limit;
e126ba97 2623 path->tclass_flowlabel =
d8966fcd
DC		 2624 cpu_to_be32((grh->traffic_class << 20) |
2625 (grh->flow_label));
2626 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2627 }
2628
d8966fcd 2629 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2630 if (err < 0)
2631 return err;
2632 path->static_rate = err;
2633 path->port = port;
2634
e126ba97 2635 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2636 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2637
75850d0b 2638 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2639 return modify_raw_packet_eth_prio(dev->mdev,
2640 &qp->raw_packet_qp.sq,
d8966fcd 2641 sl & 0xf);
75850d0b 2642
e126ba97
EC		 2643 return 0;
2644}
2645
2646static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2647 [MLX5_QP_STATE_INIT] = {
2648 [MLX5_QP_STATE_INIT] = {
2649 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2650 MLX5_QP_OPTPAR_RAE |
2651 MLX5_QP_OPTPAR_RWE |
2652 MLX5_QP_OPTPAR_PKEY_INDEX |
2653 MLX5_QP_OPTPAR_PRI_PORT,
2654 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2655 MLX5_QP_OPTPAR_PKEY_INDEX |
2656 MLX5_QP_OPTPAR_PRI_PORT,
2657 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2658 MLX5_QP_OPTPAR_Q_KEY |
2659 MLX5_QP_OPTPAR_PRI_PORT,
2660 },
2661 [MLX5_QP_STATE_RTR] = {
2662 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2663 MLX5_QP_OPTPAR_RRE |
2664 MLX5_QP_OPTPAR_RAE |
2665 MLX5_QP_OPTPAR_RWE |
2666 MLX5_QP_OPTPAR_PKEY_INDEX,
2667 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2668 MLX5_QP_OPTPAR_RWE |
2669 MLX5_QP_OPTPAR_PKEY_INDEX,
2670 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2671 MLX5_QP_OPTPAR_Q_KEY,
2672 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2673 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2674 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2675 MLX5_QP_OPTPAR_RRE |
2676 MLX5_QP_OPTPAR_RAE |
2677 MLX5_QP_OPTPAR_RWE |
2678 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2679 },
2680 },
2681 [MLX5_QP_STATE_RTR] = {
2682 [MLX5_QP_STATE_RTS] = {
2683 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2684 MLX5_QP_OPTPAR_RRE |
2685 MLX5_QP_OPTPAR_RAE |
2686 MLX5_QP_OPTPAR_RWE |
2687 MLX5_QP_OPTPAR_PM_STATE |
2688 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2689 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2690 MLX5_QP_OPTPAR_RWE |
2691 MLX5_QP_OPTPAR_PM_STATE,
2692 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2693 },
2694 },
2695 [MLX5_QP_STATE_RTS] = {
2696 [MLX5_QP_STATE_RTS] = {
2697 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2698 MLX5_QP_OPTPAR_RAE |
2699 MLX5_QP_OPTPAR_RWE |
2700 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2701 MLX5_QP_OPTPAR_PM_STATE |
2702 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2703 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2704 MLX5_QP_OPTPAR_PM_STATE |
2705 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2706 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2707 MLX5_QP_OPTPAR_SRQN |
2708 MLX5_QP_OPTPAR_CQN_RCV,
2709 },
2710 },
2711 [MLX5_QP_STATE_SQER] = {
2712 [MLX5_QP_STATE_RTS] = {
2713 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2714 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2715 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2716 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2717 MLX5_QP_OPTPAR_RWE |
2718 MLX5_QP_OPTPAR_RAE |
2719 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2720 },
2721 },
2722};
2723
2724static int ib_nr_to_mlx5_nr(int ib_mask)
2725{
2726 switch (ib_mask) {
2727 case IB_QP_STATE:
2728 return 0;
2729 case IB_QP_CUR_STATE:
2730 return 0;
2731 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2732 return 0;
2733 case IB_QP_ACCESS_FLAGS:
2734 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2735 MLX5_QP_OPTPAR_RAE;
2736 case IB_QP_PKEY_INDEX:
2737 return MLX5_QP_OPTPAR_PKEY_INDEX;
2738 case IB_QP_PORT:
2739 return MLX5_QP_OPTPAR_PRI_PORT;
2740 case IB_QP_QKEY:
2741 return MLX5_QP_OPTPAR_Q_KEY;
2742 case IB_QP_AV:
2743 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2744 MLX5_QP_OPTPAR_PRI_PORT;
2745 case IB_QP_PATH_MTU:
2746 return 0;
2747 case IB_QP_TIMEOUT:
2748 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2749 case IB_QP_RETRY_CNT:
2750 return MLX5_QP_OPTPAR_RETRY_COUNT;
2751 case IB_QP_RNR_RETRY:
2752 return MLX5_QP_OPTPAR_RNR_RETRY;
2753 case IB_QP_RQ_PSN:
2754 return 0;
2755 case IB_QP_MAX_QP_RD_ATOMIC:
2756 return MLX5_QP_OPTPAR_SRA_MAX;
2757 case IB_QP_ALT_PATH:
2758 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2759 case IB_QP_MIN_RNR_TIMER:
2760 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2761 case IB_QP_SQ_PSN:
2762 return 0;
2763 case IB_QP_MAX_DEST_RD_ATOMIC:
2764 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2765 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2766 case IB_QP_PATH_MIG_STATE:
2767 return MLX5_QP_OPTPAR_PM_STATE;
2768 case IB_QP_CAP:
2769 return 0;
2770 case IB_QP_DEST_QPN:
2771 return 0;
2772 }
2773 return 0;
2774}
2775
2776static int ib_mask_to_mlx5_opt(int ib_mask)
2777{
2778 int result = 0;
2779 int i;
2780
2781 for (i = 0; i < 8 * sizeof(int); i++) {
2782 if ((1 << i) & ib_mask)
2783 result |= ib_nr_to_mlx5_nr(1 << i);
2784 }
2785
2786 return result;
2787}
2788
34d57585
YH		 2789static int modify_raw_packet_qp_rq(
2790 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2791 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 2792{
2793 void *in;
2794 void *rqc;
2795 int inlen;
2796 int err;
2797
2798 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2799 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2800 if (!in)
2801 return -ENOMEM;
2802
2803 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
34d57585 2804 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 2805
2806 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2807 MLX5_SET(rqc, rqc, state, new_state);
2808
eb49ab0c
AV		 2809 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2810 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2811 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2812 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2813 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2814 } else
2815 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2816 dev->ib_dev.name);
2817 }
2818
2819 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2820 if (err)
2821 goto out;
2822
2823 rq->state = new_state;
2824
2825out:
2826 kvfree(in);
2827 return err;
2828}
2829
2830static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2831 struct mlx5_ib_sq *sq,
2832 int new_state,
2833 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2834{
7d29f349 2835 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 2836 struct mlx5_rate_limit old_rl = ibqp->rl;
2837 struct mlx5_rate_limit new_rl = old_rl;
2838 bool new_rate_added = false;
7d29f349 2839 u16 rl_index = 0;
ad5f8e96 2840 void *in;
2841 void *sqc;
2842 int inlen;
2843 int err;
2844
2845 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2846 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2847 if (!in)
2848 return -ENOMEM;
2849
2850 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2851
2852 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2853 MLX5_SET(sqc, sqc, state, new_state);
2854
7d29f349
BW		 2855 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2856 if (new_state != MLX5_SQC_STATE_RDY)
2857 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2858 __func__);
2859 else
61147f39 2860 new_rl = raw_qp_param->rl;
7d29f349
BW		 2861 }
2862
61147f39
BW		 2863 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2864 if (new_rl.rate) {
2865 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 2866 if (err) {
61147f39
BW		 2867 pr_err("Failed configuring rate limit(err %d): \
2868 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2869 err, new_rl.rate, new_rl.max_burst_sz,
2870 new_rl.typical_pkt_sz);
2871
7d29f349
BW		 2872 goto out;
2873 }
61147f39 2874 new_rate_added = true;
7d29f349
BW		 2875 }
2876
2877 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 2878 /* index 0 means no limit */
7d29f349
BW		 2879 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2880 }
2881
ad5f8e96 2882 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2883 if (err) {
2884 /* Remove new rate from table if failed */
61147f39
BW		 2885 if (new_rate_added)
2886 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 2887 goto out;
7d29f349
BW		 2888 }
2889
2890 /* Only remove the old rate after new rate was set */
61147f39
BW		 2891 if ((old_rl.rate &&
2892 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
7d29f349 2893 (new_state != MLX5_SQC_STATE_RDY))
61147f39 2894 mlx5_rl_remove_rate(dev, &old_rl);
ad5f8e96 2895
61147f39 2896 ibqp->rl = new_rl;
ad5f8e96 2897 sq->state = new_state;
2898
2899out:
2900 kvfree(in);
2901 return err;
2902}
2903
2904static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2905 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2906 u8 tx_affinity)
ad5f8e96 2907{
2908 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2909 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2910 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2911 int modify_rq = !!qp->rq.wqe_cnt;
2912 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2913 int rq_state;
2914 int sq_state;
2915 int err;
2916
0680efa2 2917 switch (raw_qp_param->operation) {
ad5f8e96 2918 case MLX5_CMD_OP_RST2INIT_QP:
2919 rq_state = MLX5_RQC_STATE_RDY;
2920 sq_state = MLX5_SQC_STATE_RDY;
2921 break;
2922 case MLX5_CMD_OP_2ERR_QP:
2923 rq_state = MLX5_RQC_STATE_ERR;
2924 sq_state = MLX5_SQC_STATE_ERR;
2925 break;
2926 case MLX5_CMD_OP_2RST_QP:
2927 rq_state = MLX5_RQC_STATE_RST;
2928 sq_state = MLX5_SQC_STATE_RST;
2929 break;
ad5f8e96 2930 case MLX5_CMD_OP_RTR2RTS_QP:
2931 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2932 if (raw_qp_param->set_mask ==
2933 MLX5_RAW_QP_RATE_LIMIT) {
2934 modify_rq = 0;
2935 sq_state = sq->state;
2936 } else {
2937 return raw_qp_param->set_mask ? -EINVAL : 0;
2938 }
2939 break;
2940 case MLX5_CMD_OP_INIT2INIT_QP:
2941 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2942 if (raw_qp_param->set_mask)
2943 return -EINVAL;
2944 else
2945 return 0;
ad5f8e96 2946 default:
2947 WARN_ON(1);
2948 return -EINVAL;
2949 }
2950
7d29f349 2951 if (modify_rq) {
34d57585
YH		 2952 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
2953 qp->ibqp.pd);
ad5f8e96 2954 if (err)
2955 return err;
2956 }
2957
7d29f349 2958 if (modify_sq) {
13eab21f
AH		 2959 if (tx_affinity) {
2960 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2961 tx_affinity);
2962 if (err)
2963 return err;
2964 }
2965
7d29f349 2966 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2967 }
ad5f8e96 2968
2969 return 0;
2970}
2971
c6a21c38
MD		 2972static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
2973 struct mlx5_ib_pd *pd,
2974 struct mlx5_ib_qp_base *qp_base,
2975 u8 port_num)
2976{
2977 struct mlx5_ib_ucontext *ucontext = NULL;
2978 unsigned int tx_port_affinity;
2979
2980 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
2981 ucontext = to_mucontext(pd->ibpd.uobject->context);
2982
2983 if (ucontext) {
2984 tx_port_affinity = (unsigned int)atomic_add_return(
2985 1, &ucontext->tx_port_affinity) %
2986 MLX5_MAX_PORTS +
2987 1;
2988 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
2989 tx_port_affinity, qp_base->mqp.qpn, ucontext);
2990 } else {
2991 tx_port_affinity =
2992 (unsigned int)atomic_add_return(
2993 1, &dev->roce[port_num].tx_port_affinity) %
2994 MLX5_MAX_PORTS +
2995 1;
2996 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
2997 tx_port_affinity, qp_base->mqp.qpn);
2998 }
2999
3000 return tx_port_affinity;
3001}
3002
e126ba97
EC		 3003static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3004 const struct ib_qp_attr *attr, int attr_mask,
61147f39
BW		 3005 enum ib_qp_state cur_state, enum ib_qp_state new_state,
3006 const struct mlx5_ib_modify_qp *ucmd)
e126ba97 3007{
427c1e7b 3008 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3009 [MLX5_QP_STATE_RST] = {
3010 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3011 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3012 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3013 },
3014 [MLX5_QP_STATE_INIT] = {
3015 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3016 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3017 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3018 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3019 },
3020 [MLX5_QP_STATE_RTR] = {
3021 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3022 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3023 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3024 },
3025 [MLX5_QP_STATE_RTS] = {
3026 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3027 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3028 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3029 },
3030 [MLX5_QP_STATE_SQD] = {
3031 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3032 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3033 },
3034 [MLX5_QP_STATE_SQER] = {
3035 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3036 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3037 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3038 },
3039 [MLX5_QP_STATE_ERR] = {
3040 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3041 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3042 }
3043 };
3044
e126ba97
EC		 3045 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3046 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 3047 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 3048 struct mlx5_ib_cq *send_cq, *recv_cq;
3049 struct mlx5_qp_context *context;
e126ba97 3050 struct mlx5_ib_pd *pd;
eb49ab0c 3051 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 3052 enum mlx5_qp_state mlx5_cur, mlx5_new;
3053 enum mlx5_qp_optpar optpar;
e126ba97
EC		 3054 int mlx5_st;
3055 int err;
427c1e7b 3056 u16 op;
13eab21f 3057 u8 tx_affinity = 0;
e126ba97 3058
55de9a77
LR		 3059 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3060 qp->qp_sub_type : ibqp->qp_type);
3061 if (mlx5_st < 0)
3062 return -EINVAL;
3063
1a412fb1
SM		 3064 context = kzalloc(sizeof(*context), GFP_KERNEL);
3065 if (!context)
e126ba97
EC		 3066 return -ENOMEM;
3067
c6a21c38 3068 pd = get_pd(qp);
55de9a77 3069 context->flags = cpu_to_be32(mlx5_st << 16);
e126ba97
EC		 3070
3071 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3072 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3073 } else {
3074 switch (attr->path_mig_state) {
3075 case IB_MIG_MIGRATED:
3076 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3077 break;
3078 case IB_MIG_REARM:
3079 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3080 break;
3081 case IB_MIG_ARMED:
3082 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3083 break;
3084 }
3085 }
3086
13eab21f
AH		 3087 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3088 if ((ibqp->qp_type == IB_QPT_RC) ||
3089 (ibqp->qp_type == IB_QPT_UD &&
3090 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3091 (ibqp->qp_type == IB_QPT_UC) ||
3092 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3093 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3094 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3095 if (mlx5_lag_is_active(dev->mdev)) {
7fd8aefb 3096 u8 p = mlx5_core_native_port_num(dev->mdev);
c6a21c38 3097 tx_affinity = get_tx_affinity(dev, pd, base, p);
13eab21f
AH		 3098 context->flags |= cpu_to_be32(tx_affinity << 24);
3099 }
3100 }
3101 }
3102
d16e91da 3103 if (is_sqp(ibqp->qp_type)) {
e126ba97 3104 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 3105 } else if ((ibqp->qp_type == IB_QPT_UD &&
3106 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 3107 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3108 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3109 } else if (attr_mask & IB_QP_PATH_MTU) {
3110 if (attr->path_mtu < IB_MTU_256 ||
3111 attr->path_mtu > IB_MTU_4096) {
3112 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3113 err = -EINVAL;
3114 goto out;
3115 }
938fe83c
SM		 3116 context->mtu_msgmax = (attr->path_mtu << 5) |
3117 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 3118 }
3119
3120 if (attr_mask & IB_QP_DEST_QPN)
3121 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3122
3123 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 3124 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 3125
3126 /* todo implement counter_index functionality */
3127
3128 if (is_sqp(ibqp->qp_type))
3129 context->pri_path.port = qp->port;
3130
3131 if (attr_mask & IB_QP_PORT)
3132 context->pri_path.port = attr->port_num;
3133
3134 if (attr_mask & IB_QP_AV) {
75850d0b 3135 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 3136 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 3137 attr_mask, 0, attr, false);
e126ba97
EC		 3138 if (err)
3139 goto out;
3140 }
3141
3142 if (attr_mask & IB_QP_TIMEOUT)
3143 context->pri_path.ackto_lt |= attr->timeout << 3;
3144
3145 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 3146 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3147 &context->alt_path,
f879ee8d
AS		 3148 attr->alt_port_num,
3149 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3150 0, attr, true);
e126ba97
EC		 3151 if (err)
3152 goto out;
3153 }
3154
89ea94a7
MG		 3155 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3156 &send_cq, &recv_cq);
e126ba97
EC		 3157
3158 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3159 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3160 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3161 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3162
3163 if (attr_mask & IB_QP_RNR_RETRY)
3164 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3165
3166 if (attr_mask & IB_QP_RETRY_CNT)
3167 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3168
3169 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3170 if (attr->max_rd_atomic)
3171 context->params1 |=
3172 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3173 }
3174
3175 if (attr_mask & IB_QP_SQ_PSN)
3176 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3177
3178 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3179 if (attr->max_dest_rd_atomic)
3180 context->params2 |=
3181 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3182 }
3183
3184 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3185 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3186
3187 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3188 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3189
3190 if (attr_mask & IB_QP_RQ_PSN)
3191 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3192
3193 if (attr_mask & IB_QP_QKEY)
3194 context->qkey = cpu_to_be32(attr->qkey);
3195
3196 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3197 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3198
0837e86a
MB		 3199 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3200 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3201 qp->port) - 1;
c2e53b2c
YH		 3202
3203 /* Underlay port should be used - index 0 function per port */
3204 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3205 port_num = 0;
3206
eb49ab0c 3207 mibport = &dev->port[port_num];
0837e86a 3208 context->qp_counter_set_usr_page |=
e1f24a79 3209 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3210 }
3211
e126ba97
EC		 3212 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3213 context->sq_crq_size |= cpu_to_be16(1 << 4);
3214
b11a4f9c
HE		 3215 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3216 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3217
3218 mlx5_cur = to_mlx5_state(cur_state);
3219 mlx5_new = to_mlx5_state(new_state);
e126ba97 3220
427c1e7b 3221 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3222 !optab[mlx5_cur][mlx5_new]) {
3223 err = -EINVAL;
427c1e7b 3224 goto out;
5d414b17 3225 }
427c1e7b 3226
3227 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3228 optpar = ib_mask_to_mlx5_opt(attr_mask);
3229 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3230
c2e53b2c
YH		 3231 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3232 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3233 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3234
3235 raw_qp_param.operation = op;
eb49ab0c 3236 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3237 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3238 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3239 }
7d29f349
BW		 3240
3241 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3242 raw_qp_param.rl.rate = attr->rate_limit;
3243
3244 if (ucmd->burst_info.max_burst_sz) {
3245 if (attr->rate_limit &&
3246 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3247 raw_qp_param.rl.max_burst_sz =
3248 ucmd->burst_info.max_burst_sz;
3249 } else {
3250 err = -EINVAL;
3251 goto out;
3252 }
3253 }
3254
3255 if (ucmd->burst_info.typical_pkt_sz) {
3256 if (attr->rate_limit &&
3257 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3258 raw_qp_param.rl.typical_pkt_sz =
3259 ucmd->burst_info.typical_pkt_sz;
3260 } else {
3261 err = -EINVAL;
3262 goto out;
3263 }
3264 }
3265
7d29f349
BW		 3266 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3267 }
3268
13eab21f 3269 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3270 } else {
1a412fb1 3271 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3272 &base->mqp);
0680efa2
AV		 3273 }
3274
e126ba97
EC		 3275 if (err)
3276 goto out;
3277
3278 qp->state = new_state;
3279
3280 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3281 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3282 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3283 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3284 if (attr_mask & IB_QP_PORT)
3285 qp->port = attr->port_num;
3286 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3287 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3288
3289 /*
3290 * If we moved a kernel QP to RESET, clean up all old CQ
3291 * entries and reinitialize the QP.
3292 */
75a45982
LR		 3293 if (new_state == IB_QPS_RESET &&
3294 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 3295 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3296 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3297 if (send_cq != recv_cq)
19098df2 3298 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3299
3300 qp->rq.head = 0;
3301 qp->rq.tail = 0;
3302 qp->sq.head = 0;
3303 qp->sq.tail = 0;
3304 qp->sq.cur_post = 0;
3305 qp->sq.last_poll = 0;
3306 qp->db.db[MLX5_RCV_DBR] = 0;
3307 qp->db.db[MLX5_SND_DBR] = 0;
3308 }
3309
3310out:
1a412fb1 3311 kfree(context);
e126ba97
EC		 3312 return err;
3313}
3314
c32a4f29
MS		 3315static inline bool is_valid_mask(int mask, int req, int opt)
3316{
3317 if ((mask & req) != req)
3318 return false;
3319
3320 if (mask & ~(req | opt))
3321 return false;
3322
3323 return true;
3324}
3325
3326/* check valid transition for driver QP types
3327 * for now the only QP type that this function supports is DCI
3328 */
3329static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3330 enum ib_qp_attr_mask attr_mask)
3331{
3332 int req = IB_QP_STATE;
3333 int opt = 0;
3334
99ed748e
MS		 3335 if (new_state == IB_QPS_RESET) {
3336 return is_valid_mask(attr_mask, req, opt);
3337 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
c32a4f29
MS		 3338 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3339 return is_valid_mask(attr_mask, req, opt);
3340 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3341 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3342 return is_valid_mask(attr_mask, req, opt);
3343 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3344 req |= IB_QP_PATH_MTU;
3345 opt = IB_QP_PKEY_INDEX;
3346 return is_valid_mask(attr_mask, req, opt);
3347 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3348 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3349 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3350 opt = IB_QP_MIN_RNR_TIMER;
3351 return is_valid_mask(attr_mask, req, opt);
3352 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3353 opt = IB_QP_MIN_RNR_TIMER;
3354 return is_valid_mask(attr_mask, req, opt);
3355 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3356 return is_valid_mask(attr_mask, req, opt);
3357 }
3358 return false;
3359}
3360
776a3906
MS		 3361/* mlx5_ib_modify_dct: modify a DCT QP
3362 * valid transitions are:
3363 * RESET to INIT: must set access_flags, pkey_index and port
3364 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3365 * mtu, gid_index and hop_limit
3366 * Other transitions and attributes are illegal
3367 */
3368static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3369 int attr_mask, struct ib_udata *udata)
3370{
3371 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3372 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3373 enum ib_qp_state cur_state, new_state;
3374 int err = 0;
3375 int required = IB_QP_STATE;
3376 void *dctc;
3377
3378 if (!(attr_mask & IB_QP_STATE))
3379 return -EINVAL;
3380
3381 cur_state = qp->state;
3382 new_state = attr->qp_state;
3383
3384 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3385 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3386 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3387 if (!is_valid_mask(attr_mask, required, 0))
3388 return -EINVAL;
3389
3390 if (attr->port_num == 0 ||
3391 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3392 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3393 attr->port_num, dev->num_ports);
3394 return -EINVAL;
3395 }
3396 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3397 MLX5_SET(dctc, dctc, rre, 1);
3398 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3399 MLX5_SET(dctc, dctc, rwe, 1);
3400 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3401 if (!mlx5_ib_dc_atomic_is_supported(dev))
3402 return -EOPNOTSUPP;
3403 MLX5_SET(dctc, dctc, rae, 1);
3404 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3405 }
3406 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3407 MLX5_SET(dctc, dctc, port, attr->port_num);
3408 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3409
3410 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3411 struct mlx5_ib_modify_qp_resp resp = {};
3412 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3413 sizeof(resp.dctn);
3414
3415 if (udata->outlen < min_resp_len)
3416 return -EINVAL;
3417 resp.response_length = min_resp_len;
3418
3419 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3420 if (!is_valid_mask(attr_mask, required, 0))
3421 return -EINVAL;
3422 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3423 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3424 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3425 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3426 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3427 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3428
3429 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3430 MLX5_ST_SZ_BYTES(create_dct_in));
3431 if (err)
3432 return err;
3433 resp.dctn = qp->dct.mdct.mqp.qpn;
3434 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3435 if (err) {
3436 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3437 return err;
3438 }
3439 } else {
3440 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3441 return -EINVAL;
3442 }
3443 if (err)
3444 qp->state = IB_QPS_ERR;
3445 else
3446 qp->state = new_state;
3447 return err;
3448}
3449
e126ba97
EC		 3450int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3451 int attr_mask, struct ib_udata *udata)
3452{
3453 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3454 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 3455 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 3456 enum ib_qp_type qp_type;
e126ba97 3457 enum ib_qp_state cur_state, new_state;
61147f39 3458 size_t required_cmd_sz;
e126ba97
EC		 3459 int err = -EINVAL;
3460 int port;
2811ba51 3461 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 3462
28d61370
YH		 3463 if (ibqp->rwq_ind_tbl)
3464 return -ENOSYS;
3465
61147f39
BW		 3466 if (udata && udata->inlen) {
3467 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3468 sizeof(ucmd.reserved);
3469 if (udata->inlen < required_cmd_sz)
3470 return -EINVAL;
3471
3472 if (udata->inlen > sizeof(ucmd) &&
3473 !ib_is_udata_cleared(udata, sizeof(ucmd),
3474 udata->inlen - sizeof(ucmd)))
3475 return -EOPNOTSUPP;
3476
3477 if (ib_copy_from_udata(&ucmd, udata,
3478 min(udata->inlen, sizeof(ucmd))))
3479 return -EFAULT;
3480
3481 if (ucmd.comp_mask ||
3482 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3483 memchr_inv(&ucmd.burst_info.reserved, 0,
3484 sizeof(ucmd.burst_info.reserved)))
3485 return -EOPNOTSUPP;
3486 }
3487
d16e91da
HE		 3488 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3489 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3490
c32a4f29
MS		 3491 if (ibqp->qp_type == IB_QPT_DRIVER)
3492 qp_type = qp->qp_sub_type;
3493 else
3494 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3495 IB_QPT_GSI : ibqp->qp_type;
3496
776a3906
MS		 3497 if (qp_type == MLX5_IB_QPT_DCT)
3498 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
d16e91da 3499
e126ba97
EC		 3500 mutex_lock(&qp->mutex);
3501
3502 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3503 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3504
2811ba51
AS		 3505 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3506 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3507 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3508 }
3509
c2e53b2c
YH		 3510 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3511 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3512 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3513 attr_mask);
3514 goto out;
3515 }
3516 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29
MS		 3517 qp_type != MLX5_IB_QPT_DCI &&
3518 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 3519 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3520 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3521 goto out;
c32a4f29
MS		 3522 } else if (qp_type == MLX5_IB_QPT_DCI &&
3523 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3524 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3525 cur_state, new_state, qp_type, attr_mask);
3526 goto out;
158abf86 3527 }
e126ba97
EC		 3528
3529 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3530 (attr->port_num == 0 ||
508562d6 3531 attr->port_num > dev->num_ports)) {
158abf86
HE		 3532 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3533 attr->port_num, dev->num_ports);
e126ba97 3534 goto out;
158abf86 3535 }
e126ba97
EC		 3536
3537 if (attr_mask & IB_QP_PKEY_INDEX) {
3538 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3539 if (attr->pkey_index >=
158abf86
HE		 3540 dev->mdev->port_caps[port - 1].pkey_table_len) {
3541 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3542 attr->pkey_index);
e126ba97 3543 goto out;
158abf86 3544 }
e126ba97
EC		 3545 }
3546
3547 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3548 attr->max_rd_atomic >
158abf86
HE		 3549 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3550 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3551 attr->max_rd_atomic);
e126ba97 3552 goto out;
158abf86 3553 }
e126ba97
EC		 3554
3555 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3556 attr->max_dest_rd_atomic >
158abf86
HE		 3557 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3558 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3559 attr->max_dest_rd_atomic);
e126ba97 3560 goto out;
158abf86 3561 }
e126ba97
EC		 3562
3563 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3564 err = 0;
3565 goto out;
3566 }
3567
61147f39
BW		 3568 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3569 new_state, &ucmd);
e126ba97
EC		 3570
3571out:
3572 mutex_unlock(&qp->mutex);
3573 return err;
3574}
3575
3576static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3577{
3578 struct mlx5_ib_cq *cq;
3579 unsigned cur;
3580
3581 cur = wq->head - wq->tail;
3582 if (likely(cur + nreq < wq->max_post))
3583 return 0;
3584
3585 cq = to_mcq(ib_cq);
3586 spin_lock(&cq->lock);
3587 cur = wq->head - wq->tail;
3588 spin_unlock(&cq->lock);
3589
3590 return cur + nreq >= wq->max_post;
3591}
3592
3593static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3594 u64 remote_addr, u32 rkey)
3595{
3596 rseg->raddr = cpu_to_be64(remote_addr);
3597 rseg->rkey = cpu_to_be32(rkey);
3598 rseg->reserved = 0;
3599}
3600
f0313965 3601static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
f696bf6d 3602 const struct ib_send_wr *wr, void *qend,
f0313965
ES		 3603 struct mlx5_ib_qp *qp, int *size)
3604{
3605 void *seg = eseg;
3606
3607 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3608
3609 if (wr->send_flags & IB_SEND_IP_CSUM)
3610 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3611 MLX5_ETH_WQE_L4_CSUM;
3612
3613 seg += sizeof(struct mlx5_wqe_eth_seg);
3614 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3615
3616 if (wr->opcode == IB_WR_LSO) {
3617 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3618 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3619 u64 left, leftlen, copysz;
3620 void *pdata = ud_wr->header;
3621
3622 left = ud_wr->hlen;
3623 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3624 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3625
3626 /*
3627 * check if there is space till the end of queue, if yes,
3628 * copy all in one shot, otherwise copy till the end of queue,
3629 * rollback and than the copy the left
3630 */
2b31f7ae 3631 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3632 copysz = min_t(u64, leftlen, left);
3633
3634 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3635
3636 if (likely(copysz > size_of_inl_hdr_start)) {
3637 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3638 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3639 }
3640
3641 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3642 seg = mlx5_get_send_wqe(qp, 0);
3643 left -= copysz;
3644 pdata += copysz;
3645 memcpy(seg, pdata, left);
3646 seg += ALIGN(left, 16);
3647 *size += ALIGN(left, 16) / 16;
3648 }
3649 }
3650
3651 return seg;
3652}
3653
e126ba97 3654static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
f696bf6d 3655 const struct ib_send_wr *wr)
e126ba97 3656{
e622f2f4
CH		 3657 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3658 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3659 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3660}
3661
3662static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3663{
3664 dseg->byte_count = cpu_to_be32(sg->length);
3665 dseg->lkey = cpu_to_be32(sg->lkey);
3666 dseg->addr = cpu_to_be64(sg->addr);
3667}
3668
31616255 3669static u64 get_xlt_octo(u64 bytes)
e126ba97 3670{
31616255
AK		 3671 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3672 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3673}
3674
3675static __be64 frwr_mkey_mask(void)
3676{
3677 u64 result;
3678
3679 result = MLX5_MKEY_MASK_LEN |
3680 MLX5_MKEY_MASK_PAGE_SIZE |
3681 MLX5_MKEY_MASK_START_ADDR |
3682 MLX5_MKEY_MASK_EN_RINVAL |
3683 MLX5_MKEY_MASK_KEY |
3684 MLX5_MKEY_MASK_LR |
3685 MLX5_MKEY_MASK_LW |
3686 MLX5_MKEY_MASK_RR |
3687 MLX5_MKEY_MASK_RW |
3688 MLX5_MKEY_MASK_A |
3689 MLX5_MKEY_MASK_SMALL_FENCE |
3690 MLX5_MKEY_MASK_FREE;
3691
3692 return cpu_to_be64(result);
3693}
3694
e6631814
SG		 3695static __be64 sig_mkey_mask(void)
3696{
3697 u64 result;
3698
3699 result = MLX5_MKEY_MASK_LEN |
3700 MLX5_MKEY_MASK_PAGE_SIZE |
3701 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3702 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3703 MLX5_MKEY_MASK_EN_RINVAL |
3704 MLX5_MKEY_MASK_KEY |
3705 MLX5_MKEY_MASK_LR |
3706 MLX5_MKEY_MASK_LW |
3707 MLX5_MKEY_MASK_RR |
3708 MLX5_MKEY_MASK_RW |
3709 MLX5_MKEY_MASK_SMALL_FENCE |
3710 MLX5_MKEY_MASK_FREE |
3711 MLX5_MKEY_MASK_BSF_EN;
3712
3713 return cpu_to_be64(result);
3714}
3715
8a187ee5 3716static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
064e5262 3717 struct mlx5_ib_mr *mr, bool umr_inline)
8a187ee5 3718{
31616255 3719 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3720
3721 memset(umr, 0, sizeof(*umr));
b005d316 3722
8a187ee5 3723 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
064e5262
IB		 3724 if (umr_inline)
3725 umr->flags |= MLX5_UMR_INLINE;
31616255 3726 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3727 umr->mkey_mask = frwr_mkey_mask();
3728}
3729
dd01e66a 3730static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3731{
3732 memset(umr, 0, sizeof(*umr));
dd01e66a 3733 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3734 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3735}
3736
31616255 3737static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3738{
3739 u64 result;
3740
31616255 3741 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3742 MLX5_MKEY_MASK_FREE;
3743
968e78dd
HE		 3744 return cpu_to_be64(result);
3745}
3746
31616255 3747static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3748{
3749 u64 result;
3750
3751 result = MLX5_MKEY_MASK_FREE;
3752
3753 return cpu_to_be64(result);
3754}
3755
56e11d62
NO		 3756static __be64 get_umr_update_translation_mask(void)
3757{
3758 u64 result;
3759
3760 result = MLX5_MKEY_MASK_LEN |
3761 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3762 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3763
3764 return cpu_to_be64(result);
3765}
3766
31616255 3767static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3768{
3769 u64 result;
3770
31616255
AK		 3771 result = MLX5_MKEY_MASK_LR |
3772 MLX5_MKEY_MASK_LW |
56e11d62 3773 MLX5_MKEY_MASK_RR |
31616255
AK		 3774 MLX5_MKEY_MASK_RW;
3775
3776 if (atomic)
3777 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3778
3779 return cpu_to_be64(result);
3780}
3781
3782static __be64 get_umr_update_pd_mask(void)
3783{
3784 u64 result;
3785
31616255 3786 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3787
3788 return cpu_to_be64(result);
3789}
3790
c8d75a98
MD		 3791static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3792{
3793 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3794 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3795 (mask & MLX5_MKEY_MASK_A &&
3796 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3797 return -EPERM;
3798 return 0;
3799}
3800
3801static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3802 struct mlx5_wqe_umr_ctrl_seg *umr,
f696bf6d 3803 const struct ib_send_wr *wr, int atomic)
e126ba97 3804{
f696bf6d 3805 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3806
3807 memset(umr, 0, sizeof(*umr));
3808
968e78dd
HE		 3809 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3810 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3811 else
3812 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3813
31616255
AK		 3814 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3815 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3816 u64 offset = get_xlt_octo(umrwr->offset);
3817
3818 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3819 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3820 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3821 }
31616255
AK		 3822 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3823 umr->mkey_mask |= get_umr_update_translation_mask();
3824 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3825 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3826 umr->mkey_mask |= get_umr_update_pd_mask();
3827 }
3828 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3829 umr->mkey_mask |= get_umr_enable_mr_mask();
3830 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3831 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3832
3833 if (!wr->num_sge)
968e78dd 3834 umr->flags |= MLX5_UMR_INLINE;
c8d75a98
MD		 3835
3836 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
e126ba97
EC		 3837}
3838
3839static u8 get_umr_flags(int acc)
3840{
3841 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3842 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3843 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3844 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3845 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3846}
3847
8a187ee5
SG		 3848static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3849 struct mlx5_ib_mr *mr,
3850 u32 key, int access)
3851{
3852 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3853
3854 memset(seg, 0, sizeof(*seg));
b005d316 3855
ec22eb53 3856 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3857 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3858 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3859 /* KLMs take twice the size of MTTs */
3860 ndescs *= 2;
3861
3862 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3863 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3864 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3865 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3866 seg->len = cpu_to_be64(mr->ibmr.length);
3867 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3868}
3869
dd01e66a 3870static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3871{
3872 memset(seg, 0, sizeof(*seg));
dd01e66a 3873 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3874}
3875
f696bf6d
BVA		 3876static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
3877 const struct ib_send_wr *wr)
e126ba97 3878{
f696bf6d 3879 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3880
e126ba97 3881 memset(seg, 0, sizeof(*seg));
31616255 3882 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3883 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3884
968e78dd 3885 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3886 if (umrwr->pd)
3887 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3888 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3889 !umrwr->length)
3890 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3891
3892 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3893 seg->len = cpu_to_be64(umrwr->length);
3894 seg->log2_page_size = umrwr->page_shift;
746b5583 3895 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3896 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3897}
3898
8a187ee5
SG		 3899static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3900 struct mlx5_ib_mr *mr,
3901 struct mlx5_ib_pd *pd)
3902{
3903 int bcount = mr->desc_size * mr->ndescs;
3904
3905 dseg->addr = cpu_to_be64(mr->desc_map);
3906 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3907 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3908}
3909
064e5262
IB		 3910static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3911 struct mlx5_ib_mr *mr, int mr_list_size)
3912{
3913 void *qend = qp->sq.qend;
3914 void *addr = mr->descs;
3915 int copy;
3916
3917 if (unlikely(seg + mr_list_size > qend)) {
3918 copy = qend - seg;
3919 memcpy(seg, addr, copy);
3920 addr += copy;
3921 mr_list_size -= copy;
3922 seg = mlx5_get_send_wqe(qp, 0);
3923 }
3924 memcpy(seg, addr, mr_list_size);
3925 seg += mr_list_size;
3926}
3927
f696bf6d 3928static __be32 send_ieth(const struct ib_send_wr *wr)
e126ba97
EC		 3929{
3930 switch (wr->opcode) {
3931 case IB_WR_SEND_WITH_IMM:
3932 case IB_WR_RDMA_WRITE_WITH_IMM:
3933 return wr->ex.imm_data;
3934
3935 case IB_WR_SEND_WITH_INV:
3936 return cpu_to_be32(wr->ex.invalidate_rkey);
3937
3938 default:
3939 return 0;
3940 }
3941}
3942
3943static u8 calc_sig(void *wqe, int size)
3944{
3945 u8 *p = wqe;
3946 u8 res = 0;
3947 int i;
3948
3949 for (i = 0; i < size; i++)
3950 res ^= p[i];
3951
3952 return ~res;
3953}
3954
3955static u8 wq_sig(void *wqe)
3956{
3957 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3958}
3959
f696bf6d 3960static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
e126ba97
EC		 3961 void *wqe, int *sz)
3962{
3963 struct mlx5_wqe_inline_seg *seg;
3964 void *qend = qp->sq.qend;
3965 void *addr;
3966 int inl = 0;
3967 int copy;
3968 int len;
3969 int i;
3970
3971 seg = wqe;
3972 wqe += sizeof(*seg);
3973 for (i = 0; i < wr->num_sge; i++) {
3974 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3975 len = wr->sg_list[i].length;
3976 inl += len;
3977
3978 if (unlikely(inl > qp->max_inline_data))
3979 return -ENOMEM;
3980
3981 if (unlikely(wqe + len > qend)) {
3982 copy = qend - wqe;
3983 memcpy(wqe, addr, copy);
3984 addr += copy;
3985 len -= copy;
3986 wqe = mlx5_get_send_wqe(qp, 0);
3987 }
3988 memcpy(wqe, addr, len);
3989 wqe += len;
3990 }
3991
3992 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3993
3994 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3995
3996 return 0;
3997}
3998
e6631814
SG		 3999static u16 prot_field_size(enum ib_signature_type type)
4000{
4001 switch (type) {
4002 case IB_SIG_TYPE_T10_DIF:
4003 return MLX5_DIF_SIZE;
4004 default:
4005 return 0;
4006 }
4007}
4008
4009static u8 bs_selector(int block_size)
4010{
4011 switch (block_size) {
4012 case 512: return 0x1;
4013 case 520: return 0x2;
4014 case 4096: return 0x3;
4015 case 4160: return 0x4;
4016 case 1073741824: return 0x5;
4017 default: return 0;
4018 }
4019}
4020
78eda2bb
SG		 4021static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4022 struct mlx5_bsf_inl *inl)
e6631814 4023{
142537f4
SG		 4024 /* Valid inline section and allow BSF refresh */
4025 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4026 MLX5_BSF_REFRESH_DIF);
4027 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4028 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 4029 /* repeating block */
4030 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4031 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4032 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 4033
78eda2bb
SG		 4034 if (domain->sig.dif.ref_remap)
4035 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 4036
78eda2bb
SG		 4037 if (domain->sig.dif.app_escape) {
4038 if (domain->sig.dif.ref_escape)
4039 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4040 else
4041 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 4042 }
4043
78eda2bb
SG		 4044 inl->dif_app_bitmask_check =
4045 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 4046}
4047
4048static int mlx5_set_bsf(struct ib_mr *sig_mr,
4049 struct ib_sig_attrs *sig_attrs,
4050 struct mlx5_bsf *bsf, u32 data_size)
4051{
4052 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4053 struct mlx5_bsf_basic *basic = &bsf->basic;
4054 struct ib_sig_domain *mem = &sig_attrs->mem;
4055 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 4056
c7f44fbd 4057 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 4058
4059 /* Basic + Extended + Inline */
4060 basic->bsf_size_sbs = 1 << 7;
4061 /* Input domain check byte mask */
4062 basic->check_byte_mask = sig_attrs->check_mask;
4063 basic->raw_data_size = cpu_to_be32(data_size);
4064
4065 /* Memory domain */
e6631814 4066 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 4067 case IB_SIG_TYPE_NONE:
4068 break;
e6631814 4069 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 4070 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4071 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4072 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4073 break;
4074 default:
4075 return -EINVAL;
4076 }
e6631814 4077
78eda2bb
SG		 4078 /* Wire domain */
4079 switch (sig_attrs->wire.sig_type) {
4080 case IB_SIG_TYPE_NONE:
4081 break;
4082 case IB_SIG_TYPE_T10_DIF:
e6631814 4083 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 4084 mem->sig_type == wire->sig_type) {
e6631814 4085 /* Same block structure */
142537f4 4086 basic->bsf_size_sbs |= 1 << 4;
e6631814 4087 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 4088 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 4089 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 4090 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 4091 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 4092 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 4093 } else
4094 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4095
142537f4 4096 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 4097 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 4098 break;
e6631814
SG		 4099 default:
4100 return -EINVAL;
4101 }
4102
4103 return 0;
4104}
4105
f696bf6d 4106static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
e622f2f4 4107 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 4108{
e622f2f4
CH		 4109 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4110 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4111 struct mlx5_bsf *bsf;
e622f2f4
CH		 4112 u32 data_len = wr->wr.sg_list->length;
4113 u32 data_key = wr->wr.sg_list->lkey;
4114 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 4115 int ret;
4116 int wqe_size;
4117
e622f2f4
CH		 4118 if (!wr->prot ||
4119 (data_key == wr->prot->lkey &&
4120 data_va == wr->prot->addr &&
4121 data_len == wr->prot->length)) {
e6631814
SG		 4122 /**
4123 * Source domain doesn't contain signature information
5c273b16 4124 * or data and protection are interleaved in memory.
e6631814
SG		 4125 * So need construct:
4126 * ------------------
4127 * | data_klm |
4128 * ------------------
4129 * | BSF |
4130 * ------------------
4131 **/
4132 struct mlx5_klm *data_klm = *seg;
4133
4134 data_klm->bcount = cpu_to_be32(data_len);
4135 data_klm->key = cpu_to_be32(data_key);
4136 data_klm->va = cpu_to_be64(data_va);
4137 wqe_size = ALIGN(sizeof(*data_klm), 64);
4138 } else {
4139 /**
4140 * Source domain contains signature information
4141 * So need construct a strided block format:
4142 * ---------------------------
4143 * | stride_block_ctrl |
4144 * ---------------------------
4145 * | data_klm |
4146 * ---------------------------
4147 * | prot_klm |
4148 * ---------------------------
4149 * | BSF |
4150 * ---------------------------
4151 **/
4152 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4153 struct mlx5_stride_block_entry *data_sentry;
4154 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 4155 u32 prot_key = wr->prot->lkey;
4156 u64 prot_va = wr->prot->addr;
e6631814
SG		 4157 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4158 int prot_size;
4159
4160 sblock_ctrl = *seg;
4161 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4162 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4163
4164 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4165 if (!prot_size) {
4166 pr_err("Bad block size given: %u\n", block_size);
4167 return -EINVAL;
4168 }
4169 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4170 prot_size);
4171 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4172 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4173 sblock_ctrl->num_entries = cpu_to_be16(2);
4174
4175 data_sentry->bcount = cpu_to_be16(block_size);
4176 data_sentry->key = cpu_to_be32(data_key);
4177 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 4178 data_sentry->stride = cpu_to_be16(block_size);
4179
e6631814
SG		 4180 prot_sentry->bcount = cpu_to_be16(prot_size);
4181 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 4182 prot_sentry->va = cpu_to_be64(prot_va);
4183 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 4184
e6631814
SG		 4185 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4186 sizeof(*prot_sentry), 64);
4187 }
4188
4189 *seg += wqe_size;
4190 *size += wqe_size / 16;
4191 if (unlikely((*seg == qp->sq.qend)))
4192 *seg = mlx5_get_send_wqe(qp, 0);
4193
4194 bsf = *seg;
4195 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4196 if (ret)
4197 return -EINVAL;
4198
4199 *seg += sizeof(*bsf);
4200 *size += sizeof(*bsf) / 16;
4201 if (unlikely((*seg == qp->sq.qend)))
4202 *seg = mlx5_get_send_wqe(qp, 0);
4203
4204 return 0;
4205}
4206
4207static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
f696bf6d 4208 const struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 4209 u32 length, u32 pdn)
4210{
e622f2f4 4211 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4212 u32 sig_key = sig_mr->rkey;
d5436ba0 4213 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 4214
4215 memset(seg, 0, sizeof(*seg));
4216
e622f2f4 4217 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 4218 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 4219 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 4220 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 4221 MLX5_MKEY_BSF_EN | pdn);
4222 seg->len = cpu_to_be64(length);
31616255 4223 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 4224 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4225}
4226
4227static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 4228 u32 size)
e6631814
SG		 4229{
4230 memset(umr, 0, sizeof(*umr));
4231
4232 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 4233 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 4234 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4235 umr->mkey_mask = sig_mkey_mask();
4236}
4237
4238
f696bf6d
BVA		 4239static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4240 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 4241{
f696bf6d 4242 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
e622f2f4 4243 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 4244 u32 pdn = get_pd(qp)->pdn;
31616255 4245 u32 xlt_size;
e6631814
SG		 4246 int region_len, ret;
4247
e622f2f4
CH		 4248 if (unlikely(wr->wr.num_sge != 1) ||
4249 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 4250 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4251 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 4252 return -EINVAL;
4253
4254 /* length of the protected region, data + protection */
e622f2f4
CH		 4255 region_len = wr->wr.sg_list->length;
4256 if (wr->prot &&
4257 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4258 wr->prot->addr != wr->wr.sg_list->addr ||
4259 wr->prot->length != wr->wr.sg_list->length))
4260 region_len += wr->prot->length;
e6631814
SG		 4261
4262 /**
4263 * KLM octoword size - if protection was provided
4264 * then we use strided block format (3 octowords),
4265 * else we use single KLM (1 octoword)
4266 **/
31616255 4267 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 4268
31616255 4269 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 4270 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4271 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4272 if (unlikely((*seg == qp->sq.qend)))
4273 *seg = mlx5_get_send_wqe(qp, 0);
4274
31616255 4275 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 4276 *seg += sizeof(struct mlx5_mkey_seg);
4277 *size += sizeof(struct mlx5_mkey_seg) / 16;
4278 if (unlikely((*seg == qp->sq.qend)))
4279 *seg = mlx5_get_send_wqe(qp, 0);
4280
4281 ret = set_sig_data_segment(wr, qp, seg, size);
4282 if (ret)
4283 return ret;
4284
d5436ba0 4285 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 4286 return 0;
4287}
4288
4289static int set_psv_wr(struct ib_sig_domain *domain,
4290 u32 psv_idx, void **seg, int *size)
4291{
4292 struct mlx5_seg_set_psv *psv_seg = *seg;
4293
4294 memset(psv_seg, 0, sizeof(*psv_seg));
4295 psv_seg->psv_num = cpu_to_be32(psv_idx);
4296 switch (domain->sig_type) {
78eda2bb
SG		 4297 case IB_SIG_TYPE_NONE:
4298 break;
e6631814
SG		 4299 case IB_SIG_TYPE_T10_DIF:
4300 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4301 domain->sig.dif.app_tag);
4302 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 4303 break;
e6631814 4304 default:
12bbf1ea
LR		 4305 pr_err("Bad signature type (%d) is given.\n",
4306 domain->sig_type);
4307 return -EINVAL;
e6631814
SG		 4308 }
4309
78eda2bb
SG		 4310 *seg += sizeof(*psv_seg);
4311 *size += sizeof(*psv_seg) / 16;
4312
e6631814
SG		 4313 return 0;
4314}
4315
8a187ee5 4316static int set_reg_wr(struct mlx5_ib_qp *qp,
f696bf6d 4317 const struct ib_reg_wr *wr,
8a187ee5
SG		 4318 void **seg, int *size)
4319{
4320 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4321 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
064e5262
IB		 4322 int mr_list_size = mr->ndescs * mr->desc_size;
4323 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
8a187ee5
SG		 4324
4325 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4326 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4327 "Invalid IB_SEND_INLINE send flag\n");
4328 return -EINVAL;
4329 }
4330
064e5262 4331 set_reg_umr_seg(*seg, mr, umr_inline);
8a187ee5
SG		 4332 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4333 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4334 if (unlikely((*seg == qp->sq.qend)))
4335 *seg = mlx5_get_send_wqe(qp, 0);
4336
4337 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4338 *seg += sizeof(struct mlx5_mkey_seg);
4339 *size += sizeof(struct mlx5_mkey_seg) / 16;
4340 if (unlikely((*seg == qp->sq.qend)))
4341 *seg = mlx5_get_send_wqe(qp, 0);
4342
064e5262
IB		 4343 if (umr_inline) {
4344 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4345 *size += get_xlt_octo(mr_list_size);
4346 } else {
4347 set_reg_data_seg(*seg, mr, pd);
4348 *seg += sizeof(struct mlx5_wqe_data_seg);
4349 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4350 }
8a187ee5
SG		 4351 return 0;
4352}
4353
dd01e66a 4354static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 4355{
dd01e66a 4356 set_linv_umr_seg(*seg);
e126ba97
EC		 4357 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4358 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4359 if (unlikely((*seg == qp->sq.qend)))
4360 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 4361 set_linv_mkey_seg(*seg);
e126ba97
EC		 4362 *seg += sizeof(struct mlx5_mkey_seg);
4363 *size += sizeof(struct mlx5_mkey_seg) / 16;
4364 if (unlikely((*seg == qp->sq.qend)))
4365 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 4366}
4367
4368static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4369{
4370 __be32 *p = NULL;
4371 int tidx = idx;
4372 int i, j;
4373
4374 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4375 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4376 if ((i & 0xf) == 0) {
4377 void *buf = mlx5_get_send_wqe(qp, tidx);
4378 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4379 p = buf;
4380 j = 0;
4381 }
4382 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4383 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4384 be32_to_cpu(p[j + 3]));
4385 }
4386}
4387
7bb1fafc 4388static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
6e5eadac 4389 struct mlx5_wqe_ctrl_seg **ctrl,
f696bf6d 4390 const struct ib_send_wr *wr, unsigned *idx,
7bb1fafc 4391 int *size, int nreq, bool send_signaled, bool solicited)
6e5eadac 4392{
b2a232d2
LR		 4393 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4394 return -ENOMEM;
6e5eadac
SG		 4395
4396 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4397 *seg = mlx5_get_send_wqe(qp, *idx);
4398 *ctrl = *seg;
4399 *(uint32_t *)(*seg + 8) = 0;
4400 (*ctrl)->imm = send_ieth(wr);
4401 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
7bb1fafc
BVA		 4402 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4403 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
6e5eadac
SG		 4404
4405 *seg += sizeof(**ctrl);
4406 *size = sizeof(**ctrl) / 16;
4407
b2a232d2 4408 return 0;
6e5eadac
SG		 4409}
4410
7bb1fafc
BVA		 4411static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4412 struct mlx5_wqe_ctrl_seg **ctrl,
4413 const struct ib_send_wr *wr, unsigned *idx,
4414 int *size, int nreq)
4415{
4416 return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq,
4417 wr->send_flags & IB_SEND_SIGNALED,
4418 wr->send_flags & IB_SEND_SOLICITED);
4419}
4420
6e5eadac
SG		 4421static void finish_wqe(struct mlx5_ib_qp *qp,
4422 struct mlx5_wqe_ctrl_seg *ctrl,
4423 u8 size, unsigned idx, u64 wr_id,
6e8484c5 4424 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 4425{
4426 u8 opmod = 0;
4427
4428 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4429 mlx5_opcode | ((u32)opmod << 24));
19098df2 4430 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4431 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4432 if (unlikely(qp->wq_sig))
4433 ctrl->signature = wq_sig(ctrl);
4434
4435 qp->sq.wrid[idx] = wr_id;
4436 qp->sq.w_list[idx].opcode = mlx5_opcode;
4437 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4438 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4439 qp->sq.w_list[idx].next = qp->sq.cur_post;
4440}
4441
d34ac5cd
BVA		 4442static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4443 const struct ib_send_wr **bad_wr, bool drain)
e126ba97
EC		 4444{
4445 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4446 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4447 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4448 struct mlx5_ib_qp *qp;
e6631814 4449 struct mlx5_ib_mr *mr;
e126ba97
EC		 4450 struct mlx5_wqe_data_seg *dpseg;
4451 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4452 struct mlx5_bf *bf;
e126ba97 4453 int uninitialized_var(size);
d16e91da 4454 void *qend;
e126ba97 4455 unsigned long flags;
e126ba97
EC		 4456 unsigned idx;
4457 int err = 0;
e126ba97
EC		 4458 int num_sge;
4459 void *seg;
4460 int nreq;
4461 int i;
4462 u8 next_fence = 0;
e126ba97
EC		 4463 u8 fence;
4464
6c75520f
PP		 4465 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4466 !drain)) {
4467 *bad_wr = wr;
4468 return -EIO;
4469 }
4470
d16e91da
HE		 4471 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4472 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4473
4474 qp = to_mqp(ibqp);
5fe9dec0 4475 bf = &qp->bf;
d16e91da
HE		 4476 qend = qp->sq.qend;
4477
e126ba97
EC		 4478 spin_lock_irqsave(&qp->sq.lock, flags);
4479
4480 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4481 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4482 mlx5_ib_warn(dev, "\n");
4483 err = -EINVAL;
4484 *bad_wr = wr;
4485 goto out;
4486 }
4487
6e5eadac
SG		 4488 num_sge = wr->num_sge;
4489 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4490 mlx5_ib_warn(dev, "\n");
24be409b 4491 err = -EINVAL;
e126ba97
EC		 4492 *bad_wr = wr;
4493 goto out;
4494 }
4495
6e5eadac
SG		 4496 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4497 if (err) {
e126ba97
EC		 4498 mlx5_ib_warn(dev, "\n");
4499 err = -ENOMEM;
4500 *bad_wr = wr;
4501 goto out;
4502 }
4503
6e8484c5
MG		 4504 if (wr->opcode == IB_WR_LOCAL_INV ||
4505 wr->opcode == IB_WR_REG_MR) {
4506 fence = dev->umr_fence;
4507 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4508 } else if (wr->send_flags & IB_SEND_FENCE) {
4509 if (qp->next_fence)
4510 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4511 else
4512 fence = MLX5_FENCE_MODE_FENCE;
4513 } else {
4514 fence = qp->next_fence;
4515 }
4516
e126ba97
EC		 4517 switch (ibqp->qp_type) {
4518 case IB_QPT_XRC_INI:
4519 xrc = seg;
e126ba97
EC		 4520 seg += sizeof(*xrc);
4521 size += sizeof(*xrc) / 16;
4522 /* fall through */
4523 case IB_QPT_RC:
4524 switch (wr->opcode) {
4525 case IB_WR_RDMA_READ:
4526 case IB_WR_RDMA_WRITE:
4527 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4528 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4529 rdma_wr(wr)->rkey);
f241e749 4530 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4531 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4532 break;
4533
4534 case IB_WR_ATOMIC_CMP_AND_SWP:
4535 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4536 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4537 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4538 err = -ENOSYS;
4539 *bad_wr = wr;
4540 goto out;
e126ba97
EC		 4541
4542 case IB_WR_LOCAL_INV:
e126ba97
EC		 4543 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4544 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 4545 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 4546 num_sge = 0;
4547 break;
4548
8a187ee5 4549 case IB_WR_REG_MR:
8a187ee5
SG		 4550 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4551 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4552 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4553 if (err) {
4554 *bad_wr = wr;
4555 goto out;
4556 }
4557 num_sge = 0;
4558 break;
4559
e6631814
SG		 4560 case IB_WR_REG_SIG_MR:
4561 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4562 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4563
4564 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4565 err = set_sig_umr_wr(wr, qp, &seg, &size);
4566 if (err) {
4567 mlx5_ib_warn(dev, "\n");
4568 *bad_wr = wr;
4569 goto out;
4570 }
4571
6e8484c5
MG		 4572 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4573 fence, MLX5_OPCODE_UMR);
e6631814
SG		 4574 /*
4575 * SET_PSV WQEs are not signaled and solicited
4576 * on error
4577 */
7bb1fafc
BVA		 4578 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4579 &size, nreq, false, true);
e6631814
SG		 4580 if (err) {
4581 mlx5_ib_warn(dev, "\n");
4582 err = -ENOMEM;
4583 *bad_wr = wr;
4584 goto out;
4585 }
4586
e622f2f4 4587 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4588 mr->sig->psv_memory.psv_idx, &seg,
4589 &size);
4590 if (err) {
4591 mlx5_ib_warn(dev, "\n");
4592 *bad_wr = wr;
4593 goto out;
4594 }
4595
6e8484c5
MG		 4596 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4597 fence, MLX5_OPCODE_SET_PSV);
7bb1fafc
BVA		 4598 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4599 &size, nreq, false, true);
e6631814
SG		 4600 if (err) {
4601 mlx5_ib_warn(dev, "\n");
4602 err = -ENOMEM;
4603 *bad_wr = wr;
4604 goto out;
4605 }
4606
e622f2f4 4607 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4608 mr->sig->psv_wire.psv_idx, &seg,
4609 &size);
4610 if (err) {
4611 mlx5_ib_warn(dev, "\n");
4612 *bad_wr = wr;
4613 goto out;
4614 }
4615
6e8484c5
MG		 4616 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4617 fence, MLX5_OPCODE_SET_PSV);
4618 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4619 num_sge = 0;
4620 goto skip_psv;
4621
e126ba97
EC		 4622 default:
4623 break;
4624 }
4625 break;
4626
4627 case IB_QPT_UC:
4628 switch (wr->opcode) {
4629 case IB_WR_RDMA_WRITE:
4630 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4631 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4632 rdma_wr(wr)->rkey);
e126ba97
EC		 4633 seg += sizeof(struct mlx5_wqe_raddr_seg);
4634 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4635 break;
4636
4637 default:
4638 break;
4639 }
4640 break;
4641
e126ba97 4642 case IB_QPT_SMI:
1e0e50b6
MG		 4643 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4644 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4645 err = -EPERM;
4646 *bad_wr = wr;
4647 goto out;
4648 }
f6b1ee34 4649 /* fall through */
d16e91da 4650 case MLX5_IB_QPT_HW_GSI:
e126ba97 4651 set_datagram_seg(seg, wr);
f241e749 4652 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4653 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4654 if (unlikely((seg == qend)))
4655 seg = mlx5_get_send_wqe(qp, 0);
4656 break;
f0313965
ES		 4657 case IB_QPT_UD:
4658 set_datagram_seg(seg, wr);
4659 seg += sizeof(struct mlx5_wqe_datagram_seg);
4660 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4661
4662 if (unlikely((seg == qend)))
4663 seg = mlx5_get_send_wqe(qp, 0);
4664
4665 /* handle qp that supports ud offload */
4666 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4667 struct mlx5_wqe_eth_pad *pad;
e126ba97 4668
f0313965
ES		 4669 pad = seg;
4670 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4671 seg += sizeof(struct mlx5_wqe_eth_pad);
4672 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4673
4674 seg = set_eth_seg(seg, wr, qend, qp, &size);
4675
4676 if (unlikely((seg == qend)))
4677 seg = mlx5_get_send_wqe(qp, 0);
4678 }
4679 break;
e126ba97
EC		 4680 case MLX5_IB_QPT_REG_UMR:
4681 if (wr->opcode != MLX5_IB_WR_UMR) {
4682 err = -EINVAL;
4683 mlx5_ib_warn(dev, "bad opcode\n");
4684 goto out;
4685 }
4686 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4687 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
c8d75a98
MD		 4688 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4689 if (unlikely(err))
4690 goto out;
e126ba97
EC		 4691 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4692 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4693 if (unlikely((seg == qend)))
4694 seg = mlx5_get_send_wqe(qp, 0);
4695 set_reg_mkey_segment(seg, wr);
4696 seg += sizeof(struct mlx5_mkey_seg);
4697 size += sizeof(struct mlx5_mkey_seg) / 16;
4698 if (unlikely((seg == qend)))
4699 seg = mlx5_get_send_wqe(qp, 0);
4700 break;
4701
4702 default:
4703 break;
4704 }
4705
4706 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4707 int uninitialized_var(sz);
4708
4709 err = set_data_inl_seg(qp, wr, seg, &sz);
4710 if (unlikely(err)) {
4711 mlx5_ib_warn(dev, "\n");
4712 *bad_wr = wr;
4713 goto out;
4714 }
e126ba97
EC		 4715 size += sz;
4716 } else {
4717 dpseg = seg;
4718 for (i = 0; i < num_sge; i++) {
4719 if (unlikely(dpseg == qend)) {
4720 seg = mlx5_get_send_wqe(qp, 0);
4721 dpseg = seg;
4722 }
4723 if (likely(wr->sg_list[i].length)) {
4724 set_data_ptr_seg(dpseg, wr->sg_list + i);
4725 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4726 dpseg++;
4727 }
4728 }
4729 }
4730
6e8484c5
MG		 4731 qp->next_fence = next_fence;
4732 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4733 mlx5_ib_opcode[wr->opcode]);
e6631814 4734skip_psv:
e126ba97
EC		 4735 if (0)
4736 dump_wqe(qp, idx, size);
4737 }
4738
4739out:
4740 if (likely(nreq)) {
4741 qp->sq.head += nreq;
4742
4743 /* Make sure that descriptors are written before
4744 * updating doorbell record and ringing the doorbell
4745 */
4746 wmb();
4747
4748 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4749
ada388f7
EC		 4750 /* Make sure doorbell record is visible to the HCA before
4751 * we hit doorbell */
4752 wmb();
4753
5fe9dec0
EC		 4754 /* currently we support only regular doorbells */
4755 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4756 /* Make sure doorbells don't leak out of SQ spinlock
4757 * and reach the HCA out of order.
4758 */
4759 mmiowb();
e126ba97 4760 bf->offset ^= bf->buf_size;
e126ba97
EC		 4761 }
4762
4763 spin_unlock_irqrestore(&qp->sq.lock, flags);
4764
4765 return err;
4766}
4767
d34ac5cd
BVA		 4768int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4769 const struct ib_send_wr **bad_wr)
d0e84c0a
YH		 4770{
4771 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4772}
4773
e126ba97
EC		 4774static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4775{
4776 sig->signature = calc_sig(sig, size);
4777}
4778
d34ac5cd
BVA		 4779static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4780 const struct ib_recv_wr **bad_wr, bool drain)
e126ba97
EC		 4781{
4782 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4783 struct mlx5_wqe_data_seg *scat;
4784 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4785 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4786 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4787 unsigned long flags;
4788 int err = 0;
4789 int nreq;
4790 int ind;
4791 int i;
4792
6c75520f
PP		 4793 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4794 !drain)) {
4795 *bad_wr = wr;
4796 return -EIO;
4797 }
4798
d16e91da
HE		 4799 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4800 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4801
e126ba97
EC		 4802 spin_lock_irqsave(&qp->rq.lock, flags);
4803
4804 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4805
4806 for (nreq = 0; wr; nreq++, wr = wr->next) {
4807 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4808 err = -ENOMEM;
4809 *bad_wr = wr;
4810 goto out;
4811 }
4812
4813 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4814 err = -EINVAL;
4815 *bad_wr = wr;
4816 goto out;
4817 }
4818
4819 scat = get_recv_wqe(qp, ind);
4820 if (qp->wq_sig)
4821 scat++;
4822
4823 for (i = 0; i < wr->num_sge; i++)
4824 set_data_ptr_seg(scat + i, wr->sg_list + i);
4825
4826 if (i < qp->rq.max_gs) {
4827 scat[i].byte_count = 0;
4828 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4829 scat[i].addr = 0;
4830 }
4831
4832 if (qp->wq_sig) {
4833 sig = (struct mlx5_rwqe_sig *)scat;
4834 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4835 }
4836
4837 qp->rq.wrid[ind] = wr->wr_id;
4838
4839 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4840 }
4841
4842out:
4843 if (likely(nreq)) {
4844 qp->rq.head += nreq;
4845
4846 /* Make sure that descriptors are written before
4847 * doorbell record.
4848 */
4849 wmb();
4850
4851 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4852 }
4853
4854 spin_unlock_irqrestore(&qp->rq.lock, flags);
4855
4856 return err;
4857}
4858
d34ac5cd
BVA		 4859int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4860 const struct ib_recv_wr **bad_wr)
d0e84c0a
YH		 4861{
4862 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
4863}
4864
e126ba97
EC		 4865static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4866{
4867 switch (mlx5_state) {
4868 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4869 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4870 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4871 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4872 case MLX5_QP_STATE_SQ_DRAINING:
4873 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4874 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4875 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4876 default: return -1;
4877 }
4878}
4879
4880static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4881{
4882 switch (mlx5_mig_state) {
4883 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4884 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4885 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4886 default: return -1;
4887 }
4888}
4889
4890static int to_ib_qp_access_flags(int mlx5_flags)
4891{
4892 int ib_flags = 0;
4893
4894 if (mlx5_flags & MLX5_QP_BIT_RRE)
4895 ib_flags |= IB_ACCESS_REMOTE_READ;
4896 if (mlx5_flags & MLX5_QP_BIT_RWE)
4897 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4898 if (mlx5_flags & MLX5_QP_BIT_RAE)
4899 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4900
4901 return ib_flags;
4902}
4903
38349389 4904static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4905 struct rdma_ah_attr *ah_attr,
38349389 4906 struct mlx5_qp_path *path)
e126ba97 4907{
e126ba97 4908
d8966fcd 4909 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4910
e7996a9a 4911 if (!path->port || path->port > ibdev->num_ports)
e126ba97
EC		 4912 return;
4913
ae59c3f0
LR		 4914 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4915
d8966fcd
DC		 4916 rdma_ah_set_port_num(ah_attr, path->port);
4917 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4918
4919 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4920 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4921 rdma_ah_set_static_rate(ah_attr,
4922 path->static_rate ? path->static_rate - 5 : 0);
4923 if (path->grh_mlid & (1 << 7)) {
4924 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4925
4926 rdma_ah_set_grh(ah_attr, NULL,
4927 tc_fl & 0xfffff,
4928 path->mgid_index,
4929 path->hop_limit,
4930 (tc_fl >> 20) & 0xff);
4931 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4932 }
4933}
4934
6d2f89df 4935static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4936 struct mlx5_ib_sq *sq,
4937 u8 *sq_state)
4938{
6d2f89df 4939 int err;
4940
28160771 4941 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
6d2f89df 4942 if (err)
4943 goto out;
6d2f89df 4944 sq->state = *sq_state;
4945
4946out:
6d2f89df 4947 return err;
4948}
4949
4950static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4951 struct mlx5_ib_rq *rq,
4952 u8 *rq_state)
4953{
4954 void *out;
4955 void *rqc;
4956 int inlen;
4957 int err;
4958
4959 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4960 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4961 if (!out)
4962 return -ENOMEM;
4963
4964 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4965 if (err)
4966 goto out;
4967
4968 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4969 *rq_state = MLX5_GET(rqc, rqc, state);
4970 rq->state = *rq_state;
4971
4972out:
4973 kvfree(out);
4974 return err;
4975}
4976
4977static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4978 struct mlx5_ib_qp *qp, u8 *qp_state)
4979{
4980 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4981 [MLX5_RQC_STATE_RST] = {
4982 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4983 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4984 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4985 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4986 },
4987 [MLX5_RQC_STATE_RDY] = {
4988 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4989 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4990 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4991 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4992 },
4993 [MLX5_RQC_STATE_ERR] = {
4994 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4995 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4996 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4997 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4998 },
4999 [MLX5_RQ_STATE_NA] = {
5000 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5001 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5002 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
5003 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
5004 },
5005 };
5006
5007 *qp_state = sqrq_trans[rq_state][sq_state];
5008
5009 if (*qp_state == MLX5_QP_STATE_BAD) {
5010 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5011 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5012 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5013 return -EINVAL;
5014 }
5015
5016 if (*qp_state == MLX5_QP_STATE)
5017 *qp_state = qp->state;
5018
5019 return 0;
5020}
5021
5022static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5023 struct mlx5_ib_qp *qp,
5024 u8 *raw_packet_qp_state)
5025{
5026 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5027 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5028 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5029 int err;
5030 u8 sq_state = MLX5_SQ_STATE_NA;
5031 u8 rq_state = MLX5_RQ_STATE_NA;
5032
5033 if (qp->sq.wqe_cnt) {
5034 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5035 if (err)
5036 return err;
5037 }
5038
5039 if (qp->rq.wqe_cnt) {
5040 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5041 if (err)
5042 return err;
5043 }
5044
5045 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5046 raw_packet_qp_state);
5047}
5048
5049static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5050 struct ib_qp_attr *qp_attr)
e126ba97 5051{
09a7d9ec 5052 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 5053 struct mlx5_qp_context *context;
5054 int mlx5_state;
09a7d9ec 5055 u32 *outb;
e126ba97
EC		 5056 int err = 0;
5057
09a7d9ec 5058 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 5059 if (!outb)
5060 return -ENOMEM;
5061
19098df2 5062 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 5063 outlen);
e126ba97 5064 if (err)
6d2f89df 5065 goto out;
e126ba97 5066
09a7d9ec
SM		 5067 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5068 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5069
e126ba97
EC		 5070 mlx5_state = be32_to_cpu(context->flags) >> 28;
5071
5072 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 5073 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5074 qp_attr->path_mig_state =
5075 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5076 qp_attr->qkey = be32_to_cpu(context->qkey);
5077 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5078 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5079 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5080 qp_attr->qp_access_flags =
5081 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5082
5083 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 5084 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5085 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 5086 qp_attr->alt_pkey_index =
5087 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 5088 qp_attr->alt_port_num =
5089 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 5090 }
5091
d3ae2bde 5092 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 5093 qp_attr->port_num = context->pri_path.port;
5094
5095 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5096 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5097
5098 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5099
5100 qp_attr->max_dest_rd_atomic =
5101 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5102 qp_attr->min_rnr_timer =
5103 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5104 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5105 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5106 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5107 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 5108
5109out:
5110 kfree(outb);
5111 return err;
5112}
5113
776a3906
MS		 5114static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5115 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5116 struct ib_qp_init_attr *qp_init_attr)
5117{
5118 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5119 u32 *out;
5120 u32 access_flags = 0;
5121 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5122 void *dctc;
5123 int err;
5124 int supported_mask = IB_QP_STATE |
5125 IB_QP_ACCESS_FLAGS |
5126 IB_QP_PORT |
5127 IB_QP_MIN_RNR_TIMER |
5128 IB_QP_AV |
5129 IB_QP_PATH_MTU |
5130 IB_QP_PKEY_INDEX;
5131
5132 if (qp_attr_mask & ~supported_mask)
5133 return -EINVAL;
5134 if (mqp->state != IB_QPS_RTR)
5135 return -EINVAL;
5136
5137 out = kzalloc(outlen, GFP_KERNEL);
5138 if (!out)
5139 return -ENOMEM;
5140
5141 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5142 if (err)
5143 goto out;
5144
5145 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5146
5147 if (qp_attr_mask & IB_QP_STATE)
5148 qp_attr->qp_state = IB_QPS_RTR;
5149
5150 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5151 if (MLX5_GET(dctc, dctc, rre))
5152 access_flags |= IB_ACCESS_REMOTE_READ;
5153 if (MLX5_GET(dctc, dctc, rwe))
5154 access_flags |= IB_ACCESS_REMOTE_WRITE;
5155 if (MLX5_GET(dctc, dctc, rae))
5156 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5157 qp_attr->qp_access_flags = access_flags;
5158 }
5159
5160 if (qp_attr_mask & IB_QP_PORT)
5161 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5162 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5163 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5164 if (qp_attr_mask & IB_QP_AV) {
5165 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5166 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5167 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5168 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5169 }
5170 if (qp_attr_mask & IB_QP_PATH_MTU)
5171 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5172 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5173 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5174out:
5175 kfree(out);
5176 return err;
5177}
5178
6d2f89df 5179int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5180 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5181{
5182 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5183 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5184 int err = 0;
5185 u8 raw_packet_qp_state;
5186
28d61370
YH		 5187 if (ibqp->rwq_ind_tbl)
5188 return -ENOSYS;
5189
d16e91da
HE		 5190 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5191 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5192 qp_init_attr);
5193
c2e53b2c
YH		 5194 /* Not all of output fields are applicable, make sure to zero them */
5195 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5196 memset(qp_attr, 0, sizeof(*qp_attr));
5197
776a3906
MS		 5198 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5199 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5200 qp_attr_mask, qp_init_attr);
5201
6d2f89df 5202 mutex_lock(&qp->mutex);
5203
c2e53b2c
YH		 5204 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5205 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 5206 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5207 if (err)
5208 goto out;
5209 qp->state = raw_packet_qp_state;
5210 qp_attr->port_num = 1;
5211 } else {
5212 err = query_qp_attr(dev, qp, qp_attr);
5213 if (err)
5214 goto out;
5215 }
5216
5217 qp_attr->qp_state = qp->state;
e126ba97
EC		 5218 qp_attr->cur_qp_state = qp_attr->qp_state;
5219 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5220 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5221
5222 if (!ibqp->uobject) {
0540d814 5223 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 5224 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 5225 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 5226 } else {
5227 qp_attr->cap.max_send_wr = 0;
5228 qp_attr->cap.max_send_sge = 0;
5229 }
5230
0540d814
NO		 5231 qp_init_attr->qp_type = ibqp->qp_type;
5232 qp_init_attr->recv_cq = ibqp->recv_cq;
5233 qp_init_attr->send_cq = ibqp->send_cq;
5234 qp_init_attr->srq = ibqp->srq;
5235 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 5236
5237 qp_init_attr->cap = qp_attr->cap;
5238
5239 qp_init_attr->create_flags = 0;
5240 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5241 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5242
051f2630
LR		 5243 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5244 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5245 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5246 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5247 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5248 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 5249 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5250 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 5251
e126ba97
EC		 5252 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5253 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5254
e126ba97
EC		 5255out:
5256 mutex_unlock(&qp->mutex);
5257 return err;
5258}
5259
5260struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5261 struct ib_ucontext *context,
5262 struct ib_udata *udata)
5263{
5264 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5265 struct mlx5_ib_xrcd *xrcd;
5266 int err;
5267
938fe83c 5268 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 5269 return ERR_PTR(-ENOSYS);
5270
5271 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5272 if (!xrcd)
5273 return ERR_PTR(-ENOMEM);
5274
9603b61d 5275 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 5276 if (err) {
5277 kfree(xrcd);
5278 return ERR_PTR(-ENOMEM);
5279 }
5280
5281 return &xrcd->ibxrcd;
5282}
5283
5284int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5285{
5286 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5287 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5288 int err;
5289
9603b61d 5290 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
b081808a 5291 if (err)
e126ba97 5292 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
e126ba97
EC		 5293
5294 kfree(xrcd);
e126ba97
EC		 5295 return 0;
5296}
79b20a6c 5297
350d0e4c
YH		 5298static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5299{
5300 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5301 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5302 struct ib_event event;
5303
5304 if (rwq->ibwq.event_handler) {
5305 event.device = rwq->ibwq.device;
5306 event.element.wq = &rwq->ibwq;
5307 switch (type) {
5308 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5309 event.event = IB_EVENT_WQ_FATAL;
5310 break;
5311 default:
5312 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5313 return;
5314 }
5315
5316 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5317 }
5318}
5319
03404e8a
MG		 5320static int set_delay_drop(struct mlx5_ib_dev *dev)
5321{
5322 int err = 0;
5323
5324 mutex_lock(&dev->delay_drop.lock);
5325 if (dev->delay_drop.activate)
5326 goto out;
5327
5328 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5329 if (err)
5330 goto out;
5331
5332 dev->delay_drop.activate = true;
5333out:
5334 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 5335
5336 if (!err)
5337 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 5338 return err;
5339}
5340
79b20a6c
YH		 5341static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5342 struct ib_wq_init_attr *init_attr)
5343{
5344 struct mlx5_ib_dev *dev;
4be6da1e 5345 int has_net_offloads;
79b20a6c
YH		 5346 __be64 *rq_pas0;
5347 void *in;
5348 void *rqc;
5349 void *wq;
5350 int inlen;
5351 int err;
5352
5353 dev = to_mdev(pd->device);
5354
5355 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 5356 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5357 if (!in)
5358 return -ENOMEM;
5359
34d57585 5360 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
79b20a6c
YH		 5361 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5362 MLX5_SET(rqc, rqc, mem_rq_type,
5363 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5364 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5365 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5366 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5367 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5368 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 5369 MLX5_SET(wq, wq, wq_type,
5370 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5371 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 5372 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5373 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5374 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5375 err = -EOPNOTSUPP;
5376 goto out;
5377 } else {
5378 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5379 }
5380 }
79b20a6c 5381 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 5382 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5383 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5384 MLX5_SET(wq, wq, log_wqe_stride_size,
5385 rwq->single_stride_log_num_of_bytes -
5386 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5387 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5388 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5389 }
79b20a6c
YH		 5390 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5391 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5392 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5393 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5394 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5395 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 5396 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 5397 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 5398 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 5399 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5400 err = -EOPNOTSUPP;
5401 goto out;
5402 }
5403 } else {
5404 MLX5_SET(rqc, rqc, vsd, 1);
5405 }
4be6da1e
NO		 5406 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5407 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5408 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5409 err = -EOPNOTSUPP;
5410 goto out;
5411 }
5412 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5413 }
03404e8a
MG		 5414 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5415 if (!(dev->ib_dev.attrs.raw_packet_caps &
5416 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5417 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5418 err = -EOPNOTSUPP;
5419 goto out;
5420 }
5421 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5422 }
79b20a6c
YH		 5423 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5424 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5425 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5426 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5427 err = set_delay_drop(dev);
5428 if (err) {
5429 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5430 err);
5431 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5432 } else {
5433 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5434 }
5435 }
b1f74a84 5436out:
79b20a6c
YH		 5437 kvfree(in);
5438 return err;
5439}
5440
5441static int set_user_rq_size(struct mlx5_ib_dev *dev,
5442 struct ib_wq_init_attr *wq_init_attr,
5443 struct mlx5_ib_create_wq *ucmd,
5444 struct mlx5_ib_rwq *rwq)
5445{
5446 /* Sanity check RQ size before proceeding */
5447 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5448 return -EINVAL;
5449
5450 if (!ucmd->rq_wqe_count)
5451 return -EINVAL;
5452
5453 rwq->wqe_count = ucmd->rq_wqe_count;
5454 rwq->wqe_shift = ucmd->rq_wqe_shift;
0dfe4522
LR		 5455 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5456 return -EINVAL;
5457
79b20a6c
YH		 5458 rwq->log_rq_stride = rwq->wqe_shift;
5459 rwq->log_rq_size = ilog2(rwq->wqe_count);
5460 return 0;
5461}
5462
5463static int prepare_user_rq(struct ib_pd *pd,
5464 struct ib_wq_init_attr *init_attr,
5465 struct ib_udata *udata,
5466 struct mlx5_ib_rwq *rwq)
5467{
5468 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5469 struct mlx5_ib_create_wq ucmd = {};
5470 int err;
5471 size_t required_cmd_sz;
5472
ccc87087
NO		 5473 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5474 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5475 if (udata->inlen < required_cmd_sz) {
5476 mlx5_ib_dbg(dev, "invalid inlen\n");
5477 return -EINVAL;
5478 }
5479
5480 if (udata->inlen > sizeof(ucmd) &&
5481 !ib_is_udata_cleared(udata, sizeof(ucmd),
5482 udata->inlen - sizeof(ucmd))) {
5483 mlx5_ib_dbg(dev, "inlen is not supported\n");
5484 return -EOPNOTSUPP;
5485 }
5486
5487 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5488 mlx5_ib_dbg(dev, "copy failed\n");
5489 return -EFAULT;
5490 }
5491
ccc87087 5492 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5493 mlx5_ib_dbg(dev, "invalid comp mask\n");
5494 return -EOPNOTSUPP;
ccc87087
NO		 5495 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5496 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5497 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5498 return -EOPNOTSUPP;
5499 }
5500 if ((ucmd.single_stride_log_num_of_bytes <
5501 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5502 (ucmd.single_stride_log_num_of_bytes >
5503 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5504 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5505 ucmd.single_stride_log_num_of_bytes,
5506 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5507 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5508 return -EINVAL;
5509 }
5510 if ((ucmd.single_wqe_log_num_of_strides >
5511 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5512 (ucmd.single_wqe_log_num_of_strides <
5513 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5514 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5515 ucmd.single_wqe_log_num_of_strides,
5516 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5517 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5518 return -EINVAL;
5519 }
5520 rwq->single_stride_log_num_of_bytes =
5521 ucmd.single_stride_log_num_of_bytes;
5522 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5523 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5524 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5525 }
5526
5527 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5528 if (err) {
5529 mlx5_ib_dbg(dev, "err %d\n", err);
5530 return err;
5531 }
5532
5533 err = create_user_rq(dev, pd, rwq, &ucmd);
5534 if (err) {
5535 mlx5_ib_dbg(dev, "err %d\n", err);
5536 if (err)
5537 return err;
5538 }
5539
5540 rwq->user_index = ucmd.user_index;
5541 return 0;
5542}
5543
5544struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5545 struct ib_wq_init_attr *init_attr,
5546 struct ib_udata *udata)
5547{
5548 struct mlx5_ib_dev *dev;
5549 struct mlx5_ib_rwq *rwq;
5550 struct mlx5_ib_create_wq_resp resp = {};
5551 size_t min_resp_len;
5552 int err;
5553
5554 if (!udata)
5555 return ERR_PTR(-ENOSYS);
5556
5557 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5558 if (udata->outlen && udata->outlen < min_resp_len)
5559 return ERR_PTR(-EINVAL);
5560
5561 dev = to_mdev(pd->device);
5562 switch (init_attr->wq_type) {
5563 case IB_WQT_RQ:
5564 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5565 if (!rwq)
5566 return ERR_PTR(-ENOMEM);
5567 err = prepare_user_rq(pd, init_attr, udata, rwq);
5568 if (err)
5569 goto err;
5570 err = create_rq(rwq, pd, init_attr);
5571 if (err)
5572 goto err_user_rq;
5573 break;
5574 default:
5575 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5576 init_attr->wq_type);
5577 return ERR_PTR(-EINVAL);
5578 }
5579
350d0e4c 5580 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5581 rwq->ibwq.state = IB_WQS_RESET;
5582 if (udata->outlen) {
5583 resp.response_length = offsetof(typeof(resp), response_length) +
5584 sizeof(resp.response_length);
5585 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5586 if (err)
5587 goto err_copy;
5588 }
5589
350d0e4c
YH		 5590 rwq->core_qp.event = mlx5_ib_wq_event;
5591 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5592 return &rwq->ibwq;
5593
5594err_copy:
350d0e4c 5595 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5596err_user_rq:
fe248c3a 5597 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5598err:
5599 kfree(rwq);
5600 return ERR_PTR(err);
5601}
5602
5603int mlx5_ib_destroy_wq(struct ib_wq *wq)
5604{
5605 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5606 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5607
350d0e4c 5608 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5609 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5610 kfree(rwq);
5611
5612 return 0;
5613}
5614
c5f90929
YH		 5615struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5616 struct ib_rwq_ind_table_init_attr *init_attr,
5617 struct ib_udata *udata)
5618{
5619 struct mlx5_ib_dev *dev = to_mdev(device);
5620 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5621 int sz = 1 << init_attr->log_ind_tbl_size;
5622 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5623 size_t min_resp_len;
5624 int inlen;
5625 int err;
5626 int i;
5627 u32 *in;
5628 void *rqtc;
5629
5630 if (udata->inlen > 0 &&
5631 !ib_is_udata_cleared(udata, 0,
5632 udata->inlen))
5633 return ERR_PTR(-EOPNOTSUPP);
5634
efd7f400
MG		 5635 if (init_attr->log_ind_tbl_size >
5636 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5637 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5638 init_attr->log_ind_tbl_size,
5639 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5640 return ERR_PTR(-EINVAL);
5641 }
5642
c5f90929
YH		 5643 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5644 if (udata->outlen && udata->outlen < min_resp_len)
5645 return ERR_PTR(-EINVAL);
5646
5647 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5648 if (!rwq_ind_tbl)
5649 return ERR_PTR(-ENOMEM);
5650
5651 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5652 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5653 if (!in) {
5654 err = -ENOMEM;
5655 goto err;
5656 }
5657
5658 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5659
5660 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5661 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5662
5663 for (i = 0; i < sz; i++)
5664 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5665
5666 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5667 kvfree(in);
5668
5669 if (err)
5670 goto err;
5671
5672 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5673 if (udata->outlen) {
5674 resp.response_length = offsetof(typeof(resp), response_length) +
5675 sizeof(resp.response_length);
5676 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5677 if (err)
5678 goto err_copy;
5679 }
5680
5681 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5682
5683err_copy:
5684 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5685err:
5686 kfree(rwq_ind_tbl);
5687 return ERR_PTR(err);
5688}
5689
5690int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5691{
5692 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5693 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5694
5695 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5696
5697 kfree(rwq_ind_tbl);
5698 return 0;
5699}
5700
79b20a6c
YH		 5701int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5702 u32 wq_attr_mask, struct ib_udata *udata)
5703{
5704 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5705 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5706 struct mlx5_ib_modify_wq ucmd = {};
5707 size_t required_cmd_sz;
5708 int curr_wq_state;
5709 int wq_state;
5710 int inlen;
5711 int err;
5712 void *rqc;
5713 void *in;
5714
5715 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5716 if (udata->inlen < required_cmd_sz)
5717 return -EINVAL;
5718
5719 if (udata->inlen > sizeof(ucmd) &&
5720 !ib_is_udata_cleared(udata, sizeof(ucmd),
5721 udata->inlen - sizeof(ucmd)))
5722 return -EOPNOTSUPP;
5723
5724 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5725 return -EFAULT;
5726
5727 if (ucmd.comp_mask || ucmd.reserved)
5728 return -EOPNOTSUPP;
5729
5730 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5731 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5732 if (!in)
5733 return -ENOMEM;
5734
5735 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5736
5737 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5738 wq_attr->curr_wq_state : wq->state;
5739 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5740 wq_attr->wq_state : curr_wq_state;
5741 if (curr_wq_state == IB_WQS_ERR)
5742 curr_wq_state = MLX5_RQC_STATE_ERR;
5743 if (wq_state == IB_WQS_ERR)
5744 wq_state = MLX5_RQC_STATE_ERR;
5745 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
34d57585 5746 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
79b20a6c
YH		 5747 MLX5_SET(rqc, rqc, state, wq_state);
5748
b1f74a84
NO		 5749 if (wq_attr_mask & IB_WQ_FLAGS) {
5750 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5751 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5752 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5753 mlx5_ib_dbg(dev, "VLAN offloads are not "
5754 "supported\n");
5755 err = -EOPNOTSUPP;
5756 goto out;
5757 }
5758 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5759 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5760 MLX5_SET(rqc, rqc, vsd,
5761 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5762 }
b1383aa6
NO		 5763
5764 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5765 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5766 err = -EOPNOTSUPP;
5767 goto out;
5768 }
b1f74a84
NO		 5769 }
5770
23a6964e
MD		 5771 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5772 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5773 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5774 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 5775 MLX5_SET(rqc, rqc, counter_set_id,
5776 dev->port->cnts.set_id);
23a6964e
MD		 5777 } else
5778 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5779 dev->ib_dev.name);
5780 }
5781
350d0e4c 5782 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 5783 if (!err)
5784 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5785
b1f74a84
NO		 5786out:
5787 kvfree(in);
79b20a6c
YH		 5788 return err;
5789}
d0e84c0a
YH		 5790
5791struct mlx5_ib_drain_cqe {
5792 struct ib_cqe cqe;
5793 struct completion done;
5794};
5795
5796static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5797{
5798 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5799 struct mlx5_ib_drain_cqe,
5800 cqe);
5801
5802 complete(&cqe->done);
5803}
5804
5805/* This function returns only once the drained WR was completed */
5806static void handle_drain_completion(struct ib_cq *cq,
5807 struct mlx5_ib_drain_cqe *sdrain,
5808 struct mlx5_ib_dev *dev)
5809{
5810 struct mlx5_core_dev *mdev = dev->mdev;
5811
5812 if (cq->poll_ctx == IB_POLL_DIRECT) {
5813 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5814 ib_process_cq_direct(cq, -1);
5815 return;
5816 }
5817
5818 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5819 struct mlx5_ib_cq *mcq = to_mcq(cq);
5820 bool triggered = false;
5821 unsigned long flags;
5822
5823 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5824 /* Make sure that the CQ handler won't run if wasn't run yet */
5825 if (!mcq->mcq.reset_notify_added)
5826 mcq->mcq.reset_notify_added = 1;
5827 else
5828 triggered = true;
5829 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5830
5831 if (triggered) {
5832 /* Wait for any scheduled/running task to be ended */
5833 switch (cq->poll_ctx) {
5834 case IB_POLL_SOFTIRQ:
5835 irq_poll_disable(&cq->iop);
5836 irq_poll_enable(&cq->iop);
5837 break;
5838 case IB_POLL_WORKQUEUE:
5839 cancel_work_sync(&cq->work);
5840 break;
5841 default:
5842 WARN_ON_ONCE(1);
5843 }
5844 }
5845
5846 /* Run the CQ handler - this makes sure that the drain WR will
5847 * be processed if wasn't processed yet.
5848 */
5849 mcq->mcq.comp(&mcq->mcq);
5850 }
5851
5852 wait_for_completion(&sdrain->done);
5853}
5854
5855void mlx5_ib_drain_sq(struct ib_qp *qp)
5856{
5857 struct ib_cq *cq = qp->send_cq;
5858 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5859 struct mlx5_ib_drain_cqe sdrain;
d34ac5cd 5860 const struct ib_send_wr *bad_swr;
d0e84c0a
YH		 5861 struct ib_rdma_wr swr = {
5862 .wr = {
5863 .next = NULL,
5864 { .wr_cqe = &sdrain.cqe, },
5865 .opcode = IB_WR_RDMA_WRITE,
5866 },
5867 };
5868 int ret;
5869 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5870 struct mlx5_core_dev *mdev = dev->mdev;
5871
5872 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5873 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5874 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5875 return;
5876 }
5877
5878 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5879 init_completion(&sdrain.done);
5880
5881 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
5882 if (ret) {
5883 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5884 return;
5885 }
5886
5887 handle_drain_completion(cq, &sdrain, dev);
5888}
5889
5890void mlx5_ib_drain_rq(struct ib_qp *qp)
5891{
5892 struct ib_cq *cq = qp->recv_cq;
5893 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5894 struct mlx5_ib_drain_cqe rdrain;
d34ac5cd
BVA		 5895 struct ib_recv_wr rwr = {};
5896 const struct ib_recv_wr *bad_rwr;
d0e84c0a
YH		 5897 int ret;
5898 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5899 struct mlx5_core_dev *mdev = dev->mdev;
5900
5901 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5902 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5903 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5904 return;
5905 }
5906
5907 rwr.wr_cqe = &rdrain.cqe;
5908 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5909 init_completion(&rdrain.done);
5910
5911 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
5912 if (ret) {
5913 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5914 return;
5915 }
5916
5917 handle_drain_completion(cq, &rdrain, dev);
5918}
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