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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <rdma/ib_umem.h> | |
2811ba51 | 35 | #include <rdma/ib_cache.h> |
cfb5e088 | 36 | #include <rdma/ib_user_verbs.h> |
d14133dd | 37 | #include <rdma/rdma_counter.h> |
c2e53b2c | 38 | #include <linux/mlx5/fs.h> |
e126ba97 | 39 | #include "mlx5_ib.h" |
b96c9dde | 40 | #include "ib_rep.h" |
443c1cf9 | 41 | #include "cmd.h" |
e126ba97 EC |
42 | |
43 | /* not supported currently */ | |
44 | static int wq_signature; | |
45 | ||
46 | enum { | |
47 | MLX5_IB_ACK_REQ_FREQ = 8, | |
48 | }; | |
49 | ||
50 | enum { | |
51 | MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, | |
52 | MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, | |
53 | MLX5_IB_LINK_TYPE_IB = 0, | |
54 | MLX5_IB_LINK_TYPE_ETH = 1 | |
55 | }; | |
56 | ||
57 | enum { | |
58 | MLX5_IB_SQ_STRIDE = 6, | |
064e5262 | 59 | MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, |
e126ba97 EC |
60 | }; |
61 | ||
62 | static const u32 mlx5_ib_opcode[] = { | |
63 | [IB_WR_SEND] = MLX5_OPCODE_SEND, | |
f0313965 | 64 | [IB_WR_LSO] = MLX5_OPCODE_LSO, |
e126ba97 EC |
65 | [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, |
66 | [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, | |
67 | [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, | |
68 | [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, | |
69 | [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, | |
70 | [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, | |
71 | [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, | |
72 | [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, | |
8a187ee5 | 73 | [IB_WR_REG_MR] = MLX5_OPCODE_UMR, |
e126ba97 EC |
74 | [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, |
75 | [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, | |
76 | [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, | |
77 | }; | |
78 | ||
f0313965 ES |
79 | struct mlx5_wqe_eth_pad { |
80 | u8 rsvd0[16]; | |
81 | }; | |
e126ba97 | 82 | |
eb49ab0c AV |
83 | enum raw_qp_set_mask_map { |
84 | MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, | |
7d29f349 | 85 | MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, |
eb49ab0c AV |
86 | }; |
87 | ||
0680efa2 AV |
88 | struct mlx5_modify_raw_qp_param { |
89 | u16 operation; | |
eb49ab0c AV |
90 | |
91 | u32 set_mask; /* raw_qp_set_mask_map */ | |
61147f39 BW |
92 | |
93 | struct mlx5_rate_limit rl; | |
94 | ||
eb49ab0c | 95 | u8 rq_q_ctr_id; |
d5ed8ac3 | 96 | u16 port; |
0680efa2 AV |
97 | }; |
98 | ||
89ea94a7 MG |
99 | static void get_cqs(enum ib_qp_type qp_type, |
100 | struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, | |
101 | struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); | |
102 | ||
e126ba97 EC |
103 | static int is_qp0(enum ib_qp_type qp_type) |
104 | { | |
105 | return qp_type == IB_QPT_SMI; | |
106 | } | |
107 | ||
e126ba97 EC |
108 | static int is_sqp(enum ib_qp_type qp_type) |
109 | { | |
110 | return is_qp0(qp_type) || is_qp1(qp_type); | |
111 | } | |
112 | ||
c1395a2a | 113 | /** |
fbeb4075 MS |
114 | * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ |
115 | * to kernel buffer | |
c1395a2a | 116 | * |
fbeb4075 MS |
117 | * @umem: User space memory where the WQ is |
118 | * @buffer: buffer to copy to | |
119 | * @buflen: buffer length | |
120 | * @wqe_index: index of WQE to copy from | |
121 | * @wq_offset: offset to start of WQ | |
122 | * @wq_wqe_cnt: number of WQEs in WQ | |
123 | * @wq_wqe_shift: log2 of WQE size | |
124 | * @bcnt: number of bytes to copy | |
125 | * @bytes_copied: number of bytes to copy (return value) | |
c1395a2a | 126 | * |
fbeb4075 MS |
127 | * Copies from start of WQE bcnt or less bytes. |
128 | * Does not gurantee to copy the entire WQE. | |
c1395a2a | 129 | * |
fbeb4075 | 130 | * Return: zero on success, or an error code. |
c1395a2a | 131 | */ |
da9ee9d8 MS |
132 | static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer, |
133 | size_t buflen, int wqe_index, | |
134 | int wq_offset, int wq_wqe_cnt, | |
135 | int wq_wqe_shift, int bcnt, | |
fbeb4075 | 136 | size_t *bytes_copied) |
c1395a2a | 137 | { |
fbeb4075 MS |
138 | size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); |
139 | size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); | |
140 | size_t copy_length; | |
c1395a2a HE |
141 | int ret; |
142 | ||
fbeb4075 MS |
143 | /* don't copy more than requested, more than buffer length or |
144 | * beyond WQ end | |
145 | */ | |
146 | copy_length = min_t(u32, buflen, wq_end - offset); | |
147 | copy_length = min_t(u32, copy_length, bcnt); | |
148 | ||
149 | ret = ib_umem_copy_from(buffer, umem, offset, copy_length); | |
150 | if (ret) | |
151 | return ret; | |
c1395a2a | 152 | |
fbeb4075 MS |
153 | if (!ret && bytes_copied) |
154 | *bytes_copied = copy_length; | |
c1395a2a | 155 | |
fbeb4075 MS |
156 | return 0; |
157 | } | |
c1395a2a | 158 | |
da9ee9d8 MS |
159 | static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, |
160 | void *buffer, size_t buflen, size_t *bc) | |
161 | { | |
162 | struct mlx5_wqe_ctrl_seg *ctrl; | |
163 | size_t bytes_copied = 0; | |
164 | size_t wqe_length; | |
165 | void *p; | |
166 | int ds; | |
167 | ||
168 | wqe_index = wqe_index & qp->sq.fbc.sz_m1; | |
169 | ||
170 | /* read the control segment first */ | |
171 | p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); | |
172 | ctrl = p; | |
173 | ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; | |
174 | wqe_length = ds * MLX5_WQE_DS_UNITS; | |
175 | ||
176 | /* read rest of WQE if it spreads over more than one stride */ | |
177 | while (bytes_copied < wqe_length) { | |
178 | size_t copy_length = | |
179 | min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB); | |
180 | ||
181 | if (!copy_length) | |
182 | break; | |
183 | ||
184 | memcpy(buffer + bytes_copied, p, copy_length); | |
185 | bytes_copied += copy_length; | |
186 | ||
187 | wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1; | |
188 | p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index); | |
189 | } | |
190 | *bc = bytes_copied; | |
191 | return 0; | |
192 | } | |
193 | ||
194 | static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, | |
195 | void *buffer, size_t buflen, size_t *bc) | |
fbeb4075 MS |
196 | { |
197 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; | |
198 | struct ib_umem *umem = base->ubuffer.umem; | |
199 | struct mlx5_ib_wq *wq = &qp->sq; | |
200 | struct mlx5_wqe_ctrl_seg *ctrl; | |
201 | size_t bytes_copied; | |
202 | size_t bytes_copied2; | |
203 | size_t wqe_length; | |
204 | int ret; | |
205 | int ds; | |
206 | ||
fbeb4075 | 207 | /* at first read as much as possible */ |
da9ee9d8 MS |
208 | ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, |
209 | wq->offset, wq->wqe_cnt, | |
210 | wq->wqe_shift, buflen, | |
fbeb4075 | 211 | &bytes_copied); |
c1395a2a HE |
212 | if (ret) |
213 | return ret; | |
214 | ||
fbeb4075 MS |
215 | /* we need at least control segment size to proceed */ |
216 | if (bytes_copied < sizeof(*ctrl)) | |
217 | return -EINVAL; | |
218 | ||
219 | ctrl = buffer; | |
220 | ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; | |
221 | wqe_length = ds * MLX5_WQE_DS_UNITS; | |
c1395a2a | 222 | |
fbeb4075 MS |
223 | /* if we copied enough then we are done */ |
224 | if (bytes_copied >= wqe_length) { | |
225 | *bc = bytes_copied; | |
226 | return 0; | |
c1395a2a HE |
227 | } |
228 | ||
fbeb4075 MS |
229 | /* otherwise this a wrapped around wqe |
230 | * so read the remaining bytes starting | |
231 | * from wqe_index 0 | |
232 | */ | |
da9ee9d8 MS |
233 | ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied, |
234 | buflen - bytes_copied, 0, wq->offset, | |
235 | wq->wqe_cnt, wq->wqe_shift, | |
fbeb4075 MS |
236 | wqe_length - bytes_copied, |
237 | &bytes_copied2); | |
238 | ||
239 | if (ret) | |
240 | return ret; | |
241 | *bc = bytes_copied + bytes_copied2; | |
242 | return 0; | |
243 | } | |
244 | ||
da9ee9d8 MS |
245 | int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, |
246 | size_t buflen, size_t *bc) | |
247 | { | |
248 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; | |
249 | struct ib_umem *umem = base->ubuffer.umem; | |
250 | ||
251 | if (buflen < sizeof(struct mlx5_wqe_ctrl_seg)) | |
252 | return -EINVAL; | |
253 | ||
254 | if (!umem) | |
255 | return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer, | |
256 | buflen, bc); | |
257 | ||
258 | return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc); | |
259 | } | |
260 | ||
261 | static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, | |
262 | void *buffer, size_t buflen, size_t *bc) | |
fbeb4075 MS |
263 | { |
264 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; | |
265 | struct ib_umem *umem = base->ubuffer.umem; | |
266 | struct mlx5_ib_wq *wq = &qp->rq; | |
267 | size_t bytes_copied; | |
268 | int ret; | |
269 | ||
da9ee9d8 MS |
270 | ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, |
271 | wq->offset, wq->wqe_cnt, | |
272 | wq->wqe_shift, buflen, | |
fbeb4075 | 273 | &bytes_copied); |
c1395a2a | 274 | |
c1395a2a HE |
275 | if (ret) |
276 | return ret; | |
fbeb4075 MS |
277 | *bc = bytes_copied; |
278 | return 0; | |
279 | } | |
280 | ||
da9ee9d8 MS |
281 | int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, |
282 | size_t buflen, size_t *bc) | |
283 | { | |
284 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; | |
285 | struct ib_umem *umem = base->ubuffer.umem; | |
286 | struct mlx5_ib_wq *wq = &qp->rq; | |
287 | size_t wqe_size = 1 << wq->wqe_shift; | |
288 | ||
289 | if (buflen < wqe_size) | |
290 | return -EINVAL; | |
291 | ||
292 | if (!umem) | |
293 | return -EOPNOTSUPP; | |
294 | ||
295 | return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc); | |
296 | } | |
297 | ||
298 | static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, | |
299 | void *buffer, size_t buflen, size_t *bc) | |
fbeb4075 MS |
300 | { |
301 | struct ib_umem *umem = srq->umem; | |
302 | size_t bytes_copied; | |
303 | int ret; | |
c1395a2a | 304 | |
da9ee9d8 MS |
305 | ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0, |
306 | srq->msrq.max, srq->msrq.wqe_shift, | |
307 | buflen, &bytes_copied); | |
fbeb4075 MS |
308 | |
309 | if (ret) | |
310 | return ret; | |
311 | *bc = bytes_copied; | |
312 | return 0; | |
c1395a2a HE |
313 | } |
314 | ||
da9ee9d8 MS |
315 | int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, |
316 | size_t buflen, size_t *bc) | |
317 | { | |
318 | struct ib_umem *umem = srq->umem; | |
319 | size_t wqe_size = 1 << srq->msrq.wqe_shift; | |
320 | ||
321 | if (buflen < wqe_size) | |
322 | return -EINVAL; | |
323 | ||
324 | if (!umem) | |
325 | return -EOPNOTSUPP; | |
326 | ||
327 | return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc); | |
328 | } | |
329 | ||
e126ba97 EC |
330 | static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) |
331 | { | |
332 | struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; | |
333 | struct ib_event event; | |
334 | ||
19098df2 | 335 | if (type == MLX5_EVENT_TYPE_PATH_MIG) { |
336 | /* This event is only valid for trans_qps */ | |
337 | to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; | |
338 | } | |
e126ba97 EC |
339 | |
340 | if (ibqp->event_handler) { | |
341 | event.device = ibqp->device; | |
342 | event.element.qp = ibqp; | |
343 | switch (type) { | |
344 | case MLX5_EVENT_TYPE_PATH_MIG: | |
345 | event.event = IB_EVENT_PATH_MIG; | |
346 | break; | |
347 | case MLX5_EVENT_TYPE_COMM_EST: | |
348 | event.event = IB_EVENT_COMM_EST; | |
349 | break; | |
350 | case MLX5_EVENT_TYPE_SQ_DRAINED: | |
351 | event.event = IB_EVENT_SQ_DRAINED; | |
352 | break; | |
353 | case MLX5_EVENT_TYPE_SRQ_LAST_WQE: | |
354 | event.event = IB_EVENT_QP_LAST_WQE_REACHED; | |
355 | break; | |
356 | case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: | |
357 | event.event = IB_EVENT_QP_FATAL; | |
358 | break; | |
359 | case MLX5_EVENT_TYPE_PATH_MIG_FAILED: | |
360 | event.event = IB_EVENT_PATH_MIG_ERR; | |
361 | break; | |
362 | case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: | |
363 | event.event = IB_EVENT_QP_REQ_ERR; | |
364 | break; | |
365 | case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: | |
366 | event.event = IB_EVENT_QP_ACCESS_ERR; | |
367 | break; | |
368 | default: | |
369 | pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); | |
370 | return; | |
371 | } | |
372 | ||
373 | ibqp->event_handler(&event, ibqp->qp_context); | |
374 | } | |
375 | } | |
376 | ||
377 | static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, | |
378 | int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) | |
379 | { | |
380 | int wqe_size; | |
381 | int wq_size; | |
382 | ||
383 | /* Sanity check RQ size before proceeding */ | |
938fe83c | 384 | if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) |
e126ba97 EC |
385 | return -EINVAL; |
386 | ||
387 | if (!has_rq) { | |
388 | qp->rq.max_gs = 0; | |
389 | qp->rq.wqe_cnt = 0; | |
390 | qp->rq.wqe_shift = 0; | |
0540d814 NO |
391 | cap->max_recv_wr = 0; |
392 | cap->max_recv_sge = 0; | |
e126ba97 EC |
393 | } else { |
394 | if (ucmd) { | |
395 | qp->rq.wqe_cnt = ucmd->rq_wqe_count; | |
002bf228 LR |
396 | if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) |
397 | return -EINVAL; | |
e126ba97 | 398 | qp->rq.wqe_shift = ucmd->rq_wqe_shift; |
002bf228 LR |
399 | if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) |
400 | return -EINVAL; | |
e126ba97 EC |
401 | qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; |
402 | qp->rq.max_post = qp->rq.wqe_cnt; | |
403 | } else { | |
404 | wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; | |
405 | wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); | |
406 | wqe_size = roundup_pow_of_two(wqe_size); | |
407 | wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; | |
408 | wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); | |
409 | qp->rq.wqe_cnt = wq_size / wqe_size; | |
938fe83c | 410 | if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { |
e126ba97 EC |
411 | mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", |
412 | wqe_size, | |
938fe83c SM |
413 | MLX5_CAP_GEN(dev->mdev, |
414 | max_wqe_sz_rq)); | |
e126ba97 EC |
415 | return -EINVAL; |
416 | } | |
417 | qp->rq.wqe_shift = ilog2(wqe_size); | |
418 | qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; | |
419 | qp->rq.max_post = qp->rq.wqe_cnt; | |
420 | } | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
f0313965 | 426 | static int sq_overhead(struct ib_qp_init_attr *attr) |
e126ba97 | 427 | { |
618af384 | 428 | int size = 0; |
e126ba97 | 429 | |
f0313965 | 430 | switch (attr->qp_type) { |
e126ba97 | 431 | case IB_QPT_XRC_INI: |
b125a54b | 432 | size += sizeof(struct mlx5_wqe_xrc_seg); |
e126ba97 EC |
433 | /* fall through */ |
434 | case IB_QPT_RC: | |
435 | size += sizeof(struct mlx5_wqe_ctrl_seg) + | |
75c1657e LR |
436 | max(sizeof(struct mlx5_wqe_atomic_seg) + |
437 | sizeof(struct mlx5_wqe_raddr_seg), | |
438 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + | |
064e5262 IB |
439 | sizeof(struct mlx5_mkey_seg) + |
440 | MLX5_IB_SQ_UMR_INLINE_THRESHOLD / | |
441 | MLX5_IB_UMR_OCTOWORD); | |
e126ba97 EC |
442 | break; |
443 | ||
b125a54b EC |
444 | case IB_QPT_XRC_TGT: |
445 | return 0; | |
446 | ||
e126ba97 | 447 | case IB_QPT_UC: |
b125a54b | 448 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
75c1657e LR |
449 | max(sizeof(struct mlx5_wqe_raddr_seg), |
450 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + | |
451 | sizeof(struct mlx5_mkey_seg)); | |
e126ba97 EC |
452 | break; |
453 | ||
454 | case IB_QPT_UD: | |
f0313965 ES |
455 | if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) |
456 | size += sizeof(struct mlx5_wqe_eth_pad) + | |
457 | sizeof(struct mlx5_wqe_eth_seg); | |
458 | /* fall through */ | |
e126ba97 | 459 | case IB_QPT_SMI: |
d16e91da | 460 | case MLX5_IB_QPT_HW_GSI: |
b125a54b | 461 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
e126ba97 EC |
462 | sizeof(struct mlx5_wqe_datagram_seg); |
463 | break; | |
464 | ||
465 | case MLX5_IB_QPT_REG_UMR: | |
b125a54b | 466 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
e126ba97 EC |
467 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + |
468 | sizeof(struct mlx5_mkey_seg); | |
469 | break; | |
470 | ||
471 | default: | |
472 | return -EINVAL; | |
473 | } | |
474 | ||
475 | return size; | |
476 | } | |
477 | ||
478 | static int calc_send_wqe(struct ib_qp_init_attr *attr) | |
479 | { | |
480 | int inl_size = 0; | |
481 | int size; | |
482 | ||
f0313965 | 483 | size = sq_overhead(attr); |
e126ba97 EC |
484 | if (size < 0) |
485 | return size; | |
486 | ||
487 | if (attr->cap.max_inline_data) { | |
488 | inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + | |
489 | attr->cap.max_inline_data; | |
490 | } | |
491 | ||
492 | size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); | |
c0a6cbb9 | 493 | if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN && |
e1e66cc2 | 494 | ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) |
c0a6cbb9 | 495 | return MLX5_SIG_WQE_SIZE; |
e1e66cc2 SG |
496 | else |
497 | return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); | |
e126ba97 EC |
498 | } |
499 | ||
288c01b7 EC |
500 | static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) |
501 | { | |
502 | int max_sge; | |
503 | ||
504 | if (attr->qp_type == IB_QPT_RC) | |
505 | max_sge = (min_t(int, wqe_size, 512) - | |
506 | sizeof(struct mlx5_wqe_ctrl_seg) - | |
507 | sizeof(struct mlx5_wqe_raddr_seg)) / | |
508 | sizeof(struct mlx5_wqe_data_seg); | |
509 | else if (attr->qp_type == IB_QPT_XRC_INI) | |
510 | max_sge = (min_t(int, wqe_size, 512) - | |
511 | sizeof(struct mlx5_wqe_ctrl_seg) - | |
512 | sizeof(struct mlx5_wqe_xrc_seg) - | |
513 | sizeof(struct mlx5_wqe_raddr_seg)) / | |
514 | sizeof(struct mlx5_wqe_data_seg); | |
515 | else | |
516 | max_sge = (wqe_size - sq_overhead(attr)) / | |
517 | sizeof(struct mlx5_wqe_data_seg); | |
518 | ||
519 | return min_t(int, max_sge, wqe_size - sq_overhead(attr) / | |
520 | sizeof(struct mlx5_wqe_data_seg)); | |
521 | } | |
522 | ||
e126ba97 EC |
523 | static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, |
524 | struct mlx5_ib_qp *qp) | |
525 | { | |
526 | int wqe_size; | |
527 | int wq_size; | |
528 | ||
529 | if (!attr->cap.max_send_wr) | |
530 | return 0; | |
531 | ||
532 | wqe_size = calc_send_wqe(attr); | |
533 | mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); | |
534 | if (wqe_size < 0) | |
535 | return wqe_size; | |
536 | ||
938fe83c | 537 | if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { |
b125a54b | 538 | mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", |
938fe83c | 539 | wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); |
e126ba97 EC |
540 | return -EINVAL; |
541 | } | |
542 | ||
f0313965 ES |
543 | qp->max_inline_data = wqe_size - sq_overhead(attr) - |
544 | sizeof(struct mlx5_wqe_inline_seg); | |
e126ba97 EC |
545 | attr->cap.max_inline_data = qp->max_inline_data; |
546 | ||
547 | wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); | |
548 | qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; | |
938fe83c | 549 | if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { |
1974ab9d BVA |
550 | mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", |
551 | attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, | |
938fe83c SM |
552 | qp->sq.wqe_cnt, |
553 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); | |
b125a54b EC |
554 | return -ENOMEM; |
555 | } | |
e126ba97 | 556 | qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); |
288c01b7 EC |
557 | qp->sq.max_gs = get_send_sge(attr, wqe_size); |
558 | if (qp->sq.max_gs < attr->cap.max_send_sge) | |
559 | return -ENOMEM; | |
560 | ||
561 | attr->cap.max_send_sge = qp->sq.max_gs; | |
b125a54b EC |
562 | qp->sq.max_post = wq_size / wqe_size; |
563 | attr->cap.max_send_wr = qp->sq.max_post; | |
e126ba97 EC |
564 | |
565 | return wq_size; | |
566 | } | |
567 | ||
568 | static int set_user_buf_size(struct mlx5_ib_dev *dev, | |
569 | struct mlx5_ib_qp *qp, | |
19098df2 | 570 | struct mlx5_ib_create_qp *ucmd, |
0fb2ed66 | 571 | struct mlx5_ib_qp_base *base, |
572 | struct ib_qp_init_attr *attr) | |
e126ba97 EC |
573 | { |
574 | int desc_sz = 1 << qp->sq.wqe_shift; | |
575 | ||
938fe83c | 576 | if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { |
e126ba97 | 577 | mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", |
938fe83c | 578 | desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); |
e126ba97 EC |
579 | return -EINVAL; |
580 | } | |
581 | ||
af8b38ed GP |
582 | if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { |
583 | mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", | |
584 | ucmd->sq_wqe_count); | |
e126ba97 EC |
585 | return -EINVAL; |
586 | } | |
587 | ||
588 | qp->sq.wqe_cnt = ucmd->sq_wqe_count; | |
589 | ||
938fe83c | 590 | if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { |
e126ba97 | 591 | mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", |
938fe83c SM |
592 | qp->sq.wqe_cnt, |
593 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); | |
e126ba97 EC |
594 | return -EINVAL; |
595 | } | |
596 | ||
c2e53b2c YH |
597 | if (attr->qp_type == IB_QPT_RAW_PACKET || |
598 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 599 | base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; |
600 | qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; | |
601 | } else { | |
602 | base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + | |
603 | (qp->sq.wqe_cnt << 6); | |
604 | } | |
e126ba97 EC |
605 | |
606 | return 0; | |
607 | } | |
608 | ||
609 | static int qp_has_rq(struct ib_qp_init_attr *attr) | |
610 | { | |
611 | if (attr->qp_type == IB_QPT_XRC_INI || | |
612 | attr->qp_type == IB_QPT_XRC_TGT || attr->srq || | |
613 | attr->qp_type == MLX5_IB_QPT_REG_UMR || | |
614 | !attr->cap.max_recv_wr) | |
615 | return 0; | |
616 | ||
617 | return 1; | |
618 | } | |
619 | ||
0b80c14f EC |
620 | enum { |
621 | /* this is the first blue flame register in the array of bfregs assigned | |
622 | * to a processes. Since we do not use it for blue flame but rather | |
623 | * regular 64 bit doorbells, we do not need a lock for maintaiing | |
624 | * "odd/even" order | |
625 | */ | |
626 | NUM_NON_BLUE_FLAME_BFREGS = 1, | |
627 | }; | |
628 | ||
b037c29a EC |
629 | static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) |
630 | { | |
31a78a5a | 631 | return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; |
b037c29a EC |
632 | } |
633 | ||
634 | static int num_med_bfreg(struct mlx5_ib_dev *dev, | |
635 | struct mlx5_bfreg_info *bfregi) | |
c1be5232 EC |
636 | { |
637 | int n; | |
638 | ||
b037c29a EC |
639 | n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - |
640 | NUM_NON_BLUE_FLAME_BFREGS; | |
c1be5232 EC |
641 | |
642 | return n >= 0 ? n : 0; | |
643 | } | |
644 | ||
18b0362e YH |
645 | static int first_med_bfreg(struct mlx5_ib_dev *dev, |
646 | struct mlx5_bfreg_info *bfregi) | |
647 | { | |
648 | return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; | |
649 | } | |
650 | ||
b037c29a EC |
651 | static int first_hi_bfreg(struct mlx5_ib_dev *dev, |
652 | struct mlx5_bfreg_info *bfregi) | |
c1be5232 EC |
653 | { |
654 | int med; | |
c1be5232 | 655 | |
b037c29a EC |
656 | med = num_med_bfreg(dev, bfregi); |
657 | return ++med; | |
c1be5232 EC |
658 | } |
659 | ||
b037c29a EC |
660 | static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, |
661 | struct mlx5_bfreg_info *bfregi) | |
e126ba97 | 662 | { |
e126ba97 EC |
663 | int i; |
664 | ||
b037c29a EC |
665 | for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { |
666 | if (!bfregi->count[i]) { | |
2f5ff264 | 667 | bfregi->count[i]++; |
e126ba97 EC |
668 | return i; |
669 | } | |
670 | } | |
671 | ||
672 | return -ENOMEM; | |
673 | } | |
674 | ||
b037c29a EC |
675 | static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, |
676 | struct mlx5_bfreg_info *bfregi) | |
e126ba97 | 677 | { |
18b0362e | 678 | int minidx = first_med_bfreg(dev, bfregi); |
e126ba97 EC |
679 | int i; |
680 | ||
18b0362e YH |
681 | if (minidx < 0) |
682 | return minidx; | |
683 | ||
684 | for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { | |
2f5ff264 | 685 | if (bfregi->count[i] < bfregi->count[minidx]) |
e126ba97 | 686 | minidx = i; |
0b80c14f EC |
687 | if (!bfregi->count[minidx]) |
688 | break; | |
e126ba97 EC |
689 | } |
690 | ||
2f5ff264 | 691 | bfregi->count[minidx]++; |
e126ba97 EC |
692 | return minidx; |
693 | } | |
694 | ||
b037c29a | 695 | static int alloc_bfreg(struct mlx5_ib_dev *dev, |
ffaf58de | 696 | struct mlx5_bfreg_info *bfregi) |
e126ba97 | 697 | { |
ffaf58de | 698 | int bfregn = -ENOMEM; |
e126ba97 | 699 | |
0a2fd01c YH |
700 | if (bfregi->lib_uar_dyn) |
701 | return -EINVAL; | |
702 | ||
2f5ff264 | 703 | mutex_lock(&bfregi->lock); |
ffaf58de LR |
704 | if (bfregi->ver >= 2) { |
705 | bfregn = alloc_high_class_bfreg(dev, bfregi); | |
706 | if (bfregn < 0) | |
707 | bfregn = alloc_med_class_bfreg(dev, bfregi); | |
708 | } | |
709 | ||
710 | if (bfregn < 0) { | |
0b80c14f | 711 | BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); |
2f5ff264 EC |
712 | bfregn = 0; |
713 | bfregi->count[bfregn]++; | |
e126ba97 | 714 | } |
2f5ff264 | 715 | mutex_unlock(&bfregi->lock); |
e126ba97 | 716 | |
2f5ff264 | 717 | return bfregn; |
e126ba97 EC |
718 | } |
719 | ||
4ed131d0 | 720 | void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) |
e126ba97 | 721 | { |
2f5ff264 | 722 | mutex_lock(&bfregi->lock); |
b037c29a | 723 | bfregi->count[bfregn]--; |
2f5ff264 | 724 | mutex_unlock(&bfregi->lock); |
e126ba97 EC |
725 | } |
726 | ||
727 | static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) | |
728 | { | |
729 | switch (state) { | |
730 | case IB_QPS_RESET: return MLX5_QP_STATE_RST; | |
731 | case IB_QPS_INIT: return MLX5_QP_STATE_INIT; | |
732 | case IB_QPS_RTR: return MLX5_QP_STATE_RTR; | |
733 | case IB_QPS_RTS: return MLX5_QP_STATE_RTS; | |
734 | case IB_QPS_SQD: return MLX5_QP_STATE_SQD; | |
735 | case IB_QPS_SQE: return MLX5_QP_STATE_SQER; | |
736 | case IB_QPS_ERR: return MLX5_QP_STATE_ERR; | |
737 | default: return -1; | |
738 | } | |
739 | } | |
740 | ||
741 | static int to_mlx5_st(enum ib_qp_type type) | |
742 | { | |
743 | switch (type) { | |
744 | case IB_QPT_RC: return MLX5_QP_ST_RC; | |
745 | case IB_QPT_UC: return MLX5_QP_ST_UC; | |
746 | case IB_QPT_UD: return MLX5_QP_ST_UD; | |
747 | case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; | |
748 | case IB_QPT_XRC_INI: | |
749 | case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; | |
750 | case IB_QPT_SMI: return MLX5_QP_ST_QP0; | |
d16e91da | 751 | case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; |
c32a4f29 | 752 | case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; |
e126ba97 | 753 | case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; |
e126ba97 | 754 | case IB_QPT_RAW_PACKET: |
0fb2ed66 | 755 | case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; |
e126ba97 EC |
756 | case IB_QPT_MAX: |
757 | default: return -EINVAL; | |
758 | } | |
759 | } | |
760 | ||
89ea94a7 MG |
761 | static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, |
762 | struct mlx5_ib_cq *recv_cq); | |
763 | static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, | |
764 | struct mlx5_ib_cq *recv_cq); | |
765 | ||
7c043e90 | 766 | int bfregn_to_uar_index(struct mlx5_ib_dev *dev, |
05f58ceb | 767 | struct mlx5_bfreg_info *bfregi, u32 bfregn, |
7c043e90 | 768 | bool dyn_bfreg) |
e126ba97 | 769 | { |
05f58ceb LR |
770 | unsigned int bfregs_per_sys_page; |
771 | u32 index_of_sys_page; | |
772 | u32 offset; | |
b037c29a | 773 | |
0a2fd01c YH |
774 | if (bfregi->lib_uar_dyn) |
775 | return -EINVAL; | |
776 | ||
b037c29a EC |
777 | bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * |
778 | MLX5_NON_FP_BFREGS_PER_UAR; | |
779 | index_of_sys_page = bfregn / bfregs_per_sys_page; | |
780 | ||
1ee47ab3 YH |
781 | if (dyn_bfreg) { |
782 | index_of_sys_page += bfregi->num_static_sys_pages; | |
05f58ceb LR |
783 | |
784 | if (index_of_sys_page >= bfregi->num_sys_pages) | |
785 | return -EINVAL; | |
786 | ||
1ee47ab3 YH |
787 | if (bfregn > bfregi->num_dyn_bfregs || |
788 | bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { | |
789 | mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); | |
790 | return -EINVAL; | |
791 | } | |
792 | } | |
b037c29a | 793 | |
1ee47ab3 | 794 | offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; |
b037c29a | 795 | return bfregi->sys_pages[index_of_sys_page] + offset; |
e126ba97 EC |
796 | } |
797 | ||
b0ea0fa5 | 798 | static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, |
19098df2 | 799 | unsigned long addr, size_t size, |
b0ea0fa5 JG |
800 | struct ib_umem **umem, int *npages, int *page_shift, |
801 | int *ncont, u32 *offset) | |
19098df2 | 802 | { |
803 | int err; | |
804 | ||
c320e527 | 805 | *umem = ib_umem_get(&dev->ib_dev, addr, size, 0); |
19098df2 | 806 | if (IS_ERR(*umem)) { |
807 | mlx5_ib_dbg(dev, "umem_get failed\n"); | |
808 | return PTR_ERR(*umem); | |
809 | } | |
810 | ||
762f899a | 811 | mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); |
19098df2 | 812 | |
813 | err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); | |
814 | if (err) { | |
815 | mlx5_ib_warn(dev, "bad offset\n"); | |
816 | goto err_umem; | |
817 | } | |
818 | ||
819 | mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", | |
820 | addr, size, *npages, *page_shift, *ncont, *offset); | |
821 | ||
822 | return 0; | |
823 | ||
824 | err_umem: | |
825 | ib_umem_release(*umem); | |
826 | *umem = NULL; | |
827 | ||
828 | return err; | |
829 | } | |
830 | ||
fe248c3a | 831 | static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
bdeacabd | 832 | struct mlx5_ib_rwq *rwq, struct ib_udata *udata) |
79b20a6c | 833 | { |
bdeacabd SR |
834 | struct mlx5_ib_ucontext *context = |
835 | rdma_udata_to_drv_context( | |
836 | udata, | |
837 | struct mlx5_ib_ucontext, | |
838 | ibucontext); | |
79b20a6c | 839 | |
fe248c3a MG |
840 | if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) |
841 | atomic_dec(&dev->delay_drop.rqs_cnt); | |
842 | ||
79b20a6c | 843 | mlx5_ib_db_unmap_user(context, &rwq->db); |
836a0fbb | 844 | ib_umem_release(rwq->umem); |
79b20a6c YH |
845 | } |
846 | ||
847 | static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, | |
b0ea0fa5 | 848 | struct ib_udata *udata, struct mlx5_ib_rwq *rwq, |
79b20a6c YH |
849 | struct mlx5_ib_create_wq *ucmd) |
850 | { | |
89944450 SR |
851 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
852 | udata, struct mlx5_ib_ucontext, ibucontext); | |
79b20a6c YH |
853 | int page_shift = 0; |
854 | int npages; | |
855 | u32 offset = 0; | |
856 | int ncont = 0; | |
857 | int err; | |
858 | ||
859 | if (!ucmd->buf_addr) | |
860 | return -EINVAL; | |
861 | ||
c320e527 | 862 | rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0); |
79b20a6c YH |
863 | if (IS_ERR(rwq->umem)) { |
864 | mlx5_ib_dbg(dev, "umem_get failed\n"); | |
865 | err = PTR_ERR(rwq->umem); | |
866 | return err; | |
867 | } | |
868 | ||
762f899a | 869 | mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, |
79b20a6c YH |
870 | &ncont, NULL); |
871 | err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, | |
872 | &rwq->rq_page_offset); | |
873 | if (err) { | |
874 | mlx5_ib_warn(dev, "bad offset\n"); | |
875 | goto err_umem; | |
876 | } | |
877 | ||
878 | rwq->rq_num_pas = ncont; | |
879 | rwq->page_shift = page_shift; | |
880 | rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; | |
881 | rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); | |
882 | ||
883 | mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", | |
884 | (unsigned long long)ucmd->buf_addr, rwq->buf_size, | |
885 | npages, page_shift, ncont, offset); | |
886 | ||
89944450 | 887 | err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); |
79b20a6c YH |
888 | if (err) { |
889 | mlx5_ib_dbg(dev, "map failed\n"); | |
890 | goto err_umem; | |
891 | } | |
892 | ||
893 | rwq->create_type = MLX5_WQ_USER; | |
894 | return 0; | |
895 | ||
896 | err_umem: | |
897 | ib_umem_release(rwq->umem); | |
898 | return err; | |
899 | } | |
900 | ||
b037c29a EC |
901 | static int adjust_bfregn(struct mlx5_ib_dev *dev, |
902 | struct mlx5_bfreg_info *bfregi, int bfregn) | |
903 | { | |
904 | return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + | |
905 | bfregn % MLX5_NON_FP_BFREGS_PER_UAR; | |
906 | } | |
907 | ||
e126ba97 EC |
908 | static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
909 | struct mlx5_ib_qp *qp, struct ib_udata *udata, | |
0fb2ed66 | 910 | struct ib_qp_init_attr *attr, |
09a7d9ec | 911 | u32 **in, |
19098df2 | 912 | struct mlx5_ib_create_qp_resp *resp, int *inlen, |
913 | struct mlx5_ib_qp_base *base) | |
e126ba97 EC |
914 | { |
915 | struct mlx5_ib_ucontext *context; | |
916 | struct mlx5_ib_create_qp ucmd; | |
19098df2 | 917 | struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; |
9e9c47d0 | 918 | int page_shift = 0; |
1ee47ab3 | 919 | int uar_index = 0; |
e126ba97 | 920 | int npages; |
9e9c47d0 | 921 | u32 offset = 0; |
2f5ff264 | 922 | int bfregn; |
9e9c47d0 | 923 | int ncont = 0; |
09a7d9ec SM |
924 | __be64 *pas; |
925 | void *qpc; | |
e126ba97 | 926 | int err; |
5aa3771d | 927 | u16 uid; |
ac42a5ee | 928 | u32 uar_flags; |
e126ba97 EC |
929 | |
930 | err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); | |
931 | if (err) { | |
932 | mlx5_ib_dbg(dev, "copy failed\n"); | |
933 | return err; | |
934 | } | |
935 | ||
89944450 SR |
936 | context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, |
937 | ibucontext); | |
ac42a5ee YH |
938 | uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX | |
939 | MLX5_QP_FLAG_BFREG_INDEX); | |
940 | switch (uar_flags) { | |
941 | case MLX5_QP_FLAG_UAR_PAGE_INDEX: | |
942 | uar_index = ucmd.bfreg_index; | |
943 | bfregn = MLX5_IB_INVALID_BFREG; | |
944 | break; | |
945 | case MLX5_QP_FLAG_BFREG_INDEX: | |
1ee47ab3 YH |
946 | uar_index = bfregn_to_uar_index(dev, &context->bfregi, |
947 | ucmd.bfreg_index, true); | |
948 | if (uar_index < 0) | |
949 | return uar_index; | |
1ee47ab3 | 950 | bfregn = MLX5_IB_INVALID_BFREG; |
ac42a5ee YH |
951 | break; |
952 | case 0: | |
953 | if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) | |
954 | return -EINVAL; | |
ffaf58de LR |
955 | bfregn = alloc_bfreg(dev, &context->bfregi); |
956 | if (bfregn < 0) | |
957 | return bfregn; | |
ac42a5ee YH |
958 | break; |
959 | default: | |
960 | return -EINVAL; | |
e126ba97 EC |
961 | } |
962 | ||
2f5ff264 | 963 | mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); |
1ee47ab3 YH |
964 | if (bfregn != MLX5_IB_INVALID_BFREG) |
965 | uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, | |
966 | false); | |
e126ba97 | 967 | |
48fea837 HE |
968 | qp->rq.offset = 0; |
969 | qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); | |
970 | qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; | |
971 | ||
0fb2ed66 | 972 | err = set_user_buf_size(dev, qp, &ucmd, base, attr); |
e126ba97 | 973 | if (err) |
2f5ff264 | 974 | goto err_bfreg; |
e126ba97 | 975 | |
19098df2 | 976 | if (ucmd.buf_addr && ubuffer->buf_size) { |
977 | ubuffer->buf_addr = ucmd.buf_addr; | |
b0ea0fa5 JG |
978 | err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, |
979 | ubuffer->buf_size, &ubuffer->umem, | |
980 | &npages, &page_shift, &ncont, &offset); | |
19098df2 | 981 | if (err) |
2f5ff264 | 982 | goto err_bfreg; |
9e9c47d0 | 983 | } else { |
19098df2 | 984 | ubuffer->umem = NULL; |
e126ba97 | 985 | } |
e126ba97 | 986 | |
09a7d9ec SM |
987 | *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + |
988 | MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; | |
1b9a07ee | 989 | *in = kvzalloc(*inlen, GFP_KERNEL); |
e126ba97 EC |
990 | if (!*in) { |
991 | err = -ENOMEM; | |
992 | goto err_umem; | |
993 | } | |
09a7d9ec | 994 | |
7422edce YH |
995 | uid = (attr->qp_type != IB_QPT_XRC_TGT && |
996 | attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; | |
5aa3771d | 997 | MLX5_SET(create_qp_in, *in, uid, uid); |
09a7d9ec | 998 | pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); |
19098df2 | 999 | if (ubuffer->umem) |
09a7d9ec SM |
1000 | mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); |
1001 | ||
1002 | qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); | |
1003 | ||
1004 | MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
1005 | MLX5_SET(qpc, qpc, page_offset, offset); | |
e126ba97 | 1006 | |
09a7d9ec | 1007 | MLX5_SET(qpc, qpc, uar_page, uar_index); |
1ee47ab3 YH |
1008 | if (bfregn != MLX5_IB_INVALID_BFREG) |
1009 | resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); | |
1010 | else | |
1011 | resp->bfreg_index = MLX5_IB_INVALID_BFREG; | |
2f5ff264 | 1012 | qp->bfregn = bfregn; |
e126ba97 | 1013 | |
b0ea0fa5 | 1014 | err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db); |
e126ba97 EC |
1015 | if (err) { |
1016 | mlx5_ib_dbg(dev, "map failed\n"); | |
1017 | goto err_free; | |
1018 | } | |
1019 | ||
41d902cb | 1020 | err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); |
e126ba97 EC |
1021 | if (err) { |
1022 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1023 | goto err_unmap; | |
1024 | } | |
1025 | qp->create_type = MLX5_QP_USER; | |
1026 | ||
1027 | return 0; | |
1028 | ||
1029 | err_unmap: | |
1030 | mlx5_ib_db_unmap_user(context, &qp->db); | |
1031 | ||
1032 | err_free: | |
479163f4 | 1033 | kvfree(*in); |
e126ba97 EC |
1034 | |
1035 | err_umem: | |
836a0fbb | 1036 | ib_umem_release(ubuffer->umem); |
e126ba97 | 1037 | |
2f5ff264 | 1038 | err_bfreg: |
1ee47ab3 YH |
1039 | if (bfregn != MLX5_IB_INVALID_BFREG) |
1040 | mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); | |
e126ba97 EC |
1041 | return err; |
1042 | } | |
1043 | ||
b037c29a | 1044 | static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
bdeacabd SR |
1045 | struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base, |
1046 | struct ib_udata *udata) | |
e126ba97 | 1047 | { |
bdeacabd SR |
1048 | struct mlx5_ib_ucontext *context = |
1049 | rdma_udata_to_drv_context( | |
1050 | udata, | |
1051 | struct mlx5_ib_ucontext, | |
1052 | ibucontext); | |
e126ba97 | 1053 | |
e126ba97 | 1054 | mlx5_ib_db_unmap_user(context, &qp->db); |
836a0fbb | 1055 | ib_umem_release(base->ubuffer.umem); |
1ee47ab3 YH |
1056 | |
1057 | /* | |
1058 | * Free only the BFREGs which are handled by the kernel. | |
1059 | * BFREGs of UARs allocated dynamically are handled by user. | |
1060 | */ | |
1061 | if (qp->bfregn != MLX5_IB_INVALID_BFREG) | |
1062 | mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); | |
e126ba97 EC |
1063 | } |
1064 | ||
34f4c955 GL |
1065 | /* get_sq_edge - Get the next nearby edge. |
1066 | * | |
1067 | * An 'edge' is defined as the first following address after the end | |
1068 | * of the fragment or the SQ. Accordingly, during the WQE construction | |
1069 | * which repetitively increases the pointer to write the next data, it | |
1070 | * simply should check if it gets to an edge. | |
1071 | * | |
1072 | * @sq - SQ buffer. | |
1073 | * @idx - Stride index in the SQ buffer. | |
1074 | * | |
1075 | * Return: | |
1076 | * The new edge. | |
1077 | */ | |
1078 | static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) | |
1079 | { | |
1080 | void *fragment_end; | |
1081 | ||
1082 | fragment_end = mlx5_frag_buf_get_wqe | |
1083 | (&sq->fbc, | |
1084 | mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); | |
1085 | ||
1086 | return fragment_end + MLX5_SEND_WQE_BB; | |
1087 | } | |
1088 | ||
e126ba97 EC |
1089 | static int create_kernel_qp(struct mlx5_ib_dev *dev, |
1090 | struct ib_qp_init_attr *init_attr, | |
1091 | struct mlx5_ib_qp *qp, | |
09a7d9ec | 1092 | u32 **in, int *inlen, |
19098df2 | 1093 | struct mlx5_ib_qp_base *base) |
e126ba97 | 1094 | { |
e126ba97 | 1095 | int uar_index; |
09a7d9ec | 1096 | void *qpc; |
e126ba97 EC |
1097 | int err; |
1098 | ||
c0a6cbb9 | 1099 | if (init_attr->create_flags & ~(IB_QP_CREATE_INTEGRITY_EN | |
f0313965 | 1100 | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | |
b11a4f9c | 1101 | IB_QP_CREATE_IPOIB_UD_LSO | |
93d576af | 1102 | IB_QP_CREATE_NETIF_QP | |
11f552e2 MG |
1103 | MLX5_IB_QP_CREATE_SQPN_QP1 | |
1104 | MLX5_IB_QP_CREATE_WC_TEST)) | |
1a4c3a3d | 1105 | return -EINVAL; |
e126ba97 EC |
1106 | |
1107 | if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) | |
5fe9dec0 | 1108 | qp->bf.bfreg = &dev->fp_bfreg; |
11f552e2 MG |
1109 | else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) |
1110 | qp->bf.bfreg = &dev->wc_bfreg; | |
5fe9dec0 EC |
1111 | else |
1112 | qp->bf.bfreg = &dev->bfreg; | |
e126ba97 | 1113 | |
d8030b0d EC |
1114 | /* We need to divide by two since each register is comprised of |
1115 | * two buffers of identical size, namely odd and even | |
1116 | */ | |
1117 | qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; | |
5fe9dec0 | 1118 | uar_index = qp->bf.bfreg->index; |
e126ba97 EC |
1119 | |
1120 | err = calc_sq_size(dev, init_attr, qp); | |
1121 | if (err < 0) { | |
1122 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5fe9dec0 | 1123 | return err; |
e126ba97 EC |
1124 | } |
1125 | ||
1126 | qp->rq.offset = 0; | |
1127 | qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; | |
19098df2 | 1128 | base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); |
e126ba97 | 1129 | |
34f4c955 GL |
1130 | err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, |
1131 | &qp->buf, dev->mdev->priv.numa_node); | |
e126ba97 EC |
1132 | if (err) { |
1133 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5fe9dec0 | 1134 | return err; |
e126ba97 EC |
1135 | } |
1136 | ||
34f4c955 GL |
1137 | if (qp->rq.wqe_cnt) |
1138 | mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, | |
1139 | ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); | |
1140 | ||
1141 | if (qp->sq.wqe_cnt) { | |
1142 | int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / | |
1143 | MLX5_SEND_WQE_BB; | |
1144 | mlx5_init_fbc_offset(qp->buf.frags + | |
1145 | (qp->sq.offset / PAGE_SIZE), | |
1146 | ilog2(MLX5_SEND_WQE_BB), | |
1147 | ilog2(qp->sq.wqe_cnt), | |
1148 | sq_strides_offset, &qp->sq.fbc); | |
1149 | ||
1150 | qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); | |
1151 | } | |
1152 | ||
09a7d9ec SM |
1153 | *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + |
1154 | MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; | |
1b9a07ee | 1155 | *in = kvzalloc(*inlen, GFP_KERNEL); |
e126ba97 EC |
1156 | if (!*in) { |
1157 | err = -ENOMEM; | |
1158 | goto err_buf; | |
1159 | } | |
09a7d9ec SM |
1160 | |
1161 | qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); | |
1162 | MLX5_SET(qpc, qpc, uar_page, uar_index); | |
1163 | MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
1164 | ||
e126ba97 | 1165 | /* Set "fast registration enabled" for all kernel QPs */ |
09a7d9ec SM |
1166 | MLX5_SET(qpc, qpc, fre, 1); |
1167 | MLX5_SET(qpc, qpc, rlky, 1); | |
e126ba97 | 1168 | |
3f89b01f | 1169 | if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { |
09a7d9ec | 1170 | MLX5_SET(qpc, qpc, deth_sqpn, 1); |
b11a4f9c HE |
1171 | qp->flags |= MLX5_IB_QP_SQPN_QP1; |
1172 | } | |
1173 | ||
34f4c955 GL |
1174 | mlx5_fill_page_frag_array(&qp->buf, |
1175 | (__be64 *)MLX5_ADDR_OF(create_qp_in, | |
1176 | *in, pas)); | |
e126ba97 | 1177 | |
9603b61d | 1178 | err = mlx5_db_alloc(dev->mdev, &qp->db); |
e126ba97 EC |
1179 | if (err) { |
1180 | mlx5_ib_dbg(dev, "err %d\n", err); | |
1181 | goto err_free; | |
1182 | } | |
1183 | ||
b5883008 LD |
1184 | qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, |
1185 | sizeof(*qp->sq.wrid), GFP_KERNEL); | |
1186 | qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, | |
1187 | sizeof(*qp->sq.wr_data), GFP_KERNEL); | |
1188 | qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, | |
1189 | sizeof(*qp->rq.wrid), GFP_KERNEL); | |
1190 | qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, | |
1191 | sizeof(*qp->sq.w_list), GFP_KERNEL); | |
1192 | qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, | |
1193 | sizeof(*qp->sq.wqe_head), GFP_KERNEL); | |
e126ba97 EC |
1194 | |
1195 | if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || | |
1196 | !qp->sq.w_list || !qp->sq.wqe_head) { | |
1197 | err = -ENOMEM; | |
1198 | goto err_wrid; | |
1199 | } | |
1200 | qp->create_type = MLX5_QP_KERNEL; | |
1201 | ||
1202 | return 0; | |
1203 | ||
1204 | err_wrid: | |
b5883008 LD |
1205 | kvfree(qp->sq.wqe_head); |
1206 | kvfree(qp->sq.w_list); | |
1207 | kvfree(qp->sq.wrid); | |
1208 | kvfree(qp->sq.wr_data); | |
1209 | kvfree(qp->rq.wrid); | |
f4044dac | 1210 | mlx5_db_free(dev->mdev, &qp->db); |
e126ba97 EC |
1211 | |
1212 | err_free: | |
479163f4 | 1213 | kvfree(*in); |
e126ba97 EC |
1214 | |
1215 | err_buf: | |
34f4c955 | 1216 | mlx5_frag_buf_free(dev->mdev, &qp->buf); |
e126ba97 EC |
1217 | return err; |
1218 | } | |
1219 | ||
1220 | static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) | |
1221 | { | |
b5883008 LD |
1222 | kvfree(qp->sq.wqe_head); |
1223 | kvfree(qp->sq.w_list); | |
1224 | kvfree(qp->sq.wrid); | |
1225 | kvfree(qp->sq.wr_data); | |
1226 | kvfree(qp->rq.wrid); | |
f4044dac | 1227 | mlx5_db_free(dev->mdev, &qp->db); |
34f4c955 | 1228 | mlx5_frag_buf_free(dev->mdev, &qp->buf); |
e126ba97 EC |
1229 | } |
1230 | ||
09a7d9ec | 1231 | static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) |
e126ba97 EC |
1232 | { |
1233 | if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || | |
c32a4f29 | 1234 | (attr->qp_type == MLX5_IB_QPT_DCI) || |
e126ba97 | 1235 | (attr->qp_type == IB_QPT_XRC_INI)) |
09a7d9ec | 1236 | return MLX5_SRQ_RQ; |
e126ba97 | 1237 | else if (!qp->has_rq) |
09a7d9ec | 1238 | return MLX5_ZERO_LEN_RQ; |
e126ba97 | 1239 | else |
09a7d9ec | 1240 | return MLX5_NON_ZERO_RQ; |
e126ba97 EC |
1241 | } |
1242 | ||
1243 | static int is_connected(enum ib_qp_type qp_type) | |
1244 | { | |
5d6ff1ba YC |
1245 | if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || |
1246 | qp_type == MLX5_IB_QPT_DCI) | |
e126ba97 EC |
1247 | return 1; |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
0fb2ed66 | 1252 | static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, |
c2e53b2c | 1253 | struct mlx5_ib_qp *qp, |
1cd6dbd3 YH |
1254 | struct mlx5_ib_sq *sq, u32 tdn, |
1255 | struct ib_pd *pd) | |
0fb2ed66 | 1256 | { |
c4f287c4 | 1257 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; |
0fb2ed66 | 1258 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
1259 | ||
1cd6dbd3 | 1260 | MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1261 | MLX5_SET(tisc, tisc, transport_domain, tdn); |
c2e53b2c YH |
1262 | if (qp->flags & MLX5_IB_QP_UNDERLAY) |
1263 | MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); | |
1264 | ||
0fb2ed66 | 1265 | return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); |
1266 | } | |
1267 | ||
1268 | static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, | |
1cd6dbd3 | 1269 | struct mlx5_ib_sq *sq, struct ib_pd *pd) |
0fb2ed66 | 1270 | { |
1cd6dbd3 | 1271 | mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); |
0fb2ed66 | 1272 | } |
1273 | ||
d5ed8ac3 | 1274 | static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq) |
b96c9dde MB |
1275 | { |
1276 | if (sq->flow_rule) | |
1277 | mlx5_del_flow_rules(sq->flow_rule); | |
d5ed8ac3 | 1278 | sq->flow_rule = NULL; |
b96c9dde MB |
1279 | } |
1280 | ||
0fb2ed66 | 1281 | static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, |
b0ea0fa5 | 1282 | struct ib_udata *udata, |
0fb2ed66 | 1283 | struct mlx5_ib_sq *sq, void *qpin, |
1284 | struct ib_pd *pd) | |
1285 | { | |
1286 | struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; | |
1287 | __be64 *pas; | |
1288 | void *in; | |
1289 | void *sqc; | |
1290 | void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); | |
1291 | void *wq; | |
1292 | int inlen; | |
1293 | int err; | |
1294 | int page_shift = 0; | |
1295 | int npages; | |
1296 | int ncont = 0; | |
1297 | u32 offset = 0; | |
1298 | ||
b0ea0fa5 JG |
1299 | err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, |
1300 | &sq->ubuffer.umem, &npages, &page_shift, &ncont, | |
1301 | &offset); | |
0fb2ed66 | 1302 | if (err) |
1303 | return err; | |
1304 | ||
1305 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; | |
1b9a07ee | 1306 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1307 | if (!in) { |
1308 | err = -ENOMEM; | |
1309 | goto err_umem; | |
1310 | } | |
1311 | ||
c14003f0 | 1312 | MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1313 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); |
1314 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); | |
795b609c BW |
1315 | if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) |
1316 | MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); | |
0fb2ed66 | 1317 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
1318 | MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); | |
1319 | MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); | |
1320 | MLX5_SET(sqc, sqc, tis_lst_sz, 1); | |
1321 | MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); | |
96dc3fc5 NO |
1322 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && |
1323 | MLX5_CAP_ETH(dev->mdev, swp)) | |
1324 | MLX5_SET(sqc, sqc, allow_swp, 1); | |
0fb2ed66 | 1325 | |
1326 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1327 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
1328 | MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); | |
1329 | MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); | |
1330 | MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); | |
1331 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); | |
1332 | MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); | |
1333 | MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
1334 | MLX5_SET(wq, wq, page_offset, offset); | |
1335 | ||
1336 | pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); | |
1337 | mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); | |
1338 | ||
1339 | err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); | |
1340 | ||
1341 | kvfree(in); | |
1342 | ||
1343 | if (err) | |
1344 | goto err_umem; | |
1345 | ||
1346 | return 0; | |
1347 | ||
1348 | err_umem: | |
1349 | ib_umem_release(sq->ubuffer.umem); | |
1350 | sq->ubuffer.umem = NULL; | |
1351 | ||
1352 | return err; | |
1353 | } | |
1354 | ||
1355 | static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, | |
1356 | struct mlx5_ib_sq *sq) | |
1357 | { | |
d5ed8ac3 | 1358 | destroy_flow_rule_vport_sq(sq); |
0fb2ed66 | 1359 | mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); |
1360 | ib_umem_release(sq->ubuffer.umem); | |
1361 | } | |
1362 | ||
2c292dbb | 1363 | static size_t get_rq_pas_size(void *qpc) |
0fb2ed66 | 1364 | { |
1365 | u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; | |
1366 | u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); | |
1367 | u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); | |
1368 | u32 page_offset = MLX5_GET(qpc, qpc, page_offset); | |
1369 | u32 po_quanta = 1 << (log_page_size - 6); | |
1370 | u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); | |
1371 | u32 page_size = 1 << log_page_size; | |
1372 | u32 rq_sz_po = rq_sz + (page_offset * po_quanta); | |
1373 | u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; | |
1374 | ||
1375 | return rq_num_pas * sizeof(u64); | |
1376 | } | |
1377 | ||
1378 | static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, | |
2c292dbb | 1379 | struct mlx5_ib_rq *rq, void *qpin, |
34d57585 | 1380 | size_t qpinlen, struct ib_pd *pd) |
0fb2ed66 | 1381 | { |
358e42ea | 1382 | struct mlx5_ib_qp *mqp = rq->base.container_mibqp; |
0fb2ed66 | 1383 | __be64 *pas; |
1384 | __be64 *qp_pas; | |
1385 | void *in; | |
1386 | void *rqc; | |
1387 | void *wq; | |
1388 | void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); | |
2c292dbb BP |
1389 | size_t rq_pas_size = get_rq_pas_size(qpc); |
1390 | size_t inlen; | |
0fb2ed66 | 1391 | int err; |
2c292dbb BP |
1392 | |
1393 | if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) | |
1394 | return -EINVAL; | |
0fb2ed66 | 1395 | |
1396 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; | |
1b9a07ee | 1397 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1398 | if (!in) |
1399 | return -ENOMEM; | |
1400 | ||
34d57585 | 1401 | MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1402 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); |
e4cc4fa7 NO |
1403 | if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) |
1404 | MLX5_SET(rqc, rqc, vsd, 1); | |
0fb2ed66 | 1405 | MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); |
1406 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); | |
1407 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
1408 | MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); | |
1409 | MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); | |
1410 | ||
358e42ea MD |
1411 | if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) |
1412 | MLX5_SET(rqc, rqc, scatter_fcs, 1); | |
1413 | ||
0fb2ed66 | 1414 | wq = MLX5_ADDR_OF(rqc, rqc, wq); |
1415 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
b1383aa6 NO |
1416 | if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) |
1417 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
0fb2ed66 | 1418 | MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); |
1419 | MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); | |
1420 | MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); | |
1421 | MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); | |
1422 | MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); | |
1423 | MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); | |
1424 | ||
1425 | pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); | |
1426 | qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); | |
1427 | memcpy(pas, qp_pas, rq_pas_size); | |
1428 | ||
1429 | err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); | |
1430 | ||
1431 | kvfree(in); | |
1432 | ||
1433 | return err; | |
1434 | } | |
1435 | ||
1436 | static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, | |
1437 | struct mlx5_ib_rq *rq) | |
1438 | { | |
1439 | mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); | |
1440 | } | |
1441 | ||
f95ef6cb MG |
1442 | static bool tunnel_offload_supported(struct mlx5_core_dev *dev) |
1443 | { | |
1444 | return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || | |
1445 | MLX5_CAP_ETH(dev, tunnel_stateless_gre) || | |
1446 | MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); | |
1447 | } | |
1448 | ||
0042f9e4 MB |
1449 | static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, |
1450 | struct mlx5_ib_rq *rq, | |
443c1cf9 YH |
1451 | u32 qp_flags_en, |
1452 | struct ib_pd *pd) | |
0042f9e4 MB |
1453 | { |
1454 | if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | | |
1455 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) | |
1456 | mlx5_ib_disable_lb(dev, false, true); | |
443c1cf9 | 1457 | mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); |
0042f9e4 MB |
1458 | } |
1459 | ||
0fb2ed66 | 1460 | static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, |
f95ef6cb | 1461 | struct mlx5_ib_rq *rq, u32 tdn, |
443c1cf9 | 1462 | u32 *qp_flags_en, |
1f1d6abb AL |
1463 | struct ib_pd *pd, |
1464 | u32 *out, int outlen) | |
0fb2ed66 | 1465 | { |
175edba8 | 1466 | u8 lb_flag = 0; |
0fb2ed66 | 1467 | u32 *in; |
1468 | void *tirc; | |
1469 | int inlen; | |
1470 | int err; | |
1471 | ||
1472 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 1473 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1474 | if (!in) |
1475 | return -ENOMEM; | |
1476 | ||
443c1cf9 | 1477 | MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1478 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
1479 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); | |
1480 | MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); | |
1481 | MLX5_SET(tirc, tirc, transport_domain, tdn); | |
175edba8 | 1482 | if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) |
f95ef6cb | 1483 | MLX5_SET(tirc, tirc, tunneled_offload_en, 1); |
0fb2ed66 | 1484 | |
175edba8 MB |
1485 | if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) |
1486 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; | |
1487 | ||
1488 | if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) | |
1489 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; | |
1490 | ||
6a4d00be | 1491 | if (dev->is_rep) { |
175edba8 MB |
1492 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; |
1493 | *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
1494 | } | |
1495 | ||
1496 | MLX5_SET(tirc, tirc, self_lb_block, lb_flag); | |
ec9c2fb8 | 1497 | |
1f1d6abb | 1498 | err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen); |
0fb2ed66 | 1499 | |
1f1d6abb | 1500 | rq->tirn = MLX5_GET(create_tir_out, out, tirn); |
0042f9e4 MB |
1501 | if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { |
1502 | err = mlx5_ib_enable_lb(dev, false, true); | |
1503 | ||
1504 | if (err) | |
443c1cf9 | 1505 | destroy_raw_packet_qp_tir(dev, rq, 0, pd); |
0042f9e4 | 1506 | } |
0fb2ed66 | 1507 | kvfree(in); |
1508 | ||
1509 | return err; | |
1510 | } | |
1511 | ||
0fb2ed66 | 1512 | static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
2c292dbb | 1513 | u32 *in, size_t inlen, |
7f72052c YH |
1514 | struct ib_pd *pd, |
1515 | struct ib_udata *udata, | |
1516 | struct mlx5_ib_create_qp_resp *resp) | |
0fb2ed66 | 1517 | { |
1518 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
1519 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1520 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
89944450 SR |
1521 | struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( |
1522 | udata, struct mlx5_ib_ucontext, ibucontext); | |
0fb2ed66 | 1523 | int err; |
1524 | u32 tdn = mucontext->tdn; | |
7f72052c | 1525 | u16 uid = to_mpd(pd)->uid; |
1f1d6abb | 1526 | u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; |
0fb2ed66 | 1527 | |
1528 | if (qp->sq.wqe_cnt) { | |
1cd6dbd3 | 1529 | err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); |
0fb2ed66 | 1530 | if (err) |
1531 | return err; | |
1532 | ||
b0ea0fa5 | 1533 | err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); |
0fb2ed66 | 1534 | if (err) |
1535 | goto err_destroy_tis; | |
1536 | ||
7f72052c YH |
1537 | if (uid) { |
1538 | resp->tisn = sq->tisn; | |
1539 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; | |
1540 | resp->sqn = sq->base.mqp.qpn; | |
1541 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; | |
1542 | } | |
1543 | ||
0fb2ed66 | 1544 | sq->base.container_mibqp = qp; |
1d31e9c0 | 1545 | sq->base.mqp.event = mlx5_ib_qp_event; |
0fb2ed66 | 1546 | } |
1547 | ||
1548 | if (qp->rq.wqe_cnt) { | |
358e42ea MD |
1549 | rq->base.container_mibqp = qp; |
1550 | ||
e4cc4fa7 NO |
1551 | if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) |
1552 | rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; | |
b1383aa6 NO |
1553 | if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) |
1554 | rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; | |
34d57585 | 1555 | err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); |
0fb2ed66 | 1556 | if (err) |
1557 | goto err_destroy_sq; | |
1558 | ||
1f1d6abb AL |
1559 | err = create_raw_packet_qp_tir( |
1560 | dev, rq, tdn, &qp->flags_en, pd, out, | |
1561 | MLX5_ST_SZ_BYTES(create_tir_out)); | |
0fb2ed66 | 1562 | if (err) |
1563 | goto err_destroy_rq; | |
7f72052c YH |
1564 | |
1565 | if (uid) { | |
1566 | resp->rqn = rq->base.mqp.qpn; | |
1567 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; | |
1568 | resp->tirn = rq->tirn; | |
1569 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; | |
1f1d6abb AL |
1570 | if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { |
1571 | resp->tir_icm_addr = MLX5_GET( | |
1572 | create_tir_out, out, icm_address_31_0); | |
1573 | resp->tir_icm_addr |= | |
1574 | (u64)MLX5_GET(create_tir_out, out, | |
1575 | icm_address_39_32) | |
1576 | << 32; | |
1577 | resp->tir_icm_addr |= | |
1578 | (u64)MLX5_GET(create_tir_out, out, | |
1579 | icm_address_63_40) | |
1580 | << 40; | |
1581 | resp->comp_mask |= | |
1582 | MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; | |
1583 | } | |
7f72052c | 1584 | } |
0fb2ed66 | 1585 | } |
1586 | ||
1587 | qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : | |
1588 | rq->base.mqp.qpn; | |
7f72052c YH |
1589 | err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); |
1590 | if (err) | |
1591 | goto err_destroy_tir; | |
0fb2ed66 | 1592 | |
1593 | return 0; | |
1594 | ||
7f72052c YH |
1595 | err_destroy_tir: |
1596 | destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); | |
0fb2ed66 | 1597 | err_destroy_rq: |
1598 | destroy_raw_packet_qp_rq(dev, rq); | |
1599 | err_destroy_sq: | |
1600 | if (!qp->sq.wqe_cnt) | |
1601 | return err; | |
1602 | destroy_raw_packet_qp_sq(dev, sq); | |
1603 | err_destroy_tis: | |
1cd6dbd3 | 1604 | destroy_raw_packet_qp_tis(dev, sq, pd); |
0fb2ed66 | 1605 | |
1606 | return err; | |
1607 | } | |
1608 | ||
1609 | static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, | |
1610 | struct mlx5_ib_qp *qp) | |
1611 | { | |
1612 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
1613 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1614 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
1615 | ||
1616 | if (qp->rq.wqe_cnt) { | |
443c1cf9 | 1617 | destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); |
0fb2ed66 | 1618 | destroy_raw_packet_qp_rq(dev, rq); |
1619 | } | |
1620 | ||
1621 | if (qp->sq.wqe_cnt) { | |
1622 | destroy_raw_packet_qp_sq(dev, sq); | |
1cd6dbd3 | 1623 | destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); |
0fb2ed66 | 1624 | } |
1625 | } | |
1626 | ||
1627 | static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, | |
1628 | struct mlx5_ib_raw_packet_qp *raw_packet_qp) | |
1629 | { | |
1630 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1631 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
1632 | ||
1633 | sq->sq = &qp->sq; | |
1634 | rq->rq = &qp->rq; | |
1635 | sq->doorbell = &qp->db; | |
1636 | rq->doorbell = &qp->db; | |
1637 | } | |
1638 | ||
28d61370 YH |
1639 | static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) |
1640 | { | |
0042f9e4 MB |
1641 | if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | |
1642 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) | |
1643 | mlx5_ib_disable_lb(dev, false, true); | |
443c1cf9 YH |
1644 | mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, |
1645 | to_mpd(qp->ibqp.pd)->uid); | |
28d61370 YH |
1646 | } |
1647 | ||
1648 | static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
1649 | struct ib_pd *pd, | |
1650 | struct ib_qp_init_attr *init_attr, | |
1651 | struct ib_udata *udata) | |
1652 | { | |
89944450 SR |
1653 | struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( |
1654 | udata, struct mlx5_ib_ucontext, ibucontext); | |
28d61370 YH |
1655 | struct mlx5_ib_create_qp_resp resp = {}; |
1656 | int inlen; | |
1f1d6abb | 1657 | int outlen; |
28d61370 YH |
1658 | int err; |
1659 | u32 *in; | |
1f1d6abb | 1660 | u32 *out; |
28d61370 YH |
1661 | void *tirc; |
1662 | void *hfso; | |
1663 | u32 selected_fields = 0; | |
2d93fc85 | 1664 | u32 outer_l4; |
28d61370 YH |
1665 | size_t min_resp_len; |
1666 | u32 tdn = mucontext->tdn; | |
1667 | struct mlx5_ib_create_qp_rss ucmd = {}; | |
1668 | size_t required_cmd_sz; | |
175edba8 | 1669 | u8 lb_flag = 0; |
28d61370 YH |
1670 | |
1671 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) | |
1672 | return -EOPNOTSUPP; | |
1673 | ||
1674 | if (init_attr->create_flags || init_attr->send_cq) | |
1675 | return -EINVAL; | |
1676 | ||
2f5ff264 | 1677 | min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); |
28d61370 YH |
1678 | if (udata->outlen < min_resp_len) |
1679 | return -EINVAL; | |
1680 | ||
f95ef6cb | 1681 | required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); |
28d61370 YH |
1682 | if (udata->inlen < required_cmd_sz) { |
1683 | mlx5_ib_dbg(dev, "invalid inlen\n"); | |
1684 | return -EINVAL; | |
1685 | } | |
1686 | ||
1687 | if (udata->inlen > sizeof(ucmd) && | |
1688 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
1689 | udata->inlen - sizeof(ucmd))) { | |
1690 | mlx5_ib_dbg(dev, "inlen is not supported\n"); | |
1691 | return -EOPNOTSUPP; | |
1692 | } | |
1693 | ||
1694 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { | |
1695 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1696 | return -EFAULT; | |
1697 | } | |
1698 | ||
1699 | if (ucmd.comp_mask) { | |
1700 | mlx5_ib_dbg(dev, "invalid comp mask\n"); | |
1701 | return -EOPNOTSUPP; | |
1702 | } | |
1703 | ||
175edba8 MB |
1704 | if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | |
1705 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | | |
1706 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { | |
f95ef6cb MG |
1707 | mlx5_ib_dbg(dev, "invalid flags\n"); |
1708 | return -EOPNOTSUPP; | |
1709 | } | |
1710 | ||
1711 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && | |
1712 | !tunnel_offload_supported(dev->mdev)) { | |
1713 | mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); | |
28d61370 YH |
1714 | return -EOPNOTSUPP; |
1715 | } | |
1716 | ||
309fa347 MG |
1717 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && |
1718 | !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { | |
1719 | mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); | |
1720 | return -EOPNOTSUPP; | |
1721 | } | |
1722 | ||
6a4d00be | 1723 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) { |
175edba8 MB |
1724 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; |
1725 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
1726 | } | |
1727 | ||
1728 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { | |
1729 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; | |
1730 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; | |
1731 | } | |
1732 | ||
41d902cb | 1733 | err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); |
28d61370 YH |
1734 | if (err) { |
1735 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1736 | return -EINVAL; | |
1737 | } | |
1738 | ||
1739 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1f1d6abb AL |
1740 | outlen = MLX5_ST_SZ_BYTES(create_tir_out); |
1741 | in = kvzalloc(inlen + outlen, GFP_KERNEL); | |
28d61370 YH |
1742 | if (!in) |
1743 | return -ENOMEM; | |
1744 | ||
1f1d6abb | 1745 | out = in + MLX5_ST_SZ_DW(create_tir_in); |
443c1cf9 | 1746 | MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); |
28d61370 YH |
1747 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
1748 | MLX5_SET(tirc, tirc, disp_type, | |
1749 | MLX5_TIRC_DISP_TYPE_INDIRECT); | |
1750 | MLX5_SET(tirc, tirc, indirect_table, | |
1751 | init_attr->rwq_ind_tbl->ind_tbl_num); | |
1752 | MLX5_SET(tirc, tirc, transport_domain, tdn); | |
1753 | ||
1754 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
f95ef6cb MG |
1755 | |
1756 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) | |
1757 | MLX5_SET(tirc, tirc, tunneled_offload_en, 1); | |
1758 | ||
175edba8 MB |
1759 | MLX5_SET(tirc, tirc, self_lb_block, lb_flag); |
1760 | ||
309fa347 MG |
1761 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) |
1762 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); | |
1763 | else | |
1764 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1765 | ||
28d61370 YH |
1766 | switch (ucmd.rx_hash_function) { |
1767 | case MLX5_RX_HASH_FUNC_TOEPLITZ: | |
1768 | { | |
1769 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); | |
1770 | size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); | |
1771 | ||
1772 | if (len != ucmd.rx_key_len) { | |
1773 | err = -EINVAL; | |
1774 | goto err; | |
1775 | } | |
1776 | ||
1777 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); | |
28d61370 YH |
1778 | memcpy(rss_key, ucmd.rx_hash_key, len); |
1779 | break; | |
1780 | } | |
1781 | default: | |
1782 | err = -EOPNOTSUPP; | |
1783 | goto err; | |
1784 | } | |
1785 | ||
1786 | if (!ucmd.rx_hash_fields_mask) { | |
1787 | /* special case when this TIR serves as steering entry without hashing */ | |
1788 | if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) | |
1789 | goto create_tir; | |
1790 | err = -EINVAL; | |
1791 | goto err; | |
1792 | } | |
1793 | ||
1794 | if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1795 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && | |
1796 | ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || | |
1797 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { | |
1798 | err = -EINVAL; | |
1799 | goto err; | |
1800 | } | |
1801 | ||
1802 | /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ | |
1803 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1804 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) | |
1805 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1806 | MLX5_L3_PROT_TYPE_IPV4); | |
1807 | else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || | |
1808 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) | |
1809 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1810 | MLX5_L3_PROT_TYPE_IPV6); | |
1811 | ||
2d93fc85 MB |
1812 | outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || |
1813 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | | |
1814 | ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || | |
1815 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | | |
1816 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; | |
1817 | ||
1818 | /* Check that only one l4 protocol is set */ | |
1819 | if (outer_l4 & (outer_l4 - 1)) { | |
28d61370 YH |
1820 | err = -EINVAL; |
1821 | goto err; | |
1822 | } | |
1823 | ||
1824 | /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ | |
1825 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || | |
1826 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) | |
1827 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1828 | MLX5_L4_PROT_TYPE_TCP); | |
1829 | else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || | |
1830 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) | |
1831 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1832 | MLX5_L4_PROT_TYPE_UDP); | |
1833 | ||
1834 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1835 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) | |
1836 | selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; | |
1837 | ||
1838 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || | |
1839 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) | |
1840 | selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; | |
1841 | ||
1842 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || | |
1843 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) | |
1844 | selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; | |
1845 | ||
1846 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || | |
1847 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) | |
1848 | selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; | |
1849 | ||
2d93fc85 MB |
1850 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) |
1851 | selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; | |
1852 | ||
28d61370 YH |
1853 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); |
1854 | ||
1855 | create_tir: | |
1f1d6abb | 1856 | err = mlx5_core_create_tir_out(dev->mdev, in, inlen, out, outlen); |
28d61370 | 1857 | |
1f1d6abb | 1858 | qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn); |
0042f9e4 MB |
1859 | if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { |
1860 | err = mlx5_ib_enable_lb(dev, false, true); | |
1861 | ||
1862 | if (err) | |
443c1cf9 YH |
1863 | mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, |
1864 | to_mpd(pd)->uid); | |
0042f9e4 MB |
1865 | } |
1866 | ||
28d61370 YH |
1867 | if (err) |
1868 | goto err; | |
1869 | ||
7f72052c YH |
1870 | if (mucontext->devx_uid) { |
1871 | resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; | |
1872 | resp.tirn = qp->rss_qp.tirn; | |
1f1d6abb AL |
1873 | if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) { |
1874 | resp.tir_icm_addr = | |
1875 | MLX5_GET(create_tir_out, out, icm_address_31_0); | |
1876 | resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, | |
1877 | icm_address_39_32) | |
1878 | << 32; | |
1879 | resp.tir_icm_addr |= (u64)MLX5_GET(create_tir_out, out, | |
1880 | icm_address_63_40) | |
1881 | << 40; | |
1882 | resp.comp_mask |= | |
1883 | MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR; | |
1884 | } | |
7f72052c YH |
1885 | } |
1886 | ||
1887 | err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); | |
1888 | if (err) | |
1889 | goto err_copy; | |
1890 | ||
28d61370 YH |
1891 | kvfree(in); |
1892 | /* qpn is reserved for that QP */ | |
1893 | qp->trans_qp.base.mqp.qpn = 0; | |
d9f88e5a | 1894 | qp->flags |= MLX5_IB_QP_RSS; |
28d61370 YH |
1895 | return 0; |
1896 | ||
7f72052c YH |
1897 | err_copy: |
1898 | mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); | |
28d61370 YH |
1899 | err: |
1900 | kvfree(in); | |
1901 | return err; | |
1902 | } | |
1903 | ||
5d6ff1ba YC |
1904 | static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, |
1905 | void *qpc) | |
1906 | { | |
1907 | int rcqe_sz; | |
1908 | ||
1909 | if (init_attr->qp_type == MLX5_IB_QPT_DCI) | |
1910 | return; | |
1911 | ||
1912 | rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); | |
1913 | ||
7249c8ea GL |
1914 | if (init_attr->qp_type == MLX5_IB_QPT_DCT) { |
1915 | if (rcqe_sz == 128) | |
1916 | MLX5_SET(dctc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); | |
1917 | ||
5d6ff1ba YC |
1918 | return; |
1919 | } | |
1920 | ||
7249c8ea GL |
1921 | MLX5_SET(qpc, qpc, cs_res, |
1922 | rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE : | |
1923 | MLX5_RES_SCAT_DATA32_CQE); | |
5d6ff1ba YC |
1924 | } |
1925 | ||
1926 | static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, | |
1927 | struct ib_qp_init_attr *init_attr, | |
6f4bc0ea | 1928 | struct mlx5_ib_create_qp *ucmd, |
5d6ff1ba YC |
1929 | void *qpc) |
1930 | { | |
1931 | enum ib_qp_type qpt = init_attr->qp_type; | |
1932 | int scqe_sz; | |
2ab367a7 | 1933 | bool allow_scat_cqe = false; |
5d6ff1ba YC |
1934 | |
1935 | if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) | |
1936 | return; | |
1937 | ||
6f4bc0ea YC |
1938 | if (ucmd) |
1939 | allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; | |
1940 | ||
1941 | if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) | |
5d6ff1ba YC |
1942 | return; |
1943 | ||
1944 | scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); | |
1945 | if (scqe_sz == 128) { | |
1946 | MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); | |
1947 | return; | |
1948 | } | |
1949 | ||
1950 | if (init_attr->qp_type != MLX5_IB_QPT_DCI || | |
1951 | MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) | |
1952 | MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); | |
1953 | } | |
1954 | ||
a60109dc YC |
1955 | static int atomic_size_to_mode(int size_mask) |
1956 | { | |
1957 | /* driver does not support atomic_size > 256B | |
1958 | * and does not know how to translate bigger sizes | |
1959 | */ | |
1960 | int supported_size_mask = size_mask & 0x1ff; | |
1961 | int log_max_size; | |
1962 | ||
1963 | if (!supported_size_mask) | |
1964 | return -EOPNOTSUPP; | |
1965 | ||
1966 | log_max_size = __fls(supported_size_mask); | |
1967 | ||
1968 | if (log_max_size > 3) | |
1969 | return log_max_size; | |
1970 | ||
1971 | return MLX5_ATOMIC_MODE_8B; | |
1972 | } | |
1973 | ||
1974 | static int get_atomic_mode(struct mlx5_ib_dev *dev, | |
1975 | enum ib_qp_type qp_type) | |
1976 | { | |
1977 | u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); | |
1978 | u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); | |
1979 | int atomic_mode = -EOPNOTSUPP; | |
1980 | int atomic_size_mask; | |
1981 | ||
1982 | if (!atomic) | |
1983 | return -EOPNOTSUPP; | |
1984 | ||
1985 | if (qp_type == MLX5_IB_QPT_DCT) | |
1986 | atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); | |
1987 | else | |
1988 | atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); | |
1989 | ||
1990 | if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || | |
1991 | (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) | |
1992 | atomic_mode = atomic_size_to_mode(atomic_size_mask); | |
1993 | ||
1994 | if (atomic_mode <= 0 && | |
1995 | (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && | |
1996 | atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) | |
1997 | atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; | |
1998 | ||
1999 | return atomic_mode; | |
2000 | } | |
2001 | ||
2e43bb31 YC |
2002 | static inline bool check_flags_mask(uint64_t input, uint64_t supported) |
2003 | { | |
2004 | return (input & ~supported) == 0; | |
2005 | } | |
2006 | ||
e126ba97 EC |
2007 | static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
2008 | struct ib_qp_init_attr *init_attr, | |
2009 | struct ib_udata *udata, struct mlx5_ib_qp *qp) | |
2010 | { | |
2011 | struct mlx5_ib_resources *devr = &dev->devr; | |
09a7d9ec | 2012 | int inlen = MLX5_ST_SZ_BYTES(create_qp_in); |
938fe83c | 2013 | struct mlx5_core_dev *mdev = dev->mdev; |
0625b4ba | 2014 | struct mlx5_ib_create_qp_resp resp = {}; |
89944450 SR |
2015 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
2016 | udata, struct mlx5_ib_ucontext, ibucontext); | |
89ea94a7 MG |
2017 | struct mlx5_ib_cq *send_cq; |
2018 | struct mlx5_ib_cq *recv_cq; | |
2019 | unsigned long flags; | |
cfb5e088 | 2020 | u32 uidx = MLX5_IB_DEFAULT_UIDX; |
09a7d9ec SM |
2021 | struct mlx5_ib_create_qp ucmd; |
2022 | struct mlx5_ib_qp_base *base; | |
e7b169f3 | 2023 | int mlx5_st; |
cfb5e088 | 2024 | void *qpc; |
09a7d9ec SM |
2025 | u32 *in; |
2026 | int err; | |
e126ba97 EC |
2027 | |
2028 | mutex_init(&qp->mutex); | |
2029 | spin_lock_init(&qp->sq.lock); | |
2030 | spin_lock_init(&qp->rq.lock); | |
2031 | ||
e7b169f3 NO |
2032 | mlx5_st = to_mlx5_st(init_attr->qp_type); |
2033 | if (mlx5_st < 0) | |
2034 | return -EINVAL; | |
2035 | ||
28d61370 YH |
2036 | if (init_attr->rwq_ind_tbl) { |
2037 | if (!udata) | |
2038 | return -ENOSYS; | |
2039 | ||
2040 | err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); | |
2041 | return err; | |
2042 | } | |
2043 | ||
f360d88a | 2044 | if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { |
938fe83c | 2045 | if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { |
f360d88a EC |
2046 | mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); |
2047 | return -EINVAL; | |
2048 | } else { | |
2049 | qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; | |
2050 | } | |
2051 | } | |
2052 | ||
051f2630 LR |
2053 | if (init_attr->create_flags & |
2054 | (IB_QP_CREATE_CROSS_CHANNEL | | |
2055 | IB_QP_CREATE_MANAGED_SEND | | |
2056 | IB_QP_CREATE_MANAGED_RECV)) { | |
2057 | if (!MLX5_CAP_GEN(mdev, cd)) { | |
2058 | mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); | |
2059 | return -EINVAL; | |
2060 | } | |
2061 | if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) | |
2062 | qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; | |
2063 | if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) | |
2064 | qp->flags |= MLX5_IB_QP_MANAGED_SEND; | |
2065 | if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) | |
2066 | qp->flags |= MLX5_IB_QP_MANAGED_RECV; | |
2067 | } | |
f0313965 ES |
2068 | |
2069 | if (init_attr->qp_type == IB_QPT_UD && | |
2070 | (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) | |
2071 | if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { | |
2072 | mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); | |
2073 | return -EOPNOTSUPP; | |
2074 | } | |
2075 | ||
358e42ea MD |
2076 | if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { |
2077 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
2078 | mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); | |
2079 | return -EOPNOTSUPP; | |
2080 | } | |
2081 | if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || | |
2082 | !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { | |
2083 | mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); | |
2084 | return -EOPNOTSUPP; | |
2085 | } | |
2086 | qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; | |
2087 | } | |
2088 | ||
e126ba97 EC |
2089 | if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) |
2090 | qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; | |
2091 | ||
e4cc4fa7 NO |
2092 | if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { |
2093 | if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && | |
2094 | MLX5_CAP_ETH(dev->mdev, vlan_cap)) || | |
2095 | (init_attr->qp_type != IB_QPT_RAW_PACKET)) | |
2096 | return -EOPNOTSUPP; | |
2097 | qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; | |
2098 | } | |
2099 | ||
e00b64f7 | 2100 | if (udata) { |
e126ba97 EC |
2101 | if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { |
2102 | mlx5_ib_dbg(dev, "copy failed\n"); | |
2103 | return -EFAULT; | |
2104 | } | |
2105 | ||
2e43bb31 | 2106 | if (!check_flags_mask(ucmd.flags, |
8af526e0 MB |
2107 | MLX5_QP_FLAG_ALLOW_SCATTER_CQE | |
2108 | MLX5_QP_FLAG_BFREG_INDEX | | |
2109 | MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE | | |
2110 | MLX5_QP_FLAG_SCATTER_CQE | | |
2e43bb31 | 2111 | MLX5_QP_FLAG_SIGNATURE | |
8af526e0 MB |
2112 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC | |
2113 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | | |
2114 | MLX5_QP_FLAG_TUNNEL_OFFLOADS | | |
ac42a5ee | 2115 | MLX5_QP_FLAG_UAR_PAGE_INDEX | |
8af526e0 MB |
2116 | MLX5_QP_FLAG_TYPE_DCI | |
2117 | MLX5_QP_FLAG_TYPE_DCT)) | |
2e43bb31 YC |
2118 | return -EINVAL; |
2119 | ||
89944450 | 2120 | err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx); |
cfb5e088 HA |
2121 | if (err) |
2122 | return err; | |
2123 | ||
e126ba97 | 2124 | qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); |
5d6ff1ba YC |
2125 | if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) |
2126 | qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); | |
f95ef6cb MG |
2127 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { |
2128 | if (init_attr->qp_type != IB_QPT_RAW_PACKET || | |
2129 | !tunnel_offload_supported(mdev)) { | |
2130 | mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); | |
2131 | return -EOPNOTSUPP; | |
2132 | } | |
175edba8 MB |
2133 | qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; |
2134 | } | |
2135 | ||
2136 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { | |
2137 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
2138 | mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); | |
2139 | return -EOPNOTSUPP; | |
2140 | } | |
2141 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
2142 | } | |
2143 | ||
2144 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { | |
2145 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
2146 | mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); | |
2147 | return -EOPNOTSUPP; | |
2148 | } | |
2149 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; | |
f95ef6cb | 2150 | } |
c2e53b2c | 2151 | |
569c6651 DG |
2152 | if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { |
2153 | if (init_attr->qp_type != IB_QPT_RC || | |
2154 | !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { | |
2155 | mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); | |
2156 | return -EOPNOTSUPP; | |
2157 | } | |
2158 | qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; | |
2159 | } | |
2160 | ||
c2e53b2c YH |
2161 | if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { |
2162 | if (init_attr->qp_type != IB_QPT_UD || | |
2163 | (MLX5_CAP_GEN(dev->mdev, port_type) != | |
2164 | MLX5_CAP_PORT_TYPE_IB) || | |
2165 | !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { | |
2166 | mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); | |
2167 | return -EOPNOTSUPP; | |
2168 | } | |
2169 | ||
2170 | qp->flags |= MLX5_IB_QP_UNDERLAY; | |
2171 | qp->underlay_qpn = init_attr->source_qpn; | |
2172 | } | |
e126ba97 EC |
2173 | } else { |
2174 | qp->wq_sig = !!wq_signature; | |
2175 | } | |
2176 | ||
c2e53b2c YH |
2177 | base = (init_attr->qp_type == IB_QPT_RAW_PACKET || |
2178 | qp->flags & MLX5_IB_QP_UNDERLAY) ? | |
2179 | &qp->raw_packet_qp.rq.base : | |
2180 | &qp->trans_qp.base; | |
2181 | ||
e126ba97 EC |
2182 | qp->has_rq = qp_has_rq(init_attr); |
2183 | err = set_rq_size(dev, &init_attr->cap, qp->has_rq, | |
e00b64f7 | 2184 | qp, udata ? &ucmd : NULL); |
e126ba97 EC |
2185 | if (err) { |
2186 | mlx5_ib_dbg(dev, "err %d\n", err); | |
2187 | return err; | |
2188 | } | |
2189 | ||
2190 | if (pd) { | |
e00b64f7 | 2191 | if (udata) { |
938fe83c SM |
2192 | __u32 max_wqes = |
2193 | 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); | |
e126ba97 EC |
2194 | mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); |
2195 | if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || | |
2196 | ucmd.rq_wqe_count != qp->rq.wqe_cnt) { | |
2197 | mlx5_ib_dbg(dev, "invalid rq params\n"); | |
2198 | return -EINVAL; | |
2199 | } | |
938fe83c | 2200 | if (ucmd.sq_wqe_count > max_wqes) { |
e126ba97 | 2201 | mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", |
938fe83c | 2202 | ucmd.sq_wqe_count, max_wqes); |
e126ba97 EC |
2203 | return -EINVAL; |
2204 | } | |
b11a4f9c | 2205 | if (init_attr->create_flags & |
3f89b01f | 2206 | MLX5_IB_QP_CREATE_SQPN_QP1) { |
b11a4f9c HE |
2207 | mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); |
2208 | return -EINVAL; | |
2209 | } | |
0fb2ed66 | 2210 | err = create_user_qp(dev, pd, qp, udata, init_attr, &in, |
2211 | &resp, &inlen, base); | |
e126ba97 EC |
2212 | if (err) |
2213 | mlx5_ib_dbg(dev, "err %d\n", err); | |
2214 | } else { | |
19098df2 | 2215 | err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, |
2216 | base); | |
e126ba97 EC |
2217 | if (err) |
2218 | mlx5_ib_dbg(dev, "err %d\n", err); | |
e126ba97 EC |
2219 | } |
2220 | ||
2221 | if (err) | |
2222 | return err; | |
2223 | } else { | |
1b9a07ee | 2224 | in = kvzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
2225 | if (!in) |
2226 | return -ENOMEM; | |
2227 | ||
2228 | qp->create_type = MLX5_QP_EMPTY; | |
2229 | } | |
2230 | ||
2231 | if (is_sqp(init_attr->qp_type)) | |
2232 | qp->port = init_attr->port_num; | |
2233 | ||
09a7d9ec SM |
2234 | qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); |
2235 | ||
e7b169f3 | 2236 | MLX5_SET(qpc, qpc, st, mlx5_st); |
09a7d9ec | 2237 | MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); |
e126ba97 EC |
2238 | |
2239 | if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) | |
09a7d9ec | 2240 | MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); |
e126ba97 | 2241 | else |
09a7d9ec SM |
2242 | MLX5_SET(qpc, qpc, latency_sensitive, 1); |
2243 | ||
e126ba97 EC |
2244 | |
2245 | if (qp->wq_sig) | |
09a7d9ec | 2246 | MLX5_SET(qpc, qpc, wq_signature, 1); |
e126ba97 | 2247 | |
f360d88a | 2248 | if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) |
09a7d9ec | 2249 | MLX5_SET(qpc, qpc, block_lb_mc, 1); |
f360d88a | 2250 | |
051f2630 | 2251 | if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) |
09a7d9ec | 2252 | MLX5_SET(qpc, qpc, cd_master, 1); |
051f2630 | 2253 | if (qp->flags & MLX5_IB_QP_MANAGED_SEND) |
09a7d9ec | 2254 | MLX5_SET(qpc, qpc, cd_slave_send, 1); |
051f2630 | 2255 | if (qp->flags & MLX5_IB_QP_MANAGED_RECV) |
09a7d9ec | 2256 | MLX5_SET(qpc, qpc, cd_slave_receive, 1); |
569c6651 DG |
2257 | if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) |
2258 | MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); | |
e126ba97 | 2259 | if (qp->scat_cqe && is_connected(init_attr->qp_type)) { |
5d6ff1ba | 2260 | configure_responder_scat_cqe(init_attr, qpc); |
6f4bc0ea | 2261 | configure_requester_scat_cqe(dev, init_attr, |
e00b64f7 | 2262 | udata ? &ucmd : NULL, |
6f4bc0ea | 2263 | qpc); |
e126ba97 EC |
2264 | } |
2265 | ||
2266 | if (qp->rq.wqe_cnt) { | |
09a7d9ec SM |
2267 | MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); |
2268 | MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); | |
e126ba97 EC |
2269 | } |
2270 | ||
09a7d9ec | 2271 | MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); |
e126ba97 | 2272 | |
3fd3307e | 2273 | if (qp->sq.wqe_cnt) { |
09a7d9ec | 2274 | MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); |
3fd3307e | 2275 | } else { |
09a7d9ec | 2276 | MLX5_SET(qpc, qpc, no_sq, 1); |
3fd3307e AK |
2277 | if (init_attr->srq && |
2278 | init_attr->srq->srq_type == IB_SRQT_TM) | |
2279 | MLX5_SET(qpc, qpc, offload_type, | |
2280 | MLX5_QPC_OFFLOAD_TYPE_RNDV); | |
2281 | } | |
e126ba97 EC |
2282 | |
2283 | /* Set default resources */ | |
2284 | switch (init_attr->qp_type) { | |
2285 | case IB_QPT_XRC_TGT: | |
09a7d9ec SM |
2286 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); |
2287 | MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); | |
2288 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); | |
2289 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); | |
e126ba97 EC |
2290 | break; |
2291 | case IB_QPT_XRC_INI: | |
09a7d9ec SM |
2292 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); |
2293 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); | |
2294 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); | |
e126ba97 EC |
2295 | break; |
2296 | default: | |
2297 | if (init_attr->srq) { | |
09a7d9ec SM |
2298 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); |
2299 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); | |
e126ba97 | 2300 | } else { |
09a7d9ec SM |
2301 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); |
2302 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); | |
e126ba97 EC |
2303 | } |
2304 | } | |
2305 | ||
2306 | if (init_attr->send_cq) | |
09a7d9ec | 2307 | MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); |
e126ba97 EC |
2308 | |
2309 | if (init_attr->recv_cq) | |
09a7d9ec | 2310 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); |
e126ba97 | 2311 | |
09a7d9ec | 2312 | MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); |
e126ba97 | 2313 | |
09a7d9ec SM |
2314 | /* 0xffffff means we ask to work with cqe version 0 */ |
2315 | if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) | |
cfb5e088 | 2316 | MLX5_SET(qpc, qpc, user_index, uidx); |
09a7d9ec | 2317 | |
f0313965 ES |
2318 | /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ |
2319 | if (init_attr->qp_type == IB_QPT_UD && | |
2320 | (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { | |
f0313965 ES |
2321 | MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); |
2322 | qp->flags |= MLX5_IB_QP_LSO; | |
2323 | } | |
cfb5e088 | 2324 | |
b1383aa6 NO |
2325 | if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { |
2326 | if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { | |
2327 | mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); | |
2328 | err = -EOPNOTSUPP; | |
2329 | goto err; | |
2330 | } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
2331 | MLX5_SET(qpc, qpc, end_padding_mode, | |
2332 | MLX5_WQ_END_PAD_MODE_ALIGN); | |
2333 | } else { | |
2334 | qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; | |
2335 | } | |
2336 | } | |
2337 | ||
2c292dbb BP |
2338 | if (inlen < 0) { |
2339 | err = -EINVAL; | |
2340 | goto err; | |
2341 | } | |
2342 | ||
c2e53b2c YH |
2343 | if (init_attr->qp_type == IB_QPT_RAW_PACKET || |
2344 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 2345 | qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; |
2346 | raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); | |
7f72052c YH |
2347 | err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, |
2348 | &resp); | |
0fb2ed66 | 2349 | } else { |
2350 | err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); | |
2351 | } | |
2352 | ||
e126ba97 EC |
2353 | if (err) { |
2354 | mlx5_ib_dbg(dev, "create qp failed\n"); | |
2355 | goto err_create; | |
2356 | } | |
2357 | ||
479163f4 | 2358 | kvfree(in); |
e126ba97 | 2359 | |
19098df2 | 2360 | base->container_mibqp = qp; |
2361 | base->mqp.event = mlx5_ib_qp_event; | |
e126ba97 | 2362 | |
89ea94a7 MG |
2363 | get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, |
2364 | &send_cq, &recv_cq); | |
2365 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
2366 | mlx5_ib_lock_cqs(send_cq, recv_cq); | |
2367 | /* Maintain device to QPs access, needed for further handling via reset | |
2368 | * flow | |
2369 | */ | |
2370 | list_add_tail(&qp->qps_list, &dev->qp_list); | |
2371 | /* Maintain CQ to QPs access, needed for further handling via reset flow | |
2372 | */ | |
2373 | if (send_cq) | |
2374 | list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); | |
2375 | if (recv_cq) | |
2376 | list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); | |
2377 | mlx5_ib_unlock_cqs(send_cq, recv_cq); | |
2378 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
2379 | ||
e126ba97 EC |
2380 | return 0; |
2381 | ||
2382 | err_create: | |
2383 | if (qp->create_type == MLX5_QP_USER) | |
bdeacabd | 2384 | destroy_qp_user(dev, pd, qp, base, udata); |
e126ba97 EC |
2385 | else if (qp->create_type == MLX5_QP_KERNEL) |
2386 | destroy_qp_kernel(dev, qp); | |
2387 | ||
b1383aa6 | 2388 | err: |
479163f4 | 2389 | kvfree(in); |
e126ba97 EC |
2390 | return err; |
2391 | } | |
2392 | ||
2393 | static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) | |
2394 | __acquires(&send_cq->lock) __acquires(&recv_cq->lock) | |
2395 | { | |
2396 | if (send_cq) { | |
2397 | if (recv_cq) { | |
2398 | if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
89ea94a7 | 2399 | spin_lock(&send_cq->lock); |
e126ba97 EC |
2400 | spin_lock_nested(&recv_cq->lock, |
2401 | SINGLE_DEPTH_NESTING); | |
2402 | } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { | |
89ea94a7 | 2403 | spin_lock(&send_cq->lock); |
e126ba97 EC |
2404 | __acquire(&recv_cq->lock); |
2405 | } else { | |
89ea94a7 | 2406 | spin_lock(&recv_cq->lock); |
e126ba97 EC |
2407 | spin_lock_nested(&send_cq->lock, |
2408 | SINGLE_DEPTH_NESTING); | |
2409 | } | |
2410 | } else { | |
89ea94a7 | 2411 | spin_lock(&send_cq->lock); |
6a4f139a | 2412 | __acquire(&recv_cq->lock); |
e126ba97 EC |
2413 | } |
2414 | } else if (recv_cq) { | |
89ea94a7 | 2415 | spin_lock(&recv_cq->lock); |
6a4f139a EC |
2416 | __acquire(&send_cq->lock); |
2417 | } else { | |
2418 | __acquire(&send_cq->lock); | |
2419 | __acquire(&recv_cq->lock); | |
e126ba97 EC |
2420 | } |
2421 | } | |
2422 | ||
2423 | static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) | |
2424 | __releases(&send_cq->lock) __releases(&recv_cq->lock) | |
2425 | { | |
2426 | if (send_cq) { | |
2427 | if (recv_cq) { | |
2428 | if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
2429 | spin_unlock(&recv_cq->lock); | |
89ea94a7 | 2430 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2431 | } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { |
2432 | __release(&recv_cq->lock); | |
89ea94a7 | 2433 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2434 | } else { |
2435 | spin_unlock(&send_cq->lock); | |
89ea94a7 | 2436 | spin_unlock(&recv_cq->lock); |
e126ba97 EC |
2437 | } |
2438 | } else { | |
6a4f139a | 2439 | __release(&recv_cq->lock); |
89ea94a7 | 2440 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2441 | } |
2442 | } else if (recv_cq) { | |
6a4f139a | 2443 | __release(&send_cq->lock); |
89ea94a7 | 2444 | spin_unlock(&recv_cq->lock); |
6a4f139a EC |
2445 | } else { |
2446 | __release(&recv_cq->lock); | |
2447 | __release(&send_cq->lock); | |
e126ba97 EC |
2448 | } |
2449 | } | |
2450 | ||
2451 | static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) | |
2452 | { | |
2453 | return to_mpd(qp->ibqp.pd); | |
2454 | } | |
2455 | ||
89ea94a7 MG |
2456 | static void get_cqs(enum ib_qp_type qp_type, |
2457 | struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, | |
e126ba97 EC |
2458 | struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) |
2459 | { | |
89ea94a7 | 2460 | switch (qp_type) { |
e126ba97 EC |
2461 | case IB_QPT_XRC_TGT: |
2462 | *send_cq = NULL; | |
2463 | *recv_cq = NULL; | |
2464 | break; | |
2465 | case MLX5_IB_QPT_REG_UMR: | |
2466 | case IB_QPT_XRC_INI: | |
89ea94a7 | 2467 | *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; |
e126ba97 EC |
2468 | *recv_cq = NULL; |
2469 | break; | |
2470 | ||
2471 | case IB_QPT_SMI: | |
d16e91da | 2472 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 EC |
2473 | case IB_QPT_RC: |
2474 | case IB_QPT_UC: | |
2475 | case IB_QPT_UD: | |
2476 | case IB_QPT_RAW_IPV6: | |
2477 | case IB_QPT_RAW_ETHERTYPE: | |
0fb2ed66 | 2478 | case IB_QPT_RAW_PACKET: |
89ea94a7 MG |
2479 | *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; |
2480 | *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; | |
e126ba97 EC |
2481 | break; |
2482 | ||
e126ba97 EC |
2483 | case IB_QPT_MAX: |
2484 | default: | |
2485 | *send_cq = NULL; | |
2486 | *recv_cq = NULL; | |
2487 | break; | |
2488 | } | |
2489 | } | |
2490 | ||
ad5f8e96 | 2491 | static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
13eab21f AH |
2492 | const struct mlx5_modify_raw_qp_param *raw_qp_param, |
2493 | u8 lag_tx_affinity); | |
ad5f8e96 | 2494 | |
bdeacabd SR |
2495 | static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
2496 | struct ib_udata *udata) | |
e126ba97 EC |
2497 | { |
2498 | struct mlx5_ib_cq *send_cq, *recv_cq; | |
c2e53b2c | 2499 | struct mlx5_ib_qp_base *base; |
89ea94a7 | 2500 | unsigned long flags; |
e126ba97 EC |
2501 | int err; |
2502 | ||
28d61370 YH |
2503 | if (qp->ibqp.rwq_ind_tbl) { |
2504 | destroy_rss_raw_qp_tir(dev, qp); | |
2505 | return; | |
2506 | } | |
2507 | ||
c2e53b2c YH |
2508 | base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
2509 | qp->flags & MLX5_IB_QP_UNDERLAY) ? | |
0fb2ed66 | 2510 | &qp->raw_packet_qp.rq.base : |
2511 | &qp->trans_qp.base; | |
2512 | ||
6aec21f6 | 2513 | if (qp->state != IB_QPS_RESET) { |
c2e53b2c YH |
2514 | if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && |
2515 | !(qp->flags & MLX5_IB_QP_UNDERLAY)) { | |
ad5f8e96 | 2516 | err = mlx5_core_qp_modify(dev->mdev, |
1a412fb1 SM |
2517 | MLX5_CMD_OP_2RST_QP, 0, |
2518 | NULL, &base->mqp); | |
ad5f8e96 | 2519 | } else { |
0680efa2 AV |
2520 | struct mlx5_modify_raw_qp_param raw_qp_param = { |
2521 | .operation = MLX5_CMD_OP_2RST_QP | |
2522 | }; | |
2523 | ||
13eab21f | 2524 | err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); |
ad5f8e96 | 2525 | } |
2526 | if (err) | |
427c1e7b | 2527 | mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", |
19098df2 | 2528 | base->mqp.qpn); |
6aec21f6 | 2529 | } |
e126ba97 | 2530 | |
89ea94a7 MG |
2531 | get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, |
2532 | &send_cq, &recv_cq); | |
2533 | ||
2534 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
2535 | mlx5_ib_lock_cqs(send_cq, recv_cq); | |
2536 | /* del from lists under both locks above to protect reset flow paths */ | |
2537 | list_del(&qp->qps_list); | |
2538 | if (send_cq) | |
2539 | list_del(&qp->cq_send_list); | |
2540 | ||
2541 | if (recv_cq) | |
2542 | list_del(&qp->cq_recv_list); | |
e126ba97 EC |
2543 | |
2544 | if (qp->create_type == MLX5_QP_KERNEL) { | |
19098df2 | 2545 | __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, |
e126ba97 EC |
2546 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); |
2547 | if (send_cq != recv_cq) | |
19098df2 | 2548 | __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, |
2549 | NULL); | |
e126ba97 | 2550 | } |
89ea94a7 MG |
2551 | mlx5_ib_unlock_cqs(send_cq, recv_cq); |
2552 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
e126ba97 | 2553 | |
c2e53b2c YH |
2554 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
2555 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 2556 | destroy_raw_packet_qp(dev, qp); |
2557 | } else { | |
2558 | err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); | |
2559 | if (err) | |
2560 | mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", | |
2561 | base->mqp.qpn); | |
2562 | } | |
e126ba97 | 2563 | |
e126ba97 EC |
2564 | if (qp->create_type == MLX5_QP_KERNEL) |
2565 | destroy_qp_kernel(dev, qp); | |
2566 | else if (qp->create_type == MLX5_QP_USER) | |
bdeacabd | 2567 | destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); |
e126ba97 EC |
2568 | } |
2569 | ||
2570 | static const char *ib_qp_type_str(enum ib_qp_type type) | |
2571 | { | |
2572 | switch (type) { | |
2573 | case IB_QPT_SMI: | |
2574 | return "IB_QPT_SMI"; | |
2575 | case IB_QPT_GSI: | |
2576 | return "IB_QPT_GSI"; | |
2577 | case IB_QPT_RC: | |
2578 | return "IB_QPT_RC"; | |
2579 | case IB_QPT_UC: | |
2580 | return "IB_QPT_UC"; | |
2581 | case IB_QPT_UD: | |
2582 | return "IB_QPT_UD"; | |
2583 | case IB_QPT_RAW_IPV6: | |
2584 | return "IB_QPT_RAW_IPV6"; | |
2585 | case IB_QPT_RAW_ETHERTYPE: | |
2586 | return "IB_QPT_RAW_ETHERTYPE"; | |
2587 | case IB_QPT_XRC_INI: | |
2588 | return "IB_QPT_XRC_INI"; | |
2589 | case IB_QPT_XRC_TGT: | |
2590 | return "IB_QPT_XRC_TGT"; | |
2591 | case IB_QPT_RAW_PACKET: | |
2592 | return "IB_QPT_RAW_PACKET"; | |
2593 | case MLX5_IB_QPT_REG_UMR: | |
2594 | return "MLX5_IB_QPT_REG_UMR"; | |
b4aaa1f0 MS |
2595 | case IB_QPT_DRIVER: |
2596 | return "IB_QPT_DRIVER"; | |
e126ba97 EC |
2597 | case IB_QPT_MAX: |
2598 | default: | |
2599 | return "Invalid QP type"; | |
2600 | } | |
2601 | } | |
2602 | ||
b4aaa1f0 MS |
2603 | static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, |
2604 | struct ib_qp_init_attr *attr, | |
89944450 SR |
2605 | struct mlx5_ib_create_qp *ucmd, |
2606 | struct ib_udata *udata) | |
b4aaa1f0 | 2607 | { |
89944450 SR |
2608 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
2609 | udata, struct mlx5_ib_ucontext, ibucontext); | |
b4aaa1f0 MS |
2610 | struct mlx5_ib_qp *qp; |
2611 | int err = 0; | |
2612 | u32 uidx = MLX5_IB_DEFAULT_UIDX; | |
2613 | void *dctc; | |
2614 | ||
2615 | if (!attr->srq || !attr->recv_cq) | |
2616 | return ERR_PTR(-EINVAL); | |
2617 | ||
89944450 | 2618 | err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx); |
b4aaa1f0 MS |
2619 | if (err) |
2620 | return ERR_PTR(err); | |
2621 | ||
2622 | qp = kzalloc(sizeof(*qp), GFP_KERNEL); | |
2623 | if (!qp) | |
2624 | return ERR_PTR(-ENOMEM); | |
2625 | ||
2626 | qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); | |
2627 | if (!qp->dct.in) { | |
2628 | err = -ENOMEM; | |
2629 | goto err_free; | |
2630 | } | |
2631 | ||
a01a5860 | 2632 | MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); |
b4aaa1f0 | 2633 | dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); |
776a3906 | 2634 | qp->qp_sub_type = MLX5_IB_QPT_DCT; |
b4aaa1f0 MS |
2635 | MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); |
2636 | MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); | |
2637 | MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); | |
2638 | MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); | |
2639 | MLX5_SET(dctc, dctc, user_index, uidx); | |
2640 | ||
5d6ff1ba YC |
2641 | if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) |
2642 | configure_responder_scat_cqe(attr, dctc); | |
2643 | ||
b4aaa1f0 MS |
2644 | qp->state = IB_QPS_RESET; |
2645 | ||
2646 | return &qp->ibqp; | |
2647 | err_free: | |
2648 | kfree(qp); | |
2649 | return ERR_PTR(err); | |
2650 | } | |
2651 | ||
2652 | static int set_mlx_qp_type(struct mlx5_ib_dev *dev, | |
2653 | struct ib_qp_init_attr *init_attr, | |
2654 | struct mlx5_ib_create_qp *ucmd, | |
2655 | struct ib_udata *udata) | |
2656 | { | |
2657 | enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; | |
2658 | int err; | |
2659 | ||
2660 | if (!udata) | |
2661 | return -EINVAL; | |
2662 | ||
2663 | if (udata->inlen < sizeof(*ucmd)) { | |
2664 | mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); | |
2665 | return -EINVAL; | |
2666 | } | |
2667 | err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); | |
2668 | if (err) | |
2669 | return err; | |
2670 | ||
2671 | if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { | |
2672 | init_attr->qp_type = MLX5_IB_QPT_DCI; | |
2673 | } else { | |
2674 | if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { | |
2675 | init_attr->qp_type = MLX5_IB_QPT_DCT; | |
2676 | } else { | |
2677 | mlx5_ib_dbg(dev, "Invalid QP flags\n"); | |
2678 | return -EINVAL; | |
2679 | } | |
2680 | } | |
2681 | ||
2682 | if (!MLX5_CAP_GEN(dev->mdev, dct)) { | |
2683 | mlx5_ib_dbg(dev, "DC transport is not supported\n"); | |
2684 | return -EOPNOTSUPP; | |
2685 | } | |
2686 | ||
2687 | return 0; | |
2688 | } | |
2689 | ||
e126ba97 | 2690 | struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, |
b4aaa1f0 | 2691 | struct ib_qp_init_attr *verbs_init_attr, |
e126ba97 EC |
2692 | struct ib_udata *udata) |
2693 | { | |
2694 | struct mlx5_ib_dev *dev; | |
2695 | struct mlx5_ib_qp *qp; | |
2696 | u16 xrcdn = 0; | |
2697 | int err; | |
b4aaa1f0 MS |
2698 | struct ib_qp_init_attr mlx_init_attr; |
2699 | struct ib_qp_init_attr *init_attr = verbs_init_attr; | |
89944450 SR |
2700 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
2701 | udata, struct mlx5_ib_ucontext, ibucontext); | |
e126ba97 EC |
2702 | |
2703 | if (pd) { | |
2704 | dev = to_mdev(pd->device); | |
0fb2ed66 | 2705 | |
2706 | if (init_attr->qp_type == IB_QPT_RAW_PACKET) { | |
89944450 | 2707 | if (!ucontext) { |
0fb2ed66 | 2708 | mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); |
2709 | return ERR_PTR(-EINVAL); | |
89944450 | 2710 | } else if (!ucontext->cqe_version) { |
0fb2ed66 | 2711 | mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); |
2712 | return ERR_PTR(-EINVAL); | |
2713 | } | |
2714 | } | |
09f16cf5 MD |
2715 | } else { |
2716 | /* being cautious here */ | |
2717 | if (init_attr->qp_type != IB_QPT_XRC_TGT && | |
2718 | init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { | |
2719 | pr_warn("%s: no PD for transport %s\n", __func__, | |
2720 | ib_qp_type_str(init_attr->qp_type)); | |
2721 | return ERR_PTR(-EINVAL); | |
2722 | } | |
2723 | dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); | |
e126ba97 EC |
2724 | } |
2725 | ||
b4aaa1f0 MS |
2726 | if (init_attr->qp_type == IB_QPT_DRIVER) { |
2727 | struct mlx5_ib_create_qp ucmd; | |
2728 | ||
2729 | init_attr = &mlx_init_attr; | |
2730 | memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); | |
2731 | err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); | |
2732 | if (err) | |
2733 | return ERR_PTR(err); | |
c32a4f29 MS |
2734 | |
2735 | if (init_attr->qp_type == MLX5_IB_QPT_DCI) { | |
2736 | if (init_attr->cap.max_recv_wr || | |
2737 | init_attr->cap.max_recv_sge) { | |
2738 | mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); | |
2739 | return ERR_PTR(-EINVAL); | |
2740 | } | |
776a3906 | 2741 | } else { |
89944450 | 2742 | return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata); |
c32a4f29 | 2743 | } |
b4aaa1f0 MS |
2744 | } |
2745 | ||
e126ba97 EC |
2746 | switch (init_attr->qp_type) { |
2747 | case IB_QPT_XRC_TGT: | |
2748 | case IB_QPT_XRC_INI: | |
938fe83c | 2749 | if (!MLX5_CAP_GEN(dev->mdev, xrc)) { |
e126ba97 EC |
2750 | mlx5_ib_dbg(dev, "XRC not supported\n"); |
2751 | return ERR_PTR(-ENOSYS); | |
2752 | } | |
2753 | init_attr->recv_cq = NULL; | |
2754 | if (init_attr->qp_type == IB_QPT_XRC_TGT) { | |
2755 | xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; | |
2756 | init_attr->send_cq = NULL; | |
2757 | } | |
2758 | ||
2759 | /* fall through */ | |
0fb2ed66 | 2760 | case IB_QPT_RAW_PACKET: |
e126ba97 EC |
2761 | case IB_QPT_RC: |
2762 | case IB_QPT_UC: | |
2763 | case IB_QPT_UD: | |
2764 | case IB_QPT_SMI: | |
d16e91da | 2765 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 | 2766 | case MLX5_IB_QPT_REG_UMR: |
c32a4f29 | 2767 | case MLX5_IB_QPT_DCI: |
e126ba97 EC |
2768 | qp = kzalloc(sizeof(*qp), GFP_KERNEL); |
2769 | if (!qp) | |
2770 | return ERR_PTR(-ENOMEM); | |
2771 | ||
2772 | err = create_qp_common(dev, pd, init_attr, udata, qp); | |
2773 | if (err) { | |
2774 | mlx5_ib_dbg(dev, "create_qp_common failed\n"); | |
2775 | kfree(qp); | |
2776 | return ERR_PTR(err); | |
2777 | } | |
2778 | ||
2779 | if (is_qp0(init_attr->qp_type)) | |
2780 | qp->ibqp.qp_num = 0; | |
2781 | else if (is_qp1(init_attr->qp_type)) | |
2782 | qp->ibqp.qp_num = 1; | |
2783 | else | |
19098df2 | 2784 | qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; |
e126ba97 EC |
2785 | |
2786 | mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", | |
19098df2 | 2787 | qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, |
a1ab8402 EC |
2788 | init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, |
2789 | init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); | |
e126ba97 | 2790 | |
19098df2 | 2791 | qp->trans_qp.xrcdn = xrcdn; |
e126ba97 EC |
2792 | |
2793 | break; | |
2794 | ||
d16e91da HE |
2795 | case IB_QPT_GSI: |
2796 | return mlx5_ib_gsi_create_qp(pd, init_attr); | |
2797 | ||
e126ba97 EC |
2798 | case IB_QPT_RAW_IPV6: |
2799 | case IB_QPT_RAW_ETHERTYPE: | |
e126ba97 EC |
2800 | case IB_QPT_MAX: |
2801 | default: | |
2802 | mlx5_ib_dbg(dev, "unsupported qp type %d\n", | |
2803 | init_attr->qp_type); | |
2804 | /* Don't support raw QPs */ | |
bb8865f4 | 2805 | return ERR_PTR(-EOPNOTSUPP); |
e126ba97 EC |
2806 | } |
2807 | ||
b4aaa1f0 MS |
2808 | if (verbs_init_attr->qp_type == IB_QPT_DRIVER) |
2809 | qp->qp_sub_type = init_attr->qp_type; | |
2810 | ||
e126ba97 EC |
2811 | return &qp->ibqp; |
2812 | } | |
2813 | ||
776a3906 MS |
2814 | static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) |
2815 | { | |
2816 | struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); | |
2817 | ||
2818 | if (mqp->state == IB_QPS_RTR) { | |
2819 | int err; | |
2820 | ||
2821 | err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); | |
2822 | if (err) { | |
2823 | mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); | |
2824 | return err; | |
2825 | } | |
2826 | } | |
2827 | ||
2828 | kfree(mqp->dct.in); | |
2829 | kfree(mqp); | |
2830 | return 0; | |
2831 | } | |
2832 | ||
c4367a26 | 2833 | int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) |
e126ba97 EC |
2834 | { |
2835 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
2836 | struct mlx5_ib_qp *mqp = to_mqp(qp); | |
2837 | ||
d16e91da HE |
2838 | if (unlikely(qp->qp_type == IB_QPT_GSI)) |
2839 | return mlx5_ib_gsi_destroy_qp(qp); | |
2840 | ||
776a3906 MS |
2841 | if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) |
2842 | return mlx5_ib_destroy_dct(mqp); | |
2843 | ||
bdeacabd | 2844 | destroy_qp_common(dev, mqp, udata); |
e126ba97 EC |
2845 | |
2846 | kfree(mqp); | |
2847 | ||
2848 | return 0; | |
2849 | } | |
2850 | ||
a60109dc YC |
2851 | static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, |
2852 | const struct ib_qp_attr *attr, | |
bf3b4f06 | 2853 | int attr_mask, __be32 *hw_access_flags_be) |
e126ba97 | 2854 | { |
e126ba97 | 2855 | u8 dest_rd_atomic; |
bf3b4f06 | 2856 | u32 access_flags, hw_access_flags = 0; |
e126ba97 | 2857 | |
a60109dc YC |
2858 | struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); |
2859 | ||
e126ba97 EC |
2860 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) |
2861 | dest_rd_atomic = attr->max_dest_rd_atomic; | |
2862 | else | |
19098df2 | 2863 | dest_rd_atomic = qp->trans_qp.resp_depth; |
e126ba97 EC |
2864 | |
2865 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
2866 | access_flags = attr->qp_access_flags; | |
2867 | else | |
19098df2 | 2868 | access_flags = qp->trans_qp.atomic_rd_en; |
e126ba97 EC |
2869 | |
2870 | if (!dest_rd_atomic) | |
2871 | access_flags &= IB_ACCESS_REMOTE_WRITE; | |
2872 | ||
2873 | if (access_flags & IB_ACCESS_REMOTE_READ) | |
bf3b4f06 | 2874 | hw_access_flags |= MLX5_QP_BIT_RRE; |
13f8d9c1 | 2875 | if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { |
a60109dc YC |
2876 | int atomic_mode; |
2877 | ||
2878 | atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); | |
2879 | if (atomic_mode < 0) | |
2880 | return -EOPNOTSUPP; | |
2881 | ||
bf3b4f06 BVA |
2882 | hw_access_flags |= MLX5_QP_BIT_RAE; |
2883 | hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; | |
a60109dc YC |
2884 | } |
2885 | ||
e126ba97 | 2886 | if (access_flags & IB_ACCESS_REMOTE_WRITE) |
bf3b4f06 | 2887 | hw_access_flags |= MLX5_QP_BIT_RWE; |
a60109dc | 2888 | |
bf3b4f06 | 2889 | *hw_access_flags_be = cpu_to_be32(hw_access_flags); |
e126ba97 | 2890 | |
a60109dc | 2891 | return 0; |
e126ba97 EC |
2892 | } |
2893 | ||
2894 | enum { | |
2895 | MLX5_PATH_FLAG_FL = 1 << 0, | |
2896 | MLX5_PATH_FLAG_FREE_AR = 1 << 1, | |
2897 | MLX5_PATH_FLAG_COUNTER = 1 << 2, | |
2898 | }; | |
2899 | ||
2900 | static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) | |
2901 | { | |
4f32ac2e | 2902 | if (rate == IB_RATE_PORT_CURRENT) |
e126ba97 | 2903 | return 0; |
4f32ac2e | 2904 | |
a5a5d199 | 2905 | if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) |
e126ba97 | 2906 | return -EINVAL; |
e126ba97 | 2907 | |
4f32ac2e DG |
2908 | while (rate != IB_RATE_PORT_CURRENT && |
2909 | !(1 << (rate + MLX5_STAT_RATE_OFFSET) & | |
2910 | MLX5_CAP_GEN(dev->mdev, stat_rate_support))) | |
2911 | --rate; | |
2912 | ||
2913 | return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; | |
e126ba97 EC |
2914 | } |
2915 | ||
75850d0b | 2916 | static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, |
1cd6dbd3 YH |
2917 | struct mlx5_ib_sq *sq, u8 sl, |
2918 | struct ib_pd *pd) | |
75850d0b | 2919 | { |
2920 | void *in; | |
2921 | void *tisc; | |
2922 | int inlen; | |
2923 | int err; | |
2924 | ||
2925 | inlen = MLX5_ST_SZ_BYTES(modify_tis_in); | |
1b9a07ee | 2926 | in = kvzalloc(inlen, GFP_KERNEL); |
75850d0b | 2927 | if (!in) |
2928 | return -ENOMEM; | |
2929 | ||
2930 | MLX5_SET(modify_tis_in, in, bitmask.prio, 1); | |
1cd6dbd3 | 2931 | MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); |
75850d0b | 2932 | |
2933 | tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); | |
2934 | MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); | |
2935 | ||
2936 | err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); | |
2937 | ||
2938 | kvfree(in); | |
2939 | ||
2940 | return err; | |
2941 | } | |
2942 | ||
13eab21f | 2943 | static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, |
1cd6dbd3 YH |
2944 | struct mlx5_ib_sq *sq, u8 tx_affinity, |
2945 | struct ib_pd *pd) | |
13eab21f AH |
2946 | { |
2947 | void *in; | |
2948 | void *tisc; | |
2949 | int inlen; | |
2950 | int err; | |
2951 | ||
2952 | inlen = MLX5_ST_SZ_BYTES(modify_tis_in); | |
1b9a07ee | 2953 | in = kvzalloc(inlen, GFP_KERNEL); |
13eab21f AH |
2954 | if (!in) |
2955 | return -ENOMEM; | |
2956 | ||
2957 | MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); | |
1cd6dbd3 | 2958 | MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); |
13eab21f AH |
2959 | |
2960 | tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); | |
2961 | MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); | |
2962 | ||
2963 | err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); | |
2964 | ||
2965 | kvfree(in); | |
2966 | ||
2967 | return err; | |
2968 | } | |
2969 | ||
75850d0b | 2970 | static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
90898850 | 2971 | const struct rdma_ah_attr *ah, |
e126ba97 | 2972 | struct mlx5_qp_path *path, u8 port, int attr_mask, |
f879ee8d AS |
2973 | u32 path_flags, const struct ib_qp_attr *attr, |
2974 | bool alt) | |
e126ba97 | 2975 | { |
d8966fcd | 2976 | const struct ib_global_route *grh = rdma_ah_read_grh(ah); |
e126ba97 | 2977 | int err; |
ed88451e | 2978 | enum ib_gid_type gid_type; |
d8966fcd DC |
2979 | u8 ah_flags = rdma_ah_get_ah_flags(ah); |
2980 | u8 sl = rdma_ah_get_sl(ah); | |
e126ba97 | 2981 | |
e126ba97 | 2982 | if (attr_mask & IB_QP_PKEY_INDEX) |
f879ee8d AS |
2983 | path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : |
2984 | attr->pkey_index); | |
e126ba97 | 2985 | |
d8966fcd DC |
2986 | if (ah_flags & IB_AH_GRH) { |
2987 | if (grh->sgid_index >= | |
938fe83c | 2988 | dev->mdev->port_caps[port - 1].gid_table_len) { |
f4f01b54 | 2989 | pr_err("sgid_index (%u) too large. max is %d\n", |
d8966fcd | 2990 | grh->sgid_index, |
938fe83c | 2991 | dev->mdev->port_caps[port - 1].gid_table_len); |
f83b4263 EC |
2992 | return -EINVAL; |
2993 | } | |
2811ba51 | 2994 | } |
44c58487 DC |
2995 | |
2996 | if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { | |
d8966fcd | 2997 | if (!(ah_flags & IB_AH_GRH)) |
2811ba51 | 2998 | return -EINVAL; |
47ec3866 | 2999 | |
44c58487 | 3000 | memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); |
2b621851 MD |
3001 | if (qp->ibqp.qp_type == IB_QPT_RC || |
3002 | qp->ibqp.qp_type == IB_QPT_UC || | |
3003 | qp->ibqp.qp_type == IB_QPT_XRC_INI || | |
3004 | qp->ibqp.qp_type == IB_QPT_XRC_TGT) | |
47ec3866 PP |
3005 | path->udp_sport = |
3006 | mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); | |
d8966fcd | 3007 | path->dci_cfi_prio_sl = (sl & 0x7) << 4; |
47ec3866 | 3008 | gid_type = ah->grh.sgid_attr->gid_type; |
ed88451e | 3009 | if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) |
d8966fcd | 3010 | path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; |
2811ba51 | 3011 | } else { |
d3ae2bde NO |
3012 | path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; |
3013 | path->fl_free_ar |= | |
3014 | (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; | |
d8966fcd DC |
3015 | path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); |
3016 | path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; | |
3017 | if (ah_flags & IB_AH_GRH) | |
2811ba51 | 3018 | path->grh_mlid |= 1 << 7; |
d8966fcd | 3019 | path->dci_cfi_prio_sl = sl & 0xf; |
2811ba51 AS |
3020 | } |
3021 | ||
d8966fcd DC |
3022 | if (ah_flags & IB_AH_GRH) { |
3023 | path->mgid_index = grh->sgid_index; | |
3024 | path->hop_limit = grh->hop_limit; | |
e126ba97 | 3025 | path->tclass_flowlabel = |
d8966fcd DC |
3026 | cpu_to_be32((grh->traffic_class << 20) | |
3027 | (grh->flow_label)); | |
3028 | memcpy(path->rgid, grh->dgid.raw, 16); | |
e126ba97 EC |
3029 | } |
3030 | ||
d8966fcd | 3031 | err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); |
e126ba97 EC |
3032 | if (err < 0) |
3033 | return err; | |
3034 | path->static_rate = err; | |
3035 | path->port = port; | |
3036 | ||
e126ba97 | 3037 | if (attr_mask & IB_QP_TIMEOUT) |
f879ee8d | 3038 | path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; |
e126ba97 | 3039 | |
75850d0b | 3040 | if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) |
3041 | return modify_raw_packet_eth_prio(dev->mdev, | |
3042 | &qp->raw_packet_qp.sq, | |
1cd6dbd3 | 3043 | sl & 0xf, qp->ibqp.pd); |
75850d0b | 3044 | |
e126ba97 EC |
3045 | return 0; |
3046 | } | |
3047 | ||
3048 | static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { | |
3049 | [MLX5_QP_STATE_INIT] = { | |
3050 | [MLX5_QP_STATE_INIT] = { | |
3051 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | | |
3052 | MLX5_QP_OPTPAR_RAE | | |
3053 | MLX5_QP_OPTPAR_RWE | | |
3054 | MLX5_QP_OPTPAR_PKEY_INDEX | | |
3055 | MLX5_QP_OPTPAR_PRI_PORT, | |
3056 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | | |
3057 | MLX5_QP_OPTPAR_PKEY_INDEX | | |
3058 | MLX5_QP_OPTPAR_PRI_PORT, | |
3059 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
3060 | MLX5_QP_OPTPAR_Q_KEY | | |
3061 | MLX5_QP_OPTPAR_PRI_PORT, | |
8f4426aa JM |
3062 | [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | |
3063 | MLX5_QP_OPTPAR_RAE | | |
3064 | MLX5_QP_OPTPAR_RWE | | |
3065 | MLX5_QP_OPTPAR_PKEY_INDEX | | |
3066 | MLX5_QP_OPTPAR_PRI_PORT, | |
e126ba97 EC |
3067 | }, |
3068 | [MLX5_QP_STATE_RTR] = { | |
3069 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
3070 | MLX5_QP_OPTPAR_RRE | | |
3071 | MLX5_QP_OPTPAR_RAE | | |
3072 | MLX5_QP_OPTPAR_RWE | | |
3073 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
3074 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
3075 | MLX5_QP_OPTPAR_RWE | | |
3076 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
3077 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
3078 | MLX5_QP_OPTPAR_Q_KEY, | |
3079 | [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
3080 | MLX5_QP_OPTPAR_Q_KEY, | |
a4774e90 EC |
3081 | [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | |
3082 | MLX5_QP_OPTPAR_RRE | | |
3083 | MLX5_QP_OPTPAR_RAE | | |
3084 | MLX5_QP_OPTPAR_RWE | | |
3085 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
e126ba97 EC |
3086 | }, |
3087 | }, | |
3088 | [MLX5_QP_STATE_RTR] = { | |
3089 | [MLX5_QP_STATE_RTS] = { | |
3090 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
3091 | MLX5_QP_OPTPAR_RRE | | |
3092 | MLX5_QP_OPTPAR_RAE | | |
3093 | MLX5_QP_OPTPAR_RWE | | |
3094 | MLX5_QP_OPTPAR_PM_STATE | | |
3095 | MLX5_QP_OPTPAR_RNR_TIMEOUT, | |
3096 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
3097 | MLX5_QP_OPTPAR_RWE | | |
3098 | MLX5_QP_OPTPAR_PM_STATE, | |
3099 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, | |
8f4426aa JM |
3100 | [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | |
3101 | MLX5_QP_OPTPAR_RRE | | |
3102 | MLX5_QP_OPTPAR_RAE | | |
3103 | MLX5_QP_OPTPAR_RWE | | |
3104 | MLX5_QP_OPTPAR_PM_STATE | | |
3105 | MLX5_QP_OPTPAR_RNR_TIMEOUT, | |
e126ba97 EC |
3106 | }, |
3107 | }, | |
3108 | [MLX5_QP_STATE_RTS] = { | |
3109 | [MLX5_QP_STATE_RTS] = { | |
3110 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | | |
3111 | MLX5_QP_OPTPAR_RAE | | |
3112 | MLX5_QP_OPTPAR_RWE | | |
3113 | MLX5_QP_OPTPAR_RNR_TIMEOUT | | |
c2a3431e EC |
3114 | MLX5_QP_OPTPAR_PM_STATE | |
3115 | MLX5_QP_OPTPAR_ALT_ADDR_PATH, | |
e126ba97 | 3116 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | |
c2a3431e EC |
3117 | MLX5_QP_OPTPAR_PM_STATE | |
3118 | MLX5_QP_OPTPAR_ALT_ADDR_PATH, | |
e126ba97 EC |
3119 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | |
3120 | MLX5_QP_OPTPAR_SRQN | | |
3121 | MLX5_QP_OPTPAR_CQN_RCV, | |
8f4426aa JM |
3122 | [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE | |
3123 | MLX5_QP_OPTPAR_RAE | | |
3124 | MLX5_QP_OPTPAR_RWE | | |
3125 | MLX5_QP_OPTPAR_RNR_TIMEOUT | | |
3126 | MLX5_QP_OPTPAR_PM_STATE | | |
3127 | MLX5_QP_OPTPAR_ALT_ADDR_PATH, | |
e126ba97 EC |
3128 | }, |
3129 | }, | |
3130 | [MLX5_QP_STATE_SQER] = { | |
3131 | [MLX5_QP_STATE_RTS] = { | |
3132 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, | |
3133 | [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, | |
75959f56 | 3134 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, |
a4774e90 EC |
3135 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | |
3136 | MLX5_QP_OPTPAR_RWE | | |
3137 | MLX5_QP_OPTPAR_RAE | | |
3138 | MLX5_QP_OPTPAR_RRE, | |
8f4426aa JM |
3139 | [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | |
3140 | MLX5_QP_OPTPAR_RWE | | |
3141 | MLX5_QP_OPTPAR_RAE | | |
3142 | MLX5_QP_OPTPAR_RRE, | |
e126ba97 EC |
3143 | }, |
3144 | }, | |
3145 | }; | |
3146 | ||
3147 | static int ib_nr_to_mlx5_nr(int ib_mask) | |
3148 | { | |
3149 | switch (ib_mask) { | |
3150 | case IB_QP_STATE: | |
3151 | return 0; | |
3152 | case IB_QP_CUR_STATE: | |
3153 | return 0; | |
3154 | case IB_QP_EN_SQD_ASYNC_NOTIFY: | |
3155 | return 0; | |
3156 | case IB_QP_ACCESS_FLAGS: | |
3157 | return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | | |
3158 | MLX5_QP_OPTPAR_RAE; | |
3159 | case IB_QP_PKEY_INDEX: | |
3160 | return MLX5_QP_OPTPAR_PKEY_INDEX; | |
3161 | case IB_QP_PORT: | |
3162 | return MLX5_QP_OPTPAR_PRI_PORT; | |
3163 | case IB_QP_QKEY: | |
3164 | return MLX5_QP_OPTPAR_Q_KEY; | |
3165 | case IB_QP_AV: | |
3166 | return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | | |
3167 | MLX5_QP_OPTPAR_PRI_PORT; | |
3168 | case IB_QP_PATH_MTU: | |
3169 | return 0; | |
3170 | case IB_QP_TIMEOUT: | |
3171 | return MLX5_QP_OPTPAR_ACK_TIMEOUT; | |
3172 | case IB_QP_RETRY_CNT: | |
3173 | return MLX5_QP_OPTPAR_RETRY_COUNT; | |
3174 | case IB_QP_RNR_RETRY: | |
3175 | return MLX5_QP_OPTPAR_RNR_RETRY; | |
3176 | case IB_QP_RQ_PSN: | |
3177 | return 0; | |
3178 | case IB_QP_MAX_QP_RD_ATOMIC: | |
3179 | return MLX5_QP_OPTPAR_SRA_MAX; | |
3180 | case IB_QP_ALT_PATH: | |
3181 | return MLX5_QP_OPTPAR_ALT_ADDR_PATH; | |
3182 | case IB_QP_MIN_RNR_TIMER: | |
3183 | return MLX5_QP_OPTPAR_RNR_TIMEOUT; | |
3184 | case IB_QP_SQ_PSN: | |
3185 | return 0; | |
3186 | case IB_QP_MAX_DEST_RD_ATOMIC: | |
3187 | return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | | |
3188 | MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; | |
3189 | case IB_QP_PATH_MIG_STATE: | |
3190 | return MLX5_QP_OPTPAR_PM_STATE; | |
3191 | case IB_QP_CAP: | |
3192 | return 0; | |
3193 | case IB_QP_DEST_QPN: | |
3194 | return 0; | |
3195 | } | |
3196 | return 0; | |
3197 | } | |
3198 | ||
3199 | static int ib_mask_to_mlx5_opt(int ib_mask) | |
3200 | { | |
3201 | int result = 0; | |
3202 | int i; | |
3203 | ||
3204 | for (i = 0; i < 8 * sizeof(int); i++) { | |
3205 | if ((1 << i) & ib_mask) | |
3206 | result |= ib_nr_to_mlx5_nr(1 << i); | |
3207 | } | |
3208 | ||
3209 | return result; | |
3210 | } | |
3211 | ||
34d57585 YH |
3212 | static int modify_raw_packet_qp_rq( |
3213 | struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, | |
3214 | const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) | |
ad5f8e96 | 3215 | { |
3216 | void *in; | |
3217 | void *rqc; | |
3218 | int inlen; | |
3219 | int err; | |
3220 | ||
3221 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 3222 | in = kvzalloc(inlen, GFP_KERNEL); |
ad5f8e96 | 3223 | if (!in) |
3224 | return -ENOMEM; | |
3225 | ||
3226 | MLX5_SET(modify_rq_in, in, rq_state, rq->state); | |
34d57585 | 3227 | MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); |
ad5f8e96 | 3228 | |
3229 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
3230 | MLX5_SET(rqc, rqc, state, new_state); | |
3231 | ||
eb49ab0c AV |
3232 | if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { |
3233 | if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { | |
3234 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
23a6964e | 3235 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); |
eb49ab0c AV |
3236 | MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); |
3237 | } else | |
5a738b5d JG |
3238 | dev_info_once( |
3239 | &dev->ib_dev.dev, | |
3240 | "RAW PACKET QP counters are not supported on current FW\n"); | |
eb49ab0c AV |
3241 | } |
3242 | ||
3243 | err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); | |
ad5f8e96 | 3244 | if (err) |
3245 | goto out; | |
3246 | ||
3247 | rq->state = new_state; | |
3248 | ||
3249 | out: | |
3250 | kvfree(in); | |
3251 | return err; | |
3252 | } | |
3253 | ||
c14003f0 YH |
3254 | static int modify_raw_packet_qp_sq( |
3255 | struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, | |
3256 | const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) | |
ad5f8e96 | 3257 | { |
7d29f349 | 3258 | struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; |
61147f39 BW |
3259 | struct mlx5_rate_limit old_rl = ibqp->rl; |
3260 | struct mlx5_rate_limit new_rl = old_rl; | |
3261 | bool new_rate_added = false; | |
7d29f349 | 3262 | u16 rl_index = 0; |
ad5f8e96 | 3263 | void *in; |
3264 | void *sqc; | |
3265 | int inlen; | |
3266 | int err; | |
3267 | ||
3268 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 3269 | in = kvzalloc(inlen, GFP_KERNEL); |
ad5f8e96 | 3270 | if (!in) |
3271 | return -ENOMEM; | |
3272 | ||
c14003f0 | 3273 | MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); |
ad5f8e96 | 3274 | MLX5_SET(modify_sq_in, in, sq_state, sq->state); |
3275 | ||
3276 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
3277 | MLX5_SET(sqc, sqc, state, new_state); | |
3278 | ||
7d29f349 BW |
3279 | if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { |
3280 | if (new_state != MLX5_SQC_STATE_RDY) | |
3281 | pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", | |
3282 | __func__); | |
3283 | else | |
61147f39 | 3284 | new_rl = raw_qp_param->rl; |
7d29f349 BW |
3285 | } |
3286 | ||
61147f39 BW |
3287 | if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { |
3288 | if (new_rl.rate) { | |
3289 | err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); | |
7d29f349 | 3290 | if (err) { |
61147f39 BW |
3291 | pr_err("Failed configuring rate limit(err %d): \ |
3292 | rate %u, max_burst_sz %u, typical_pkt_sz %u\n", | |
3293 | err, new_rl.rate, new_rl.max_burst_sz, | |
3294 | new_rl.typical_pkt_sz); | |
3295 | ||
7d29f349 BW |
3296 | goto out; |
3297 | } | |
61147f39 | 3298 | new_rate_added = true; |
7d29f349 BW |
3299 | } |
3300 | ||
3301 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); | |
61147f39 | 3302 | /* index 0 means no limit */ |
7d29f349 BW |
3303 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); |
3304 | } | |
3305 | ||
ad5f8e96 | 3306 | err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); |
7d29f349 BW |
3307 | if (err) { |
3308 | /* Remove new rate from table if failed */ | |
61147f39 BW |
3309 | if (new_rate_added) |
3310 | mlx5_rl_remove_rate(dev, &new_rl); | |
ad5f8e96 | 3311 | goto out; |
7d29f349 BW |
3312 | } |
3313 | ||
3314 | /* Only remove the old rate after new rate was set */ | |
c8973df2 RW |
3315 | if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) || |
3316 | (new_state != MLX5_SQC_STATE_RDY)) { | |
61147f39 | 3317 | mlx5_rl_remove_rate(dev, &old_rl); |
c8973df2 RW |
3318 | if (new_state != MLX5_SQC_STATE_RDY) |
3319 | memset(&new_rl, 0, sizeof(new_rl)); | |
3320 | } | |
ad5f8e96 | 3321 | |
61147f39 | 3322 | ibqp->rl = new_rl; |
ad5f8e96 | 3323 | sq->state = new_state; |
3324 | ||
3325 | out: | |
3326 | kvfree(in); | |
3327 | return err; | |
3328 | } | |
3329 | ||
3330 | static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
13eab21f AH |
3331 | const struct mlx5_modify_raw_qp_param *raw_qp_param, |
3332 | u8 tx_affinity) | |
ad5f8e96 | 3333 | { |
3334 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
3335 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
3336 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
7d29f349 BW |
3337 | int modify_rq = !!qp->rq.wqe_cnt; |
3338 | int modify_sq = !!qp->sq.wqe_cnt; | |
ad5f8e96 | 3339 | int rq_state; |
3340 | int sq_state; | |
3341 | int err; | |
3342 | ||
0680efa2 | 3343 | switch (raw_qp_param->operation) { |
ad5f8e96 | 3344 | case MLX5_CMD_OP_RST2INIT_QP: |
3345 | rq_state = MLX5_RQC_STATE_RDY; | |
3346 | sq_state = MLX5_SQC_STATE_RDY; | |
3347 | break; | |
3348 | case MLX5_CMD_OP_2ERR_QP: | |
3349 | rq_state = MLX5_RQC_STATE_ERR; | |
3350 | sq_state = MLX5_SQC_STATE_ERR; | |
3351 | break; | |
3352 | case MLX5_CMD_OP_2RST_QP: | |
3353 | rq_state = MLX5_RQC_STATE_RST; | |
3354 | sq_state = MLX5_SQC_STATE_RST; | |
3355 | break; | |
ad5f8e96 | 3356 | case MLX5_CMD_OP_RTR2RTS_QP: |
3357 | case MLX5_CMD_OP_RTS2RTS_QP: | |
7d29f349 BW |
3358 | if (raw_qp_param->set_mask == |
3359 | MLX5_RAW_QP_RATE_LIMIT) { | |
3360 | modify_rq = 0; | |
3361 | sq_state = sq->state; | |
3362 | } else { | |
3363 | return raw_qp_param->set_mask ? -EINVAL : 0; | |
3364 | } | |
3365 | break; | |
3366 | case MLX5_CMD_OP_INIT2INIT_QP: | |
3367 | case MLX5_CMD_OP_INIT2RTR_QP: | |
eb49ab0c AV |
3368 | if (raw_qp_param->set_mask) |
3369 | return -EINVAL; | |
3370 | else | |
3371 | return 0; | |
ad5f8e96 | 3372 | default: |
3373 | WARN_ON(1); | |
3374 | return -EINVAL; | |
3375 | } | |
3376 | ||
7d29f349 | 3377 | if (modify_rq) { |
34d57585 YH |
3378 | err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, |
3379 | qp->ibqp.pd); | |
ad5f8e96 | 3380 | if (err) |
3381 | return err; | |
3382 | } | |
3383 | ||
7d29f349 | 3384 | if (modify_sq) { |
d5ed8ac3 MB |
3385 | struct mlx5_flow_handle *flow_rule; |
3386 | ||
13eab21f AH |
3387 | if (tx_affinity) { |
3388 | err = modify_raw_packet_tx_affinity(dev->mdev, sq, | |
1cd6dbd3 YH |
3389 | tx_affinity, |
3390 | qp->ibqp.pd); | |
13eab21f AH |
3391 | if (err) |
3392 | return err; | |
3393 | } | |
3394 | ||
d5ed8ac3 MB |
3395 | flow_rule = create_flow_rule_vport_sq(dev, sq, |
3396 | raw_qp_param->port); | |
3397 | if (IS_ERR(flow_rule)) | |
1db86318 | 3398 | return PTR_ERR(flow_rule); |
d5ed8ac3 MB |
3399 | |
3400 | err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, | |
3401 | raw_qp_param, qp->ibqp.pd); | |
3402 | if (err) { | |
3403 | if (flow_rule) | |
3404 | mlx5_del_flow_rules(flow_rule); | |
3405 | return err; | |
3406 | } | |
3407 | ||
3408 | if (flow_rule) { | |
3409 | destroy_flow_rule_vport_sq(sq); | |
3410 | sq->flow_rule = flow_rule; | |
3411 | } | |
3412 | ||
3413 | return err; | |
13eab21f | 3414 | } |
ad5f8e96 | 3415 | |
3416 | return 0; | |
3417 | } | |
3418 | ||
c6a21c38 MD |
3419 | static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, |
3420 | struct mlx5_ib_pd *pd, | |
3421 | struct mlx5_ib_qp_base *qp_base, | |
89944450 | 3422 | u8 port_num, struct ib_udata *udata) |
c6a21c38 | 3423 | { |
89944450 SR |
3424 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
3425 | udata, struct mlx5_ib_ucontext, ibucontext); | |
c6a21c38 MD |
3426 | unsigned int tx_port_affinity; |
3427 | ||
c6a21c38 MD |
3428 | if (ucontext) { |
3429 | tx_port_affinity = (unsigned int)atomic_add_return( | |
3430 | 1, &ucontext->tx_port_affinity) % | |
3431 | MLX5_MAX_PORTS + | |
3432 | 1; | |
3433 | mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", | |
3434 | tx_port_affinity, qp_base->mqp.qpn, ucontext); | |
3435 | } else { | |
3436 | tx_port_affinity = | |
3437 | (unsigned int)atomic_add_return( | |
95579e78 | 3438 | 1, &dev->port[port_num].roce.tx_port_affinity) % |
c6a21c38 MD |
3439 | MLX5_MAX_PORTS + |
3440 | 1; | |
3441 | mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", | |
3442 | tx_port_affinity, qp_base->mqp.qpn); | |
3443 | } | |
3444 | ||
3445 | return tx_port_affinity; | |
3446 | } | |
3447 | ||
d14133dd MZ |
3448 | static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, |
3449 | struct rdma_counter *counter) | |
3450 | { | |
3451 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
3452 | struct mlx5_ib_qp *mqp = to_mqp(qp); | |
3453 | struct mlx5_qp_context context = {}; | |
d14133dd MZ |
3454 | struct mlx5_ib_qp_base *base; |
3455 | u32 set_id; | |
3456 | ||
3e1f000f | 3457 | if (counter) |
d14133dd | 3458 | set_id = counter->id; |
3e1f000f PP |
3459 | else |
3460 | set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); | |
d14133dd MZ |
3461 | |
3462 | base = &mqp->trans_qp.base; | |
3463 | context.qp_counter_set_usr_page &= cpu_to_be32(0xffffff); | |
3464 | context.qp_counter_set_usr_page |= cpu_to_be32(set_id << 24); | |
3465 | return mlx5_core_qp_modify(dev->mdev, | |
3466 | MLX5_CMD_OP_RTS2RTS_QP, | |
3467 | MLX5_QP_OPTPAR_COUNTER_SET_ID, | |
3468 | &context, &base->mqp); | |
3469 | } | |
3470 | ||
e126ba97 EC |
3471 | static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, |
3472 | const struct ib_qp_attr *attr, int attr_mask, | |
89944450 SR |
3473 | enum ib_qp_state cur_state, |
3474 | enum ib_qp_state new_state, | |
3475 | const struct mlx5_ib_modify_qp *ucmd, | |
3476 | struct ib_udata *udata) | |
e126ba97 | 3477 | { |
427c1e7b | 3478 | static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { |
3479 | [MLX5_QP_STATE_RST] = { | |
3480 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3481 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3482 | [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, | |
3483 | }, | |
3484 | [MLX5_QP_STATE_INIT] = { | |
3485 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3486 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3487 | [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, | |
3488 | [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, | |
3489 | }, | |
3490 | [MLX5_QP_STATE_RTR] = { | |
3491 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3492 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3493 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, | |
3494 | }, | |
3495 | [MLX5_QP_STATE_RTS] = { | |
3496 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3497 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3498 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, | |
3499 | }, | |
3500 | [MLX5_QP_STATE_SQD] = { | |
3501 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3502 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3503 | }, | |
3504 | [MLX5_QP_STATE_SQER] = { | |
3505 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3506 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3507 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, | |
3508 | }, | |
3509 | [MLX5_QP_STATE_ERR] = { | |
3510 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3511 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3512 | } | |
3513 | }; | |
3514 | ||
e126ba97 EC |
3515 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); |
3516 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
19098df2 | 3517 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; |
e126ba97 EC |
3518 | struct mlx5_ib_cq *send_cq, *recv_cq; |
3519 | struct mlx5_qp_context *context; | |
e126ba97 EC |
3520 | struct mlx5_ib_pd *pd; |
3521 | enum mlx5_qp_state mlx5_cur, mlx5_new; | |
3522 | enum mlx5_qp_optpar optpar; | |
d14133dd | 3523 | u32 set_id = 0; |
e126ba97 EC |
3524 | int mlx5_st; |
3525 | int err; | |
427c1e7b | 3526 | u16 op; |
13eab21f | 3527 | u8 tx_affinity = 0; |
e126ba97 | 3528 | |
55de9a77 LR |
3529 | mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? |
3530 | qp->qp_sub_type : ibqp->qp_type); | |
3531 | if (mlx5_st < 0) | |
3532 | return -EINVAL; | |
3533 | ||
1a412fb1 SM |
3534 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
3535 | if (!context) | |
e126ba97 EC |
3536 | return -ENOMEM; |
3537 | ||
c6a21c38 | 3538 | pd = get_pd(qp); |
55de9a77 | 3539 | context->flags = cpu_to_be32(mlx5_st << 16); |
e126ba97 EC |
3540 | |
3541 | if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { | |
3542 | context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); | |
3543 | } else { | |
3544 | switch (attr->path_mig_state) { | |
3545 | case IB_MIG_MIGRATED: | |
3546 | context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); | |
3547 | break; | |
3548 | case IB_MIG_REARM: | |
3549 | context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); | |
3550 | break; | |
3551 | case IB_MIG_ARMED: | |
3552 | context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); | |
3553 | break; | |
3554 | } | |
3555 | } | |
3556 | ||
13eab21f AH |
3557 | if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { |
3558 | if ((ibqp->qp_type == IB_QPT_RC) || | |
3559 | (ibqp->qp_type == IB_QPT_UD && | |
3560 | !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || | |
3561 | (ibqp->qp_type == IB_QPT_UC) || | |
3562 | (ibqp->qp_type == IB_QPT_RAW_PACKET) || | |
3563 | (ibqp->qp_type == IB_QPT_XRC_INI) || | |
3564 | (ibqp->qp_type == IB_QPT_XRC_TGT)) { | |
7c34ec19 | 3565 | if (dev->lag_active) { |
95579e78 | 3566 | u8 p = mlx5_core_native_port_num(dev->mdev) - 1; |
89944450 SR |
3567 | tx_affinity = get_tx_affinity(dev, pd, base, p, |
3568 | udata); | |
13eab21f AH |
3569 | context->flags |= cpu_to_be32(tx_affinity << 24); |
3570 | } | |
3571 | } | |
3572 | } | |
3573 | ||
d16e91da | 3574 | if (is_sqp(ibqp->qp_type)) { |
e126ba97 | 3575 | context->mtu_msgmax = (IB_MTU_256 << 5) | 8; |
c2e53b2c YH |
3576 | } else if ((ibqp->qp_type == IB_QPT_UD && |
3577 | !(qp->flags & MLX5_IB_QP_UNDERLAY)) || | |
e126ba97 EC |
3578 | ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { |
3579 | context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; | |
3580 | } else if (attr_mask & IB_QP_PATH_MTU) { | |
3581 | if (attr->path_mtu < IB_MTU_256 || | |
3582 | attr->path_mtu > IB_MTU_4096) { | |
3583 | mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); | |
3584 | err = -EINVAL; | |
3585 | goto out; | |
3586 | } | |
938fe83c SM |
3587 | context->mtu_msgmax = (attr->path_mtu << 5) | |
3588 | (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); | |
e126ba97 EC |
3589 | } |
3590 | ||
3591 | if (attr_mask & IB_QP_DEST_QPN) | |
3592 | context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); | |
3593 | ||
3594 | if (attr_mask & IB_QP_PKEY_INDEX) | |
d3ae2bde | 3595 | context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); |
e126ba97 EC |
3596 | |
3597 | /* todo implement counter_index functionality */ | |
3598 | ||
3599 | if (is_sqp(ibqp->qp_type)) | |
3600 | context->pri_path.port = qp->port; | |
3601 | ||
3602 | if (attr_mask & IB_QP_PORT) | |
3603 | context->pri_path.port = attr->port_num; | |
3604 | ||
3605 | if (attr_mask & IB_QP_AV) { | |
75850d0b | 3606 | err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, |
e126ba97 | 3607 | attr_mask & IB_QP_PORT ? attr->port_num : qp->port, |
f879ee8d | 3608 | attr_mask, 0, attr, false); |
e126ba97 EC |
3609 | if (err) |
3610 | goto out; | |
3611 | } | |
3612 | ||
3613 | if (attr_mask & IB_QP_TIMEOUT) | |
3614 | context->pri_path.ackto_lt |= attr->timeout << 3; | |
3615 | ||
3616 | if (attr_mask & IB_QP_ALT_PATH) { | |
75850d0b | 3617 | err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, |
3618 | &context->alt_path, | |
f879ee8d AS |
3619 | attr->alt_port_num, |
3620 | attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, | |
3621 | 0, attr, true); | |
e126ba97 EC |
3622 | if (err) |
3623 | goto out; | |
3624 | } | |
3625 | ||
89ea94a7 MG |
3626 | get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, |
3627 | &send_cq, &recv_cq); | |
e126ba97 EC |
3628 | |
3629 | context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); | |
3630 | context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; | |
3631 | context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; | |
3632 | context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); | |
3633 | ||
3634 | if (attr_mask & IB_QP_RNR_RETRY) | |
3635 | context->params1 |= cpu_to_be32(attr->rnr_retry << 13); | |
3636 | ||
3637 | if (attr_mask & IB_QP_RETRY_CNT) | |
3638 | context->params1 |= cpu_to_be32(attr->retry_cnt << 16); | |
3639 | ||
3640 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { | |
3641 | if (attr->max_rd_atomic) | |
3642 | context->params1 |= | |
3643 | cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); | |
3644 | } | |
3645 | ||
3646 | if (attr_mask & IB_QP_SQ_PSN) | |
3647 | context->next_send_psn = cpu_to_be32(attr->sq_psn); | |
3648 | ||
3649 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { | |
3650 | if (attr->max_dest_rd_atomic) | |
3651 | context->params2 |= | |
3652 | cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); | |
3653 | } | |
3654 | ||
a60109dc | 3655 | if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { |
bf3b4f06 | 3656 | __be32 access_flags; |
a60109dc YC |
3657 | |
3658 | err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); | |
3659 | if (err) | |
3660 | goto out; | |
3661 | ||
3662 | context->params2 |= access_flags; | |
3663 | } | |
e126ba97 EC |
3664 | |
3665 | if (attr_mask & IB_QP_MIN_RNR_TIMER) | |
3666 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); | |
3667 | ||
3668 | if (attr_mask & IB_QP_RQ_PSN) | |
3669 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); | |
3670 | ||
3671 | if (attr_mask & IB_QP_QKEY) | |
3672 | context->qkey = cpu_to_be32(attr->qkey); | |
3673 | ||
3674 | if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) | |
3675 | context->db_rec_addr = cpu_to_be64(qp->db.dma); | |
3676 | ||
0837e86a MB |
3677 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { |
3678 | u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : | |
3679 | qp->port) - 1; | |
c2e53b2c YH |
3680 | |
3681 | /* Underlay port should be used - index 0 function per port */ | |
3682 | if (qp->flags & MLX5_IB_QP_UNDERLAY) | |
3683 | port_num = 0; | |
3684 | ||
d14133dd MZ |
3685 | if (ibqp->counter) |
3686 | set_id = ibqp->counter->id; | |
3687 | else | |
3e1f000f | 3688 | set_id = mlx5_ib_get_counters_id(dev, port_num); |
0837e86a | 3689 | context->qp_counter_set_usr_page |= |
d14133dd | 3690 | cpu_to_be32(set_id << 24); |
0837e86a MB |
3691 | } |
3692 | ||
e126ba97 EC |
3693 | if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) |
3694 | context->sq_crq_size |= cpu_to_be16(1 << 4); | |
3695 | ||
b11a4f9c HE |
3696 | if (qp->flags & MLX5_IB_QP_SQPN_QP1) |
3697 | context->deth_sqpn = cpu_to_be32(1); | |
e126ba97 EC |
3698 | |
3699 | mlx5_cur = to_mlx5_state(cur_state); | |
3700 | mlx5_new = to_mlx5_state(new_state); | |
e126ba97 | 3701 | |
427c1e7b | 3702 | if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || |
5d414b17 DC |
3703 | !optab[mlx5_cur][mlx5_new]) { |
3704 | err = -EINVAL; | |
427c1e7b | 3705 | goto out; |
5d414b17 | 3706 | } |
427c1e7b | 3707 | |
3708 | op = optab[mlx5_cur][mlx5_new]; | |
e126ba97 EC |
3709 | optpar = ib_mask_to_mlx5_opt(attr_mask); |
3710 | optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; | |
ad5f8e96 | 3711 | |
c2e53b2c YH |
3712 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
3713 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0680efa2 AV |
3714 | struct mlx5_modify_raw_qp_param raw_qp_param = {}; |
3715 | ||
3716 | raw_qp_param.operation = op; | |
eb49ab0c | 3717 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { |
d14133dd | 3718 | raw_qp_param.rq_q_ctr_id = set_id; |
eb49ab0c AV |
3719 | raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; |
3720 | } | |
7d29f349 | 3721 | |
d5ed8ac3 MB |
3722 | if (attr_mask & IB_QP_PORT) |
3723 | raw_qp_param.port = attr->port_num; | |
3724 | ||
7d29f349 | 3725 | if (attr_mask & IB_QP_RATE_LIMIT) { |
61147f39 BW |
3726 | raw_qp_param.rl.rate = attr->rate_limit; |
3727 | ||
3728 | if (ucmd->burst_info.max_burst_sz) { | |
3729 | if (attr->rate_limit && | |
3730 | MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { | |
3731 | raw_qp_param.rl.max_burst_sz = | |
3732 | ucmd->burst_info.max_burst_sz; | |
3733 | } else { | |
3734 | err = -EINVAL; | |
3735 | goto out; | |
3736 | } | |
3737 | } | |
3738 | ||
3739 | if (ucmd->burst_info.typical_pkt_sz) { | |
3740 | if (attr->rate_limit && | |
3741 | MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { | |
3742 | raw_qp_param.rl.typical_pkt_sz = | |
3743 | ucmd->burst_info.typical_pkt_sz; | |
3744 | } else { | |
3745 | err = -EINVAL; | |
3746 | goto out; | |
3747 | } | |
3748 | } | |
3749 | ||
7d29f349 BW |
3750 | raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; |
3751 | } | |
3752 | ||
13eab21f | 3753 | err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); |
0680efa2 | 3754 | } else { |
1a412fb1 | 3755 | err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, |
ad5f8e96 | 3756 | &base->mqp); |
0680efa2 AV |
3757 | } |
3758 | ||
e126ba97 EC |
3759 | if (err) |
3760 | goto out; | |
3761 | ||
3762 | qp->state = new_state; | |
3763 | ||
3764 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
19098df2 | 3765 | qp->trans_qp.atomic_rd_en = attr->qp_access_flags; |
e126ba97 | 3766 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) |
19098df2 | 3767 | qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; |
e126ba97 EC |
3768 | if (attr_mask & IB_QP_PORT) |
3769 | qp->port = attr->port_num; | |
3770 | if (attr_mask & IB_QP_ALT_PATH) | |
19098df2 | 3771 | qp->trans_qp.alt_port = attr->alt_port_num; |
e126ba97 EC |
3772 | |
3773 | /* | |
3774 | * If we moved a kernel QP to RESET, clean up all old CQ | |
3775 | * entries and reinitialize the QP. | |
3776 | */ | |
75a45982 LR |
3777 | if (new_state == IB_QPS_RESET && |
3778 | !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { | |
19098df2 | 3779 | mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, |
e126ba97 EC |
3780 | ibqp->srq ? to_msrq(ibqp->srq) : NULL); |
3781 | if (send_cq != recv_cq) | |
19098df2 | 3782 | mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); |
e126ba97 EC |
3783 | |
3784 | qp->rq.head = 0; | |
3785 | qp->rq.tail = 0; | |
3786 | qp->sq.head = 0; | |
3787 | qp->sq.tail = 0; | |
3788 | qp->sq.cur_post = 0; | |
34f4c955 GL |
3789 | if (qp->sq.wqe_cnt) |
3790 | qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); | |
950bf4f1 | 3791 | qp->sq.last_poll = 0; |
e126ba97 EC |
3792 | qp->db.db[MLX5_RCV_DBR] = 0; |
3793 | qp->db.db[MLX5_SND_DBR] = 0; | |
3794 | } | |
3795 | ||
d14133dd MZ |
3796 | if ((new_state == IB_QPS_RTS) && qp->counter_pending) { |
3797 | err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter); | |
3798 | if (!err) | |
3799 | qp->counter_pending = 0; | |
3800 | } | |
3801 | ||
e126ba97 | 3802 | out: |
1a412fb1 | 3803 | kfree(context); |
e126ba97 EC |
3804 | return err; |
3805 | } | |
3806 | ||
c32a4f29 MS |
3807 | static inline bool is_valid_mask(int mask, int req, int opt) |
3808 | { | |
3809 | if ((mask & req) != req) | |
3810 | return false; | |
3811 | ||
3812 | if (mask & ~(req | opt)) | |
3813 | return false; | |
3814 | ||
3815 | return true; | |
3816 | } | |
3817 | ||
3818 | /* check valid transition for driver QP types | |
3819 | * for now the only QP type that this function supports is DCI | |
3820 | */ | |
3821 | static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, | |
3822 | enum ib_qp_attr_mask attr_mask) | |
3823 | { | |
3824 | int req = IB_QP_STATE; | |
3825 | int opt = 0; | |
3826 | ||
99ed748e MS |
3827 | if (new_state == IB_QPS_RESET) { |
3828 | return is_valid_mask(attr_mask, req, opt); | |
3829 | } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { | |
c32a4f29 MS |
3830 | req |= IB_QP_PKEY_INDEX | IB_QP_PORT; |
3831 | return is_valid_mask(attr_mask, req, opt); | |
3832 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { | |
3833 | opt = IB_QP_PKEY_INDEX | IB_QP_PORT; | |
3834 | return is_valid_mask(attr_mask, req, opt); | |
3835 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { | |
3836 | req |= IB_QP_PATH_MTU; | |
5ec0304c | 3837 | opt = IB_QP_PKEY_INDEX | IB_QP_AV; |
c32a4f29 MS |
3838 | return is_valid_mask(attr_mask, req, opt); |
3839 | } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { | |
3840 | req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | | |
3841 | IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; | |
3842 | opt = IB_QP_MIN_RNR_TIMER; | |
3843 | return is_valid_mask(attr_mask, req, opt); | |
3844 | } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { | |
3845 | opt = IB_QP_MIN_RNR_TIMER; | |
3846 | return is_valid_mask(attr_mask, req, opt); | |
3847 | } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { | |
3848 | return is_valid_mask(attr_mask, req, opt); | |
3849 | } | |
3850 | return false; | |
3851 | } | |
3852 | ||
776a3906 MS |
3853 | /* mlx5_ib_modify_dct: modify a DCT QP |
3854 | * valid transitions are: | |
3855 | * RESET to INIT: must set access_flags, pkey_index and port | |
3856 | * INIT to RTR : must set min_rnr_timer, tclass, flow_label, | |
3857 | * mtu, gid_index and hop_limit | |
3858 | * Other transitions and attributes are illegal | |
3859 | */ | |
3860 | static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
3861 | int attr_mask, struct ib_udata *udata) | |
3862 | { | |
3863 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
3864 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
3865 | enum ib_qp_state cur_state, new_state; | |
3866 | int err = 0; | |
3867 | int required = IB_QP_STATE; | |
3868 | void *dctc; | |
3869 | ||
3870 | if (!(attr_mask & IB_QP_STATE)) | |
3871 | return -EINVAL; | |
3872 | ||
3873 | cur_state = qp->state; | |
3874 | new_state = attr->qp_state; | |
3875 | ||
3876 | dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); | |
3877 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { | |
3e1f000f PP |
3878 | u16 set_id; |
3879 | ||
776a3906 MS |
3880 | required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; |
3881 | if (!is_valid_mask(attr_mask, required, 0)) | |
3882 | return -EINVAL; | |
3883 | ||
3884 | if (attr->port_num == 0 || | |
3885 | attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { | |
3886 | mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", | |
3887 | attr->port_num, dev->num_ports); | |
3888 | return -EINVAL; | |
3889 | } | |
3890 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) | |
3891 | MLX5_SET(dctc, dctc, rre, 1); | |
3892 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) | |
3893 | MLX5_SET(dctc, dctc, rwe, 1); | |
3894 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { | |
a60109dc YC |
3895 | int atomic_mode; |
3896 | ||
3897 | atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); | |
3898 | if (atomic_mode < 0) | |
776a3906 | 3899 | return -EOPNOTSUPP; |
a60109dc YC |
3900 | |
3901 | MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); | |
776a3906 | 3902 | MLX5_SET(dctc, dctc, rae, 1); |
776a3906 MS |
3903 | } |
3904 | MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); | |
3905 | MLX5_SET(dctc, dctc, port, attr->port_num); | |
3e1f000f PP |
3906 | |
3907 | set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1); | |
3908 | MLX5_SET(dctc, dctc, counter_set_id, set_id); | |
776a3906 MS |
3909 | |
3910 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { | |
3911 | struct mlx5_ib_modify_qp_resp resp = {}; | |
c5ae1954 | 3912 | u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0}; |
776a3906 MS |
3913 | u32 min_resp_len = offsetof(typeof(resp), dctn) + |
3914 | sizeof(resp.dctn); | |
3915 | ||
3916 | if (udata->outlen < min_resp_len) | |
3917 | return -EINVAL; | |
3918 | resp.response_length = min_resp_len; | |
3919 | ||
3920 | required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; | |
3921 | if (!is_valid_mask(attr_mask, required, 0)) | |
3922 | return -EINVAL; | |
3923 | MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); | |
3924 | MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); | |
3925 | MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); | |
3926 | MLX5_SET(dctc, dctc, mtu, attr->path_mtu); | |
3927 | MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); | |
3928 | MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); | |
3929 | ||
3930 | err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, | |
c5ae1954 YH |
3931 | MLX5_ST_SZ_BYTES(create_dct_in), out, |
3932 | sizeof(out)); | |
776a3906 MS |
3933 | if (err) |
3934 | return err; | |
3935 | resp.dctn = qp->dct.mdct.mqp.qpn; | |
3936 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
3937 | if (err) { | |
3938 | mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); | |
3939 | return err; | |
3940 | } | |
3941 | } else { | |
3942 | mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); | |
3943 | return -EINVAL; | |
3944 | } | |
3945 | if (err) | |
3946 | qp->state = IB_QPS_ERR; | |
3947 | else | |
3948 | qp->state = new_state; | |
3949 | return err; | |
3950 | } | |
3951 | ||
e126ba97 EC |
3952 | int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
3953 | int attr_mask, struct ib_udata *udata) | |
3954 | { | |
3955 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
3956 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
61147f39 | 3957 | struct mlx5_ib_modify_qp ucmd = {}; |
d16e91da | 3958 | enum ib_qp_type qp_type; |
e126ba97 | 3959 | enum ib_qp_state cur_state, new_state; |
61147f39 | 3960 | size_t required_cmd_sz; |
e126ba97 EC |
3961 | int err = -EINVAL; |
3962 | int port; | |
3963 | ||
28d61370 YH |
3964 | if (ibqp->rwq_ind_tbl) |
3965 | return -ENOSYS; | |
3966 | ||
61147f39 BW |
3967 | if (udata && udata->inlen) { |
3968 | required_cmd_sz = offsetof(typeof(ucmd), reserved) + | |
3969 | sizeof(ucmd.reserved); | |
3970 | if (udata->inlen < required_cmd_sz) | |
3971 | return -EINVAL; | |
3972 | ||
3973 | if (udata->inlen > sizeof(ucmd) && | |
3974 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
3975 | udata->inlen - sizeof(ucmd))) | |
3976 | return -EOPNOTSUPP; | |
3977 | ||
3978 | if (ib_copy_from_udata(&ucmd, udata, | |
3979 | min(udata->inlen, sizeof(ucmd)))) | |
3980 | return -EFAULT; | |
3981 | ||
3982 | if (ucmd.comp_mask || | |
3983 | memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || | |
3984 | memchr_inv(&ucmd.burst_info.reserved, 0, | |
3985 | sizeof(ucmd.burst_info.reserved))) | |
3986 | return -EOPNOTSUPP; | |
3987 | } | |
3988 | ||
d16e91da HE |
3989 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
3990 | return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); | |
3991 | ||
c32a4f29 MS |
3992 | if (ibqp->qp_type == IB_QPT_DRIVER) |
3993 | qp_type = qp->qp_sub_type; | |
3994 | else | |
3995 | qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? | |
3996 | IB_QPT_GSI : ibqp->qp_type; | |
3997 | ||
776a3906 MS |
3998 | if (qp_type == MLX5_IB_QPT_DCT) |
3999 | return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); | |
d16e91da | 4000 | |
e126ba97 EC |
4001 | mutex_lock(&qp->mutex); |
4002 | ||
4003 | cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; | |
4004 | new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; | |
4005 | ||
2811ba51 AS |
4006 | if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { |
4007 | port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; | |
2811ba51 AS |
4008 | } |
4009 | ||
c2e53b2c YH |
4010 | if (qp->flags & MLX5_IB_QP_UNDERLAY) { |
4011 | if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { | |
4012 | mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", | |
4013 | attr_mask); | |
4014 | goto out; | |
4015 | } | |
4016 | } else if (qp_type != MLX5_IB_QPT_REG_UMR && | |
c32a4f29 | 4017 | qp_type != MLX5_IB_QPT_DCI && |
d31131bb KH |
4018 | !ib_modify_qp_is_ok(cur_state, new_state, qp_type, |
4019 | attr_mask)) { | |
158abf86 HE |
4020 | mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", |
4021 | cur_state, new_state, ibqp->qp_type, attr_mask); | |
e126ba97 | 4022 | goto out; |
c32a4f29 MS |
4023 | } else if (qp_type == MLX5_IB_QPT_DCI && |
4024 | !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { | |
4025 | mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", | |
4026 | cur_state, new_state, qp_type, attr_mask); | |
4027 | goto out; | |
158abf86 | 4028 | } |
e126ba97 EC |
4029 | |
4030 | if ((attr_mask & IB_QP_PORT) && | |
938fe83c | 4031 | (attr->port_num == 0 || |
508562d6 | 4032 | attr->port_num > dev->num_ports)) { |
158abf86 HE |
4033 | mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", |
4034 | attr->port_num, dev->num_ports); | |
e126ba97 | 4035 | goto out; |
158abf86 | 4036 | } |
e126ba97 EC |
4037 | |
4038 | if (attr_mask & IB_QP_PKEY_INDEX) { | |
4039 | port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; | |
938fe83c | 4040 | if (attr->pkey_index >= |
158abf86 HE |
4041 | dev->mdev->port_caps[port - 1].pkey_table_len) { |
4042 | mlx5_ib_dbg(dev, "invalid pkey index %d\n", | |
4043 | attr->pkey_index); | |
e126ba97 | 4044 | goto out; |
158abf86 | 4045 | } |
e126ba97 EC |
4046 | } |
4047 | ||
4048 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && | |
938fe83c | 4049 | attr->max_rd_atomic > |
158abf86 HE |
4050 | (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { |
4051 | mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", | |
4052 | attr->max_rd_atomic); | |
e126ba97 | 4053 | goto out; |
158abf86 | 4054 | } |
e126ba97 EC |
4055 | |
4056 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && | |
938fe83c | 4057 | attr->max_dest_rd_atomic > |
158abf86 HE |
4058 | (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { |
4059 | mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", | |
4060 | attr->max_dest_rd_atomic); | |
e126ba97 | 4061 | goto out; |
158abf86 | 4062 | } |
e126ba97 EC |
4063 | |
4064 | if (cur_state == new_state && cur_state == IB_QPS_RESET) { | |
4065 | err = 0; | |
4066 | goto out; | |
4067 | } | |
4068 | ||
61147f39 | 4069 | err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, |
89944450 | 4070 | new_state, &ucmd, udata); |
e126ba97 EC |
4071 | |
4072 | out: | |
4073 | mutex_unlock(&qp->mutex); | |
4074 | return err; | |
4075 | } | |
4076 | ||
34f4c955 GL |
4077 | static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, |
4078 | u32 wqe_sz, void **cur_edge) | |
4079 | { | |
4080 | u32 idx; | |
4081 | ||
4082 | idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); | |
4083 | *cur_edge = get_sq_edge(sq, idx); | |
4084 | ||
4085 | *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); | |
4086 | } | |
4087 | ||
4088 | /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the | |
4089 | * next nearby edge and get new address translation for current WQE position. | |
4090 | * @sq - SQ buffer. | |
4091 | * @seg: Current WQE position (16B aligned). | |
4092 | * @wqe_sz: Total current WQE size [16B]. | |
4093 | * @cur_edge: Updated current edge. | |
4094 | */ | |
4095 | static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, | |
4096 | u32 wqe_sz, void **cur_edge) | |
4097 | { | |
4098 | if (likely(*seg != *cur_edge)) | |
4099 | return; | |
4100 | ||
4101 | _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); | |
4102 | } | |
4103 | ||
4104 | /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's | |
4105 | * pointers. At the end @seg is aligned to 16B regardless the copied size. | |
4106 | * @sq - SQ buffer. | |
4107 | * @cur_edge: Updated current edge. | |
4108 | * @seg: Current WQE position (16B aligned). | |
4109 | * @wqe_sz: Total current WQE size [16B]. | |
4110 | * @src: Pointer to copy from. | |
4111 | * @n: Number of bytes to copy. | |
4112 | */ | |
4113 | static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, | |
4114 | void **seg, u32 *wqe_sz, const void *src, | |
4115 | size_t n) | |
4116 | { | |
4117 | while (likely(n)) { | |
4118 | size_t leftlen = *cur_edge - *seg; | |
4119 | size_t copysz = min_t(size_t, leftlen, n); | |
4120 | size_t stride; | |
4121 | ||
4122 | memcpy(*seg, src, copysz); | |
4123 | ||
4124 | n -= copysz; | |
4125 | src += copysz; | |
4126 | stride = !n ? ALIGN(copysz, 16) : copysz; | |
4127 | *seg += stride; | |
4128 | *wqe_sz += stride >> 4; | |
4129 | handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); | |
4130 | } | |
4131 | } | |
4132 | ||
e126ba97 EC |
4133 | static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) |
4134 | { | |
4135 | struct mlx5_ib_cq *cq; | |
4136 | unsigned cur; | |
4137 | ||
4138 | cur = wq->head - wq->tail; | |
4139 | if (likely(cur + nreq < wq->max_post)) | |
4140 | return 0; | |
4141 | ||
4142 | cq = to_mcq(ib_cq); | |
4143 | spin_lock(&cq->lock); | |
4144 | cur = wq->head - wq->tail; | |
4145 | spin_unlock(&cq->lock); | |
4146 | ||
4147 | return cur + nreq >= wq->max_post; | |
4148 | } | |
4149 | ||
4150 | static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, | |
4151 | u64 remote_addr, u32 rkey) | |
4152 | { | |
4153 | rseg->raddr = cpu_to_be64(remote_addr); | |
4154 | rseg->rkey = cpu_to_be32(rkey); | |
4155 | rseg->reserved = 0; | |
4156 | } | |
4157 | ||
34f4c955 GL |
4158 | static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, |
4159 | void **seg, int *size, void **cur_edge) | |
f0313965 | 4160 | { |
34f4c955 | 4161 | struct mlx5_wqe_eth_seg *eseg = *seg; |
f0313965 ES |
4162 | |
4163 | memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); | |
4164 | ||
4165 | if (wr->send_flags & IB_SEND_IP_CSUM) | |
4166 | eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | | |
4167 | MLX5_ETH_WQE_L4_CSUM; | |
4168 | ||
f0313965 ES |
4169 | if (wr->opcode == IB_WR_LSO) { |
4170 | struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); | |
34f4c955 | 4171 | size_t left, copysz; |
f0313965 | 4172 | void *pdata = ud_wr->header; |
34f4c955 | 4173 | size_t stride; |
f0313965 ES |
4174 | |
4175 | left = ud_wr->hlen; | |
4176 | eseg->mss = cpu_to_be16(ud_wr->mss); | |
2b31f7ae | 4177 | eseg->inline_hdr.sz = cpu_to_be16(left); |
f0313965 | 4178 | |
34f4c955 GL |
4179 | /* memcpy_send_wqe should get a 16B align address. Hence, we |
4180 | * first copy up to the current edge and then, if needed, | |
4181 | * fall-through to memcpy_send_wqe. | |
f0313965 | 4182 | */ |
34f4c955 GL |
4183 | copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, |
4184 | left); | |
4185 | memcpy(eseg->inline_hdr.start, pdata, copysz); | |
4186 | stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - | |
4187 | sizeof(eseg->inline_hdr.start) + copysz, 16); | |
4188 | *size += stride / 16; | |
4189 | *seg += stride; | |
4190 | ||
4191 | if (copysz < left) { | |
4192 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); | |
f0313965 ES |
4193 | left -= copysz; |
4194 | pdata += copysz; | |
34f4c955 GL |
4195 | memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, |
4196 | left); | |
f0313965 | 4197 | } |
34f4c955 GL |
4198 | |
4199 | return; | |
f0313965 ES |
4200 | } |
4201 | ||
34f4c955 GL |
4202 | *seg += sizeof(struct mlx5_wqe_eth_seg); |
4203 | *size += sizeof(struct mlx5_wqe_eth_seg) / 16; | |
f0313965 ES |
4204 | } |
4205 | ||
e126ba97 | 4206 | static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, |
f696bf6d | 4207 | const struct ib_send_wr *wr) |
e126ba97 | 4208 | { |
e622f2f4 CH |
4209 | memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); |
4210 | dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); | |
4211 | dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); | |
e126ba97 EC |
4212 | } |
4213 | ||
4214 | static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) | |
4215 | { | |
4216 | dseg->byte_count = cpu_to_be32(sg->length); | |
4217 | dseg->lkey = cpu_to_be32(sg->lkey); | |
4218 | dseg->addr = cpu_to_be64(sg->addr); | |
4219 | } | |
4220 | ||
31616255 | 4221 | static u64 get_xlt_octo(u64 bytes) |
e126ba97 | 4222 | { |
31616255 AK |
4223 | return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / |
4224 | MLX5_IB_UMR_OCTOWORD; | |
e126ba97 EC |
4225 | } |
4226 | ||
841b07f9 | 4227 | static __be64 frwr_mkey_mask(bool atomic) |
e126ba97 EC |
4228 | { |
4229 | u64 result; | |
4230 | ||
4231 | result = MLX5_MKEY_MASK_LEN | | |
4232 | MLX5_MKEY_MASK_PAGE_SIZE | | |
4233 | MLX5_MKEY_MASK_START_ADDR | | |
4234 | MLX5_MKEY_MASK_EN_RINVAL | | |
4235 | MLX5_MKEY_MASK_KEY | | |
4236 | MLX5_MKEY_MASK_LR | | |
4237 | MLX5_MKEY_MASK_LW | | |
4238 | MLX5_MKEY_MASK_RR | | |
4239 | MLX5_MKEY_MASK_RW | | |
e126ba97 EC |
4240 | MLX5_MKEY_MASK_SMALL_FENCE | |
4241 | MLX5_MKEY_MASK_FREE; | |
4242 | ||
841b07f9 MS |
4243 | if (atomic) |
4244 | result |= MLX5_MKEY_MASK_A; | |
4245 | ||
e126ba97 EC |
4246 | return cpu_to_be64(result); |
4247 | } | |
4248 | ||
e6631814 SG |
4249 | static __be64 sig_mkey_mask(void) |
4250 | { | |
4251 | u64 result; | |
4252 | ||
4253 | result = MLX5_MKEY_MASK_LEN | | |
4254 | MLX5_MKEY_MASK_PAGE_SIZE | | |
4255 | MLX5_MKEY_MASK_START_ADDR | | |
d5436ba0 | 4256 | MLX5_MKEY_MASK_EN_SIGERR | |
e6631814 SG |
4257 | MLX5_MKEY_MASK_EN_RINVAL | |
4258 | MLX5_MKEY_MASK_KEY | | |
4259 | MLX5_MKEY_MASK_LR | | |
4260 | MLX5_MKEY_MASK_LW | | |
4261 | MLX5_MKEY_MASK_RR | | |
4262 | MLX5_MKEY_MASK_RW | | |
4263 | MLX5_MKEY_MASK_SMALL_FENCE | | |
4264 | MLX5_MKEY_MASK_FREE | | |
4265 | MLX5_MKEY_MASK_BSF_EN; | |
4266 | ||
4267 | return cpu_to_be64(result); | |
4268 | } | |
4269 | ||
8a187ee5 | 4270 | static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, |
841b07f9 | 4271 | struct mlx5_ib_mr *mr, u8 flags, bool atomic) |
8a187ee5 | 4272 | { |
38ca87c6 | 4273 | int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size; |
8a187ee5 SG |
4274 | |
4275 | memset(umr, 0, sizeof(*umr)); | |
b005d316 | 4276 | |
9ac7c4bc | 4277 | umr->flags = flags; |
31616255 | 4278 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); |
841b07f9 | 4279 | umr->mkey_mask = frwr_mkey_mask(atomic); |
8a187ee5 SG |
4280 | } |
4281 | ||
dd01e66a | 4282 | static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) |
e126ba97 EC |
4283 | { |
4284 | memset(umr, 0, sizeof(*umr)); | |
dd01e66a | 4285 | umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); |
2d221588 | 4286 | umr->flags = MLX5_UMR_INLINE; |
e126ba97 EC |
4287 | } |
4288 | ||
31616255 | 4289 | static __be64 get_umr_enable_mr_mask(void) |
968e78dd HE |
4290 | { |
4291 | u64 result; | |
4292 | ||
31616255 | 4293 | result = MLX5_MKEY_MASK_KEY | |
968e78dd HE |
4294 | MLX5_MKEY_MASK_FREE; |
4295 | ||
968e78dd HE |
4296 | return cpu_to_be64(result); |
4297 | } | |
4298 | ||
31616255 | 4299 | static __be64 get_umr_disable_mr_mask(void) |
968e78dd HE |
4300 | { |
4301 | u64 result; | |
4302 | ||
4303 | result = MLX5_MKEY_MASK_FREE; | |
4304 | ||
4305 | return cpu_to_be64(result); | |
4306 | } | |
4307 | ||
56e11d62 NO |
4308 | static __be64 get_umr_update_translation_mask(void) |
4309 | { | |
4310 | u64 result; | |
4311 | ||
4312 | result = MLX5_MKEY_MASK_LEN | | |
4313 | MLX5_MKEY_MASK_PAGE_SIZE | | |
31616255 | 4314 | MLX5_MKEY_MASK_START_ADDR; |
56e11d62 NO |
4315 | |
4316 | return cpu_to_be64(result); | |
4317 | } | |
4318 | ||
31616255 | 4319 | static __be64 get_umr_update_access_mask(int atomic) |
56e11d62 NO |
4320 | { |
4321 | u64 result; | |
4322 | ||
31616255 AK |
4323 | result = MLX5_MKEY_MASK_LR | |
4324 | MLX5_MKEY_MASK_LW | | |
56e11d62 | 4325 | MLX5_MKEY_MASK_RR | |
31616255 AK |
4326 | MLX5_MKEY_MASK_RW; |
4327 | ||
4328 | if (atomic) | |
4329 | result |= MLX5_MKEY_MASK_A; | |
56e11d62 NO |
4330 | |
4331 | return cpu_to_be64(result); | |
4332 | } | |
4333 | ||
4334 | static __be64 get_umr_update_pd_mask(void) | |
4335 | { | |
4336 | u64 result; | |
4337 | ||
31616255 | 4338 | result = MLX5_MKEY_MASK_PD; |
56e11d62 NO |
4339 | |
4340 | return cpu_to_be64(result); | |
4341 | } | |
4342 | ||
c8d75a98 MD |
4343 | static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) |
4344 | { | |
4345 | if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && | |
4346 | MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || | |
4347 | (mask & MLX5_MKEY_MASK_A && | |
4348 | MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) | |
4349 | return -EPERM; | |
4350 | return 0; | |
4351 | } | |
4352 | ||
4353 | static int set_reg_umr_segment(struct mlx5_ib_dev *dev, | |
4354 | struct mlx5_wqe_umr_ctrl_seg *umr, | |
f696bf6d | 4355 | const struct ib_send_wr *wr, int atomic) |
e126ba97 | 4356 | { |
f696bf6d | 4357 | const struct mlx5_umr_wr *umrwr = umr_wr(wr); |
e126ba97 EC |
4358 | |
4359 | memset(umr, 0, sizeof(*umr)); | |
4360 | ||
6a053953 YH |
4361 | if (!umrwr->ignore_free_state) { |
4362 | if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) | |
4363 | /* fail if free */ | |
4364 | umr->flags = MLX5_UMR_CHECK_FREE; | |
4365 | else | |
4366 | /* fail if not free */ | |
4367 | umr->flags = MLX5_UMR_CHECK_NOT_FREE; | |
4368 | } | |
968e78dd | 4369 | |
31616255 AK |
4370 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); |
4371 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { | |
4372 | u64 offset = get_xlt_octo(umrwr->offset); | |
4373 | ||
4374 | umr->xlt_offset = cpu_to_be16(offset & 0xffff); | |
4375 | umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); | |
4376 | umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; | |
e126ba97 | 4377 | } |
31616255 AK |
4378 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) |
4379 | umr->mkey_mask |= get_umr_update_translation_mask(); | |
4380 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { | |
4381 | umr->mkey_mask |= get_umr_update_access_mask(atomic); | |
4382 | umr->mkey_mask |= get_umr_update_pd_mask(); | |
4383 | } | |
4384 | if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) | |
4385 | umr->mkey_mask |= get_umr_enable_mr_mask(); | |
4386 | if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) | |
4387 | umr->mkey_mask |= get_umr_disable_mr_mask(); | |
e126ba97 EC |
4388 | |
4389 | if (!wr->num_sge) | |
968e78dd | 4390 | umr->flags |= MLX5_UMR_INLINE; |
c8d75a98 MD |
4391 | |
4392 | return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); | |
e126ba97 EC |
4393 | } |
4394 | ||
4395 | static u8 get_umr_flags(int acc) | |
4396 | { | |
4397 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | | |
4398 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | | |
4399 | (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | | |
4400 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | | |
2ac45934 | 4401 | MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; |
e126ba97 EC |
4402 | } |
4403 | ||
8a187ee5 SG |
4404 | static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, |
4405 | struct mlx5_ib_mr *mr, | |
4406 | u32 key, int access) | |
4407 | { | |
38ca87c6 | 4408 | int ndescs = ALIGN(mr->ndescs + mr->meta_ndescs, 8) >> 1; |
8a187ee5 SG |
4409 | |
4410 | memset(seg, 0, sizeof(*seg)); | |
b005d316 | 4411 | |
ec22eb53 | 4412 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) |
b005d316 | 4413 | seg->log2_page_size = ilog2(mr->ibmr.page_size); |
ec22eb53 | 4414 | else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
b005d316 SG |
4415 | /* KLMs take twice the size of MTTs */ |
4416 | ndescs *= 2; | |
4417 | ||
4418 | seg->flags = get_umr_flags(access) | mr->access_mode; | |
8a187ee5 SG |
4419 | seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); |
4420 | seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); | |
4421 | seg->start_addr = cpu_to_be64(mr->ibmr.iova); | |
4422 | seg->len = cpu_to_be64(mr->ibmr.length); | |
4423 | seg->xlt_oct_size = cpu_to_be32(ndescs); | |
8a187ee5 SG |
4424 | } |
4425 | ||
dd01e66a | 4426 | static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) |
e126ba97 EC |
4427 | { |
4428 | memset(seg, 0, sizeof(*seg)); | |
dd01e66a | 4429 | seg->status = MLX5_MKEY_STATUS_FREE; |
e126ba97 EC |
4430 | } |
4431 | ||
f696bf6d BVA |
4432 | static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, |
4433 | const struct ib_send_wr *wr) | |
e126ba97 | 4434 | { |
f696bf6d | 4435 | const struct mlx5_umr_wr *umrwr = umr_wr(wr); |
968e78dd | 4436 | |
e126ba97 | 4437 | memset(seg, 0, sizeof(*seg)); |
31616255 | 4438 | if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) |
968e78dd | 4439 | seg->status = MLX5_MKEY_STATUS_FREE; |
e126ba97 | 4440 | |
968e78dd | 4441 | seg->flags = convert_access(umrwr->access_flags); |
31616255 AK |
4442 | if (umrwr->pd) |
4443 | seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); | |
4444 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && | |
4445 | !umrwr->length) | |
4446 | seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); | |
4447 | ||
4448 | seg->start_addr = cpu_to_be64(umrwr->virt_addr); | |
968e78dd HE |
4449 | seg->len = cpu_to_be64(umrwr->length); |
4450 | seg->log2_page_size = umrwr->page_shift; | |
746b5583 | 4451 | seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | |
968e78dd | 4452 | mlx5_mkey_variant(umrwr->mkey)); |
e126ba97 EC |
4453 | } |
4454 | ||
8a187ee5 SG |
4455 | static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, |
4456 | struct mlx5_ib_mr *mr, | |
4457 | struct mlx5_ib_pd *pd) | |
4458 | { | |
38ca87c6 | 4459 | int bcount = mr->desc_size * (mr->ndescs + mr->meta_ndescs); |
8a187ee5 SG |
4460 | |
4461 | dseg->addr = cpu_to_be64(mr->desc_map); | |
4462 | dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); | |
4463 | dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); | |
4464 | } | |
4465 | ||
f696bf6d | 4466 | static __be32 send_ieth(const struct ib_send_wr *wr) |
e126ba97 EC |
4467 | { |
4468 | switch (wr->opcode) { | |
4469 | case IB_WR_SEND_WITH_IMM: | |
4470 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
4471 | return wr->ex.imm_data; | |
4472 | ||
4473 | case IB_WR_SEND_WITH_INV: | |
4474 | return cpu_to_be32(wr->ex.invalidate_rkey); | |
4475 | ||
4476 | default: | |
4477 | return 0; | |
4478 | } | |
4479 | } | |
4480 | ||
4481 | static u8 calc_sig(void *wqe, int size) | |
4482 | { | |
4483 | u8 *p = wqe; | |
4484 | u8 res = 0; | |
4485 | int i; | |
4486 | ||
4487 | for (i = 0; i < size; i++) | |
4488 | res ^= p[i]; | |
4489 | ||
4490 | return ~res; | |
4491 | } | |
4492 | ||
4493 | static u8 wq_sig(void *wqe) | |
4494 | { | |
4495 | return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); | |
4496 | } | |
4497 | ||
f696bf6d | 4498 | static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, |
34f4c955 | 4499 | void **wqe, int *wqe_sz, void **cur_edge) |
e126ba97 EC |
4500 | { |
4501 | struct mlx5_wqe_inline_seg *seg; | |
34f4c955 | 4502 | size_t offset; |
e126ba97 | 4503 | int inl = 0; |
e126ba97 EC |
4504 | int i; |
4505 | ||
34f4c955 GL |
4506 | seg = *wqe; |
4507 | *wqe += sizeof(*seg); | |
4508 | offset = sizeof(*seg); | |
4509 | ||
e126ba97 | 4510 | for (i = 0; i < wr->num_sge; i++) { |
34f4c955 GL |
4511 | size_t len = wr->sg_list[i].length; |
4512 | void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); | |
4513 | ||
e126ba97 EC |
4514 | inl += len; |
4515 | ||
4516 | if (unlikely(inl > qp->max_inline_data)) | |
4517 | return -ENOMEM; | |
4518 | ||
34f4c955 GL |
4519 | while (likely(len)) { |
4520 | size_t leftlen; | |
4521 | size_t copysz; | |
4522 | ||
4523 | handle_post_send_edge(&qp->sq, wqe, | |
4524 | *wqe_sz + (offset >> 4), | |
4525 | cur_edge); | |
4526 | ||
4527 | leftlen = *cur_edge - *wqe; | |
4528 | copysz = min_t(size_t, leftlen, len); | |
4529 | ||
4530 | memcpy(*wqe, addr, copysz); | |
4531 | len -= copysz; | |
4532 | addr += copysz; | |
4533 | *wqe += copysz; | |
4534 | offset += copysz; | |
e126ba97 | 4535 | } |
e126ba97 EC |
4536 | } |
4537 | ||
4538 | seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); | |
4539 | ||
34f4c955 | 4540 | *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; |
e126ba97 EC |
4541 | |
4542 | return 0; | |
4543 | } | |
4544 | ||
e6631814 SG |
4545 | static u16 prot_field_size(enum ib_signature_type type) |
4546 | { | |
4547 | switch (type) { | |
4548 | case IB_SIG_TYPE_T10_DIF: | |
4549 | return MLX5_DIF_SIZE; | |
4550 | default: | |
4551 | return 0; | |
4552 | } | |
4553 | } | |
4554 | ||
4555 | static u8 bs_selector(int block_size) | |
4556 | { | |
4557 | switch (block_size) { | |
4558 | case 512: return 0x1; | |
4559 | case 520: return 0x2; | |
4560 | case 4096: return 0x3; | |
4561 | case 4160: return 0x4; | |
4562 | case 1073741824: return 0x5; | |
4563 | default: return 0; | |
4564 | } | |
4565 | } | |
4566 | ||
78eda2bb SG |
4567 | static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, |
4568 | struct mlx5_bsf_inl *inl) | |
e6631814 | 4569 | { |
142537f4 SG |
4570 | /* Valid inline section and allow BSF refresh */ |
4571 | inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | | |
4572 | MLX5_BSF_REFRESH_DIF); | |
4573 | inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); | |
4574 | inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); | |
78eda2bb SG |
4575 | /* repeating block */ |
4576 | inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; | |
4577 | inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? | |
4578 | MLX5_DIF_CRC : MLX5_DIF_IPCS; | |
e6631814 | 4579 | |
78eda2bb SG |
4580 | if (domain->sig.dif.ref_remap) |
4581 | inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; | |
e6631814 | 4582 | |
78eda2bb SG |
4583 | if (domain->sig.dif.app_escape) { |
4584 | if (domain->sig.dif.ref_escape) | |
4585 | inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; | |
4586 | else | |
4587 | inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; | |
e6631814 SG |
4588 | } |
4589 | ||
78eda2bb SG |
4590 | inl->dif_app_bitmask_check = |
4591 | cpu_to_be16(domain->sig.dif.apptag_check_mask); | |
e6631814 SG |
4592 | } |
4593 | ||
4594 | static int mlx5_set_bsf(struct ib_mr *sig_mr, | |
4595 | struct ib_sig_attrs *sig_attrs, | |
4596 | struct mlx5_bsf *bsf, u32 data_size) | |
4597 | { | |
4598 | struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; | |
4599 | struct mlx5_bsf_basic *basic = &bsf->basic; | |
4600 | struct ib_sig_domain *mem = &sig_attrs->mem; | |
4601 | struct ib_sig_domain *wire = &sig_attrs->wire; | |
e6631814 | 4602 | |
c7f44fbd | 4603 | memset(bsf, 0, sizeof(*bsf)); |
78eda2bb SG |
4604 | |
4605 | /* Basic + Extended + Inline */ | |
4606 | basic->bsf_size_sbs = 1 << 7; | |
4607 | /* Input domain check byte mask */ | |
4608 | basic->check_byte_mask = sig_attrs->check_mask; | |
4609 | basic->raw_data_size = cpu_to_be32(data_size); | |
4610 | ||
4611 | /* Memory domain */ | |
e6631814 | 4612 | switch (sig_attrs->mem.sig_type) { |
78eda2bb SG |
4613 | case IB_SIG_TYPE_NONE: |
4614 | break; | |
e6631814 | 4615 | case IB_SIG_TYPE_T10_DIF: |
78eda2bb SG |
4616 | basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); |
4617 | basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); | |
4618 | mlx5_fill_inl_bsf(mem, &bsf->m_inl); | |
4619 | break; | |
4620 | default: | |
4621 | return -EINVAL; | |
4622 | } | |
e6631814 | 4623 | |
78eda2bb SG |
4624 | /* Wire domain */ |
4625 | switch (sig_attrs->wire.sig_type) { | |
4626 | case IB_SIG_TYPE_NONE: | |
4627 | break; | |
4628 | case IB_SIG_TYPE_T10_DIF: | |
e6631814 | 4629 | if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && |
78eda2bb | 4630 | mem->sig_type == wire->sig_type) { |
e6631814 | 4631 | /* Same block structure */ |
142537f4 | 4632 | basic->bsf_size_sbs |= 1 << 4; |
e6631814 | 4633 | if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) |
fd22f78c | 4634 | basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; |
c7f44fbd | 4635 | if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) |
fd22f78c | 4636 | basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; |
c7f44fbd | 4637 | if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) |
fd22f78c | 4638 | basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; |
e6631814 SG |
4639 | } else |
4640 | basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); | |
4641 | ||
142537f4 | 4642 | basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); |
78eda2bb | 4643 | mlx5_fill_inl_bsf(wire, &bsf->w_inl); |
e6631814 | 4644 | break; |
e6631814 SG |
4645 | default: |
4646 | return -EINVAL; | |
4647 | } | |
4648 | ||
4649 | return 0; | |
4650 | } | |
4651 | ||
38ca87c6 MG |
4652 | static int set_sig_data_segment(const struct ib_send_wr *send_wr, |
4653 | struct ib_mr *sig_mr, | |
4654 | struct ib_sig_attrs *sig_attrs, | |
4655 | struct mlx5_ib_qp *qp, void **seg, int *size, | |
4656 | void **cur_edge) | |
e6631814 | 4657 | { |
e6631814 | 4658 | struct mlx5_bsf *bsf; |
38ca87c6 MG |
4659 | u32 data_len; |
4660 | u32 data_key; | |
4661 | u64 data_va; | |
4662 | u32 prot_len = 0; | |
4663 | u32 prot_key = 0; | |
4664 | u64 prot_va = 0; | |
4665 | bool prot = false; | |
e6631814 SG |
4666 | int ret; |
4667 | int wqe_size; | |
5c171cbe IR |
4668 | struct mlx5_ib_mr *mr = to_mmr(sig_mr); |
4669 | struct mlx5_ib_mr *pi_mr = mr->pi_mr; | |
e6631814 | 4670 | |
5c171cbe IR |
4671 | data_len = pi_mr->data_length; |
4672 | data_key = pi_mr->ibmr.lkey; | |
2563e2f3 | 4673 | data_va = pi_mr->data_iova; |
5c171cbe IR |
4674 | if (pi_mr->meta_ndescs) { |
4675 | prot_len = pi_mr->meta_length; | |
4676 | prot_key = pi_mr->ibmr.lkey; | |
de0ae958 | 4677 | prot_va = pi_mr->pi_iova; |
5c171cbe | 4678 | prot = true; |
38ca87c6 MG |
4679 | } |
4680 | ||
4681 | if (!prot || (data_key == prot_key && data_va == prot_va && | |
4682 | data_len == prot_len)) { | |
e6631814 SG |
4683 | /** |
4684 | * Source domain doesn't contain signature information | |
5c273b16 | 4685 | * or data and protection are interleaved in memory. |
e6631814 SG |
4686 | * So need construct: |
4687 | * ------------------ | |
4688 | * | data_klm | | |
4689 | * ------------------ | |
4690 | * | BSF | | |
4691 | * ------------------ | |
4692 | **/ | |
4693 | struct mlx5_klm *data_klm = *seg; | |
4694 | ||
4695 | data_klm->bcount = cpu_to_be32(data_len); | |
4696 | data_klm->key = cpu_to_be32(data_key); | |
4697 | data_klm->va = cpu_to_be64(data_va); | |
4698 | wqe_size = ALIGN(sizeof(*data_klm), 64); | |
4699 | } else { | |
4700 | /** | |
4701 | * Source domain contains signature information | |
4702 | * So need construct a strided block format: | |
4703 | * --------------------------- | |
4704 | * | stride_block_ctrl | | |
4705 | * --------------------------- | |
4706 | * | data_klm | | |
4707 | * --------------------------- | |
4708 | * | prot_klm | | |
4709 | * --------------------------- | |
4710 | * | BSF | | |
4711 | * --------------------------- | |
4712 | **/ | |
4713 | struct mlx5_stride_block_ctrl_seg *sblock_ctrl; | |
4714 | struct mlx5_stride_block_entry *data_sentry; | |
4715 | struct mlx5_stride_block_entry *prot_sentry; | |
e6631814 SG |
4716 | u16 block_size = sig_attrs->mem.sig.dif.pi_interval; |
4717 | int prot_size; | |
4718 | ||
4719 | sblock_ctrl = *seg; | |
4720 | data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); | |
4721 | prot_sentry = (void *)data_sentry + sizeof(*data_sentry); | |
4722 | ||
4723 | prot_size = prot_field_size(sig_attrs->mem.sig_type); | |
4724 | if (!prot_size) { | |
4725 | pr_err("Bad block size given: %u\n", block_size); | |
4726 | return -EINVAL; | |
4727 | } | |
4728 | sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + | |
4729 | prot_size); | |
4730 | sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); | |
4731 | sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); | |
4732 | sblock_ctrl->num_entries = cpu_to_be16(2); | |
4733 | ||
4734 | data_sentry->bcount = cpu_to_be16(block_size); | |
4735 | data_sentry->key = cpu_to_be32(data_key); | |
4736 | data_sentry->va = cpu_to_be64(data_va); | |
5c273b16 SG |
4737 | data_sentry->stride = cpu_to_be16(block_size); |
4738 | ||
e6631814 SG |
4739 | prot_sentry->bcount = cpu_to_be16(prot_size); |
4740 | prot_sentry->key = cpu_to_be32(prot_key); | |
5c273b16 SG |
4741 | prot_sentry->va = cpu_to_be64(prot_va); |
4742 | prot_sentry->stride = cpu_to_be16(prot_size); | |
e6631814 | 4743 | |
e6631814 SG |
4744 | wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + |
4745 | sizeof(*prot_sentry), 64); | |
4746 | } | |
4747 | ||
4748 | *seg += wqe_size; | |
4749 | *size += wqe_size / 16; | |
34f4c955 | 4750 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e6631814 SG |
4751 | |
4752 | bsf = *seg; | |
4753 | ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); | |
4754 | if (ret) | |
4755 | return -EINVAL; | |
4756 | ||
4757 | *seg += sizeof(*bsf); | |
4758 | *size += sizeof(*bsf) / 16; | |
34f4c955 | 4759 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e6631814 SG |
4760 | |
4761 | return 0; | |
4762 | } | |
4763 | ||
4764 | static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, | |
22465bba MG |
4765 | struct ib_mr *sig_mr, int access_flags, |
4766 | u32 size, u32 length, u32 pdn) | |
e6631814 | 4767 | { |
e6631814 | 4768 | u32 sig_key = sig_mr->rkey; |
d5436ba0 | 4769 | u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; |
e6631814 SG |
4770 | |
4771 | memset(seg, 0, sizeof(*seg)); | |
4772 | ||
22465bba | 4773 | seg->flags = get_umr_flags(access_flags) | MLX5_MKC_ACCESS_MODE_KLMS; |
e6631814 | 4774 | seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); |
d5436ba0 | 4775 | seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | |
e6631814 SG |
4776 | MLX5_MKEY_BSF_EN | pdn); |
4777 | seg->len = cpu_to_be64(length); | |
31616255 | 4778 | seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); |
e6631814 SG |
4779 | seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); |
4780 | } | |
4781 | ||
4782 | static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, | |
31616255 | 4783 | u32 size) |
e6631814 SG |
4784 | { |
4785 | memset(umr, 0, sizeof(*umr)); | |
4786 | ||
4787 | umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; | |
31616255 | 4788 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); |
e6631814 SG |
4789 | umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); |
4790 | umr->mkey_mask = sig_mkey_mask(); | |
4791 | } | |
4792 | ||
38ca87c6 MG |
4793 | static int set_pi_umr_wr(const struct ib_send_wr *send_wr, |
4794 | struct mlx5_ib_qp *qp, void **seg, int *size, | |
4795 | void **cur_edge) | |
4796 | { | |
4797 | const struct ib_reg_wr *wr = reg_wr(send_wr); | |
4798 | struct mlx5_ib_mr *sig_mr = to_mmr(wr->mr); | |
4799 | struct mlx5_ib_mr *pi_mr = sig_mr->pi_mr; | |
4800 | struct ib_sig_attrs *sig_attrs = sig_mr->ibmr.sig_attrs; | |
4801 | u32 pdn = get_pd(qp)->pdn; | |
4802 | u32 xlt_size; | |
4803 | int region_len, ret; | |
4804 | ||
4805 | if (unlikely(send_wr->num_sge != 0) || | |
4806 | unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) || | |
185eddc4 | 4807 | unlikely(!sig_mr->sig) || unlikely(!qp->ibqp.integrity_en) || |
38ca87c6 MG |
4808 | unlikely(!sig_mr->sig->sig_status_checked)) |
4809 | return -EINVAL; | |
4810 | ||
4811 | /* length of the protected region, data + protection */ | |
4812 | region_len = pi_mr->ibmr.length; | |
4813 | ||
4814 | /** | |
4815 | * KLM octoword size - if protection was provided | |
4816 | * then we use strided block format (3 octowords), | |
4817 | * else we use single KLM (1 octoword) | |
4818 | **/ | |
4819 | if (sig_attrs->mem.sig_type != IB_SIG_TYPE_NONE) | |
4820 | xlt_size = 0x30; | |
4821 | else | |
4822 | xlt_size = sizeof(struct mlx5_klm); | |
4823 | ||
4824 | set_sig_umr_segment(*seg, xlt_size); | |
4825 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); | |
4826 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
4827 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); | |
4828 | ||
4829 | set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len, | |
4830 | pdn); | |
4831 | *seg += sizeof(struct mlx5_mkey_seg); | |
4832 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
4833 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); | |
4834 | ||
4835 | ret = set_sig_data_segment(send_wr, wr->mr, sig_attrs, qp, seg, size, | |
4836 | cur_edge); | |
4837 | if (ret) | |
4838 | return ret; | |
4839 | ||
4840 | sig_mr->sig->sig_status_checked = false; | |
4841 | return 0; | |
4842 | } | |
e6631814 | 4843 | |
e6631814 SG |
4844 | static int set_psv_wr(struct ib_sig_domain *domain, |
4845 | u32 psv_idx, void **seg, int *size) | |
4846 | { | |
4847 | struct mlx5_seg_set_psv *psv_seg = *seg; | |
4848 | ||
4849 | memset(psv_seg, 0, sizeof(*psv_seg)); | |
4850 | psv_seg->psv_num = cpu_to_be32(psv_idx); | |
4851 | switch (domain->sig_type) { | |
78eda2bb SG |
4852 | case IB_SIG_TYPE_NONE: |
4853 | break; | |
e6631814 SG |
4854 | case IB_SIG_TYPE_T10_DIF: |
4855 | psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | | |
4856 | domain->sig.dif.app_tag); | |
4857 | psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); | |
e6631814 | 4858 | break; |
e6631814 | 4859 | default: |
12bbf1ea LR |
4860 | pr_err("Bad signature type (%d) is given.\n", |
4861 | domain->sig_type); | |
4862 | return -EINVAL; | |
e6631814 SG |
4863 | } |
4864 | ||
78eda2bb SG |
4865 | *seg += sizeof(*psv_seg); |
4866 | *size += sizeof(*psv_seg) / 16; | |
4867 | ||
e6631814 SG |
4868 | return 0; |
4869 | } | |
4870 | ||
8a187ee5 | 4871 | static int set_reg_wr(struct mlx5_ib_qp *qp, |
f696bf6d | 4872 | const struct ib_reg_wr *wr, |
9ac7c4bc MG |
4873 | void **seg, int *size, void **cur_edge, |
4874 | bool check_not_free) | |
8a187ee5 SG |
4875 | { |
4876 | struct mlx5_ib_mr *mr = to_mmr(wr->mr); | |
4877 | struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); | |
841b07f9 | 4878 | struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device); |
38ca87c6 | 4879 | int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size; |
064e5262 | 4880 | bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; |
841b07f9 | 4881 | bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC; |
9ac7c4bc | 4882 | u8 flags = 0; |
8a187ee5 | 4883 | |
d6de0bb1 | 4884 | if (!mlx5_ib_can_use_umr(dev, atomic, wr->access)) { |
841b07f9 MS |
4885 | mlx5_ib_warn(to_mdev(qp->ibqp.device), |
4886 | "Fast update of %s for MR is disabled\n", | |
4887 | (MLX5_CAP_GEN(dev->mdev, | |
4888 | umr_modify_entity_size_disabled)) ? | |
4889 | "entity size" : | |
4890 | "atomic access"); | |
4891 | return -EINVAL; | |
4892 | } | |
4893 | ||
8a187ee5 SG |
4894 | if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { |
4895 | mlx5_ib_warn(to_mdev(qp->ibqp.device), | |
4896 | "Invalid IB_SEND_INLINE send flag\n"); | |
4897 | return -EINVAL; | |
4898 | } | |
4899 | ||
9ac7c4bc MG |
4900 | if (check_not_free) |
4901 | flags |= MLX5_UMR_CHECK_NOT_FREE; | |
4902 | if (umr_inline) | |
4903 | flags |= MLX5_UMR_INLINE; | |
4904 | ||
841b07f9 | 4905 | set_reg_umr_seg(*seg, mr, flags, atomic); |
8a187ee5 SG |
4906 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4907 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
34f4c955 | 4908 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
8a187ee5 SG |
4909 | |
4910 | set_reg_mkey_seg(*seg, mr, wr->key, wr->access); | |
4911 | *seg += sizeof(struct mlx5_mkey_seg); | |
4912 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
34f4c955 | 4913 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
8a187ee5 | 4914 | |
064e5262 | 4915 | if (umr_inline) { |
34f4c955 GL |
4916 | memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, |
4917 | mr_list_size); | |
4918 | *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); | |
064e5262 IB |
4919 | } else { |
4920 | set_reg_data_seg(*seg, mr, pd); | |
4921 | *seg += sizeof(struct mlx5_wqe_data_seg); | |
4922 | *size += (sizeof(struct mlx5_wqe_data_seg) / 16); | |
4923 | } | |
8a187ee5 SG |
4924 | return 0; |
4925 | } | |
4926 | ||
34f4c955 GL |
4927 | static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, |
4928 | void **cur_edge) | |
e126ba97 | 4929 | { |
dd01e66a | 4930 | set_linv_umr_seg(*seg); |
e126ba97 EC |
4931 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4932 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
34f4c955 | 4933 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
dd01e66a | 4934 | set_linv_mkey_seg(*seg); |
e126ba97 EC |
4935 | *seg += sizeof(struct mlx5_mkey_seg); |
4936 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
34f4c955 | 4937 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e126ba97 EC |
4938 | } |
4939 | ||
34f4c955 | 4940 | static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) |
e126ba97 EC |
4941 | { |
4942 | __be32 *p = NULL; | |
e126ba97 EC |
4943 | int i, j; |
4944 | ||
34f4c955 | 4945 | pr_debug("dump WQE index %u:\n", idx); |
e126ba97 EC |
4946 | for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { |
4947 | if ((i & 0xf) == 0) { | |
1e5887b7 | 4948 | p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx); |
34f4c955 | 4949 | pr_debug("WQBB at %p:\n", (void *)p); |
e126ba97 | 4950 | j = 0; |
1e5887b7 | 4951 | idx = (idx + 1) & (qp->sq.wqe_cnt - 1); |
e126ba97 EC |
4952 | } |
4953 | pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), | |
4954 | be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), | |
4955 | be32_to_cpu(p[j + 3])); | |
4956 | } | |
4957 | } | |
4958 | ||
7bb1fafc | 4959 | static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, |
34f4c955 GL |
4960 | struct mlx5_wqe_ctrl_seg **ctrl, |
4961 | const struct ib_send_wr *wr, unsigned int *idx, | |
4962 | int *size, void **cur_edge, int nreq, | |
4963 | bool send_signaled, bool solicited) | |
6e5eadac | 4964 | { |
b2a232d2 LR |
4965 | if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) |
4966 | return -ENOMEM; | |
6e5eadac SG |
4967 | |
4968 | *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); | |
34f4c955 | 4969 | *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); |
6e5eadac SG |
4970 | *ctrl = *seg; |
4971 | *(uint32_t *)(*seg + 8) = 0; | |
4972 | (*ctrl)->imm = send_ieth(wr); | |
4973 | (*ctrl)->fm_ce_se = qp->sq_signal_bits | | |
7bb1fafc BVA |
4974 | (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | |
4975 | (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); | |
6e5eadac SG |
4976 | |
4977 | *seg += sizeof(**ctrl); | |
4978 | *size = sizeof(**ctrl) / 16; | |
34f4c955 | 4979 | *cur_edge = qp->sq.cur_edge; |
6e5eadac | 4980 | |
b2a232d2 | 4981 | return 0; |
6e5eadac SG |
4982 | } |
4983 | ||
7bb1fafc BVA |
4984 | static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, |
4985 | struct mlx5_wqe_ctrl_seg **ctrl, | |
4986 | const struct ib_send_wr *wr, unsigned *idx, | |
34f4c955 | 4987 | int *size, void **cur_edge, int nreq) |
7bb1fafc | 4988 | { |
34f4c955 | 4989 | return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, |
7bb1fafc BVA |
4990 | wr->send_flags & IB_SEND_SIGNALED, |
4991 | wr->send_flags & IB_SEND_SOLICITED); | |
4992 | } | |
4993 | ||
6e5eadac SG |
4994 | static void finish_wqe(struct mlx5_ib_qp *qp, |
4995 | struct mlx5_wqe_ctrl_seg *ctrl, | |
34f4c955 GL |
4996 | void *seg, u8 size, void *cur_edge, |
4997 | unsigned int idx, u64 wr_id, int nreq, u8 fence, | |
4998 | u32 mlx5_opcode) | |
6e5eadac SG |
4999 | { |
5000 | u8 opmod = 0; | |
5001 | ||
5002 | ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | | |
5003 | mlx5_opcode | ((u32)opmod << 24)); | |
19098df2 | 5004 | ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); |
6e5eadac | 5005 | ctrl->fm_ce_se |= fence; |
6e5eadac SG |
5006 | if (unlikely(qp->wq_sig)) |
5007 | ctrl->signature = wq_sig(ctrl); | |
5008 | ||
5009 | qp->sq.wrid[idx] = wr_id; | |
5010 | qp->sq.w_list[idx].opcode = mlx5_opcode; | |
5011 | qp->sq.wqe_head[idx] = qp->sq.head + nreq; | |
5012 | qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); | |
5013 | qp->sq.w_list[idx].next = qp->sq.cur_post; | |
34f4c955 GL |
5014 | |
5015 | /* We save the edge which was possibly updated during the WQE | |
5016 | * construction, into SQ's cache. | |
5017 | */ | |
5018 | seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); | |
5019 | qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? | |
5020 | get_sq_edge(&qp->sq, qp->sq.cur_post & | |
5021 | (qp->sq.wqe_cnt - 1)) : | |
5022 | cur_edge; | |
6e5eadac SG |
5023 | } |
5024 | ||
d34ac5cd BVA |
5025 | static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
5026 | const struct ib_send_wr **bad_wr, bool drain) | |
e126ba97 EC |
5027 | { |
5028 | struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ | |
5029 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
89ea94a7 | 5030 | struct mlx5_core_dev *mdev = dev->mdev; |
38ca87c6 | 5031 | struct ib_reg_wr reg_pi_wr; |
d16e91da | 5032 | struct mlx5_ib_qp *qp; |
e6631814 | 5033 | struct mlx5_ib_mr *mr; |
38ca87c6 | 5034 | struct mlx5_ib_mr *pi_mr; |
2563e2f3 | 5035 | struct mlx5_ib_mr pa_pi_mr; |
38ca87c6 | 5036 | struct ib_sig_attrs *sig_attrs; |
e126ba97 | 5037 | struct mlx5_wqe_xrc_seg *xrc; |
d16e91da | 5038 | struct mlx5_bf *bf; |
34f4c955 | 5039 | void *cur_edge; |
e126ba97 | 5040 | int uninitialized_var(size); |
e126ba97 | 5041 | unsigned long flags; |
e126ba97 EC |
5042 | unsigned idx; |
5043 | int err = 0; | |
e126ba97 EC |
5044 | int num_sge; |
5045 | void *seg; | |
5046 | int nreq; | |
5047 | int i; | |
5048 | u8 next_fence = 0; | |
e126ba97 EC |
5049 | u8 fence; |
5050 | ||
6c75520f PP |
5051 | if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && |
5052 | !drain)) { | |
5053 | *bad_wr = wr; | |
5054 | return -EIO; | |
5055 | } | |
5056 | ||
d16e91da HE |
5057 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
5058 | return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); | |
5059 | ||
5060 | qp = to_mqp(ibqp); | |
5fe9dec0 | 5061 | bf = &qp->bf; |
d16e91da | 5062 | |
e126ba97 EC |
5063 | spin_lock_irqsave(&qp->sq.lock, flags); |
5064 | ||
5065 | for (nreq = 0; wr; nreq++, wr = wr->next) { | |
a8f731eb | 5066 | if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { |
e126ba97 EC |
5067 | mlx5_ib_warn(dev, "\n"); |
5068 | err = -EINVAL; | |
5069 | *bad_wr = wr; | |
5070 | goto out; | |
5071 | } | |
5072 | ||
6e5eadac SG |
5073 | num_sge = wr->num_sge; |
5074 | if (unlikely(num_sge > qp->sq.max_gs)) { | |
e126ba97 | 5075 | mlx5_ib_warn(dev, "\n"); |
24be409b | 5076 | err = -EINVAL; |
e126ba97 EC |
5077 | *bad_wr = wr; |
5078 | goto out; | |
5079 | } | |
5080 | ||
34f4c955 GL |
5081 | err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, |
5082 | nreq); | |
6e5eadac | 5083 | if (err) { |
e126ba97 EC |
5084 | mlx5_ib_warn(dev, "\n"); |
5085 | err = -ENOMEM; | |
5086 | *bad_wr = wr; | |
5087 | goto out; | |
5088 | } | |
5089 | ||
38ca87c6 MG |
5090 | if (wr->opcode == IB_WR_REG_MR || |
5091 | wr->opcode == IB_WR_REG_MR_INTEGRITY) { | |
6e8484c5 MG |
5092 | fence = dev->umr_fence; |
5093 | next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | |
074fca3a MD |
5094 | } else { |
5095 | if (wr->send_flags & IB_SEND_FENCE) { | |
5096 | if (qp->next_fence) | |
5097 | fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; | |
5098 | else | |
5099 | fence = MLX5_FENCE_MODE_FENCE; | |
5100 | } else { | |
5101 | fence = qp->next_fence; | |
5102 | } | |
6e8484c5 MG |
5103 | } |
5104 | ||
e126ba97 EC |
5105 | switch (ibqp->qp_type) { |
5106 | case IB_QPT_XRC_INI: | |
5107 | xrc = seg; | |
e126ba97 EC |
5108 | seg += sizeof(*xrc); |
5109 | size += sizeof(*xrc) / 16; | |
5110 | /* fall through */ | |
5111 | case IB_QPT_RC: | |
5112 | switch (wr->opcode) { | |
5113 | case IB_WR_RDMA_READ: | |
5114 | case IB_WR_RDMA_WRITE: | |
5115 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
e622f2f4 CH |
5116 | set_raddr_seg(seg, rdma_wr(wr)->remote_addr, |
5117 | rdma_wr(wr)->rkey); | |
f241e749 | 5118 | seg += sizeof(struct mlx5_wqe_raddr_seg); |
e126ba97 EC |
5119 | size += sizeof(struct mlx5_wqe_raddr_seg) / 16; |
5120 | break; | |
5121 | ||
5122 | case IB_WR_ATOMIC_CMP_AND_SWP: | |
5123 | case IB_WR_ATOMIC_FETCH_AND_ADD: | |
e126ba97 | 5124 | case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: |
81bea28f EC |
5125 | mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); |
5126 | err = -ENOSYS; | |
5127 | *bad_wr = wr; | |
5128 | goto out; | |
e126ba97 EC |
5129 | |
5130 | case IB_WR_LOCAL_INV: | |
e126ba97 EC |
5131 | qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; |
5132 | ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); | |
34f4c955 | 5133 | set_linv_wr(qp, &seg, &size, &cur_edge); |
e126ba97 EC |
5134 | num_sge = 0; |
5135 | break; | |
5136 | ||
8a187ee5 | 5137 | case IB_WR_REG_MR: |
8a187ee5 SG |
5138 | qp->sq.wr_data[idx] = IB_WR_REG_MR; |
5139 | ctrl->imm = cpu_to_be32(reg_wr(wr)->key); | |
34f4c955 | 5140 | err = set_reg_wr(qp, reg_wr(wr), &seg, &size, |
9ac7c4bc | 5141 | &cur_edge, true); |
8a187ee5 SG |
5142 | if (err) { |
5143 | *bad_wr = wr; | |
5144 | goto out; | |
5145 | } | |
5146 | num_sge = 0; | |
5147 | break; | |
5148 | ||
38ca87c6 | 5149 | case IB_WR_REG_MR_INTEGRITY: |
2563e2f3 | 5150 | qp->sq.wr_data[idx] = IB_WR_REG_MR_INTEGRITY; |
38ca87c6 MG |
5151 | |
5152 | mr = to_mmr(reg_wr(wr)->mr); | |
5153 | pi_mr = mr->pi_mr; | |
5154 | ||
2563e2f3 MG |
5155 | if (pi_mr) { |
5156 | memset(®_pi_wr, 0, | |
5157 | sizeof(struct ib_reg_wr)); | |
5158 | ||
5159 | reg_pi_wr.mr = &pi_mr->ibmr; | |
5160 | reg_pi_wr.access = reg_wr(wr)->access; | |
5161 | reg_pi_wr.key = pi_mr->ibmr.rkey; | |
5162 | ||
5163 | ctrl->imm = cpu_to_be32(reg_pi_wr.key); | |
5164 | /* UMR for data + prot registration */ | |
5165 | err = set_reg_wr(qp, ®_pi_wr, &seg, | |
5166 | &size, &cur_edge, | |
5167 | false); | |
5168 | if (err) { | |
5169 | *bad_wr = wr; | |
5170 | goto out; | |
5171 | } | |
5172 | finish_wqe(qp, ctrl, seg, size, | |
5173 | cur_edge, idx, wr->wr_id, | |
5174 | nreq, fence, | |
5175 | MLX5_OPCODE_UMR); | |
5176 | ||
5177 | err = begin_wqe(qp, &seg, &ctrl, wr, | |
5178 | &idx, &size, &cur_edge, | |
5179 | nreq); | |
5180 | if (err) { | |
5181 | mlx5_ib_warn(dev, "\n"); | |
5182 | err = -ENOMEM; | |
5183 | *bad_wr = wr; | |
5184 | goto out; | |
5185 | } | |
5186 | } else { | |
5187 | memset(&pa_pi_mr, 0, | |
5188 | sizeof(struct mlx5_ib_mr)); | |
5189 | /* No UMR, use local_dma_lkey */ | |
5190 | pa_pi_mr.ibmr.lkey = | |
5191 | mr->ibmr.pd->local_dma_lkey; | |
5192 | ||
5193 | pa_pi_mr.ndescs = mr->ndescs; | |
5194 | pa_pi_mr.data_length = mr->data_length; | |
5195 | pa_pi_mr.data_iova = mr->data_iova; | |
5196 | if (mr->meta_ndescs) { | |
5197 | pa_pi_mr.meta_ndescs = | |
5198 | mr->meta_ndescs; | |
5199 | pa_pi_mr.meta_length = | |
5200 | mr->meta_length; | |
5201 | pa_pi_mr.pi_iova = mr->pi_iova; | |
5202 | } | |
5203 | ||
5204 | pa_pi_mr.ibmr.length = mr->ibmr.length; | |
5205 | mr->pi_mr = &pa_pi_mr; | |
38ca87c6 MG |
5206 | } |
5207 | ctrl->imm = cpu_to_be32(mr->ibmr.rkey); | |
5208 | /* UMR for sig MR */ | |
5209 | err = set_pi_umr_wr(wr, qp, &seg, &size, | |
5210 | &cur_edge); | |
5211 | if (err) { | |
5212 | mlx5_ib_warn(dev, "\n"); | |
5213 | *bad_wr = wr; | |
5214 | goto out; | |
5215 | } | |
5216 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, | |
5217 | wr->wr_id, nreq, fence, | |
5218 | MLX5_OPCODE_UMR); | |
5219 | ||
5220 | /* | |
5221 | * SET_PSV WQEs are not signaled and solicited | |
5222 | * on error | |
5223 | */ | |
5224 | sig_attrs = mr->ibmr.sig_attrs; | |
5225 | err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, | |
5226 | &size, &cur_edge, nreq, false, | |
5227 | true); | |
5228 | if (err) { | |
5229 | mlx5_ib_warn(dev, "\n"); | |
5230 | err = -ENOMEM; | |
5231 | *bad_wr = wr; | |
5232 | goto out; | |
5233 | } | |
5234 | err = set_psv_wr(&sig_attrs->mem, | |
5235 | mr->sig->psv_memory.psv_idx, | |
5236 | &seg, &size); | |
5237 | if (err) { | |
5238 | mlx5_ib_warn(dev, "\n"); | |
5239 | *bad_wr = wr; | |
5240 | goto out; | |
5241 | } | |
5242 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, | |
5243 | wr->wr_id, nreq, next_fence, | |
5244 | MLX5_OPCODE_SET_PSV); | |
5245 | ||
5246 | err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, | |
5247 | &size, &cur_edge, nreq, false, | |
5248 | true); | |
5249 | if (err) { | |
5250 | mlx5_ib_warn(dev, "\n"); | |
5251 | err = -ENOMEM; | |
5252 | *bad_wr = wr; | |
5253 | goto out; | |
5254 | } | |
5255 | err = set_psv_wr(&sig_attrs->wire, | |
5256 | mr->sig->psv_wire.psv_idx, | |
5257 | &seg, &size); | |
5258 | if (err) { | |
5259 | mlx5_ib_warn(dev, "\n"); | |
5260 | *bad_wr = wr; | |
5261 | goto out; | |
5262 | } | |
5263 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, | |
5264 | wr->wr_id, nreq, next_fence, | |
5265 | MLX5_OPCODE_SET_PSV); | |
5266 | ||
5267 | qp->next_fence = | |
5268 | MLX5_FENCE_MODE_INITIATOR_SMALL; | |
5269 | num_sge = 0; | |
5270 | goto skip_psv; | |
5271 | ||
e126ba97 EC |
5272 | default: |
5273 | break; | |
5274 | } | |
5275 | break; | |
5276 | ||
5277 | case IB_QPT_UC: | |
5278 | switch (wr->opcode) { | |
5279 | case IB_WR_RDMA_WRITE: | |
5280 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
e622f2f4 CH |
5281 | set_raddr_seg(seg, rdma_wr(wr)->remote_addr, |
5282 | rdma_wr(wr)->rkey); | |
e126ba97 EC |
5283 | seg += sizeof(struct mlx5_wqe_raddr_seg); |
5284 | size += sizeof(struct mlx5_wqe_raddr_seg) / 16; | |
5285 | break; | |
5286 | ||
5287 | default: | |
5288 | break; | |
5289 | } | |
5290 | break; | |
5291 | ||
e126ba97 | 5292 | case IB_QPT_SMI: |
1e0e50b6 MG |
5293 | if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { |
5294 | mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); | |
5295 | err = -EPERM; | |
5296 | *bad_wr = wr; | |
5297 | goto out; | |
5298 | } | |
f6b1ee34 | 5299 | /* fall through */ |
d16e91da | 5300 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 | 5301 | set_datagram_seg(seg, wr); |
f241e749 | 5302 | seg += sizeof(struct mlx5_wqe_datagram_seg); |
e126ba97 | 5303 | size += sizeof(struct mlx5_wqe_datagram_seg) / 16; |
34f4c955 GL |
5304 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
5305 | ||
e126ba97 | 5306 | break; |
f0313965 ES |
5307 | case IB_QPT_UD: |
5308 | set_datagram_seg(seg, wr); | |
5309 | seg += sizeof(struct mlx5_wqe_datagram_seg); | |
5310 | size += sizeof(struct mlx5_wqe_datagram_seg) / 16; | |
34f4c955 | 5311 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
f0313965 ES |
5312 | |
5313 | /* handle qp that supports ud offload */ | |
5314 | if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { | |
5315 | struct mlx5_wqe_eth_pad *pad; | |
e126ba97 | 5316 | |
f0313965 ES |
5317 | pad = seg; |
5318 | memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); | |
5319 | seg += sizeof(struct mlx5_wqe_eth_pad); | |
5320 | size += sizeof(struct mlx5_wqe_eth_pad) / 16; | |
34f4c955 GL |
5321 | set_eth_seg(wr, qp, &seg, &size, &cur_edge); |
5322 | handle_post_send_edge(&qp->sq, &seg, size, | |
5323 | &cur_edge); | |
f0313965 ES |
5324 | } |
5325 | break; | |
e126ba97 EC |
5326 | case MLX5_IB_QPT_REG_UMR: |
5327 | if (wr->opcode != MLX5_IB_WR_UMR) { | |
5328 | err = -EINVAL; | |
5329 | mlx5_ib_warn(dev, "bad opcode\n"); | |
5330 | goto out; | |
5331 | } | |
5332 | qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; | |
e622f2f4 | 5333 | ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); |
c8d75a98 MD |
5334 | err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); |
5335 | if (unlikely(err)) | |
5336 | goto out; | |
e126ba97 EC |
5337 | seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
5338 | size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
34f4c955 | 5339 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
e126ba97 EC |
5340 | set_reg_mkey_segment(seg, wr); |
5341 | seg += sizeof(struct mlx5_mkey_seg); | |
5342 | size += sizeof(struct mlx5_mkey_seg) / 16; | |
34f4c955 | 5343 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
e126ba97 EC |
5344 | break; |
5345 | ||
5346 | default: | |
5347 | break; | |
5348 | } | |
5349 | ||
5350 | if (wr->send_flags & IB_SEND_INLINE && num_sge) { | |
34f4c955 | 5351 | err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); |
e126ba97 EC |
5352 | if (unlikely(err)) { |
5353 | mlx5_ib_warn(dev, "\n"); | |
5354 | *bad_wr = wr; | |
5355 | goto out; | |
5356 | } | |
e126ba97 | 5357 | } else { |
e126ba97 | 5358 | for (i = 0; i < num_sge; i++) { |
34f4c955 GL |
5359 | handle_post_send_edge(&qp->sq, &seg, size, |
5360 | &cur_edge); | |
e126ba97 | 5361 | if (likely(wr->sg_list[i].length)) { |
34f4c955 GL |
5362 | set_data_ptr_seg |
5363 | ((struct mlx5_wqe_data_seg *)seg, | |
5364 | wr->sg_list + i); | |
e126ba97 | 5365 | size += sizeof(struct mlx5_wqe_data_seg) / 16; |
34f4c955 | 5366 | seg += sizeof(struct mlx5_wqe_data_seg); |
e126ba97 EC |
5367 | } |
5368 | } | |
5369 | } | |
5370 | ||
6e8484c5 | 5371 | qp->next_fence = next_fence; |
34f4c955 GL |
5372 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, |
5373 | fence, mlx5_ib_opcode[wr->opcode]); | |
e6631814 | 5374 | skip_psv: |
e126ba97 EC |
5375 | if (0) |
5376 | dump_wqe(qp, idx, size); | |
5377 | } | |
5378 | ||
5379 | out: | |
5380 | if (likely(nreq)) { | |
5381 | qp->sq.head += nreq; | |
5382 | ||
5383 | /* Make sure that descriptors are written before | |
5384 | * updating doorbell record and ringing the doorbell | |
5385 | */ | |
5386 | wmb(); | |
5387 | ||
5388 | qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); | |
5389 | ||
ada388f7 EC |
5390 | /* Make sure doorbell record is visible to the HCA before |
5391 | * we hit doorbell */ | |
5392 | wmb(); | |
5393 | ||
bbf29f61 | 5394 | mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset); |
5fe9dec0 EC |
5395 | /* Make sure doorbells don't leak out of SQ spinlock |
5396 | * and reach the HCA out of order. | |
5397 | */ | |
e126ba97 | 5398 | bf->offset ^= bf->buf_size; |
e126ba97 EC |
5399 | } |
5400 | ||
5401 | spin_unlock_irqrestore(&qp->sq.lock, flags); | |
5402 | ||
5403 | return err; | |
5404 | } | |
5405 | ||
d34ac5cd BVA |
5406 | int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
5407 | const struct ib_send_wr **bad_wr) | |
d0e84c0a YH |
5408 | { |
5409 | return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); | |
5410 | } | |
5411 | ||
e126ba97 EC |
5412 | static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) |
5413 | { | |
5414 | sig->signature = calc_sig(sig, size); | |
5415 | } | |
5416 | ||
d34ac5cd BVA |
5417 | static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, |
5418 | const struct ib_recv_wr **bad_wr, bool drain) | |
e126ba97 EC |
5419 | { |
5420 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
5421 | struct mlx5_wqe_data_seg *scat; | |
5422 | struct mlx5_rwqe_sig *sig; | |
89ea94a7 MG |
5423 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); |
5424 | struct mlx5_core_dev *mdev = dev->mdev; | |
e126ba97 EC |
5425 | unsigned long flags; |
5426 | int err = 0; | |
5427 | int nreq; | |
5428 | int ind; | |
5429 | int i; | |
5430 | ||
6c75520f PP |
5431 | if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && |
5432 | !drain)) { | |
5433 | *bad_wr = wr; | |
5434 | return -EIO; | |
5435 | } | |
5436 | ||
d16e91da HE |
5437 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
5438 | return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); | |
5439 | ||
e126ba97 EC |
5440 | spin_lock_irqsave(&qp->rq.lock, flags); |
5441 | ||
5442 | ind = qp->rq.head & (qp->rq.wqe_cnt - 1); | |
5443 | ||
5444 | for (nreq = 0; wr; nreq++, wr = wr->next) { | |
5445 | if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { | |
5446 | err = -ENOMEM; | |
5447 | *bad_wr = wr; | |
5448 | goto out; | |
5449 | } | |
5450 | ||
5451 | if (unlikely(wr->num_sge > qp->rq.max_gs)) { | |
5452 | err = -EINVAL; | |
5453 | *bad_wr = wr; | |
5454 | goto out; | |
5455 | } | |
5456 | ||
34f4c955 | 5457 | scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); |
e126ba97 EC |
5458 | if (qp->wq_sig) |
5459 | scat++; | |
5460 | ||
5461 | for (i = 0; i < wr->num_sge; i++) | |
5462 | set_data_ptr_seg(scat + i, wr->sg_list + i); | |
5463 | ||
5464 | if (i < qp->rq.max_gs) { | |
5465 | scat[i].byte_count = 0; | |
5466 | scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); | |
5467 | scat[i].addr = 0; | |
5468 | } | |
5469 | ||
5470 | if (qp->wq_sig) { | |
5471 | sig = (struct mlx5_rwqe_sig *)scat; | |
5472 | set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); | |
5473 | } | |
5474 | ||
5475 | qp->rq.wrid[ind] = wr->wr_id; | |
5476 | ||
5477 | ind = (ind + 1) & (qp->rq.wqe_cnt - 1); | |
5478 | } | |
5479 | ||
5480 | out: | |
5481 | if (likely(nreq)) { | |
5482 | qp->rq.head += nreq; | |
5483 | ||
5484 | /* Make sure that descriptors are written before | |
5485 | * doorbell record. | |
5486 | */ | |
5487 | wmb(); | |
5488 | ||
5489 | *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); | |
5490 | } | |
5491 | ||
5492 | spin_unlock_irqrestore(&qp->rq.lock, flags); | |
5493 | ||
5494 | return err; | |
5495 | } | |
5496 | ||
d34ac5cd BVA |
5497 | int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, |
5498 | const struct ib_recv_wr **bad_wr) | |
d0e84c0a YH |
5499 | { |
5500 | return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); | |
5501 | } | |
5502 | ||
e126ba97 EC |
5503 | static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) |
5504 | { | |
5505 | switch (mlx5_state) { | |
5506 | case MLX5_QP_STATE_RST: return IB_QPS_RESET; | |
5507 | case MLX5_QP_STATE_INIT: return IB_QPS_INIT; | |
5508 | case MLX5_QP_STATE_RTR: return IB_QPS_RTR; | |
5509 | case MLX5_QP_STATE_RTS: return IB_QPS_RTS; | |
5510 | case MLX5_QP_STATE_SQ_DRAINING: | |
5511 | case MLX5_QP_STATE_SQD: return IB_QPS_SQD; | |
5512 | case MLX5_QP_STATE_SQER: return IB_QPS_SQE; | |
5513 | case MLX5_QP_STATE_ERR: return IB_QPS_ERR; | |
5514 | default: return -1; | |
5515 | } | |
5516 | } | |
5517 | ||
5518 | static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) | |
5519 | { | |
5520 | switch (mlx5_mig_state) { | |
5521 | case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; | |
5522 | case MLX5_QP_PM_REARM: return IB_MIG_REARM; | |
5523 | case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; | |
5524 | default: return -1; | |
5525 | } | |
5526 | } | |
5527 | ||
5528 | static int to_ib_qp_access_flags(int mlx5_flags) | |
5529 | { | |
5530 | int ib_flags = 0; | |
5531 | ||
5532 | if (mlx5_flags & MLX5_QP_BIT_RRE) | |
5533 | ib_flags |= IB_ACCESS_REMOTE_READ; | |
5534 | if (mlx5_flags & MLX5_QP_BIT_RWE) | |
5535 | ib_flags |= IB_ACCESS_REMOTE_WRITE; | |
5536 | if (mlx5_flags & MLX5_QP_BIT_RAE) | |
5537 | ib_flags |= IB_ACCESS_REMOTE_ATOMIC; | |
5538 | ||
5539 | return ib_flags; | |
5540 | } | |
5541 | ||
38349389 | 5542 | static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, |
d8966fcd | 5543 | struct rdma_ah_attr *ah_attr, |
38349389 | 5544 | struct mlx5_qp_path *path) |
e126ba97 | 5545 | { |
e126ba97 | 5546 | |
d8966fcd | 5547 | memset(ah_attr, 0, sizeof(*ah_attr)); |
e126ba97 | 5548 | |
e7996a9a | 5549 | if (!path->port || path->port > ibdev->num_ports) |
e126ba97 EC |
5550 | return; |
5551 | ||
ae59c3f0 LR |
5552 | ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); |
5553 | ||
d8966fcd DC |
5554 | rdma_ah_set_port_num(ah_attr, path->port); |
5555 | rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); | |
5556 | ||
5557 | rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); | |
5558 | rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); | |
5559 | rdma_ah_set_static_rate(ah_attr, | |
5560 | path->static_rate ? path->static_rate - 5 : 0); | |
5561 | if (path->grh_mlid & (1 << 7)) { | |
5562 | u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); | |
5563 | ||
5564 | rdma_ah_set_grh(ah_attr, NULL, | |
5565 | tc_fl & 0xfffff, | |
5566 | path->mgid_index, | |
5567 | path->hop_limit, | |
5568 | (tc_fl >> 20) & 0xff); | |
5569 | rdma_ah_set_dgid_raw(ah_attr, path->rgid); | |
e126ba97 EC |
5570 | } |
5571 | } | |
5572 | ||
6d2f89df | 5573 | static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, |
5574 | struct mlx5_ib_sq *sq, | |
5575 | u8 *sq_state) | |
5576 | { | |
6d2f89df | 5577 | int err; |
5578 | ||
28160771 | 5579 | err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); |
6d2f89df | 5580 | if (err) |
5581 | goto out; | |
6d2f89df | 5582 | sq->state = *sq_state; |
5583 | ||
5584 | out: | |
6d2f89df | 5585 | return err; |
5586 | } | |
5587 | ||
5588 | static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, | |
5589 | struct mlx5_ib_rq *rq, | |
5590 | u8 *rq_state) | |
5591 | { | |
5592 | void *out; | |
5593 | void *rqc; | |
5594 | int inlen; | |
5595 | int err; | |
5596 | ||
5597 | inlen = MLX5_ST_SZ_BYTES(query_rq_out); | |
1b9a07ee | 5598 | out = kvzalloc(inlen, GFP_KERNEL); |
6d2f89df | 5599 | if (!out) |
5600 | return -ENOMEM; | |
5601 | ||
5602 | err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); | |
5603 | if (err) | |
5604 | goto out; | |
5605 | ||
5606 | rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); | |
5607 | *rq_state = MLX5_GET(rqc, rqc, state); | |
5608 | rq->state = *rq_state; | |
5609 | ||
5610 | out: | |
5611 | kvfree(out); | |
5612 | return err; | |
5613 | } | |
5614 | ||
5615 | static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, | |
5616 | struct mlx5_ib_qp *qp, u8 *qp_state) | |
5617 | { | |
5618 | static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { | |
5619 | [MLX5_RQC_STATE_RST] = { | |
5620 | [MLX5_SQC_STATE_RST] = IB_QPS_RESET, | |
5621 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, | |
5622 | [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, | |
5623 | [MLX5_SQ_STATE_NA] = IB_QPS_RESET, | |
5624 | }, | |
5625 | [MLX5_RQC_STATE_RDY] = { | |
5626 | [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, | |
5627 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, | |
5628 | [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, | |
5629 | [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, | |
5630 | }, | |
5631 | [MLX5_RQC_STATE_ERR] = { | |
5632 | [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, | |
5633 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, | |
5634 | [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, | |
5635 | [MLX5_SQ_STATE_NA] = IB_QPS_ERR, | |
5636 | }, | |
5637 | [MLX5_RQ_STATE_NA] = { | |
5638 | [MLX5_SQC_STATE_RST] = IB_QPS_RESET, | |
5639 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, | |
5640 | [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, | |
5641 | [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, | |
5642 | }, | |
5643 | }; | |
5644 | ||
5645 | *qp_state = sqrq_trans[rq_state][sq_state]; | |
5646 | ||
5647 | if (*qp_state == MLX5_QP_STATE_BAD) { | |
5648 | WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", | |
5649 | qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, | |
5650 | qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); | |
5651 | return -EINVAL; | |
5652 | } | |
5653 | ||
5654 | if (*qp_state == MLX5_QP_STATE) | |
5655 | *qp_state = qp->state; | |
5656 | ||
5657 | return 0; | |
5658 | } | |
5659 | ||
5660 | static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, | |
5661 | struct mlx5_ib_qp *qp, | |
5662 | u8 *raw_packet_qp_state) | |
5663 | { | |
5664 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
5665 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
5666 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
5667 | int err; | |
5668 | u8 sq_state = MLX5_SQ_STATE_NA; | |
5669 | u8 rq_state = MLX5_RQ_STATE_NA; | |
5670 | ||
5671 | if (qp->sq.wqe_cnt) { | |
5672 | err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); | |
5673 | if (err) | |
5674 | return err; | |
5675 | } | |
5676 | ||
5677 | if (qp->rq.wqe_cnt) { | |
5678 | err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); | |
5679 | if (err) | |
5680 | return err; | |
5681 | } | |
5682 | ||
5683 | return sqrq_state_to_qp_state(sq_state, rq_state, qp, | |
5684 | raw_packet_qp_state); | |
5685 | } | |
5686 | ||
5687 | static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
5688 | struct ib_qp_attr *qp_attr) | |
e126ba97 | 5689 | { |
09a7d9ec | 5690 | int outlen = MLX5_ST_SZ_BYTES(query_qp_out); |
e126ba97 EC |
5691 | struct mlx5_qp_context *context; |
5692 | int mlx5_state; | |
09a7d9ec | 5693 | u32 *outb; |
e126ba97 EC |
5694 | int err = 0; |
5695 | ||
09a7d9ec | 5696 | outb = kzalloc(outlen, GFP_KERNEL); |
6d2f89df | 5697 | if (!outb) |
5698 | return -ENOMEM; | |
5699 | ||
19098df2 | 5700 | err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, |
09a7d9ec | 5701 | outlen); |
e126ba97 | 5702 | if (err) |
6d2f89df | 5703 | goto out; |
e126ba97 | 5704 | |
09a7d9ec SM |
5705 | /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ |
5706 | context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); | |
5707 | ||
e126ba97 EC |
5708 | mlx5_state = be32_to_cpu(context->flags) >> 28; |
5709 | ||
5710 | qp->state = to_ib_qp_state(mlx5_state); | |
e126ba97 EC |
5711 | qp_attr->path_mtu = context->mtu_msgmax >> 5; |
5712 | qp_attr->path_mig_state = | |
5713 | to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); | |
5714 | qp_attr->qkey = be32_to_cpu(context->qkey); | |
5715 | qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; | |
5716 | qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; | |
5717 | qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; | |
5718 | qp_attr->qp_access_flags = | |
5719 | to_ib_qp_access_flags(be32_to_cpu(context->params2)); | |
5720 | ||
5721 | if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { | |
38349389 DC |
5722 | to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); |
5723 | to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); | |
d3ae2bde NO |
5724 | qp_attr->alt_pkey_index = |
5725 | be16_to_cpu(context->alt_path.pkey_index); | |
d8966fcd DC |
5726 | qp_attr->alt_port_num = |
5727 | rdma_ah_get_port_num(&qp_attr->alt_ah_attr); | |
e126ba97 EC |
5728 | } |
5729 | ||
d3ae2bde | 5730 | qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); |
e126ba97 EC |
5731 | qp_attr->port_num = context->pri_path.port; |
5732 | ||
5733 | /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ | |
5734 | qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; | |
5735 | ||
5736 | qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); | |
5737 | ||
5738 | qp_attr->max_dest_rd_atomic = | |
5739 | 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); | |
5740 | qp_attr->min_rnr_timer = | |
5741 | (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; | |
5742 | qp_attr->timeout = context->pri_path.ackto_lt >> 3; | |
5743 | qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; | |
5744 | qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; | |
5745 | qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; | |
6d2f89df | 5746 | |
5747 | out: | |
5748 | kfree(outb); | |
5749 | return err; | |
5750 | } | |
5751 | ||
776a3906 MS |
5752 | static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, |
5753 | struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
5754 | struct ib_qp_init_attr *qp_init_attr) | |
5755 | { | |
5756 | struct mlx5_core_dct *dct = &mqp->dct.mdct; | |
5757 | u32 *out; | |
5758 | u32 access_flags = 0; | |
5759 | int outlen = MLX5_ST_SZ_BYTES(query_dct_out); | |
5760 | void *dctc; | |
5761 | int err; | |
5762 | int supported_mask = IB_QP_STATE | | |
5763 | IB_QP_ACCESS_FLAGS | | |
5764 | IB_QP_PORT | | |
5765 | IB_QP_MIN_RNR_TIMER | | |
5766 | IB_QP_AV | | |
5767 | IB_QP_PATH_MTU | | |
5768 | IB_QP_PKEY_INDEX; | |
5769 | ||
5770 | if (qp_attr_mask & ~supported_mask) | |
5771 | return -EINVAL; | |
5772 | if (mqp->state != IB_QPS_RTR) | |
5773 | return -EINVAL; | |
5774 | ||
5775 | out = kzalloc(outlen, GFP_KERNEL); | |
5776 | if (!out) | |
5777 | return -ENOMEM; | |
5778 | ||
5779 | err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); | |
5780 | if (err) | |
5781 | goto out; | |
5782 | ||
5783 | dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); | |
5784 | ||
5785 | if (qp_attr_mask & IB_QP_STATE) | |
5786 | qp_attr->qp_state = IB_QPS_RTR; | |
5787 | ||
5788 | if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { | |
5789 | if (MLX5_GET(dctc, dctc, rre)) | |
5790 | access_flags |= IB_ACCESS_REMOTE_READ; | |
5791 | if (MLX5_GET(dctc, dctc, rwe)) | |
5792 | access_flags |= IB_ACCESS_REMOTE_WRITE; | |
5793 | if (MLX5_GET(dctc, dctc, rae)) | |
5794 | access_flags |= IB_ACCESS_REMOTE_ATOMIC; | |
5795 | qp_attr->qp_access_flags = access_flags; | |
5796 | } | |
5797 | ||
5798 | if (qp_attr_mask & IB_QP_PORT) | |
5799 | qp_attr->port_num = MLX5_GET(dctc, dctc, port); | |
5800 | if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) | |
5801 | qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); | |
5802 | if (qp_attr_mask & IB_QP_AV) { | |
5803 | qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); | |
5804 | qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); | |
5805 | qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); | |
5806 | qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); | |
5807 | } | |
5808 | if (qp_attr_mask & IB_QP_PATH_MTU) | |
5809 | qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); | |
5810 | if (qp_attr_mask & IB_QP_PKEY_INDEX) | |
5811 | qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); | |
5812 | out: | |
5813 | kfree(out); | |
5814 | return err; | |
5815 | } | |
5816 | ||
6d2f89df | 5817 | int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, |
5818 | int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) | |
5819 | { | |
5820 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
5821 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
5822 | int err = 0; | |
5823 | u8 raw_packet_qp_state; | |
5824 | ||
28d61370 YH |
5825 | if (ibqp->rwq_ind_tbl) |
5826 | return -ENOSYS; | |
5827 | ||
d16e91da HE |
5828 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
5829 | return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, | |
5830 | qp_init_attr); | |
5831 | ||
c2e53b2c YH |
5832 | /* Not all of output fields are applicable, make sure to zero them */ |
5833 | memset(qp_init_attr, 0, sizeof(*qp_init_attr)); | |
5834 | memset(qp_attr, 0, sizeof(*qp_attr)); | |
5835 | ||
776a3906 MS |
5836 | if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) |
5837 | return mlx5_ib_dct_query_qp(dev, qp, qp_attr, | |
5838 | qp_attr_mask, qp_init_attr); | |
5839 | ||
6d2f89df | 5840 | mutex_lock(&qp->mutex); |
5841 | ||
c2e53b2c YH |
5842 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
5843 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
6d2f89df | 5844 | err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); |
5845 | if (err) | |
5846 | goto out; | |
5847 | qp->state = raw_packet_qp_state; | |
5848 | qp_attr->port_num = 1; | |
5849 | } else { | |
5850 | err = query_qp_attr(dev, qp, qp_attr); | |
5851 | if (err) | |
5852 | goto out; | |
5853 | } | |
5854 | ||
5855 | qp_attr->qp_state = qp->state; | |
e126ba97 EC |
5856 | qp_attr->cur_qp_state = qp_attr->qp_state; |
5857 | qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; | |
5858 | qp_attr->cap.max_recv_sge = qp->rq.max_gs; | |
5859 | ||
5860 | if (!ibqp->uobject) { | |
0540d814 | 5861 | qp_attr->cap.max_send_wr = qp->sq.max_post; |
e126ba97 | 5862 | qp_attr->cap.max_send_sge = qp->sq.max_gs; |
0540d814 | 5863 | qp_init_attr->qp_context = ibqp->qp_context; |
e126ba97 EC |
5864 | } else { |
5865 | qp_attr->cap.max_send_wr = 0; | |
5866 | qp_attr->cap.max_send_sge = 0; | |
5867 | } | |
5868 | ||
0540d814 NO |
5869 | qp_init_attr->qp_type = ibqp->qp_type; |
5870 | qp_init_attr->recv_cq = ibqp->recv_cq; | |
5871 | qp_init_attr->send_cq = ibqp->send_cq; | |
5872 | qp_init_attr->srq = ibqp->srq; | |
5873 | qp_attr->cap.max_inline_data = qp->max_inline_data; | |
e126ba97 EC |
5874 | |
5875 | qp_init_attr->cap = qp_attr->cap; | |
5876 | ||
5877 | qp_init_attr->create_flags = 0; | |
5878 | if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) | |
5879 | qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; | |
5880 | ||
051f2630 LR |
5881 | if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) |
5882 | qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; | |
5883 | if (qp->flags & MLX5_IB_QP_MANAGED_SEND) | |
5884 | qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; | |
5885 | if (qp->flags & MLX5_IB_QP_MANAGED_RECV) | |
5886 | qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; | |
b11a4f9c | 5887 | if (qp->flags & MLX5_IB_QP_SQPN_QP1) |
3f89b01f | 5888 | qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; |
051f2630 | 5889 | |
e126ba97 EC |
5890 | qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? |
5891 | IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; | |
5892 | ||
e126ba97 EC |
5893 | out: |
5894 | mutex_unlock(&qp->mutex); | |
5895 | return err; | |
5896 | } | |
5897 | ||
5898 | struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, | |
ff23dfa1 | 5899 | struct ib_udata *udata) |
e126ba97 EC |
5900 | { |
5901 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
5902 | struct mlx5_ib_xrcd *xrcd; | |
5903 | int err; | |
5904 | ||
938fe83c | 5905 | if (!MLX5_CAP_GEN(dev->mdev, xrc)) |
e126ba97 EC |
5906 | return ERR_PTR(-ENOSYS); |
5907 | ||
5908 | xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); | |
5909 | if (!xrcd) | |
5910 | return ERR_PTR(-ENOMEM); | |
5911 | ||
5aa3771d | 5912 | err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); |
e126ba97 EC |
5913 | if (err) { |
5914 | kfree(xrcd); | |
5915 | return ERR_PTR(-ENOMEM); | |
5916 | } | |
5917 | ||
5918 | return &xrcd->ibxrcd; | |
5919 | } | |
5920 | ||
c4367a26 | 5921 | int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) |
e126ba97 EC |
5922 | { |
5923 | struct mlx5_ib_dev *dev = to_mdev(xrcd->device); | |
5924 | u32 xrcdn = to_mxrcd(xrcd)->xrcdn; | |
5925 | int err; | |
5926 | ||
5aa3771d | 5927 | err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); |
b081808a | 5928 | if (err) |
e126ba97 | 5929 | mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); |
e126ba97 EC |
5930 | |
5931 | kfree(xrcd); | |
e126ba97 EC |
5932 | return 0; |
5933 | } | |
79b20a6c | 5934 | |
350d0e4c YH |
5935 | static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) |
5936 | { | |
5937 | struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); | |
5938 | struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); | |
5939 | struct ib_event event; | |
5940 | ||
5941 | if (rwq->ibwq.event_handler) { | |
5942 | event.device = rwq->ibwq.device; | |
5943 | event.element.wq = &rwq->ibwq; | |
5944 | switch (type) { | |
5945 | case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: | |
5946 | event.event = IB_EVENT_WQ_FATAL; | |
5947 | break; | |
5948 | default: | |
5949 | mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); | |
5950 | return; | |
5951 | } | |
5952 | ||
5953 | rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); | |
5954 | } | |
5955 | } | |
5956 | ||
03404e8a MG |
5957 | static int set_delay_drop(struct mlx5_ib_dev *dev) |
5958 | { | |
5959 | int err = 0; | |
5960 | ||
5961 | mutex_lock(&dev->delay_drop.lock); | |
5962 | if (dev->delay_drop.activate) | |
5963 | goto out; | |
5964 | ||
5965 | err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); | |
5966 | if (err) | |
5967 | goto out; | |
5968 | ||
5969 | dev->delay_drop.activate = true; | |
5970 | out: | |
5971 | mutex_unlock(&dev->delay_drop.lock); | |
fe248c3a MG |
5972 | |
5973 | if (!err) | |
5974 | atomic_inc(&dev->delay_drop.rqs_cnt); | |
03404e8a MG |
5975 | return err; |
5976 | } | |
5977 | ||
79b20a6c YH |
5978 | static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, |
5979 | struct ib_wq_init_attr *init_attr) | |
5980 | { | |
5981 | struct mlx5_ib_dev *dev; | |
4be6da1e | 5982 | int has_net_offloads; |
79b20a6c YH |
5983 | __be64 *rq_pas0; |
5984 | void *in; | |
5985 | void *rqc; | |
5986 | void *wq; | |
5987 | int inlen; | |
5988 | int err; | |
5989 | ||
5990 | dev = to_mdev(pd->device); | |
5991 | ||
5992 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; | |
1b9a07ee | 5993 | in = kvzalloc(inlen, GFP_KERNEL); |
79b20a6c YH |
5994 | if (!in) |
5995 | return -ENOMEM; | |
5996 | ||
34d57585 | 5997 | MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); |
79b20a6c YH |
5998 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); |
5999 | MLX5_SET(rqc, rqc, mem_rq_type, | |
6000 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); | |
6001 | MLX5_SET(rqc, rqc, user_index, rwq->user_index); | |
6002 | MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); | |
6003 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); | |
6004 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
6005 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
ccc87087 NO |
6006 | MLX5_SET(wq, wq, wq_type, |
6007 | rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? | |
6008 | MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); | |
b1383aa6 NO |
6009 | if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { |
6010 | if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { | |
6011 | mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); | |
6012 | err = -EOPNOTSUPP; | |
6013 | goto out; | |
6014 | } else { | |
6015 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
6016 | } | |
6017 | } | |
79b20a6c | 6018 | MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); |
ccc87087 | 6019 | if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { |
c16339b6 MZ |
6020 | /* |
6021 | * In Firmware number of strides in each WQE is: | |
6022 | * "512 * 2^single_wqe_log_num_of_strides" | |
6023 | * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are | |
6024 | * accepted as 0 to 9 | |
6025 | */ | |
6026 | static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1, | |
6027 | 2, 3, 4, 5, 6, 7, 8, 9 }; | |
ccc87087 NO |
6028 | MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); |
6029 | MLX5_SET(wq, wq, log_wqe_stride_size, | |
6030 | rwq->single_stride_log_num_of_bytes - | |
6031 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); | |
c16339b6 MZ |
6032 | MLX5_SET(wq, wq, log_wqe_num_of_strides, |
6033 | fw_map[rwq->log_num_strides - | |
6034 | MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]); | |
ccc87087 | 6035 | } |
79b20a6c YH |
6036 | MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); |
6037 | MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); | |
6038 | MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); | |
6039 | MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); | |
6040 | MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); | |
6041 | MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); | |
4be6da1e | 6042 | has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); |
b1f74a84 | 6043 | if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { |
4be6da1e | 6044 | if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { |
b1f74a84 NO |
6045 | mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); |
6046 | err = -EOPNOTSUPP; | |
6047 | goto out; | |
6048 | } | |
6049 | } else { | |
6050 | MLX5_SET(rqc, rqc, vsd, 1); | |
6051 | } | |
4be6da1e NO |
6052 | if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { |
6053 | if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { | |
6054 | mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); | |
6055 | err = -EOPNOTSUPP; | |
6056 | goto out; | |
6057 | } | |
6058 | MLX5_SET(rqc, rqc, scatter_fcs, 1); | |
6059 | } | |
03404e8a MG |
6060 | if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { |
6061 | if (!(dev->ib_dev.attrs.raw_packet_caps & | |
6062 | IB_RAW_PACKET_CAP_DELAY_DROP)) { | |
6063 | mlx5_ib_dbg(dev, "Delay drop is not supported\n"); | |
6064 | err = -EOPNOTSUPP; | |
6065 | goto out; | |
6066 | } | |
6067 | MLX5_SET(rqc, rqc, delay_drop_en, 1); | |
6068 | } | |
79b20a6c YH |
6069 | rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); |
6070 | mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); | |
350d0e4c | 6071 | err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); |
03404e8a MG |
6072 | if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { |
6073 | err = set_delay_drop(dev); | |
6074 | if (err) { | |
6075 | mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", | |
6076 | err); | |
6077 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); | |
6078 | } else { | |
6079 | rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; | |
6080 | } | |
6081 | } | |
b1f74a84 | 6082 | out: |
79b20a6c YH |
6083 | kvfree(in); |
6084 | return err; | |
6085 | } | |
6086 | ||
6087 | static int set_user_rq_size(struct mlx5_ib_dev *dev, | |
6088 | struct ib_wq_init_attr *wq_init_attr, | |
6089 | struct mlx5_ib_create_wq *ucmd, | |
6090 | struct mlx5_ib_rwq *rwq) | |
6091 | { | |
6092 | /* Sanity check RQ size before proceeding */ | |
6093 | if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) | |
6094 | return -EINVAL; | |
6095 | ||
6096 | if (!ucmd->rq_wqe_count) | |
6097 | return -EINVAL; | |
6098 | ||
6099 | rwq->wqe_count = ucmd->rq_wqe_count; | |
6100 | rwq->wqe_shift = ucmd->rq_wqe_shift; | |
0dfe4522 LR |
6101 | if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) |
6102 | return -EINVAL; | |
6103 | ||
79b20a6c YH |
6104 | rwq->log_rq_stride = rwq->wqe_shift; |
6105 | rwq->log_rq_size = ilog2(rwq->wqe_count); | |
6106 | return 0; | |
6107 | } | |
6108 | ||
c16339b6 MZ |
6109 | static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides) |
6110 | { | |
6111 | if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || | |
6112 | (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) | |
6113 | return false; | |
6114 | ||
6115 | if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) && | |
6116 | (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) | |
6117 | return false; | |
6118 | ||
6119 | return true; | |
6120 | } | |
6121 | ||
79b20a6c YH |
6122 | static int prepare_user_rq(struct ib_pd *pd, |
6123 | struct ib_wq_init_attr *init_attr, | |
6124 | struct ib_udata *udata, | |
6125 | struct mlx5_ib_rwq *rwq) | |
6126 | { | |
6127 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
6128 | struct mlx5_ib_create_wq ucmd = {}; | |
6129 | int err; | |
6130 | size_t required_cmd_sz; | |
6131 | ||
ccc87087 NO |
6132 | required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) |
6133 | + sizeof(ucmd.single_stride_log_num_of_bytes); | |
79b20a6c YH |
6134 | if (udata->inlen < required_cmd_sz) { |
6135 | mlx5_ib_dbg(dev, "invalid inlen\n"); | |
6136 | return -EINVAL; | |
6137 | } | |
6138 | ||
6139 | if (udata->inlen > sizeof(ucmd) && | |
6140 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
6141 | udata->inlen - sizeof(ucmd))) { | |
6142 | mlx5_ib_dbg(dev, "inlen is not supported\n"); | |
6143 | return -EOPNOTSUPP; | |
6144 | } | |
6145 | ||
6146 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { | |
6147 | mlx5_ib_dbg(dev, "copy failed\n"); | |
6148 | return -EFAULT; | |
6149 | } | |
6150 | ||
ccc87087 | 6151 | if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { |
79b20a6c YH |
6152 | mlx5_ib_dbg(dev, "invalid comp mask\n"); |
6153 | return -EOPNOTSUPP; | |
ccc87087 NO |
6154 | } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { |
6155 | if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { | |
6156 | mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); | |
6157 | return -EOPNOTSUPP; | |
6158 | } | |
6159 | if ((ucmd.single_stride_log_num_of_bytes < | |
6160 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || | |
6161 | (ucmd.single_stride_log_num_of_bytes > | |
6162 | MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { | |
6163 | mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", | |
6164 | ucmd.single_stride_log_num_of_bytes, | |
6165 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, | |
6166 | MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); | |
6167 | return -EINVAL; | |
6168 | } | |
c16339b6 MZ |
6169 | if (!log_of_strides_valid(dev, |
6170 | ucmd.single_wqe_log_num_of_strides)) { | |
6171 | mlx5_ib_dbg( | |
6172 | dev, | |
6173 | "Invalid log num strides (%u. Range is %u - %u)\n", | |
6174 | ucmd.single_wqe_log_num_of_strides, | |
6175 | MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ? | |
6176 | MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES : | |
6177 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, | |
6178 | MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); | |
ccc87087 NO |
6179 | return -EINVAL; |
6180 | } | |
6181 | rwq->single_stride_log_num_of_bytes = | |
6182 | ucmd.single_stride_log_num_of_bytes; | |
6183 | rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; | |
6184 | rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; | |
6185 | rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; | |
79b20a6c YH |
6186 | } |
6187 | ||
6188 | err = set_user_rq_size(dev, init_attr, &ucmd, rwq); | |
6189 | if (err) { | |
6190 | mlx5_ib_dbg(dev, "err %d\n", err); | |
6191 | return err; | |
6192 | } | |
6193 | ||
b0ea0fa5 | 6194 | err = create_user_rq(dev, pd, udata, rwq, &ucmd); |
79b20a6c YH |
6195 | if (err) { |
6196 | mlx5_ib_dbg(dev, "err %d\n", err); | |
645ba597 | 6197 | return err; |
79b20a6c YH |
6198 | } |
6199 | ||
6200 | rwq->user_index = ucmd.user_index; | |
6201 | return 0; | |
6202 | } | |
6203 | ||
6204 | struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, | |
6205 | struct ib_wq_init_attr *init_attr, | |
6206 | struct ib_udata *udata) | |
6207 | { | |
6208 | struct mlx5_ib_dev *dev; | |
6209 | struct mlx5_ib_rwq *rwq; | |
6210 | struct mlx5_ib_create_wq_resp resp = {}; | |
6211 | size_t min_resp_len; | |
6212 | int err; | |
6213 | ||
6214 | if (!udata) | |
6215 | return ERR_PTR(-ENOSYS); | |
6216 | ||
6217 | min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); | |
6218 | if (udata->outlen && udata->outlen < min_resp_len) | |
6219 | return ERR_PTR(-EINVAL); | |
6220 | ||
ba80013f MG |
6221 | if (!capable(CAP_SYS_RAWIO) && |
6222 | init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) | |
6223 | return ERR_PTR(-EPERM); | |
6224 | ||
79b20a6c YH |
6225 | dev = to_mdev(pd->device); |
6226 | switch (init_attr->wq_type) { | |
6227 | case IB_WQT_RQ: | |
6228 | rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); | |
6229 | if (!rwq) | |
6230 | return ERR_PTR(-ENOMEM); | |
6231 | err = prepare_user_rq(pd, init_attr, udata, rwq); | |
6232 | if (err) | |
6233 | goto err; | |
6234 | err = create_rq(rwq, pd, init_attr); | |
6235 | if (err) | |
6236 | goto err_user_rq; | |
6237 | break; | |
6238 | default: | |
6239 | mlx5_ib_dbg(dev, "unsupported wq type %d\n", | |
6240 | init_attr->wq_type); | |
6241 | return ERR_PTR(-EINVAL); | |
6242 | } | |
6243 | ||
350d0e4c | 6244 | rwq->ibwq.wq_num = rwq->core_qp.qpn; |
79b20a6c YH |
6245 | rwq->ibwq.state = IB_WQS_RESET; |
6246 | if (udata->outlen) { | |
6247 | resp.response_length = offsetof(typeof(resp), response_length) + | |
6248 | sizeof(resp.response_length); | |
6249 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
6250 | if (err) | |
6251 | goto err_copy; | |
6252 | } | |
6253 | ||
350d0e4c YH |
6254 | rwq->core_qp.event = mlx5_ib_wq_event; |
6255 | rwq->ibwq.event_handler = init_attr->event_handler; | |
79b20a6c YH |
6256 | return &rwq->ibwq; |
6257 | ||
6258 | err_copy: | |
350d0e4c | 6259 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); |
79b20a6c | 6260 | err_user_rq: |
bdeacabd | 6261 | destroy_user_rq(dev, pd, rwq, udata); |
79b20a6c YH |
6262 | err: |
6263 | kfree(rwq); | |
6264 | return ERR_PTR(err); | |
6265 | } | |
6266 | ||
a49b1dc7 | 6267 | void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) |
79b20a6c YH |
6268 | { |
6269 | struct mlx5_ib_dev *dev = to_mdev(wq->device); | |
6270 | struct mlx5_ib_rwq *rwq = to_mrwq(wq); | |
6271 | ||
350d0e4c | 6272 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); |
bdeacabd | 6273 | destroy_user_rq(dev, wq->pd, rwq, udata); |
79b20a6c | 6274 | kfree(rwq); |
79b20a6c YH |
6275 | } |
6276 | ||
c5f90929 YH |
6277 | struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, |
6278 | struct ib_rwq_ind_table_init_attr *init_attr, | |
6279 | struct ib_udata *udata) | |
6280 | { | |
6281 | struct mlx5_ib_dev *dev = to_mdev(device); | |
6282 | struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; | |
6283 | int sz = 1 << init_attr->log_ind_tbl_size; | |
6284 | struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; | |
6285 | size_t min_resp_len; | |
6286 | int inlen; | |
6287 | int err; | |
6288 | int i; | |
6289 | u32 *in; | |
6290 | void *rqtc; | |
6291 | ||
6292 | if (udata->inlen > 0 && | |
6293 | !ib_is_udata_cleared(udata, 0, | |
6294 | udata->inlen)) | |
6295 | return ERR_PTR(-EOPNOTSUPP); | |
6296 | ||
efd7f400 MG |
6297 | if (init_attr->log_ind_tbl_size > |
6298 | MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { | |
6299 | mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", | |
6300 | init_attr->log_ind_tbl_size, | |
6301 | MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); | |
6302 | return ERR_PTR(-EINVAL); | |
6303 | } | |
6304 | ||
c5f90929 YH |
6305 | min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); |
6306 | if (udata->outlen && udata->outlen < min_resp_len) | |
6307 | return ERR_PTR(-EINVAL); | |
6308 | ||
6309 | rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); | |
6310 | if (!rwq_ind_tbl) | |
6311 | return ERR_PTR(-ENOMEM); | |
6312 | ||
6313 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; | |
1b9a07ee | 6314 | in = kvzalloc(inlen, GFP_KERNEL); |
c5f90929 YH |
6315 | if (!in) { |
6316 | err = -ENOMEM; | |
6317 | goto err; | |
6318 | } | |
6319 | ||
6320 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
6321 | ||
6322 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
6323 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
6324 | ||
6325 | for (i = 0; i < sz; i++) | |
6326 | MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); | |
6327 | ||
5deba86e YH |
6328 | rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; |
6329 | MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); | |
6330 | ||
c5f90929 YH |
6331 | err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); |
6332 | kvfree(in); | |
6333 | ||
6334 | if (err) | |
6335 | goto err; | |
6336 | ||
6337 | rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; | |
6338 | if (udata->outlen) { | |
6339 | resp.response_length = offsetof(typeof(resp), response_length) + | |
6340 | sizeof(resp.response_length); | |
6341 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
6342 | if (err) | |
6343 | goto err_copy; | |
6344 | } | |
6345 | ||
6346 | return &rwq_ind_tbl->ib_rwq_ind_tbl; | |
6347 | ||
6348 | err_copy: | |
5deba86e | 6349 | mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); |
c5f90929 YH |
6350 | err: |
6351 | kfree(rwq_ind_tbl); | |
6352 | return ERR_PTR(err); | |
6353 | } | |
6354 | ||
6355 | int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) | |
6356 | { | |
6357 | struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); | |
6358 | struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); | |
6359 | ||
5deba86e | 6360 | mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); |
c5f90929 YH |
6361 | |
6362 | kfree(rwq_ind_tbl); | |
6363 | return 0; | |
6364 | } | |
6365 | ||
79b20a6c YH |
6366 | int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, |
6367 | u32 wq_attr_mask, struct ib_udata *udata) | |
6368 | { | |
6369 | struct mlx5_ib_dev *dev = to_mdev(wq->device); | |
6370 | struct mlx5_ib_rwq *rwq = to_mrwq(wq); | |
6371 | struct mlx5_ib_modify_wq ucmd = {}; | |
6372 | size_t required_cmd_sz; | |
6373 | int curr_wq_state; | |
6374 | int wq_state; | |
6375 | int inlen; | |
6376 | int err; | |
6377 | void *rqc; | |
6378 | void *in; | |
6379 | ||
6380 | required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); | |
6381 | if (udata->inlen < required_cmd_sz) | |
6382 | return -EINVAL; | |
6383 | ||
6384 | if (udata->inlen > sizeof(ucmd) && | |
6385 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
6386 | udata->inlen - sizeof(ucmd))) | |
6387 | return -EOPNOTSUPP; | |
6388 | ||
6389 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) | |
6390 | return -EFAULT; | |
6391 | ||
6392 | if (ucmd.comp_mask || ucmd.reserved) | |
6393 | return -EOPNOTSUPP; | |
6394 | ||
6395 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 6396 | in = kvzalloc(inlen, GFP_KERNEL); |
79b20a6c YH |
6397 | if (!in) |
6398 | return -ENOMEM; | |
6399 | ||
6400 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
6401 | ||
6402 | curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? | |
6403 | wq_attr->curr_wq_state : wq->state; | |
6404 | wq_state = (wq_attr_mask & IB_WQ_STATE) ? | |
6405 | wq_attr->wq_state : curr_wq_state; | |
6406 | if (curr_wq_state == IB_WQS_ERR) | |
6407 | curr_wq_state = MLX5_RQC_STATE_ERR; | |
6408 | if (wq_state == IB_WQS_ERR) | |
6409 | wq_state = MLX5_RQC_STATE_ERR; | |
6410 | MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); | |
34d57585 | 6411 | MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); |
79b20a6c YH |
6412 | MLX5_SET(rqc, rqc, state, wq_state); |
6413 | ||
b1f74a84 NO |
6414 | if (wq_attr_mask & IB_WQ_FLAGS) { |
6415 | if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { | |
6416 | if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && | |
6417 | MLX5_CAP_ETH(dev->mdev, vlan_cap))) { | |
6418 | mlx5_ib_dbg(dev, "VLAN offloads are not " | |
6419 | "supported\n"); | |
6420 | err = -EOPNOTSUPP; | |
6421 | goto out; | |
6422 | } | |
6423 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
6424 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
6425 | MLX5_SET(rqc, rqc, vsd, | |
6426 | (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); | |
6427 | } | |
b1383aa6 NO |
6428 | |
6429 | if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { | |
6430 | mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); | |
6431 | err = -EOPNOTSUPP; | |
6432 | goto out; | |
6433 | } | |
b1f74a84 NO |
6434 | } |
6435 | ||
23a6964e | 6436 | if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { |
3e1f000f PP |
6437 | u16 set_id; |
6438 | ||
6439 | set_id = mlx5_ib_get_counters_id(dev, 0); | |
23a6964e MD |
6440 | if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { |
6441 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
6442 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); | |
3e1f000f | 6443 | MLX5_SET(rqc, rqc, counter_set_id, set_id); |
23a6964e | 6444 | } else |
5a738b5d JG |
6445 | dev_info_once( |
6446 | &dev->ib_dev.dev, | |
6447 | "Receive WQ counters are not supported on current FW\n"); | |
23a6964e MD |
6448 | } |
6449 | ||
350d0e4c | 6450 | err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); |
79b20a6c YH |
6451 | if (!err) |
6452 | rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; | |
6453 | ||
b1f74a84 NO |
6454 | out: |
6455 | kvfree(in); | |
79b20a6c YH |
6456 | return err; |
6457 | } | |
d0e84c0a YH |
6458 | |
6459 | struct mlx5_ib_drain_cqe { | |
6460 | struct ib_cqe cqe; | |
6461 | struct completion done; | |
6462 | }; | |
6463 | ||
6464 | static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) | |
6465 | { | |
6466 | struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, | |
6467 | struct mlx5_ib_drain_cqe, | |
6468 | cqe); | |
6469 | ||
6470 | complete(&cqe->done); | |
6471 | } | |
6472 | ||
6473 | /* This function returns only once the drained WR was completed */ | |
6474 | static void handle_drain_completion(struct ib_cq *cq, | |
6475 | struct mlx5_ib_drain_cqe *sdrain, | |
6476 | struct mlx5_ib_dev *dev) | |
6477 | { | |
6478 | struct mlx5_core_dev *mdev = dev->mdev; | |
6479 | ||
6480 | if (cq->poll_ctx == IB_POLL_DIRECT) { | |
6481 | while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) | |
6482 | ib_process_cq_direct(cq, -1); | |
6483 | return; | |
6484 | } | |
6485 | ||
6486 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
6487 | struct mlx5_ib_cq *mcq = to_mcq(cq); | |
6488 | bool triggered = false; | |
6489 | unsigned long flags; | |
6490 | ||
6491 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
6492 | /* Make sure that the CQ handler won't run if wasn't run yet */ | |
6493 | if (!mcq->mcq.reset_notify_added) | |
6494 | mcq->mcq.reset_notify_added = 1; | |
6495 | else | |
6496 | triggered = true; | |
6497 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
6498 | ||
6499 | if (triggered) { | |
6500 | /* Wait for any scheduled/running task to be ended */ | |
6501 | switch (cq->poll_ctx) { | |
6502 | case IB_POLL_SOFTIRQ: | |
6503 | irq_poll_disable(&cq->iop); | |
6504 | irq_poll_enable(&cq->iop); | |
6505 | break; | |
6506 | case IB_POLL_WORKQUEUE: | |
6507 | cancel_work_sync(&cq->work); | |
6508 | break; | |
6509 | default: | |
6510 | WARN_ON_ONCE(1); | |
6511 | } | |
6512 | } | |
6513 | ||
6514 | /* Run the CQ handler - this makes sure that the drain WR will | |
6515 | * be processed if wasn't processed yet. | |
6516 | */ | |
4e0e2ea1 | 6517 | mcq->mcq.comp(&mcq->mcq, NULL); |
d0e84c0a YH |
6518 | } |
6519 | ||
6520 | wait_for_completion(&sdrain->done); | |
6521 | } | |
6522 | ||
6523 | void mlx5_ib_drain_sq(struct ib_qp *qp) | |
6524 | { | |
6525 | struct ib_cq *cq = qp->send_cq; | |
6526 | struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; | |
6527 | struct mlx5_ib_drain_cqe sdrain; | |
d34ac5cd | 6528 | const struct ib_send_wr *bad_swr; |
d0e84c0a YH |
6529 | struct ib_rdma_wr swr = { |
6530 | .wr = { | |
6531 | .next = NULL, | |
6532 | { .wr_cqe = &sdrain.cqe, }, | |
6533 | .opcode = IB_WR_RDMA_WRITE, | |
6534 | }, | |
6535 | }; | |
6536 | int ret; | |
6537 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
6538 | struct mlx5_core_dev *mdev = dev->mdev; | |
6539 | ||
6540 | ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | |
6541 | if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
6542 | WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); | |
6543 | return; | |
6544 | } | |
6545 | ||
6546 | sdrain.cqe.done = mlx5_ib_drain_qp_done; | |
6547 | init_completion(&sdrain.done); | |
6548 | ||
6549 | ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); | |
6550 | if (ret) { | |
6551 | WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); | |
6552 | return; | |
6553 | } | |
6554 | ||
6555 | handle_drain_completion(cq, &sdrain, dev); | |
6556 | } | |
6557 | ||
6558 | void mlx5_ib_drain_rq(struct ib_qp *qp) | |
6559 | { | |
6560 | struct ib_cq *cq = qp->recv_cq; | |
6561 | struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; | |
6562 | struct mlx5_ib_drain_cqe rdrain; | |
d34ac5cd BVA |
6563 | struct ib_recv_wr rwr = {}; |
6564 | const struct ib_recv_wr *bad_rwr; | |
d0e84c0a YH |
6565 | int ret; |
6566 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
6567 | struct mlx5_core_dev *mdev = dev->mdev; | |
6568 | ||
6569 | ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | |
6570 | if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
6571 | WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); | |
6572 | return; | |
6573 | } | |
6574 | ||
6575 | rwr.wr_cqe = &rdrain.cqe; | |
6576 | rdrain.cqe.done = mlx5_ib_drain_qp_done; | |
6577 | init_completion(&rdrain.done); | |
6578 | ||
6579 | ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); | |
6580 | if (ret) { | |
6581 | WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); | |
6582 | return; | |
6583 | } | |
6584 | ||
6585 | handle_drain_completion(cq, &rdrain, dev); | |
6586 | } | |
d14133dd MZ |
6587 | |
6588 | /** | |
6589 | * Bind a qp to a counter. If @counter is NULL then bind the qp to | |
6590 | * the default counter | |
6591 | */ | |
6592 | int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter) | |
6593 | { | |
10189e8e | 6594 | struct mlx5_ib_dev *dev = to_mdev(qp->device); |
d14133dd MZ |
6595 | struct mlx5_ib_qp *mqp = to_mqp(qp); |
6596 | int err = 0; | |
6597 | ||
6598 | mutex_lock(&mqp->mutex); | |
6599 | if (mqp->state == IB_QPS_RESET) { | |
6600 | qp->counter = counter; | |
6601 | goto out; | |
6602 | } | |
6603 | ||
10189e8e MZ |
6604 | if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) { |
6605 | err = -EOPNOTSUPP; | |
6606 | goto out; | |
6607 | } | |
6608 | ||
d14133dd MZ |
6609 | if (mqp->state == IB_QPS_RTS) { |
6610 | err = __mlx5_ib_qp_set_counter(qp, counter); | |
6611 | if (!err) | |
6612 | qp->counter = counter; | |
6613 | ||
6614 | goto out; | |
6615 | } | |
6616 | ||
6617 | mqp->counter_pending = 1; | |
6618 | qp->counter = counter; | |
6619 | ||
6620 | out: | |
6621 | mutex_unlock(&mqp->mutex); | |
6622 | return err; | |
6623 | } |