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RDMA/core: Fix return error value in _ib_modify_qp() to negative
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
d14133dd 37#include <rdma/rdma_counter.h>
c2e53b2c 38#include <linux/mlx5/fs.h>
e126ba97 39#include "mlx5_ib.h"
b96c9dde 40#include "ib_rep.h"
64825827 41#include "counters.h"
443c1cf9 42#include "cmd.h"
333fbaa0 43#include "qp.h"
029e88fd 44#include "wr.h"
e126ba97 45
e126ba97
EC		 46enum {
47 MLX5_IB_ACK_REQ_FREQ = 8,
48};
49
50enum {
51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
53 MLX5_IB_LINK_TYPE_IB = 0,
54 MLX5_IB_LINK_TYPE_ETH = 1
55};
56
eb49ab0c
AV		 57enum raw_qp_set_mask_map {
58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 60};
61
0680efa2
AV		 62struct mlx5_modify_raw_qp_param {
63 u16 operation;
eb49ab0c
AV		 64
65 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 66
67 struct mlx5_rate_limit rl;
68
eb49ab0c 69 u8 rq_q_ctr_id;
d5ed8ac3 70 u16 port;
0680efa2
AV		 71};
72
89ea94a7
MG		 73static void get_cqs(enum ib_qp_type qp_type,
74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
76
e126ba97
EC		 77static int is_qp0(enum ib_qp_type qp_type)
78{
79 return qp_type == IB_QPT_SMI;
80}
81
e126ba97
EC		 82static int is_sqp(enum ib_qp_type qp_type)
83{
84 return is_qp0(qp_type) || is_qp1(qp_type);
85}
86
c1395a2a 87/**
fbeb4075
MS		 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
89 * to kernel buffer
c1395a2a 90 *
fbeb4075
MS		 91 * @umem: User space memory where the WQ is
92 * @buffer: buffer to copy to
93 * @buflen: buffer length
94 * @wqe_index: index of WQE to copy from
95 * @wq_offset: offset to start of WQ
96 * @wq_wqe_cnt: number of WQEs in WQ
97 * @wq_wqe_shift: log2 of WQE size
98 * @bcnt: number of bytes to copy
99 * @bytes_copied: number of bytes to copy (return value)
c1395a2a 100 *
fbeb4075
MS		 101 * Copies from start of WQE bcnt or less bytes.
102 * Does not gurantee to copy the entire WQE.
c1395a2a 103 *
fbeb4075 104 * Return: zero on success, or an error code.
c1395a2a 105 */
da9ee9d8
MS		 106static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
107 size_t buflen, int wqe_index,
108 int wq_offset, int wq_wqe_cnt,
109 int wq_wqe_shift, int bcnt,
fbeb4075 110 size_t *bytes_copied)
c1395a2a 111{
fbeb4075
MS		 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
114 size_t copy_length;
c1395a2a
HE		 115 int ret;
116
fbeb4075
MS		 117 /* don't copy more than requested, more than buffer length or
118 * beyond WQ end
119 */
120 copy_length = min_t(u32, buflen, wq_end - offset);
121 copy_length = min_t(u32, copy_length, bcnt);
122
123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
124 if (ret)
125 return ret;
c1395a2a 126
fbeb4075
MS		 127 if (!ret && bytes_copied)
128 *bytes_copied = copy_length;
c1395a2a 129
fbeb4075
MS		 130 return 0;
131}
c1395a2a 132
da9ee9d8
MS		 133static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
134 void *buffer, size_t buflen, size_t *bc)
135{
136 struct mlx5_wqe_ctrl_seg *ctrl;
137 size_t bytes_copied = 0;
138 size_t wqe_length;
139 void *p;
140 int ds;
141
142 wqe_index = wqe_index & qp->sq.fbc.sz_m1;
143
144 /* read the control segment first */
145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
146 ctrl = p;
147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
148 wqe_length = ds * MLX5_WQE_DS_UNITS;
149
150 /* read rest of WQE if it spreads over more than one stride */
151 while (bytes_copied < wqe_length) {
152 size_t copy_length =
153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
154
155 if (!copy_length)
156 break;
157
158 memcpy(buffer + bytes_copied, p, copy_length);
159 bytes_copied += copy_length;
160
161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
163 }
164 *bc = bytes_copied;
165 return 0;
166}
167
168static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
169 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 170{
171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
172 struct ib_umem *umem = base->ubuffer.umem;
173 struct mlx5_ib_wq *wq = &qp->sq;
174 struct mlx5_wqe_ctrl_seg *ctrl;
175 size_t bytes_copied;
176 size_t bytes_copied2;
177 size_t wqe_length;
178 int ret;
179 int ds;
180
fbeb4075 181 /* at first read as much as possible */
da9ee9d8
MS		 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
183 wq->offset, wq->wqe_cnt,
184 wq->wqe_shift, buflen,
fbeb4075 185 &bytes_copied);
c1395a2a
HE		 186 if (ret)
187 return ret;
188
fbeb4075
MS		 189 /* we need at least control segment size to proceed */
190 if (bytes_copied < sizeof(*ctrl))
191 return -EINVAL;
192
193 ctrl = buffer;
194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
195 wqe_length = ds * MLX5_WQE_DS_UNITS;
c1395a2a 196
fbeb4075
MS		 197 /* if we copied enough then we are done */
198 if (bytes_copied >= wqe_length) {
199 *bc = bytes_copied;
200 return 0;
c1395a2a
HE		 201 }
202
fbeb4075
MS		 203 /* otherwise this a wrapped around wqe
204 * so read the remaining bytes starting
205 * from wqe_index 0
206 */
da9ee9d8
MS		 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
208 buflen - bytes_copied, 0, wq->offset,
209 wq->wqe_cnt, wq->wqe_shift,
fbeb4075
MS		 210 wqe_length - bytes_copied,
211 &bytes_copied2);
212
213 if (ret)
214 return ret;
215 *bc = bytes_copied + bytes_copied2;
216 return 0;
217}
218
da9ee9d8
MS		 219int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
220 size_t buflen, size_t *bc)
221{
222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
223 struct ib_umem *umem = base->ubuffer.umem;
224
225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
226 return -EINVAL;
227
228 if (!umem)
229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
230 buflen, bc);
231
232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
233}
234
235static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
236 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 237{
238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
239 struct ib_umem *umem = base->ubuffer.umem;
240 struct mlx5_ib_wq *wq = &qp->rq;
241 size_t bytes_copied;
242 int ret;
243
da9ee9d8
MS		 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
245 wq->offset, wq->wqe_cnt,
246 wq->wqe_shift, buflen,
fbeb4075 247 &bytes_copied);
c1395a2a 248
c1395a2a
HE		 249 if (ret)
250 return ret;
fbeb4075
MS		 251 *bc = bytes_copied;
252 return 0;
253}
254
da9ee9d8
MS		 255int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
256 size_t buflen, size_t *bc)
257{
258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
259 struct ib_umem *umem = base->ubuffer.umem;
260 struct mlx5_ib_wq *wq = &qp->rq;
261 size_t wqe_size = 1 << wq->wqe_shift;
262
263 if (buflen < wqe_size)
264 return -EINVAL;
265
266 if (!umem)
267 return -EOPNOTSUPP;
268
269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
270}
271
272static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
273 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 274{
275 struct ib_umem *umem = srq->umem;
276 size_t bytes_copied;
277 int ret;
c1395a2a 278
da9ee9d8
MS		 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
280 srq->msrq.max, srq->msrq.wqe_shift,
281 buflen, &bytes_copied);
fbeb4075
MS		 282
283 if (ret)
284 return ret;
285 *bc = bytes_copied;
286 return 0;
c1395a2a
HE		 287}
288
da9ee9d8
MS		 289int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
290 size_t buflen, size_t *bc)
291{
292 struct ib_umem *umem = srq->umem;
293 size_t wqe_size = 1 << srq->msrq.wqe_shift;
294
295 if (buflen < wqe_size)
296 return -EINVAL;
297
298 if (!umem)
299 return -EOPNOTSUPP;
300
301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
302}
303
e126ba97
EC		 304static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
305{
306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
307 struct ib_event event;
308
19098df2 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
310 /* This event is only valid for trans_qps */
311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
312 }
e126ba97
EC		 313
314 if (ibqp->event_handler) {
315 event.device = ibqp->device;
316 event.element.qp = ibqp;
317 switch (type) {
318 case MLX5_EVENT_TYPE_PATH_MIG:
319 event.event = IB_EVENT_PATH_MIG;
320 break;
321 case MLX5_EVENT_TYPE_COMM_EST:
322 event.event = IB_EVENT_COMM_EST;
323 break;
324 case MLX5_EVENT_TYPE_SQ_DRAINED:
325 event.event = IB_EVENT_SQ_DRAINED;
326 break;
327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
328 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
329 break;
330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
331 event.event = IB_EVENT_QP_FATAL;
332 break;
333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
334 event.event = IB_EVENT_PATH_MIG_ERR;
335 break;
336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
337 event.event = IB_EVENT_QP_REQ_ERR;
338 break;
339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
340 event.event = IB_EVENT_QP_ACCESS_ERR;
341 break;
342 default:
343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
344 return;
345 }
346
347 ibqp->event_handler(&event, ibqp->qp_context);
348 }
349}
350
351static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
353{
354 int wqe_size;
355 int wq_size;
356
357 /* Sanity check RQ size before proceeding */
938fe83c 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 359 return -EINVAL;
360
361 if (!has_rq) {
362 qp->rq.max_gs = 0;
363 qp->rq.wqe_cnt = 0;
364 qp->rq.wqe_shift = 0;
0540d814
NO		 365 cap->max_recv_wr = 0;
366 cap->max_recv_sge = 0;
e126ba97 367 } else {
c95e6d53
LR		 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
369
e126ba97
EC		 370 if (ucmd) {
371 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
002bf228
LR		 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
373 return -EINVAL;
e126ba97 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
c95e6d53
LR		 375 if ((1 << qp->rq.wqe_shift) /
376 sizeof(struct mlx5_wqe_data_seg) <
377 wq_sig)
002bf228 378 return -EINVAL;
c95e6d53
LR		 379 qp->rq.max_gs =
380 (1 << qp->rq.wqe_shift) /
381 sizeof(struct mlx5_wqe_data_seg) -
382 wq_sig;
e126ba97
EC		 383 qp->rq.max_post = qp->rq.wqe_cnt;
384 } else {
c95e6d53
LR		 385 wqe_size =
386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
387 0;
e126ba97
EC		 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
389 wqe_size = roundup_pow_of_two(wqe_size);
390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
392 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
395 wqe_size,
938fe83c
SM		 396 MLX5_CAP_GEN(dev->mdev,
397 max_wqe_sz_rq));
e126ba97
EC		 398 return -EINVAL;
399 }
400 qp->rq.wqe_shift = ilog2(wqe_size);
c95e6d53
LR		 401 qp->rq.max_gs =
402 (1 << qp->rq.wqe_shift) /
403 sizeof(struct mlx5_wqe_data_seg) -
404 wq_sig;
e126ba97
EC		 405 qp->rq.max_post = qp->rq.wqe_cnt;
406 }
407 }
408
409 return 0;
410}
411
f0313965 412static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 413{
618af384 414 int size = 0;
e126ba97 415
f0313965 416 switch (attr->qp_type) {
e126ba97 417 case IB_QPT_XRC_INI:
b125a54b 418 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 419 /* fall through */
420 case IB_QPT_RC:
421 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 422 max(sizeof(struct mlx5_wqe_atomic_seg) +
423 sizeof(struct mlx5_wqe_raddr_seg),
424 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
064e5262
IB		 425 sizeof(struct mlx5_mkey_seg) +
426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
427 MLX5_IB_UMR_OCTOWORD);
e126ba97
EC		 428 break;
429
b125a54b
EC		 430 case IB_QPT_XRC_TGT:
431 return 0;
432
e126ba97 433 case IB_QPT_UC:
b125a54b 434 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 435 max(sizeof(struct mlx5_wqe_raddr_seg),
436 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
437 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 438 break;
439
440 case IB_QPT_UD:
f0313965
ES		 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
442 size += sizeof(struct mlx5_wqe_eth_pad) +
443 sizeof(struct mlx5_wqe_eth_seg);
444 /* fall through */
e126ba97 445 case IB_QPT_SMI:
d16e91da 446 case MLX5_IB_QPT_HW_GSI:
b125a54b 447 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 448 sizeof(struct mlx5_wqe_datagram_seg);
449 break;
450
451 case MLX5_IB_QPT_REG_UMR:
b125a54b 452 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
454 sizeof(struct mlx5_mkey_seg);
455 break;
456
457 default:
458 return -EINVAL;
459 }
460
461 return size;
462}
463
464static int calc_send_wqe(struct ib_qp_init_attr *attr)
465{
466 int inl_size = 0;
467 int size;
468
f0313965 469 size = sq_overhead(attr);
e126ba97
EC		 470 if (size < 0)
471 return size;
472
473 if (attr->cap.max_inline_data) {
474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
475 attr->cap.max_inline_data;
476 }
477
478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
c0a6cbb9 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
e1e66cc2 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
c0a6cbb9 481 return MLX5_SIG_WQE_SIZE;
e1e66cc2
SG		 482 else
483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 484}
485
288c01b7
EC		 486static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
487{
488 int max_sge;
489
490 if (attr->qp_type == IB_QPT_RC)
491 max_sge = (min_t(int, wqe_size, 512) -
492 sizeof(struct mlx5_wqe_ctrl_seg) -
493 sizeof(struct mlx5_wqe_raddr_seg)) /
494 sizeof(struct mlx5_wqe_data_seg);
495 else if (attr->qp_type == IB_QPT_XRC_INI)
496 max_sge = (min_t(int, wqe_size, 512) -
497 sizeof(struct mlx5_wqe_ctrl_seg) -
498 sizeof(struct mlx5_wqe_xrc_seg) -
499 sizeof(struct mlx5_wqe_raddr_seg)) /
500 sizeof(struct mlx5_wqe_data_seg);
501 else
502 max_sge = (wqe_size - sq_overhead(attr)) /
503 sizeof(struct mlx5_wqe_data_seg);
504
505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
506 sizeof(struct mlx5_wqe_data_seg));
507}
508
e126ba97
EC		 509static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
510 struct mlx5_ib_qp *qp)
511{
512 int wqe_size;
513 int wq_size;
514
515 if (!attr->cap.max_send_wr)
516 return 0;
517
518 wqe_size = calc_send_wqe(attr);
519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
520 if (wqe_size < 0)
521 return wqe_size;
522
938fe83c 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 526 return -EINVAL;
527 }
528
f0313965
ES		 529 qp->max_inline_data = wqe_size - sq_overhead(attr) -
530 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 531 attr->cap.max_inline_data = qp->max_inline_data;
532
533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 538 qp->sq.wqe_cnt,
539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 540 return -ENOMEM;
541 }
e126ba97 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 543 qp->sq.max_gs = get_send_sge(attr, wqe_size);
544 if (qp->sq.max_gs < attr->cap.max_send_sge)
545 return -ENOMEM;
546
547 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 548 qp->sq.max_post = wq_size / wqe_size;
549 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 550
551 return wq_size;
552}
553
554static int set_user_buf_size(struct mlx5_ib_dev *dev,
555 struct mlx5_ib_qp *qp,
19098df2 556 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 557 struct mlx5_ib_qp_base *base,
558 struct ib_qp_init_attr *attr)
e126ba97
EC		 559{
560 int desc_sz = 1 << qp->sq.wqe_shift;
561
938fe83c 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 565 return -EINVAL;
566 }
567
af8b38ed
GP		 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
570 ucmd->sq_wqe_count);
e126ba97
EC		 571 return -EINVAL;
572 }
573
574 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
575
938fe83c 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 578 qp->sq.wqe_cnt,
579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 580 return -EINVAL;
581 }
582
c2e53b2c 583 if (attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0fb2ed66 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
587 } else {
588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
589 (qp->sq.wqe_cnt << 6);
590 }
e126ba97
EC		 591
592 return 0;
593}
594
595static int qp_has_rq(struct ib_qp_init_attr *attr)
596{
597 if (attr->qp_type == IB_QPT_XRC_INI ||
598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
599 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
600 !attr->cap.max_recv_wr)
601 return 0;
602
603 return 1;
604}
605
0b80c14f
EC		 606enum {
607 /* this is the first blue flame register in the array of bfregs assigned
608 * to a processes. Since we do not use it for blue flame but rather
609 * regular 64 bit doorbells, we do not need a lock for maintaiing
610 * "odd/even" order
611 */
612 NUM_NON_BLUE_FLAME_BFREGS = 1,
613};
614
b037c29a
EC		 615static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
616{
31a78a5a 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 618}
619
620static int num_med_bfreg(struct mlx5_ib_dev *dev,
621 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 622{
623 int n;
624
b037c29a
EC		 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
626 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 627
628 return n >= 0 ? n : 0;
629}
630
18b0362e
YH		 631static int first_med_bfreg(struct mlx5_ib_dev *dev,
632 struct mlx5_bfreg_info *bfregi)
633{
634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
635}
636
b037c29a
EC		 637static int first_hi_bfreg(struct mlx5_ib_dev *dev,
638 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 639{
640 int med;
c1be5232 641
b037c29a
EC		 642 med = num_med_bfreg(dev, bfregi);
643 return ++med;
c1be5232
EC		 644}
645
b037c29a
EC		 646static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
647 struct mlx5_bfreg_info *bfregi)
e126ba97 648{
e126ba97
EC		 649 int i;
650
b037c29a
EC		 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
652 if (!bfregi->count[i]) {
2f5ff264 653 bfregi->count[i]++;
e126ba97
EC		 654 return i;
655 }
656 }
657
658 return -ENOMEM;
659}
660
b037c29a
EC		 661static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
662 struct mlx5_bfreg_info *bfregi)
e126ba97 663{
18b0362e 664 int minidx = first_med_bfreg(dev, bfregi);
e126ba97
EC		 665 int i;
666
18b0362e
YH		 667 if (minidx < 0)
668 return minidx;
669
670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 671 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 672 minidx = i;
0b80c14f
EC		 673 if (!bfregi->count[minidx])
674 break;
e126ba97
EC		 675 }
676
2f5ff264 677 bfregi->count[minidx]++;
e126ba97
EC		 678 return minidx;
679}
680
b037c29a 681static int alloc_bfreg(struct mlx5_ib_dev *dev,
ffaf58de 682 struct mlx5_bfreg_info *bfregi)
e126ba97 683{
ffaf58de 684 int bfregn = -ENOMEM;
e126ba97 685
0a2fd01c
YH		 686 if (bfregi->lib_uar_dyn)
687 return -EINVAL;
688
2f5ff264 689 mutex_lock(&bfregi->lock);
ffaf58de
LR		 690 if (bfregi->ver >= 2) {
691 bfregn = alloc_high_class_bfreg(dev, bfregi);
692 if (bfregn < 0)
693 bfregn = alloc_med_class_bfreg(dev, bfregi);
694 }
695
696 if (bfregn < 0) {
0b80c14f 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 698 bfregn = 0;
699 bfregi->count[bfregn]++;
e126ba97 700 }
2f5ff264 701 mutex_unlock(&bfregi->lock);
e126ba97 702
2f5ff264 703 return bfregn;
e126ba97
EC		 704}
705
4ed131d0 706void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 707{
2f5ff264 708 mutex_lock(&bfregi->lock);
b037c29a 709 bfregi->count[bfregn]--;
2f5ff264 710 mutex_unlock(&bfregi->lock);
e126ba97
EC		 711}
712
713static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
714{
715 switch (state) {
716 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
723 default: return -1;
724 }
725}
726
727static int to_mlx5_st(enum ib_qp_type type)
728{
729 switch (type) {
730 case IB_QPT_RC: return MLX5_QP_ST_RC;
731 case IB_QPT_UC: return MLX5_QP_ST_UC;
732 case IB_QPT_UD: return MLX5_QP_ST_UD;
733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
734 case IB_QPT_XRC_INI:
735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
736 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
3ae7e66a 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 740 default: return -EINVAL;
741 }
742}
743
89ea94a7
MG		 744static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
745 struct mlx5_ib_cq *recv_cq);
746static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
747 struct mlx5_ib_cq *recv_cq);
748
7c043e90 749int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
05f58ceb 750 struct mlx5_bfreg_info *bfregi, u32 bfregn,
7c043e90 751 bool dyn_bfreg)
e126ba97 752{
05f58ceb
LR		 753 unsigned int bfregs_per_sys_page;
754 u32 index_of_sys_page;
755 u32 offset;
b037c29a 756
0a2fd01c
YH		 757 if (bfregi->lib_uar_dyn)
758 return -EINVAL;
759
b037c29a
EC		 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
761 MLX5_NON_FP_BFREGS_PER_UAR;
762 index_of_sys_page = bfregn / bfregs_per_sys_page;
763
1ee47ab3
YH		 764 if (dyn_bfreg) {
765 index_of_sys_page += bfregi->num_static_sys_pages;
05f58ceb
LR		 766
767 if (index_of_sys_page >= bfregi->num_sys_pages)
768 return -EINVAL;
769
1ee47ab3
YH		 770 if (bfregn > bfregi->num_dyn_bfregs ||
771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
773 return -EINVAL;
774 }
775 }
b037c29a 776
1ee47ab3 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 778 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 779}
780
b0ea0fa5 781static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
19098df2 782 unsigned long addr, size_t size,
b0ea0fa5
JG		 783 struct ib_umem **umem, int *npages, int *page_shift,
784 int *ncont, u32 *offset)
19098df2 785{
786 int err;
787
c320e527 788 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
19098df2 789 if (IS_ERR(*umem)) {
790 mlx5_ib_dbg(dev, "umem_get failed\n");
791 return PTR_ERR(*umem);
792 }
793
762f899a 794 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 795
796 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
797 if (err) {
798 mlx5_ib_warn(dev, "bad offset\n");
799 goto err_umem;
800 }
801
802 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
803 addr, size, *npages, *page_shift, *ncont, *offset);
804
805 return 0;
806
807err_umem:
808 ib_umem_release(*umem);
809 *umem = NULL;
810
811 return err;
812}
813
fe248c3a 814static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
bdeacabd 815 struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
79b20a6c 816{
bdeacabd
SR		 817 struct mlx5_ib_ucontext *context =
818 rdma_udata_to_drv_context(
819 udata,
820 struct mlx5_ib_ucontext,
821 ibucontext);
79b20a6c 822
fe248c3a
MG		 823 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
824 atomic_dec(&dev->delay_drop.rqs_cnt);
825
79b20a6c 826 mlx5_ib_db_unmap_user(context, &rwq->db);
836a0fbb 827 ib_umem_release(rwq->umem);
79b20a6c
YH		 828}
829
830static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
b0ea0fa5 831 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
79b20a6c
YH		 832 struct mlx5_ib_create_wq *ucmd)
833{
89944450
SR		 834 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
835 udata, struct mlx5_ib_ucontext, ibucontext);
79b20a6c
YH		 836 int page_shift = 0;
837 int npages;
838 u32 offset = 0;
839 int ncont = 0;
840 int err;
841
842 if (!ucmd->buf_addr)
843 return -EINVAL;
844
c320e527 845 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
79b20a6c
YH		 846 if (IS_ERR(rwq->umem)) {
847 mlx5_ib_dbg(dev, "umem_get failed\n");
848 err = PTR_ERR(rwq->umem);
849 return err;
850 }
851
762f899a 852 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 853 &ncont, NULL);
854 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
855 &rwq->rq_page_offset);
856 if (err) {
857 mlx5_ib_warn(dev, "bad offset\n");
858 goto err_umem;
859 }
860
861 rwq->rq_num_pas = ncont;
862 rwq->page_shift = page_shift;
863 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
864 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
865
866 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
867 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
868 npages, page_shift, ncont, offset);
869
89944450 870 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
79b20a6c
YH		 871 if (err) {
872 mlx5_ib_dbg(dev, "map failed\n");
873 goto err_umem;
874 }
875
79b20a6c
YH		 876 return 0;
877
878err_umem:
879 ib_umem_release(rwq->umem);
880 return err;
881}
882
b037c29a
EC		 883static int adjust_bfregn(struct mlx5_ib_dev *dev,
884 struct mlx5_bfreg_info *bfregi, int bfregn)
885{
886 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
887 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
888}
889
98fc1126
LR		 890static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
891 struct mlx5_ib_qp *qp, struct ib_udata *udata,
892 struct ib_qp_init_attr *attr, u32 **in,
893 struct mlx5_ib_create_qp_resp *resp, int *inlen,
894 struct mlx5_ib_qp_base *base,
895 struct mlx5_ib_create_qp *ucmd)
e126ba97
EC		 896{
897 struct mlx5_ib_ucontext *context;
19098df2 898 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 899 int page_shift = 0;
1ee47ab3 900 int uar_index = 0;
e126ba97 901 int npages;
9e9c47d0 902 u32 offset = 0;
2f5ff264 903 int bfregn;
9e9c47d0 904 int ncont = 0;
09a7d9ec
SM		 905 __be64 *pas;
906 void *qpc;
e126ba97 907 int err;
5aa3771d 908 u16 uid;
ac42a5ee 909 u32 uar_flags;
e126ba97 910
89944450
SR		 911 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
912 ibucontext);
76883a6c
LR		 913 uar_flags = qp->flags_en &
914 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
ac42a5ee
YH		 915 switch (uar_flags) {
916 case MLX5_QP_FLAG_UAR_PAGE_INDEX:
76883a6c 917 uar_index = ucmd->bfreg_index;
ac42a5ee
YH		 918 bfregn = MLX5_IB_INVALID_BFREG;
919 break;
920 case MLX5_QP_FLAG_BFREG_INDEX:
1ee47ab3 921 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
76883a6c 922 ucmd->bfreg_index, true);
1ee47ab3
YH		 923 if (uar_index < 0)
924 return uar_index;
1ee47ab3 925 bfregn = MLX5_IB_INVALID_BFREG;
ac42a5ee
YH		 926 break;
927 case 0:
2be08c30 928 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
ac42a5ee 929 return -EINVAL;
ffaf58de
LR		 930 bfregn = alloc_bfreg(dev, &context->bfregi);
931 if (bfregn < 0)
932 return bfregn;
ac42a5ee
YH		 933 break;
934 default:
935 return -EINVAL;
e126ba97
EC		 936 }
937
2f5ff264 938 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 939 if (bfregn != MLX5_IB_INVALID_BFREG)
940 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
941 false);
e126ba97 942
48fea837
HE		 943 qp->rq.offset = 0;
944 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
945 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
946
76883a6c 947 err = set_user_buf_size(dev, qp, ucmd, base, attr);
e126ba97 948 if (err)
2f5ff264 949 goto err_bfreg;
e126ba97 950
76883a6c
LR		 951 if (ucmd->buf_addr && ubuffer->buf_size) {
952 ubuffer->buf_addr = ucmd->buf_addr;
b0ea0fa5
JG		 953 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
954 ubuffer->buf_size, &ubuffer->umem,
955 &npages, &page_shift, &ncont, &offset);
19098df2 956 if (err)
2f5ff264 957 goto err_bfreg;
9e9c47d0 958 } else {
19098df2 959 ubuffer->umem = NULL;
e126ba97 960 }
e126ba97 961
09a7d9ec
SM		 962 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
963 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 964 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 965 if (!*in) {
966 err = -ENOMEM;
967 goto err_umem;
968 }
09a7d9ec 969
04bcc1c2 970 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
5aa3771d 971 MLX5_SET(create_qp_in, *in, uid, uid);
09a7d9ec 972 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 973 if (ubuffer->umem)
09a7d9ec
SM		 974 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
975
976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
977
978 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
979 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 980
09a7d9ec 981 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 982 if (bfregn != MLX5_IB_INVALID_BFREG)
983 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
984 else
985 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 986 qp->bfregn = bfregn;
e126ba97 987
76883a6c 988 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
e126ba97
EC		 989 if (err) {
990 mlx5_ib_dbg(dev, "map failed\n");
991 goto err_free;
992 }
993
e126ba97
EC		 994 return 0;
995
e126ba97 996err_free:
479163f4 997 kvfree(*in);
e126ba97
EC		 998
999err_umem:
836a0fbb 1000 ib_umem_release(ubuffer->umem);
e126ba97 1001
2f5ff264 1002err_bfreg:
1ee47ab3
YH		 1003 if (bfregn != MLX5_IB_INVALID_BFREG)
1004 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 1005 return err;
1006}
1007
747c519c
LR		 1008static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1009 struct mlx5_ib_qp_base *base, struct ib_udata *udata)
e126ba97 1010{
747c519c
LR		 1011 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1012 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 1013
747c519c
LR		 1014 if (udata) {
1015 /* User QP */
1016 mlx5_ib_db_unmap_user(context, &qp->db);
1017 ib_umem_release(base->ubuffer.umem);
1018
1019 /*
1020 * Free only the BFREGs which are handled by the kernel.
1021 * BFREGs of UARs allocated dynamically are handled by user.
1022 */
1023 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1024 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1025 return;
1026 }
1ee47ab3 1027
747c519c
LR		 1028 /* Kernel QP */
1029 kvfree(qp->sq.wqe_head);
1030 kvfree(qp->sq.w_list);
1031 kvfree(qp->sq.wrid);
1032 kvfree(qp->sq.wr_data);
1033 kvfree(qp->rq.wrid);
1034 if (qp->db.db)
1035 mlx5_db_free(dev->mdev, &qp->db);
1036 if (qp->buf.frags)
1037 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1038}
1039
98fc1126
LR		 1040static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1041 struct ib_qp_init_attr *init_attr,
1042 struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1043 struct mlx5_ib_qp_base *base)
e126ba97 1044{
e126ba97 1045 int uar_index;
09a7d9ec 1046 void *qpc;
e126ba97
EC		 1047 int err;
1048
e126ba97 1049 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0 1050 qp->bf.bfreg = &dev->fp_bfreg;
2978975c 1051 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
11f552e2 1052 qp->bf.bfreg = &dev->wc_bfreg;
5fe9dec0
EC		 1053 else
1054 qp->bf.bfreg = &dev->bfreg;
e126ba97 1055
d8030b0d
EC		 1056 /* We need to divide by two since each register is comprised of
1057 * two buffers of identical size, namely odd and even
1058 */
1059 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 1060 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 1061
1062 err = calc_sq_size(dev, init_attr, qp);
1063 if (err < 0) {
1064 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 1065 return err;
e126ba97
EC		 1066 }
1067
1068 qp->rq.offset = 0;
1069 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 1070 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 1071
34f4c955
GL		 1072 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1073 &qp->buf, dev->mdev->priv.numa_node);
e126ba97
EC		 1074 if (err) {
1075 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 1076 return err;
e126ba97
EC		 1077 }
1078
34f4c955
GL		 1079 if (qp->rq.wqe_cnt)
1080 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1081 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1082
1083 if (qp->sq.wqe_cnt) {
1084 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
1085 MLX5_SEND_WQE_BB;
1086 mlx5_init_fbc_offset(qp->buf.frags +
1087 (qp->sq.offset / PAGE_SIZE),
1088 ilog2(MLX5_SEND_WQE_BB),
1089 ilog2(qp->sq.wqe_cnt),
1090 sq_strides_offset, &qp->sq.fbc);
1091
1092 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1093 }
1094
09a7d9ec
SM		 1095 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1096 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 1097 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 1098 if (!*in) {
1099 err = -ENOMEM;
1100 goto err_buf;
1101 }
09a7d9ec
SM		 1102
1103 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1104 MLX5_SET(qpc, qpc, uar_page, uar_index);
1105 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1106
e126ba97 1107 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 1108 MLX5_SET(qpc, qpc, fre, 1);
1109 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 1110
2978975c 1111 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
09a7d9ec 1112 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c 1113
34f4c955
GL		 1114 mlx5_fill_page_frag_array(&qp->buf,
1115 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1116 *in, pas));
e126ba97 1117
9603b61d 1118 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 1119 if (err) {
1120 mlx5_ib_dbg(dev, "err %d\n", err);
1121 goto err_free;
1122 }
1123
b5883008
LD		 1124 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1125 sizeof(*qp->sq.wrid), GFP_KERNEL);
1126 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1127 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1128 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1129 sizeof(*qp->rq.wrid), GFP_KERNEL);
1130 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1131 sizeof(*qp->sq.w_list), GFP_KERNEL);
1132 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1133 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1134
1135 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1136 !qp->sq.w_list || !qp->sq.wqe_head) {
1137 err = -ENOMEM;
1138 goto err_wrid;
1139 }
e126ba97
EC		 1140
1141 return 0;
1142
1143err_wrid:
b5883008
LD		 1144 kvfree(qp->sq.wqe_head);
1145 kvfree(qp->sq.w_list);
1146 kvfree(qp->sq.wrid);
1147 kvfree(qp->sq.wr_data);
1148 kvfree(qp->rq.wrid);
f4044dac 1149 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1150
1151err_free:
479163f4 1152 kvfree(*in);
e126ba97
EC		 1153
1154err_buf:
34f4c955 1155 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1156 return err;
1157}
1158
09a7d9ec 1159static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97 1160{
7aede1a2
LR		 1161 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1162 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
09a7d9ec 1163 return MLX5_SRQ_RQ;
e126ba97 1164 else if (!qp->has_rq)
09a7d9ec 1165 return MLX5_ZERO_LEN_RQ;
7aede1a2
LR		 1166
1167 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1168}
1169
0fb2ed66 1170static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1171 struct mlx5_ib_qp *qp,
1cd6dbd3
YH		 1172 struct mlx5_ib_sq *sq, u32 tdn,
1173 struct ib_pd *pd)
0fb2ed66 1174{
e0b4b472 1175 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
0fb2ed66 1176 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1177
1cd6dbd3 1178 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1179 MLX5_SET(tisc, tisc, transport_domain, tdn);
2be08c30 1180 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
c2e53b2c
YH		 1181 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1182
e0b4b472 1183 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
0fb2ed66 1184}
1185
1186static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1cd6dbd3 1187 struct mlx5_ib_sq *sq, struct ib_pd *pd)
0fb2ed66 1188{
1cd6dbd3 1189 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
0fb2ed66 1190}
1191
d5ed8ac3 1192static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
b96c9dde
MB		 1193{
1194 if (sq->flow_rule)
1195 mlx5_del_flow_rules(sq->flow_rule);
d5ed8ac3 1196 sq->flow_rule = NULL;
b96c9dde
MB		 1197}
1198
0fb2ed66 1199static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
b0ea0fa5 1200 struct ib_udata *udata,
0fb2ed66 1201 struct mlx5_ib_sq *sq, void *qpin,
1202 struct ib_pd *pd)
1203{
1204 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1205 __be64 *pas;
1206 void *in;
1207 void *sqc;
1208 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1209 void *wq;
1210 int inlen;
1211 int err;
1212 int page_shift = 0;
1213 int npages;
1214 int ncont = 0;
1215 u32 offset = 0;
1216
b0ea0fa5
JG		 1217 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1218 &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1219 &offset);
0fb2ed66 1220 if (err)
1221 return err;
1222
1223 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1224 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1225 if (!in) {
1226 err = -ENOMEM;
1227 goto err_umem;
1228 }
1229
c14003f0 1230 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1231 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1232 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1233 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1234 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1235 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1236 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1237 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1238 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1239 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1240 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1241 MLX5_CAP_ETH(dev->mdev, swp))
1242 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1243
1244 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1245 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1246 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1247 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1248 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1249 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1250 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1251 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1252 MLX5_SET(wq, wq, page_offset, offset);
1253
1254 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1255 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1256
333fbaa0 1257 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
0fb2ed66 1258
1259 kvfree(in);
1260
1261 if (err)
1262 goto err_umem;
1263
1264 return 0;
1265
1266err_umem:
1267 ib_umem_release(sq->ubuffer.umem);
1268 sq->ubuffer.umem = NULL;
1269
1270 return err;
1271}
1272
1273static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1274 struct mlx5_ib_sq *sq)
1275{
d5ed8ac3 1276 destroy_flow_rule_vport_sq(sq);
333fbaa0 1277 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
0fb2ed66 1278 ib_umem_release(sq->ubuffer.umem);
1279}
1280
2c292dbb 1281static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1282{
1283 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1284 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1285 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1286 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1287 u32 po_quanta = 1 << (log_page_size - 6);
1288 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1289 u32 page_size = 1 << log_page_size;
1290 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1291 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1292
1293 return rq_num_pas * sizeof(u64);
1294}
1295
1296static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb 1297 struct mlx5_ib_rq *rq, void *qpin,
34d57585 1298 size_t qpinlen, struct ib_pd *pd)
0fb2ed66 1299{
358e42ea 1300 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1301 __be64 *pas;
1302 __be64 *qp_pas;
1303 void *in;
1304 void *rqc;
1305 void *wq;
1306 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1307 size_t rq_pas_size = get_rq_pas_size(qpc);
1308 size_t inlen;
0fb2ed66 1309 int err;
2c292dbb
BP		 1310
1311 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1312 return -EINVAL;
0fb2ed66 1313
1314 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1315 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1316 if (!in)
1317 return -ENOMEM;
1318
34d57585 1319 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1320 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1321 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1322 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1323 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1324 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1325 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1326 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1327 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1328
2be08c30 1329 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
358e42ea
MD		 1330 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1331
0fb2ed66 1332 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1333 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1334 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1335 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1336 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1337 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1338 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1339 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1340 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1341 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1342
1343 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1344 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1345 memcpy(pas, qp_pas, rq_pas_size);
1346
333fbaa0 1347 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
0fb2ed66 1348
1349 kvfree(in);
1350
1351 return err;
1352}
1353
1354static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1355 struct mlx5_ib_rq *rq)
1356{
333fbaa0 1357 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
0fb2ed66 1358}
1359
0042f9e4
MB		 1360static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1361 struct mlx5_ib_rq *rq,
443c1cf9
YH		 1362 u32 qp_flags_en,
1363 struct ib_pd *pd)
0042f9e4
MB		 1364{
1365 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1366 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1367 mlx5_ib_disable_lb(dev, false, true);
443c1cf9 1368 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
0042f9e4
MB		 1369}
1370
0fb2ed66 1371static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb 1372 struct mlx5_ib_rq *rq, u32 tdn,
e0b4b472
LR		 1373 u32 *qp_flags_en, struct ib_pd *pd,
1374 u32 *out)
0fb2ed66 1375{
175edba8 1376 u8 lb_flag = 0;
0fb2ed66 1377 u32 *in;
1378 void *tirc;
1379 int inlen;
1380 int err;
1381
1382 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1383 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1384 if (!in)
1385 return -ENOMEM;
1386
443c1cf9 1387 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1388 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1389 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1390 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1391 MLX5_SET(tirc, tirc, transport_domain, tdn);
175edba8 1392 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb 1393 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1394
175edba8
MB		 1395 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1396 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1397
1398 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1399 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1400
6a4d00be 1401 if (dev->is_rep) {
175edba8
MB		 1402 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1403 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1404 }
1405
1406 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
e0b4b472
LR		 1407 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1408 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1f1d6abb 1409 rq->tirn = MLX5_GET(create_tir_out, out, tirn);
0042f9e4
MB		 1410 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1411 err = mlx5_ib_enable_lb(dev, false, true);
1412
1413 if (err)
443c1cf9 1414 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
0042f9e4 1415 }
0fb2ed66 1416 kvfree(in);
1417
1418 return err;
1419}
1420
0fb2ed66 1421static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1422 u32 *in, size_t inlen,
7f72052c
YH		 1423 struct ib_pd *pd,
1424 struct ib_udata *udata,
1425 struct mlx5_ib_create_qp_resp *resp)
0fb2ed66 1426{
1427 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1428 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1429 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
89944450
SR		 1430 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1431 udata, struct mlx5_ib_ucontext, ibucontext);
0fb2ed66 1432 int err;
1433 u32 tdn = mucontext->tdn;
7f72052c 1434 u16 uid = to_mpd(pd)->uid;
1f1d6abb 1435 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
0fb2ed66 1436
0eacc574
AL		 1437 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt)
1438 return -EINVAL;
0fb2ed66 1439 if (qp->sq.wqe_cnt) {
1cd6dbd3 1440 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
0fb2ed66 1441 if (err)
1442 return err;
1443
b0ea0fa5 1444 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
0fb2ed66 1445 if (err)
1446 goto err_destroy_tis;
1447
7f72052c
YH		 1448 if (uid) {
1449 resp->tisn = sq->tisn;
1450 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1451 resp->sqn = sq->base.mqp.qpn;
1452 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1453 }
1454
0fb2ed66 1455 sq->base.container_mibqp = qp;
1d31e9c0 1456 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1457 }
1458
1459 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1460 rq->base.container_mibqp = qp;
1461
2be08c30 1462 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
e4cc4fa7 1463 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
2be08c30 1464 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
b1383aa6 1465 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
34d57585 1466 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
0fb2ed66 1467 if (err)
1468 goto err_destroy_sq;
1469
e0b4b472
LR		 1470 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1471 out);
0fb2ed66 1472 if (err)
1473 goto err_destroy_rq;
7f72052c
YH		 1474
1475 if (uid) {
1476 resp->rqn = rq->base.mqp.qpn;
1477 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1478 resp->tirn = rq->tirn;
1479 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1f1d6abb
AL		 1480 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1481 resp->tir_icm_addr = MLX5_GET(
1482 create_tir_out, out, icm_address_31_0);
1483 resp->tir_icm_addr |=
1484 (u64)MLX5_GET(create_tir_out, out,
1485 icm_address_39_32)
1486 << 32;
1487 resp->tir_icm_addr |=
1488 (u64)MLX5_GET(create_tir_out, out,
1489 icm_address_63_40)
1490 << 40;
1491 resp->comp_mask |=
1492 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1493 }
7f72052c 1494 }
0fb2ed66 1495 }
1496
1497 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1498 rq->base.mqp.qpn;
0fb2ed66 1499 return 0;
1500
1501err_destroy_rq:
1502 destroy_raw_packet_qp_rq(dev, rq);
1503err_destroy_sq:
1504 if (!qp->sq.wqe_cnt)
1505 return err;
1506 destroy_raw_packet_qp_sq(dev, sq);
1507err_destroy_tis:
1cd6dbd3 1508 destroy_raw_packet_qp_tis(dev, sq, pd);
0fb2ed66 1509
1510 return err;
1511}
1512
1513static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1514 struct mlx5_ib_qp *qp)
1515{
1516 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1517 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1518 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1519
1520 if (qp->rq.wqe_cnt) {
443c1cf9 1521 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
0fb2ed66 1522 destroy_raw_packet_qp_rq(dev, rq);
1523 }
1524
1525 if (qp->sq.wqe_cnt) {
1526 destroy_raw_packet_qp_sq(dev, sq);
1cd6dbd3 1527 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
0fb2ed66 1528 }
1529}
1530
1531static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1532 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1533{
1534 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1535 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1536
1537 sq->sq = &qp->sq;
1538 rq->rq = &qp->rq;
1539 sq->doorbell = &qp->db;
1540 rq->doorbell = &qp->db;
1541}
1542
28d61370
YH		 1543static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1544{
0042f9e4
MB		 1545 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1546 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1547 mlx5_ib_disable_lb(dev, false, true);
443c1cf9
YH		 1548 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1549 to_mpd(qp->ibqp.pd)->uid);
28d61370
YH		 1550}
1551
f78d358c
LR		 1552struct mlx5_create_qp_params {
1553 struct ib_udata *udata;
1554 size_t inlen;
6f2cf76e 1555 size_t outlen;
e383085c 1556 size_t ucmd_size;
f78d358c
LR		 1557 void *ucmd;
1558 u8 is_rss_raw : 1;
1559 struct ib_qp_init_attr *attr;
1560 u32 uidx;
08d53976 1561 struct mlx5_ib_create_qp_resp resp;
f78d358c
LR		 1562};
1563
1564static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1565 struct mlx5_ib_qp *qp,
1566 struct mlx5_create_qp_params *params)
28d61370 1567{
f78d358c
LR		 1568 struct ib_qp_init_attr *init_attr = params->attr;
1569 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd;
1570 struct ib_udata *udata = params->udata;
89944450
SR		 1571 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1572 udata, struct mlx5_ib_ucontext, ibucontext);
28d61370 1573 int inlen;
1f1d6abb 1574 int outlen;
28d61370
YH		 1575 int err;
1576 u32 *in;
1f1d6abb 1577 u32 *out;
28d61370
YH		 1578 void *tirc;
1579 void *hfso;
1580 u32 selected_fields = 0;
2d93fc85 1581 u32 outer_l4;
28d61370 1582 u32 tdn = mucontext->tdn;
175edba8 1583 u8 lb_flag = 0;
28d61370 1584
5ce0592b 1585 if (ucmd->comp_mask) {
28d61370
YH		 1586 mlx5_ib_dbg(dev, "invalid comp mask\n");
1587 return -EOPNOTSUPP;
1588 }
1589
5ce0592b
LR		 1590 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1591 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
309fa347
MG		 1592 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1593 return -EOPNOTSUPP;
1594 }
1595
37518fa4 1596 if (dev->is_rep)
175edba8 1597 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
175edba8 1598
37518fa4
LR		 1599 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1600 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1601
1602 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
175edba8 1603 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
175edba8 1604
28d61370 1605 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1f1d6abb
AL		 1606 outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1607 in = kvzalloc(inlen + outlen, GFP_KERNEL);
28d61370
YH		 1608 if (!in)
1609 return -ENOMEM;
1610
1f1d6abb 1611 out = in + MLX5_ST_SZ_DW(create_tir_in);
443c1cf9 1612 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
28d61370
YH		 1613 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1614 MLX5_SET(tirc, tirc, disp_type,
1615 MLX5_TIRC_DISP_TYPE_INDIRECT);
1616 MLX5_SET(tirc, tirc, indirect_table,
1617 init_attr->rwq_ind_tbl->ind_tbl_num);
1618 MLX5_SET(tirc, tirc, transport_domain, tdn);
1619
1620 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb 1621
5ce0592b 1622 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb
MG		 1623 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1624
175edba8
MB		 1625 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1626
5ce0592b 1627 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
309fa347
MG		 1628 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1629 else
1630 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1631
5ce0592b 1632 switch (ucmd->rx_hash_function) {
28d61370
YH		 1633 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1634 {
1635 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1636 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1637
5ce0592b 1638 if (len != ucmd->rx_key_len) {
28d61370
YH		 1639 err = -EINVAL;
1640 goto err;
1641 }
1642
1643 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
5ce0592b 1644 memcpy(rss_key, ucmd->rx_hash_key, len);
28d61370
YH		 1645 break;
1646 }
1647 default:
1648 err = -EOPNOTSUPP;
1649 goto err;
1650 }
1651
5ce0592b 1652 if (!ucmd->rx_hash_fields_mask) {
28d61370
YH		 1653 /* special case when this TIR serves as steering entry without hashing */
1654 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1655 goto create_tir;
1656 err = -EINVAL;
1657 goto err;
1658 }
1659
5ce0592b
LR		 1660 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1661 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1662 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1663 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
28d61370
YH		 1664 err = -EINVAL;
1665 goto err;
1666 }
1667
1668 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
5ce0592b
LR		 1669 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1670 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
28d61370
YH		 1671 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1672 MLX5_L3_PROT_TYPE_IPV4);
5ce0592b
LR		 1673 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1674 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
28d61370
YH		 1675 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1676 MLX5_L3_PROT_TYPE_IPV6);
1677
5ce0592b
LR		 1678 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1679 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1680 << 0 |
1681 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1682 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1683 << 1 |
1684 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
2d93fc85
MB		 1685
1686 /* Check that only one l4 protocol is set */
1687 if (outer_l4 & (outer_l4 - 1)) {
28d61370
YH		 1688 err = -EINVAL;
1689 goto err;
1690 }
1691
1692 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
5ce0592b
LR		 1693 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1694 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
28d61370
YH		 1695 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1696 MLX5_L4_PROT_TYPE_TCP);
5ce0592b
LR		 1697 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1698 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
28d61370
YH		 1699 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1700 MLX5_L4_PROT_TYPE_UDP);
1701
5ce0592b
LR		 1702 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1703 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
28d61370
YH		 1704 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1705
5ce0592b
LR		 1706 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1707 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
28d61370
YH		 1708 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1709
5ce0592b
LR		 1710 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1711 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
28d61370
YH		 1712 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1713
5ce0592b
LR		 1714 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1715 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
28d61370
YH		 1716 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1717
5ce0592b 1718 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
2d93fc85
MB		 1719 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1720
28d61370
YH		 1721 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1722
1723create_tir:
e0b4b472
LR		 1724 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1725 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
28d61370 1726
1f1d6abb 1727 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
0042f9e4
MB		 1728 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1729 err = mlx5_ib_enable_lb(dev, false, true);
1730
1731 if (err)
443c1cf9
YH		 1732 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1733 to_mpd(pd)->uid);
0042f9e4
MB		 1734 }
1735
28d61370
YH		 1736 if (err)
1737 goto err;
1738
7f72052c 1739 if (mucontext->devx_uid) {
08d53976
LR		 1740 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1741 params->resp.tirn = qp->rss_qp.tirn;
1f1d6abb 1742 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
08d53976 1743 params->resp.tir_icm_addr =
1f1d6abb 1744 MLX5_GET(create_tir_out, out, icm_address_31_0);
08d53976
LR		 1745 params->resp.tir_icm_addr |=
1746 (u64)MLX5_GET(create_tir_out, out,
1747 icm_address_39_32)
1748 << 32;
1749 params->resp.tir_icm_addr |=
1750 (u64)MLX5_GET(create_tir_out, out,
1751 icm_address_63_40)
1752 << 40;
1753 params->resp.comp_mask |=
1f1d6abb
AL		 1754 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1755 }
7f72052c
YH		 1756 }
1757
28d61370
YH		 1758 kvfree(in);
1759 /* qpn is reserved for that QP */
1760 qp->trans_qp.base.mqp.qpn = 0;
2be08c30 1761 qp->is_rss = true;
28d61370
YH		 1762 return 0;
1763
1764err:
1765 kvfree(in);
1766 return err;
1767}
1768
5d6ff1ba
YC		 1769static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1770 struct ib_qp_init_attr *init_attr,
6f4bc0ea 1771 struct mlx5_ib_create_qp *ucmd,
5d6ff1ba
YC		 1772 void *qpc)
1773{
5d6ff1ba 1774 int scqe_sz;
2ab367a7 1775 bool allow_scat_cqe = false;
5d6ff1ba 1776
6f4bc0ea
YC		 1777 if (ucmd)
1778 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1779
1780 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
5d6ff1ba
YC		 1781 return;
1782
1783 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1784 if (scqe_sz == 128) {
1785 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1786 return;
1787 }
1788
1789 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1790 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1791 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1792}
1793
a60109dc
YC		 1794static int atomic_size_to_mode(int size_mask)
1795{
1796 /* driver does not support atomic_size > 256B
1797 * and does not know how to translate bigger sizes
1798 */
1799 int supported_size_mask = size_mask & 0x1ff;
1800 int log_max_size;
1801
1802 if (!supported_size_mask)
1803 return -EOPNOTSUPP;
1804
1805 log_max_size = __fls(supported_size_mask);
1806
1807 if (log_max_size > 3)
1808 return log_max_size;
1809
1810 return MLX5_ATOMIC_MODE_8B;
1811}
1812
1813static int get_atomic_mode(struct mlx5_ib_dev *dev,
1814 enum ib_qp_type qp_type)
1815{
1816 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1817 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1818 int atomic_mode = -EOPNOTSUPP;
1819 int atomic_size_mask;
1820
1821 if (!atomic)
1822 return -EOPNOTSUPP;
1823
1824 if (qp_type == MLX5_IB_QPT_DCT)
1825 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1826 else
1827 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1828
1829 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1830 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1831 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1832
1833 if (atomic_mode <= 0 &&
1834 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1835 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1836 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1837
1838 return atomic_mode;
1839}
1840
f78d358c
LR		 1841static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1842 struct mlx5_create_qp_params *params)
04bcc1c2 1843{
e383085c 1844 struct mlx5_ib_create_qp *ucmd = params->ucmd;
f78d358c 1845 struct ib_qp_init_attr *attr = params->attr;
f78d358c 1846 u32 uidx = params->uidx;
04bcc1c2 1847 struct mlx5_ib_resources *devr = &dev->devr;
3e09a427 1848 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
04bcc1c2
LR		 1849 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1850 struct mlx5_core_dev *mdev = dev->mdev;
1851 struct mlx5_ib_qp_base *base;
1852 unsigned long flags;
1853 void *qpc;
1854 u32 *in;
1855 int err;
1856
1857 mutex_init(&qp->mutex);
1858
1859 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1860 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1861
1862 in = kvzalloc(inlen, GFP_KERNEL);
1863 if (!in)
1864 return -ENOMEM;
1865
e383085c
LR		 1866 if (MLX5_CAP_GEN(mdev, ece_support))
1867 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
04bcc1c2
LR		 1868 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1869
1870 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1871 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1872 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1873
1874 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1875 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1876 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1877 MLX5_SET(qpc, qpc, cd_master, 1);
1878 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1879 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1880 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1881 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1882
1883 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1884 MLX5_SET(qpc, qpc, no_sq, 1);
1885 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1886 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1887 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1888 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1889 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1890
1891 /* 0xffffff means we ask to work with cqe version 0 */
1892 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1893 MLX5_SET(qpc, qpc, user_index, uidx);
1894
1895 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1896 MLX5_SET(qpc, qpc, end_padding_mode,
1897 MLX5_WQ_END_PAD_MODE_ALIGN);
1898 /* Special case to clean flag */
1899 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1900 }
1901
1902 base = &qp->trans_qp.base;
3e09a427 1903 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
04bcc1c2 1904 kvfree(in);
6367da46 1905 if (err)
04bcc1c2 1906 return err;
04bcc1c2
LR		 1907
1908 base->container_mibqp = qp;
1909 base->mqp.event = mlx5_ib_qp_event;
92cd667c
LR		 1910 if (MLX5_CAP_GEN(mdev, ece_support))
1911 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
04bcc1c2
LR		 1912
1913 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1914 list_add_tail(&qp->qps_list, &dev->qp_list);
1915 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1916
968f0b6f 1917 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn;
04bcc1c2
LR		 1918 return 0;
1919}
1920
98fc1126 1921static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
f78d358c
LR		 1922 struct mlx5_ib_qp *qp,
1923 struct mlx5_create_qp_params *params)
e126ba97 1924{
f78d358c
LR		 1925 struct ib_qp_init_attr *init_attr = params->attr;
1926 struct mlx5_ib_create_qp *ucmd = params->ucmd;
3e09a427 1927 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
f78d358c
LR		 1928 struct ib_udata *udata = params->udata;
1929 u32 uidx = params->uidx;
e126ba97 1930 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1931 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1932 struct mlx5_core_dev *mdev = dev->mdev;
89ea94a7
MG		 1933 struct mlx5_ib_cq *send_cq;
1934 struct mlx5_ib_cq *recv_cq;
1935 unsigned long flags;
09a7d9ec 1936 struct mlx5_ib_qp_base *base;
e7b169f3 1937 int mlx5_st;
cfb5e088 1938 void *qpc;
09a7d9ec
SM		 1939 u32 *in;
1940 int err;
e126ba97
EC		 1941
1942 mutex_init(&qp->mutex);
1943 spin_lock_init(&qp->sq.lock);
1944 spin_lock_init(&qp->rq.lock);
1945
7aede1a2 1946 mlx5_st = to_mlx5_st(qp->type);
e7b169f3
NO		 1947 if (mlx5_st < 0)
1948 return -EINVAL;
1949
e126ba97
EC		 1950 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1951 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1952
2978975c
LR		 1953 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1954 qp->underlay_qpn = init_attr->source_qpn;
1955
c2e53b2c 1956 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 1957 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
c2e53b2c
YH		 1958 &qp->raw_packet_qp.rq.base :
1959 &qp->trans_qp.base;
1960
e126ba97 1961 qp->has_rq = qp_has_rq(init_attr);
2dfac92d 1962 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
e126ba97
EC		 1963 if (err) {
1964 mlx5_ib_dbg(dev, "err %d\n", err);
1965 return err;
1966 }
1967
98fc1126
LR		 1968 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1969 ucmd->rq_wqe_count != qp->rq.wqe_cnt)
1970 return -EINVAL;
04bcc1c2 1971
98fc1126
LR		 1972 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1973 return -EINVAL;
e126ba97 1974
08d53976
LR		 1975 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, &params->resp,
1976 &inlen, base, ucmd);
04bcc1c2
LR		 1977 if (err)
1978 return err;
e126ba97
EC		 1979
1980 if (is_sqp(init_attr->qp_type))
1981 qp->port = init_attr->port_num;
1982
e383085c
LR		 1983 if (MLX5_CAP_GEN(mdev, ece_support))
1984 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
09a7d9ec
SM		 1985 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1986
e7b169f3 1987 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 1988 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
98fc1126 1989 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
e126ba97 1990
c95e6d53 1991 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
09a7d9ec 1992 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1993
2be08c30 1994 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1995 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1996
2be08c30 1997 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
09a7d9ec 1998 MLX5_SET(qpc, qpc, cd_master, 1);
2be08c30 1999 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
09a7d9ec 2000 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2be08c30 2001 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
09a7d9ec 2002 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2be08c30 2003 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
569c6651 2004 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
90ecb37a
LR		 2005 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2006 (init_attr->qp_type == IB_QPT_RC ||
2007 init_attr->qp_type == IB_QPT_UC)) {
52c81f47 2008 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
8bde2c50
LR		 2009
2010 MLX5_SET(qpc, qpc, cs_res,
2011 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2012 MLX5_RES_SCAT_DATA32_CQE);
2013 }
90ecb37a 2014 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
7aede1a2 2015 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
2dfac92d 2016 configure_requester_scat_cqe(dev, init_attr, ucmd, qpc);
e126ba97
EC		 2017
2018 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 2019 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2020 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 2021 }
2022
09a7d9ec 2023 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 2024
3fd3307e 2025 if (qp->sq.wqe_cnt) {
09a7d9ec 2026 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 2027 } else {
09a7d9ec 2028 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 2029 if (init_attr->srq &&
2030 init_attr->srq->srq_type == IB_SRQT_TM)
2031 MLX5_SET(qpc, qpc, offload_type,
2032 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2033 }
e126ba97
EC		 2034
2035 /* Set default resources */
2036 switch (init_attr->qp_type) {
e126ba97 2037 case IB_QPT_XRC_INI:
09a7d9ec 2038 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
f4375443 2039 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
09a7d9ec 2040 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 2041 break;
2042 default:
2043 if (init_attr->srq) {
f4375443 2044 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
09a7d9ec 2045 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 2046 } else {
f4375443 2047 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
09a7d9ec 2048 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 2049 }
2050 }
2051
2052 if (init_attr->send_cq)
09a7d9ec 2053 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 2054
2055 if (init_attr->recv_cq)
09a7d9ec 2056 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 2057
09a7d9ec 2058 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 2059
09a7d9ec
SM		 2060 /* 0xffffff means we ask to work with cqe version 0 */
2061 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 2062 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 2063
2978975c
LR		 2064 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2065 init_attr->qp_type != IB_QPT_RAW_PACKET) {
2066 MLX5_SET(qpc, qpc, end_padding_mode,
2067 MLX5_WQ_END_PAD_MODE_ALIGN);
2068 /* Special case to clean flag */
2069 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
b1383aa6
NO		 2070 }
2071
c2e53b2c 2072 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 2073 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2dfac92d 2074 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
0fb2ed66 2075 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
7f72052c 2076 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
08d53976 2077 &params->resp);
04bcc1c2 2078 } else
3e09a427 2079 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
e126ba97 2080
479163f4 2081 kvfree(in);
04bcc1c2
LR		 2082 if (err)
2083 goto err_create;
e126ba97 2084
19098df2 2085 base->container_mibqp = qp;
2086 base->mqp.event = mlx5_ib_qp_event;
92cd667c
LR		 2087 if (MLX5_CAP_GEN(mdev, ece_support))
2088 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
e126ba97 2089
7aede1a2 2090 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
89ea94a7
MG		 2091 &send_cq, &recv_cq);
2092 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2093 mlx5_ib_lock_cqs(send_cq, recv_cq);
2094 /* Maintain device to QPs access, needed for further handling via reset
2095 * flow
2096 */
2097 list_add_tail(&qp->qps_list, &dev->qp_list);
2098 /* Maintain CQ to QPs access, needed for further handling via reset flow
2099 */
2100 if (send_cq)
2101 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2102 if (recv_cq)
2103 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2104 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2105 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2106
e126ba97
EC		 2107 return 0;
2108
2109err_create:
747c519c 2110 destroy_qp(dev, qp, base, udata);
e126ba97
EC		 2111 return err;
2112}
2113
98fc1126 2114static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
f78d358c
LR		 2115 struct mlx5_ib_qp *qp,
2116 struct mlx5_create_qp_params *params)
98fc1126 2117{
f78d358c
LR		 2118 struct ib_qp_init_attr *attr = params->attr;
2119 u32 uidx = params->uidx;
98fc1126 2120 struct mlx5_ib_resources *devr = &dev->devr;
3e09a427 2121 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
98fc1126
LR		 2122 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2123 struct mlx5_core_dev *mdev = dev->mdev;
2124 struct mlx5_ib_cq *send_cq;
2125 struct mlx5_ib_cq *recv_cq;
2126 unsigned long flags;
2127 struct mlx5_ib_qp_base *base;
2128 int mlx5_st;
2129 void *qpc;
2130 u32 *in;
2131 int err;
2132
2133 mutex_init(&qp->mutex);
2134 spin_lock_init(&qp->sq.lock);
2135 spin_lock_init(&qp->rq.lock);
2136
2137 mlx5_st = to_mlx5_st(qp->type);
2138 if (mlx5_st < 0)
2139 return -EINVAL;
2140
2141 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2142 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2143
2144 base = &qp->trans_qp.base;
2145
2146 qp->has_rq = qp_has_rq(attr);
2147 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2148 if (err) {
2149 mlx5_ib_dbg(dev, "err %d\n", err);
2150 return err;
2151 }
2152
2153 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2154 if (err)
2155 return err;
2156
2157 if (is_sqp(attr->qp_type))
2158 qp->port = attr->port_num;
2159
2160 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2161
2162 MLX5_SET(qpc, qpc, st, mlx5_st);
2163 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2164
2165 if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2166 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2167 else
2168 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2169
2170
2171 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2172 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2173
2174 if (qp->rq.wqe_cnt) {
2175 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2176 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2177 }
2178
2179 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2180
2181 if (qp->sq.wqe_cnt)
2182 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2183 else
2184 MLX5_SET(qpc, qpc, no_sq, 1);
2185
2186 if (attr->srq) {
f4375443 2187 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
98fc1126
LR		 2188 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2189 to_msrq(attr->srq)->msrq.srqn);
2190 } else {
f4375443 2191 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
98fc1126
LR		 2192 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2193 to_msrq(devr->s1)->msrq.srqn);
2194 }
2195
2196 if (attr->send_cq)
2197 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2198
2199 if (attr->recv_cq)
2200 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2201
2202 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2203
2204 /* 0xffffff means we ask to work with cqe version 0 */
2205 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2206 MLX5_SET(qpc, qpc, user_index, uidx);
2207
2208 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2209 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2210 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2211
3e09a427 2212 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
98fc1126
LR		 2213 kvfree(in);
2214 if (err)
2215 goto err_create;
2216
2217 base->container_mibqp = qp;
2218 base->mqp.event = mlx5_ib_qp_event;
2219
2220 get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2221 &send_cq, &recv_cq);
2222 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2223 mlx5_ib_lock_cqs(send_cq, recv_cq);
2224 /* Maintain device to QPs access, needed for further handling via reset
2225 * flow
2226 */
2227 list_add_tail(&qp->qps_list, &dev->qp_list);
2228 /* Maintain CQ to QPs access, needed for further handling via reset flow
2229 */
2230 if (send_cq)
2231 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2232 if (recv_cq)
2233 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2234 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2235 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2236
2237 return 0;
2238
2239err_create:
747c519c 2240 destroy_qp(dev, qp, base, NULL);
98fc1126
LR		 2241 return err;
2242}
2243
e126ba97
EC		 2244static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2245 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2246{
2247 if (send_cq) {
2248 if (recv_cq) {
2249 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 2250 spin_lock(&send_cq->lock);
e126ba97
EC		 2251 spin_lock_nested(&recv_cq->lock,
2252 SINGLE_DEPTH_NESTING);
2253 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 2254 spin_lock(&send_cq->lock);
e126ba97
EC		 2255 __acquire(&recv_cq->lock);
2256 } else {
89ea94a7 2257 spin_lock(&recv_cq->lock);
e126ba97
EC		 2258 spin_lock_nested(&send_cq->lock,
2259 SINGLE_DEPTH_NESTING);
2260 }
2261 } else {
89ea94a7 2262 spin_lock(&send_cq->lock);
6a4f139a 2263 __acquire(&recv_cq->lock);
e126ba97
EC		 2264 }
2265 } else if (recv_cq) {
89ea94a7 2266 spin_lock(&recv_cq->lock);
6a4f139a
EC		 2267 __acquire(&send_cq->lock);
2268 } else {
2269 __acquire(&send_cq->lock);
2270 __acquire(&recv_cq->lock);
e126ba97
EC		 2271 }
2272}
2273
2274static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2275 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2276{
2277 if (send_cq) {
2278 if (recv_cq) {
2279 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2280 spin_unlock(&recv_cq->lock);
89ea94a7 2281 spin_unlock(&send_cq->lock);
e126ba97
EC		 2282 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2283 __release(&recv_cq->lock);
89ea94a7 2284 spin_unlock(&send_cq->lock);
e126ba97
EC		 2285 } else {
2286 spin_unlock(&send_cq->lock);
89ea94a7 2287 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2288 }
2289 } else {
6a4f139a 2290 __release(&recv_cq->lock);
89ea94a7 2291 spin_unlock(&send_cq->lock);
e126ba97
EC		 2292 }
2293 } else if (recv_cq) {
6a4f139a 2294 __release(&send_cq->lock);
89ea94a7 2295 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2296 } else {
2297 __release(&recv_cq->lock);
2298 __release(&send_cq->lock);
e126ba97
EC		 2299 }
2300}
2301
89ea94a7
MG		 2302static void get_cqs(enum ib_qp_type qp_type,
2303 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2304 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2305{
89ea94a7 2306 switch (qp_type) {
e126ba97
EC		 2307 case IB_QPT_XRC_TGT:
2308 *send_cq = NULL;
2309 *recv_cq = NULL;
2310 break;
2311 case MLX5_IB_QPT_REG_UMR:
2312 case IB_QPT_XRC_INI:
89ea94a7 2313 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2314 *recv_cq = NULL;
2315 break;
2316
2317 case IB_QPT_SMI:
d16e91da 2318 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2319 case IB_QPT_RC:
2320 case IB_QPT_UC:
2321 case IB_QPT_UD:
0fb2ed66 2322 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2323 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2324 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97 2325 break;
e126ba97
EC		 2326 default:
2327 *send_cq = NULL;
2328 *recv_cq = NULL;
2329 break;
2330 }
2331}
2332
ad5f8e96 2333static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2334 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2335 u8 lag_tx_affinity);
ad5f8e96 2336
bdeacabd
SR		 2337static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2338 struct ib_udata *udata)
e126ba97
EC		 2339{
2340 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2341 struct mlx5_ib_qp_base *base;
89ea94a7 2342 unsigned long flags;
e126ba97
EC		 2343 int err;
2344
28d61370
YH		 2345 if (qp->ibqp.rwq_ind_tbl) {
2346 destroy_rss_raw_qp_tir(dev, qp);
2347 return;
2348 }
2349
c2e53b2c 2350 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 2351 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
0fb2ed66 2352 &qp->raw_packet_qp.rq.base :
2353 &qp->trans_qp.base;
2354
6aec21f6 2355 if (qp->state != IB_QPS_RESET) {
c2e53b2c 2356 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2be08c30 2357 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
333fbaa0 2358 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
5f62a521 2359 NULL, &base->mqp, NULL);
ad5f8e96 2360 } else {
0680efa2
AV		 2361 struct mlx5_modify_raw_qp_param raw_qp_param = {
2362 .operation = MLX5_CMD_OP_2RST_QP
2363 };
2364
13eab21f 2365 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2366 }
2367 if (err)
427c1e7b 2368 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2369 base->mqp.qpn);
6aec21f6 2370 }
e126ba97 2371
89ea94a7
MG		 2372 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2373 &send_cq, &recv_cq);
2374
2375 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2376 mlx5_ib_lock_cqs(send_cq, recv_cq);
2377 /* del from lists under both locks above to protect reset flow paths */
2378 list_del(&qp->qps_list);
2379 if (send_cq)
2380 list_del(&qp->cq_send_list);
2381
2382 if (recv_cq)
2383 list_del(&qp->cq_recv_list);
e126ba97 2384
03c4077b 2385 if (!udata) {
19098df2 2386 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2387 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2388 if (send_cq != recv_cq)
19098df2 2389 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2390 NULL);
e126ba97 2391 }
89ea94a7
MG		 2392 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2393 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2394
c2e53b2c 2395 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 2396 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0fb2ed66 2397 destroy_raw_packet_qp(dev, qp);
2398 } else {
333fbaa0 2399 err = mlx5_core_destroy_qp(dev, &base->mqp);
0fb2ed66 2400 if (err)
2401 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2402 base->mqp.qpn);
2403 }
e126ba97 2404
747c519c 2405 destroy_qp(dev, qp, base, udata);
e126ba97
EC		 2406}
2407
a645a89d
LR		 2408static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2409 struct mlx5_ib_qp *qp,
f78d358c 2410 struct mlx5_create_qp_params *params)
b4aaa1f0 2411{
f78d358c
LR		 2412 struct ib_qp_init_attr *attr = params->attr;
2413 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2414 u32 uidx = params->uidx;
b4aaa1f0
MS		 2415 void *dctc;
2416
b4aaa1f0 2417 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
9c2ba4ed 2418 if (!qp->dct.in)
47c80612 2419 return -ENOMEM;
b4aaa1f0 2420
a01a5860 2421 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
b4aaa1f0 2422 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
b4aaa1f0
MS		 2423 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2424 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2425 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2426 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2427 MLX5_SET(dctc, dctc, user_index, uidx);
a645a89d
LR		 2428 if (MLX5_CAP_GEN(dev->mdev, ece_support))
2429 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
b4aaa1f0 2430
37518fa4 2431 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
fd9dab7e
LR		 2432 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2433
2434 if (rcqe_sz == 128)
2435 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2436 }
5d6ff1ba 2437
b4aaa1f0
MS		 2438 qp->state = IB_QPS_RESET;
2439
47c80612 2440 return 0;
b4aaa1f0
MS		 2441}
2442
7aede1a2
LR		 2443static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2444 enum ib_qp_type *type)
6eb7edff
LR		 2445{
2446 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2447 goto out;
2448
2449 switch (attr->qp_type) {
2450 case IB_QPT_XRC_TGT:
2451 case IB_QPT_XRC_INI:
2452 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2453 goto out;
2454 fallthrough;
6eb7edff
LR		 2455 case IB_QPT_RC:
2456 case IB_QPT_UC:
6eb7edff
LR		 2457 case IB_QPT_SMI:
2458 case MLX5_IB_QPT_HW_GSI:
6eb7edff
LR		 2459 case IB_QPT_DRIVER:
2460 case IB_QPT_GSI:
42caf9cb
MB		 2461 if (dev->profile == &raw_eth_profile)
2462 goto out;
2463 case IB_QPT_RAW_PACKET:
2464 case IB_QPT_UD:
2465 case MLX5_IB_QPT_REG_UMR:
7aede1a2 2466 break;
6eb7edff
LR		 2467 default:
2468 goto out;
b4aaa1f0
MS		 2469 }
2470
7aede1a2 2471 *type = attr->qp_type;
b4aaa1f0 2472 return 0;
6eb7edff
LR		 2473
2474out:
2475 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2476 return -EOPNOTSUPP;
b4aaa1f0
MS		 2477}
2478
2242cc25
LR		 2479static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2480 struct ib_qp_init_attr *attr,
2481 struct ib_udata *udata)
2482{
2483 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2484 udata, struct mlx5_ib_ucontext, ibucontext);
2485
2486 if (!udata) {
2487 /* Kernel create_qp callers */
2488 if (attr->rwq_ind_tbl)
2489 return -EOPNOTSUPP;
2490
2491 switch (attr->qp_type) {
2492 case IB_QPT_RAW_PACKET:
2493 case IB_QPT_DRIVER:
2494 return -EOPNOTSUPP;
2495 default:
2496 return 0;
2497 }
2498 }
2499
2500 /* Userspace create_qp callers */
2501 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2502 mlx5_ib_dbg(dev,
2503 "Raw Packet QP is only supported for CQE version > 0\n");
2504 return -EINVAL;
2505 }
2506
2507 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2508 mlx5_ib_dbg(dev,
2509 "Wrong QP type %d for the RWQ indirect table\n",
2510 attr->qp_type);
2511 return -EINVAL;
2512 }
2513
2514 switch (attr->qp_type) {
2515 case IB_QPT_SMI:
2516 case MLX5_IB_QPT_HW_GSI:
2517 case MLX5_IB_QPT_REG_UMR:
2518 case IB_QPT_GSI:
2519 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2520 attr->qp_type);
2521 return -EINVAL;
2522 default:
2523 break;
2524 }
2525
2526 /*
2527 * We don't need to see this warning, it means that kernel code
2528 * missing ib_pd. Placed here to catch developer's mistakes.
2529 */
2530 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2531 "There is a missing PD pointer assignment\n");
2532 return 0;
2533}
2534
37518fa4
LR		 2535static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2536 bool cond, struct mlx5_ib_qp *qp)
2537{
2538 if (!(*flags & flag))
2539 return;
2540
2541 if (cond) {
2542 qp->flags_en |= flag;
2543 *flags &= ~flag;
2544 return;
2545 }
2546
2547 if (flag == MLX5_QP_FLAG_SCATTER_CQE) {
2548 /*
2549 * We don't return error if this flag was provided,
2550 * and mlx5 doesn't have right capability.
2551 */
2552 *flags &= ~MLX5_QP_FLAG_SCATTER_CQE;
2553 return;
2554 }
2555 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2556}
2557
2558static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5ce0592b 2559 void *ucmd, struct ib_qp_init_attr *attr)
2fdddbd5 2560{
37518fa4 2561 struct mlx5_core_dev *mdev = dev->mdev;
37518fa4 2562 bool cond;
5ce0592b
LR		 2563 int flags;
2564
2565 if (attr->rwq_ind_tbl)
2566 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2567 else
2568 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
37518fa4
LR		 2569
2570 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2fdddbd5 2571 case MLX5_QP_FLAG_TYPE_DCI:
7aede1a2 2572 qp->type = MLX5_IB_QPT_DCI;
2fdddbd5
LR		 2573 break;
2574 case MLX5_QP_FLAG_TYPE_DCT:
7aede1a2 2575 qp->type = MLX5_IB_QPT_DCT;
37518fa4 2576 break;
7aede1a2
LR		 2577 default:
2578 if (qp->type != IB_QPT_DRIVER)
2579 break;
2580 /*
2581 * It is IB_QPT_DRIVER and or no subtype or
2582 * wrong subtype were provided.
2583 */
2fdddbd5 2584 return -EINVAL;
7aede1a2 2585 }
37518fa4
LR		 2586
2587 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2588 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2589
2590 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2591 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2592 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
2593
7aede1a2 2594 if (qp->type == IB_QPT_RAW_PACKET) {
37518fa4
LR		 2595 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2596 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2597 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2598 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2599 cond, qp);
2600 process_vendor_flag(dev, &flags,
2601 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2602 qp);
2603 process_vendor_flag(dev, &flags,
2604 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2605 qp);
2fdddbd5
LR		 2606 }
2607
7aede1a2 2608 if (qp->type == IB_QPT_RC)
37518fa4
LR		 2609 process_vendor_flag(dev, &flags,
2610 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2611 MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2612
76883a6c
LR		 2613 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2614 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2615
5d6fffed
LR		 2616 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2617 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2618 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC);
2619 if (attr->rwq_ind_tbl && cond) {
2620 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n",
2621 cond);
2622 return -EINVAL;
2623 }
2624
37518fa4
LR		 2625 if (flags)
2626 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2627
2628 return (flags) ? -EINVAL : 0;
5d6fffed 2629 }
2fdddbd5 2630
2978975c
LR		 2631static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2632 bool cond, struct mlx5_ib_qp *qp)
2633{
2634 if (!(*flags & flag))
2635 return;
2636
2637 if (cond) {
2638 qp->flags |= flag;
2639 *flags &= ~flag;
2640 return;
2641 }
2642
2643 if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2644 /*
2645 * Special case, if condition didn't meet, it won't be error,
2646 * just different in-kernel flow.
2647 */
2648 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2649 return;
2650 }
2651 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2652}
2653
2654static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2655 struct ib_qp_init_attr *attr)
2656{
7aede1a2 2657 enum ib_qp_type qp_type = qp->type;
2978975c
LR		 2658 struct mlx5_core_dev *mdev = dev->mdev;
2659 int create_flags = attr->create_flags;
2660 bool cond;
2661
42caf9cb
MB		 2662 if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile)
2663 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST)
2664 return -EINVAL;
2665
7aede1a2 2666 if (qp_type == MLX5_IB_QPT_DCT)
2978975c
LR		 2667 return (create_flags) ? -EINVAL : 0;
2668
2669 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2670 return (create_flags) ? -EINVAL : 0;
2671
2672 process_create_flag(dev, &create_flags,
2673 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2674 MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2675 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2676 MLX5_CAP_GEN(mdev, cd), qp);
2677 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2678 MLX5_CAP_GEN(mdev, cd), qp);
2679 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2680 MLX5_CAP_GEN(mdev, cd), qp);
2681
2682 if (qp_type == IB_QPT_UD) {
2683 process_create_flag(dev, &create_flags,
2684 IB_QP_CREATE_IPOIB_UD_LSO,
2685 MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2686 qp);
2687 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2688 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2689 cond, qp);
2690 }
2691
2692 if (qp_type == IB_QPT_RAW_PACKET) {
2693 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2694 MLX5_CAP_ETH(mdev, scatter_fcs);
2695 process_create_flag(dev, &create_flags,
2696 IB_QP_CREATE_SCATTER_FCS, cond, qp);
2697
2698 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2699 MLX5_CAP_ETH(mdev, vlan_cap);
2700 process_create_flag(dev, &create_flags,
2701 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2702 }
2703
2704 process_create_flag(dev, &create_flags,
2705 IB_QP_CREATE_PCI_WRITE_END_PADDING,
2706 MLX5_CAP_GEN(mdev, end_pad), qp);
2707
2708 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2709 qp_type != MLX5_IB_QPT_REG_UMR, qp);
2710 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2711 true, qp);
2712
2713 if (create_flags)
2714 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2715 create_flags);
2716
2717 return (create_flags) ? -EINVAL : 0;
2718}
2719
6f2cf76e
LR		 2720static int process_udata_size(struct mlx5_ib_dev *dev,
2721 struct mlx5_create_qp_params *params)
2fdddbd5
LR		 2722{
2723 size_t ucmd = sizeof(struct mlx5_ib_create_qp);
6f2cf76e
LR		 2724 struct ib_udata *udata = params->udata;
2725 size_t outlen = udata->outlen;
5ce0592b 2726 size_t inlen = udata->inlen;
2fdddbd5 2727
6f2cf76e 2728 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp));
e383085c 2729 params->ucmd_size = ucmd;
6f2cf76e 2730 if (!params->is_rss_raw) {
e383085c
LR		 2731 /* User has old rdma-core, which doesn't support ECE */
2732 size_t min_inlen =
2733 offsetof(struct mlx5_ib_create_qp, ece_options);
2734
2735 /*
2736 * We will check in check_ucmd_data() that user
2737 * cleared everything after inlen.
2738 */
2739 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd);
6f2cf76e
LR		 2740 goto out;
2741 }
5ce0592b 2742
6f2cf76e 2743 /* RSS RAW QP */
5ce0592b 2744 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
6f2cf76e
LR		 2745 return -EINVAL;
2746
2747 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index))
2748 return -EINVAL;
5ce0592b
LR		 2749
2750 ucmd = sizeof(struct mlx5_ib_create_qp_rss);
e383085c 2751 params->ucmd_size = ucmd;
5ce0592b 2752 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
6f2cf76e
LR		 2753 return -EINVAL;
2754
2755 params->inlen = min(ucmd, inlen);
2756out:
2757 if (!params->inlen)
e383085c 2758 mlx5_ib_dbg(dev, "udata is too small\n");
2dfac92d 2759
6f2cf76e 2760 return (params->inlen) ? 0 : -EINVAL;
2fdddbd5
LR		 2761}
2762
968f0b6f
LR		 2763static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2764 struct mlx5_ib_qp *qp,
2765 struct mlx5_create_qp_params *params)
5d0dc3d9 2766{
968f0b6f
LR		 2767 int err;
2768
2769 if (params->is_rss_raw) {
2770 err = create_rss_raw_qp_tir(dev, pd, qp, params);
2771 goto out;
2772 }
2773
2774 if (qp->type == MLX5_IB_QPT_DCT) {
a645a89d 2775 err = create_dct(dev, pd, qp, params);
968f0b6f
LR		 2776 goto out;
2777 }
2778
2779 if (qp->type == IB_QPT_XRC_TGT) {
2780 err = create_xrc_tgt_qp(dev, qp, params);
2781 goto out;
2782 }
5d0dc3d9 2783
968f0b6f
LR		 2784 if (params->udata)
2785 err = create_user_qp(dev, pd, qp, params);
2786 else
2787 err = create_kernel_qp(dev, pd, qp, params);
2788
2789out:
2790 if (err) {
2791 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type);
2792 return err;
2793 }
2794
2795 if (is_qp0(qp->type))
2796 qp->ibqp.qp_num = 0;
2797 else if (is_qp1(qp->type))
2798 qp->ibqp.qp_num = 1;
2799 else
2800 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2801
2802 mlx5_ib_dbg(dev,
3e09a427 2803 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n",
968f0b6f
LR		 2804 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2805 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn :
2806 -1,
2807 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn :
3e09a427
LR		 2808 -1,
2809 params->resp.ece_options);
968f0b6f
LR		 2810
2811 return 0;
5d0dc3d9
LR		 2812}
2813
7aede1a2
LR		 2814static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2815 struct ib_qp_init_attr *attr)
2816{
2817 int ret = 0;
2818
2819 switch (qp->type) {
2820 case MLX5_IB_QPT_DCT:
2821 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2822 break;
2823 case MLX5_IB_QPT_DCI:
2824 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2825 -EINVAL :
2826 0;
2827 break;
266424eb
LR		 2828 case IB_QPT_RAW_PACKET:
2829 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2830 break;
7aede1a2
LR		 2831 default:
2832 break;
2833 }
2834
2835 if (ret)
2836 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2837
2838 return ret;
2839}
2840
f78d358c
LR		 2841static int get_qp_uidx(struct mlx5_ib_qp *qp,
2842 struct mlx5_create_qp_params *params)
21aad80b 2843{
f78d358c
LR		 2844 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2845 struct ib_udata *udata = params->udata;
21aad80b
LR		 2846 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2847 udata, struct mlx5_ib_ucontext, ibucontext);
2848
f78d358c 2849 if (params->is_rss_raw)
21aad80b
LR		 2850 return 0;
2851
f78d358c 2852 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &params->uidx);
21aad80b
LR		 2853}
2854
08d53976
LR		 2855static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2856{
2857 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2858
2859 if (mqp->state == IB_QPS_RTR) {
2860 int err;
2861
2862 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2863 if (err) {
2864 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2865 return err;
2866 }
2867 }
2868
2869 kfree(mqp->dct.in);
2870 kfree(mqp);
2871 return 0;
2872}
2873
e383085c
LR		 2874static int check_ucmd_data(struct mlx5_ib_dev *dev,
2875 struct mlx5_create_qp_params *params)
2876{
2877 struct ib_qp_init_attr *attr = params->attr;
2878 struct ib_udata *udata = params->udata;
2879 size_t size, last;
2880 int ret;
2881
2882 if (params->is_rss_raw)
2883 /*
2884 * These QPs don't have "reserved" field in their
2885 * create_qp input struct, so their data is always valid.
2886 */
2887 last = sizeof(struct mlx5_ib_create_qp_rss);
2888 else
a645a89d 2889 /* IB_QPT_RAW_PACKET doesn't have ECE data */
e383085c 2890 switch (attr->qp_type) {
e383085c
LR		 2891 case IB_QPT_RAW_PACKET:
2892 last = offsetof(struct mlx5_ib_create_qp, ece_options);
2893 break;
2894 default:
2895 last = offsetof(struct mlx5_ib_create_qp, reserved);
2896 }
2897
2898 if (udata->inlen <= last)
2899 return 0;
2900
2901 /*
2902 * User provides different create_qp structures based on the
2903 * flow and we need to know if he cleared memory after our
2904 * struct create_qp ends.
2905 */
2906 size = udata->inlen - last;
2907 ret = ib_is_udata_cleared(params->udata, last, size);
2908 if (!ret)
2909 mlx5_ib_dbg(
2910 dev,
2911 "udata is not cleared, inlen = %lu, ucmd = %lu, last = %lu, size = %lu\n",
2912 udata->inlen, params->ucmd_size, last, size);
2913 return ret ? 0 : -EINVAL;
2914}
2915
f78d358c 2916struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr,
e126ba97
EC		 2917 struct ib_udata *udata)
2918{
f78d358c 2919 struct mlx5_create_qp_params params = {};
e126ba97
EC		 2920 struct mlx5_ib_dev *dev;
2921 struct mlx5_ib_qp *qp;
7aede1a2 2922 enum ib_qp_type type;
e126ba97
EC		 2923 int err;
2924
6eb7edff 2925 dev = pd ? to_mdev(pd->device) :
f78d358c 2926 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device);
0fb2ed66 2927
f78d358c
LR		 2928 err = check_qp_type(dev, attr, &type);
2929 if (err)
6eb7edff 2930 return ERR_PTR(err);
6eb7edff 2931
f78d358c 2932 err = check_valid_flow(dev, pd, attr, udata);
2242cc25
LR		 2933 if (err)
2934 return ERR_PTR(err);
e126ba97 2935
f78d358c
LR		 2936 if (attr->qp_type == IB_QPT_GSI)
2937 return mlx5_ib_gsi_create_qp(pd, attr);
9c2ba4ed 2938
f78d358c
LR		 2939 params.udata = udata;
2940 params.uidx = MLX5_IB_DEFAULT_UIDX;
2941 params.attr = attr;
2942 params.is_rss_raw = !!attr->rwq_ind_tbl;
2fdddbd5 2943
f78d358c 2944 if (udata) {
6f2cf76e
LR		 2945 err = process_udata_size(dev, &params);
2946 if (err)
2947 return ERR_PTR(err);
2fdddbd5 2948
e383085c
LR		 2949 err = check_ucmd_data(dev, &params);
2950 if (err)
2951 return ERR_PTR(err);
2952
2953 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL);
f78d358c 2954 if (!params.ucmd)
5ce0592b
LR		 2955 return ERR_PTR(-ENOMEM);
2956
f78d358c 2957 err = ib_copy_from_udata(params.ucmd, udata, params.inlen);
2fdddbd5 2958 if (err)
5ce0592b 2959 goto free_ucmd;
2fdddbd5
LR		 2960 }
2961
9c2ba4ed 2962 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
5ce0592b
LR		 2963 if (!qp) {
2964 err = -ENOMEM;
2965 goto free_ucmd;
2966 }
9c2ba4ed 2967
7aede1a2 2968 qp->type = type;
37518fa4 2969 if (udata) {
f78d358c 2970 err = process_vendor_flags(dev, qp, params.ucmd, attr);
b4aaa1f0 2971 if (err)
9c2ba4ed 2972 goto free_qp;
21aad80b 2973
f78d358c 2974 err = get_qp_uidx(qp, &params);
21aad80b
LR		 2975 if (err)
2976 goto free_qp;
b4aaa1f0 2977 }
f78d358c 2978 err = process_create_flags(dev, qp, attr);
2978975c
LR		 2979 if (err)
2980 goto free_qp;
b4aaa1f0 2981
f78d358c 2982 err = check_qp_attr(dev, qp, attr);
7aede1a2
LR		 2983 if (err)
2984 goto free_qp;
2985
968f0b6f
LR		 2986 err = create_qp(dev, pd, qp, &params);
2987 if (err)
9c2ba4ed 2988 goto free_qp;
e126ba97 2989
f78d358c 2990 kfree(params.ucmd);
08d53976 2991 params.ucmd = NULL;
5ce0592b 2992
08d53976
LR		 2993 if (udata)
2994 /*
2995 * It is safe to copy response for all user create QP flows,
2996 * including MLX5_IB_QPT_DCT, which doesn't need it.
2997 * In that case, resp will be filled with zeros.
2998 */
2999 err = ib_copy_to_udata(udata, &params.resp, params.outlen);
3000 if (err)
3001 goto destroy_qp;
3002
e126ba97 3003 return &qp->ibqp;
9c2ba4ed 3004
08d53976
LR		 3005destroy_qp:
3006 if (qp->type == MLX5_IB_QPT_DCT)
3007 mlx5_ib_destroy_dct(qp);
3008 else
3009 destroy_qp_common(dev, qp, udata);
3010 qp = NULL;
9c2ba4ed
LR		 3011free_qp:
3012 kfree(qp);
5ce0592b 3013free_ucmd:
f78d358c 3014 kfree(params.ucmd);
9c2ba4ed 3015 return ERR_PTR(err);
e126ba97
EC		 3016}
3017
c4367a26 3018int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
e126ba97
EC		 3019{
3020 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3021 struct mlx5_ib_qp *mqp = to_mqp(qp);
3022
d16e91da
HE		 3023 if (unlikely(qp->qp_type == IB_QPT_GSI))
3024 return mlx5_ib_gsi_destroy_qp(qp);
3025
7aede1a2 3026 if (mqp->type == MLX5_IB_QPT_DCT)
776a3906
MS		 3027 return mlx5_ib_destroy_dct(mqp);
3028
bdeacabd 3029 destroy_qp_common(dev, mqp, udata);
e126ba97
EC		 3030
3031 kfree(mqp);
3032
3033 return 0;
3034}
3035
f18e26af
LR		 3036static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
3037 const struct ib_qp_attr *attr, int attr_mask,
3038 void *qpc)
e126ba97 3039{
a60109dc 3040 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
f18e26af
LR		 3041 u8 dest_rd_atomic;
3042 u32 access_flags;
a60109dc 3043
e126ba97
EC		 3044 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3045 dest_rd_atomic = attr->max_dest_rd_atomic;
3046 else
19098df2 3047 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 3048
3049 if (attr_mask & IB_QP_ACCESS_FLAGS)
3050 access_flags = attr->qp_access_flags;
3051 else
19098df2 3052 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 3053
3054 if (!dest_rd_atomic)
3055 access_flags &= IB_ACCESS_REMOTE_WRITE;
3056
f18e26af
LR		 3057 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
3058
13f8d9c1 3059 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 3060 int atomic_mode;
3061
3062 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3063 if (atomic_mode < 0)
3064 return -EOPNOTSUPP;
3065
f18e26af
LR		 3066 MLX5_SET(qpc, qpc, rae, 1);
3067 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
a60109dc
YC		 3068 }
3069
f18e26af 3070 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
a60109dc 3071 return 0;
e126ba97
EC		 3072}
3073
3074enum {
3075 MLX5_PATH_FLAG_FL = 1 << 0,
3076 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
3077 MLX5_PATH_FLAG_COUNTER = 1 << 2,
3078};
3079
3080static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3081{
4f32ac2e 3082 if (rate == IB_RATE_PORT_CURRENT)
e126ba97 3083 return 0;
4f32ac2e 3084
a5a5d199 3085 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
e126ba97 3086 return -EINVAL;
e126ba97 3087
4f32ac2e
DG		 3088 while (rate != IB_RATE_PORT_CURRENT &&
3089 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
3090 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
3091 --rate;
3092
3093 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
e126ba97
EC		 3094}
3095
75850d0b 3096static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 3097 struct mlx5_ib_sq *sq, u8 sl,
3098 struct ib_pd *pd)
75850d0b 3099{
3100 void *in;
3101 void *tisc;
3102 int inlen;
3103 int err;
3104
3105 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 3106 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 3107 if (!in)
3108 return -ENOMEM;
3109
3110 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1cd6dbd3 3111 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
75850d0b 3112
3113 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3114 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3115
e0b4b472 3116 err = mlx5_core_modify_tis(dev, sq->tisn, in);
75850d0b 3117
3118 kvfree(in);
3119
3120 return err;
3121}
3122
13eab21f 3123static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 3124 struct mlx5_ib_sq *sq, u8 tx_affinity,
3125 struct ib_pd *pd)
13eab21f
AH		 3126{
3127 void *in;
3128 void *tisc;
3129 int inlen;
3130 int err;
3131
3132 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 3133 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 3134 if (!in)
3135 return -ENOMEM;
3136
3137 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
1cd6dbd3 3138 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
13eab21f
AH		 3139
3140 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3141 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3142
e0b4b472 3143 err = mlx5_core_modify_tis(dev, sq->tisn, in);
13eab21f
AH		 3144
3145 kvfree(in);
3146
3147 return err;
3148}
3149
f18e26af 3150static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
2b880b2e
MZ		 3151 u32 lqpn, u32 rqpn)
3152
3153{
3154 u32 fl = ah->grh.flow_label;
2b880b2e
MZ		 3155
3156 if (!fl)
3157 fl = rdma_calc_flow_label(lqpn, rqpn);
3158
f18e26af 3159 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
2b880b2e
MZ		 3160}
3161
75850d0b 3162static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
f18e26af
LR		 3163 const struct rdma_ah_attr *ah, void *path, u8 port,
3164 int attr_mask, u32 path_flags,
3165 const struct ib_qp_attr *attr, bool alt)
e126ba97 3166{
d8966fcd 3167 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 3168 int err;
ed88451e 3169 enum ib_gid_type gid_type;
d8966fcd
DC		 3170 u8 ah_flags = rdma_ah_get_ah_flags(ah);
3171 u8 sl = rdma_ah_get_sl(ah);
e126ba97 3172
e126ba97 3173 if (attr_mask & IB_QP_PKEY_INDEX)
f18e26af
LR		 3174 MLX5_SET(ads, path, pkey_index,
3175 alt ? attr->alt_pkey_index : attr->pkey_index);
e126ba97 3176
d8966fcd
DC		 3177 if (ah_flags & IB_AH_GRH) {
3178 if (grh->sgid_index >=
938fe83c 3179 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 3180 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 3181 grh->sgid_index,
938fe83c 3182 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 3183 return -EINVAL;
3184 }
2811ba51 3185 }
44c58487
DC		 3186
3187 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 3188 if (!(ah_flags & IB_AH_GRH))
2811ba51 3189 return -EINVAL;
47ec3866 3190
f18e26af
LR		 3191 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
3192 ah->roce.dmac);
2b880b2e
MZ		 3193 if ((qp->ibqp.qp_type == IB_QPT_RC ||
3194 qp->ibqp.qp_type == IB_QPT_UC ||
3195 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3196 qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
3197 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) &&
3198 (attr_mask & IB_QP_DEST_QPN))
3199 mlx5_set_path_udp_sport(path, ah,
3200 qp->ibqp.qp_num,
3201 attr->dest_qp_num);
f18e26af 3202 MLX5_SET(ads, path, eth_prio, sl & 0x7);
47ec3866 3203 gid_type = ah->grh.sgid_attr->gid_type;
ed88451e 3204 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
f18e26af 3205 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
2811ba51 3206 } else {
f18e26af
LR		 3207 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
3208 MLX5_SET(ads, path, free_ar,
3209 !!(path_flags & MLX5_PATH_FLAG_FREE_AR));
3210 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
3211 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
3212 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
3213 MLX5_SET(ads, path, sl, sl);
2811ba51
AS		 3214 }
3215
d8966fcd 3216 if (ah_flags & IB_AH_GRH) {
f18e26af
LR		 3217 MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
3218 MLX5_SET(ads, path, hop_limit, grh->hop_limit);
3219 MLX5_SET(ads, path, tclass, grh->traffic_class);
3220 MLX5_SET(ads, path, flow_label, grh->flow_label);
3221 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
3222 sizeof(grh->dgid.raw));
e126ba97
EC		 3223 }
3224
d8966fcd 3225 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 3226 if (err < 0)
3227 return err;
f18e26af
LR		 3228 MLX5_SET(ads, path, stat_rate, err);
3229 MLX5_SET(ads, path, vhca_port_num, port);
e126ba97 3230
e126ba97 3231 if (attr_mask & IB_QP_TIMEOUT)
f18e26af
LR		 3232 MLX5_SET(ads, path, ack_timeout,
3233 alt ? attr->alt_timeout : attr->timeout);
e126ba97 3234
75850d0b 3235 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3236 return modify_raw_packet_eth_prio(dev->mdev,
3237 &qp->raw_packet_qp.sq,
1cd6dbd3 3238 sl & 0xf, qp->ibqp.pd);
75850d0b 3239
e126ba97
EC		 3240 return 0;
3241}
3242
3243static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3244 [MLX5_QP_STATE_INIT] = {
3245 [MLX5_QP_STATE_INIT] = {
3246 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3247 MLX5_QP_OPTPAR_RAE |
3248 MLX5_QP_OPTPAR_RWE |
3249 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3250 MLX5_QP_OPTPAR_PRI_PORT |
3251 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3252 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3253 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3254 MLX5_QP_OPTPAR_PRI_PORT |
3255 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3256 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3257 MLX5_QP_OPTPAR_Q_KEY |
3258 MLX5_QP_OPTPAR_PRI_PORT,
8f4426aa
JM		 3259 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3260 MLX5_QP_OPTPAR_RAE |
3261 MLX5_QP_OPTPAR_RWE |
3262 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3263 MLX5_QP_OPTPAR_PRI_PORT |
3264 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3265 },
3266 [MLX5_QP_STATE_RTR] = {
3267 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3268 MLX5_QP_OPTPAR_RRE |
3269 MLX5_QP_OPTPAR_RAE |
3270 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3271 MLX5_QP_OPTPAR_PKEY_INDEX |
3272 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3273 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3274 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3275 MLX5_QP_OPTPAR_PKEY_INDEX |
3276 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3277 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3278 MLX5_QP_OPTPAR_Q_KEY,
3279 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
3280 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 3281 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3282 MLX5_QP_OPTPAR_RRE |
3283 MLX5_QP_OPTPAR_RAE |
3284 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3285 MLX5_QP_OPTPAR_PKEY_INDEX |
3286 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3287 },
3288 },
3289 [MLX5_QP_STATE_RTR] = {
3290 [MLX5_QP_STATE_RTS] = {
3291 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3292 MLX5_QP_OPTPAR_RRE |
3293 MLX5_QP_OPTPAR_RAE |
3294 MLX5_QP_OPTPAR_RWE |
3295 MLX5_QP_OPTPAR_PM_STATE |
3296 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3297 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3298 MLX5_QP_OPTPAR_RWE |
3299 MLX5_QP_OPTPAR_PM_STATE,
3300 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
8f4426aa
JM		 3301 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3302 MLX5_QP_OPTPAR_RRE |
3303 MLX5_QP_OPTPAR_RAE |
3304 MLX5_QP_OPTPAR_RWE |
3305 MLX5_QP_OPTPAR_PM_STATE |
3306 MLX5_QP_OPTPAR_RNR_TIMEOUT,
e126ba97
EC		 3307 },
3308 },
3309 [MLX5_QP_STATE_RTS] = {
3310 [MLX5_QP_STATE_RTS] = {
3311 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3312 MLX5_QP_OPTPAR_RAE |
3313 MLX5_QP_OPTPAR_RWE |
3314 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 3315 MLX5_QP_OPTPAR_PM_STATE |
3316 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 3317 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 3318 MLX5_QP_OPTPAR_PM_STATE |
3319 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 3320 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
3321 MLX5_QP_OPTPAR_SRQN |
3322 MLX5_QP_OPTPAR_CQN_RCV,
8f4426aa
JM		 3323 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3324 MLX5_QP_OPTPAR_RAE |
3325 MLX5_QP_OPTPAR_RWE |
3326 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3327 MLX5_QP_OPTPAR_PM_STATE |
3328 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 3329 },
3330 },
3331 [MLX5_QP_STATE_SQER] = {
3332 [MLX5_QP_STATE_RTS] = {
3333 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3334 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 3335 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 3336 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3337 MLX5_QP_OPTPAR_RWE |
3338 MLX5_QP_OPTPAR_RAE |
3339 MLX5_QP_OPTPAR_RRE,
8f4426aa
JM		 3340 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3341 MLX5_QP_OPTPAR_RWE |
3342 MLX5_QP_OPTPAR_RAE |
3343 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 3344 },
3345 },
3346};
3347
3348static int ib_nr_to_mlx5_nr(int ib_mask)
3349{
3350 switch (ib_mask) {
3351 case IB_QP_STATE:
3352 return 0;
3353 case IB_QP_CUR_STATE:
3354 return 0;
3355 case IB_QP_EN_SQD_ASYNC_NOTIFY:
3356 return 0;
3357 case IB_QP_ACCESS_FLAGS:
3358 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3359 MLX5_QP_OPTPAR_RAE;
3360 case IB_QP_PKEY_INDEX:
3361 return MLX5_QP_OPTPAR_PKEY_INDEX;
3362 case IB_QP_PORT:
3363 return MLX5_QP_OPTPAR_PRI_PORT;
3364 case IB_QP_QKEY:
3365 return MLX5_QP_OPTPAR_Q_KEY;
3366 case IB_QP_AV:
3367 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3368 MLX5_QP_OPTPAR_PRI_PORT;
3369 case IB_QP_PATH_MTU:
3370 return 0;
3371 case IB_QP_TIMEOUT:
3372 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3373 case IB_QP_RETRY_CNT:
3374 return MLX5_QP_OPTPAR_RETRY_COUNT;
3375 case IB_QP_RNR_RETRY:
3376 return MLX5_QP_OPTPAR_RNR_RETRY;
3377 case IB_QP_RQ_PSN:
3378 return 0;
3379 case IB_QP_MAX_QP_RD_ATOMIC:
3380 return MLX5_QP_OPTPAR_SRA_MAX;
3381 case IB_QP_ALT_PATH:
3382 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3383 case IB_QP_MIN_RNR_TIMER:
3384 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3385 case IB_QP_SQ_PSN:
3386 return 0;
3387 case IB_QP_MAX_DEST_RD_ATOMIC:
3388 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3389 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3390 case IB_QP_PATH_MIG_STATE:
3391 return MLX5_QP_OPTPAR_PM_STATE;
3392 case IB_QP_CAP:
3393 return 0;
3394 case IB_QP_DEST_QPN:
3395 return 0;
3396 }
3397 return 0;
3398}
3399
3400static int ib_mask_to_mlx5_opt(int ib_mask)
3401{
3402 int result = 0;
3403 int i;
3404
3405 for (i = 0; i < 8 * sizeof(int); i++) {
3406 if ((1 << i) & ib_mask)
3407 result |= ib_nr_to_mlx5_nr(1 << i);
3408 }
3409
3410 return result;
3411}
3412
34d57585
YH		 3413static int modify_raw_packet_qp_rq(
3414 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3415 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3416{
3417 void *in;
3418 void *rqc;
3419 int inlen;
3420 int err;
3421
3422 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 3423 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3424 if (!in)
3425 return -ENOMEM;
3426
3427 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
34d57585 3428 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3429
3430 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3431 MLX5_SET(rqc, rqc, state, new_state);
3432
eb49ab0c
AV		 3433 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3434 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3435 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 3436 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 3437 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3438 } else
5a738b5d
JG		 3439 dev_info_once(
3440 &dev->ib_dev.dev,
3441 "RAW PACKET QP counters are not supported on current FW\n");
eb49ab0c
AV		 3442 }
3443
e0b4b472 3444 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
ad5f8e96 3445 if (err)
3446 goto out;
3447
3448 rq->state = new_state;
3449
3450out:
3451 kvfree(in);
3452 return err;
3453}
3454
c14003f0
YH		 3455static int modify_raw_packet_qp_sq(
3456 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3457 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3458{
7d29f349 3459 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 3460 struct mlx5_rate_limit old_rl = ibqp->rl;
3461 struct mlx5_rate_limit new_rl = old_rl;
3462 bool new_rate_added = false;
7d29f349 3463 u16 rl_index = 0;
ad5f8e96 3464 void *in;
3465 void *sqc;
3466 int inlen;
3467 int err;
3468
3469 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 3470 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3471 if (!in)
3472 return -ENOMEM;
3473
c14003f0 3474 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3475 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3476
3477 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3478 MLX5_SET(sqc, sqc, state, new_state);
3479
7d29f349
BW		 3480 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3481 if (new_state != MLX5_SQC_STATE_RDY)
3482 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3483 __func__);
3484 else
61147f39 3485 new_rl = raw_qp_param->rl;
7d29f349
BW		 3486 }
3487
61147f39
BW		 3488 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3489 if (new_rl.rate) {
3490 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 3491 if (err) {
61147f39
BW		 3492 pr_err("Failed configuring rate limit(err %d): \
3493 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3494 err, new_rl.rate, new_rl.max_burst_sz,
3495 new_rl.typical_pkt_sz);
3496
7d29f349
BW		 3497 goto out;
3498 }
61147f39 3499 new_rate_added = true;
7d29f349
BW		 3500 }
3501
3502 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 3503 /* index 0 means no limit */
7d29f349
BW		 3504 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3505 }
3506
e0b4b472 3507 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
7d29f349
BW		 3508 if (err) {
3509 /* Remove new rate from table if failed */
61147f39
BW		 3510 if (new_rate_added)
3511 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 3512 goto out;
7d29f349
BW		 3513 }
3514
3515 /* Only remove the old rate after new rate was set */
c8973df2
RW		 3516 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3517 (new_state != MLX5_SQC_STATE_RDY)) {
61147f39 3518 mlx5_rl_remove_rate(dev, &old_rl);
c8973df2
RW		 3519 if (new_state != MLX5_SQC_STATE_RDY)
3520 memset(&new_rl, 0, sizeof(new_rl));
3521 }
ad5f8e96 3522
61147f39 3523 ibqp->rl = new_rl;
ad5f8e96 3524 sq->state = new_state;
3525
3526out:
3527 kvfree(in);
3528 return err;
3529}
3530
3531static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 3532 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3533 u8 tx_affinity)
ad5f8e96 3534{
3535 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3536 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3537 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 3538 int modify_rq = !!qp->rq.wqe_cnt;
3539 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 3540 int rq_state;
3541 int sq_state;
3542 int err;
3543
0680efa2 3544 switch (raw_qp_param->operation) {
ad5f8e96 3545 case MLX5_CMD_OP_RST2INIT_QP:
3546 rq_state = MLX5_RQC_STATE_RDY;
c94e272b 3547 sq_state = MLX5_SQC_STATE_RST;
ad5f8e96 3548 break;
3549 case MLX5_CMD_OP_2ERR_QP:
3550 rq_state = MLX5_RQC_STATE_ERR;
3551 sq_state = MLX5_SQC_STATE_ERR;
3552 break;
3553 case MLX5_CMD_OP_2RST_QP:
3554 rq_state = MLX5_RQC_STATE_RST;
3555 sq_state = MLX5_SQC_STATE_RST;
3556 break;
ad5f8e96 3557 case MLX5_CMD_OP_RTR2RTS_QP:
3558 case MLX5_CMD_OP_RTS2RTS_QP:
c94e272b
MG		 3559 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT)
3560 return -EINVAL;
3561
3562 modify_rq = 0;
3563 sq_state = MLX5_SQC_STATE_RDY;
7d29f349
BW		 3564 break;
3565 case MLX5_CMD_OP_INIT2INIT_QP:
3566 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 3567 if (raw_qp_param->set_mask)
3568 return -EINVAL;
3569 else
3570 return 0;
ad5f8e96 3571 default:
3572 WARN_ON(1);
3573 return -EINVAL;
3574 }
3575
7d29f349 3576 if (modify_rq) {
34d57585
YH		 3577 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3578 qp->ibqp.pd);
ad5f8e96 3579 if (err)
3580 return err;
3581 }
3582
7d29f349 3583 if (modify_sq) {
d5ed8ac3
MB		 3584 struct mlx5_flow_handle *flow_rule;
3585
13eab21f
AH		 3586 if (tx_affinity) {
3587 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
1cd6dbd3
YH		 3588 tx_affinity,
3589 qp->ibqp.pd);
13eab21f
AH		 3590 if (err)
3591 return err;
3592 }
3593
d5ed8ac3
MB		 3594 flow_rule = create_flow_rule_vport_sq(dev, sq,
3595 raw_qp_param->port);
3596 if (IS_ERR(flow_rule))
1db86318 3597 return PTR_ERR(flow_rule);
d5ed8ac3
MB		 3598
3599 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3600 raw_qp_param, qp->ibqp.pd);
3601 if (err) {
3602 if (flow_rule)
3603 mlx5_del_flow_rules(flow_rule);
3604 return err;
3605 }
3606
3607 if (flow_rule) {
3608 destroy_flow_rule_vport_sq(sq);
3609 sq->flow_rule = flow_rule;
3610 }
3611
3612 return err;
13eab21f 3613 }
ad5f8e96 3614
3615 return 0;
3616}
3617
5163b274
MG		 3618static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev,
3619 struct ib_udata *udata)
c6a21c38 3620{
89944450
SR		 3621 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3622 udata, struct mlx5_ib_ucontext, ibucontext);
5163b274
MG		 3623 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3624 atomic_t *tx_port_affinity;
c6a21c38 3625
5163b274
MG		 3626 if (ucontext)
3627 tx_port_affinity = &ucontext->tx_port_affinity;
3628 else
3629 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity;
3630
3631 return (unsigned int)atomic_add_return(1, tx_port_affinity) %
3632 MLX5_MAX_PORTS + 1;
3633}
3634
3635static bool qp_supports_affinity(struct ib_qp *qp)
3636{
5163b274 3637 if ((qp->qp_type == IB_QPT_RC) ||
cfc1a89e 3638 (qp->qp_type == IB_QPT_UD) ||
5163b274
MG		 3639 (qp->qp_type == IB_QPT_UC) ||
3640 (qp->qp_type == IB_QPT_RAW_PACKET) ||
3641 (qp->qp_type == IB_QPT_XRC_INI) ||
3642 (qp->qp_type == IB_QPT_XRC_TGT))
3643 return true;
3644 return false;
3645}
3646
cfc1a89e
MG		 3647static unsigned int get_tx_affinity(struct ib_qp *qp,
3648 const struct ib_qp_attr *attr,
3649 int attr_mask, u8 init,
5163b274
MG		 3650 struct ib_udata *udata)
3651{
3652 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3653 udata, struct mlx5_ib_ucontext, ibucontext);
3654 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3655 struct mlx5_ib_qp *mqp = to_mqp(qp);
3656 struct mlx5_ib_qp_base *qp_base;
3657 unsigned int tx_affinity;
3658
802dcc7f
MZ		 3659 if (!(mlx5_ib_lag_should_assign_affinity(dev) &&
3660 qp_supports_affinity(qp)))
5163b274
MG		 3661 return 0;
3662
cfc1a89e
MG		 3663 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3664 tx_affinity = mqp->gsi_lag_port;
3665 else if (init)
3666 tx_affinity = get_tx_affinity_rr(dev, udata);
3667 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave)
3668 tx_affinity =
3669 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3670 else
3671 return 0;
5163b274
MG		 3672
3673 qp_base = &mqp->trans_qp.base;
3674 if (ucontext)
c6a21c38 3675 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
5163b274
MG		 3676 tx_affinity, qp_base->mqp.qpn, ucontext);
3677 else
c6a21c38 3678 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
5163b274
MG		 3679 tx_affinity, qp_base->mqp.qpn);
3680 return tx_affinity;
c6a21c38
MD		 3681}
3682
d14133dd
MZ		 3683static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3684 struct rdma_counter *counter)
3685{
3686 struct mlx5_ib_dev *dev = to_mdev(qp->device);
64bae2d4 3687 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {};
d14133dd 3688 struct mlx5_ib_qp *mqp = to_mqp(qp);
d14133dd
MZ		 3689 struct mlx5_ib_qp_base *base;
3690 u32 set_id;
64bae2d4 3691 u32 *qpc;
d14133dd 3692
3e1f000f 3693 if (counter)
d14133dd 3694 set_id = counter->id;
3e1f000f
PP		 3695 else
3696 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
d14133dd
MZ		 3697
3698 base = &mqp->trans_qp.base;
64bae2d4
LR		 3699 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
3700 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);
3701 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid);
3702 MLX5_SET(rts2rts_qp_in, in, opt_param_mask,
3703 MLX5_QP_OPTPAR_COUNTER_SET_ID);
3704
3705 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc);
3706 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3707 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
d14133dd
MZ		 3708}
3709
e126ba97
EC		 3710static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3711 const struct ib_qp_attr *attr, int attr_mask,
89944450
SR		 3712 enum ib_qp_state cur_state,
3713 enum ib_qp_state new_state,
3714 const struct mlx5_ib_modify_qp *ucmd,
50aec2c3 3715 struct mlx5_ib_modify_qp_resp *resp,
89944450 3716 struct ib_udata *udata)
e126ba97 3717{
427c1e7b 3718 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3719 [MLX5_QP_STATE_RST] = {
3720 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3721 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3722 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3723 },
3724 [MLX5_QP_STATE_INIT] = {
3725 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3726 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3727 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3728 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3729 },
3730 [MLX5_QP_STATE_RTR] = {
3731 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3732 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3733 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3734 },
3735 [MLX5_QP_STATE_RTS] = {
3736 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3737 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3738 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3739 },
3740 [MLX5_QP_STATE_SQD] = {
3741 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3742 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3743 },
3744 [MLX5_QP_STATE_SQER] = {
3745 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3746 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3747 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3748 },
3749 [MLX5_QP_STATE_ERR] = {
3750 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3751 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3752 }
3753 };
3754
e126ba97
EC		 3755 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3756 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 3757 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97 3758 struct mlx5_ib_cq *send_cq, *recv_cq;
e126ba97
EC		 3759 struct mlx5_ib_pd *pd;
3760 enum mlx5_qp_state mlx5_cur, mlx5_new;
f18e26af 3761 void *qpc, *pri_path, *alt_path;
cfc1a89e 3762 enum mlx5_qp_optpar optpar = 0;
d14133dd 3763 u32 set_id = 0;
e126ba97
EC		 3764 int mlx5_st;
3765 int err;
427c1e7b 3766 u16 op;
13eab21f 3767 u8 tx_affinity = 0;
e126ba97 3768
7aede1a2 3769 mlx5_st = to_mlx5_st(qp->type);
55de9a77
LR		 3770 if (mlx5_st < 0)
3771 return -EINVAL;
3772
f18e26af
LR		 3773 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
3774 if (!qpc)
e126ba97
EC		 3775 return -ENOMEM;
3776
029e88fd 3777 pd = to_mpd(qp->ibqp.pd);
f18e26af 3778 MLX5_SET(qpc, qpc, st, mlx5_st);
e126ba97
EC		 3779
3780 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
f18e26af 3781 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 3782 } else {
3783 switch (attr->path_mig_state) {
3784 case IB_MIG_MIGRATED:
f18e26af 3785 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 3786 break;
3787 case IB_MIG_REARM:
f18e26af 3788 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
e126ba97
EC		 3789 break;
3790 case IB_MIG_ARMED:
f18e26af 3791 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
e126ba97
EC		 3792 break;
3793 }
3794 }
3795
cfc1a89e 3796 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
5163b274
MG		 3797 cur_state == IB_QPS_RESET &&
3798 new_state == IB_QPS_INIT, udata);
f18e26af
LR		 3799
3800 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
3801 if (tx_affinity && new_state == IB_QPS_RTR &&
3802 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3803 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
13eab21f 3804
d16e91da 3805 if (is_sqp(ibqp->qp_type)) {
f18e26af
LR		 3806 MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
3807 MLX5_SET(qpc, qpc, log_msg_max, 8);
c2e53b2c 3808 } else if ((ibqp->qp_type == IB_QPT_UD &&
2be08c30 3809 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
e126ba97 3810 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
f18e26af
LR		 3811 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
3812 MLX5_SET(qpc, qpc, log_msg_max, 12);
e126ba97
EC		 3813 } else if (attr_mask & IB_QP_PATH_MTU) {
3814 if (attr->path_mtu < IB_MTU_256 ||
3815 attr->path_mtu > IB_MTU_4096) {
3816 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3817 err = -EINVAL;
3818 goto out;
3819 }
f18e26af
LR		 3820 MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
3821 MLX5_SET(qpc, qpc, log_msg_max,
3822 MLX5_CAP_GEN(dev->mdev, log_max_msg));
e126ba97
EC		 3823 }
3824
3825 if (attr_mask & IB_QP_DEST_QPN)
f18e26af
LR		 3826 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
3827
3828 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
3829 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
e126ba97
EC		 3830
3831 if (attr_mask & IB_QP_PKEY_INDEX)
f18e26af 3832 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
e126ba97
EC		 3833
3834 /* todo implement counter_index functionality */
3835
3836 if (is_sqp(ibqp->qp_type))
f18e26af 3837 MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
e126ba97
EC		 3838
3839 if (attr_mask & IB_QP_PORT)
f18e26af 3840 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
e126ba97
EC		 3841
3842 if (attr_mask & IB_QP_AV) {
f18e26af
LR		 3843 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
3844 attr_mask & IB_QP_PORT ? attr->port_num :
3845 qp->port,
f879ee8d 3846 attr_mask, 0, attr, false);
e126ba97
EC		 3847 if (err)
3848 goto out;
3849 }
3850
3851 if (attr_mask & IB_QP_TIMEOUT)
f18e26af 3852 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
e126ba97
EC		 3853
3854 if (attr_mask & IB_QP_ALT_PATH) {
f18e26af 3855 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
f879ee8d 3856 attr->alt_port_num,
f18e26af
LR		 3857 attr_mask | IB_QP_PKEY_INDEX |
3858 IB_QP_TIMEOUT,
f879ee8d 3859 0, attr, true);
e126ba97
EC		 3860 if (err)
3861 goto out;
3862 }
3863
89ea94a7
MG		 3864 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3865 &send_cq, &recv_cq);
e126ba97 3866
f18e26af
LR		 3867 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3868 if (send_cq)
3869 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
3870 if (recv_cq)
3871 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
3872
3873 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
e126ba97
EC		 3874
3875 if (attr_mask & IB_QP_RNR_RETRY)
f18e26af 3876 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
e126ba97
EC		 3877
3878 if (attr_mask & IB_QP_RETRY_CNT)
f18e26af 3879 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
e126ba97 3880
f18e26af
LR		 3881 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
3882 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
e126ba97
EC		 3883
3884 if (attr_mask & IB_QP_SQ_PSN)
f18e26af 3885 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
e126ba97 3886
f18e26af
LR		 3887 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
3888 MLX5_SET(qpc, qpc, log_rra_max,
3889 ilog2(attr->max_dest_rd_atomic));
e126ba97 3890
a60109dc 3891 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
f18e26af 3892 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
a60109dc
YC		 3893 if (err)
3894 goto out;
a60109dc 3895 }
e126ba97
EC		 3896
3897 if (attr_mask & IB_QP_MIN_RNR_TIMER)
f18e26af 3898 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
e126ba97
EC		 3899
3900 if (attr_mask & IB_QP_RQ_PSN)
f18e26af 3901 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
e126ba97
EC		 3902
3903 if (attr_mask & IB_QP_QKEY)
f18e26af 3904 MLX5_SET(qpc, qpc, q_key, attr->qkey);
e126ba97
EC		 3905
3906 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
f18e26af 3907 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 3908
0837e86a
MB		 3909 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3910 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3911 qp->port) - 1;
c2e53b2c
YH		 3912
3913 /* Underlay port should be used - index 0 function per port */
2be08c30 3914 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
c2e53b2c
YH		 3915 port_num = 0;
3916
d14133dd
MZ		 3917 if (ibqp->counter)
3918 set_id = ibqp->counter->id;
3919 else
3e1f000f 3920 set_id = mlx5_ib_get_counters_id(dev, port_num);
f18e26af 3921 MLX5_SET(qpc, qpc, counter_set_id, set_id);
0837e86a
MB		 3922 }
3923
e126ba97 3924 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
f18e26af 3925 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 3926
2be08c30 3927 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
f18e26af 3928 MLX5_SET(qpc, qpc, deth_sqpn, 1);
e126ba97
EC		 3929
3930 mlx5_cur = to_mlx5_state(cur_state);
3931 mlx5_new = to_mlx5_state(new_state);
e126ba97 3932
427c1e7b 3933 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3934 !optab[mlx5_cur][mlx5_new]) {
3935 err = -EINVAL;
427c1e7b 3936 goto out;
5d414b17 3937 }
427c1e7b 3938
3939 op = optab[mlx5_cur][mlx5_new];
cfc1a89e 3940 optpar |= ib_mask_to_mlx5_opt(attr_mask);
e126ba97 3941 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3942
c2e53b2c 3943 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 3944 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0680efa2
AV		 3945 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3946
3947 raw_qp_param.operation = op;
eb49ab0c 3948 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
d14133dd 3949 raw_qp_param.rq_q_ctr_id = set_id;
eb49ab0c
AV		 3950 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3951 }
7d29f349 3952
d5ed8ac3
MB		 3953 if (attr_mask & IB_QP_PORT)
3954 raw_qp_param.port = attr->port_num;
3955
7d29f349 3956 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3957 raw_qp_param.rl.rate = attr->rate_limit;
3958
3959 if (ucmd->burst_info.max_burst_sz) {
3960 if (attr->rate_limit &&
3961 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3962 raw_qp_param.rl.max_burst_sz =
3963 ucmd->burst_info.max_burst_sz;
3964 } else {
3965 err = -EINVAL;
3966 goto out;
3967 }
3968 }
3969
3970 if (ucmd->burst_info.typical_pkt_sz) {
3971 if (attr->rate_limit &&
3972 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3973 raw_qp_param.rl.typical_pkt_sz =
3974 ucmd->burst_info.typical_pkt_sz;
3975 } else {
3976 err = -EINVAL;
3977 goto out;
3978 }
3979 }
3980
7d29f349
BW		 3981 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3982 }
3983
13eab21f 3984 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3985 } else {
50aec2c3
LR		 3986 if (udata) {
3987 /* For the kernel flows, the resp will stay zero */
3988 resp->ece_options =
3989 MLX5_CAP_GEN(dev->mdev, ece_support) ?
3990 ucmd->ece_options : 0;
3991 resp->response_length = sizeof(*resp);
3992 }
5f62a521 3993 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp,
50aec2c3 3994 &resp->ece_options);
0680efa2
AV		 3995 }
3996
e126ba97
EC		 3997 if (err)
3998 goto out;
3999
4000 qp->state = new_state;
4001
4002 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 4003 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 4004 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 4005 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 4006 if (attr_mask & IB_QP_PORT)
4007 qp->port = attr->port_num;
4008 if (attr_mask & IB_QP_ALT_PATH)
19098df2 4009 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 4010
4011 /*
4012 * If we moved a kernel QP to RESET, clean up all old CQ
4013 * entries and reinitialize the QP.
4014 */
75a45982
LR		 4015 if (new_state == IB_QPS_RESET &&
4016 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 4017 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 4018 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
4019 if (send_cq != recv_cq)
19098df2 4020 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 4021
4022 qp->rq.head = 0;
4023 qp->rq.tail = 0;
4024 qp->sq.head = 0;
4025 qp->sq.tail = 0;
4026 qp->sq.cur_post = 0;
34f4c955
GL		 4027 if (qp->sq.wqe_cnt)
4028 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
950bf4f1 4029 qp->sq.last_poll = 0;
e126ba97
EC		 4030 qp->db.db[MLX5_RCV_DBR] = 0;
4031 qp->db.db[MLX5_SND_DBR] = 0;
4032 }
4033
d14133dd
MZ		 4034 if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
4035 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
4036 if (!err)
4037 qp->counter_pending = 0;
4038 }
4039
e126ba97 4040out:
f18e26af 4041 kfree(qpc);
e126ba97
EC		 4042 return err;
4043}
4044
c32a4f29
MS		 4045static inline bool is_valid_mask(int mask, int req, int opt)
4046{
4047 if ((mask & req) != req)
4048 return false;
4049
4050 if (mask & ~(req | opt))
4051 return false;
4052
4053 return true;
4054}
4055
4056/* check valid transition for driver QP types
4057 * for now the only QP type that this function supports is DCI
4058 */
4059static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
4060 enum ib_qp_attr_mask attr_mask)
4061{
4062 int req = IB_QP_STATE;
4063 int opt = 0;
4064
99ed748e
MS		 4065 if (new_state == IB_QPS_RESET) {
4066 return is_valid_mask(attr_mask, req, opt);
4067 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
c32a4f29
MS		 4068 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
4069 return is_valid_mask(attr_mask, req, opt);
4070 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4071 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
4072 return is_valid_mask(attr_mask, req, opt);
4073 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4074 req |= IB_QP_PATH_MTU;
5ec0304c 4075 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
c32a4f29
MS		 4076 return is_valid_mask(attr_mask, req, opt);
4077 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4078 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
4079 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
4080 opt = IB_QP_MIN_RNR_TIMER;
4081 return is_valid_mask(attr_mask, req, opt);
4082 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
4083 opt = IB_QP_MIN_RNR_TIMER;
4084 return is_valid_mask(attr_mask, req, opt);
4085 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
4086 return is_valid_mask(attr_mask, req, opt);
4087 }
4088 return false;
4089}
4090
776a3906
MS		 4091/* mlx5_ib_modify_dct: modify a DCT QP
4092 * valid transitions are:
4093 * RESET to INIT: must set access_flags, pkey_index and port
4094 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
4095 * mtu, gid_index and hop_limit
4096 * Other transitions and attributes are illegal
4097 */
4098static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
a645a89d
LR		 4099 int attr_mask, struct mlx5_ib_modify_qp *ucmd,
4100 struct ib_udata *udata)
776a3906
MS		 4101{
4102 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4103 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4104 enum ib_qp_state cur_state, new_state;
4105 int err = 0;
4106 int required = IB_QP_STATE;
4107 void *dctc;
4108
4109 if (!(attr_mask & IB_QP_STATE))
4110 return -EINVAL;
4111
4112 cur_state = qp->state;
4113 new_state = attr->qp_state;
4114
4115 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
a645a89d
LR		 4116 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options)
4117 /*
4118 * DCT doesn't initialize QP till modify command is executed,
4119 * so we need to overwrite previously set ECE field if user
4120 * provided any value except zero, which means not set/not
4121 * valid.
4122 */
4123 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
4124
776a3906 4125 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3e1f000f
PP		 4126 u16 set_id;
4127
776a3906
MS		 4128 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4129 if (!is_valid_mask(attr_mask, required, 0))
4130 return -EINVAL;
4131
4132 if (attr->port_num == 0 ||
4133 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
4134 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4135 attr->port_num, dev->num_ports);
4136 return -EINVAL;
4137 }
4138 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4139 MLX5_SET(dctc, dctc, rre, 1);
4140 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4141 MLX5_SET(dctc, dctc, rwe, 1);
4142 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 4143 int atomic_mode;
4144
4145 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4146 if (atomic_mode < 0)
776a3906 4147 return -EOPNOTSUPP;
a60109dc
YC		 4148
4149 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
776a3906 4150 MLX5_SET(dctc, dctc, rae, 1);
776a3906
MS		 4151 }
4152 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
4153 MLX5_SET(dctc, dctc, port, attr->port_num);
3e1f000f
PP		 4154
4155 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4156 MLX5_SET(dctc, dctc, counter_set_id, set_id);
776a3906
MS		 4157 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4158 struct mlx5_ib_modify_qp_resp resp = {};
a645a89d
LR		 4159 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {};
4160 u32 min_resp_len = offsetofend(typeof(resp), dctn);
776a3906
MS		 4161
4162 if (udata->outlen < min_resp_len)
4163 return -EINVAL;
4164 resp.response_length = min_resp_len;
4165
a645a89d
LR		 4166 /*
4167 * If we don't have enough space for the ECE options,
4168 * simply indicate it with resp.response_length.
4169 */
4170 resp.response_length = (udata->outlen < sizeof(resp)) ?
4171 min_resp_len :
4172 sizeof(resp);
4173
776a3906
MS		 4174 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4175 if (!is_valid_mask(attr_mask, required, 0))
4176 return -EINVAL;
4177 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4178 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4179 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4180 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4181 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4182 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4183
333fbaa0 4184 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
c5ae1954
YH		 4185 MLX5_ST_SZ_BYTES(create_dct_in), out,
4186 sizeof(out));
776a3906
MS		 4187 if (err)
4188 return err;
4189 resp.dctn = qp->dct.mdct.mqp.qpn;
a645a89d
LR		 4190 if (MLX5_CAP_GEN(dev->mdev, ece_support))
4191 resp.ece_options = MLX5_GET(create_dct_out, out, ece);
776a3906
MS		 4192 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4193 if (err) {
333fbaa0 4194 mlx5_core_destroy_dct(dev, &qp->dct.mdct);
776a3906
MS		 4195 return err;
4196 }
4197 } else {
4198 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4199 return -EINVAL;
4200 }
4201 if (err)
4202 qp->state = IB_QPS_ERR;
4203 else
4204 qp->state = new_state;
4205 return err;
4206}
4207
e126ba97
EC		 4208int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4209 int attr_mask, struct ib_udata *udata)
4210{
4211 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
50aec2c3 4212 struct mlx5_ib_modify_qp_resp resp = {};
e126ba97 4213 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 4214 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 4215 enum ib_qp_type qp_type;
e126ba97
EC		 4216 enum ib_qp_state cur_state, new_state;
4217 int err = -EINVAL;
4218 int port;
4219
28d61370
YH		 4220 if (ibqp->rwq_ind_tbl)
4221 return -ENOSYS;
4222
61147f39 4223 if (udata && udata->inlen) {
5f62a521 4224 if (udata->inlen < offsetofend(typeof(ucmd), ece_options))
61147f39
BW		 4225 return -EINVAL;
4226
4227 if (udata->inlen > sizeof(ucmd) &&
4228 !ib_is_udata_cleared(udata, sizeof(ucmd),
4229 udata->inlen - sizeof(ucmd)))
4230 return -EOPNOTSUPP;
4231
4232 if (ib_copy_from_udata(&ucmd, udata,
4233 min(udata->inlen, sizeof(ucmd))))
4234 return -EFAULT;
4235
4236 if (ucmd.comp_mask ||
61147f39
BW		 4237 memchr_inv(&ucmd.burst_info.reserved, 0,
4238 sizeof(ucmd.burst_info.reserved)))
4239 return -EOPNOTSUPP;
5f62a521 4240
61147f39
BW		 4241 }
4242
d16e91da
HE		 4243 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4244 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4245
7aede1a2
LR		 4246 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4247 qp->type;
c32a4f29 4248
a645a89d
LR		 4249 if (qp_type == MLX5_IB_QPT_DCT)
4250 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata);
d16e91da 4251
e126ba97
EC		 4252 mutex_lock(&qp->mutex);
4253
4254 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4255 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4256
2811ba51
AS		 4257 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4258 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2811ba51
AS		 4259 }
4260
2be08c30 4261 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
c2e53b2c
YH		 4262 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4263 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4264 attr_mask);
4265 goto out;
4266 }
4267 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29 4268 qp_type != MLX5_IB_QPT_DCI &&
d31131bb
KH		 4269 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4270 attr_mask)) {
158abf86
HE		 4271 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4272 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 4273 goto out;
c32a4f29
MS		 4274 } else if (qp_type == MLX5_IB_QPT_DCI &&
4275 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4276 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4277 cur_state, new_state, qp_type, attr_mask);
4278 goto out;
158abf86 4279 }
e126ba97
EC		 4280
4281 if ((attr_mask & IB_QP_PORT) &&
938fe83c 4282 (attr->port_num == 0 ||
508562d6 4283 attr->port_num > dev->num_ports)) {
158abf86
HE		 4284 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4285 attr->port_num, dev->num_ports);
e126ba97 4286 goto out;
158abf86 4287 }
e126ba97
EC		 4288
4289 if (attr_mask & IB_QP_PKEY_INDEX) {
4290 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 4291 if (attr->pkey_index >=
158abf86
HE		 4292 dev->mdev->port_caps[port - 1].pkey_table_len) {
4293 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4294 attr->pkey_index);
e126ba97 4295 goto out;
158abf86 4296 }
e126ba97
EC		 4297 }
4298
4299 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 4300 attr->max_rd_atomic >
158abf86
HE		 4301 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4302 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4303 attr->max_rd_atomic);
e126ba97 4304 goto out;
158abf86 4305 }
e126ba97
EC		 4306
4307 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 4308 attr->max_dest_rd_atomic >
158abf86
HE		 4309 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4310 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4311 attr->max_dest_rd_atomic);
e126ba97 4312 goto out;
158abf86 4313 }
e126ba97
EC		 4314
4315 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4316 err = 0;
4317 goto out;
4318 }
4319
61147f39 4320 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
50aec2c3
LR		 4321 new_state, &ucmd, &resp, udata);
4322
4323 /* resp.response_length is set in ECE supported flows only */
4324 if (!err && resp.response_length &&
4325 udata->outlen >= resp.response_length)
6512f11d
LR		 4326 /* Return -EFAULT to the user and expect him to destroy QP. */
4327 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97
EC		 4328
4329out:
4330 mutex_unlock(&qp->mutex);
4331 return err;
4332}
4333
e126ba97
EC		 4334static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4335{
4336 switch (mlx5_state) {
4337 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4338 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4339 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4340 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4341 case MLX5_QP_STATE_SQ_DRAINING:
4342 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4343 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4344 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4345 default: return -1;
4346 }
4347}
4348
4349static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4350{
4351 switch (mlx5_mig_state) {
4352 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4353 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4354 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4355 default: return -1;
4356 }
4357}
4358
38349389 4359static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
70bd7fb8 4360 struct rdma_ah_attr *ah_attr, void *path)
e126ba97 4361{
70bd7fb8
LR		 4362 int port = MLX5_GET(ads, path, vhca_port_num);
4363 int static_rate;
e126ba97 4364
d8966fcd 4365 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4366
70bd7fb8 4367 if (!port || port > ibdev->num_ports)
e126ba97
EC		 4368 return;
4369
70bd7fb8 4370 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port);
ae59c3f0 4371
70bd7fb8
LR		 4372 rdma_ah_set_port_num(ah_attr, port);
4373 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl));
d8966fcd 4374
70bd7fb8
LR		 4375 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid));
4376 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid));
2d7e3ff7 4377
70bd7fb8
LR		 4378 static_rate = MLX5_GET(ads, path, stat_rate);
4379 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0);
4380 if (MLX5_GET(ads, path, grh) ||
2d7e3ff7 4381 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
70bd7fb8
LR		 4382 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label),
4383 MLX5_GET(ads, path, src_addr_index),
4384 MLX5_GET(ads, path, hop_limit),
4385 MLX5_GET(ads, path, tclass));
4386 memcpy(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip),
4387 MLX5_FLD_SZ_BYTES(ads, rgid_rip));
e126ba97
EC		 4388 }
4389}
4390
6d2f89df 4391static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4392 struct mlx5_ib_sq *sq,
4393 u8 *sq_state)
4394{
6d2f89df 4395 int err;
4396
28160771 4397 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
6d2f89df 4398 if (err)
4399 goto out;
6d2f89df 4400 sq->state = *sq_state;
4401
4402out:
6d2f89df 4403 return err;
4404}
4405
4406static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4407 struct mlx5_ib_rq *rq,
4408 u8 *rq_state)
4409{
4410 void *out;
4411 void *rqc;
4412 int inlen;
4413 int err;
4414
4415 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4416 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4417 if (!out)
4418 return -ENOMEM;
4419
4420 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4421 if (err)
4422 goto out;
4423
4424 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4425 *rq_state = MLX5_GET(rqc, rqc, state);
4426 rq->state = *rq_state;
4427
4428out:
4429 kvfree(out);
4430 return err;
4431}
4432
4433static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4434 struct mlx5_ib_qp *qp, u8 *qp_state)
4435{
4436 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4437 [MLX5_RQC_STATE_RST] = {
4438 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4439 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4440 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4441 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4442 },
4443 [MLX5_RQC_STATE_RDY] = {
c94e272b 4444 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
6d2f89df 4445 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4446 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4447 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4448 },
4449 [MLX5_RQC_STATE_ERR] = {
4450 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4451 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4452 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4453 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4454 },
4455 [MLX5_RQ_STATE_NA] = {
c94e272b 4456 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
6d2f89df 4457 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4458 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4459 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4460 },
4461 };
4462
4463 *qp_state = sqrq_trans[rq_state][sq_state];
4464
4465 if (*qp_state == MLX5_QP_STATE_BAD) {
4466 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4467 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4468 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4469 return -EINVAL;
4470 }
4471
4472 if (*qp_state == MLX5_QP_STATE)
4473 *qp_state = qp->state;
4474
4475 return 0;
4476}
4477
4478static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4479 struct mlx5_ib_qp *qp,
4480 u8 *raw_packet_qp_state)
4481{
4482 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4483 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4484 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4485 int err;
4486 u8 sq_state = MLX5_SQ_STATE_NA;
4487 u8 rq_state = MLX5_RQ_STATE_NA;
4488
4489 if (qp->sq.wqe_cnt) {
4490 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4491 if (err)
4492 return err;
4493 }
4494
4495 if (qp->rq.wqe_cnt) {
4496 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4497 if (err)
4498 return err;
4499 }
4500
4501 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4502 raw_packet_qp_state);
4503}
4504
4505static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4506 struct ib_qp_attr *qp_attr)
e126ba97 4507{
09a7d9ec 4508 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
70bd7fb8 4509 void *qpc, *pri_path, *alt_path;
09a7d9ec 4510 u32 *outb;
70bd7fb8 4511 int err;
e126ba97 4512
09a7d9ec 4513 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4514 if (!outb)
4515 return -ENOMEM;
4516
333fbaa0 4517 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
e126ba97 4518 if (err)
6d2f89df 4519 goto out;
e126ba97 4520
70bd7fb8
LR		 4521 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc);
4522
4523 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state));
4524 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING)
4525 qp_attr->sq_draining = 1;
4526
4527 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu);
4528 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state));
4529 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key);
4530 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn);
4531 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn);
4532 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn);
09a7d9ec 4533
70bd7fb8
LR		 4534 if (MLX5_GET(qpc, qpc, rre))
4535 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ;
4536 if (MLX5_GET(qpc, qpc, rwe))
4537 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE;
4538 if (MLX5_GET(qpc, qpc, rae))
4539 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC;
e126ba97 4540
70bd7fb8
LR		 4541 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max);
4542 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max);
4543 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak);
4544 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count);
4545 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry);
4546
4547 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
4548 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
e126ba97
EC		 4549
4550 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
70bd7fb8
LR		 4551 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path);
4552 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path);
4553 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index);
4554 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num);
4555 }
4556
4557 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index);
4558 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num);
4559 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout);
4560 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout);
6d2f89df 4561
4562out:
4563 kfree(outb);
4564 return err;
4565}
4566
776a3906
MS		 4567static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4568 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4569 struct ib_qp_init_attr *qp_init_attr)
4570{
4571 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4572 u32 *out;
4573 u32 access_flags = 0;
4574 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4575 void *dctc;
4576 int err;
4577 int supported_mask = IB_QP_STATE |
4578 IB_QP_ACCESS_FLAGS |
4579 IB_QP_PORT |
4580 IB_QP_MIN_RNR_TIMER |
4581 IB_QP_AV |
4582 IB_QP_PATH_MTU |
4583 IB_QP_PKEY_INDEX;
4584
4585 if (qp_attr_mask & ~supported_mask)
4586 return -EINVAL;
4587 if (mqp->state != IB_QPS_RTR)
4588 return -EINVAL;
4589
4590 out = kzalloc(outlen, GFP_KERNEL);
4591 if (!out)
4592 return -ENOMEM;
4593
333fbaa0 4594 err = mlx5_core_dct_query(dev, dct, out, outlen);
776a3906
MS		 4595 if (err)
4596 goto out;
4597
4598 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4599
4600 if (qp_attr_mask & IB_QP_STATE)
4601 qp_attr->qp_state = IB_QPS_RTR;
4602
4603 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4604 if (MLX5_GET(dctc, dctc, rre))
4605 access_flags |= IB_ACCESS_REMOTE_READ;
4606 if (MLX5_GET(dctc, dctc, rwe))
4607 access_flags |= IB_ACCESS_REMOTE_WRITE;
4608 if (MLX5_GET(dctc, dctc, rae))
4609 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4610 qp_attr->qp_access_flags = access_flags;
4611 }
4612
4613 if (qp_attr_mask & IB_QP_PORT)
4614 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4615 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4616 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4617 if (qp_attr_mask & IB_QP_AV) {
4618 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4619 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4620 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4621 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4622 }
4623 if (qp_attr_mask & IB_QP_PATH_MTU)
4624 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4625 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4626 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4627out:
4628 kfree(out);
4629 return err;
4630}
4631
6d2f89df 4632int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4633 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4634{
4635 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4636 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4637 int err = 0;
4638 u8 raw_packet_qp_state;
4639
28d61370
YH		 4640 if (ibqp->rwq_ind_tbl)
4641 return -ENOSYS;
4642
d16e91da
HE		 4643 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4644 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4645 qp_init_attr);
4646
c2e53b2c
YH		 4647 /* Not all of output fields are applicable, make sure to zero them */
4648 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4649 memset(qp_attr, 0, sizeof(*qp_attr));
4650
7aede1a2 4651 if (unlikely(qp->type == MLX5_IB_QPT_DCT))
776a3906
MS		 4652 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4653 qp_attr_mask, qp_init_attr);
4654
6d2f89df 4655 mutex_lock(&qp->mutex);
4656
c2e53b2c 4657 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 4658 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
6d2f89df 4659 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4660 if (err)
4661 goto out;
4662 qp->state = raw_packet_qp_state;
4663 qp_attr->port_num = 1;
4664 } else {
4665 err = query_qp_attr(dev, qp, qp_attr);
4666 if (err)
4667 goto out;
4668 }
4669
4670 qp_attr->qp_state = qp->state;
e126ba97
EC		 4671 qp_attr->cur_qp_state = qp_attr->qp_state;
4672 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4673 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4674
4675 if (!ibqp->uobject) {
0540d814 4676 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4677 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4678 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4679 } else {
4680 qp_attr->cap.max_send_wr = 0;
4681 qp_attr->cap.max_send_sge = 0;
4682 }
4683
0540d814
NO		 4684 qp_init_attr->qp_type = ibqp->qp_type;
4685 qp_init_attr->recv_cq = ibqp->recv_cq;
4686 qp_init_attr->send_cq = ibqp->send_cq;
4687 qp_init_attr->srq = ibqp->srq;
4688 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4689
4690 qp_init_attr->cap = qp_attr->cap;
4691
a8f3ea61 4692 qp_init_attr->create_flags = qp->flags;
051f2630 4693
e126ba97
EC		 4694 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4695 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4696
e126ba97
EC		 4697out:
4698 mutex_unlock(&qp->mutex);
4699 return err;
4700}
4701
28ad5f65 4702int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata)
e126ba97 4703{
28ad5f65
LR		 4704 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device);
4705 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd);
e126ba97 4706
938fe83c 4707 if (!MLX5_CAP_GEN(dev->mdev, xrc))
28ad5f65 4708 return -EOPNOTSUPP;
e126ba97 4709
28ad5f65 4710 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
e126ba97
EC		 4711}
4712
28ad5f65 4713void mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
e126ba97
EC		 4714{
4715 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4716 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
e126ba97 4717
28ad5f65 4718 mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
e126ba97 4719}
79b20a6c 4720
350d0e4c
YH		 4721static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4722{
4723 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4724 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4725 struct ib_event event;
4726
4727 if (rwq->ibwq.event_handler) {
4728 event.device = rwq->ibwq.device;
4729 event.element.wq = &rwq->ibwq;
4730 switch (type) {
4731 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4732 event.event = IB_EVENT_WQ_FATAL;
4733 break;
4734 default:
4735 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4736 return;
4737 }
4738
4739 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4740 }
4741}
4742
03404e8a
MG		 4743static int set_delay_drop(struct mlx5_ib_dev *dev)
4744{
4745 int err = 0;
4746
4747 mutex_lock(&dev->delay_drop.lock);
4748 if (dev->delay_drop.activate)
4749 goto out;
4750
333fbaa0 4751 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
03404e8a
MG		 4752 if (err)
4753 goto out;
4754
4755 dev->delay_drop.activate = true;
4756out:
4757 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 4758
4759 if (!err)
4760 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 4761 return err;
4762}
4763
79b20a6c
YH		 4764static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4765 struct ib_wq_init_attr *init_attr)
4766{
4767 struct mlx5_ib_dev *dev;
4be6da1e 4768 int has_net_offloads;
79b20a6c
YH		 4769 __be64 *rq_pas0;
4770 void *in;
4771 void *rqc;
4772 void *wq;
4773 int inlen;
4774 int err;
4775
4776 dev = to_mdev(pd->device);
4777
4778 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 4779 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 4780 if (!in)
4781 return -ENOMEM;
4782
34d57585 4783 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
79b20a6c
YH		 4784 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4785 MLX5_SET(rqc, rqc, mem_rq_type,
4786 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4787 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4788 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4789 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4790 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4791 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 4792 MLX5_SET(wq, wq, wq_type,
4793 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4794 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 4795 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4796 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4797 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4798 err = -EOPNOTSUPP;
4799 goto out;
4800 } else {
4801 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4802 }
4803 }
79b20a6c 4804 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087 4805 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
c16339b6
MZ		 4806 /*
4807 * In Firmware number of strides in each WQE is:
4808 * "512 * 2^single_wqe_log_num_of_strides"
4809 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
4810 * accepted as 0 to 9
4811 */
4812 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
4813 2, 3, 4, 5, 6, 7, 8, 9 };
ccc87087
NO		 4814 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4815 MLX5_SET(wq, wq, log_wqe_stride_size,
4816 rwq->single_stride_log_num_of_bytes -
4817 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
c16339b6
MZ		 4818 MLX5_SET(wq, wq, log_wqe_num_of_strides,
4819 fw_map[rwq->log_num_strides -
4820 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
ccc87087 4821 }
79b20a6c
YH		 4822 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4823 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4824 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4825 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4826 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4827 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4828 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4829 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4830 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4831 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4832 err = -EOPNOTSUPP;
4833 goto out;
4834 }
4835 } else {
4836 MLX5_SET(rqc, rqc, vsd, 1);
4837 }
4be6da1e
NO		 4838 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4839 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4840 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4841 err = -EOPNOTSUPP;
4842 goto out;
4843 }
4844 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4845 }
03404e8a
MG		 4846 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4847 if (!(dev->ib_dev.attrs.raw_packet_caps &
4848 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4849 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4850 err = -EOPNOTSUPP;
4851 goto out;
4852 }
4853 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4854 }
79b20a6c
YH		 4855 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4856 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
333fbaa0 4857 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
03404e8a
MG		 4858 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4859 err = set_delay_drop(dev);
4860 if (err) {
4861 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4862 err);
333fbaa0 4863 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
03404e8a
MG		 4864 } else {
4865 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4866 }
4867 }
b1f74a84 4868out:
79b20a6c
YH		 4869 kvfree(in);
4870 return err;
4871}
4872
4873static int set_user_rq_size(struct mlx5_ib_dev *dev,
4874 struct ib_wq_init_attr *wq_init_attr,
4875 struct mlx5_ib_create_wq *ucmd,
4876 struct mlx5_ib_rwq *rwq)
4877{
4878 /* Sanity check RQ size before proceeding */
4879 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4880 return -EINVAL;
4881
4882 if (!ucmd->rq_wqe_count)
4883 return -EINVAL;
4884
4885 rwq->wqe_count = ucmd->rq_wqe_count;
4886 rwq->wqe_shift = ucmd->rq_wqe_shift;
0dfe4522
LR		 4887 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
4888 return -EINVAL;
4889
79b20a6c
YH		 4890 rwq->log_rq_stride = rwq->wqe_shift;
4891 rwq->log_rq_size = ilog2(rwq->wqe_count);
4892 return 0;
4893}
4894
c16339b6
MZ		 4895static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
4896{
4897 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4898 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4899 return false;
4900
4901 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
4902 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4903 return false;
4904
4905 return true;
4906}
4907
79b20a6c
YH		 4908static int prepare_user_rq(struct ib_pd *pd,
4909 struct ib_wq_init_attr *init_attr,
4910 struct ib_udata *udata,
4911 struct mlx5_ib_rwq *rwq)
4912{
4913 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4914 struct mlx5_ib_create_wq ucmd = {};
4915 int err;
4916 size_t required_cmd_sz;
4917
ccc87087
NO		 4918 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4919 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 4920 if (udata->inlen < required_cmd_sz) {
4921 mlx5_ib_dbg(dev, "invalid inlen\n");
4922 return -EINVAL;
4923 }
4924
4925 if (udata->inlen > sizeof(ucmd) &&
4926 !ib_is_udata_cleared(udata, sizeof(ucmd),
4927 udata->inlen - sizeof(ucmd))) {
4928 mlx5_ib_dbg(dev, "inlen is not supported\n");
4929 return -EOPNOTSUPP;
4930 }
4931
4932 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4933 mlx5_ib_dbg(dev, "copy failed\n");
4934 return -EFAULT;
4935 }
4936
ccc87087 4937 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 4938 mlx5_ib_dbg(dev, "invalid comp mask\n");
4939 return -EOPNOTSUPP;
ccc87087
NO		 4940 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4941 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4942 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4943 return -EOPNOTSUPP;
4944 }
4945 if ((ucmd.single_stride_log_num_of_bytes <
4946 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4947 (ucmd.single_stride_log_num_of_bytes >
4948 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4949 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4950 ucmd.single_stride_log_num_of_bytes,
4951 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4952 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4953 return -EINVAL;
4954 }
c16339b6
MZ		 4955 if (!log_of_strides_valid(dev,
4956 ucmd.single_wqe_log_num_of_strides)) {
4957 mlx5_ib_dbg(
4958 dev,
4959 "Invalid log num strides (%u. Range is %u - %u)\n",
4960 ucmd.single_wqe_log_num_of_strides,
4961 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
4962 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
4963 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4964 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
ccc87087
NO		 4965 return -EINVAL;
4966 }
4967 rwq->single_stride_log_num_of_bytes =
4968 ucmd.single_stride_log_num_of_bytes;
4969 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4970 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4971 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 4972 }
4973
4974 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4975 if (err) {
4976 mlx5_ib_dbg(dev, "err %d\n", err);
4977 return err;
4978 }
4979
b0ea0fa5 4980 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
79b20a6c
YH		 4981 if (err) {
4982 mlx5_ib_dbg(dev, "err %d\n", err);
645ba597 4983 return err;
79b20a6c
YH		 4984 }
4985
4986 rwq->user_index = ucmd.user_index;
4987 return 0;
4988}
4989
4990struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4991 struct ib_wq_init_attr *init_attr,
4992 struct ib_udata *udata)
4993{
4994 struct mlx5_ib_dev *dev;
4995 struct mlx5_ib_rwq *rwq;
4996 struct mlx5_ib_create_wq_resp resp = {};
4997 size_t min_resp_len;
4998 int err;
4999
5000 if (!udata)
5001 return ERR_PTR(-ENOSYS);
5002
5003 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5004 if (udata->outlen && udata->outlen < min_resp_len)
5005 return ERR_PTR(-EINVAL);
5006
ba80013f
MG		 5007 if (!capable(CAP_SYS_RAWIO) &&
5008 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5009 return ERR_PTR(-EPERM);
5010
79b20a6c
YH		 5011 dev = to_mdev(pd->device);
5012 switch (init_attr->wq_type) {
5013 case IB_WQT_RQ:
5014 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5015 if (!rwq)
5016 return ERR_PTR(-ENOMEM);
5017 err = prepare_user_rq(pd, init_attr, udata, rwq);
5018 if (err)
5019 goto err;
5020 err = create_rq(rwq, pd, init_attr);
5021 if (err)
5022 goto err_user_rq;
5023 break;
5024 default:
5025 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5026 init_attr->wq_type);
5027 return ERR_PTR(-EINVAL);
5028 }
5029
350d0e4c 5030 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5031 rwq->ibwq.state = IB_WQS_RESET;
5032 if (udata->outlen) {
5033 resp.response_length = offsetof(typeof(resp), response_length) +
5034 sizeof(resp.response_length);
5035 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5036 if (err)
5037 goto err_copy;
5038 }
5039
350d0e4c
YH		 5040 rwq->core_qp.event = mlx5_ib_wq_event;
5041 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5042 return &rwq->ibwq;
5043
5044err_copy:
333fbaa0 5045 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
79b20a6c 5046err_user_rq:
bdeacabd 5047 destroy_user_rq(dev, pd, rwq, udata);
79b20a6c
YH		 5048err:
5049 kfree(rwq);
5050 return ERR_PTR(err);
5051}
5052
a49b1dc7 5053void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
79b20a6c
YH		 5054{
5055 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5056 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5057
333fbaa0 5058 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
bdeacabd 5059 destroy_user_rq(dev, wq->pd, rwq, udata);
79b20a6c 5060 kfree(rwq);
79b20a6c
YH		 5061}
5062
c5f90929
YH		 5063struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5064 struct ib_rwq_ind_table_init_attr *init_attr,
5065 struct ib_udata *udata)
5066{
5067 struct mlx5_ib_dev *dev = to_mdev(device);
5068 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5069 int sz = 1 << init_attr->log_ind_tbl_size;
5070 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5071 size_t min_resp_len;
5072 int inlen;
5073 int err;
5074 int i;
5075 u32 *in;
5076 void *rqtc;
5077
5078 if (udata->inlen > 0 &&
5079 !ib_is_udata_cleared(udata, 0,
5080 udata->inlen))
5081 return ERR_PTR(-EOPNOTSUPP);
5082
efd7f400
MG		 5083 if (init_attr->log_ind_tbl_size >
5084 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5085 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5086 init_attr->log_ind_tbl_size,
5087 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5088 return ERR_PTR(-EINVAL);
5089 }
5090
c5f90929
YH		 5091 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5092 if (udata->outlen && udata->outlen < min_resp_len)
5093 return ERR_PTR(-EINVAL);
5094
5095 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5096 if (!rwq_ind_tbl)
5097 return ERR_PTR(-ENOMEM);
5098
5099 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5100 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5101 if (!in) {
5102 err = -ENOMEM;
5103 goto err;
5104 }
5105
5106 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5107
5108 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5109 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5110
5111 for (i = 0; i < sz; i++)
5112 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5113
5deba86e
YH		 5114 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5115 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5116
c5f90929
YH		 5117 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5118 kvfree(in);
5119
5120 if (err)
5121 goto err;
5122
5123 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5124 if (udata->outlen) {
5125 resp.response_length = offsetof(typeof(resp), response_length) +
5126 sizeof(resp.response_length);
5127 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5128 if (err)
5129 goto err_copy;
5130 }
5131
5132 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5133
5134err_copy:
5deba86e 5135 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5136err:
5137 kfree(rwq_ind_tbl);
5138 return ERR_PTR(err);
5139}
5140
5141int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5142{
5143 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5144 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5145
5deba86e 5146 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5147
5148 kfree(rwq_ind_tbl);
5149 return 0;
5150}
5151
79b20a6c
YH		 5152int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5153 u32 wq_attr_mask, struct ib_udata *udata)
5154{
5155 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5156 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5157 struct mlx5_ib_modify_wq ucmd = {};
5158 size_t required_cmd_sz;
5159 int curr_wq_state;
5160 int wq_state;
5161 int inlen;
5162 int err;
5163 void *rqc;
5164 void *in;
5165
5166 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5167 if (udata->inlen < required_cmd_sz)
5168 return -EINVAL;
5169
5170 if (udata->inlen > sizeof(ucmd) &&
5171 !ib_is_udata_cleared(udata, sizeof(ucmd),
5172 udata->inlen - sizeof(ucmd)))
5173 return -EOPNOTSUPP;
5174
5175 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5176 return -EFAULT;
5177
5178 if (ucmd.comp_mask || ucmd.reserved)
5179 return -EOPNOTSUPP;
5180
5181 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5182 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5183 if (!in)
5184 return -ENOMEM;
5185
5186 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5187
5188 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5189 wq_attr->curr_wq_state : wq->state;
5190 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5191 wq_attr->wq_state : curr_wq_state;
5192 if (curr_wq_state == IB_WQS_ERR)
5193 curr_wq_state = MLX5_RQC_STATE_ERR;
5194 if (wq_state == IB_WQS_ERR)
5195 wq_state = MLX5_RQC_STATE_ERR;
5196 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
34d57585 5197 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
79b20a6c
YH		 5198 MLX5_SET(rqc, rqc, state, wq_state);
5199
b1f74a84
NO		 5200 if (wq_attr_mask & IB_WQ_FLAGS) {
5201 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5202 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5203 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5204 mlx5_ib_dbg(dev, "VLAN offloads are not "
5205 "supported\n");
5206 err = -EOPNOTSUPP;
5207 goto out;
5208 }
5209 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5210 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5211 MLX5_SET(rqc, rqc, vsd,
5212 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5213 }
b1383aa6
NO		 5214
5215 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5216 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5217 err = -EOPNOTSUPP;
5218 goto out;
5219 }
b1f74a84
NO		 5220 }
5221
23a6964e 5222 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
3e1f000f
PP		 5223 u16 set_id;
5224
5225 set_id = mlx5_ib_get_counters_id(dev, 0);
23a6964e
MD		 5226 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5227 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5228 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3e1f000f 5229 MLX5_SET(rqc, rqc, counter_set_id, set_id);
23a6964e 5230 } else
5a738b5d
JG		 5231 dev_info_once(
5232 &dev->ib_dev.dev,
5233 "Receive WQ counters are not supported on current FW\n");
23a6964e
MD		 5234 }
5235
e0b4b472 5236 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
79b20a6c
YH		 5237 if (!err)
5238 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5239
b1f74a84
NO		 5240out:
5241 kvfree(in);
79b20a6c
YH		 5242 return err;
5243}
d0e84c0a
YH		 5244
5245struct mlx5_ib_drain_cqe {
5246 struct ib_cqe cqe;
5247 struct completion done;
5248};
5249
5250static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5251{
5252 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5253 struct mlx5_ib_drain_cqe,
5254 cqe);
5255
5256 complete(&cqe->done);
5257}
5258
5259/* This function returns only once the drained WR was completed */
5260static void handle_drain_completion(struct ib_cq *cq,
5261 struct mlx5_ib_drain_cqe *sdrain,
5262 struct mlx5_ib_dev *dev)
5263{
5264 struct mlx5_core_dev *mdev = dev->mdev;
5265
5266 if (cq->poll_ctx == IB_POLL_DIRECT) {
5267 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5268 ib_process_cq_direct(cq, -1);
5269 return;
5270 }
5271
5272 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5273 struct mlx5_ib_cq *mcq = to_mcq(cq);
5274 bool triggered = false;
5275 unsigned long flags;
5276
5277 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5278 /* Make sure that the CQ handler won't run if wasn't run yet */
5279 if (!mcq->mcq.reset_notify_added)
5280 mcq->mcq.reset_notify_added = 1;
5281 else
5282 triggered = true;
5283 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5284
5285 if (triggered) {
5286 /* Wait for any scheduled/running task to be ended */
5287 switch (cq->poll_ctx) {
5288 case IB_POLL_SOFTIRQ:
5289 irq_poll_disable(&cq->iop);
5290 irq_poll_enable(&cq->iop);
5291 break;
5292 case IB_POLL_WORKQUEUE:
5293 cancel_work_sync(&cq->work);
5294 break;
5295 default:
5296 WARN_ON_ONCE(1);
5297 }
5298 }
5299
5300 /* Run the CQ handler - this makes sure that the drain WR will
5301 * be processed if wasn't processed yet.
5302 */
4e0e2ea1 5303 mcq->mcq.comp(&mcq->mcq, NULL);
d0e84c0a
YH		 5304 }
5305
5306 wait_for_completion(&sdrain->done);
5307}
5308
5309void mlx5_ib_drain_sq(struct ib_qp *qp)
5310{
5311 struct ib_cq *cq = qp->send_cq;
5312 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5313 struct mlx5_ib_drain_cqe sdrain;
d34ac5cd 5314 const struct ib_send_wr *bad_swr;
d0e84c0a
YH		 5315 struct ib_rdma_wr swr = {
5316 .wr = {
5317 .next = NULL,
5318 { .wr_cqe = &sdrain.cqe, },
5319 .opcode = IB_WR_RDMA_WRITE,
5320 },
5321 };
5322 int ret;
5323 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5324 struct mlx5_core_dev *mdev = dev->mdev;
5325
5326 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5327 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5328 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5329 return;
5330 }
5331
5332 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5333 init_completion(&sdrain.done);
5334
029e88fd 5335 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr);
d0e84c0a
YH		 5336 if (ret) {
5337 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5338 return;
5339 }
5340
5341 handle_drain_completion(cq, &sdrain, dev);
5342}
5343
5344void mlx5_ib_drain_rq(struct ib_qp *qp)
5345{
5346 struct ib_cq *cq = qp->recv_cq;
5347 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5348 struct mlx5_ib_drain_cqe rdrain;
d34ac5cd
BVA		 5349 struct ib_recv_wr rwr = {};
5350 const struct ib_recv_wr *bad_rwr;
d0e84c0a
YH		 5351 int ret;
5352 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5353 struct mlx5_core_dev *mdev = dev->mdev;
5354
5355 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5356 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5357 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5358 return;
5359 }
5360
5361 rwr.wr_cqe = &rdrain.cqe;
5362 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5363 init_completion(&rdrain.done);
5364
029e88fd 5365 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr);
d0e84c0a
YH		 5366 if (ret) {
5367 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5368 return;
5369 }
5370
5371 handle_drain_completion(cq, &rdrain, dev);
5372}
d14133dd
MZ		 5373
5374/**
5375 * Bind a qp to a counter. If @counter is NULL then bind the qp to
5376 * the default counter
5377 */
5378int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
5379{
10189e8e 5380 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d14133dd
MZ		 5381 struct mlx5_ib_qp *mqp = to_mqp(qp);
5382 int err = 0;
5383
5384 mutex_lock(&mqp->mutex);
5385 if (mqp->state == IB_QPS_RESET) {
5386 qp->counter = counter;
5387 goto out;
5388 }
5389
10189e8e
MZ		 5390 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
5391 err = -EOPNOTSUPP;
5392 goto out;
5393 }
5394
d14133dd
MZ		 5395 if (mqp->state == IB_QPS_RTS) {
5396 err = __mlx5_ib_qp_set_counter(qp, counter);
5397 if (!err)
5398 qp->counter = counter;
5399
5400 goto out;
5401 }
5402
5403 mqp->counter_pending = 1;
5404 qp->counter = counter;
5405
5406out:
5407 mutex_unlock(&mqp->mutex);
5408 return err;
5409}
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