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net/mlx5e: E-switch vport manager is valid for ethernet only
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97 37#include "mlx5_ib.h"
e126ba97
EC		 38
39/* not supported currently */
40static int wq_signature;
41
42enum {
43 MLX5_IB_ACK_REQ_FREQ = 8,
44};
45
46enum {
47 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
48 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49 MLX5_IB_LINK_TYPE_IB = 0,
50 MLX5_IB_LINK_TYPE_ETH = 1
51};
52
53enum {
54 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 59 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 60 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
61 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
62 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
63 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
64 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
65 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
66 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
67 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 68 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 69 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
70 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
71 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
72};
73
f0313965
ES		 74struct mlx5_wqe_eth_pad {
75 u8 rsvd0[16];
76};
e126ba97 77
eb49ab0c
AV		 78enum raw_qp_set_mask_map {
79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 80 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 81};
82
0680efa2
AV		 83struct mlx5_modify_raw_qp_param {
84 u16 operation;
eb49ab0c
AV		 85
86 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 87 u32 rate_limit;
eb49ab0c 88 u8 rq_q_ctr_id;
0680efa2
AV		 89};
90
89ea94a7
MG		 91static void get_cqs(enum ib_qp_type qp_type,
92 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
93 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
94
e126ba97
EC		 95static int is_qp0(enum ib_qp_type qp_type)
96{
97 return qp_type == IB_QPT_SMI;
98}
99
e126ba97
EC		 100static int is_sqp(enum ib_qp_type qp_type)
101{
102 return is_qp0(qp_type) || is_qp1(qp_type);
103}
104
105static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
106{
107 return mlx5_buf_offset(&qp->buf, offset);
108}
109
110static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
111{
112 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
113}
114
115void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
116{
117 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
118}
119
c1395a2a
HE		 120/**
121 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
122 *
123 * @qp: QP to copy from.
124 * @send: copy from the send queue when non-zero, use the receive queue
125 * otherwise.
126 * @wqe_index: index to start copying from. For send work queues, the
127 * wqe_index is in units of MLX5_SEND_WQE_BB.
128 * For receive work queue, it is the number of work queue
129 * element in the queue.
130 * @buffer: destination buffer.
131 * @length: maximum number of bytes to copy.
132 *
133 * Copies at least a single WQE, but may copy more data.
134 *
135 * Return: the number of bytes copied, or an error code.
136 */
137int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 138 void *buffer, u32 length,
139 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 140{
141 struct ib_device *ibdev = qp->ibqp.device;
142 struct mlx5_ib_dev *dev = to_mdev(ibdev);
143 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
144 size_t offset;
145 size_t wq_end;
19098df2 146 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 147 u32 first_copy_length;
148 int wqe_length;
149 int ret;
150
151 if (wq->wqe_cnt == 0) {
152 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
153 qp->ibqp.qp_type);
154 return -EINVAL;
155 }
156
157 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
158 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
159
160 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
161 return -EINVAL;
162
163 if (offset > umem->length ||
164 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
165 return -EINVAL;
166
167 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
168 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
169 if (ret)
170 return ret;
171
172 if (send) {
173 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
174 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
175
176 wqe_length = ds * MLX5_WQE_DS_UNITS;
177 } else {
178 wqe_length = 1 << wq->wqe_shift;
179 }
180
181 if (wqe_length <= first_copy_length)
182 return first_copy_length;
183
184 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
185 wqe_length - first_copy_length);
186 if (ret)
187 return ret;
188
189 return wqe_length;
190}
191
e126ba97
EC		 192static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
193{
194 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
195 struct ib_event event;
196
19098df2 197 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
198 /* This event is only valid for trans_qps */
199 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
200 }
e126ba97
EC		 201
202 if (ibqp->event_handler) {
203 event.device = ibqp->device;
204 event.element.qp = ibqp;
205 switch (type) {
206 case MLX5_EVENT_TYPE_PATH_MIG:
207 event.event = IB_EVENT_PATH_MIG;
208 break;
209 case MLX5_EVENT_TYPE_COMM_EST:
210 event.event = IB_EVENT_COMM_EST;
211 break;
212 case MLX5_EVENT_TYPE_SQ_DRAINED:
213 event.event = IB_EVENT_SQ_DRAINED;
214 break;
215 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
216 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
217 break;
218 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
219 event.event = IB_EVENT_QP_FATAL;
220 break;
221 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
222 event.event = IB_EVENT_PATH_MIG_ERR;
223 break;
224 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
225 event.event = IB_EVENT_QP_REQ_ERR;
226 break;
227 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
228 event.event = IB_EVENT_QP_ACCESS_ERR;
229 break;
230 default:
231 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
232 return;
233 }
234
235 ibqp->event_handler(&event, ibqp->qp_context);
236 }
237}
238
239static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
240 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
241{
242 int wqe_size;
243 int wq_size;
244
245 /* Sanity check RQ size before proceeding */
938fe83c 246 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 247 return -EINVAL;
248
249 if (!has_rq) {
250 qp->rq.max_gs = 0;
251 qp->rq.wqe_cnt = 0;
252 qp->rq.wqe_shift = 0;
0540d814
NO		 253 cap->max_recv_wr = 0;
254 cap->max_recv_sge = 0;
e126ba97
EC		 255 } else {
256 if (ucmd) {
257 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
258 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
259 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
260 qp->rq.max_post = qp->rq.wqe_cnt;
261 } else {
262 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
263 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
264 wqe_size = roundup_pow_of_two(wqe_size);
265 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
266 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
267 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 268 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 269 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
270 wqe_size,
938fe83c
SM		 271 MLX5_CAP_GEN(dev->mdev,
272 max_wqe_sz_rq));
e126ba97
EC		 273 return -EINVAL;
274 }
275 qp->rq.wqe_shift = ilog2(wqe_size);
276 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
277 qp->rq.max_post = qp->rq.wqe_cnt;
278 }
279 }
280
281 return 0;
282}
283
f0313965 284static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 285{
618af384 286 int size = 0;
e126ba97 287
f0313965 288 switch (attr->qp_type) {
e126ba97 289 case IB_QPT_XRC_INI:
b125a54b 290 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 291 /* fall through */
292 case IB_QPT_RC:
293 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 294 max(sizeof(struct mlx5_wqe_atomic_seg) +
295 sizeof(struct mlx5_wqe_raddr_seg),
296 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
297 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 298 break;
299
b125a54b
EC		 300 case IB_QPT_XRC_TGT:
301 return 0;
302
e126ba97 303 case IB_QPT_UC:
b125a54b 304 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 305 max(sizeof(struct mlx5_wqe_raddr_seg),
306 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
307 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 308 break;
309
310 case IB_QPT_UD:
f0313965
ES		 311 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
312 size += sizeof(struct mlx5_wqe_eth_pad) +
313 sizeof(struct mlx5_wqe_eth_seg);
314 /* fall through */
e126ba97 315 case IB_QPT_SMI:
d16e91da 316 case MLX5_IB_QPT_HW_GSI:
b125a54b 317 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 318 sizeof(struct mlx5_wqe_datagram_seg);
319 break;
320
321 case MLX5_IB_QPT_REG_UMR:
b125a54b 322 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 323 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
324 sizeof(struct mlx5_mkey_seg);
325 break;
326
327 default:
328 return -EINVAL;
329 }
330
331 return size;
332}
333
334static int calc_send_wqe(struct ib_qp_init_attr *attr)
335{
336 int inl_size = 0;
337 int size;
338
f0313965 339 size = sq_overhead(attr);
e126ba97
EC		 340 if (size < 0)
341 return size;
342
343 if (attr->cap.max_inline_data) {
344 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
345 attr->cap.max_inline_data;
346 }
347
348 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 349 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
350 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
351 return MLX5_SIG_WQE_SIZE;
352 else
353 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 354}
355
288c01b7
EC		 356static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357{
358 int max_sge;
359
360 if (attr->qp_type == IB_QPT_RC)
361 max_sge = (min_t(int, wqe_size, 512) -
362 sizeof(struct mlx5_wqe_ctrl_seg) -
363 sizeof(struct mlx5_wqe_raddr_seg)) /
364 sizeof(struct mlx5_wqe_data_seg);
365 else if (attr->qp_type == IB_QPT_XRC_INI)
366 max_sge = (min_t(int, wqe_size, 512) -
367 sizeof(struct mlx5_wqe_ctrl_seg) -
368 sizeof(struct mlx5_wqe_xrc_seg) -
369 sizeof(struct mlx5_wqe_raddr_seg)) /
370 sizeof(struct mlx5_wqe_data_seg);
371 else
372 max_sge = (wqe_size - sq_overhead(attr)) /
373 sizeof(struct mlx5_wqe_data_seg);
374
375 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
376 sizeof(struct mlx5_wqe_data_seg));
377}
378
e126ba97
EC		 379static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
380 struct mlx5_ib_qp *qp)
381{
382 int wqe_size;
383 int wq_size;
384
385 if (!attr->cap.max_send_wr)
386 return 0;
387
388 wqe_size = calc_send_wqe(attr);
389 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
390 if (wqe_size < 0)
391 return wqe_size;
392
938fe83c 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 394 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 395 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 396 return -EINVAL;
397 }
398
f0313965
ES		 399 qp->max_inline_data = wqe_size - sq_overhead(attr) -
400 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 401 attr->cap.max_inline_data = qp->max_inline_data;
402
e1e66cc2
SG		 403 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
404 qp->signature_en = true;
405
e126ba97
EC		 406 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
407 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 408 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 409 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
410 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 411 qp->sq.wqe_cnt,
412 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 413 return -ENOMEM;
414 }
e126ba97 415 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 416 qp->sq.max_gs = get_send_sge(attr, wqe_size);
417 if (qp->sq.max_gs < attr->cap.max_send_sge)
418 return -ENOMEM;
419
420 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 421 qp->sq.max_post = wq_size / wqe_size;
422 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 423
424 return wq_size;
425}
426
427static int set_user_buf_size(struct mlx5_ib_dev *dev,
428 struct mlx5_ib_qp *qp,
19098df2 429 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 430 struct mlx5_ib_qp_base *base,
431 struct ib_qp_init_attr *attr)
e126ba97
EC		 432{
433 int desc_sz = 1 << qp->sq.wqe_shift;
434
938fe83c 435 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 436 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 437 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 438 return -EINVAL;
439 }
440
441 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
442 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
443 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
444 return -EINVAL;
445 }
446
447 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
448
938fe83c 449 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 450 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 451 qp->sq.wqe_cnt,
452 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 453 return -EINVAL;
454 }
455
0fb2ed66 456 if (attr->qp_type == IB_QPT_RAW_PACKET) {
457 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
458 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
459 } else {
460 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
461 (qp->sq.wqe_cnt << 6);
462 }
e126ba97
EC		 463
464 return 0;
465}
466
467static int qp_has_rq(struct ib_qp_init_attr *attr)
468{
469 if (attr->qp_type == IB_QPT_XRC_INI ||
470 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
471 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
472 !attr->cap.max_recv_wr)
473 return 0;
474
475 return 1;
476}
477
2f5ff264 478static int first_med_bfreg(void)
c1be5232
EC		 479{
480 return 1;
481}
482
0b80c14f
EC		 483enum {
484 /* this is the first blue flame register in the array of bfregs assigned
485 * to a processes. Since we do not use it for blue flame but rather
486 * regular 64 bit doorbells, we do not need a lock for maintaiing
487 * "odd/even" order
488 */
489 NUM_NON_BLUE_FLAME_BFREGS = 1,
490};
491
b037c29a
EC		 492static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
493{
494 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
495}
496
497static int num_med_bfreg(struct mlx5_ib_dev *dev,
498 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 499{
500 int n;
501
b037c29a
EC		 502 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
503 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 504
505 return n >= 0 ? n : 0;
506}
507
b037c29a
EC		 508static int first_hi_bfreg(struct mlx5_ib_dev *dev,
509 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 510{
511 int med;
c1be5232 512
b037c29a
EC		 513 med = num_med_bfreg(dev, bfregi);
514 return ++med;
c1be5232
EC		 515}
516
b037c29a
EC		 517static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
518 struct mlx5_bfreg_info *bfregi)
e126ba97 519{
e126ba97
EC		 520 int i;
521
b037c29a
EC		 522 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
523 if (!bfregi->count[i]) {
2f5ff264 524 bfregi->count[i]++;
e126ba97
EC		 525 return i;
526 }
527 }
528
529 return -ENOMEM;
530}
531
b037c29a
EC		 532static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
533 struct mlx5_bfreg_info *bfregi)
e126ba97 534{
2f5ff264 535 int minidx = first_med_bfreg();
e126ba97
EC		 536 int i;
537
b037c29a 538 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 539 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 540 minidx = i;
0b80c14f
EC		 541 if (!bfregi->count[minidx])
542 break;
e126ba97
EC		 543 }
544
2f5ff264 545 bfregi->count[minidx]++;
e126ba97
EC		 546 return minidx;
547}
548
b037c29a
EC		 549static int alloc_bfreg(struct mlx5_ib_dev *dev,
550 struct mlx5_bfreg_info *bfregi,
2f5ff264 551 enum mlx5_ib_latency_class lat)
e126ba97 552{
2f5ff264 553 int bfregn = -EINVAL;
e126ba97 554
2f5ff264 555 mutex_lock(&bfregi->lock);
e126ba97
EC		 556 switch (lat) {
557 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 558 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 559 bfregn = 0;
560 bfregi->count[bfregn]++;
e126ba97
EC		 561 break;
562
563 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 564 if (bfregi->ver < 2)
565 bfregn = -ENOMEM;
78c0f98c 566 else
b037c29a 567 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 568 break;
569
570 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 571 if (bfregi->ver < 2)
572 bfregn = -ENOMEM;
78c0f98c 573 else
b037c29a 574 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 575 break;
576 }
2f5ff264 577 mutex_unlock(&bfregi->lock);
e126ba97 578
2f5ff264 579 return bfregn;
e126ba97
EC		 580}
581
b037c29a 582static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 583{
2f5ff264 584 mutex_lock(&bfregi->lock);
b037c29a 585 bfregi->count[bfregn]--;
2f5ff264 586 mutex_unlock(&bfregi->lock);
e126ba97
EC		 587}
588
589static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
590{
591 switch (state) {
592 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
593 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
594 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
595 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
596 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
597 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
598 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
599 default: return -1;
600 }
601}
602
603static int to_mlx5_st(enum ib_qp_type type)
604{
605 switch (type) {
606 case IB_QPT_RC: return MLX5_QP_ST_RC;
607 case IB_QPT_UC: return MLX5_QP_ST_UC;
608 case IB_QPT_UD: return MLX5_QP_ST_UD;
609 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
610 case IB_QPT_XRC_INI:
611 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
612 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 613 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 614 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 615 case IB_QPT_RAW_PACKET:
0fb2ed66 616 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 617 case IB_QPT_MAX:
618 default: return -EINVAL;
619 }
620}
621
89ea94a7
MG		 622static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
623 struct mlx5_ib_cq *recv_cq);
624static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626
b037c29a
EC		 627static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
628 struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 629{
b037c29a
EC		 630 int bfregs_per_sys_page;
631 int index_of_sys_page;
632 int offset;
633
634 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
635 MLX5_NON_FP_BFREGS_PER_UAR;
636 index_of_sys_page = bfregn / bfregs_per_sys_page;
637
638 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
639
640 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 641}
642
19098df2 643static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
644 struct ib_pd *pd,
645 unsigned long addr, size_t size,
646 struct ib_umem **umem,
647 int *npages, int *page_shift, int *ncont,
648 u32 *offset)
649{
650 int err;
651
652 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
653 if (IS_ERR(*umem)) {
654 mlx5_ib_dbg(dev, "umem_get failed\n");
655 return PTR_ERR(*umem);
656 }
657
762f899a 658 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 659
660 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
661 if (err) {
662 mlx5_ib_warn(dev, "bad offset\n");
663 goto err_umem;
664 }
665
666 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
667 addr, size, *npages, *page_shift, *ncont, *offset);
668
669 return 0;
670
671err_umem:
672 ib_umem_release(*umem);
673 *umem = NULL;
674
675 return err;
676}
677
79b20a6c
YH		 678static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
679{
680 struct mlx5_ib_ucontext *context;
681
682 context = to_mucontext(pd->uobject->context);
683 mlx5_ib_db_unmap_user(context, &rwq->db);
684 if (rwq->umem)
685 ib_umem_release(rwq->umem);
686}
687
688static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
689 struct mlx5_ib_rwq *rwq,
690 struct mlx5_ib_create_wq *ucmd)
691{
692 struct mlx5_ib_ucontext *context;
693 int page_shift = 0;
694 int npages;
695 u32 offset = 0;
696 int ncont = 0;
697 int err;
698
699 if (!ucmd->buf_addr)
700 return -EINVAL;
701
702 context = to_mucontext(pd->uobject->context);
703 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
704 rwq->buf_size, 0, 0);
705 if (IS_ERR(rwq->umem)) {
706 mlx5_ib_dbg(dev, "umem_get failed\n");
707 err = PTR_ERR(rwq->umem);
708 return err;
709 }
710
762f899a 711 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 712 &ncont, NULL);
713 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
714 &rwq->rq_page_offset);
715 if (err) {
716 mlx5_ib_warn(dev, "bad offset\n");
717 goto err_umem;
718 }
719
720 rwq->rq_num_pas = ncont;
721 rwq->page_shift = page_shift;
722 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
723 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
724
725 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
726 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
727 npages, page_shift, ncont, offset);
728
729 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
730 if (err) {
731 mlx5_ib_dbg(dev, "map failed\n");
732 goto err_umem;
733 }
734
735 rwq->create_type = MLX5_WQ_USER;
736 return 0;
737
738err_umem:
739 ib_umem_release(rwq->umem);
740 return err;
741}
742
b037c29a
EC		 743static int adjust_bfregn(struct mlx5_ib_dev *dev,
744 struct mlx5_bfreg_info *bfregi, int bfregn)
745{
746 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
747 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
748}
749
e126ba97
EC		 750static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
751 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 752 struct ib_qp_init_attr *attr,
09a7d9ec 753 u32 **in,
19098df2 754 struct mlx5_ib_create_qp_resp *resp, int *inlen,
755 struct mlx5_ib_qp_base *base)
e126ba97
EC		 756{
757 struct mlx5_ib_ucontext *context;
758 struct mlx5_ib_create_qp ucmd;
19098df2 759 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 760 int page_shift = 0;
e126ba97
EC		 761 int uar_index;
762 int npages;
9e9c47d0 763 u32 offset = 0;
2f5ff264 764 int bfregn;
9e9c47d0 765 int ncont = 0;
09a7d9ec
SM		 766 __be64 *pas;
767 void *qpc;
e126ba97
EC		 768 int err;
769
770 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
771 if (err) {
772 mlx5_ib_dbg(dev, "copy failed\n");
773 return err;
774 }
775
776 context = to_mucontext(pd->uobject->context);
777 /*
778 * TBD: should come from the verbs when we have the API
779 */
051f2630
LR		 780 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
781 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 782 bfregn = MLX5_CROSS_CHANNEL_BFREG;
051f2630 783 else {
b037c29a 784 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 785 if (bfregn < 0) {
786 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 787 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 788 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 789 if (bfregn < 0) {
790 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 791 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 792 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 793 if (bfregn < 0) {
794 mlx5_ib_warn(dev, "bfreg allocation failed\n");
795 return bfregn;
051f2630 796 }
c1be5232 797 }
e126ba97
EC		 798 }
799 }
800
b037c29a 801 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
2f5ff264 802 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
e126ba97 803
48fea837
HE		 804 qp->rq.offset = 0;
805 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
806 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
807
0fb2ed66 808 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 809 if (err)
2f5ff264 810 goto err_bfreg;
e126ba97 811
19098df2 812 if (ucmd.buf_addr && ubuffer->buf_size) {
813 ubuffer->buf_addr = ucmd.buf_addr;
814 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
815 ubuffer->buf_size,
816 &ubuffer->umem, &npages, &page_shift,
817 &ncont, &offset);
818 if (err)
2f5ff264 819 goto err_bfreg;
9e9c47d0 820 } else {
19098df2 821 ubuffer->umem = NULL;
e126ba97 822 }
e126ba97 823
09a7d9ec
SM		 824 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
825 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
e126ba97
EC		 826 *in = mlx5_vzalloc(*inlen);
827 if (!*in) {
828 err = -ENOMEM;
829 goto err_umem;
830 }
09a7d9ec
SM		 831
832 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 833 if (ubuffer->umem)
09a7d9ec
SM		 834 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
835
836 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
837
838 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
839 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 840
09a7d9ec 841 MLX5_SET(qpc, qpc, uar_page, uar_index);
b037c29a 842 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
2f5ff264 843 qp->bfregn = bfregn;
e126ba97
EC		 844
845 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
846 if (err) {
847 mlx5_ib_dbg(dev, "map failed\n");
848 goto err_free;
849 }
850
851 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
852 if (err) {
853 mlx5_ib_dbg(dev, "copy failed\n");
854 goto err_unmap;
855 }
856 qp->create_type = MLX5_QP_USER;
857
858 return 0;
859
860err_unmap:
861 mlx5_ib_db_unmap_user(context, &qp->db);
862
863err_free:
479163f4 864 kvfree(*in);
e126ba97
EC		 865
866err_umem:
19098df2 867 if (ubuffer->umem)
868 ib_umem_release(ubuffer->umem);
e126ba97 869
2f5ff264 870err_bfreg:
b037c29a 871 free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 872 return err;
873}
874
b037c29a
EC		 875static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
876 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 877{
878 struct mlx5_ib_ucontext *context;
879
880 context = to_mucontext(pd->uobject->context);
881 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 882 if (base->ubuffer.umem)
883 ib_umem_release(base->ubuffer.umem);
b037c29a 884 free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 885}
886
887static int create_kernel_qp(struct mlx5_ib_dev *dev,
888 struct ib_qp_init_attr *init_attr,
889 struct mlx5_ib_qp *qp,
09a7d9ec 890 u32 **in, int *inlen,
19098df2 891 struct mlx5_ib_qp_base *base)
e126ba97 892{
e126ba97 893 int uar_index;
09a7d9ec 894 void *qpc;
e126ba97
EC		 895 int err;
896
f0313965
ES		 897 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
898 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 899 IB_QP_CREATE_IPOIB_UD_LSO |
900 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 901 return -EINVAL;
e126ba97
EC		 902
903 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 904 qp->bf.bfreg = &dev->fp_bfreg;
905 else
906 qp->bf.bfreg = &dev->bfreg;
e126ba97 907
d8030b0d
EC		 908 /* We need to divide by two since each register is comprised of
909 * two buffers of identical size, namely odd and even
910 */
911 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 912 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 913
914 err = calc_sq_size(dev, init_attr, qp);
915 if (err < 0) {
916 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 917 return err;
e126ba97
EC		 918 }
919
920 qp->rq.offset = 0;
921 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 922 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 923
19098df2 924 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 925 if (err) {
926 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 927 return err;
e126ba97
EC		 928 }
929
930 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 931 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
932 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
e126ba97
EC		 933 *in = mlx5_vzalloc(*inlen);
934 if (!*in) {
935 err = -ENOMEM;
936 goto err_buf;
937 }
09a7d9ec
SM		 938
939 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
940 MLX5_SET(qpc, qpc, uar_page, uar_index);
941 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
942
e126ba97 943 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 944 MLX5_SET(qpc, qpc, fre, 1);
945 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 946
b11a4f9c 947 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 948 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 949 qp->flags |= MLX5_IB_QP_SQPN_QP1;
950 }
951
09a7d9ec
SM		 952 mlx5_fill_page_array(&qp->buf,
953 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 954
9603b61d 955 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 956 if (err) {
957 mlx5_ib_dbg(dev, "err %d\n", err);
958 goto err_free;
959 }
960
e126ba97
EC		 961 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
962 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
963 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
964 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
965 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
966
967 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
968 !qp->sq.w_list || !qp->sq.wqe_head) {
969 err = -ENOMEM;
970 goto err_wrid;
971 }
972 qp->create_type = MLX5_QP_KERNEL;
973
974 return 0;
975
976err_wrid:
e126ba97
EC		 977 kfree(qp->sq.wqe_head);
978 kfree(qp->sq.w_list);
979 kfree(qp->sq.wrid);
980 kfree(qp->sq.wr_data);
981 kfree(qp->rq.wrid);
f4044dac 982 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 983
984err_free:
479163f4 985 kvfree(*in);
e126ba97
EC		 986
987err_buf:
9603b61d 988 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 989 return err;
990}
991
992static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
993{
e126ba97
EC		 994 kfree(qp->sq.wqe_head);
995 kfree(qp->sq.w_list);
996 kfree(qp->sq.wrid);
997 kfree(qp->sq.wr_data);
998 kfree(qp->rq.wrid);
f4044dac 999 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1000 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1001}
1002
09a7d9ec 1003static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1004{
1005 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1006 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1007 return MLX5_SRQ_RQ;
e126ba97 1008 else if (!qp->has_rq)
09a7d9ec 1009 return MLX5_ZERO_LEN_RQ;
e126ba97 1010 else
09a7d9ec 1011 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1012}
1013
1014static int is_connected(enum ib_qp_type qp_type)
1015{
1016 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1017 return 1;
1018
1019 return 0;
1020}
1021
0fb2ed66 1022static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1023 struct mlx5_ib_sq *sq, u32 tdn)
1024{
c4f287c4 1025 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1026 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1027
0fb2ed66 1028 MLX5_SET(tisc, tisc, transport_domain, tdn);
0fb2ed66 1029 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1030}
1031
1032static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1033 struct mlx5_ib_sq *sq)
1034{
1035 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1036}
1037
1038static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1039 struct mlx5_ib_sq *sq, void *qpin,
1040 struct ib_pd *pd)
1041{
1042 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1043 __be64 *pas;
1044 void *in;
1045 void *sqc;
1046 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1047 void *wq;
1048 int inlen;
1049 int err;
1050 int page_shift = 0;
1051 int npages;
1052 int ncont = 0;
1053 u32 offset = 0;
1054
1055 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1056 &sq->ubuffer.umem, &npages, &page_shift,
1057 &ncont, &offset);
1058 if (err)
1059 return err;
1060
1061 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1062 in = mlx5_vzalloc(inlen);
1063 if (!in) {
1064 err = -ENOMEM;
1065 goto err_umem;
1066 }
1067
1068 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1069 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1070 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1071 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1072 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1073 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1074 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1075
1076 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1077 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1078 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1079 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1080 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1081 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1082 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1083 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1084 MLX5_SET(wq, wq, page_offset, offset);
1085
1086 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1087 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1088
1089 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1090
1091 kvfree(in);
1092
1093 if (err)
1094 goto err_umem;
1095
1096 return 0;
1097
1098err_umem:
1099 ib_umem_release(sq->ubuffer.umem);
1100 sq->ubuffer.umem = NULL;
1101
1102 return err;
1103}
1104
1105static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1106 struct mlx5_ib_sq *sq)
1107{
1108 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1109 ib_umem_release(sq->ubuffer.umem);
1110}
1111
1112static int get_rq_pas_size(void *qpc)
1113{
1114 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1115 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1116 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1117 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1118 u32 po_quanta = 1 << (log_page_size - 6);
1119 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1120 u32 page_size = 1 << log_page_size;
1121 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1122 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1123
1124 return rq_num_pas * sizeof(u64);
1125}
1126
1127static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1128 struct mlx5_ib_rq *rq, void *qpin)
1129{
358e42ea 1130 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1131 __be64 *pas;
1132 __be64 *qp_pas;
1133 void *in;
1134 void *rqc;
1135 void *wq;
1136 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1137 int inlen;
1138 int err;
1139 u32 rq_pas_size = get_rq_pas_size(qpc);
1140
1141 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1142 in = mlx5_vzalloc(inlen);
1143 if (!in)
1144 return -ENOMEM;
1145
1146 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1147 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1148 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1149 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1150 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1151 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1152 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1153 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1154
358e42ea
MD		 1155 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1156 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1157
0fb2ed66 1158 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1159 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1160 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1161 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1162 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1163 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1164 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1165 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1166 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1167 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1168
1169 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1170 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1171 memcpy(pas, qp_pas, rq_pas_size);
1172
1173 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1174
1175 kvfree(in);
1176
1177 return err;
1178}
1179
1180static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1181 struct mlx5_ib_rq *rq)
1182{
1183 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1184}
1185
1186static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1187 struct mlx5_ib_rq *rq, u32 tdn)
1188{
1189 u32 *in;
1190 void *tirc;
1191 int inlen;
1192 int err;
1193
1194 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1195 in = mlx5_vzalloc(inlen);
1196 if (!in)
1197 return -ENOMEM;
1198
1199 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1200 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1201 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1202 MLX5_SET(tirc, tirc, transport_domain, tdn);
1203
1204 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1205
1206 kvfree(in);
1207
1208 return err;
1209}
1210
1211static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1212 struct mlx5_ib_rq *rq)
1213{
1214 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1215}
1216
1217static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1218 u32 *in,
0fb2ed66 1219 struct ib_pd *pd)
1220{
1221 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1222 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1223 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1224 struct ib_uobject *uobj = pd->uobject;
1225 struct ib_ucontext *ucontext = uobj->context;
1226 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1227 int err;
1228 u32 tdn = mucontext->tdn;
1229
1230 if (qp->sq.wqe_cnt) {
1231 err = create_raw_packet_qp_tis(dev, sq, tdn);
1232 if (err)
1233 return err;
1234
1235 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1236 if (err)
1237 goto err_destroy_tis;
1238
1239 sq->base.container_mibqp = qp;
1240 }
1241
1242 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1243 rq->base.container_mibqp = qp;
1244
e4cc4fa7
NO		 1245 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1246 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
0fb2ed66 1247 err = create_raw_packet_qp_rq(dev, rq, in);
1248 if (err)
1249 goto err_destroy_sq;
1250
0fb2ed66 1251
1252 err = create_raw_packet_qp_tir(dev, rq, tdn);
1253 if (err)
1254 goto err_destroy_rq;
1255 }
1256
1257 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1258 rq->base.mqp.qpn;
1259
1260 return 0;
1261
1262err_destroy_rq:
1263 destroy_raw_packet_qp_rq(dev, rq);
1264err_destroy_sq:
1265 if (!qp->sq.wqe_cnt)
1266 return err;
1267 destroy_raw_packet_qp_sq(dev, sq);
1268err_destroy_tis:
1269 destroy_raw_packet_qp_tis(dev, sq);
1270
1271 return err;
1272}
1273
1274static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1275 struct mlx5_ib_qp *qp)
1276{
1277 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1278 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1279 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1280
1281 if (qp->rq.wqe_cnt) {
1282 destroy_raw_packet_qp_tir(dev, rq);
1283 destroy_raw_packet_qp_rq(dev, rq);
1284 }
1285
1286 if (qp->sq.wqe_cnt) {
1287 destroy_raw_packet_qp_sq(dev, sq);
1288 destroy_raw_packet_qp_tis(dev, sq);
1289 }
1290}
1291
1292static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1293 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1294{
1295 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1296 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1297
1298 sq->sq = &qp->sq;
1299 rq->rq = &qp->rq;
1300 sq->doorbell = &qp->db;
1301 rq->doorbell = &qp->db;
1302}
1303
28d61370
YH		 1304static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1305{
1306 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1307}
1308
1309static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1310 struct ib_pd *pd,
1311 struct ib_qp_init_attr *init_attr,
1312 struct ib_udata *udata)
1313{
1314 struct ib_uobject *uobj = pd->uobject;
1315 struct ib_ucontext *ucontext = uobj->context;
1316 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1317 struct mlx5_ib_create_qp_resp resp = {};
1318 int inlen;
1319 int err;
1320 u32 *in;
1321 void *tirc;
1322 void *hfso;
1323 u32 selected_fields = 0;
1324 size_t min_resp_len;
1325 u32 tdn = mucontext->tdn;
1326 struct mlx5_ib_create_qp_rss ucmd = {};
1327 size_t required_cmd_sz;
1328
1329 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1330 return -EOPNOTSUPP;
1331
1332 if (init_attr->create_flags || init_attr->send_cq)
1333 return -EINVAL;
1334
2f5ff264 1335 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1336 if (udata->outlen < min_resp_len)
1337 return -EINVAL;
1338
1339 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1340 if (udata->inlen < required_cmd_sz) {
1341 mlx5_ib_dbg(dev, "invalid inlen\n");
1342 return -EINVAL;
1343 }
1344
1345 if (udata->inlen > sizeof(ucmd) &&
1346 !ib_is_udata_cleared(udata, sizeof(ucmd),
1347 udata->inlen - sizeof(ucmd))) {
1348 mlx5_ib_dbg(dev, "inlen is not supported\n");
1349 return -EOPNOTSUPP;
1350 }
1351
1352 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1353 mlx5_ib_dbg(dev, "copy failed\n");
1354 return -EFAULT;
1355 }
1356
1357 if (ucmd.comp_mask) {
1358 mlx5_ib_dbg(dev, "invalid comp mask\n");
1359 return -EOPNOTSUPP;
1360 }
1361
1362 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1363 mlx5_ib_dbg(dev, "invalid reserved\n");
1364 return -EOPNOTSUPP;
1365 }
1366
1367 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1368 if (err) {
1369 mlx5_ib_dbg(dev, "copy failed\n");
1370 return -EINVAL;
1371 }
1372
1373 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1374 in = mlx5_vzalloc(inlen);
1375 if (!in)
1376 return -ENOMEM;
1377
1378 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1379 MLX5_SET(tirc, tirc, disp_type,
1380 MLX5_TIRC_DISP_TYPE_INDIRECT);
1381 MLX5_SET(tirc, tirc, indirect_table,
1382 init_attr->rwq_ind_tbl->ind_tbl_num);
1383 MLX5_SET(tirc, tirc, transport_domain, tdn);
1384
1385 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1386 switch (ucmd.rx_hash_function) {
1387 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1388 {
1389 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1390 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1391
1392 if (len != ucmd.rx_key_len) {
1393 err = -EINVAL;
1394 goto err;
1395 }
1396
1397 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1398 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1399 memcpy(rss_key, ucmd.rx_hash_key, len);
1400 break;
1401 }
1402 default:
1403 err = -EOPNOTSUPP;
1404 goto err;
1405 }
1406
1407 if (!ucmd.rx_hash_fields_mask) {
1408 /* special case when this TIR serves as steering entry without hashing */
1409 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1410 goto create_tir;
1411 err = -EINVAL;
1412 goto err;
1413 }
1414
1415 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1416 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1417 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1418 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1419 err = -EINVAL;
1420 goto err;
1421 }
1422
1423 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1424 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1425 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1426 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1427 MLX5_L3_PROT_TYPE_IPV4);
1428 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1429 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1430 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1431 MLX5_L3_PROT_TYPE_IPV6);
1432
1433 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1434 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1435 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1436 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1437 err = -EINVAL;
1438 goto err;
1439 }
1440
1441 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1442 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1443 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1444 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1445 MLX5_L4_PROT_TYPE_TCP);
1446 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1447 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1448 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1449 MLX5_L4_PROT_TYPE_UDP);
1450
1451 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1452 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1453 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1454
1455 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1456 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1457 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1458
1459 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1460 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1461 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1462
1463 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1464 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1465 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1466
1467 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1468
1469create_tir:
1470 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1471
1472 if (err)
1473 goto err;
1474
1475 kvfree(in);
1476 /* qpn is reserved for that QP */
1477 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1478 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1479 return 0;
1480
1481err:
1482 kvfree(in);
1483 return err;
1484}
1485
e126ba97
EC		 1486static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1487 struct ib_qp_init_attr *init_attr,
1488 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1489{
1490 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1491 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1492 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1493 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1494 struct mlx5_ib_cq *send_cq;
1495 struct mlx5_ib_cq *recv_cq;
1496 unsigned long flags;
cfb5e088 1497 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1498 struct mlx5_ib_create_qp ucmd;
1499 struct mlx5_ib_qp_base *base;
cfb5e088 1500 void *qpc;
09a7d9ec
SM		 1501 u32 *in;
1502 int err;
e126ba97 1503
0fb2ed66 1504 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1505 &qp->raw_packet_qp.rq.base :
1506 &qp->trans_qp.base;
1507
e126ba97
EC		 1508 mutex_init(&qp->mutex);
1509 spin_lock_init(&qp->sq.lock);
1510 spin_lock_init(&qp->rq.lock);
1511
28d61370
YH		 1512 if (init_attr->rwq_ind_tbl) {
1513 if (!udata)
1514 return -ENOSYS;
1515
1516 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1517 return err;
1518 }
1519
f360d88a 1520 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1521 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1522 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1523 return -EINVAL;
1524 } else {
1525 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1526 }
1527 }
1528
051f2630
LR		 1529 if (init_attr->create_flags &
1530 (IB_QP_CREATE_CROSS_CHANNEL |
1531 IB_QP_CREATE_MANAGED_SEND |
1532 IB_QP_CREATE_MANAGED_RECV)) {
1533 if (!MLX5_CAP_GEN(mdev, cd)) {
1534 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1535 return -EINVAL;
1536 }
1537 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1538 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1539 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1540 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1541 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1542 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1543 }
f0313965
ES		 1544
1545 if (init_attr->qp_type == IB_QPT_UD &&
1546 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1547 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1548 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1549 return -EOPNOTSUPP;
1550 }
1551
358e42ea
MD		 1552 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1553 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1554 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1555 return -EOPNOTSUPP;
1556 }
1557 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1558 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1559 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1560 return -EOPNOTSUPP;
1561 }
1562 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1563 }
1564
e126ba97
EC		 1565 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1566 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1567
e4cc4fa7
NO		 1568 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1569 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1570 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1571 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1572 return -EOPNOTSUPP;
1573 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1574 }
1575
e126ba97
EC		 1576 if (pd && pd->uobject) {
1577 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1578 mlx5_ib_dbg(dev, "copy failed\n");
1579 return -EFAULT;
1580 }
1581
cfb5e088
HA		 1582 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1583 &ucmd, udata->inlen, &uidx);
1584 if (err)
1585 return err;
1586
e126ba97
EC		 1587 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1588 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1589 } else {
1590 qp->wq_sig = !!wq_signature;
1591 }
1592
1593 qp->has_rq = qp_has_rq(init_attr);
1594 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1595 qp, (pd && pd->uobject) ? &ucmd : NULL);
1596 if (err) {
1597 mlx5_ib_dbg(dev, "err %d\n", err);
1598 return err;
1599 }
1600
1601 if (pd) {
1602 if (pd->uobject) {
938fe83c
SM		 1603 __u32 max_wqes =
1604 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1605 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1606 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1607 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1608 mlx5_ib_dbg(dev, "invalid rq params\n");
1609 return -EINVAL;
1610 }
938fe83c 1611 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1612 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1613 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1614 return -EINVAL;
1615 }
b11a4f9c
HE		 1616 if (init_attr->create_flags &
1617 mlx5_ib_create_qp_sqpn_qp1()) {
1618 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1619 return -EINVAL;
1620 }
0fb2ed66 1621 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1622 &resp, &inlen, base);
e126ba97
EC		 1623 if (err)
1624 mlx5_ib_dbg(dev, "err %d\n", err);
1625 } else {
19098df2 1626 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1627 base);
e126ba97
EC		 1628 if (err)
1629 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1630 }
1631
1632 if (err)
1633 return err;
1634 } else {
09a7d9ec 1635 in = mlx5_vzalloc(inlen);
e126ba97
EC		 1636 if (!in)
1637 return -ENOMEM;
1638
1639 qp->create_type = MLX5_QP_EMPTY;
1640 }
1641
1642 if (is_sqp(init_attr->qp_type))
1643 qp->port = init_attr->port_num;
1644
09a7d9ec
SM		 1645 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1646
1647 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1648 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1649
1650 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1651 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1652 else
09a7d9ec
SM		 1653 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1654
e126ba97
EC		 1655
1656 if (qp->wq_sig)
09a7d9ec 1657 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1658
f360d88a 1659 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1660 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1661
051f2630 1662 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1663 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1664 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1665 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1666 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1667 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1668
e126ba97
EC		 1669 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1670 int rcqe_sz;
1671 int scqe_sz;
1672
1673 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1674 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1675
1676 if (rcqe_sz == 128)
09a7d9ec 1677 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1678 else
09a7d9ec 1679 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1680
1681 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1682 if (scqe_sz == 128)
09a7d9ec 1683 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1684 else
09a7d9ec 1685 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1686 }
1687 }
1688
1689 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1690 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1691 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1692 }
1693
09a7d9ec 1694 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97
EC		 1695
1696 if (qp->sq.wqe_cnt)
09a7d9ec 1697 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
e126ba97 1698 else
09a7d9ec 1699 MLX5_SET(qpc, qpc, no_sq, 1);
e126ba97
EC		 1700
1701 /* Set default resources */
1702 switch (init_attr->qp_type) {
1703 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1704 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1705 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1706 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1707 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1708 break;
1709 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1710 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1711 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1712 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1713 break;
1714 default:
1715 if (init_attr->srq) {
09a7d9ec
SM		 1716 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1717 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1718 } else {
09a7d9ec
SM		 1719 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1720 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1721 }
1722 }
1723
1724 if (init_attr->send_cq)
09a7d9ec 1725 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1726
1727 if (init_attr->recv_cq)
09a7d9ec 1728 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1729
09a7d9ec 1730 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1731
09a7d9ec
SM		 1732 /* 0xffffff means we ask to work with cqe version 0 */
1733 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1734 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1735
f0313965
ES		 1736 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1737 if (init_attr->qp_type == IB_QPT_UD &&
1738 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1739 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1740 qp->flags |= MLX5_IB_QP_LSO;
1741 }
cfb5e088 1742
0fb2ed66 1743 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1744 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1745 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1746 err = create_raw_packet_qp(dev, qp, in, pd);
1747 } else {
1748 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1749 }
1750
e126ba97
EC		 1751 if (err) {
1752 mlx5_ib_dbg(dev, "create qp failed\n");
1753 goto err_create;
1754 }
1755
479163f4 1756 kvfree(in);
e126ba97 1757
19098df2 1758 base->container_mibqp = qp;
1759 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1760
89ea94a7
MG		 1761 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1762 &send_cq, &recv_cq);
1763 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1764 mlx5_ib_lock_cqs(send_cq, recv_cq);
1765 /* Maintain device to QPs access, needed for further handling via reset
1766 * flow
1767 */
1768 list_add_tail(&qp->qps_list, &dev->qp_list);
1769 /* Maintain CQ to QPs access, needed for further handling via reset flow
1770 */
1771 if (send_cq)
1772 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1773 if (recv_cq)
1774 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1775 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1776 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1777
e126ba97
EC		 1778 return 0;
1779
1780err_create:
1781 if (qp->create_type == MLX5_QP_USER)
b037c29a 1782 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1783 else if (qp->create_type == MLX5_QP_KERNEL)
1784 destroy_qp_kernel(dev, qp);
1785
479163f4 1786 kvfree(in);
e126ba97
EC		 1787 return err;
1788}
1789
1790static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1791 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1792{
1793 if (send_cq) {
1794 if (recv_cq) {
1795 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1796 spin_lock(&send_cq->lock);
e126ba97
EC		 1797 spin_lock_nested(&recv_cq->lock,
1798 SINGLE_DEPTH_NESTING);
1799 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1800 spin_lock(&send_cq->lock);
e126ba97
EC		 1801 __acquire(&recv_cq->lock);
1802 } else {
89ea94a7 1803 spin_lock(&recv_cq->lock);
e126ba97
EC		 1804 spin_lock_nested(&send_cq->lock,
1805 SINGLE_DEPTH_NESTING);
1806 }
1807 } else {
89ea94a7 1808 spin_lock(&send_cq->lock);
6a4f139a 1809 __acquire(&recv_cq->lock);
e126ba97
EC		 1810 }
1811 } else if (recv_cq) {
89ea94a7 1812 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1813 __acquire(&send_cq->lock);
1814 } else {
1815 __acquire(&send_cq->lock);
1816 __acquire(&recv_cq->lock);
e126ba97
EC		 1817 }
1818}
1819
1820static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1821 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1822{
1823 if (send_cq) {
1824 if (recv_cq) {
1825 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1826 spin_unlock(&recv_cq->lock);
89ea94a7 1827 spin_unlock(&send_cq->lock);
e126ba97
EC		 1828 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1829 __release(&recv_cq->lock);
89ea94a7 1830 spin_unlock(&send_cq->lock);
e126ba97
EC		 1831 } else {
1832 spin_unlock(&send_cq->lock);
89ea94a7 1833 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1834 }
1835 } else {
6a4f139a 1836 __release(&recv_cq->lock);
89ea94a7 1837 spin_unlock(&send_cq->lock);
e126ba97
EC		 1838 }
1839 } else if (recv_cq) {
6a4f139a 1840 __release(&send_cq->lock);
89ea94a7 1841 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1842 } else {
1843 __release(&recv_cq->lock);
1844 __release(&send_cq->lock);
e126ba97
EC		 1845 }
1846}
1847
1848static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1849{
1850 return to_mpd(qp->ibqp.pd);
1851}
1852
89ea94a7
MG		 1853static void get_cqs(enum ib_qp_type qp_type,
1854 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1855 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1856{
89ea94a7 1857 switch (qp_type) {
e126ba97
EC		 1858 case IB_QPT_XRC_TGT:
1859 *send_cq = NULL;
1860 *recv_cq = NULL;
1861 break;
1862 case MLX5_IB_QPT_REG_UMR:
1863 case IB_QPT_XRC_INI:
89ea94a7 1864 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1865 *recv_cq = NULL;
1866 break;
1867
1868 case IB_QPT_SMI:
d16e91da 1869 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1870 case IB_QPT_RC:
1871 case IB_QPT_UC:
1872 case IB_QPT_UD:
1873 case IB_QPT_RAW_IPV6:
1874 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1875 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1876 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1877 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1878 break;
1879
e126ba97
EC		 1880 case IB_QPT_MAX:
1881 default:
1882 *send_cq = NULL;
1883 *recv_cq = NULL;
1884 break;
1885 }
1886}
1887
ad5f8e96 1888static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 1889 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1890 u8 lag_tx_affinity);
ad5f8e96 1891
e126ba97
EC		 1892static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1893{
1894 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1895 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
89ea94a7 1896 unsigned long flags;
e126ba97
EC		 1897 int err;
1898
28d61370
YH		 1899 if (qp->ibqp.rwq_ind_tbl) {
1900 destroy_rss_raw_qp_tir(dev, qp);
1901 return;
1902 }
1903
0fb2ed66 1904 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1905 &qp->raw_packet_qp.rq.base :
1906 &qp->trans_qp.base;
1907
6aec21f6 1908 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1909 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
ad5f8e96 1910 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1911 MLX5_CMD_OP_2RST_QP, 0,
1912 NULL, &base->mqp);
ad5f8e96 1913 } else {
0680efa2
AV		 1914 struct mlx5_modify_raw_qp_param raw_qp_param = {
1915 .operation = MLX5_CMD_OP_2RST_QP
1916 };
1917
13eab21f 1918 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 1919 }
1920 if (err)
427c1e7b 1921 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1922 base->mqp.qpn);
6aec21f6 1923 }
e126ba97 1924
89ea94a7
MG		 1925 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1926 &send_cq, &recv_cq);
1927
1928 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1929 mlx5_ib_lock_cqs(send_cq, recv_cq);
1930 /* del from lists under both locks above to protect reset flow paths */
1931 list_del(&qp->qps_list);
1932 if (send_cq)
1933 list_del(&qp->cq_send_list);
1934
1935 if (recv_cq)
1936 list_del(&qp->cq_recv_list);
e126ba97
EC		 1937
1938 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1939 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1940 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1941 if (send_cq != recv_cq)
19098df2 1942 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1943 NULL);
e126ba97 1944 }
89ea94a7
MG		 1945 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1946 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1947
0fb2ed66 1948 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1949 destroy_raw_packet_qp(dev, qp);
1950 } else {
1951 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1952 if (err)
1953 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1954 base->mqp.qpn);
1955 }
e126ba97 1956
e126ba97
EC		 1957 if (qp->create_type == MLX5_QP_KERNEL)
1958 destroy_qp_kernel(dev, qp);
1959 else if (qp->create_type == MLX5_QP_USER)
b037c29a 1960 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1961}
1962
1963static const char *ib_qp_type_str(enum ib_qp_type type)
1964{
1965 switch (type) {
1966 case IB_QPT_SMI:
1967 return "IB_QPT_SMI";
1968 case IB_QPT_GSI:
1969 return "IB_QPT_GSI";
1970 case IB_QPT_RC:
1971 return "IB_QPT_RC";
1972 case IB_QPT_UC:
1973 return "IB_QPT_UC";
1974 case IB_QPT_UD:
1975 return "IB_QPT_UD";
1976 case IB_QPT_RAW_IPV6:
1977 return "IB_QPT_RAW_IPV6";
1978 case IB_QPT_RAW_ETHERTYPE:
1979 return "IB_QPT_RAW_ETHERTYPE";
1980 case IB_QPT_XRC_INI:
1981 return "IB_QPT_XRC_INI";
1982 case IB_QPT_XRC_TGT:
1983 return "IB_QPT_XRC_TGT";
1984 case IB_QPT_RAW_PACKET:
1985 return "IB_QPT_RAW_PACKET";
1986 case MLX5_IB_QPT_REG_UMR:
1987 return "MLX5_IB_QPT_REG_UMR";
1988 case IB_QPT_MAX:
1989 default:
1990 return "Invalid QP type";
1991 }
1992}
1993
1994struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1995 struct ib_qp_init_attr *init_attr,
1996 struct ib_udata *udata)
1997{
1998 struct mlx5_ib_dev *dev;
1999 struct mlx5_ib_qp *qp;
2000 u16 xrcdn = 0;
2001 int err;
2002
2003 if (pd) {
2004 dev = to_mdev(pd->device);
0fb2ed66 2005
2006 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2007 if (!pd->uobject) {
2008 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2009 return ERR_PTR(-EINVAL);
2010 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2011 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2012 return ERR_PTR(-EINVAL);
2013 }
2014 }
09f16cf5
MD		 2015 } else {
2016 /* being cautious here */
2017 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2018 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2019 pr_warn("%s: no PD for transport %s\n", __func__,
2020 ib_qp_type_str(init_attr->qp_type));
2021 return ERR_PTR(-EINVAL);
2022 }
2023 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2024 }
2025
2026 switch (init_attr->qp_type) {
2027 case IB_QPT_XRC_TGT:
2028 case IB_QPT_XRC_INI:
938fe83c 2029 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2030 mlx5_ib_dbg(dev, "XRC not supported\n");
2031 return ERR_PTR(-ENOSYS);
2032 }
2033 init_attr->recv_cq = NULL;
2034 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2035 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2036 init_attr->send_cq = NULL;
2037 }
2038
2039 /* fall through */
0fb2ed66 2040 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2041 case IB_QPT_RC:
2042 case IB_QPT_UC:
2043 case IB_QPT_UD:
2044 case IB_QPT_SMI:
d16e91da 2045 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2046 case MLX5_IB_QPT_REG_UMR:
2047 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2048 if (!qp)
2049 return ERR_PTR(-ENOMEM);
2050
2051 err = create_qp_common(dev, pd, init_attr, udata, qp);
2052 if (err) {
2053 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2054 kfree(qp);
2055 return ERR_PTR(err);
2056 }
2057
2058 if (is_qp0(init_attr->qp_type))
2059 qp->ibqp.qp_num = 0;
2060 else if (is_qp1(init_attr->qp_type))
2061 qp->ibqp.qp_num = 1;
2062 else
19098df2 2063 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2064
2065 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2066 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2067 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2068 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2069
19098df2 2070 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2071
2072 break;
2073
d16e91da
HE		 2074 case IB_QPT_GSI:
2075 return mlx5_ib_gsi_create_qp(pd, init_attr);
2076
e126ba97
EC		 2077 case IB_QPT_RAW_IPV6:
2078 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2079 case IB_QPT_MAX:
2080 default:
2081 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2082 init_attr->qp_type);
2083 /* Don't support raw QPs */
2084 return ERR_PTR(-EINVAL);
2085 }
2086
2087 return &qp->ibqp;
2088}
2089
2090int mlx5_ib_destroy_qp(struct ib_qp *qp)
2091{
2092 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2093 struct mlx5_ib_qp *mqp = to_mqp(qp);
2094
d16e91da
HE		 2095 if (unlikely(qp->qp_type == IB_QPT_GSI))
2096 return mlx5_ib_gsi_destroy_qp(qp);
2097
e126ba97
EC		 2098 destroy_qp_common(dev, mqp);
2099
2100 kfree(mqp);
2101
2102 return 0;
2103}
2104
2105static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2106 int attr_mask)
2107{
2108 u32 hw_access_flags = 0;
2109 u8 dest_rd_atomic;
2110 u32 access_flags;
2111
2112 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2113 dest_rd_atomic = attr->max_dest_rd_atomic;
2114 else
19098df2 2115 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2116
2117 if (attr_mask & IB_QP_ACCESS_FLAGS)
2118 access_flags = attr->qp_access_flags;
2119 else
19098df2 2120 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2121
2122 if (!dest_rd_atomic)
2123 access_flags &= IB_ACCESS_REMOTE_WRITE;
2124
2125 if (access_flags & IB_ACCESS_REMOTE_READ)
2126 hw_access_flags |= MLX5_QP_BIT_RRE;
2127 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2128 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2129 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2130 hw_access_flags |= MLX5_QP_BIT_RWE;
2131
2132 return cpu_to_be32(hw_access_flags);
2133}
2134
2135enum {
2136 MLX5_PATH_FLAG_FL = 1 << 0,
2137 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2138 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2139};
2140
2141static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2142{
2143 if (rate == IB_RATE_PORT_CURRENT) {
2144 return 0;
2145 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2146 return -EINVAL;
2147 } else {
2148 while (rate != IB_RATE_2_5_GBPS &&
2149 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2150 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2151 --rate;
2152 }
2153
2154 return rate + MLX5_STAT_RATE_OFFSET;
2155}
2156
75850d0b 2157static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2158 struct mlx5_ib_sq *sq, u8 sl)
2159{
2160 void *in;
2161 void *tisc;
2162 int inlen;
2163 int err;
2164
2165 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2166 in = mlx5_vzalloc(inlen);
2167 if (!in)
2168 return -ENOMEM;
2169
2170 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2171
2172 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2173 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2174
2175 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2176
2177 kvfree(in);
2178
2179 return err;
2180}
2181
13eab21f
AH		 2182static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2183 struct mlx5_ib_sq *sq, u8 tx_affinity)
2184{
2185 void *in;
2186 void *tisc;
2187 int inlen;
2188 int err;
2189
2190 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2191 in = mlx5_vzalloc(inlen);
2192 if (!in)
2193 return -ENOMEM;
2194
2195 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2196
2197 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2198 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2199
2200 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2201
2202 kvfree(in);
2203
2204 return err;
2205}
2206
75850d0b 2207static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2208 const struct ib_ah_attr *ah,
e126ba97 2209 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2210 u32 path_flags, const struct ib_qp_attr *attr,
2211 bool alt)
e126ba97 2212{
2811ba51 2213 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97 2214 int err;
ed88451e 2215 enum ib_gid_type gid_type;
e126ba97 2216
e126ba97 2217 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2218 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2219 attr->pkey_index);
e126ba97 2220
e126ba97 2221 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 2222 if (ah->grh.sgid_index >=
2223 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2224 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 2225 ah->grh.sgid_index,
2226 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2227 return -EINVAL;
2228 }
2811ba51
AS		 2229 }
2230
2231 if (ll == IB_LINK_LAYER_ETHERNET) {
2232 if (!(ah->ah_flags & IB_AH_GRH))
2233 return -EINVAL;
ed88451e
MD		 2234 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
2235 &gid_type);
2236 if (err)
2237 return err;
2811ba51
AS		 2238 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2239 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2240 ah->grh.sgid_index);
2241 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
ed88451e
MD		 2242 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2243 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
2811ba51 2244 } else {
d3ae2bde
NO		 2245 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2246 path->fl_free_ar |=
2247 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 2248 path->rlid = cpu_to_be16(ah->dlid);
2249 path->grh_mlid = ah->src_path_bits & 0x7f;
2250 if (ah->ah_flags & IB_AH_GRH)
2251 path->grh_mlid |= 1 << 7;
2252 path->dci_cfi_prio_sl = ah->sl & 0xf;
2253 }
2254
2255 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 2256 path->mgid_index = ah->grh.sgid_index;
2257 path->hop_limit = ah->grh.hop_limit;
2258 path->tclass_flowlabel =
2259 cpu_to_be32((ah->grh.traffic_class << 20) |
2260 (ah->grh.flow_label));
2261 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2262 }
2263
2264 err = ib_rate_to_mlx5(dev, ah->static_rate);
2265 if (err < 0)
2266 return err;
2267 path->static_rate = err;
2268 path->port = port;
2269
e126ba97 2270 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2271 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2272
75850d0b 2273 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2274 return modify_raw_packet_eth_prio(dev->mdev,
2275 &qp->raw_packet_qp.sq,
2276 ah->sl & 0xf);
2277
e126ba97
EC		 2278 return 0;
2279}
2280
2281static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2282 [MLX5_QP_STATE_INIT] = {
2283 [MLX5_QP_STATE_INIT] = {
2284 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2285 MLX5_QP_OPTPAR_RAE |
2286 MLX5_QP_OPTPAR_RWE |
2287 MLX5_QP_OPTPAR_PKEY_INDEX |
2288 MLX5_QP_OPTPAR_PRI_PORT,
2289 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2290 MLX5_QP_OPTPAR_PKEY_INDEX |
2291 MLX5_QP_OPTPAR_PRI_PORT,
2292 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2293 MLX5_QP_OPTPAR_Q_KEY |
2294 MLX5_QP_OPTPAR_PRI_PORT,
2295 },
2296 [MLX5_QP_STATE_RTR] = {
2297 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2298 MLX5_QP_OPTPAR_RRE |
2299 MLX5_QP_OPTPAR_RAE |
2300 MLX5_QP_OPTPAR_RWE |
2301 MLX5_QP_OPTPAR_PKEY_INDEX,
2302 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2303 MLX5_QP_OPTPAR_RWE |
2304 MLX5_QP_OPTPAR_PKEY_INDEX,
2305 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2306 MLX5_QP_OPTPAR_Q_KEY,
2307 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2308 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2309 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2310 MLX5_QP_OPTPAR_RRE |
2311 MLX5_QP_OPTPAR_RAE |
2312 MLX5_QP_OPTPAR_RWE |
2313 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2314 },
2315 },
2316 [MLX5_QP_STATE_RTR] = {
2317 [MLX5_QP_STATE_RTS] = {
2318 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2319 MLX5_QP_OPTPAR_RRE |
2320 MLX5_QP_OPTPAR_RAE |
2321 MLX5_QP_OPTPAR_RWE |
2322 MLX5_QP_OPTPAR_PM_STATE |
2323 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2324 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2325 MLX5_QP_OPTPAR_RWE |
2326 MLX5_QP_OPTPAR_PM_STATE,
2327 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2328 },
2329 },
2330 [MLX5_QP_STATE_RTS] = {
2331 [MLX5_QP_STATE_RTS] = {
2332 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2333 MLX5_QP_OPTPAR_RAE |
2334 MLX5_QP_OPTPAR_RWE |
2335 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2336 MLX5_QP_OPTPAR_PM_STATE |
2337 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2338 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2339 MLX5_QP_OPTPAR_PM_STATE |
2340 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2341 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2342 MLX5_QP_OPTPAR_SRQN |
2343 MLX5_QP_OPTPAR_CQN_RCV,
2344 },
2345 },
2346 [MLX5_QP_STATE_SQER] = {
2347 [MLX5_QP_STATE_RTS] = {
2348 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2349 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2350 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2351 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2352 MLX5_QP_OPTPAR_RWE |
2353 MLX5_QP_OPTPAR_RAE |
2354 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2355 },
2356 },
2357};
2358
2359static int ib_nr_to_mlx5_nr(int ib_mask)
2360{
2361 switch (ib_mask) {
2362 case IB_QP_STATE:
2363 return 0;
2364 case IB_QP_CUR_STATE:
2365 return 0;
2366 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2367 return 0;
2368 case IB_QP_ACCESS_FLAGS:
2369 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2370 MLX5_QP_OPTPAR_RAE;
2371 case IB_QP_PKEY_INDEX:
2372 return MLX5_QP_OPTPAR_PKEY_INDEX;
2373 case IB_QP_PORT:
2374 return MLX5_QP_OPTPAR_PRI_PORT;
2375 case IB_QP_QKEY:
2376 return MLX5_QP_OPTPAR_Q_KEY;
2377 case IB_QP_AV:
2378 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2379 MLX5_QP_OPTPAR_PRI_PORT;
2380 case IB_QP_PATH_MTU:
2381 return 0;
2382 case IB_QP_TIMEOUT:
2383 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2384 case IB_QP_RETRY_CNT:
2385 return MLX5_QP_OPTPAR_RETRY_COUNT;
2386 case IB_QP_RNR_RETRY:
2387 return MLX5_QP_OPTPAR_RNR_RETRY;
2388 case IB_QP_RQ_PSN:
2389 return 0;
2390 case IB_QP_MAX_QP_RD_ATOMIC:
2391 return MLX5_QP_OPTPAR_SRA_MAX;
2392 case IB_QP_ALT_PATH:
2393 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2394 case IB_QP_MIN_RNR_TIMER:
2395 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2396 case IB_QP_SQ_PSN:
2397 return 0;
2398 case IB_QP_MAX_DEST_RD_ATOMIC:
2399 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2400 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2401 case IB_QP_PATH_MIG_STATE:
2402 return MLX5_QP_OPTPAR_PM_STATE;
2403 case IB_QP_CAP:
2404 return 0;
2405 case IB_QP_DEST_QPN:
2406 return 0;
2407 }
2408 return 0;
2409}
2410
2411static int ib_mask_to_mlx5_opt(int ib_mask)
2412{
2413 int result = 0;
2414 int i;
2415
2416 for (i = 0; i < 8 * sizeof(int); i++) {
2417 if ((1 << i) & ib_mask)
2418 result |= ib_nr_to_mlx5_nr(1 << i);
2419 }
2420
2421 return result;
2422}
2423
eb49ab0c
AV		 2424static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2425 struct mlx5_ib_rq *rq, int new_state,
2426 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2427{
2428 void *in;
2429 void *rqc;
2430 int inlen;
2431 int err;
2432
2433 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2434 in = mlx5_vzalloc(inlen);
2435 if (!in)
2436 return -ENOMEM;
2437
2438 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2439
2440 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2441 MLX5_SET(rqc, rqc, state, new_state);
2442
eb49ab0c
AV		 2443 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2444 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2445 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2446 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2447 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2448 } else
2449 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2450 dev->ib_dev.name);
2451 }
2452
2453 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2454 if (err)
2455 goto out;
2456
2457 rq->state = new_state;
2458
2459out:
2460 kvfree(in);
2461 return err;
2462}
2463
2464static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2465 struct mlx5_ib_sq *sq,
2466 int new_state,
2467 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2468{
7d29f349
BW		 2469 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2470 u32 old_rate = ibqp->rate_limit;
2471 u32 new_rate = old_rate;
2472 u16 rl_index = 0;
ad5f8e96 2473 void *in;
2474 void *sqc;
2475 int inlen;
2476 int err;
2477
2478 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2479 in = mlx5_vzalloc(inlen);
2480 if (!in)
2481 return -ENOMEM;
2482
2483 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2484
2485 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2486 MLX5_SET(sqc, sqc, state, new_state);
2487
7d29f349
BW		 2488 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2489 if (new_state != MLX5_SQC_STATE_RDY)
2490 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2491 __func__);
2492 else
2493 new_rate = raw_qp_param->rate_limit;
2494 }
2495
2496 if (old_rate != new_rate) {
2497 if (new_rate) {
2498 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2499 if (err) {
2500 pr_err("Failed configuring rate %u: %d\n",
2501 new_rate, err);
2502 goto out;
2503 }
2504 }
2505
2506 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2507 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2508 }
2509
ad5f8e96 2510 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2511 if (err) {
2512 /* Remove new rate from table if failed */
2513 if (new_rate &&
2514 old_rate != new_rate)
2515 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2516 goto out;
7d29f349
BW		 2517 }
2518
2519 /* Only remove the old rate after new rate was set */
2520 if ((old_rate &&
2521 (old_rate != new_rate)) ||
2522 (new_state != MLX5_SQC_STATE_RDY))
2523 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2524
7d29f349 2525 ibqp->rate_limit = new_rate;
ad5f8e96 2526 sq->state = new_state;
2527
2528out:
2529 kvfree(in);
2530 return err;
2531}
2532
2533static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2534 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2535 u8 tx_affinity)
ad5f8e96 2536{
2537 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2538 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2539 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2540 int modify_rq = !!qp->rq.wqe_cnt;
2541 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2542 int rq_state;
2543 int sq_state;
2544 int err;
2545
0680efa2 2546 switch (raw_qp_param->operation) {
ad5f8e96 2547 case MLX5_CMD_OP_RST2INIT_QP:
2548 rq_state = MLX5_RQC_STATE_RDY;
2549 sq_state = MLX5_SQC_STATE_RDY;
2550 break;
2551 case MLX5_CMD_OP_2ERR_QP:
2552 rq_state = MLX5_RQC_STATE_ERR;
2553 sq_state = MLX5_SQC_STATE_ERR;
2554 break;
2555 case MLX5_CMD_OP_2RST_QP:
2556 rq_state = MLX5_RQC_STATE_RST;
2557 sq_state = MLX5_SQC_STATE_RST;
2558 break;
ad5f8e96 2559 case MLX5_CMD_OP_RTR2RTS_QP:
2560 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2561 if (raw_qp_param->set_mask ==
2562 MLX5_RAW_QP_RATE_LIMIT) {
2563 modify_rq = 0;
2564 sq_state = sq->state;
2565 } else {
2566 return raw_qp_param->set_mask ? -EINVAL : 0;
2567 }
2568 break;
2569 case MLX5_CMD_OP_INIT2INIT_QP:
2570 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2571 if (raw_qp_param->set_mask)
2572 return -EINVAL;
2573 else
2574 return 0;
ad5f8e96 2575 default:
2576 WARN_ON(1);
2577 return -EINVAL;
2578 }
2579
7d29f349
BW		 2580 if (modify_rq) {
2581 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2582 if (err)
2583 return err;
2584 }
2585
7d29f349 2586 if (modify_sq) {
13eab21f
AH		 2587 if (tx_affinity) {
2588 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2589 tx_affinity);
2590 if (err)
2591 return err;
2592 }
2593
7d29f349 2594 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2595 }
ad5f8e96 2596
2597 return 0;
2598}
2599
e126ba97
EC		 2600static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2601 const struct ib_qp_attr *attr, int attr_mask,
2602 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2603{
427c1e7b 2604 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2605 [MLX5_QP_STATE_RST] = {
2606 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2607 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2608 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2609 },
2610 [MLX5_QP_STATE_INIT] = {
2611 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2612 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2613 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2614 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2615 },
2616 [MLX5_QP_STATE_RTR] = {
2617 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2618 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2619 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2620 },
2621 [MLX5_QP_STATE_RTS] = {
2622 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2623 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2624 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2625 },
2626 [MLX5_QP_STATE_SQD] = {
2627 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2628 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2629 },
2630 [MLX5_QP_STATE_SQER] = {
2631 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2632 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2633 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2634 },
2635 [MLX5_QP_STATE_ERR] = {
2636 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2637 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2638 }
2639 };
2640
e126ba97
EC		 2641 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2642 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2643 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2644 struct mlx5_ib_cq *send_cq, *recv_cq;
2645 struct mlx5_qp_context *context;
e126ba97 2646 struct mlx5_ib_pd *pd;
eb49ab0c 2647 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2648 enum mlx5_qp_state mlx5_cur, mlx5_new;
2649 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2650 int mlx5_st;
2651 int err;
427c1e7b 2652 u16 op;
13eab21f 2653 u8 tx_affinity = 0;
e126ba97 2654
1a412fb1
SM		 2655 context = kzalloc(sizeof(*context), GFP_KERNEL);
2656 if (!context)
e126ba97
EC		 2657 return -ENOMEM;
2658
e126ba97 2659 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2660 if (err < 0) {
2661 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2662 goto out;
158abf86 2663 }
e126ba97
EC		 2664
2665 context->flags = cpu_to_be32(err << 16);
2666
2667 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2668 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2669 } else {
2670 switch (attr->path_mig_state) {
2671 case IB_MIG_MIGRATED:
2672 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2673 break;
2674 case IB_MIG_REARM:
2675 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2676 break;
2677 case IB_MIG_ARMED:
2678 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2679 break;
2680 }
2681 }
2682
13eab21f
AH		 2683 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2684 if ((ibqp->qp_type == IB_QPT_RC) ||
2685 (ibqp->qp_type == IB_QPT_UD &&
2686 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2687 (ibqp->qp_type == IB_QPT_UC) ||
2688 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2689 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2690 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2691 if (mlx5_lag_is_active(dev->mdev)) {
2692 tx_affinity = (unsigned int)atomic_add_return(1,
2693 &dev->roce.next_port) %
2694 MLX5_MAX_PORTS + 1;
2695 context->flags |= cpu_to_be32(tx_affinity << 24);
2696 }
2697 }
2698 }
2699
d16e91da 2700 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2701 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2702 } else if (ibqp->qp_type == IB_QPT_UD ||
2703 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2704 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2705 } else if (attr_mask & IB_QP_PATH_MTU) {
2706 if (attr->path_mtu < IB_MTU_256 ||
2707 attr->path_mtu > IB_MTU_4096) {
2708 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2709 err = -EINVAL;
2710 goto out;
2711 }
938fe83c
SM		 2712 context->mtu_msgmax = (attr->path_mtu << 5) |
2713 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2714 }
2715
2716 if (attr_mask & IB_QP_DEST_QPN)
2717 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2718
2719 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2720 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2721
2722 /* todo implement counter_index functionality */
2723
2724 if (is_sqp(ibqp->qp_type))
2725 context->pri_path.port = qp->port;
2726
2727 if (attr_mask & IB_QP_PORT)
2728 context->pri_path.port = attr->port_num;
2729
2730 if (attr_mask & IB_QP_AV) {
75850d0b 2731 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2732 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2733 attr_mask, 0, attr, false);
e126ba97
EC		 2734 if (err)
2735 goto out;
2736 }
2737
2738 if (attr_mask & IB_QP_TIMEOUT)
2739 context->pri_path.ackto_lt |= attr->timeout << 3;
2740
2741 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2742 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2743 &context->alt_path,
f879ee8d
AS		 2744 attr->alt_port_num,
2745 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2746 0, attr, true);
e126ba97
EC		 2747 if (err)
2748 goto out;
2749 }
2750
2751 pd = get_pd(qp);
89ea94a7
MG		 2752 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2753 &send_cq, &recv_cq);
e126ba97
EC		 2754
2755 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2756 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2757 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2758 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2759
2760 if (attr_mask & IB_QP_RNR_RETRY)
2761 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2762
2763 if (attr_mask & IB_QP_RETRY_CNT)
2764 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2765
2766 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2767 if (attr->max_rd_atomic)
2768 context->params1 |=
2769 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2770 }
2771
2772 if (attr_mask & IB_QP_SQ_PSN)
2773 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2774
2775 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2776 if (attr->max_dest_rd_atomic)
2777 context->params2 |=
2778 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2779 }
2780
2781 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2782 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2783
2784 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2785 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2786
2787 if (attr_mask & IB_QP_RQ_PSN)
2788 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2789
2790 if (attr_mask & IB_QP_QKEY)
2791 context->qkey = cpu_to_be32(attr->qkey);
2792
2793 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2794 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2795
0837e86a
MB		 2796 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2797 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2798 qp->port) - 1;
eb49ab0c 2799 mibport = &dev->port[port_num];
0837e86a 2800 context->qp_counter_set_usr_page |=
7c16f477 2801 cpu_to_be32((u32)(mibport->q_cnts.set_id) << 24);
0837e86a
MB		 2802 }
2803
e126ba97
EC		 2804 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2805 context->sq_crq_size |= cpu_to_be16(1 << 4);
2806
b11a4f9c
HE		 2807 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2808 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2809
2810 mlx5_cur = to_mlx5_state(cur_state);
2811 mlx5_new = to_mlx5_state(new_state);
2812 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2813 if (mlx5_st < 0)
e126ba97
EC		 2814 goto out;
2815
427c1e7b 2816 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2817 !optab[mlx5_cur][mlx5_new])
2818 goto out;
2819
2820 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2821 optpar = ib_mask_to_mlx5_opt(attr_mask);
2822 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2823
0680efa2
AV		 2824 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2825 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2826
2827 raw_qp_param.operation = op;
eb49ab0c 2828 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
7c16f477 2829 raw_qp_param.rq_q_ctr_id = mibport->q_cnts.set_id;
eb49ab0c
AV		 2830 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2831 }
7d29f349
BW		 2832
2833 if (attr_mask & IB_QP_RATE_LIMIT) {
2834 raw_qp_param.rate_limit = attr->rate_limit;
2835 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2836 }
2837
13eab21f 2838 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 2839 } else {
1a412fb1 2840 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2841 &base->mqp);
0680efa2
AV		 2842 }
2843
e126ba97
EC		 2844 if (err)
2845 goto out;
2846
2847 qp->state = new_state;
2848
2849 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2850 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2851 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2852 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2853 if (attr_mask & IB_QP_PORT)
2854 qp->port = attr->port_num;
2855 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2856 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2857
2858 /*
2859 * If we moved a kernel QP to RESET, clean up all old CQ
2860 * entries and reinitialize the QP.
2861 */
2862 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2863 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2864 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2865 if (send_cq != recv_cq)
19098df2 2866 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2867
2868 qp->rq.head = 0;
2869 qp->rq.tail = 0;
2870 qp->sq.head = 0;
2871 qp->sq.tail = 0;
2872 qp->sq.cur_post = 0;
2873 qp->sq.last_poll = 0;
2874 qp->db.db[MLX5_RCV_DBR] = 0;
2875 qp->db.db[MLX5_SND_DBR] = 0;
2876 }
2877
2878out:
1a412fb1 2879 kfree(context);
e126ba97
EC		 2880 return err;
2881}
2882
2883int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2884 int attr_mask, struct ib_udata *udata)
2885{
2886 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2887 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2888 enum ib_qp_type qp_type;
e126ba97
EC		 2889 enum ib_qp_state cur_state, new_state;
2890 int err = -EINVAL;
2891 int port;
2811ba51 2892 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2893
28d61370
YH		 2894 if (ibqp->rwq_ind_tbl)
2895 return -ENOSYS;
2896
d16e91da
HE		 2897 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2898 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2899
2900 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2901 IB_QPT_GSI : ibqp->qp_type;
2902
e126ba97
EC		 2903 mutex_lock(&qp->mutex);
2904
2905 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2906 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2907
2811ba51
AS		 2908 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2909 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2910 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2911 }
2912
d16e91da
HE		 2913 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2914 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2915 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2916 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2917 goto out;
158abf86 2918 }
e126ba97
EC		 2919
2920 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2921 (attr->port_num == 0 ||
158abf86
HE		 2922 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2923 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2924 attr->port_num, dev->num_ports);
e126ba97 2925 goto out;
158abf86 2926 }
e126ba97
EC		 2927
2928 if (attr_mask & IB_QP_PKEY_INDEX) {
2929 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2930 if (attr->pkey_index >=
158abf86
HE		 2931 dev->mdev->port_caps[port - 1].pkey_table_len) {
2932 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2933 attr->pkey_index);
e126ba97 2934 goto out;
158abf86 2935 }
e126ba97
EC		 2936 }
2937
2938 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2939 attr->max_rd_atomic >
158abf86
HE		 2940 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2941 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2942 attr->max_rd_atomic);
e126ba97 2943 goto out;
158abf86 2944 }
e126ba97
EC		 2945
2946 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2947 attr->max_dest_rd_atomic >
158abf86
HE		 2948 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2949 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2950 attr->max_dest_rd_atomic);
e126ba97 2951 goto out;
158abf86 2952 }
e126ba97
EC		 2953
2954 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2955 err = 0;
2956 goto out;
2957 }
2958
2959 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2960
2961out:
2962 mutex_unlock(&qp->mutex);
2963 return err;
2964}
2965
2966static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2967{
2968 struct mlx5_ib_cq *cq;
2969 unsigned cur;
2970
2971 cur = wq->head - wq->tail;
2972 if (likely(cur + nreq < wq->max_post))
2973 return 0;
2974
2975 cq = to_mcq(ib_cq);
2976 spin_lock(&cq->lock);
2977 cur = wq->head - wq->tail;
2978 spin_unlock(&cq->lock);
2979
2980 return cur + nreq >= wq->max_post;
2981}
2982
2983static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2984 u64 remote_addr, u32 rkey)
2985{
2986 rseg->raddr = cpu_to_be64(remote_addr);
2987 rseg->rkey = cpu_to_be32(rkey);
2988 rseg->reserved = 0;
2989}
2990
f0313965
ES		 2991static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2992 struct ib_send_wr *wr, void *qend,
2993 struct mlx5_ib_qp *qp, int *size)
2994{
2995 void *seg = eseg;
2996
2997 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2998
2999 if (wr->send_flags & IB_SEND_IP_CSUM)
3000 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3001 MLX5_ETH_WQE_L4_CSUM;
3002
3003 seg += sizeof(struct mlx5_wqe_eth_seg);
3004 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3005
3006 if (wr->opcode == IB_WR_LSO) {
3007 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3008 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3009 u64 left, leftlen, copysz;
3010 void *pdata = ud_wr->header;
3011
3012 left = ud_wr->hlen;
3013 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3014 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3015
3016 /*
3017 * check if there is space till the end of queue, if yes,
3018 * copy all in one shot, otherwise copy till the end of queue,
3019 * rollback and than the copy the left
3020 */
2b31f7ae 3021 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3022 copysz = min_t(u64, leftlen, left);
3023
3024 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3025
3026 if (likely(copysz > size_of_inl_hdr_start)) {
3027 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3028 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3029 }
3030
3031 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3032 seg = mlx5_get_send_wqe(qp, 0);
3033 left -= copysz;
3034 pdata += copysz;
3035 memcpy(seg, pdata, left);
3036 seg += ALIGN(left, 16);
3037 *size += ALIGN(left, 16) / 16;
3038 }
3039 }
3040
3041 return seg;
3042}
3043
e126ba97
EC		 3044static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3045 struct ib_send_wr *wr)
3046{
e622f2f4
CH		 3047 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3048 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3049 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3050}
3051
3052static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3053{
3054 dseg->byte_count = cpu_to_be32(sg->length);
3055 dseg->lkey = cpu_to_be32(sg->lkey);
3056 dseg->addr = cpu_to_be64(sg->addr);
3057}
3058
31616255 3059static u64 get_xlt_octo(u64 bytes)
e126ba97 3060{
31616255
AK		 3061 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3062 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3063}
3064
3065static __be64 frwr_mkey_mask(void)
3066{
3067 u64 result;
3068
3069 result = MLX5_MKEY_MASK_LEN |
3070 MLX5_MKEY_MASK_PAGE_SIZE |
3071 MLX5_MKEY_MASK_START_ADDR |
3072 MLX5_MKEY_MASK_EN_RINVAL |
3073 MLX5_MKEY_MASK_KEY |
3074 MLX5_MKEY_MASK_LR |
3075 MLX5_MKEY_MASK_LW |
3076 MLX5_MKEY_MASK_RR |
3077 MLX5_MKEY_MASK_RW |
3078 MLX5_MKEY_MASK_A |
3079 MLX5_MKEY_MASK_SMALL_FENCE |
3080 MLX5_MKEY_MASK_FREE;
3081
3082 return cpu_to_be64(result);
3083}
3084
e6631814
SG		 3085static __be64 sig_mkey_mask(void)
3086{
3087 u64 result;
3088
3089 result = MLX5_MKEY_MASK_LEN |
3090 MLX5_MKEY_MASK_PAGE_SIZE |
3091 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3092 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3093 MLX5_MKEY_MASK_EN_RINVAL |
3094 MLX5_MKEY_MASK_KEY |
3095 MLX5_MKEY_MASK_LR |
3096 MLX5_MKEY_MASK_LW |
3097 MLX5_MKEY_MASK_RR |
3098 MLX5_MKEY_MASK_RW |
3099 MLX5_MKEY_MASK_SMALL_FENCE |
3100 MLX5_MKEY_MASK_FREE |
3101 MLX5_MKEY_MASK_BSF_EN;
3102
3103 return cpu_to_be64(result);
3104}
3105
8a187ee5 3106static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3107 struct mlx5_ib_mr *mr)
8a187ee5 3108{
31616255 3109 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3110
3111 memset(umr, 0, sizeof(*umr));
b005d316 3112
8a187ee5 3113 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3114 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3115 umr->mkey_mask = frwr_mkey_mask();
3116}
3117
dd01e66a 3118static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3119{
3120 memset(umr, 0, sizeof(*umr));
dd01e66a 3121 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3122 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3123}
3124
31616255 3125static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3126{
3127 u64 result;
3128
31616255 3129 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3130 MLX5_MKEY_MASK_FREE;
3131
968e78dd
HE		 3132 return cpu_to_be64(result);
3133}
3134
31616255 3135static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3136{
3137 u64 result;
3138
3139 result = MLX5_MKEY_MASK_FREE;
3140
3141 return cpu_to_be64(result);
3142}
3143
56e11d62
NO		 3144static __be64 get_umr_update_translation_mask(void)
3145{
3146 u64 result;
3147
3148 result = MLX5_MKEY_MASK_LEN |
3149 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3150 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3151
3152 return cpu_to_be64(result);
3153}
3154
31616255 3155static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3156{
3157 u64 result;
3158
31616255
AK		 3159 result = MLX5_MKEY_MASK_LR |
3160 MLX5_MKEY_MASK_LW |
56e11d62 3161 MLX5_MKEY_MASK_RR |
31616255
AK		 3162 MLX5_MKEY_MASK_RW;
3163
3164 if (atomic)
3165 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3166
3167 return cpu_to_be64(result);
3168}
3169
3170static __be64 get_umr_update_pd_mask(void)
3171{
3172 u64 result;
3173
31616255 3174 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3175
3176 return cpu_to_be64(result);
3177}
3178
e126ba97 3179static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3180 struct ib_send_wr *wr, int atomic)
e126ba97 3181{
e622f2f4 3182 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3183
3184 memset(umr, 0, sizeof(*umr));
3185
968e78dd
HE		 3186 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3187 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3188 else
3189 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3190
31616255
AK		 3191 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3192 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3193 u64 offset = get_xlt_octo(umrwr->offset);
3194
3195 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3196 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3197 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3198 }
31616255
AK		 3199 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3200 umr->mkey_mask |= get_umr_update_translation_mask();
3201 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3202 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3203 umr->mkey_mask |= get_umr_update_pd_mask();
3204 }
3205 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3206 umr->mkey_mask |= get_umr_enable_mr_mask();
3207 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3208 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3209
3210 if (!wr->num_sge)
968e78dd 3211 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3212}
3213
3214static u8 get_umr_flags(int acc)
3215{
3216 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3217 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3218 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3219 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3220 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3221}
3222
8a187ee5
SG		 3223static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3224 struct mlx5_ib_mr *mr,
3225 u32 key, int access)
3226{
3227 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3228
3229 memset(seg, 0, sizeof(*seg));
b005d316 3230
ec22eb53 3231 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3232 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3233 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3234 /* KLMs take twice the size of MTTs */
3235 ndescs *= 2;
3236
3237 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3238 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3239 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3240 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3241 seg->len = cpu_to_be64(mr->ibmr.length);
3242 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3243}
3244
dd01e66a 3245static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3246{
3247 memset(seg, 0, sizeof(*seg));
dd01e66a 3248 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3249}
3250
3251static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3252{
e622f2f4 3253 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3254
e126ba97 3255 memset(seg, 0, sizeof(*seg));
31616255 3256 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3257 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3258
968e78dd 3259 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3260 if (umrwr->pd)
3261 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3262 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3263 !umrwr->length)
3264 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3265
3266 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3267 seg->len = cpu_to_be64(umrwr->length);
3268 seg->log2_page_size = umrwr->page_shift;
746b5583 3269 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3270 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3271}
3272
8a187ee5
SG		 3273static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3274 struct mlx5_ib_mr *mr,
3275 struct mlx5_ib_pd *pd)
3276{
3277 int bcount = mr->desc_size * mr->ndescs;
3278
3279 dseg->addr = cpu_to_be64(mr->desc_map);
3280 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3281 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3282}
3283
e126ba97
EC		 3284static __be32 send_ieth(struct ib_send_wr *wr)
3285{
3286 switch (wr->opcode) {
3287 case IB_WR_SEND_WITH_IMM:
3288 case IB_WR_RDMA_WRITE_WITH_IMM:
3289 return wr->ex.imm_data;
3290
3291 case IB_WR_SEND_WITH_INV:
3292 return cpu_to_be32(wr->ex.invalidate_rkey);
3293
3294 default:
3295 return 0;
3296 }
3297}
3298
3299static u8 calc_sig(void *wqe, int size)
3300{
3301 u8 *p = wqe;
3302 u8 res = 0;
3303 int i;
3304
3305 for (i = 0; i < size; i++)
3306 res ^= p[i];
3307
3308 return ~res;
3309}
3310
3311static u8 wq_sig(void *wqe)
3312{
3313 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3314}
3315
3316static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3317 void *wqe, int *sz)
3318{
3319 struct mlx5_wqe_inline_seg *seg;
3320 void *qend = qp->sq.qend;
3321 void *addr;
3322 int inl = 0;
3323 int copy;
3324 int len;
3325 int i;
3326
3327 seg = wqe;
3328 wqe += sizeof(*seg);
3329 for (i = 0; i < wr->num_sge; i++) {
3330 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3331 len = wr->sg_list[i].length;
3332 inl += len;
3333
3334 if (unlikely(inl > qp->max_inline_data))
3335 return -ENOMEM;
3336
3337 if (unlikely(wqe + len > qend)) {
3338 copy = qend - wqe;
3339 memcpy(wqe, addr, copy);
3340 addr += copy;
3341 len -= copy;
3342 wqe = mlx5_get_send_wqe(qp, 0);
3343 }
3344 memcpy(wqe, addr, len);
3345 wqe += len;
3346 }
3347
3348 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3349
3350 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3351
3352 return 0;
3353}
3354
e6631814
SG		 3355static u16 prot_field_size(enum ib_signature_type type)
3356{
3357 switch (type) {
3358 case IB_SIG_TYPE_T10_DIF:
3359 return MLX5_DIF_SIZE;
3360 default:
3361 return 0;
3362 }
3363}
3364
3365static u8 bs_selector(int block_size)
3366{
3367 switch (block_size) {
3368 case 512: return 0x1;
3369 case 520: return 0x2;
3370 case 4096: return 0x3;
3371 case 4160: return 0x4;
3372 case 1073741824: return 0x5;
3373 default: return 0;
3374 }
3375}
3376
78eda2bb
SG		 3377static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3378 struct mlx5_bsf_inl *inl)
e6631814 3379{
142537f4
SG		 3380 /* Valid inline section and allow BSF refresh */
3381 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3382 MLX5_BSF_REFRESH_DIF);
3383 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3384 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3385 /* repeating block */
3386 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3387 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3388 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3389
78eda2bb
SG		 3390 if (domain->sig.dif.ref_remap)
3391 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3392
78eda2bb
SG		 3393 if (domain->sig.dif.app_escape) {
3394 if (domain->sig.dif.ref_escape)
3395 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3396 else
3397 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3398 }
3399
78eda2bb
SG		 3400 inl->dif_app_bitmask_check =
3401 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3402}
3403
3404static int mlx5_set_bsf(struct ib_mr *sig_mr,
3405 struct ib_sig_attrs *sig_attrs,
3406 struct mlx5_bsf *bsf, u32 data_size)
3407{
3408 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3409 struct mlx5_bsf_basic *basic = &bsf->basic;
3410 struct ib_sig_domain *mem = &sig_attrs->mem;
3411 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3412
c7f44fbd 3413 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3414
3415 /* Basic + Extended + Inline */
3416 basic->bsf_size_sbs = 1 << 7;
3417 /* Input domain check byte mask */
3418 basic->check_byte_mask = sig_attrs->check_mask;
3419 basic->raw_data_size = cpu_to_be32(data_size);
3420
3421 /* Memory domain */
e6631814 3422 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3423 case IB_SIG_TYPE_NONE:
3424 break;
e6631814 3425 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3426 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3427 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3428 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3429 break;
3430 default:
3431 return -EINVAL;
3432 }
e6631814 3433
78eda2bb
SG		 3434 /* Wire domain */
3435 switch (sig_attrs->wire.sig_type) {
3436 case IB_SIG_TYPE_NONE:
3437 break;
3438 case IB_SIG_TYPE_T10_DIF:
e6631814 3439 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3440 mem->sig_type == wire->sig_type) {
e6631814 3441 /* Same block structure */
142537f4 3442 basic->bsf_size_sbs |= 1 << 4;
e6631814 3443 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3444 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3445 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3446 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3447 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3448 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3449 } else
3450 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3451
142537f4 3452 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3453 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3454 break;
e6631814
SG		 3455 default:
3456 return -EINVAL;
3457 }
3458
3459 return 0;
3460}
3461
e622f2f4
CH		 3462static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3463 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3464{
e622f2f4
CH		 3465 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3466 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3467 struct mlx5_bsf *bsf;
e622f2f4
CH		 3468 u32 data_len = wr->wr.sg_list->length;
3469 u32 data_key = wr->wr.sg_list->lkey;
3470 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3471 int ret;
3472 int wqe_size;
3473
e622f2f4
CH		 3474 if (!wr->prot ||
3475 (data_key == wr->prot->lkey &&
3476 data_va == wr->prot->addr &&
3477 data_len == wr->prot->length)) {
e6631814
SG		 3478 /**
3479 * Source domain doesn't contain signature information
5c273b16 3480 * or data and protection are interleaved in memory.
e6631814
SG		 3481 * So need construct:
3482 * ------------------
3483 * | data_klm |
3484 * ------------------
3485 * | BSF |
3486 * ------------------
3487 **/
3488 struct mlx5_klm *data_klm = *seg;
3489
3490 data_klm->bcount = cpu_to_be32(data_len);
3491 data_klm->key = cpu_to_be32(data_key);
3492 data_klm->va = cpu_to_be64(data_va);
3493 wqe_size = ALIGN(sizeof(*data_klm), 64);
3494 } else {
3495 /**
3496 * Source domain contains signature information
3497 * So need construct a strided block format:
3498 * ---------------------------
3499 * | stride_block_ctrl |
3500 * ---------------------------
3501 * | data_klm |
3502 * ---------------------------
3503 * | prot_klm |
3504 * ---------------------------
3505 * | BSF |
3506 * ---------------------------
3507 **/
3508 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3509 struct mlx5_stride_block_entry *data_sentry;
3510 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3511 u32 prot_key = wr->prot->lkey;
3512 u64 prot_va = wr->prot->addr;
e6631814
SG		 3513 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3514 int prot_size;
3515
3516 sblock_ctrl = *seg;
3517 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3518 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3519
3520 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3521 if (!prot_size) {
3522 pr_err("Bad block size given: %u\n", block_size);
3523 return -EINVAL;
3524 }
3525 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3526 prot_size);
3527 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3528 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3529 sblock_ctrl->num_entries = cpu_to_be16(2);
3530
3531 data_sentry->bcount = cpu_to_be16(block_size);
3532 data_sentry->key = cpu_to_be32(data_key);
3533 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3534 data_sentry->stride = cpu_to_be16(block_size);
3535
e6631814
SG		 3536 prot_sentry->bcount = cpu_to_be16(prot_size);
3537 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3538 prot_sentry->va = cpu_to_be64(prot_va);
3539 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3540
e6631814
SG		 3541 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3542 sizeof(*prot_sentry), 64);
3543 }
3544
3545 *seg += wqe_size;
3546 *size += wqe_size / 16;
3547 if (unlikely((*seg == qp->sq.qend)))
3548 *seg = mlx5_get_send_wqe(qp, 0);
3549
3550 bsf = *seg;
3551 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3552 if (ret)
3553 return -EINVAL;
3554
3555 *seg += sizeof(*bsf);
3556 *size += sizeof(*bsf) / 16;
3557 if (unlikely((*seg == qp->sq.qend)))
3558 *seg = mlx5_get_send_wqe(qp, 0);
3559
3560 return 0;
3561}
3562
3563static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 3564 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 3565 u32 length, u32 pdn)
3566{
e622f2f4 3567 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3568 u32 sig_key = sig_mr->rkey;
d5436ba0 3569 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3570
3571 memset(seg, 0, sizeof(*seg));
3572
e622f2f4 3573 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3574 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3575 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3576 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3577 MLX5_MKEY_BSF_EN | pdn);
3578 seg->len = cpu_to_be64(length);
31616255 3579 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 3580 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3581}
3582
3583static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3584 u32 size)
e6631814
SG		 3585{
3586 memset(umr, 0, sizeof(*umr));
3587
3588 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 3589 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 3590 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3591 umr->mkey_mask = sig_mkey_mask();
3592}
3593
3594
e622f2f4 3595static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3596 void **seg, int *size)
3597{
e622f2f4
CH		 3598 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3599 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 3600 u32 pdn = get_pd(qp)->pdn;
31616255 3601 u32 xlt_size;
e6631814
SG		 3602 int region_len, ret;
3603
e622f2f4
CH		 3604 if (unlikely(wr->wr.num_sge != 1) ||
3605 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3606 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3607 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3608 return -EINVAL;
3609
3610 /* length of the protected region, data + protection */
e622f2f4
CH		 3611 region_len = wr->wr.sg_list->length;
3612 if (wr->prot &&
3613 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3614 wr->prot->addr != wr->wr.sg_list->addr ||
3615 wr->prot->length != wr->wr.sg_list->length))
3616 region_len += wr->prot->length;
e6631814
SG		 3617
3618 /**
3619 * KLM octoword size - if protection was provided
3620 * then we use strided block format (3 octowords),
3621 * else we use single KLM (1 octoword)
3622 **/
31616255 3623 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 3624
31616255 3625 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 3626 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3627 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3628 if (unlikely((*seg == qp->sq.qend)))
3629 *seg = mlx5_get_send_wqe(qp, 0);
3630
31616255 3631 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 3632 *seg += sizeof(struct mlx5_mkey_seg);
3633 *size += sizeof(struct mlx5_mkey_seg) / 16;
3634 if (unlikely((*seg == qp->sq.qend)))
3635 *seg = mlx5_get_send_wqe(qp, 0);
3636
3637 ret = set_sig_data_segment(wr, qp, seg, size);
3638 if (ret)
3639 return ret;
3640
d5436ba0 3641 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3642 return 0;
3643}
3644
3645static int set_psv_wr(struct ib_sig_domain *domain,
3646 u32 psv_idx, void **seg, int *size)
3647{
3648 struct mlx5_seg_set_psv *psv_seg = *seg;
3649
3650 memset(psv_seg, 0, sizeof(*psv_seg));
3651 psv_seg->psv_num = cpu_to_be32(psv_idx);
3652 switch (domain->sig_type) {
78eda2bb
SG		 3653 case IB_SIG_TYPE_NONE:
3654 break;
e6631814
SG		 3655 case IB_SIG_TYPE_T10_DIF:
3656 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3657 domain->sig.dif.app_tag);
3658 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3659 break;
e6631814 3660 default:
12bbf1ea
LR		 3661 pr_err("Bad signature type (%d) is given.\n",
3662 domain->sig_type);
3663 return -EINVAL;
e6631814
SG		 3664 }
3665
78eda2bb
SG		 3666 *seg += sizeof(*psv_seg);
3667 *size += sizeof(*psv_seg) / 16;
3668
e6631814
SG		 3669 return 0;
3670}
3671
8a187ee5
SG		 3672static int set_reg_wr(struct mlx5_ib_qp *qp,
3673 struct ib_reg_wr *wr,
3674 void **seg, int *size)
3675{
3676 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3677 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3678
3679 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3680 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3681 "Invalid IB_SEND_INLINE send flag\n");
3682 return -EINVAL;
3683 }
3684
3685 set_reg_umr_seg(*seg, mr);
3686 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3687 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3688 if (unlikely((*seg == qp->sq.qend)))
3689 *seg = mlx5_get_send_wqe(qp, 0);
3690
3691 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3692 *seg += sizeof(struct mlx5_mkey_seg);
3693 *size += sizeof(struct mlx5_mkey_seg) / 16;
3694 if (unlikely((*seg == qp->sq.qend)))
3695 *seg = mlx5_get_send_wqe(qp, 0);
3696
3697 set_reg_data_seg(*seg, mr, pd);
3698 *seg += sizeof(struct mlx5_wqe_data_seg);
3699 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3700
3701 return 0;
3702}
3703
dd01e66a 3704static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3705{
dd01e66a 3706 set_linv_umr_seg(*seg);
e126ba97
EC		 3707 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3708 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3709 if (unlikely((*seg == qp->sq.qend)))
3710 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3711 set_linv_mkey_seg(*seg);
e126ba97
EC		 3712 *seg += sizeof(struct mlx5_mkey_seg);
3713 *size += sizeof(struct mlx5_mkey_seg) / 16;
3714 if (unlikely((*seg == qp->sq.qend)))
3715 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3716}
3717
3718static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3719{
3720 __be32 *p = NULL;
3721 int tidx = idx;
3722 int i, j;
3723
3724 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3725 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3726 if ((i & 0xf) == 0) {
3727 void *buf = mlx5_get_send_wqe(qp, tidx);
3728 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3729 p = buf;
3730 j = 0;
3731 }
3732 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3733 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3734 be32_to_cpu(p[j + 3]));
3735 }
3736}
3737
e126ba97
EC		 3738static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3739{
3740 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3741 wr->send_flags & IB_SEND_FENCE))
3742 return MLX5_FENCE_MODE_STRONG_ORDERING;
3743
3744 if (unlikely(fence)) {
3745 if (wr->send_flags & IB_SEND_FENCE)
3746 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3747 else
3748 return fence;
c9b25495
EC		 3749 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3750 return MLX5_FENCE_MODE_FENCE;
e126ba97 3751 }
c9b25495
EC		 3752
3753 return 0;
e126ba97
EC		 3754}
3755
6e5eadac
SG		 3756static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3757 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3758 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3759 int *size, int nreq)
3760{
b2a232d2
LR		 3761 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3762 return -ENOMEM;
6e5eadac
SG		 3763
3764 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3765 *seg = mlx5_get_send_wqe(qp, *idx);
3766 *ctrl = *seg;
3767 *(uint32_t *)(*seg + 8) = 0;
3768 (*ctrl)->imm = send_ieth(wr);
3769 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3770 (wr->send_flags & IB_SEND_SIGNALED ?
3771 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3772 (wr->send_flags & IB_SEND_SOLICITED ?
3773 MLX5_WQE_CTRL_SOLICITED : 0);
3774
3775 *seg += sizeof(**ctrl);
3776 *size = sizeof(**ctrl) / 16;
3777
b2a232d2 3778 return 0;
6e5eadac
SG		 3779}
3780
3781static void finish_wqe(struct mlx5_ib_qp *qp,
3782 struct mlx5_wqe_ctrl_seg *ctrl,
3783 u8 size, unsigned idx, u64 wr_id,
3784 int nreq, u8 fence, u8 next_fence,
3785 u32 mlx5_opcode)
3786{
3787 u8 opmod = 0;
3788
3789 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3790 mlx5_opcode | ((u32)opmod << 24));
19098df2 3791 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3792 ctrl->fm_ce_se |= fence;
3793 qp->fm_cache = next_fence;
3794 if (unlikely(qp->wq_sig))
3795 ctrl->signature = wq_sig(ctrl);
3796
3797 qp->sq.wrid[idx] = wr_id;
3798 qp->sq.w_list[idx].opcode = mlx5_opcode;
3799 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3800 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3801 qp->sq.w_list[idx].next = qp->sq.cur_post;
3802}
3803
3804
e126ba97
EC		 3805int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3806 struct ib_send_wr **bad_wr)
3807{
3808 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3809 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3810 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3811 struct mlx5_ib_qp *qp;
e6631814 3812 struct mlx5_ib_mr *mr;
e126ba97
EC		 3813 struct mlx5_wqe_data_seg *dpseg;
3814 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3815 struct mlx5_bf *bf;
e126ba97 3816 int uninitialized_var(size);
d16e91da 3817 void *qend;
e126ba97 3818 unsigned long flags;
e126ba97
EC		 3819 unsigned idx;
3820 int err = 0;
3821 int inl = 0;
3822 int num_sge;
3823 void *seg;
3824 int nreq;
3825 int i;
3826 u8 next_fence = 0;
e126ba97
EC		 3827 u8 fence;
3828
d16e91da
HE		 3829 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3830 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3831
3832 qp = to_mqp(ibqp);
5fe9dec0 3833 bf = &qp->bf;
d16e91da
HE		 3834 qend = qp->sq.qend;
3835
e126ba97
EC		 3836 spin_lock_irqsave(&qp->sq.lock, flags);
3837
89ea94a7
MG		 3838 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3839 err = -EIO;
3840 *bad_wr = wr;
3841 nreq = 0;
3842 goto out;
3843 }
3844
e126ba97 3845 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3846 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3847 mlx5_ib_warn(dev, "\n");
3848 err = -EINVAL;
3849 *bad_wr = wr;
3850 goto out;
3851 }
3852
6e5eadac
SG		 3853 fence = qp->fm_cache;
3854 num_sge = wr->num_sge;
3855 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 3856 mlx5_ib_warn(dev, "\n");
24be409b 3857 err = -EINVAL;
e126ba97
EC		 3858 *bad_wr = wr;
3859 goto out;
3860 }
3861
6e5eadac
SG		 3862 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3863 if (err) {
e126ba97
EC		 3864 mlx5_ib_warn(dev, "\n");
3865 err = -ENOMEM;
3866 *bad_wr = wr;
3867 goto out;
3868 }
3869
e126ba97
EC		 3870 switch (ibqp->qp_type) {
3871 case IB_QPT_XRC_INI:
3872 xrc = seg;
e126ba97
EC		 3873 seg += sizeof(*xrc);
3874 size += sizeof(*xrc) / 16;
3875 /* fall through */
3876 case IB_QPT_RC:
3877 switch (wr->opcode) {
3878 case IB_WR_RDMA_READ:
3879 case IB_WR_RDMA_WRITE:
3880 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3881 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3882 rdma_wr(wr)->rkey);
f241e749 3883 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3884 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3885 break;
3886
3887 case IB_WR_ATOMIC_CMP_AND_SWP:
3888 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3889 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3890 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3891 err = -ENOSYS;
3892 *bad_wr = wr;
3893 goto out;
e126ba97
EC		 3894
3895 case IB_WR_LOCAL_INV:
3896 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3897 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3898 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3899 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3900 num_sge = 0;
3901 break;
3902
8a187ee5
SG		 3903 case IB_WR_REG_MR:
3904 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3905 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3906 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3907 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3908 if (err) {
3909 *bad_wr = wr;
3910 goto out;
3911 }
3912 num_sge = 0;
3913 break;
3914
e6631814
SG		 3915 case IB_WR_REG_SIG_MR:
3916 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3917 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3918
3919 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3920 err = set_sig_umr_wr(wr, qp, &seg, &size);
3921 if (err) {
3922 mlx5_ib_warn(dev, "\n");
3923 *bad_wr = wr;
3924 goto out;
3925 }
3926
3927 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3928 nreq, get_fence(fence, wr),
3929 next_fence, MLX5_OPCODE_UMR);
3930 /*
3931 * SET_PSV WQEs are not signaled and solicited
3932 * on error
3933 */
3934 wr->send_flags &= ~IB_SEND_SIGNALED;
3935 wr->send_flags |= IB_SEND_SOLICITED;
3936 err = begin_wqe(qp, &seg, &ctrl, wr,
3937 &idx, &size, nreq);
3938 if (err) {
3939 mlx5_ib_warn(dev, "\n");
3940 err = -ENOMEM;
3941 *bad_wr = wr;
3942 goto out;
3943 }
3944
e622f2f4 3945 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3946 mr->sig->psv_memory.psv_idx, &seg,
3947 &size);
3948 if (err) {
3949 mlx5_ib_warn(dev, "\n");
3950 *bad_wr = wr;
3951 goto out;
3952 }
3953
3954 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3955 nreq, get_fence(fence, wr),
3956 next_fence, MLX5_OPCODE_SET_PSV);
3957 err = begin_wqe(qp, &seg, &ctrl, wr,
3958 &idx, &size, nreq);
3959 if (err) {
3960 mlx5_ib_warn(dev, "\n");
3961 err = -ENOMEM;
3962 *bad_wr = wr;
3963 goto out;
3964 }
3965
3966 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3967 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3968 mr->sig->psv_wire.psv_idx, &seg,
3969 &size);
3970 if (err) {
3971 mlx5_ib_warn(dev, "\n");
3972 *bad_wr = wr;
3973 goto out;
3974 }
3975
3976 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3977 nreq, get_fence(fence, wr),
3978 next_fence, MLX5_OPCODE_SET_PSV);
3979 num_sge = 0;
3980 goto skip_psv;
3981
e126ba97
EC		 3982 default:
3983 break;
3984 }
3985 break;
3986
3987 case IB_QPT_UC:
3988 switch (wr->opcode) {
3989 case IB_WR_RDMA_WRITE:
3990 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3991 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3992 rdma_wr(wr)->rkey);
e126ba97
EC		 3993 seg += sizeof(struct mlx5_wqe_raddr_seg);
3994 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3995 break;
3996
3997 default:
3998 break;
3999 }
4000 break;
4001
e126ba97 4002 case IB_QPT_SMI:
1e0e50b6
MG		 4003 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4004 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4005 err = -EPERM;
4006 *bad_wr = wr;
4007 goto out;
4008 }
d16e91da 4009 case MLX5_IB_QPT_HW_GSI:
e126ba97 4010 set_datagram_seg(seg, wr);
f241e749 4011 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4012 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4013 if (unlikely((seg == qend)))
4014 seg = mlx5_get_send_wqe(qp, 0);
4015 break;
f0313965
ES		 4016 case IB_QPT_UD:
4017 set_datagram_seg(seg, wr);
4018 seg += sizeof(struct mlx5_wqe_datagram_seg);
4019 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4020
4021 if (unlikely((seg == qend)))
4022 seg = mlx5_get_send_wqe(qp, 0);
4023
4024 /* handle qp that supports ud offload */
4025 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4026 struct mlx5_wqe_eth_pad *pad;
e126ba97 4027
f0313965
ES		 4028 pad = seg;
4029 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4030 seg += sizeof(struct mlx5_wqe_eth_pad);
4031 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4032
4033 seg = set_eth_seg(seg, wr, qend, qp, &size);
4034
4035 if (unlikely((seg == qend)))
4036 seg = mlx5_get_send_wqe(qp, 0);
4037 }
4038 break;
e126ba97
EC		 4039 case MLX5_IB_QPT_REG_UMR:
4040 if (wr->opcode != MLX5_IB_WR_UMR) {
4041 err = -EINVAL;
4042 mlx5_ib_warn(dev, "bad opcode\n");
4043 goto out;
4044 }
4045 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4046 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4047 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4048 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4049 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4050 if (unlikely((seg == qend)))
4051 seg = mlx5_get_send_wqe(qp, 0);
4052 set_reg_mkey_segment(seg, wr);
4053 seg += sizeof(struct mlx5_mkey_seg);
4054 size += sizeof(struct mlx5_mkey_seg) / 16;
4055 if (unlikely((seg == qend)))
4056 seg = mlx5_get_send_wqe(qp, 0);
4057 break;
4058
4059 default:
4060 break;
4061 }
4062
4063 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4064 int uninitialized_var(sz);
4065
4066 err = set_data_inl_seg(qp, wr, seg, &sz);
4067 if (unlikely(err)) {
4068 mlx5_ib_warn(dev, "\n");
4069 *bad_wr = wr;
4070 goto out;
4071 }
4072 inl = 1;
4073 size += sz;
4074 } else {
4075 dpseg = seg;
4076 for (i = 0; i < num_sge; i++) {
4077 if (unlikely(dpseg == qend)) {
4078 seg = mlx5_get_send_wqe(qp, 0);
4079 dpseg = seg;
4080 }
4081 if (likely(wr->sg_list[i].length)) {
4082 set_data_ptr_seg(dpseg, wr->sg_list + i);
4083 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4084 dpseg++;
4085 }
4086 }
4087 }
4088
6e5eadac
SG		 4089 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4090 get_fence(fence, wr), next_fence,
4091 mlx5_ib_opcode[wr->opcode]);
e6631814 4092skip_psv:
e126ba97
EC		 4093 if (0)
4094 dump_wqe(qp, idx, size);
4095 }
4096
4097out:
4098 if (likely(nreq)) {
4099 qp->sq.head += nreq;
4100
4101 /* Make sure that descriptors are written before
4102 * updating doorbell record and ringing the doorbell
4103 */
4104 wmb();
4105
4106 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4107
ada388f7
EC		 4108 /* Make sure doorbell record is visible to the HCA before
4109 * we hit doorbell */
4110 wmb();
4111
5fe9dec0
EC		 4112 /* currently we support only regular doorbells */
4113 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4114 /* Make sure doorbells don't leak out of SQ spinlock
4115 * and reach the HCA out of order.
4116 */
4117 mmiowb();
e126ba97 4118 bf->offset ^= bf->buf_size;
e126ba97
EC		 4119 }
4120
4121 spin_unlock_irqrestore(&qp->sq.lock, flags);
4122
4123 return err;
4124}
4125
4126static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4127{
4128 sig->signature = calc_sig(sig, size);
4129}
4130
4131int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4132 struct ib_recv_wr **bad_wr)
4133{
4134 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4135 struct mlx5_wqe_data_seg *scat;
4136 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4137 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4138 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4139 unsigned long flags;
4140 int err = 0;
4141 int nreq;
4142 int ind;
4143 int i;
4144
d16e91da
HE		 4145 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4146 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4147
e126ba97
EC		 4148 spin_lock_irqsave(&qp->rq.lock, flags);
4149
89ea94a7
MG		 4150 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4151 err = -EIO;
4152 *bad_wr = wr;
4153 nreq = 0;
4154 goto out;
4155 }
4156
e126ba97
EC		 4157 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4158
4159 for (nreq = 0; wr; nreq++, wr = wr->next) {
4160 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4161 err = -ENOMEM;
4162 *bad_wr = wr;
4163 goto out;
4164 }
4165
4166 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4167 err = -EINVAL;
4168 *bad_wr = wr;
4169 goto out;
4170 }
4171
4172 scat = get_recv_wqe(qp, ind);
4173 if (qp->wq_sig)
4174 scat++;
4175
4176 for (i = 0; i < wr->num_sge; i++)
4177 set_data_ptr_seg(scat + i, wr->sg_list + i);
4178
4179 if (i < qp->rq.max_gs) {
4180 scat[i].byte_count = 0;
4181 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4182 scat[i].addr = 0;
4183 }
4184
4185 if (qp->wq_sig) {
4186 sig = (struct mlx5_rwqe_sig *)scat;
4187 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4188 }
4189
4190 qp->rq.wrid[ind] = wr->wr_id;
4191
4192 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4193 }
4194
4195out:
4196 if (likely(nreq)) {
4197 qp->rq.head += nreq;
4198
4199 /* Make sure that descriptors are written before
4200 * doorbell record.
4201 */
4202 wmb();
4203
4204 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4205 }
4206
4207 spin_unlock_irqrestore(&qp->rq.lock, flags);
4208
4209 return err;
4210}
4211
4212static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4213{
4214 switch (mlx5_state) {
4215 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4216 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4217 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4218 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4219 case MLX5_QP_STATE_SQ_DRAINING:
4220 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4221 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4222 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4223 default: return -1;
4224 }
4225}
4226
4227static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4228{
4229 switch (mlx5_mig_state) {
4230 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4231 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4232 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4233 default: return -1;
4234 }
4235}
4236
4237static int to_ib_qp_access_flags(int mlx5_flags)
4238{
4239 int ib_flags = 0;
4240
4241 if (mlx5_flags & MLX5_QP_BIT_RRE)
4242 ib_flags |= IB_ACCESS_REMOTE_READ;
4243 if (mlx5_flags & MLX5_QP_BIT_RWE)
4244 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4245 if (mlx5_flags & MLX5_QP_BIT_RAE)
4246 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4247
4248 return ib_flags;
4249}
4250
4251static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4252 struct mlx5_qp_path *path)
4253{
9603b61d 4254 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 4255
4256 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4257 ib_ah_attr->port_num = path->port;
4258
c7a08ac7 4259 if (ib_ah_attr->port_num == 0 ||
938fe83c 4260 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4261 return;
4262
2811ba51 4263 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 4264
4265 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4266 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4267 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4268 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4269 if (ib_ah_attr->ah_flags) {
4270 ib_ah_attr->grh.sgid_index = path->mgid_index;
4271 ib_ah_attr->grh.hop_limit = path->hop_limit;
4272 ib_ah_attr->grh.traffic_class =
4273 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4274 ib_ah_attr->grh.flow_label =
4275 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4276 memcpy(ib_ah_attr->grh.dgid.raw,
4277 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4278 }
4279}
4280
6d2f89df 4281static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4282 struct mlx5_ib_sq *sq,
4283 u8 *sq_state)
4284{
4285 void *out;
4286 void *sqc;
4287 int inlen;
4288 int err;
4289
4290 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4291 out = mlx5_vzalloc(inlen);
4292 if (!out)
4293 return -ENOMEM;
4294
4295 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4296 if (err)
4297 goto out;
4298
4299 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4300 *sq_state = MLX5_GET(sqc, sqc, state);
4301 sq->state = *sq_state;
4302
4303out:
4304 kvfree(out);
4305 return err;
4306}
4307
4308static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4309 struct mlx5_ib_rq *rq,
4310 u8 *rq_state)
4311{
4312 void *out;
4313 void *rqc;
4314 int inlen;
4315 int err;
4316
4317 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4318 out = mlx5_vzalloc(inlen);
4319 if (!out)
4320 return -ENOMEM;
4321
4322 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4323 if (err)
4324 goto out;
4325
4326 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4327 *rq_state = MLX5_GET(rqc, rqc, state);
4328 rq->state = *rq_state;
4329
4330out:
4331 kvfree(out);
4332 return err;
4333}
4334
4335static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4336 struct mlx5_ib_qp *qp, u8 *qp_state)
4337{
4338 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4339 [MLX5_RQC_STATE_RST] = {
4340 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4341 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4342 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4343 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4344 },
4345 [MLX5_RQC_STATE_RDY] = {
4346 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4347 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4348 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4349 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4350 },
4351 [MLX5_RQC_STATE_ERR] = {
4352 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4353 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4354 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4355 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4356 },
4357 [MLX5_RQ_STATE_NA] = {
4358 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4359 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4360 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4361 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4362 },
4363 };
4364
4365 *qp_state = sqrq_trans[rq_state][sq_state];
4366
4367 if (*qp_state == MLX5_QP_STATE_BAD) {
4368 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4369 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4370 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4371 return -EINVAL;
4372 }
4373
4374 if (*qp_state == MLX5_QP_STATE)
4375 *qp_state = qp->state;
4376
4377 return 0;
4378}
4379
4380static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4381 struct mlx5_ib_qp *qp,
4382 u8 *raw_packet_qp_state)
4383{
4384 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4385 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4386 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4387 int err;
4388 u8 sq_state = MLX5_SQ_STATE_NA;
4389 u8 rq_state = MLX5_RQ_STATE_NA;
4390
4391 if (qp->sq.wqe_cnt) {
4392 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4393 if (err)
4394 return err;
4395 }
4396
4397 if (qp->rq.wqe_cnt) {
4398 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4399 if (err)
4400 return err;
4401 }
4402
4403 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4404 raw_packet_qp_state);
4405}
4406
4407static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4408 struct ib_qp_attr *qp_attr)
e126ba97 4409{
09a7d9ec 4410 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4411 struct mlx5_qp_context *context;
4412 int mlx5_state;
09a7d9ec 4413 u32 *outb;
e126ba97
EC		 4414 int err = 0;
4415
09a7d9ec 4416 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4417 if (!outb)
4418 return -ENOMEM;
4419
19098df2 4420 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4421 outlen);
e126ba97 4422 if (err)
6d2f89df 4423 goto out;
e126ba97 4424
09a7d9ec
SM		 4425 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4426 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4427
e126ba97
EC		 4428 mlx5_state = be32_to_cpu(context->flags) >> 28;
4429
4430 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4431 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4432 qp_attr->path_mig_state =
4433 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4434 qp_attr->qkey = be32_to_cpu(context->qkey);
4435 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4436 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4437 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4438 qp_attr->qp_access_flags =
4439 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4440
4441 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4442 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4443 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4444 qp_attr->alt_pkey_index =
4445 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4446 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4447 }
4448
d3ae2bde 4449 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4450 qp_attr->port_num = context->pri_path.port;
4451
4452 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4453 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4454
4455 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4456
4457 qp_attr->max_dest_rd_atomic =
4458 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4459 qp_attr->min_rnr_timer =
4460 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4461 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4462 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4463 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4464 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4465
4466out:
4467 kfree(outb);
4468 return err;
4469}
4470
4471int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4472 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4473{
4474 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4475 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4476 int err = 0;
4477 u8 raw_packet_qp_state;
4478
28d61370
YH		 4479 if (ibqp->rwq_ind_tbl)
4480 return -ENOSYS;
4481
d16e91da
HE		 4482 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4483 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4484 qp_init_attr);
4485
6d2f89df 4486 mutex_lock(&qp->mutex);
4487
4488 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4489 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4490 if (err)
4491 goto out;
4492 qp->state = raw_packet_qp_state;
4493 qp_attr->port_num = 1;
4494 } else {
4495 err = query_qp_attr(dev, qp, qp_attr);
4496 if (err)
4497 goto out;
4498 }
4499
4500 qp_attr->qp_state = qp->state;
e126ba97
EC		 4501 qp_attr->cur_qp_state = qp_attr->qp_state;
4502 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4503 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4504
4505 if (!ibqp->uobject) {
0540d814 4506 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4507 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4508 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4509 } else {
4510 qp_attr->cap.max_send_wr = 0;
4511 qp_attr->cap.max_send_sge = 0;
4512 }
4513
0540d814
NO		 4514 qp_init_attr->qp_type = ibqp->qp_type;
4515 qp_init_attr->recv_cq = ibqp->recv_cq;
4516 qp_init_attr->send_cq = ibqp->send_cq;
4517 qp_init_attr->srq = ibqp->srq;
4518 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4519
4520 qp_init_attr->cap = qp_attr->cap;
4521
4522 qp_init_attr->create_flags = 0;
4523 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4524 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4525
051f2630
LR		 4526 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4527 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4528 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4529 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4530 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4531 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4532 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4533 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4534
e126ba97
EC		 4535 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4536 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4537
e126ba97
EC		 4538out:
4539 mutex_unlock(&qp->mutex);
4540 return err;
4541}
4542
4543struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4544 struct ib_ucontext *context,
4545 struct ib_udata *udata)
4546{
4547 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4548 struct mlx5_ib_xrcd *xrcd;
4549 int err;
4550
938fe83c 4551 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4552 return ERR_PTR(-ENOSYS);
4553
4554 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4555 if (!xrcd)
4556 return ERR_PTR(-ENOMEM);
4557
9603b61d 4558 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4559 if (err) {
4560 kfree(xrcd);
4561 return ERR_PTR(-ENOMEM);
4562 }
4563
4564 return &xrcd->ibxrcd;
4565}
4566
4567int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4568{
4569 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4570 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4571 int err;
4572
9603b61d 4573 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4574 if (err) {
4575 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4576 return err;
4577 }
4578
4579 kfree(xrcd);
4580
4581 return 0;
4582}
79b20a6c 4583
350d0e4c
YH		 4584static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4585{
4586 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4587 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4588 struct ib_event event;
4589
4590 if (rwq->ibwq.event_handler) {
4591 event.device = rwq->ibwq.device;
4592 event.element.wq = &rwq->ibwq;
4593 switch (type) {
4594 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4595 event.event = IB_EVENT_WQ_FATAL;
4596 break;
4597 default:
4598 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4599 return;
4600 }
4601
4602 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4603 }
4604}
4605
79b20a6c
YH		 4606static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4607 struct ib_wq_init_attr *init_attr)
4608{
4609 struct mlx5_ib_dev *dev;
4be6da1e 4610 int has_net_offloads;
79b20a6c
YH		 4611 __be64 *rq_pas0;
4612 void *in;
4613 void *rqc;
4614 void *wq;
4615 int inlen;
4616 int err;
4617
4618 dev = to_mdev(pd->device);
4619
4620 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4621 in = mlx5_vzalloc(inlen);
4622 if (!in)
4623 return -ENOMEM;
4624
4625 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4626 MLX5_SET(rqc, rqc, mem_rq_type,
4627 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4628 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4629 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4630 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4631 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4632 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4633 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4634 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4635 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4636 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4637 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4638 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4639 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4640 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4641 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4642 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4643 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4644 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4645 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4646 err = -EOPNOTSUPP;
4647 goto out;
4648 }
4649 } else {
4650 MLX5_SET(rqc, rqc, vsd, 1);
4651 }
4be6da1e
NO		 4652 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4653 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4654 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4655 err = -EOPNOTSUPP;
4656 goto out;
4657 }
4658 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4659 }
79b20a6c
YH		 4660 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4661 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 4662 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
b1f74a84 4663out:
79b20a6c
YH		 4664 kvfree(in);
4665 return err;
4666}
4667
4668static int set_user_rq_size(struct mlx5_ib_dev *dev,
4669 struct ib_wq_init_attr *wq_init_attr,
4670 struct mlx5_ib_create_wq *ucmd,
4671 struct mlx5_ib_rwq *rwq)
4672{
4673 /* Sanity check RQ size before proceeding */
4674 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4675 return -EINVAL;
4676
4677 if (!ucmd->rq_wqe_count)
4678 return -EINVAL;
4679
4680 rwq->wqe_count = ucmd->rq_wqe_count;
4681 rwq->wqe_shift = ucmd->rq_wqe_shift;
4682 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4683 rwq->log_rq_stride = rwq->wqe_shift;
4684 rwq->log_rq_size = ilog2(rwq->wqe_count);
4685 return 0;
4686}
4687
4688static int prepare_user_rq(struct ib_pd *pd,
4689 struct ib_wq_init_attr *init_attr,
4690 struct ib_udata *udata,
4691 struct mlx5_ib_rwq *rwq)
4692{
4693 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4694 struct mlx5_ib_create_wq ucmd = {};
4695 int err;
4696 size_t required_cmd_sz;
4697
4698 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4699 if (udata->inlen < required_cmd_sz) {
4700 mlx5_ib_dbg(dev, "invalid inlen\n");
4701 return -EINVAL;
4702 }
4703
4704 if (udata->inlen > sizeof(ucmd) &&
4705 !ib_is_udata_cleared(udata, sizeof(ucmd),
4706 udata->inlen - sizeof(ucmd))) {
4707 mlx5_ib_dbg(dev, "inlen is not supported\n");
4708 return -EOPNOTSUPP;
4709 }
4710
4711 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4712 mlx5_ib_dbg(dev, "copy failed\n");
4713 return -EFAULT;
4714 }
4715
4716 if (ucmd.comp_mask) {
4717 mlx5_ib_dbg(dev, "invalid comp mask\n");
4718 return -EOPNOTSUPP;
4719 }
4720
4721 if (ucmd.reserved) {
4722 mlx5_ib_dbg(dev, "invalid reserved\n");
4723 return -EOPNOTSUPP;
4724 }
4725
4726 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4727 if (err) {
4728 mlx5_ib_dbg(dev, "err %d\n", err);
4729 return err;
4730 }
4731
4732 err = create_user_rq(dev, pd, rwq, &ucmd);
4733 if (err) {
4734 mlx5_ib_dbg(dev, "err %d\n", err);
4735 if (err)
4736 return err;
4737 }
4738
4739 rwq->user_index = ucmd.user_index;
4740 return 0;
4741}
4742
4743struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4744 struct ib_wq_init_attr *init_attr,
4745 struct ib_udata *udata)
4746{
4747 struct mlx5_ib_dev *dev;
4748 struct mlx5_ib_rwq *rwq;
4749 struct mlx5_ib_create_wq_resp resp = {};
4750 size_t min_resp_len;
4751 int err;
4752
4753 if (!udata)
4754 return ERR_PTR(-ENOSYS);
4755
4756 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4757 if (udata->outlen && udata->outlen < min_resp_len)
4758 return ERR_PTR(-EINVAL);
4759
4760 dev = to_mdev(pd->device);
4761 switch (init_attr->wq_type) {
4762 case IB_WQT_RQ:
4763 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4764 if (!rwq)
4765 return ERR_PTR(-ENOMEM);
4766 err = prepare_user_rq(pd, init_attr, udata, rwq);
4767 if (err)
4768 goto err;
4769 err = create_rq(rwq, pd, init_attr);
4770 if (err)
4771 goto err_user_rq;
4772 break;
4773 default:
4774 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4775 init_attr->wq_type);
4776 return ERR_PTR(-EINVAL);
4777 }
4778
350d0e4c 4779 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 4780 rwq->ibwq.state = IB_WQS_RESET;
4781 if (udata->outlen) {
4782 resp.response_length = offsetof(typeof(resp), response_length) +
4783 sizeof(resp.response_length);
4784 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4785 if (err)
4786 goto err_copy;
4787 }
4788
350d0e4c
YH		 4789 rwq->core_qp.event = mlx5_ib_wq_event;
4790 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 4791 return &rwq->ibwq;
4792
4793err_copy:
350d0e4c 4794 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4795err_user_rq:
4796 destroy_user_rq(pd, rwq);
4797err:
4798 kfree(rwq);
4799 return ERR_PTR(err);
4800}
4801
4802int mlx5_ib_destroy_wq(struct ib_wq *wq)
4803{
4804 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4805 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4806
350d0e4c 4807 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4808 destroy_user_rq(wq->pd, rwq);
4809 kfree(rwq);
4810
4811 return 0;
4812}
4813
c5f90929
YH		 4814struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4815 struct ib_rwq_ind_table_init_attr *init_attr,
4816 struct ib_udata *udata)
4817{
4818 struct mlx5_ib_dev *dev = to_mdev(device);
4819 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4820 int sz = 1 << init_attr->log_ind_tbl_size;
4821 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4822 size_t min_resp_len;
4823 int inlen;
4824 int err;
4825 int i;
4826 u32 *in;
4827 void *rqtc;
4828
4829 if (udata->inlen > 0 &&
4830 !ib_is_udata_cleared(udata, 0,
4831 udata->inlen))
4832 return ERR_PTR(-EOPNOTSUPP);
4833
efd7f400
MG		 4834 if (init_attr->log_ind_tbl_size >
4835 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4836 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4837 init_attr->log_ind_tbl_size,
4838 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4839 return ERR_PTR(-EINVAL);
4840 }
4841
c5f90929
YH		 4842 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4843 if (udata->outlen && udata->outlen < min_resp_len)
4844 return ERR_PTR(-EINVAL);
4845
4846 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4847 if (!rwq_ind_tbl)
4848 return ERR_PTR(-ENOMEM);
4849
4850 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4851 in = mlx5_vzalloc(inlen);
4852 if (!in) {
4853 err = -ENOMEM;
4854 goto err;
4855 }
4856
4857 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4858
4859 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4860 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4861
4862 for (i = 0; i < sz; i++)
4863 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4864
4865 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4866 kvfree(in);
4867
4868 if (err)
4869 goto err;
4870
4871 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4872 if (udata->outlen) {
4873 resp.response_length = offsetof(typeof(resp), response_length) +
4874 sizeof(resp.response_length);
4875 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4876 if (err)
4877 goto err_copy;
4878 }
4879
4880 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4881
4882err_copy:
4883 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4884err:
4885 kfree(rwq_ind_tbl);
4886 return ERR_PTR(err);
4887}
4888
4889int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4890{
4891 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4892 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4893
4894 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4895
4896 kfree(rwq_ind_tbl);
4897 return 0;
4898}
4899
79b20a6c
YH		 4900int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4901 u32 wq_attr_mask, struct ib_udata *udata)
4902{
4903 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4904 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4905 struct mlx5_ib_modify_wq ucmd = {};
4906 size_t required_cmd_sz;
4907 int curr_wq_state;
4908 int wq_state;
4909 int inlen;
4910 int err;
4911 void *rqc;
4912 void *in;
4913
4914 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4915 if (udata->inlen < required_cmd_sz)
4916 return -EINVAL;
4917
4918 if (udata->inlen > sizeof(ucmd) &&
4919 !ib_is_udata_cleared(udata, sizeof(ucmd),
4920 udata->inlen - sizeof(ucmd)))
4921 return -EOPNOTSUPP;
4922
4923 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4924 return -EFAULT;
4925
4926 if (ucmd.comp_mask || ucmd.reserved)
4927 return -EOPNOTSUPP;
4928
4929 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4930 in = mlx5_vzalloc(inlen);
4931 if (!in)
4932 return -ENOMEM;
4933
4934 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4935
4936 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4937 wq_attr->curr_wq_state : wq->state;
4938 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4939 wq_attr->wq_state : curr_wq_state;
4940 if (curr_wq_state == IB_WQS_ERR)
4941 curr_wq_state = MLX5_RQC_STATE_ERR;
4942 if (wq_state == IB_WQS_ERR)
4943 wq_state = MLX5_RQC_STATE_ERR;
4944 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4945 MLX5_SET(rqc, rqc, state, wq_state);
4946
b1f74a84
NO		 4947 if (wq_attr_mask & IB_WQ_FLAGS) {
4948 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4949 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
4950 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4951 mlx5_ib_dbg(dev, "VLAN offloads are not "
4952 "supported\n");
4953 err = -EOPNOTSUPP;
4954 goto out;
4955 }
4956 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4957 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
4958 MLX5_SET(rqc, rqc, vsd,
4959 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
4960 }
4961 }
4962
23a6964e
MD		 4963 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
4964 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
4965 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4966 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
4967 MLX5_SET(rqc, rqc, counter_set_id, dev->port->q_cnts.set_id);
4968 } else
4969 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
4970 dev->ib_dev.name);
4971 }
4972
350d0e4c 4973 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 4974 if (!err)
4975 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4976
b1f74a84
NO		 4977out:
4978 kvfree(in);
79b20a6c
YH		 4979 return err;
4980}
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