]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/infiniband/hw/mlx5/qp.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RDMA/mlx5: Change mlx5_ib_populate_pas() to use rdma_for_each_block()
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
d14133dd 37#include <rdma/rdma_counter.h>
c2e53b2c 38#include <linux/mlx5/fs.h>
e126ba97 39#include "mlx5_ib.h"
b96c9dde 40#include "ib_rep.h"
64825827 41#include "counters.h"
443c1cf9 42#include "cmd.h"
333fbaa0 43#include "qp.h"
029e88fd 44#include "wr.h"
e126ba97 45
e126ba97
EC		 46enum {
47 MLX5_IB_ACK_REQ_FREQ = 8,
48};
49
50enum {
51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
53 MLX5_IB_LINK_TYPE_IB = 0,
54 MLX5_IB_LINK_TYPE_ETH = 1
55};
56
eb49ab0c
AV		 57enum raw_qp_set_mask_map {
58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 60};
61
0680efa2
AV		 62struct mlx5_modify_raw_qp_param {
63 u16 operation;
eb49ab0c
AV		 64
65 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 66
67 struct mlx5_rate_limit rl;
68
eb49ab0c 69 u8 rq_q_ctr_id;
d5ed8ac3 70 u16 port;
0680efa2
AV		 71};
72
89ea94a7
MG		 73static void get_cqs(enum ib_qp_type qp_type,
74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
76
e126ba97
EC		 77static int is_qp0(enum ib_qp_type qp_type)
78{
79 return qp_type == IB_QPT_SMI;
80}
81
e126ba97
EC		 82static int is_sqp(enum ib_qp_type qp_type)
83{
84 return is_qp0(qp_type) || is_qp1(qp_type);
85}
86
c1395a2a 87/**
fbeb4075
MS		 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
89 * to kernel buffer
c1395a2a 90 *
fbeb4075
MS		 91 * @umem: User space memory where the WQ is
92 * @buffer: buffer to copy to
93 * @buflen: buffer length
94 * @wqe_index: index of WQE to copy from
95 * @wq_offset: offset to start of WQ
96 * @wq_wqe_cnt: number of WQEs in WQ
97 * @wq_wqe_shift: log2 of WQE size
98 * @bcnt: number of bytes to copy
99 * @bytes_copied: number of bytes to copy (return value)
c1395a2a 100 *
fbeb4075
MS		 101 * Copies from start of WQE bcnt or less bytes.
102 * Does not gurantee to copy the entire WQE.
c1395a2a 103 *
fbeb4075 104 * Return: zero on success, or an error code.
c1395a2a 105 */
da9ee9d8
MS		 106static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
107 size_t buflen, int wqe_index,
108 int wq_offset, int wq_wqe_cnt,
109 int wq_wqe_shift, int bcnt,
fbeb4075 110 size_t *bytes_copied)
c1395a2a 111{
fbeb4075
MS		 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
114 size_t copy_length;
c1395a2a
HE		 115 int ret;
116
fbeb4075
MS		 117 /* don't copy more than requested, more than buffer length or
118 * beyond WQ end
119 */
120 copy_length = min_t(u32, buflen, wq_end - offset);
121 copy_length = min_t(u32, copy_length, bcnt);
122
123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
124 if (ret)
125 return ret;
c1395a2a 126
fbeb4075
MS		 127 if (!ret && bytes_copied)
128 *bytes_copied = copy_length;
c1395a2a 129
fbeb4075
MS		 130 return 0;
131}
c1395a2a 132
da9ee9d8
MS		 133static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
134 void *buffer, size_t buflen, size_t *bc)
135{
136 struct mlx5_wqe_ctrl_seg *ctrl;
137 size_t bytes_copied = 0;
138 size_t wqe_length;
139 void *p;
140 int ds;
141
142 wqe_index = wqe_index & qp->sq.fbc.sz_m1;
143
144 /* read the control segment first */
145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
146 ctrl = p;
147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
148 wqe_length = ds * MLX5_WQE_DS_UNITS;
149
150 /* read rest of WQE if it spreads over more than one stride */
151 while (bytes_copied < wqe_length) {
152 size_t copy_length =
153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
154
155 if (!copy_length)
156 break;
157
158 memcpy(buffer + bytes_copied, p, copy_length);
159 bytes_copied += copy_length;
160
161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
163 }
164 *bc = bytes_copied;
165 return 0;
166}
167
168static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
169 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 170{
171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
172 struct ib_umem *umem = base->ubuffer.umem;
173 struct mlx5_ib_wq *wq = &qp->sq;
174 struct mlx5_wqe_ctrl_seg *ctrl;
175 size_t bytes_copied;
176 size_t bytes_copied2;
177 size_t wqe_length;
178 int ret;
179 int ds;
180
fbeb4075 181 /* at first read as much as possible */
da9ee9d8
MS		 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
183 wq->offset, wq->wqe_cnt,
184 wq->wqe_shift, buflen,
fbeb4075 185 &bytes_copied);
c1395a2a
HE		 186 if (ret)
187 return ret;
188
fbeb4075
MS		 189 /* we need at least control segment size to proceed */
190 if (bytes_copied < sizeof(*ctrl))
191 return -EINVAL;
192
193 ctrl = buffer;
194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
195 wqe_length = ds * MLX5_WQE_DS_UNITS;
c1395a2a 196
fbeb4075
MS		 197 /* if we copied enough then we are done */
198 if (bytes_copied >= wqe_length) {
199 *bc = bytes_copied;
200 return 0;
c1395a2a
HE		 201 }
202
fbeb4075
MS		 203 /* otherwise this a wrapped around wqe
204 * so read the remaining bytes starting
205 * from wqe_index 0
206 */
da9ee9d8
MS		 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
208 buflen - bytes_copied, 0, wq->offset,
209 wq->wqe_cnt, wq->wqe_shift,
fbeb4075
MS		 210 wqe_length - bytes_copied,
211 &bytes_copied2);
212
213 if (ret)
214 return ret;
215 *bc = bytes_copied + bytes_copied2;
216 return 0;
217}
218
da9ee9d8
MS		 219int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
220 size_t buflen, size_t *bc)
221{
222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
223 struct ib_umem *umem = base->ubuffer.umem;
224
225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
226 return -EINVAL;
227
228 if (!umem)
229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
230 buflen, bc);
231
232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
233}
234
235static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
236 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 237{
238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
239 struct ib_umem *umem = base->ubuffer.umem;
240 struct mlx5_ib_wq *wq = &qp->rq;
241 size_t bytes_copied;
242 int ret;
243
da9ee9d8
MS		 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
245 wq->offset, wq->wqe_cnt,
246 wq->wqe_shift, buflen,
fbeb4075 247 &bytes_copied);
c1395a2a 248
c1395a2a
HE		 249 if (ret)
250 return ret;
fbeb4075
MS		 251 *bc = bytes_copied;
252 return 0;
253}
254
da9ee9d8
MS		 255int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
256 size_t buflen, size_t *bc)
257{
258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
259 struct ib_umem *umem = base->ubuffer.umem;
260 struct mlx5_ib_wq *wq = &qp->rq;
261 size_t wqe_size = 1 << wq->wqe_shift;
262
263 if (buflen < wqe_size)
264 return -EINVAL;
265
266 if (!umem)
267 return -EOPNOTSUPP;
268
269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
270}
271
272static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
273 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 274{
275 struct ib_umem *umem = srq->umem;
276 size_t bytes_copied;
277 int ret;
c1395a2a 278
da9ee9d8
MS		 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
280 srq->msrq.max, srq->msrq.wqe_shift,
281 buflen, &bytes_copied);
fbeb4075
MS		 282
283 if (ret)
284 return ret;
285 *bc = bytes_copied;
286 return 0;
c1395a2a
HE		 287}
288
da9ee9d8
MS		 289int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
290 size_t buflen, size_t *bc)
291{
292 struct ib_umem *umem = srq->umem;
293 size_t wqe_size = 1 << srq->msrq.wqe_shift;
294
295 if (buflen < wqe_size)
296 return -EINVAL;
297
298 if (!umem)
299 return -EOPNOTSUPP;
300
301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
302}
303
e126ba97
EC		 304static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
305{
306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
307 struct ib_event event;
308
19098df2 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
310 /* This event is only valid for trans_qps */
311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
312 }
e126ba97
EC		 313
314 if (ibqp->event_handler) {
315 event.device = ibqp->device;
316 event.element.qp = ibqp;
317 switch (type) {
318 case MLX5_EVENT_TYPE_PATH_MIG:
319 event.event = IB_EVENT_PATH_MIG;
320 break;
321 case MLX5_EVENT_TYPE_COMM_EST:
322 event.event = IB_EVENT_COMM_EST;
323 break;
324 case MLX5_EVENT_TYPE_SQ_DRAINED:
325 event.event = IB_EVENT_SQ_DRAINED;
326 break;
327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
328 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
329 break;
330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
331 event.event = IB_EVENT_QP_FATAL;
332 break;
333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
334 event.event = IB_EVENT_PATH_MIG_ERR;
335 break;
336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
337 event.event = IB_EVENT_QP_REQ_ERR;
338 break;
339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
340 event.event = IB_EVENT_QP_ACCESS_ERR;
341 break;
342 default:
343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
344 return;
345 }
346
347 ibqp->event_handler(&event, ibqp->qp_context);
348 }
349}
350
351static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
353{
354 int wqe_size;
355 int wq_size;
356
357 /* Sanity check RQ size before proceeding */
938fe83c 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 359 return -EINVAL;
360
361 if (!has_rq) {
362 qp->rq.max_gs = 0;
363 qp->rq.wqe_cnt = 0;
364 qp->rq.wqe_shift = 0;
0540d814
NO		 365 cap->max_recv_wr = 0;
366 cap->max_recv_sge = 0;
e126ba97 367 } else {
c95e6d53
LR		 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
369
e126ba97
EC		 370 if (ucmd) {
371 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
002bf228
LR		 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
373 return -EINVAL;
e126ba97 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
c95e6d53
LR		 375 if ((1 << qp->rq.wqe_shift) /
376 sizeof(struct mlx5_wqe_data_seg) <
377 wq_sig)
002bf228 378 return -EINVAL;
c95e6d53
LR		 379 qp->rq.max_gs =
380 (1 << qp->rq.wqe_shift) /
381 sizeof(struct mlx5_wqe_data_seg) -
382 wq_sig;
e126ba97
EC		 383 qp->rq.max_post = qp->rq.wqe_cnt;
384 } else {
c95e6d53
LR		 385 wqe_size =
386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
387 0;
e126ba97
EC		 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
389 wqe_size = roundup_pow_of_two(wqe_size);
390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
392 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
395 wqe_size,
938fe83c
SM		 396 MLX5_CAP_GEN(dev->mdev,
397 max_wqe_sz_rq));
e126ba97
EC		 398 return -EINVAL;
399 }
400 qp->rq.wqe_shift = ilog2(wqe_size);
c95e6d53
LR		 401 qp->rq.max_gs =
402 (1 << qp->rq.wqe_shift) /
403 sizeof(struct mlx5_wqe_data_seg) -
404 wq_sig;
e126ba97
EC		 405 qp->rq.max_post = qp->rq.wqe_cnt;
406 }
407 }
408
409 return 0;
410}
411
f0313965 412static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 413{
618af384 414 int size = 0;
e126ba97 415
f0313965 416 switch (attr->qp_type) {
e126ba97 417 case IB_QPT_XRC_INI:
b125a54b 418 size += sizeof(struct mlx5_wqe_xrc_seg);
df561f66 419 fallthrough;
e126ba97
EC		 420 case IB_QPT_RC:
421 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 422 max(sizeof(struct mlx5_wqe_atomic_seg) +
423 sizeof(struct mlx5_wqe_raddr_seg),
424 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
064e5262
IB		 425 sizeof(struct mlx5_mkey_seg) +
426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
427 MLX5_IB_UMR_OCTOWORD);
e126ba97
EC		 428 break;
429
b125a54b
EC		 430 case IB_QPT_XRC_TGT:
431 return 0;
432
e126ba97 433 case IB_QPT_UC:
b125a54b 434 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 435 max(sizeof(struct mlx5_wqe_raddr_seg),
436 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
437 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 438 break;
439
440 case IB_QPT_UD:
f0313965
ES		 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
442 size += sizeof(struct mlx5_wqe_eth_pad) +
443 sizeof(struct mlx5_wqe_eth_seg);
df561f66 444 fallthrough;
e126ba97 445 case IB_QPT_SMI:
d16e91da 446 case MLX5_IB_QPT_HW_GSI:
b125a54b 447 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 448 sizeof(struct mlx5_wqe_datagram_seg);
449 break;
450
451 case MLX5_IB_QPT_REG_UMR:
b125a54b 452 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
454 sizeof(struct mlx5_mkey_seg);
455 break;
456
457 default:
458 return -EINVAL;
459 }
460
461 return size;
462}
463
464static int calc_send_wqe(struct ib_qp_init_attr *attr)
465{
466 int inl_size = 0;
467 int size;
468
f0313965 469 size = sq_overhead(attr);
e126ba97
EC		 470 if (size < 0)
471 return size;
472
473 if (attr->cap.max_inline_data) {
474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
475 attr->cap.max_inline_data;
476 }
477
478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
c0a6cbb9 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
e1e66cc2 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
c0a6cbb9 481 return MLX5_SIG_WQE_SIZE;
e1e66cc2
SG		 482 else
483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 484}
485
288c01b7
EC		 486static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
487{
488 int max_sge;
489
490 if (attr->qp_type == IB_QPT_RC)
491 max_sge = (min_t(int, wqe_size, 512) -
492 sizeof(struct mlx5_wqe_ctrl_seg) -
493 sizeof(struct mlx5_wqe_raddr_seg)) /
494 sizeof(struct mlx5_wqe_data_seg);
495 else if (attr->qp_type == IB_QPT_XRC_INI)
496 max_sge = (min_t(int, wqe_size, 512) -
497 sizeof(struct mlx5_wqe_ctrl_seg) -
498 sizeof(struct mlx5_wqe_xrc_seg) -
499 sizeof(struct mlx5_wqe_raddr_seg)) /
500 sizeof(struct mlx5_wqe_data_seg);
501 else
502 max_sge = (wqe_size - sq_overhead(attr)) /
503 sizeof(struct mlx5_wqe_data_seg);
504
505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
506 sizeof(struct mlx5_wqe_data_seg));
507}
508
e126ba97
EC		 509static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
510 struct mlx5_ib_qp *qp)
511{
512 int wqe_size;
513 int wq_size;
514
515 if (!attr->cap.max_send_wr)
516 return 0;
517
518 wqe_size = calc_send_wqe(attr);
519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
520 if (wqe_size < 0)
521 return wqe_size;
522
938fe83c 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 526 return -EINVAL;
527 }
528
f0313965
ES		 529 qp->max_inline_data = wqe_size - sq_overhead(attr) -
530 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 531 attr->cap.max_inline_data = qp->max_inline_data;
532
533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 538 qp->sq.wqe_cnt,
539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 540 return -ENOMEM;
541 }
e126ba97 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 543 qp->sq.max_gs = get_send_sge(attr, wqe_size);
544 if (qp->sq.max_gs < attr->cap.max_send_sge)
545 return -ENOMEM;
546
547 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 548 qp->sq.max_post = wq_size / wqe_size;
549 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 550
551 return wq_size;
552}
553
554static int set_user_buf_size(struct mlx5_ib_dev *dev,
555 struct mlx5_ib_qp *qp,
19098df2 556 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 557 struct mlx5_ib_qp_base *base,
558 struct ib_qp_init_attr *attr)
e126ba97
EC		 559{
560 int desc_sz = 1 << qp->sq.wqe_shift;
561
938fe83c 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 565 return -EINVAL;
566 }
567
af8b38ed
GP		 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
570 ucmd->sq_wqe_count);
e126ba97
EC		 571 return -EINVAL;
572 }
573
574 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
575
938fe83c 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 578 qp->sq.wqe_cnt,
579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 580 return -EINVAL;
581 }
582
c2e53b2c 583 if (attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0fb2ed66 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
587 } else {
588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
589 (qp->sq.wqe_cnt << 6);
590 }
e126ba97
EC		 591
592 return 0;
593}
594
595static int qp_has_rq(struct ib_qp_init_attr *attr)
596{
597 if (attr->qp_type == IB_QPT_XRC_INI ||
598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
599 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
600 !attr->cap.max_recv_wr)
601 return 0;
602
603 return 1;
604}
605
0b80c14f
EC		 606enum {
607 /* this is the first blue flame register in the array of bfregs assigned
608 * to a processes. Since we do not use it for blue flame but rather
609 * regular 64 bit doorbells, we do not need a lock for maintaiing
610 * "odd/even" order
611 */
612 NUM_NON_BLUE_FLAME_BFREGS = 1,
613};
614
b037c29a
EC		 615static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
616{
31a78a5a 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 618}
619
620static int num_med_bfreg(struct mlx5_ib_dev *dev,
621 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 622{
623 int n;
624
b037c29a
EC		 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
626 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 627
628 return n >= 0 ? n : 0;
629}
630
18b0362e
YH		 631static int first_med_bfreg(struct mlx5_ib_dev *dev,
632 struct mlx5_bfreg_info *bfregi)
633{
634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
635}
636
b037c29a
EC		 637static int first_hi_bfreg(struct mlx5_ib_dev *dev,
638 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 639{
640 int med;
c1be5232 641
b037c29a
EC		 642 med = num_med_bfreg(dev, bfregi);
643 return ++med;
c1be5232
EC		 644}
645
b037c29a
EC		 646static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
647 struct mlx5_bfreg_info *bfregi)
e126ba97 648{
e126ba97
EC		 649 int i;
650
b037c29a
EC		 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
652 if (!bfregi->count[i]) {
2f5ff264 653 bfregi->count[i]++;
e126ba97
EC		 654 return i;
655 }
656 }
657
658 return -ENOMEM;
659}
660
b037c29a
EC		 661static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
662 struct mlx5_bfreg_info *bfregi)
e126ba97 663{
18b0362e 664 int minidx = first_med_bfreg(dev, bfregi);
e126ba97
EC		 665 int i;
666
18b0362e
YH		 667 if (minidx < 0)
668 return minidx;
669
670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 671 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 672 minidx = i;
0b80c14f
EC		 673 if (!bfregi->count[minidx])
674 break;
e126ba97
EC		 675 }
676
2f5ff264 677 bfregi->count[minidx]++;
e126ba97
EC		 678 return minidx;
679}
680
b037c29a 681static int alloc_bfreg(struct mlx5_ib_dev *dev,
ffaf58de 682 struct mlx5_bfreg_info *bfregi)
e126ba97 683{
ffaf58de 684 int bfregn = -ENOMEM;
e126ba97 685
0a2fd01c
YH		 686 if (bfregi->lib_uar_dyn)
687 return -EINVAL;
688
2f5ff264 689 mutex_lock(&bfregi->lock);
ffaf58de
LR		 690 if (bfregi->ver >= 2) {
691 bfregn = alloc_high_class_bfreg(dev, bfregi);
692 if (bfregn < 0)
693 bfregn = alloc_med_class_bfreg(dev, bfregi);
694 }
695
696 if (bfregn < 0) {
0b80c14f 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 698 bfregn = 0;
699 bfregi->count[bfregn]++;
e126ba97 700 }
2f5ff264 701 mutex_unlock(&bfregi->lock);
e126ba97 702
2f5ff264 703 return bfregn;
e126ba97
EC		 704}
705
4ed131d0 706void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 707{
2f5ff264 708 mutex_lock(&bfregi->lock);
b037c29a 709 bfregi->count[bfregn]--;
2f5ff264 710 mutex_unlock(&bfregi->lock);
e126ba97
EC		 711}
712
713static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
714{
715 switch (state) {
716 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
723 default: return -1;
724 }
725}
726
727static int to_mlx5_st(enum ib_qp_type type)
728{
729 switch (type) {
730 case IB_QPT_RC: return MLX5_QP_ST_RC;
731 case IB_QPT_UC: return MLX5_QP_ST_UC;
732 case IB_QPT_UD: return MLX5_QP_ST_UD;
733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
734 case IB_QPT_XRC_INI:
735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
736 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
3ae7e66a 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 740 default: return -EINVAL;
741 }
742}
743
89ea94a7
MG		 744static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
745 struct mlx5_ib_cq *recv_cq);
746static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
747 struct mlx5_ib_cq *recv_cq);
748
7c043e90 749int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
05f58ceb 750 struct mlx5_bfreg_info *bfregi, u32 bfregn,
7c043e90 751 bool dyn_bfreg)
e126ba97 752{
05f58ceb
LR		 753 unsigned int bfregs_per_sys_page;
754 u32 index_of_sys_page;
755 u32 offset;
b037c29a 756
0a2fd01c
YH		 757 if (bfregi->lib_uar_dyn)
758 return -EINVAL;
759
b037c29a
EC		 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
761 MLX5_NON_FP_BFREGS_PER_UAR;
762 index_of_sys_page = bfregn / bfregs_per_sys_page;
763
1ee47ab3
YH		 764 if (dyn_bfreg) {
765 index_of_sys_page += bfregi->num_static_sys_pages;
05f58ceb
LR		 766
767 if (index_of_sys_page >= bfregi->num_sys_pages)
768 return -EINVAL;
769
1ee47ab3
YH		 770 if (bfregn > bfregi->num_dyn_bfregs ||
771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
773 return -EINVAL;
774 }
775 }
b037c29a 776
1ee47ab3 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 778 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 779}
780
b0ea0fa5 781static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
19098df2 782 unsigned long addr, size_t size,
f8fb3110 783 struct ib_umem **umem, int *page_shift,
7db0eea9 784 u32 *offset)
19098df2 785{
786 int err;
787
c320e527 788 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
19098df2 789 if (IS_ERR(*umem)) {
790 mlx5_ib_dbg(dev, "umem_get failed\n");
791 return PTR_ERR(*umem);
792 }
793
f8fb3110 794 mlx5_ib_cont_pages(*umem, addr, 0, page_shift);
19098df2 795
796 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
797 if (err) {
798 mlx5_ib_warn(dev, "bad offset\n");
799 goto err_umem;
800 }
801
f8fb3110
JG		 802 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %zu, page_shift %d, offset %d\n",
803 addr, size, ib_umem_num_pages(*umem), *page_shift, *offset);
19098df2 804
805 return 0;
806
807err_umem:
808 ib_umem_release(*umem);
809 *umem = NULL;
810
811 return err;
812}
813
fe248c3a 814static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
bdeacabd 815 struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
79b20a6c 816{
bdeacabd
SR		 817 struct mlx5_ib_ucontext *context =
818 rdma_udata_to_drv_context(
819 udata,
820 struct mlx5_ib_ucontext,
821 ibucontext);
79b20a6c 822
fe248c3a
MG		 823 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
824 atomic_dec(&dev->delay_drop.rqs_cnt);
825
79b20a6c 826 mlx5_ib_db_unmap_user(context, &rwq->db);
836a0fbb 827 ib_umem_release(rwq->umem);
79b20a6c
YH		 828}
829
830static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
b0ea0fa5 831 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
79b20a6c
YH		 832 struct mlx5_ib_create_wq *ucmd)
833{
89944450
SR		 834 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
835 udata, struct mlx5_ib_ucontext, ibucontext);
79b20a6c 836 int page_shift = 0;
79b20a6c 837 u32 offset = 0;
79b20a6c
YH		 838 int err;
839
840 if (!ucmd->buf_addr)
841 return -EINVAL;
842
c320e527 843 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
79b20a6c
YH		 844 if (IS_ERR(rwq->umem)) {
845 mlx5_ib_dbg(dev, "umem_get failed\n");
846 err = PTR_ERR(rwq->umem);
847 return err;
848 }
849
f8fb3110 850 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &page_shift);
79b20a6c
YH		 851 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
852 &rwq->rq_page_offset);
853 if (err) {
854 mlx5_ib_warn(dev, "bad offset\n");
855 goto err_umem;
856 }
857
7db0eea9 858 rwq->rq_num_pas = ib_umem_num_dma_blocks(rwq->umem, 1UL << page_shift);
79b20a6c
YH		 859 rwq->page_shift = page_shift;
860 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
861 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
862
f8fb3110
JG		 863 mlx5_ib_dbg(
864 dev,
865 "addr 0x%llx, size %zd, npages %zu, page_shift %d, ncont %d, offset %d\n",
866 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
867 ib_umem_num_pages(rwq->umem), page_shift, rwq->rq_num_pas,
868 offset);
79b20a6c 869
89944450 870 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
79b20a6c
YH		 871 if (err) {
872 mlx5_ib_dbg(dev, "map failed\n");
873 goto err_umem;
874 }
875
79b20a6c
YH		 876 return 0;
877
878err_umem:
879 ib_umem_release(rwq->umem);
880 return err;
881}
882
b037c29a
EC		 883static int adjust_bfregn(struct mlx5_ib_dev *dev,
884 struct mlx5_bfreg_info *bfregi, int bfregn)
885{
886 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
887 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
888}
889
98fc1126
LR		 890static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
891 struct mlx5_ib_qp *qp, struct ib_udata *udata,
892 struct ib_qp_init_attr *attr, u32 **in,
893 struct mlx5_ib_create_qp_resp *resp, int *inlen,
894 struct mlx5_ib_qp_base *base,
895 struct mlx5_ib_create_qp *ucmd)
e126ba97
EC		 896{
897 struct mlx5_ib_ucontext *context;
19098df2 898 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 899 int page_shift = 0;
1ee47ab3 900 int uar_index = 0;
9e9c47d0 901 u32 offset = 0;
2f5ff264 902 int bfregn;
9e9c47d0 903 int ncont = 0;
09a7d9ec
SM		 904 __be64 *pas;
905 void *qpc;
e126ba97 906 int err;
5aa3771d 907 u16 uid;
ac42a5ee 908 u32 uar_flags;
e126ba97 909
89944450
SR		 910 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
911 ibucontext);
76883a6c
LR		 912 uar_flags = qp->flags_en &
913 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
ac42a5ee
YH		 914 switch (uar_flags) {
915 case MLX5_QP_FLAG_UAR_PAGE_INDEX:
76883a6c 916 uar_index = ucmd->bfreg_index;
ac42a5ee
YH		 917 bfregn = MLX5_IB_INVALID_BFREG;
918 break;
919 case MLX5_QP_FLAG_BFREG_INDEX:
1ee47ab3 920 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
76883a6c 921 ucmd->bfreg_index, true);
1ee47ab3
YH		 922 if (uar_index < 0)
923 return uar_index;
1ee47ab3 924 bfregn = MLX5_IB_INVALID_BFREG;
ac42a5ee
YH		 925 break;
926 case 0:
2be08c30 927 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
ac42a5ee 928 return -EINVAL;
ffaf58de
LR		 929 bfregn = alloc_bfreg(dev, &context->bfregi);
930 if (bfregn < 0)
931 return bfregn;
ac42a5ee
YH		 932 break;
933 default:
934 return -EINVAL;
e126ba97
EC		 935 }
936
2f5ff264 937 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 938 if (bfregn != MLX5_IB_INVALID_BFREG)
939 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
940 false);
e126ba97 941
48fea837
HE		 942 qp->rq.offset = 0;
943 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
944 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
945
76883a6c 946 err = set_user_buf_size(dev, qp, ucmd, base, attr);
e126ba97 947 if (err)
2f5ff264 948 goto err_bfreg;
e126ba97 949
76883a6c
LR		 950 if (ucmd->buf_addr && ubuffer->buf_size) {
951 ubuffer->buf_addr = ucmd->buf_addr;
b0ea0fa5
JG		 952 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
953 ubuffer->buf_size, &ubuffer->umem,
f8fb3110 954 &page_shift, &offset);
19098df2 955 if (err)
2f5ff264 956 goto err_bfreg;
7db0eea9 957 ncont = ib_umem_num_dma_blocks(ubuffer->umem, 1UL << page_shift);
9e9c47d0 958 } else {
19098df2 959 ubuffer->umem = NULL;
e126ba97 960 }
e126ba97 961
09a7d9ec
SM		 962 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
963 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 964 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 965 if (!*in) {
966 err = -ENOMEM;
967 goto err_umem;
968 }
09a7d9ec 969
04bcc1c2 970 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
5aa3771d 971 MLX5_SET(create_qp_in, *in, uid, uid);
09a7d9ec 972 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 973 if (ubuffer->umem)
aab8d396 974 mlx5_ib_populate_pas(ubuffer->umem, 1UL << page_shift, pas, 0);
09a7d9ec
SM		 975
976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
977
978 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
979 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 980
09a7d9ec 981 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 982 if (bfregn != MLX5_IB_INVALID_BFREG)
983 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
984 else
985 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 986 qp->bfregn = bfregn;
e126ba97 987
76883a6c 988 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
e126ba97
EC		 989 if (err) {
990 mlx5_ib_dbg(dev, "map failed\n");
991 goto err_free;
992 }
993
e126ba97
EC		 994 return 0;
995
e126ba97 996err_free:
479163f4 997 kvfree(*in);
e126ba97
EC		 998
999err_umem:
836a0fbb 1000 ib_umem_release(ubuffer->umem);
e126ba97 1001
2f5ff264 1002err_bfreg:
1ee47ab3
YH		 1003 if (bfregn != MLX5_IB_INVALID_BFREG)
1004 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 1005 return err;
1006}
1007
747c519c
LR		 1008static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1009 struct mlx5_ib_qp_base *base, struct ib_udata *udata)
e126ba97 1010{
747c519c
LR		 1011 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1012 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 1013
747c519c
LR		 1014 if (udata) {
1015 /* User QP */
1016 mlx5_ib_db_unmap_user(context, &qp->db);
1017 ib_umem_release(base->ubuffer.umem);
1018
1019 /*
1020 * Free only the BFREGs which are handled by the kernel.
1021 * BFREGs of UARs allocated dynamically are handled by user.
1022 */
1023 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1024 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1025 return;
1026 }
1ee47ab3 1027
747c519c
LR		 1028 /* Kernel QP */
1029 kvfree(qp->sq.wqe_head);
1030 kvfree(qp->sq.w_list);
1031 kvfree(qp->sq.wrid);
1032 kvfree(qp->sq.wr_data);
1033 kvfree(qp->rq.wrid);
1034 if (qp->db.db)
1035 mlx5_db_free(dev->mdev, &qp->db);
1036 if (qp->buf.frags)
1037 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1038}
1039
98fc1126
LR		 1040static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1041 struct ib_qp_init_attr *init_attr,
1042 struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1043 struct mlx5_ib_qp_base *base)
e126ba97 1044{
e126ba97 1045 int uar_index;
09a7d9ec 1046 void *qpc;
e126ba97
EC		 1047 int err;
1048
e126ba97 1049 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0 1050 qp->bf.bfreg = &dev->fp_bfreg;
2978975c 1051 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
11f552e2 1052 qp->bf.bfreg = &dev->wc_bfreg;
5fe9dec0
EC		 1053 else
1054 qp->bf.bfreg = &dev->bfreg;
e126ba97 1055
d8030b0d
EC		 1056 /* We need to divide by two since each register is comprised of
1057 * two buffers of identical size, namely odd and even
1058 */
1059 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 1060 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 1061
1062 err = calc_sq_size(dev, init_attr, qp);
1063 if (err < 0) {
1064 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 1065 return err;
e126ba97
EC		 1066 }
1067
1068 qp->rq.offset = 0;
1069 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 1070 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 1071
34f4c955
GL		 1072 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1073 &qp->buf, dev->mdev->priv.numa_node);
e126ba97
EC		 1074 if (err) {
1075 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 1076 return err;
e126ba97
EC		 1077 }
1078
34f4c955
GL		 1079 if (qp->rq.wqe_cnt)
1080 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1081 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1082
1083 if (qp->sq.wqe_cnt) {
1084 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
1085 MLX5_SEND_WQE_BB;
1086 mlx5_init_fbc_offset(qp->buf.frags +
1087 (qp->sq.offset / PAGE_SIZE),
1088 ilog2(MLX5_SEND_WQE_BB),
1089 ilog2(qp->sq.wqe_cnt),
1090 sq_strides_offset, &qp->sq.fbc);
1091
1092 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1093 }
1094
09a7d9ec
SM		 1095 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1096 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 1097 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 1098 if (!*in) {
1099 err = -ENOMEM;
1100 goto err_buf;
1101 }
09a7d9ec
SM		 1102
1103 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1104 MLX5_SET(qpc, qpc, uar_page, uar_index);
1105 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1106
e126ba97 1107 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 1108 MLX5_SET(qpc, qpc, fre, 1);
1109 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 1110
2978975c 1111 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
09a7d9ec 1112 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c 1113
34f4c955
GL		 1114 mlx5_fill_page_frag_array(&qp->buf,
1115 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1116 *in, pas));
e126ba97 1117
9603b61d 1118 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 1119 if (err) {
1120 mlx5_ib_dbg(dev, "err %d\n", err);
1121 goto err_free;
1122 }
1123
b5883008
LD		 1124 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1125 sizeof(*qp->sq.wrid), GFP_KERNEL);
1126 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1127 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1128 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1129 sizeof(*qp->rq.wrid), GFP_KERNEL);
1130 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1131 sizeof(*qp->sq.w_list), GFP_KERNEL);
1132 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1133 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1134
1135 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1136 !qp->sq.w_list || !qp->sq.wqe_head) {
1137 err = -ENOMEM;
1138 goto err_wrid;
1139 }
e126ba97
EC		 1140
1141 return 0;
1142
1143err_wrid:
b5883008
LD		 1144 kvfree(qp->sq.wqe_head);
1145 kvfree(qp->sq.w_list);
1146 kvfree(qp->sq.wrid);
1147 kvfree(qp->sq.wr_data);
1148 kvfree(qp->rq.wrid);
f4044dac 1149 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1150
1151err_free:
479163f4 1152 kvfree(*in);
e126ba97
EC		 1153
1154err_buf:
34f4c955 1155 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1156 return err;
1157}
1158
09a7d9ec 1159static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97 1160{
7aede1a2
LR		 1161 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1162 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
09a7d9ec 1163 return MLX5_SRQ_RQ;
e126ba97 1164 else if (!qp->has_rq)
09a7d9ec 1165 return MLX5_ZERO_LEN_RQ;
7aede1a2
LR		 1166
1167 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1168}
1169
0fb2ed66 1170static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1171 struct mlx5_ib_qp *qp,
1cd6dbd3
YH		 1172 struct mlx5_ib_sq *sq, u32 tdn,
1173 struct ib_pd *pd)
0fb2ed66 1174{
e0b4b472 1175 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
0fb2ed66 1176 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1177
1cd6dbd3 1178 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1179 MLX5_SET(tisc, tisc, transport_domain, tdn);
2be08c30 1180 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
c2e53b2c
YH		 1181 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1182
e0b4b472 1183 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
0fb2ed66 1184}
1185
1186static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1cd6dbd3 1187 struct mlx5_ib_sq *sq, struct ib_pd *pd)
0fb2ed66 1188{
1cd6dbd3 1189 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
0fb2ed66 1190}
1191
d5ed8ac3 1192static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
b96c9dde
MB		 1193{
1194 if (sq->flow_rule)
1195 mlx5_del_flow_rules(sq->flow_rule);
d5ed8ac3 1196 sq->flow_rule = NULL;
b96c9dde
MB		 1197}
1198
0fb2ed66 1199static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
b0ea0fa5 1200 struct ib_udata *udata,
0fb2ed66 1201 struct mlx5_ib_sq *sq, void *qpin,
1202 struct ib_pd *pd)
1203{
1204 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1205 __be64 *pas;
1206 void *in;
1207 void *sqc;
1208 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1209 void *wq;
1210 int inlen;
1211 int err;
1212 int page_shift = 0;
0fb2ed66 1213 u32 offset = 0;
1214
b0ea0fa5 1215 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
f8fb3110 1216 &sq->ubuffer.umem, &page_shift, &offset);
0fb2ed66 1217 if (err)
1218 return err;
1219
7db0eea9
JG		 1220 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1221 sizeof(u64) * ib_umem_num_dma_blocks(sq->ubuffer.umem,
1222 1UL << page_shift);
1b9a07ee 1223 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1224 if (!in) {
1225 err = -ENOMEM;
1226 goto err_umem;
1227 }
1228
c14003f0 1229 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1230 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1231 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1232 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1233 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1234 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1235 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1236 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1237 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1238 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1239 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1240 MLX5_CAP_ETH(dev->mdev, swp))
1241 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1242
1243 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1244 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1245 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1246 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1247 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1248 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1249 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1250 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1251 MLX5_SET(wq, wq, page_offset, offset);
1252
1253 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
aab8d396 1254 mlx5_ib_populate_pas(sq->ubuffer.umem, 1UL << page_shift, pas, 0);
0fb2ed66 1255
333fbaa0 1256 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
0fb2ed66 1257
1258 kvfree(in);
1259
1260 if (err)
1261 goto err_umem;
1262
1263 return 0;
1264
1265err_umem:
1266 ib_umem_release(sq->ubuffer.umem);
1267 sq->ubuffer.umem = NULL;
1268
1269 return err;
1270}
1271
1272static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1273 struct mlx5_ib_sq *sq)
1274{
d5ed8ac3 1275 destroy_flow_rule_vport_sq(sq);
333fbaa0 1276 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
0fb2ed66 1277 ib_umem_release(sq->ubuffer.umem);
1278}
1279
2c292dbb 1280static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1281{
1282 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1283 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1284 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1285 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1286 u32 po_quanta = 1 << (log_page_size - 6);
1287 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1288 u32 page_size = 1 << log_page_size;
1289 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1290 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1291
1292 return rq_num_pas * sizeof(u64);
1293}
1294
1295static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb 1296 struct mlx5_ib_rq *rq, void *qpin,
34d57585 1297 size_t qpinlen, struct ib_pd *pd)
0fb2ed66 1298{
358e42ea 1299 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1300 __be64 *pas;
1301 __be64 *qp_pas;
1302 void *in;
1303 void *rqc;
1304 void *wq;
1305 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1306 size_t rq_pas_size = get_rq_pas_size(qpc);
1307 size_t inlen;
0fb2ed66 1308 int err;
2c292dbb
BP		 1309
1310 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1311 return -EINVAL;
0fb2ed66 1312
1313 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1314 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1315 if (!in)
1316 return -ENOMEM;
1317
34d57585 1318 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1319 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1320 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1321 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1322 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1323 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1324 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1325 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1326 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1327
2be08c30 1328 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
358e42ea
MD		 1329 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1330
0fb2ed66 1331 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1332 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1333 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1334 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1335 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1336 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1337 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1338 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1339 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1340 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1341
1342 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1343 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1344 memcpy(pas, qp_pas, rq_pas_size);
1345
333fbaa0 1346 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
0fb2ed66 1347
1348 kvfree(in);
1349
1350 return err;
1351}
1352
1353static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1354 struct mlx5_ib_rq *rq)
1355{
333fbaa0 1356 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
0fb2ed66 1357}
1358
0042f9e4
MB		 1359static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1360 struct mlx5_ib_rq *rq,
443c1cf9
YH		 1361 u32 qp_flags_en,
1362 struct ib_pd *pd)
0042f9e4
MB		 1363{
1364 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1365 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1366 mlx5_ib_disable_lb(dev, false, true);
443c1cf9 1367 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
0042f9e4
MB		 1368}
1369
0fb2ed66 1370static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb 1371 struct mlx5_ib_rq *rq, u32 tdn,
e0b4b472
LR		 1372 u32 *qp_flags_en, struct ib_pd *pd,
1373 u32 *out)
0fb2ed66 1374{
175edba8 1375 u8 lb_flag = 0;
0fb2ed66 1376 u32 *in;
1377 void *tirc;
1378 int inlen;
1379 int err;
1380
1381 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1382 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1383 if (!in)
1384 return -ENOMEM;
1385
443c1cf9 1386 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1387 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1388 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1389 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1390 MLX5_SET(tirc, tirc, transport_domain, tdn);
175edba8 1391 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb 1392 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1393
175edba8
MB		 1394 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1395 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1396
1397 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1398 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1399
6a4d00be 1400 if (dev->is_rep) {
175edba8
MB		 1401 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1402 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1403 }
1404
1405 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
e0b4b472
LR		 1406 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1407 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1f1d6abb 1408 rq->tirn = MLX5_GET(create_tir_out, out, tirn);
0042f9e4
MB		 1409 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1410 err = mlx5_ib_enable_lb(dev, false, true);
1411
1412 if (err)
443c1cf9 1413 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
0042f9e4 1414 }
0fb2ed66 1415 kvfree(in);
1416
1417 return err;
1418}
1419
0fb2ed66 1420static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1421 u32 *in, size_t inlen,
7f72052c
YH		 1422 struct ib_pd *pd,
1423 struct ib_udata *udata,
1424 struct mlx5_ib_create_qp_resp *resp)
0fb2ed66 1425{
1426 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1427 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1428 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
89944450
SR		 1429 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1430 udata, struct mlx5_ib_ucontext, ibucontext);
0fb2ed66 1431 int err;
1432 u32 tdn = mucontext->tdn;
7f72052c 1433 u16 uid = to_mpd(pd)->uid;
1f1d6abb 1434 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
0fb2ed66 1435
0eacc574
AL		 1436 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt)
1437 return -EINVAL;
0fb2ed66 1438 if (qp->sq.wqe_cnt) {
1cd6dbd3 1439 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
0fb2ed66 1440 if (err)
1441 return err;
1442
b0ea0fa5 1443 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
0fb2ed66 1444 if (err)
1445 goto err_destroy_tis;
1446
7f72052c
YH		 1447 if (uid) {
1448 resp->tisn = sq->tisn;
1449 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1450 resp->sqn = sq->base.mqp.qpn;
1451 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1452 }
1453
0fb2ed66 1454 sq->base.container_mibqp = qp;
1d31e9c0 1455 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1456 }
1457
1458 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1459 rq->base.container_mibqp = qp;
1460
2be08c30 1461 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
e4cc4fa7 1462 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
2be08c30 1463 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
b1383aa6 1464 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
34d57585 1465 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
0fb2ed66 1466 if (err)
1467 goto err_destroy_sq;
1468
e0b4b472
LR		 1469 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1470 out);
0fb2ed66 1471 if (err)
1472 goto err_destroy_rq;
7f72052c
YH		 1473
1474 if (uid) {
1475 resp->rqn = rq->base.mqp.qpn;
1476 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1477 resp->tirn = rq->tirn;
1478 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
54a38b66
AV		 1479 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
1480 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
1f1d6abb
AL		 1481 resp->tir_icm_addr = MLX5_GET(
1482 create_tir_out, out, icm_address_31_0);
1483 resp->tir_icm_addr |=
1484 (u64)MLX5_GET(create_tir_out, out,
1485 icm_address_39_32)
1486 << 32;
1487 resp->tir_icm_addr |=
1488 (u64)MLX5_GET(create_tir_out, out,
1489 icm_address_63_40)
1490 << 40;
1491 resp->comp_mask |=
1492 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1493 }
7f72052c 1494 }
0fb2ed66 1495 }
1496
1497 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1498 rq->base.mqp.qpn;
0fb2ed66 1499 return 0;
1500
1501err_destroy_rq:
1502 destroy_raw_packet_qp_rq(dev, rq);
1503err_destroy_sq:
1504 if (!qp->sq.wqe_cnt)
1505 return err;
1506 destroy_raw_packet_qp_sq(dev, sq);
1507err_destroy_tis:
1cd6dbd3 1508 destroy_raw_packet_qp_tis(dev, sq, pd);
0fb2ed66 1509
1510 return err;
1511}
1512
1513static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1514 struct mlx5_ib_qp *qp)
1515{
1516 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1517 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1518 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1519
1520 if (qp->rq.wqe_cnt) {
443c1cf9 1521 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
0fb2ed66 1522 destroy_raw_packet_qp_rq(dev, rq);
1523 }
1524
1525 if (qp->sq.wqe_cnt) {
1526 destroy_raw_packet_qp_sq(dev, sq);
1cd6dbd3 1527 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
0fb2ed66 1528 }
1529}
1530
1531static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1532 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1533{
1534 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1535 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1536
1537 sq->sq = &qp->sq;
1538 rq->rq = &qp->rq;
1539 sq->doorbell = &qp->db;
1540 rq->doorbell = &qp->db;
1541}
1542
28d61370
YH		 1543static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1544{
0042f9e4
MB		 1545 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1546 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1547 mlx5_ib_disable_lb(dev, false, true);
443c1cf9
YH		 1548 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1549 to_mpd(qp->ibqp.pd)->uid);
28d61370
YH		 1550}
1551
f78d358c
LR		 1552struct mlx5_create_qp_params {
1553 struct ib_udata *udata;
1554 size_t inlen;
6f2cf76e 1555 size_t outlen;
e383085c 1556 size_t ucmd_size;
f78d358c
LR		 1557 void *ucmd;
1558 u8 is_rss_raw : 1;
1559 struct ib_qp_init_attr *attr;
1560 u32 uidx;
08d53976 1561 struct mlx5_ib_create_qp_resp resp;
f78d358c
LR		 1562};
1563
1564static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1565 struct mlx5_ib_qp *qp,
1566 struct mlx5_create_qp_params *params)
28d61370 1567{
f78d358c
LR		 1568 struct ib_qp_init_attr *init_attr = params->attr;
1569 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd;
1570 struct ib_udata *udata = params->udata;
89944450
SR		 1571 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1572 udata, struct mlx5_ib_ucontext, ibucontext);
28d61370 1573 int inlen;
1f1d6abb 1574 int outlen;
28d61370
YH		 1575 int err;
1576 u32 *in;
1f1d6abb 1577 u32 *out;
28d61370
YH		 1578 void *tirc;
1579 void *hfso;
1580 u32 selected_fields = 0;
2d93fc85 1581 u32 outer_l4;
28d61370 1582 u32 tdn = mucontext->tdn;
175edba8 1583 u8 lb_flag = 0;
28d61370 1584
5ce0592b 1585 if (ucmd->comp_mask) {
28d61370
YH		 1586 mlx5_ib_dbg(dev, "invalid comp mask\n");
1587 return -EOPNOTSUPP;
1588 }
1589
5ce0592b
LR		 1590 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1591 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
309fa347
MG		 1592 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1593 return -EOPNOTSUPP;
1594 }
1595
37518fa4 1596 if (dev->is_rep)
175edba8 1597 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
175edba8 1598
37518fa4
LR		 1599 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1600 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1601
1602 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
175edba8 1603 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
175edba8 1604
28d61370 1605 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1f1d6abb
AL		 1606 outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1607 in = kvzalloc(inlen + outlen, GFP_KERNEL);
28d61370
YH		 1608 if (!in)
1609 return -ENOMEM;
1610
1f1d6abb 1611 out = in + MLX5_ST_SZ_DW(create_tir_in);
443c1cf9 1612 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
28d61370
YH		 1613 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1614 MLX5_SET(tirc, tirc, disp_type,
1615 MLX5_TIRC_DISP_TYPE_INDIRECT);
1616 MLX5_SET(tirc, tirc, indirect_table,
1617 init_attr->rwq_ind_tbl->ind_tbl_num);
1618 MLX5_SET(tirc, tirc, transport_domain, tdn);
1619
1620 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb 1621
5ce0592b 1622 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb
MG		 1623 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1624
175edba8
MB		 1625 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1626
5ce0592b 1627 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
309fa347
MG		 1628 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1629 else
1630 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1631
5ce0592b 1632 switch (ucmd->rx_hash_function) {
28d61370
YH		 1633 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1634 {
1635 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1636 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1637
5ce0592b 1638 if (len != ucmd->rx_key_len) {
28d61370
YH		 1639 err = -EINVAL;
1640 goto err;
1641 }
1642
1643 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
5ce0592b 1644 memcpy(rss_key, ucmd->rx_hash_key, len);
28d61370
YH		 1645 break;
1646 }
1647 default:
1648 err = -EOPNOTSUPP;
1649 goto err;
1650 }
1651
5ce0592b 1652 if (!ucmd->rx_hash_fields_mask) {
28d61370
YH		 1653 /* special case when this TIR serves as steering entry without hashing */
1654 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1655 goto create_tir;
1656 err = -EINVAL;
1657 goto err;
1658 }
1659
5ce0592b
LR		 1660 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1661 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1662 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1663 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
28d61370
YH		 1664 err = -EINVAL;
1665 goto err;
1666 }
1667
1668 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
5ce0592b
LR		 1669 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1670 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
28d61370
YH		 1671 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1672 MLX5_L3_PROT_TYPE_IPV4);
5ce0592b
LR		 1673 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1674 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
28d61370
YH		 1675 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1676 MLX5_L3_PROT_TYPE_IPV6);
1677
5ce0592b
LR		 1678 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1679 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1680 << 0 |
1681 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1682 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1683 << 1 |
1684 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
2d93fc85
MB		 1685
1686 /* Check that only one l4 protocol is set */
1687 if (outer_l4 & (outer_l4 - 1)) {
28d61370
YH		 1688 err = -EINVAL;
1689 goto err;
1690 }
1691
1692 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
5ce0592b
LR		 1693 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1694 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
28d61370
YH		 1695 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1696 MLX5_L4_PROT_TYPE_TCP);
5ce0592b
LR		 1697 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1698 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
28d61370
YH		 1699 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1700 MLX5_L4_PROT_TYPE_UDP);
1701
5ce0592b
LR		 1702 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1703 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
28d61370
YH		 1704 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1705
5ce0592b
LR		 1706 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1707 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
28d61370
YH		 1708 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1709
5ce0592b
LR		 1710 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1711 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
28d61370
YH		 1712 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1713
5ce0592b
LR		 1714 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1715 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
28d61370
YH		 1716 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1717
5ce0592b 1718 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
2d93fc85
MB		 1719 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1720
28d61370
YH		 1721 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1722
1723create_tir:
e0b4b472
LR		 1724 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1725 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
28d61370 1726
1f1d6abb 1727 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
0042f9e4
MB		 1728 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1729 err = mlx5_ib_enable_lb(dev, false, true);
1730
1731 if (err)
443c1cf9
YH		 1732 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1733 to_mpd(pd)->uid);
0042f9e4
MB		 1734 }
1735
28d61370
YH		 1736 if (err)
1737 goto err;
1738
7f72052c 1739 if (mucontext->devx_uid) {
08d53976
LR		 1740 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1741 params->resp.tirn = qp->rss_qp.tirn;
54a38b66
AV		 1742 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
1743 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
08d53976 1744 params->resp.tir_icm_addr =
1f1d6abb 1745 MLX5_GET(create_tir_out, out, icm_address_31_0);
08d53976
LR		 1746 params->resp.tir_icm_addr |=
1747 (u64)MLX5_GET(create_tir_out, out,
1748 icm_address_39_32)
1749 << 32;
1750 params->resp.tir_icm_addr |=
1751 (u64)MLX5_GET(create_tir_out, out,
1752 icm_address_63_40)
1753 << 40;
1754 params->resp.comp_mask |=
1f1d6abb
AL		 1755 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1756 }
7f72052c
YH		 1757 }
1758
28d61370
YH		 1759 kvfree(in);
1760 /* qpn is reserved for that QP */
1761 qp->trans_qp.base.mqp.qpn = 0;
2be08c30 1762 qp->is_rss = true;
28d61370
YH		 1763 return 0;
1764
1765err:
1766 kvfree(in);
1767 return err;
1768}
1769
5d6ff1ba 1770static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
81530ab0 1771 struct mlx5_ib_qp *qp,
5d6ff1ba
YC		 1772 struct ib_qp_init_attr *init_attr,
1773 void *qpc)
1774{
5d6ff1ba 1775 int scqe_sz;
2ab367a7 1776 bool allow_scat_cqe = false;
5d6ff1ba 1777
81530ab0 1778 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
6f4bc0ea
YC		 1779
1780 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
5d6ff1ba
YC		 1781 return;
1782
1783 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1784 if (scqe_sz == 128) {
1785 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1786 return;
1787 }
1788
1789 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1790 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1791 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1792}
1793
a60109dc
YC		 1794static int atomic_size_to_mode(int size_mask)
1795{
1796 /* driver does not support atomic_size > 256B
1797 * and does not know how to translate bigger sizes
1798 */
1799 int supported_size_mask = size_mask & 0x1ff;
1800 int log_max_size;
1801
1802 if (!supported_size_mask)
1803 return -EOPNOTSUPP;
1804
1805 log_max_size = __fls(supported_size_mask);
1806
1807 if (log_max_size > 3)
1808 return log_max_size;
1809
1810 return MLX5_ATOMIC_MODE_8B;
1811}
1812
1813static int get_atomic_mode(struct mlx5_ib_dev *dev,
1814 enum ib_qp_type qp_type)
1815{
1816 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1817 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1818 int atomic_mode = -EOPNOTSUPP;
1819 int atomic_size_mask;
1820
1821 if (!atomic)
1822 return -EOPNOTSUPP;
1823
1824 if (qp_type == MLX5_IB_QPT_DCT)
1825 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1826 else
1827 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1828
1829 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1830 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1831 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1832
1833 if (atomic_mode <= 0 &&
1834 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1835 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1836 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1837
1838 return atomic_mode;
1839}
1840
f78d358c
LR		 1841static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1842 struct mlx5_create_qp_params *params)
04bcc1c2 1843{
e383085c 1844 struct mlx5_ib_create_qp *ucmd = params->ucmd;
f78d358c 1845 struct ib_qp_init_attr *attr = params->attr;
f78d358c 1846 u32 uidx = params->uidx;
04bcc1c2 1847 struct mlx5_ib_resources *devr = &dev->devr;
3e09a427 1848 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
04bcc1c2
LR		 1849 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1850 struct mlx5_core_dev *mdev = dev->mdev;
1851 struct mlx5_ib_qp_base *base;
1852 unsigned long flags;
1853 void *qpc;
1854 u32 *in;
1855 int err;
1856
04bcc1c2
LR		 1857 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1858 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1859
1860 in = kvzalloc(inlen, GFP_KERNEL);
1861 if (!in)
1862 return -ENOMEM;
1863
6eefa839 1864 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd)
e383085c 1865 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
04bcc1c2
LR		 1866 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1867
1868 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1869 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1870 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1871
1872 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1873 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1874 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1875 MLX5_SET(qpc, qpc, cd_master, 1);
1876 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1877 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1878 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1879 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1880
1881 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1882 MLX5_SET(qpc, qpc, no_sq, 1);
1883 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1884 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1885 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1886 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1887 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1888
1889 /* 0xffffff means we ask to work with cqe version 0 */
1890 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1891 MLX5_SET(qpc, qpc, user_index, uidx);
1892
1893 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1894 MLX5_SET(qpc, qpc, end_padding_mode,
1895 MLX5_WQ_END_PAD_MODE_ALIGN);
1896 /* Special case to clean flag */
1897 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1898 }
1899
1900 base = &qp->trans_qp.base;
3e09a427 1901 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
04bcc1c2 1902 kvfree(in);
6367da46 1903 if (err)
04bcc1c2 1904 return err;
04bcc1c2
LR		 1905
1906 base->container_mibqp = qp;
1907 base->mqp.event = mlx5_ib_qp_event;
92cd667c
LR		 1908 if (MLX5_CAP_GEN(mdev, ece_support))
1909 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
04bcc1c2
LR		 1910
1911 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1912 list_add_tail(&qp->qps_list, &dev->qp_list);
1913 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1914
968f0b6f 1915 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn;
04bcc1c2
LR		 1916 return 0;
1917}
1918
98fc1126 1919static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
f78d358c
LR		 1920 struct mlx5_ib_qp *qp,
1921 struct mlx5_create_qp_params *params)
e126ba97 1922{
f78d358c
LR		 1923 struct ib_qp_init_attr *init_attr = params->attr;
1924 struct mlx5_ib_create_qp *ucmd = params->ucmd;
3e09a427 1925 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
f78d358c
LR		 1926 struct ib_udata *udata = params->udata;
1927 u32 uidx = params->uidx;
e126ba97 1928 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1929 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1930 struct mlx5_core_dev *mdev = dev->mdev;
89ea94a7
MG		 1931 struct mlx5_ib_cq *send_cq;
1932 struct mlx5_ib_cq *recv_cq;
1933 unsigned long flags;
09a7d9ec 1934 struct mlx5_ib_qp_base *base;
e7b169f3 1935 int mlx5_st;
cfb5e088 1936 void *qpc;
09a7d9ec
SM		 1937 u32 *in;
1938 int err;
e126ba97 1939
e126ba97
EC		 1940 spin_lock_init(&qp->sq.lock);
1941 spin_lock_init(&qp->rq.lock);
1942
7aede1a2 1943 mlx5_st = to_mlx5_st(qp->type);
e7b169f3
NO		 1944 if (mlx5_st < 0)
1945 return -EINVAL;
1946
e126ba97
EC		 1947 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1948 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1949
2978975c
LR		 1950 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1951 qp->underlay_qpn = init_attr->source_qpn;
1952
c2e53b2c 1953 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 1954 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
c2e53b2c
YH		 1955 &qp->raw_packet_qp.rq.base :
1956 &qp->trans_qp.base;
1957
e126ba97 1958 qp->has_rq = qp_has_rq(init_attr);
2dfac92d 1959 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
e126ba97
EC		 1960 if (err) {
1961 mlx5_ib_dbg(dev, "err %d\n", err);
1962 return err;
1963 }
1964
98fc1126
LR		 1965 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1966 ucmd->rq_wqe_count != qp->rq.wqe_cnt)
1967 return -EINVAL;
04bcc1c2 1968
98fc1126
LR		 1969 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1970 return -EINVAL;
e126ba97 1971
08d53976
LR		 1972 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, &params->resp,
1973 &inlen, base, ucmd);
04bcc1c2
LR		 1974 if (err)
1975 return err;
e126ba97
EC		 1976
1977 if (is_sqp(init_attr->qp_type))
1978 qp->port = init_attr->port_num;
1979
e383085c
LR		 1980 if (MLX5_CAP_GEN(mdev, ece_support))
1981 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
09a7d9ec
SM		 1982 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1983
e7b169f3 1984 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 1985 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
98fc1126 1986 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
e126ba97 1987
c95e6d53 1988 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
09a7d9ec 1989 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1990
2be08c30 1991 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1992 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1993
2be08c30 1994 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
09a7d9ec 1995 MLX5_SET(qpc, qpc, cd_master, 1);
2be08c30 1996 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
09a7d9ec 1997 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2be08c30 1998 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
09a7d9ec 1999 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2be08c30 2000 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
569c6651 2001 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
90ecb37a
LR		 2002 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2003 (init_attr->qp_type == IB_QPT_RC ||
2004 init_attr->qp_type == IB_QPT_UC)) {
52c81f47 2005 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
8bde2c50
LR		 2006
2007 MLX5_SET(qpc, qpc, cs_res,
2008 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2009 MLX5_RES_SCAT_DATA32_CQE);
2010 }
90ecb37a 2011 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
7aede1a2 2012 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
81530ab0 2013 configure_requester_scat_cqe(dev, qp, init_attr, qpc);
e126ba97
EC		 2014
2015 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 2016 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2017 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 2018 }
2019
09a7d9ec 2020 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 2021
3fd3307e 2022 if (qp->sq.wqe_cnt) {
09a7d9ec 2023 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 2024 } else {
09a7d9ec 2025 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 2026 if (init_attr->srq &&
2027 init_attr->srq->srq_type == IB_SRQT_TM)
2028 MLX5_SET(qpc, qpc, offload_type,
2029 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2030 }
e126ba97
EC		 2031
2032 /* Set default resources */
2033 switch (init_attr->qp_type) {
e126ba97 2034 case IB_QPT_XRC_INI:
09a7d9ec 2035 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
f4375443 2036 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
09a7d9ec 2037 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 2038 break;
2039 default:
2040 if (init_attr->srq) {
f4375443 2041 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
09a7d9ec 2042 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 2043 } else {
f4375443 2044 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
09a7d9ec 2045 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 2046 }
2047 }
2048
2049 if (init_attr->send_cq)
09a7d9ec 2050 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 2051
2052 if (init_attr->recv_cq)
09a7d9ec 2053 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 2054
09a7d9ec 2055 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 2056
09a7d9ec
SM		 2057 /* 0xffffff means we ask to work with cqe version 0 */
2058 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 2059 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 2060
2978975c
LR		 2061 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2062 init_attr->qp_type != IB_QPT_RAW_PACKET) {
2063 MLX5_SET(qpc, qpc, end_padding_mode,
2064 MLX5_WQ_END_PAD_MODE_ALIGN);
2065 /* Special case to clean flag */
2066 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
b1383aa6
NO		 2067 }
2068
c2e53b2c 2069 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 2070 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2dfac92d 2071 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
0fb2ed66 2072 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
7f72052c 2073 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
08d53976 2074 &params->resp);
04bcc1c2 2075 } else
3e09a427 2076 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
e126ba97 2077
479163f4 2078 kvfree(in);
04bcc1c2
LR		 2079 if (err)
2080 goto err_create;
e126ba97 2081
19098df2 2082 base->container_mibqp = qp;
2083 base->mqp.event = mlx5_ib_qp_event;
92cd667c
LR		 2084 if (MLX5_CAP_GEN(mdev, ece_support))
2085 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
e126ba97 2086
7aede1a2 2087 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
89ea94a7
MG		 2088 &send_cq, &recv_cq);
2089 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2090 mlx5_ib_lock_cqs(send_cq, recv_cq);
2091 /* Maintain device to QPs access, needed for further handling via reset
2092 * flow
2093 */
2094 list_add_tail(&qp->qps_list, &dev->qp_list);
2095 /* Maintain CQ to QPs access, needed for further handling via reset flow
2096 */
2097 if (send_cq)
2098 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2099 if (recv_cq)
2100 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2101 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2102 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2103
e126ba97
EC		 2104 return 0;
2105
2106err_create:
747c519c 2107 destroy_qp(dev, qp, base, udata);
e126ba97
EC		 2108 return err;
2109}
2110
98fc1126 2111static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
f78d358c
LR		 2112 struct mlx5_ib_qp *qp,
2113 struct mlx5_create_qp_params *params)
98fc1126 2114{
f78d358c
LR		 2115 struct ib_qp_init_attr *attr = params->attr;
2116 u32 uidx = params->uidx;
98fc1126 2117 struct mlx5_ib_resources *devr = &dev->devr;
3e09a427 2118 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
98fc1126
LR		 2119 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2120 struct mlx5_core_dev *mdev = dev->mdev;
2121 struct mlx5_ib_cq *send_cq;
2122 struct mlx5_ib_cq *recv_cq;
2123 unsigned long flags;
2124 struct mlx5_ib_qp_base *base;
2125 int mlx5_st;
2126 void *qpc;
2127 u32 *in;
2128 int err;
2129
98fc1126
LR		 2130 spin_lock_init(&qp->sq.lock);
2131 spin_lock_init(&qp->rq.lock);
2132
2133 mlx5_st = to_mlx5_st(qp->type);
2134 if (mlx5_st < 0)
2135 return -EINVAL;
2136
2137 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2138 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2139
2140 base = &qp->trans_qp.base;
2141
2142 qp->has_rq = qp_has_rq(attr);
2143 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2144 if (err) {
2145 mlx5_ib_dbg(dev, "err %d\n", err);
2146 return err;
2147 }
2148
2149 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2150 if (err)
2151 return err;
2152
2153 if (is_sqp(attr->qp_type))
2154 qp->port = attr->port_num;
2155
2156 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2157
2158 MLX5_SET(qpc, qpc, st, mlx5_st);
2159 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2160
2161 if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2162 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2163 else
2164 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2165
2166
2167 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2168 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2169
2170 if (qp->rq.wqe_cnt) {
2171 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2172 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2173 }
2174
2175 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2176
2177 if (qp->sq.wqe_cnt)
2178 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2179 else
2180 MLX5_SET(qpc, qpc, no_sq, 1);
2181
2182 if (attr->srq) {
f4375443 2183 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
98fc1126
LR		 2184 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2185 to_msrq(attr->srq)->msrq.srqn);
2186 } else {
f4375443 2187 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
98fc1126
LR		 2188 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2189 to_msrq(devr->s1)->msrq.srqn);
2190 }
2191
2192 if (attr->send_cq)
2193 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2194
2195 if (attr->recv_cq)
2196 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2197
2198 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2199
2200 /* 0xffffff means we ask to work with cqe version 0 */
2201 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2202 MLX5_SET(qpc, qpc, user_index, uidx);
2203
2204 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2205 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2206 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2207
3e09a427 2208 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
98fc1126
LR		 2209 kvfree(in);
2210 if (err)
2211 goto err_create;
2212
2213 base->container_mibqp = qp;
2214 base->mqp.event = mlx5_ib_qp_event;
2215
2216 get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2217 &send_cq, &recv_cq);
2218 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2219 mlx5_ib_lock_cqs(send_cq, recv_cq);
2220 /* Maintain device to QPs access, needed for further handling via reset
2221 * flow
2222 */
2223 list_add_tail(&qp->qps_list, &dev->qp_list);
2224 /* Maintain CQ to QPs access, needed for further handling via reset flow
2225 */
2226 if (send_cq)
2227 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2228 if (recv_cq)
2229 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2230 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2231 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2232
2233 return 0;
2234
2235err_create:
747c519c 2236 destroy_qp(dev, qp, base, NULL);
98fc1126
LR		 2237 return err;
2238}
2239
e126ba97
EC		 2240static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2241 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2242{
2243 if (send_cq) {
2244 if (recv_cq) {
2245 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 2246 spin_lock(&send_cq->lock);
e126ba97
EC		 2247 spin_lock_nested(&recv_cq->lock,
2248 SINGLE_DEPTH_NESTING);
2249 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 2250 spin_lock(&send_cq->lock);
e126ba97
EC		 2251 __acquire(&recv_cq->lock);
2252 } else {
89ea94a7 2253 spin_lock(&recv_cq->lock);
e126ba97
EC		 2254 spin_lock_nested(&send_cq->lock,
2255 SINGLE_DEPTH_NESTING);
2256 }
2257 } else {
89ea94a7 2258 spin_lock(&send_cq->lock);
6a4f139a 2259 __acquire(&recv_cq->lock);
e126ba97
EC		 2260 }
2261 } else if (recv_cq) {
89ea94a7 2262 spin_lock(&recv_cq->lock);
6a4f139a
EC		 2263 __acquire(&send_cq->lock);
2264 } else {
2265 __acquire(&send_cq->lock);
2266 __acquire(&recv_cq->lock);
e126ba97
EC		 2267 }
2268}
2269
2270static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2271 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2272{
2273 if (send_cq) {
2274 if (recv_cq) {
2275 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2276 spin_unlock(&recv_cq->lock);
89ea94a7 2277 spin_unlock(&send_cq->lock);
e126ba97
EC		 2278 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2279 __release(&recv_cq->lock);
89ea94a7 2280 spin_unlock(&send_cq->lock);
e126ba97
EC		 2281 } else {
2282 spin_unlock(&send_cq->lock);
89ea94a7 2283 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2284 }
2285 } else {
6a4f139a 2286 __release(&recv_cq->lock);
89ea94a7 2287 spin_unlock(&send_cq->lock);
e126ba97
EC		 2288 }
2289 } else if (recv_cq) {
6a4f139a 2290 __release(&send_cq->lock);
89ea94a7 2291 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2292 } else {
2293 __release(&recv_cq->lock);
2294 __release(&send_cq->lock);
e126ba97
EC		 2295 }
2296}
2297
89ea94a7
MG		 2298static void get_cqs(enum ib_qp_type qp_type,
2299 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2300 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2301{
89ea94a7 2302 switch (qp_type) {
e126ba97
EC		 2303 case IB_QPT_XRC_TGT:
2304 *send_cq = NULL;
2305 *recv_cq = NULL;
2306 break;
2307 case MLX5_IB_QPT_REG_UMR:
2308 case IB_QPT_XRC_INI:
89ea94a7 2309 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2310 *recv_cq = NULL;
2311 break;
2312
2313 case IB_QPT_SMI:
d16e91da 2314 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2315 case IB_QPT_RC:
2316 case IB_QPT_UC:
2317 case IB_QPT_UD:
0fb2ed66 2318 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2319 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2320 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97 2321 break;
e126ba97
EC		 2322 default:
2323 *send_cq = NULL;
2324 *recv_cq = NULL;
2325 break;
2326 }
2327}
2328
ad5f8e96 2329static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2330 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2331 u8 lag_tx_affinity);
ad5f8e96 2332
bdeacabd
SR		 2333static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2334 struct ib_udata *udata)
e126ba97
EC		 2335{
2336 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2337 struct mlx5_ib_qp_base *base;
89ea94a7 2338 unsigned long flags;
e126ba97
EC		 2339 int err;
2340
6c41965d 2341 if (qp->is_rss) {
28d61370
YH		 2342 destroy_rss_raw_qp_tir(dev, qp);
2343 return;
2344 }
2345
6c41965d 2346 base = (qp->type == IB_QPT_RAW_PACKET ||
2be08c30 2347 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
6c41965d
LR		 2348 &qp->raw_packet_qp.rq.base :
2349 &qp->trans_qp.base;
0fb2ed66 2350
6aec21f6 2351 if (qp->state != IB_QPS_RESET) {
6c41965d 2352 if (qp->type != IB_QPT_RAW_PACKET &&
2be08c30 2353 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
333fbaa0 2354 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
5f62a521 2355 NULL, &base->mqp, NULL);
ad5f8e96 2356 } else {
0680efa2
AV		 2357 struct mlx5_modify_raw_qp_param raw_qp_param = {
2358 .operation = MLX5_CMD_OP_2RST_QP
2359 };
2360
13eab21f 2361 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2362 }
2363 if (err)
427c1e7b 2364 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2365 base->mqp.qpn);
6aec21f6 2366 }
e126ba97 2367
6c41965d
LR		 2368 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq,
2369 &recv_cq);
89ea94a7
MG		 2370
2371 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2372 mlx5_ib_lock_cqs(send_cq, recv_cq);
2373 /* del from lists under both locks above to protect reset flow paths */
2374 list_del(&qp->qps_list);
2375 if (send_cq)
2376 list_del(&qp->cq_send_list);
2377
2378 if (recv_cq)
2379 list_del(&qp->cq_recv_list);
e126ba97 2380
03c4077b 2381 if (!udata) {
19098df2 2382 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2383 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2384 if (send_cq != recv_cq)
19098df2 2385 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2386 NULL);
e126ba97 2387 }
89ea94a7
MG		 2388 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2389 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2390
6c41965d 2391 if (qp->type == IB_QPT_RAW_PACKET ||
2be08c30 2392 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0fb2ed66 2393 destroy_raw_packet_qp(dev, qp);
2394 } else {
333fbaa0 2395 err = mlx5_core_destroy_qp(dev, &base->mqp);
0fb2ed66 2396 if (err)
2397 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2398 base->mqp.qpn);
2399 }
e126ba97 2400
747c519c 2401 destroy_qp(dev, qp, base, udata);
e126ba97
EC		 2402}
2403
a645a89d
LR		 2404static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2405 struct mlx5_ib_qp *qp,
f78d358c 2406 struct mlx5_create_qp_params *params)
b4aaa1f0 2407{
f78d358c
LR		 2408 struct ib_qp_init_attr *attr = params->attr;
2409 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2410 u32 uidx = params->uidx;
b4aaa1f0
MS		 2411 void *dctc;
2412
7c4b1ab9
MZ		 2413 if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct))
2414 return -EOPNOTSUPP;
2415
b4aaa1f0 2416 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
9c2ba4ed 2417 if (!qp->dct.in)
47c80612 2418 return -ENOMEM;
b4aaa1f0 2419
a01a5860 2420 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
b4aaa1f0 2421 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
b4aaa1f0
MS		 2422 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2423 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2424 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2425 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2426 MLX5_SET(dctc, dctc, user_index, uidx);
a645a89d
LR		 2427 if (MLX5_CAP_GEN(dev->mdev, ece_support))
2428 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
b4aaa1f0 2429
37518fa4 2430 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
fd9dab7e
LR		 2431 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2432
2433 if (rcqe_sz == 128)
2434 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2435 }
5d6ff1ba 2436
b4aaa1f0
MS		 2437 qp->state = IB_QPS_RESET;
2438
47c80612 2439 return 0;
b4aaa1f0
MS		 2440}
2441
7aede1a2
LR		 2442static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2443 enum ib_qp_type *type)
6eb7edff
LR		 2444{
2445 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2446 goto out;
2447
2448 switch (attr->qp_type) {
2449 case IB_QPT_XRC_TGT:
2450 case IB_QPT_XRC_INI:
2451 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2452 goto out;
2453 fallthrough;
6eb7edff
LR		 2454 case IB_QPT_RC:
2455 case IB_QPT_UC:
6eb7edff
LR		 2456 case IB_QPT_SMI:
2457 case MLX5_IB_QPT_HW_GSI:
6eb7edff
LR		 2458 case IB_QPT_DRIVER:
2459 case IB_QPT_GSI:
42caf9cb
MB		 2460 if (dev->profile == &raw_eth_profile)
2461 goto out;
2462 case IB_QPT_RAW_PACKET:
2463 case IB_QPT_UD:
2464 case MLX5_IB_QPT_REG_UMR:
7aede1a2 2465 break;
6eb7edff
LR		 2466 default:
2467 goto out;
b4aaa1f0
MS		 2468 }
2469
7aede1a2 2470 *type = attr->qp_type;
b4aaa1f0 2471 return 0;
6eb7edff
LR		 2472
2473out:
2474 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2475 return -EOPNOTSUPP;
b4aaa1f0
MS		 2476}
2477
2242cc25
LR		 2478static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2479 struct ib_qp_init_attr *attr,
2480 struct ib_udata *udata)
2481{
2482 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2483 udata, struct mlx5_ib_ucontext, ibucontext);
2484
2485 if (!udata) {
2486 /* Kernel create_qp callers */
2487 if (attr->rwq_ind_tbl)
2488 return -EOPNOTSUPP;
2489
2490 switch (attr->qp_type) {
2491 case IB_QPT_RAW_PACKET:
2492 case IB_QPT_DRIVER:
2493 return -EOPNOTSUPP;
2494 default:
2495 return 0;
2496 }
2497 }
2498
2499 /* Userspace create_qp callers */
2500 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2501 mlx5_ib_dbg(dev,
2502 "Raw Packet QP is only supported for CQE version > 0\n");
2503 return -EINVAL;
2504 }
2505
2506 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2507 mlx5_ib_dbg(dev,
2508 "Wrong QP type %d for the RWQ indirect table\n",
2509 attr->qp_type);
2510 return -EINVAL;
2511 }
2512
2242cc25
LR		 2513 /*
2514 * We don't need to see this warning, it means that kernel code
2515 * missing ib_pd. Placed here to catch developer's mistakes.
2516 */
2517 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2518 "There is a missing PD pointer assignment\n");
2519 return 0;
2520}
2521
37518fa4
LR		 2522static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2523 bool cond, struct mlx5_ib_qp *qp)
2524{
2525 if (!(*flags & flag))
2526 return;
2527
2528 if (cond) {
2529 qp->flags_en |= flag;
2530 *flags &= ~flag;
2531 return;
2532 }
2533
81530ab0
LR		 2534 switch (flag) {
2535 case MLX5_QP_FLAG_SCATTER_CQE:
2536 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE:
37518fa4 2537 /*
81530ab0
LR		 2538 * We don't return error if these flags were provided,
2539 * and mlx5 doesn't have right capability.
2540 */
2541 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE |
2542 MLX5_QP_FLAG_ALLOW_SCATTER_CQE);
37518fa4 2543 return;
81530ab0
LR		 2544 default:
2545 break;
37518fa4
LR		 2546 }
2547 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2548}
2549
2550static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5ce0592b 2551 void *ucmd, struct ib_qp_init_attr *attr)
2fdddbd5 2552{
37518fa4 2553 struct mlx5_core_dev *mdev = dev->mdev;
37518fa4 2554 bool cond;
5ce0592b
LR		 2555 int flags;
2556
2557 if (attr->rwq_ind_tbl)
2558 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2559 else
2560 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
37518fa4
LR		 2561
2562 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2fdddbd5 2563 case MLX5_QP_FLAG_TYPE_DCI:
7aede1a2 2564 qp->type = MLX5_IB_QPT_DCI;
2fdddbd5
LR		 2565 break;
2566 case MLX5_QP_FLAG_TYPE_DCT:
7aede1a2 2567 qp->type = MLX5_IB_QPT_DCT;
37518fa4 2568 break;
7aede1a2
LR		 2569 default:
2570 if (qp->type != IB_QPT_DRIVER)
2571 break;
2572 /*
2573 * It is IB_QPT_DRIVER and or no subtype or
2574 * wrong subtype were provided.
2575 */
2fdddbd5 2576 return -EINVAL;
7aede1a2 2577 }
37518fa4
LR		 2578
2579 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2580 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2581
2582 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2583 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2584 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
81530ab0
LR		 2585 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE,
2586 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
37518fa4 2587
7aede1a2 2588 if (qp->type == IB_QPT_RAW_PACKET) {
37518fa4
LR		 2589 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2590 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2591 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2592 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2593 cond, qp);
2594 process_vendor_flag(dev, &flags,
2595 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2596 qp);
2597 process_vendor_flag(dev, &flags,
2598 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2599 qp);
2fdddbd5
LR		 2600 }
2601
7aede1a2 2602 if (qp->type == IB_QPT_RC)
37518fa4
LR		 2603 process_vendor_flag(dev, &flags,
2604 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2605 MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2606
76883a6c
LR		 2607 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2608 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2609
5d6fffed
LR		 2610 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2611 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2612 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC);
2613 if (attr->rwq_ind_tbl && cond) {
2614 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n",
2615 cond);
2616 return -EINVAL;
2617 }
2618
37518fa4
LR		 2619 if (flags)
2620 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2621
2622 return (flags) ? -EINVAL : 0;
5d6fffed 2623 }
2fdddbd5 2624
2978975c
LR		 2625static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2626 bool cond, struct mlx5_ib_qp *qp)
2627{
2628 if (!(*flags & flag))
2629 return;
2630
2631 if (cond) {
2632 qp->flags |= flag;
2633 *flags &= ~flag;
2634 return;
2635 }
2636
2637 if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2638 /*
2639 * Special case, if condition didn't meet, it won't be error,
2640 * just different in-kernel flow.
2641 */
2642 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2643 return;
2644 }
2645 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2646}
2647
2648static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2649 struct ib_qp_init_attr *attr)
2650{
7aede1a2 2651 enum ib_qp_type qp_type = qp->type;
2978975c
LR		 2652 struct mlx5_core_dev *mdev = dev->mdev;
2653 int create_flags = attr->create_flags;
2654 bool cond;
2655
42caf9cb
MB		 2656 if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile)
2657 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST)
2658 return -EINVAL;
2659
7aede1a2 2660 if (qp_type == MLX5_IB_QPT_DCT)
2978975c
LR		 2661 return (create_flags) ? -EINVAL : 0;
2662
2663 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2664 return (create_flags) ? -EINVAL : 0;
2665
f81b4565
LR		 2666 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP,
2667 mlx5_get_flow_namespace(dev->mdev,
2668 MLX5_FLOW_NAMESPACE_BYPASS),
2669 qp);
9e0dc7b9
MG		 2670 process_create_flag(dev, &create_flags,
2671 IB_QP_CREATE_INTEGRITY_EN,
2672 MLX5_CAP_GEN(mdev, sho), qp);
2978975c
LR		 2673 process_create_flag(dev, &create_flags,
2674 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2675 MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2676 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2677 MLX5_CAP_GEN(mdev, cd), qp);
2678 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2679 MLX5_CAP_GEN(mdev, cd), qp);
2680 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2681 MLX5_CAP_GEN(mdev, cd), qp);
2682
2683 if (qp_type == IB_QPT_UD) {
2684 process_create_flag(dev, &create_flags,
2685 IB_QP_CREATE_IPOIB_UD_LSO,
2686 MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2687 qp);
2688 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2689 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2690 cond, qp);
2691 }
2692
2693 if (qp_type == IB_QPT_RAW_PACKET) {
2694 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2695 MLX5_CAP_ETH(mdev, scatter_fcs);
2696 process_create_flag(dev, &create_flags,
2697 IB_QP_CREATE_SCATTER_FCS, cond, qp);
2698
2699 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2700 MLX5_CAP_ETH(mdev, vlan_cap);
2701 process_create_flag(dev, &create_flags,
2702 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2703 }
2704
2705 process_create_flag(dev, &create_flags,
2706 IB_QP_CREATE_PCI_WRITE_END_PADDING,
2707 MLX5_CAP_GEN(mdev, end_pad), qp);
2708
2709 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2710 qp_type != MLX5_IB_QPT_REG_UMR, qp);
2711 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2712 true, qp);
2713
1f11a761 2714 if (create_flags) {
2978975c
LR		 2715 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2716 create_flags);
1f11a761
JG		 2717 return -EOPNOTSUPP;
2718 }
2719 return 0;
2978975c
LR		 2720}
2721
6f2cf76e
LR		 2722static int process_udata_size(struct mlx5_ib_dev *dev,
2723 struct mlx5_create_qp_params *params)
2fdddbd5
LR		 2724{
2725 size_t ucmd = sizeof(struct mlx5_ib_create_qp);
6f2cf76e
LR		 2726 struct ib_udata *udata = params->udata;
2727 size_t outlen = udata->outlen;
5ce0592b 2728 size_t inlen = udata->inlen;
2fdddbd5 2729
6f2cf76e 2730 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp));
e383085c 2731 params->ucmd_size = ucmd;
6f2cf76e 2732 if (!params->is_rss_raw) {
e383085c
LR		 2733 /* User has old rdma-core, which doesn't support ECE */
2734 size_t min_inlen =
2735 offsetof(struct mlx5_ib_create_qp, ece_options);
2736
2737 /*
2738 * We will check in check_ucmd_data() that user
2739 * cleared everything after inlen.
2740 */
2741 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd);
6f2cf76e
LR		 2742 goto out;
2743 }
5ce0592b 2744
6f2cf76e 2745 /* RSS RAW QP */
5ce0592b 2746 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
6f2cf76e
LR		 2747 return -EINVAL;
2748
2749 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index))
2750 return -EINVAL;
5ce0592b
LR		 2751
2752 ucmd = sizeof(struct mlx5_ib_create_qp_rss);
e383085c 2753 params->ucmd_size = ucmd;
5ce0592b 2754 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
6f2cf76e
LR		 2755 return -EINVAL;
2756
2757 params->inlen = min(ucmd, inlen);
2758out:
2759 if (!params->inlen)
e383085c 2760 mlx5_ib_dbg(dev, "udata is too small\n");
2dfac92d 2761
6f2cf76e 2762 return (params->inlen) ? 0 : -EINVAL;
2fdddbd5
LR		 2763}
2764
968f0b6f
LR		 2765static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2766 struct mlx5_ib_qp *qp,
2767 struct mlx5_create_qp_params *params)
5d0dc3d9 2768{
968f0b6f
LR		 2769 int err;
2770
2771 if (params->is_rss_raw) {
2772 err = create_rss_raw_qp_tir(dev, pd, qp, params);
2773 goto out;
2774 }
2775
2dc4d672
LR		 2776 switch (qp->type) {
2777 case MLX5_IB_QPT_DCT:
a645a89d 2778 err = create_dct(dev, pd, qp, params);
2dc4d672
LR		 2779 break;
2780 case IB_QPT_XRC_TGT:
968f0b6f 2781 err = create_xrc_tgt_qp(dev, qp, params);
2dc4d672
LR		 2782 break;
2783 case IB_QPT_GSI:
2784 err = mlx5_ib_create_gsi(pd, qp, params->attr);
2785 break;
2786 default:
2787 if (params->udata)
2788 err = create_user_qp(dev, pd, qp, params);
2789 else
2790 err = create_kernel_qp(dev, pd, qp, params);
968f0b6f 2791 }
5d0dc3d9 2792
968f0b6f
LR		 2793out:
2794 if (err) {
2795 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type);
2796 return err;
2797 }
2798
2799 if (is_qp0(qp->type))
2800 qp->ibqp.qp_num = 0;
2801 else if (is_qp1(qp->type))
2802 qp->ibqp.qp_num = 1;
2803 else
2804 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2805
2806 mlx5_ib_dbg(dev,
3e09a427 2807 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n",
968f0b6f
LR		 2808 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2809 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn :
2810 -1,
2811 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn :
3e09a427
LR		 2812 -1,
2813 params->resp.ece_options);
968f0b6f
LR		 2814
2815 return 0;
5d0dc3d9
LR		 2816}
2817
7aede1a2
LR		 2818static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2819 struct ib_qp_init_attr *attr)
2820{
2821 int ret = 0;
2822
2823 switch (qp->type) {
2824 case MLX5_IB_QPT_DCT:
2825 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2826 break;
2827 case MLX5_IB_QPT_DCI:
2828 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2829 -EINVAL :
2830 0;
2831 break;
266424eb
LR		 2832 case IB_QPT_RAW_PACKET:
2833 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2834 break;
7aede1a2
LR		 2835 default:
2836 break;
2837 }
2838
2839 if (ret)
2840 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2841
2842 return ret;
2843}
2844
f78d358c
LR		 2845static int get_qp_uidx(struct mlx5_ib_qp *qp,
2846 struct mlx5_create_qp_params *params)
21aad80b 2847{
f78d358c
LR		 2848 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2849 struct ib_udata *udata = params->udata;
21aad80b
LR		 2850 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2851 udata, struct mlx5_ib_ucontext, ibucontext);
2852
f78d358c 2853 if (params->is_rss_raw)
21aad80b
LR		 2854 return 0;
2855
f78d358c 2856 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &params->uidx);
21aad80b
LR		 2857}
2858
08d53976
LR		 2859static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2860{
2861 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2862
2863 if (mqp->state == IB_QPS_RTR) {
2864 int err;
2865
2866 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2867 if (err) {
2868 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2869 return err;
2870 }
2871 }
2872
2873 kfree(mqp->dct.in);
2874 kfree(mqp);
2875 return 0;
2876}
2877
e383085c
LR		 2878static int check_ucmd_data(struct mlx5_ib_dev *dev,
2879 struct mlx5_create_qp_params *params)
2880{
e383085c
LR		 2881 struct ib_udata *udata = params->udata;
2882 size_t size, last;
2883 int ret;
2884
2885 if (params->is_rss_raw)
2886 /*
2887 * These QPs don't have "reserved" field in their
2888 * create_qp input struct, so their data is always valid.
2889 */
2890 last = sizeof(struct mlx5_ib_create_qp_rss);
2891 else
2c0f5292 2892 last = offsetof(struct mlx5_ib_create_qp, reserved);
e383085c
LR		 2893
2894 if (udata->inlen <= last)
2895 return 0;
2896
2897 /*
2898 * User provides different create_qp structures based on the
2899 * flow and we need to know if he cleared memory after our
2900 * struct create_qp ends.
2901 */
2902 size = udata->inlen - last;
2903 ret = ib_is_udata_cleared(params->udata, last, size);
2904 if (!ret)
2905 mlx5_ib_dbg(
2906 dev,
4f5747cf 2907 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n",
e383085c
LR		 2908 udata->inlen, params->ucmd_size, last, size);
2909 return ret ? 0 : -EINVAL;
2910}
2911
f78d358c 2912struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr,
e126ba97
EC		 2913 struct ib_udata *udata)
2914{
f78d358c 2915 struct mlx5_create_qp_params params = {};
e126ba97
EC		 2916 struct mlx5_ib_dev *dev;
2917 struct mlx5_ib_qp *qp;
7aede1a2 2918 enum ib_qp_type type;
e126ba97
EC		 2919 int err;
2920
6eb7edff 2921 dev = pd ? to_mdev(pd->device) :
f78d358c 2922 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device);
0fb2ed66 2923
f78d358c
LR		 2924 err = check_qp_type(dev, attr, &type);
2925 if (err)
6eb7edff 2926 return ERR_PTR(err);
6eb7edff 2927
f78d358c 2928 err = check_valid_flow(dev, pd, attr, udata);
2242cc25
LR		 2929 if (err)
2930 return ERR_PTR(err);
e126ba97 2931
f78d358c
LR		 2932 params.udata = udata;
2933 params.uidx = MLX5_IB_DEFAULT_UIDX;
2934 params.attr = attr;
2935 params.is_rss_raw = !!attr->rwq_ind_tbl;
2fdddbd5 2936
f78d358c 2937 if (udata) {
6f2cf76e
LR		 2938 err = process_udata_size(dev, &params);
2939 if (err)
2940 return ERR_PTR(err);
2fdddbd5 2941
e383085c
LR		 2942 err = check_ucmd_data(dev, &params);
2943 if (err)
2944 return ERR_PTR(err);
2945
2946 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL);
f78d358c 2947 if (!params.ucmd)
5ce0592b
LR		 2948 return ERR_PTR(-ENOMEM);
2949
f78d358c 2950 err = ib_copy_from_udata(params.ucmd, udata, params.inlen);
2fdddbd5 2951 if (err)
5ce0592b 2952 goto free_ucmd;
2fdddbd5
LR		 2953 }
2954
9c2ba4ed 2955 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
5ce0592b
LR		 2956 if (!qp) {
2957 err = -ENOMEM;
2958 goto free_ucmd;
2959 }
9c2ba4ed 2960
7fa84b57 2961 mutex_init(&qp->mutex);
7aede1a2 2962 qp->type = type;
37518fa4 2963 if (udata) {
f78d358c 2964 err = process_vendor_flags(dev, qp, params.ucmd, attr);
b4aaa1f0 2965 if (err)
9c2ba4ed 2966 goto free_qp;
21aad80b 2967
f78d358c 2968 err = get_qp_uidx(qp, &params);
21aad80b
LR		 2969 if (err)
2970 goto free_qp;
b4aaa1f0 2971 }
f78d358c 2972 err = process_create_flags(dev, qp, attr);
2978975c
LR		 2973 if (err)
2974 goto free_qp;
b4aaa1f0 2975
f78d358c 2976 err = check_qp_attr(dev, qp, attr);
7aede1a2
LR		 2977 if (err)
2978 goto free_qp;
2979
968f0b6f
LR		 2980 err = create_qp(dev, pd, qp, &params);
2981 if (err)
9c2ba4ed 2982 goto free_qp;
e126ba97 2983
f78d358c 2984 kfree(params.ucmd);
08d53976 2985 params.ucmd = NULL;
5ce0592b 2986
08d53976
LR		 2987 if (udata)
2988 /*
2989 * It is safe to copy response for all user create QP flows,
2990 * including MLX5_IB_QPT_DCT, which doesn't need it.
2991 * In that case, resp will be filled with zeros.
2992 */
2993 err = ib_copy_to_udata(udata, &params.resp, params.outlen);
2994 if (err)
2995 goto destroy_qp;
2996
e126ba97 2997 return &qp->ibqp;
9c2ba4ed 2998
08d53976 2999destroy_qp:
2dc4d672
LR		 3000 switch (qp->type) {
3001 case MLX5_IB_QPT_DCT:
08d53976 3002 mlx5_ib_destroy_dct(qp);
2dc4d672
LR		 3003 break;
3004 case IB_QPT_GSI:
3005 mlx5_ib_destroy_gsi(qp);
3006 break;
3007 default:
6c41965d 3008 /*
0a037150 3009 * These lines below are temp solution till QP allocation
6c41965d
LR		 3010 * will be moved to be under IB/core responsiblity.
3011 */
3012 qp->ibqp.send_cq = attr->send_cq;
3013 qp->ibqp.recv_cq = attr->recv_cq;
0a037150 3014 qp->ibqp.pd = pd;
08d53976 3015 destroy_qp_common(dev, qp, udata);
6c41965d
LR		 3016 }
3017
08d53976 3018 qp = NULL;
9c2ba4ed
LR		 3019free_qp:
3020 kfree(qp);
5ce0592b 3021free_ucmd:
f78d358c 3022 kfree(params.ucmd);
9c2ba4ed 3023 return ERR_PTR(err);
e126ba97
EC		 3024}
3025
c4367a26 3026int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
e126ba97
EC		 3027{
3028 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3029 struct mlx5_ib_qp *mqp = to_mqp(qp);
3030
d16e91da 3031 if (unlikely(qp->qp_type == IB_QPT_GSI))
0d9aef86 3032 return mlx5_ib_destroy_gsi(mqp);
d16e91da 3033
7aede1a2 3034 if (mqp->type == MLX5_IB_QPT_DCT)
776a3906
MS		 3035 return mlx5_ib_destroy_dct(mqp);
3036
bdeacabd 3037 destroy_qp_common(dev, mqp, udata);
e126ba97
EC		 3038
3039 kfree(mqp);
3040
3041 return 0;
3042}
3043
f18e26af
LR		 3044static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
3045 const struct ib_qp_attr *attr, int attr_mask,
3046 void *qpc)
e126ba97 3047{
a60109dc 3048 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
f18e26af
LR		 3049 u8 dest_rd_atomic;
3050 u32 access_flags;
a60109dc 3051
e126ba97
EC		 3052 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3053 dest_rd_atomic = attr->max_dest_rd_atomic;
3054 else
19098df2 3055 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 3056
3057 if (attr_mask & IB_QP_ACCESS_FLAGS)
3058 access_flags = attr->qp_access_flags;
3059 else
19098df2 3060 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 3061
3062 if (!dest_rd_atomic)
3063 access_flags &= IB_ACCESS_REMOTE_WRITE;
3064
f18e26af
LR		 3065 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
3066
13f8d9c1 3067 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 3068 int atomic_mode;
3069
3070 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3071 if (atomic_mode < 0)
3072 return -EOPNOTSUPP;
3073
f18e26af
LR		 3074 MLX5_SET(qpc, qpc, rae, 1);
3075 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
a60109dc
YC		 3076 }
3077
f18e26af 3078 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
a60109dc 3079 return 0;
e126ba97
EC		 3080}
3081
3082enum {
3083 MLX5_PATH_FLAG_FL = 1 << 0,
3084 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
3085 MLX5_PATH_FLAG_COUNTER = 1 << 2,
3086};
3087
c531024b
MZ		 3088static int ib_to_mlx5_rate_map(u8 rate)
3089{
3090 switch (rate) {
3091 case IB_RATE_PORT_CURRENT:
3092 return 0;
3093 case IB_RATE_56_GBPS:
3094 return 1;
3095 case IB_RATE_25_GBPS:
3096 return 2;
3097 case IB_RATE_100_GBPS:
3098 return 3;
3099 case IB_RATE_200_GBPS:
3100 return 4;
3101 case IB_RATE_50_GBPS:
3102 return 5;
3103 default:
3104 return rate + MLX5_STAT_RATE_OFFSET;
3105 };
3106
3107 return 0;
3108}
3109
e126ba97
EC		 3110static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3111{
c531024b
MZ		 3112 u32 stat_rate_support;
3113
4f32ac2e 3114 if (rate == IB_RATE_PORT_CURRENT)
e126ba97 3115 return 0;
4f32ac2e 3116
a5a5d199 3117 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
e126ba97 3118 return -EINVAL;
e126ba97 3119
c531024b 3120 stat_rate_support = MLX5_CAP_GEN(dev->mdev, stat_rate_support);
4f32ac2e 3121 while (rate != IB_RATE_PORT_CURRENT &&
c531024b 3122 !(1 << ib_to_mlx5_rate_map(rate) & stat_rate_support))
4f32ac2e
DG		 3123 --rate;
3124
c531024b 3125 return ib_to_mlx5_rate_map(rate);
e126ba97
EC		 3126}
3127
75850d0b 3128static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 3129 struct mlx5_ib_sq *sq, u8 sl,
3130 struct ib_pd *pd)
75850d0b 3131{
3132 void *in;
3133 void *tisc;
3134 int inlen;
3135 int err;
3136
3137 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 3138 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 3139 if (!in)
3140 return -ENOMEM;
3141
3142 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1cd6dbd3 3143 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
75850d0b 3144
3145 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3146 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3147
e0b4b472 3148 err = mlx5_core_modify_tis(dev, sq->tisn, in);
75850d0b 3149
3150 kvfree(in);
3151
3152 return err;
3153}
3154
13eab21f 3155static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 3156 struct mlx5_ib_sq *sq, u8 tx_affinity,
3157 struct ib_pd *pd)
13eab21f
AH		 3158{
3159 void *in;
3160 void *tisc;
3161 int inlen;
3162 int err;
3163
3164 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 3165 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 3166 if (!in)
3167 return -ENOMEM;
3168
3169 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
1cd6dbd3 3170 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
13eab21f
AH		 3171
3172 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3173 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3174
e0b4b472 3175 err = mlx5_core_modify_tis(dev, sq->tisn, in);
13eab21f
AH		 3176
3177 kvfree(in);
3178
3179 return err;
3180}
3181
f18e26af 3182static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
2b880b2e
MZ		 3183 u32 lqpn, u32 rqpn)
3184
3185{
3186 u32 fl = ah->grh.flow_label;
2b880b2e
MZ		 3187
3188 if (!fl)
3189 fl = rdma_calc_flow_label(lqpn, rqpn);
3190
f18e26af 3191 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
2b880b2e
MZ		 3192}
3193
75850d0b 3194static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
f18e26af
LR		 3195 const struct rdma_ah_attr *ah, void *path, u8 port,
3196 int attr_mask, u32 path_flags,
3197 const struct ib_qp_attr *attr, bool alt)
e126ba97 3198{
d8966fcd 3199 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 3200 int err;
ed88451e 3201 enum ib_gid_type gid_type;
d8966fcd
DC		 3202 u8 ah_flags = rdma_ah_get_ah_flags(ah);
3203 u8 sl = rdma_ah_get_sl(ah);
e126ba97 3204
e126ba97 3205 if (attr_mask & IB_QP_PKEY_INDEX)
f18e26af
LR		 3206 MLX5_SET(ads, path, pkey_index,
3207 alt ? attr->alt_pkey_index : attr->pkey_index);
e126ba97 3208
d8966fcd
DC		 3209 if (ah_flags & IB_AH_GRH) {
3210 if (grh->sgid_index >=
938fe83c 3211 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 3212 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 3213 grh->sgid_index,
938fe83c 3214 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 3215 return -EINVAL;
3216 }
2811ba51 3217 }
44c58487
DC		 3218
3219 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 3220 if (!(ah_flags & IB_AH_GRH))
2811ba51 3221 return -EINVAL;
47ec3866 3222
f18e26af
LR		 3223 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
3224 ah->roce.dmac);
2b880b2e
MZ		 3225 if ((qp->ibqp.qp_type == IB_QPT_RC ||
3226 qp->ibqp.qp_type == IB_QPT_UC ||
3227 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3228 qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
3229 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) &&
3230 (attr_mask & IB_QP_DEST_QPN))
3231 mlx5_set_path_udp_sport(path, ah,
3232 qp->ibqp.qp_num,
3233 attr->dest_qp_num);
f18e26af 3234 MLX5_SET(ads, path, eth_prio, sl & 0x7);
47ec3866 3235 gid_type = ah->grh.sgid_attr->gid_type;
ed88451e 3236 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
f18e26af 3237 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
2811ba51 3238 } else {
f18e26af
LR		 3239 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
3240 MLX5_SET(ads, path, free_ar,
3241 !!(path_flags & MLX5_PATH_FLAG_FREE_AR));
3242 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
3243 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
3244 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
3245 MLX5_SET(ads, path, sl, sl);
2811ba51
AS		 3246 }
3247
d8966fcd 3248 if (ah_flags & IB_AH_GRH) {
f18e26af
LR		 3249 MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
3250 MLX5_SET(ads, path, hop_limit, grh->hop_limit);
3251 MLX5_SET(ads, path, tclass, grh->traffic_class);
3252 MLX5_SET(ads, path, flow_label, grh->flow_label);
3253 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
3254 sizeof(grh->dgid.raw));
e126ba97
EC		 3255 }
3256
d8966fcd 3257 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 3258 if (err < 0)
3259 return err;
f18e26af
LR		 3260 MLX5_SET(ads, path, stat_rate, err);
3261 MLX5_SET(ads, path, vhca_port_num, port);
e126ba97 3262
e126ba97 3263 if (attr_mask & IB_QP_TIMEOUT)
f18e26af
LR		 3264 MLX5_SET(ads, path, ack_timeout,
3265 alt ? attr->alt_timeout : attr->timeout);
e126ba97 3266
75850d0b 3267 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3268 return modify_raw_packet_eth_prio(dev->mdev,
3269 &qp->raw_packet_qp.sq,
1cd6dbd3 3270 sl & 0xf, qp->ibqp.pd);
75850d0b 3271
e126ba97
EC		 3272 return 0;
3273}
3274
3275static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3276 [MLX5_QP_STATE_INIT] = {
3277 [MLX5_QP_STATE_INIT] = {
3278 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3279 MLX5_QP_OPTPAR_RAE |
3280 MLX5_QP_OPTPAR_RWE |
3281 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3282 MLX5_QP_OPTPAR_PRI_PORT |
3283 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3284 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3285 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3286 MLX5_QP_OPTPAR_PRI_PORT |
3287 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3288 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3289 MLX5_QP_OPTPAR_Q_KEY |
3290 MLX5_QP_OPTPAR_PRI_PORT,
8f4426aa
JM		 3291 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3292 MLX5_QP_OPTPAR_RAE |
3293 MLX5_QP_OPTPAR_RWE |
3294 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3295 MLX5_QP_OPTPAR_PRI_PORT |
3296 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3297 },
3298 [MLX5_QP_STATE_RTR] = {
3299 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3300 MLX5_QP_OPTPAR_RRE |
3301 MLX5_QP_OPTPAR_RAE |
3302 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3303 MLX5_QP_OPTPAR_PKEY_INDEX |
3304 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3305 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3306 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3307 MLX5_QP_OPTPAR_PKEY_INDEX |
3308 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3309 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3310 MLX5_QP_OPTPAR_Q_KEY,
3311 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
3312 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 3313 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3314 MLX5_QP_OPTPAR_RRE |
3315 MLX5_QP_OPTPAR_RAE |
3316 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3317 MLX5_QP_OPTPAR_PKEY_INDEX |
3318 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3319 },
3320 },
3321 [MLX5_QP_STATE_RTR] = {
3322 [MLX5_QP_STATE_RTS] = {
3323 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3324 MLX5_QP_OPTPAR_RRE |
3325 MLX5_QP_OPTPAR_RAE |
3326 MLX5_QP_OPTPAR_RWE |
3327 MLX5_QP_OPTPAR_PM_STATE |
3328 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3329 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3330 MLX5_QP_OPTPAR_RWE |
3331 MLX5_QP_OPTPAR_PM_STATE,
3332 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
8f4426aa
JM		 3333 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3334 MLX5_QP_OPTPAR_RRE |
3335 MLX5_QP_OPTPAR_RAE |
3336 MLX5_QP_OPTPAR_RWE |
3337 MLX5_QP_OPTPAR_PM_STATE |
3338 MLX5_QP_OPTPAR_RNR_TIMEOUT,
e126ba97
EC		 3339 },
3340 },
3341 [MLX5_QP_STATE_RTS] = {
3342 [MLX5_QP_STATE_RTS] = {
3343 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3344 MLX5_QP_OPTPAR_RAE |
3345 MLX5_QP_OPTPAR_RWE |
3346 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 3347 MLX5_QP_OPTPAR_PM_STATE |
3348 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 3349 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 3350 MLX5_QP_OPTPAR_PM_STATE |
3351 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 3352 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
3353 MLX5_QP_OPTPAR_SRQN |
3354 MLX5_QP_OPTPAR_CQN_RCV,
8f4426aa
JM		 3355 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3356 MLX5_QP_OPTPAR_RAE |
3357 MLX5_QP_OPTPAR_RWE |
3358 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3359 MLX5_QP_OPTPAR_PM_STATE |
3360 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 3361 },
3362 },
3363 [MLX5_QP_STATE_SQER] = {
3364 [MLX5_QP_STATE_RTS] = {
3365 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3366 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 3367 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 3368 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3369 MLX5_QP_OPTPAR_RWE |
3370 MLX5_QP_OPTPAR_RAE |
3371 MLX5_QP_OPTPAR_RRE,
8f4426aa
JM		 3372 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3373 MLX5_QP_OPTPAR_RWE |
3374 MLX5_QP_OPTPAR_RAE |
3375 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 3376 },
3377 },
3378};
3379
3380static int ib_nr_to_mlx5_nr(int ib_mask)
3381{
3382 switch (ib_mask) {
3383 case IB_QP_STATE:
3384 return 0;
3385 case IB_QP_CUR_STATE:
3386 return 0;
3387 case IB_QP_EN_SQD_ASYNC_NOTIFY:
3388 return 0;
3389 case IB_QP_ACCESS_FLAGS:
3390 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3391 MLX5_QP_OPTPAR_RAE;
3392 case IB_QP_PKEY_INDEX:
3393 return MLX5_QP_OPTPAR_PKEY_INDEX;
3394 case IB_QP_PORT:
3395 return MLX5_QP_OPTPAR_PRI_PORT;
3396 case IB_QP_QKEY:
3397 return MLX5_QP_OPTPAR_Q_KEY;
3398 case IB_QP_AV:
3399 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3400 MLX5_QP_OPTPAR_PRI_PORT;
3401 case IB_QP_PATH_MTU:
3402 return 0;
3403 case IB_QP_TIMEOUT:
3404 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3405 case IB_QP_RETRY_CNT:
3406 return MLX5_QP_OPTPAR_RETRY_COUNT;
3407 case IB_QP_RNR_RETRY:
3408 return MLX5_QP_OPTPAR_RNR_RETRY;
3409 case IB_QP_RQ_PSN:
3410 return 0;
3411 case IB_QP_MAX_QP_RD_ATOMIC:
3412 return MLX5_QP_OPTPAR_SRA_MAX;
3413 case IB_QP_ALT_PATH:
3414 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3415 case IB_QP_MIN_RNR_TIMER:
3416 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3417 case IB_QP_SQ_PSN:
3418 return 0;
3419 case IB_QP_MAX_DEST_RD_ATOMIC:
3420 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3421 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3422 case IB_QP_PATH_MIG_STATE:
3423 return MLX5_QP_OPTPAR_PM_STATE;
3424 case IB_QP_CAP:
3425 return 0;
3426 case IB_QP_DEST_QPN:
3427 return 0;
3428 }
3429 return 0;
3430}
3431
3432static int ib_mask_to_mlx5_opt(int ib_mask)
3433{
3434 int result = 0;
3435 int i;
3436
3437 for (i = 0; i < 8 * sizeof(int); i++) {
3438 if ((1 << i) & ib_mask)
3439 result |= ib_nr_to_mlx5_nr(1 << i);
3440 }
3441
3442 return result;
3443}
3444
34d57585
YH		 3445static int modify_raw_packet_qp_rq(
3446 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3447 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3448{
3449 void *in;
3450 void *rqc;
3451 int inlen;
3452 int err;
3453
3454 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 3455 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3456 if (!in)
3457 return -ENOMEM;
3458
3459 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
34d57585 3460 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3461
3462 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3463 MLX5_SET(rqc, rqc, state, new_state);
3464
eb49ab0c
AV		 3465 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3466 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3467 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 3468 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 3469 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3470 } else
5a738b5d
JG		 3471 dev_info_once(
3472 &dev->ib_dev.dev,
3473 "RAW PACKET QP counters are not supported on current FW\n");
eb49ab0c
AV		 3474 }
3475
e0b4b472 3476 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
ad5f8e96 3477 if (err)
3478 goto out;
3479
3480 rq->state = new_state;
3481
3482out:
3483 kvfree(in);
3484 return err;
3485}
3486
c14003f0
YH		 3487static int modify_raw_packet_qp_sq(
3488 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3489 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3490{
7d29f349 3491 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 3492 struct mlx5_rate_limit old_rl = ibqp->rl;
3493 struct mlx5_rate_limit new_rl = old_rl;
3494 bool new_rate_added = false;
7d29f349 3495 u16 rl_index = 0;
ad5f8e96 3496 void *in;
3497 void *sqc;
3498 int inlen;
3499 int err;
3500
3501 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 3502 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3503 if (!in)
3504 return -ENOMEM;
3505
c14003f0 3506 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3507 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3508
3509 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3510 MLX5_SET(sqc, sqc, state, new_state);
3511
7d29f349
BW		 3512 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3513 if (new_state != MLX5_SQC_STATE_RDY)
3514 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3515 __func__);
3516 else
61147f39 3517 new_rl = raw_qp_param->rl;
7d29f349
BW		 3518 }
3519
61147f39
BW		 3520 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3521 if (new_rl.rate) {
3522 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 3523 if (err) {
61147f39
BW		 3524 pr_err("Failed configuring rate limit(err %d): \
3525 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3526 err, new_rl.rate, new_rl.max_burst_sz,
3527 new_rl.typical_pkt_sz);
3528
7d29f349
BW		 3529 goto out;
3530 }
61147f39 3531 new_rate_added = true;
7d29f349
BW		 3532 }
3533
3534 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 3535 /* index 0 means no limit */
7d29f349
BW		 3536 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3537 }
3538
e0b4b472 3539 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
7d29f349
BW		 3540 if (err) {
3541 /* Remove new rate from table if failed */
61147f39
BW		 3542 if (new_rate_added)
3543 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 3544 goto out;
7d29f349
BW		 3545 }
3546
3547 /* Only remove the old rate after new rate was set */
c8973df2
RW		 3548 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3549 (new_state != MLX5_SQC_STATE_RDY)) {
61147f39 3550 mlx5_rl_remove_rate(dev, &old_rl);
c8973df2
RW		 3551 if (new_state != MLX5_SQC_STATE_RDY)
3552 memset(&new_rl, 0, sizeof(new_rl));
3553 }
ad5f8e96 3554
61147f39 3555 ibqp->rl = new_rl;
ad5f8e96 3556 sq->state = new_state;
3557
3558out:
3559 kvfree(in);
3560 return err;
3561}
3562
3563static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 3564 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3565 u8 tx_affinity)
ad5f8e96 3566{
3567 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3568 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3569 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 3570 int modify_rq = !!qp->rq.wqe_cnt;
3571 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 3572 int rq_state;
3573 int sq_state;
3574 int err;
3575
0680efa2 3576 switch (raw_qp_param->operation) {
ad5f8e96 3577 case MLX5_CMD_OP_RST2INIT_QP:
3578 rq_state = MLX5_RQC_STATE_RDY;
c94e272b 3579 sq_state = MLX5_SQC_STATE_RST;
ad5f8e96 3580 break;
3581 case MLX5_CMD_OP_2ERR_QP:
3582 rq_state = MLX5_RQC_STATE_ERR;
3583 sq_state = MLX5_SQC_STATE_ERR;
3584 break;
3585 case MLX5_CMD_OP_2RST_QP:
3586 rq_state = MLX5_RQC_STATE_RST;
3587 sq_state = MLX5_SQC_STATE_RST;
3588 break;
ad5f8e96 3589 case MLX5_CMD_OP_RTR2RTS_QP:
3590 case MLX5_CMD_OP_RTS2RTS_QP:
c94e272b
MG		 3591 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT)
3592 return -EINVAL;
3593
3594 modify_rq = 0;
3595 sq_state = MLX5_SQC_STATE_RDY;
7d29f349
BW		 3596 break;
3597 case MLX5_CMD_OP_INIT2INIT_QP:
3598 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 3599 if (raw_qp_param->set_mask)
3600 return -EINVAL;
3601 else
3602 return 0;
ad5f8e96 3603 default:
3604 WARN_ON(1);
3605 return -EINVAL;
3606 }
3607
7d29f349 3608 if (modify_rq) {
34d57585
YH		 3609 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3610 qp->ibqp.pd);
ad5f8e96 3611 if (err)
3612 return err;
3613 }
3614
7d29f349 3615 if (modify_sq) {
d5ed8ac3
MB		 3616 struct mlx5_flow_handle *flow_rule;
3617
13eab21f
AH		 3618 if (tx_affinity) {
3619 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
1cd6dbd3
YH		 3620 tx_affinity,
3621 qp->ibqp.pd);
13eab21f
AH		 3622 if (err)
3623 return err;
3624 }
3625
d5ed8ac3
MB		 3626 flow_rule = create_flow_rule_vport_sq(dev, sq,
3627 raw_qp_param->port);
3628 if (IS_ERR(flow_rule))
1db86318 3629 return PTR_ERR(flow_rule);
d5ed8ac3
MB		 3630
3631 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3632 raw_qp_param, qp->ibqp.pd);
3633 if (err) {
3634 if (flow_rule)
3635 mlx5_del_flow_rules(flow_rule);
3636 return err;
3637 }
3638
3639 if (flow_rule) {
3640 destroy_flow_rule_vport_sq(sq);
3641 sq->flow_rule = flow_rule;
3642 }
3643
3644 return err;
13eab21f 3645 }
ad5f8e96 3646
3647 return 0;
3648}
3649
5163b274
MG		 3650static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev,
3651 struct ib_udata *udata)
c6a21c38 3652{
89944450
SR		 3653 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3654 udata, struct mlx5_ib_ucontext, ibucontext);
5163b274
MG		 3655 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3656 atomic_t *tx_port_affinity;
c6a21c38 3657
5163b274
MG		 3658 if (ucontext)
3659 tx_port_affinity = &ucontext->tx_port_affinity;
3660 else
3661 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity;
3662
3663 return (unsigned int)atomic_add_return(1, tx_port_affinity) %
3664 MLX5_MAX_PORTS + 1;
3665}
3666
8f3243a0
MZ		 3667static bool qp_supports_affinity(struct mlx5_ib_qp *qp)
3668{
3669 if ((qp->type == IB_QPT_RC) || (qp->type == IB_QPT_UD) ||
3670 (qp->type == IB_QPT_UC) || (qp->type == IB_QPT_RAW_PACKET) ||
3671 (qp->type == IB_QPT_XRC_INI) || (qp->type == IB_QPT_XRC_TGT) ||
3672 (qp->type == MLX5_IB_QPT_DCI))
5163b274
MG		 3673 return true;
3674 return false;
3675}
3676
cfc1a89e
MG		 3677static unsigned int get_tx_affinity(struct ib_qp *qp,
3678 const struct ib_qp_attr *attr,
3679 int attr_mask, u8 init,
5163b274
MG		 3680 struct ib_udata *udata)
3681{
3682 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3683 udata, struct mlx5_ib_ucontext, ibucontext);
3684 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3685 struct mlx5_ib_qp *mqp = to_mqp(qp);
3686 struct mlx5_ib_qp_base *qp_base;
3687 unsigned int tx_affinity;
3688
802dcc7f 3689 if (!(mlx5_ib_lag_should_assign_affinity(dev) &&
8f3243a0 3690 qp_supports_affinity(mqp)))
5163b274
MG		 3691 return 0;
3692
cfc1a89e
MG		 3693 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3694 tx_affinity = mqp->gsi_lag_port;
3695 else if (init)
3696 tx_affinity = get_tx_affinity_rr(dev, udata);
3697 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave)
3698 tx_affinity =
3699 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3700 else
3701 return 0;
5163b274
MG		 3702
3703 qp_base = &mqp->trans_qp.base;
3704 if (ucontext)
c6a21c38 3705 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
5163b274
MG		 3706 tx_affinity, qp_base->mqp.qpn, ucontext);
3707 else
c6a21c38 3708 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
5163b274
MG		 3709 tx_affinity, qp_base->mqp.qpn);
3710 return tx_affinity;
c6a21c38
MD		 3711}
3712
d14133dd
MZ		 3713static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3714 struct rdma_counter *counter)
3715{
3716 struct mlx5_ib_dev *dev = to_mdev(qp->device);
64bae2d4 3717 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {};
d14133dd 3718 struct mlx5_ib_qp *mqp = to_mqp(qp);
d14133dd
MZ		 3719 struct mlx5_ib_qp_base *base;
3720 u32 set_id;
64bae2d4 3721 u32 *qpc;
d14133dd 3722
3e1f000f 3723 if (counter)
d14133dd 3724 set_id = counter->id;
3e1f000f
PP		 3725 else
3726 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
d14133dd
MZ		 3727
3728 base = &mqp->trans_qp.base;
64bae2d4
LR		 3729 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
3730 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);
3731 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid);
3732 MLX5_SET(rts2rts_qp_in, in, opt_param_mask,
3733 MLX5_QP_OPTPAR_COUNTER_SET_ID);
3734
3735 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc);
3736 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3737 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
d14133dd
MZ		 3738}
3739
e126ba97
EC		 3740static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3741 const struct ib_qp_attr *attr, int attr_mask,
89944450
SR		 3742 enum ib_qp_state cur_state,
3743 enum ib_qp_state new_state,
3744 const struct mlx5_ib_modify_qp *ucmd,
50aec2c3 3745 struct mlx5_ib_modify_qp_resp *resp,
89944450 3746 struct ib_udata *udata)
e126ba97 3747{
427c1e7b 3748 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3749 [MLX5_QP_STATE_RST] = {
3750 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3751 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3752 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3753 },
3754 [MLX5_QP_STATE_INIT] = {
3755 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3756 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3757 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3758 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3759 },
3760 [MLX5_QP_STATE_RTR] = {
3761 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3762 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3763 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3764 },
3765 [MLX5_QP_STATE_RTS] = {
3766 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3767 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3768 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3769 },
3770 [MLX5_QP_STATE_SQD] = {
3771 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3772 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3773 },
3774 [MLX5_QP_STATE_SQER] = {
3775 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3776 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3777 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3778 },
3779 [MLX5_QP_STATE_ERR] = {
3780 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3781 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3782 }
3783 };
3784
e126ba97
EC		 3785 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3786 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 3787 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97 3788 struct mlx5_ib_cq *send_cq, *recv_cq;
e126ba97
EC		 3789 struct mlx5_ib_pd *pd;
3790 enum mlx5_qp_state mlx5_cur, mlx5_new;
f18e26af 3791 void *qpc, *pri_path, *alt_path;
cfc1a89e 3792 enum mlx5_qp_optpar optpar = 0;
d14133dd 3793 u32 set_id = 0;
e126ba97
EC		 3794 int mlx5_st;
3795 int err;
427c1e7b 3796 u16 op;
13eab21f 3797 u8 tx_affinity = 0;
e126ba97 3798
7aede1a2 3799 mlx5_st = to_mlx5_st(qp->type);
55de9a77
LR		 3800 if (mlx5_st < 0)
3801 return -EINVAL;
3802
f18e26af
LR		 3803 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
3804 if (!qpc)
e126ba97
EC		 3805 return -ENOMEM;
3806
029e88fd 3807 pd = to_mpd(qp->ibqp.pd);
f18e26af 3808 MLX5_SET(qpc, qpc, st, mlx5_st);
e126ba97
EC		 3809
3810 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
f18e26af 3811 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 3812 } else {
3813 switch (attr->path_mig_state) {
3814 case IB_MIG_MIGRATED:
f18e26af 3815 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 3816 break;
3817 case IB_MIG_REARM:
f18e26af 3818 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
e126ba97
EC		 3819 break;
3820 case IB_MIG_ARMED:
f18e26af 3821 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
e126ba97
EC		 3822 break;
3823 }
3824 }
3825
cfc1a89e 3826 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
5163b274
MG		 3827 cur_state == IB_QPS_RESET &&
3828 new_state == IB_QPS_INIT, udata);
f18e26af
LR		 3829
3830 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
3831 if (tx_affinity && new_state == IB_QPS_RTR &&
3832 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3833 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
13eab21f 3834
d16e91da 3835 if (is_sqp(ibqp->qp_type)) {
f18e26af
LR		 3836 MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
3837 MLX5_SET(qpc, qpc, log_msg_max, 8);
c2e53b2c 3838 } else if ((ibqp->qp_type == IB_QPT_UD &&
2be08c30 3839 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
e126ba97 3840 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
f18e26af
LR		 3841 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
3842 MLX5_SET(qpc, qpc, log_msg_max, 12);
e126ba97
EC		 3843 } else if (attr_mask & IB_QP_PATH_MTU) {
3844 if (attr->path_mtu < IB_MTU_256 ||
3845 attr->path_mtu > IB_MTU_4096) {
3846 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3847 err = -EINVAL;
3848 goto out;
3849 }
f18e26af
LR		 3850 MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
3851 MLX5_SET(qpc, qpc, log_msg_max,
3852 MLX5_CAP_GEN(dev->mdev, log_max_msg));
e126ba97
EC		 3853 }
3854
3855 if (attr_mask & IB_QP_DEST_QPN)
f18e26af
LR		 3856 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
3857
3858 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
3859 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
e126ba97
EC		 3860
3861 if (attr_mask & IB_QP_PKEY_INDEX)
f18e26af 3862 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
e126ba97
EC		 3863
3864 /* todo implement counter_index functionality */
3865
3866 if (is_sqp(ibqp->qp_type))
f18e26af 3867 MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
e126ba97
EC		 3868
3869 if (attr_mask & IB_QP_PORT)
f18e26af 3870 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
e126ba97
EC		 3871
3872 if (attr_mask & IB_QP_AV) {
f18e26af
LR		 3873 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
3874 attr_mask & IB_QP_PORT ? attr->port_num :
3875 qp->port,
f879ee8d 3876 attr_mask, 0, attr, false);
e126ba97
EC		 3877 if (err)
3878 goto out;
3879 }
3880
3881 if (attr_mask & IB_QP_TIMEOUT)
f18e26af 3882 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
e126ba97
EC		 3883
3884 if (attr_mask & IB_QP_ALT_PATH) {
f18e26af 3885 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
f879ee8d 3886 attr->alt_port_num,
f18e26af
LR		 3887 attr_mask | IB_QP_PKEY_INDEX |
3888 IB_QP_TIMEOUT,
f879ee8d 3889 0, attr, true);
e126ba97
EC		 3890 if (err)
3891 goto out;
3892 }
3893
89ea94a7
MG		 3894 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3895 &send_cq, &recv_cq);
e126ba97 3896
f18e26af
LR		 3897 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3898 if (send_cq)
3899 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
3900 if (recv_cq)
3901 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
3902
3903 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
e126ba97
EC		 3904
3905 if (attr_mask & IB_QP_RNR_RETRY)
f18e26af 3906 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
e126ba97
EC		 3907
3908 if (attr_mask & IB_QP_RETRY_CNT)
f18e26af 3909 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
e126ba97 3910
f18e26af
LR		 3911 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
3912 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
e126ba97
EC		 3913
3914 if (attr_mask & IB_QP_SQ_PSN)
f18e26af 3915 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
e126ba97 3916
f18e26af
LR		 3917 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
3918 MLX5_SET(qpc, qpc, log_rra_max,
3919 ilog2(attr->max_dest_rd_atomic));
e126ba97 3920
a60109dc 3921 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
f18e26af 3922 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
a60109dc
YC		 3923 if (err)
3924 goto out;
a60109dc 3925 }
e126ba97
EC		 3926
3927 if (attr_mask & IB_QP_MIN_RNR_TIMER)
f18e26af 3928 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
e126ba97
EC		 3929
3930 if (attr_mask & IB_QP_RQ_PSN)
f18e26af 3931 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
e126ba97
EC		 3932
3933 if (attr_mask & IB_QP_QKEY)
f18e26af 3934 MLX5_SET(qpc, qpc, q_key, attr->qkey);
e126ba97
EC		 3935
3936 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
f18e26af 3937 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 3938
0837e86a
MB		 3939 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3940 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3941 qp->port) - 1;
c2e53b2c
YH		 3942
3943 /* Underlay port should be used - index 0 function per port */
2be08c30 3944 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
c2e53b2c
YH		 3945 port_num = 0;
3946
d14133dd
MZ		 3947 if (ibqp->counter)
3948 set_id = ibqp->counter->id;
3949 else
3e1f000f 3950 set_id = mlx5_ib_get_counters_id(dev, port_num);
f18e26af 3951 MLX5_SET(qpc, qpc, counter_set_id, set_id);
0837e86a
MB		 3952 }
3953
e126ba97 3954 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
f18e26af 3955 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 3956
2be08c30 3957 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
f18e26af 3958 MLX5_SET(qpc, qpc, deth_sqpn, 1);
e126ba97
EC		 3959
3960 mlx5_cur = to_mlx5_state(cur_state);
3961 mlx5_new = to_mlx5_state(new_state);
e126ba97 3962
427c1e7b 3963 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3964 !optab[mlx5_cur][mlx5_new]) {
3965 err = -EINVAL;
427c1e7b 3966 goto out;
5d414b17 3967 }
427c1e7b 3968
3969 op = optab[mlx5_cur][mlx5_new];
cfc1a89e 3970 optpar |= ib_mask_to_mlx5_opt(attr_mask);
e126ba97 3971 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3972
c2e53b2c 3973 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 3974 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0680efa2
AV		 3975 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3976
3977 raw_qp_param.operation = op;
eb49ab0c 3978 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
d14133dd 3979 raw_qp_param.rq_q_ctr_id = set_id;
eb49ab0c
AV		 3980 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3981 }
7d29f349 3982
d5ed8ac3
MB		 3983 if (attr_mask & IB_QP_PORT)
3984 raw_qp_param.port = attr->port_num;
3985
7d29f349 3986 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3987 raw_qp_param.rl.rate = attr->rate_limit;
3988
3989 if (ucmd->burst_info.max_burst_sz) {
3990 if (attr->rate_limit &&
3991 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3992 raw_qp_param.rl.max_burst_sz =
3993 ucmd->burst_info.max_burst_sz;
3994 } else {
3995 err = -EINVAL;
3996 goto out;
3997 }
3998 }
3999
4000 if (ucmd->burst_info.typical_pkt_sz) {
4001 if (attr->rate_limit &&
4002 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
4003 raw_qp_param.rl.typical_pkt_sz =
4004 ucmd->burst_info.typical_pkt_sz;
4005 } else {
4006 err = -EINVAL;
4007 goto out;
4008 }
4009 }
4010
7d29f349
BW		 4011 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
4012 }
4013
13eab21f 4014 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 4015 } else {
50aec2c3
LR		 4016 if (udata) {
4017 /* For the kernel flows, the resp will stay zero */
4018 resp->ece_options =
4019 MLX5_CAP_GEN(dev->mdev, ece_support) ?
4020 ucmd->ece_options : 0;
4021 resp->response_length = sizeof(*resp);
4022 }
5f62a521 4023 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp,
50aec2c3 4024 &resp->ece_options);
0680efa2
AV		 4025 }
4026
e126ba97
EC		 4027 if (err)
4028 goto out;
4029
4030 qp->state = new_state;
4031
4032 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 4033 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 4034 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 4035 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 4036 if (attr_mask & IB_QP_PORT)
4037 qp->port = attr->port_num;
4038 if (attr_mask & IB_QP_ALT_PATH)
19098df2 4039 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 4040
4041 /*
4042 * If we moved a kernel QP to RESET, clean up all old CQ
4043 * entries and reinitialize the QP.
4044 */
75a45982
LR		 4045 if (new_state == IB_QPS_RESET &&
4046 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 4047 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 4048 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
4049 if (send_cq != recv_cq)
19098df2 4050 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 4051
4052 qp->rq.head = 0;
4053 qp->rq.tail = 0;
4054 qp->sq.head = 0;
4055 qp->sq.tail = 0;
4056 qp->sq.cur_post = 0;
34f4c955
GL		 4057 if (qp->sq.wqe_cnt)
4058 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
950bf4f1 4059 qp->sq.last_poll = 0;
e126ba97
EC		 4060 qp->db.db[MLX5_RCV_DBR] = 0;
4061 qp->db.db[MLX5_SND_DBR] = 0;
4062 }
4063
d14133dd
MZ		 4064 if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
4065 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
4066 if (!err)
4067 qp->counter_pending = 0;
4068 }
4069
e126ba97 4070out:
f18e26af 4071 kfree(qpc);
e126ba97
EC		 4072 return err;
4073}
4074
c32a4f29
MS		 4075static inline bool is_valid_mask(int mask, int req, int opt)
4076{
4077 if ((mask & req) != req)
4078 return false;
4079
4080 if (mask & ~(req | opt))
4081 return false;
4082
4083 return true;
4084}
4085
4086/* check valid transition for driver QP types
4087 * for now the only QP type that this function supports is DCI
4088 */
4089static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
4090 enum ib_qp_attr_mask attr_mask)
4091{
4092 int req = IB_QP_STATE;
4093 int opt = 0;
4094
99ed748e
MS		 4095 if (new_state == IB_QPS_RESET) {
4096 return is_valid_mask(attr_mask, req, opt);
4097 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
c32a4f29
MS		 4098 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
4099 return is_valid_mask(attr_mask, req, opt);
4100 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4101 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
4102 return is_valid_mask(attr_mask, req, opt);
4103 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4104 req |= IB_QP_PATH_MTU;
5ec0304c 4105 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
c32a4f29
MS		 4106 return is_valid_mask(attr_mask, req, opt);
4107 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4108 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
4109 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
4110 opt = IB_QP_MIN_RNR_TIMER;
4111 return is_valid_mask(attr_mask, req, opt);
4112 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
4113 opt = IB_QP_MIN_RNR_TIMER;
4114 return is_valid_mask(attr_mask, req, opt);
4115 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
4116 return is_valid_mask(attr_mask, req, opt);
4117 }
4118 return false;
4119}
4120
776a3906
MS		 4121/* mlx5_ib_modify_dct: modify a DCT QP
4122 * valid transitions are:
4123 * RESET to INIT: must set access_flags, pkey_index and port
4124 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
4125 * mtu, gid_index and hop_limit
4126 * Other transitions and attributes are illegal
4127 */
4128static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
a645a89d
LR		 4129 int attr_mask, struct mlx5_ib_modify_qp *ucmd,
4130 struct ib_udata *udata)
776a3906
MS		 4131{
4132 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4133 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4134 enum ib_qp_state cur_state, new_state;
776a3906
MS		 4135 int required = IB_QP_STATE;
4136 void *dctc;
71cab8ef 4137 int err;
776a3906
MS		 4138
4139 if (!(attr_mask & IB_QP_STATE))
4140 return -EINVAL;
4141
4142 cur_state = qp->state;
4143 new_state = attr->qp_state;
4144
4145 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
a645a89d
LR		 4146 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options)
4147 /*
4148 * DCT doesn't initialize QP till modify command is executed,
4149 * so we need to overwrite previously set ECE field if user
4150 * provided any value except zero, which means not set/not
4151 * valid.
4152 */
4153 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
4154
776a3906 4155 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3e1f000f
PP		 4156 u16 set_id;
4157
776a3906
MS		 4158 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4159 if (!is_valid_mask(attr_mask, required, 0))
4160 return -EINVAL;
4161
4162 if (attr->port_num == 0 ||
4163 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
4164 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4165 attr->port_num, dev->num_ports);
4166 return -EINVAL;
4167 }
4168 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4169 MLX5_SET(dctc, dctc, rre, 1);
4170 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4171 MLX5_SET(dctc, dctc, rwe, 1);
4172 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 4173 int atomic_mode;
4174
4175 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4176 if (atomic_mode < 0)
776a3906 4177 return -EOPNOTSUPP;
a60109dc
YC		 4178
4179 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
776a3906 4180 MLX5_SET(dctc, dctc, rae, 1);
776a3906
MS		 4181 }
4182 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
7c4b1ab9
MZ		 4183 if (mlx5_lag_is_active(dev->mdev))
4184 MLX5_SET(dctc, dctc, port,
4185 get_tx_affinity_rr(dev, udata));
4186 else
4187 MLX5_SET(dctc, dctc, port, attr->port_num);
3e1f000f
PP		 4188
4189 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4190 MLX5_SET(dctc, dctc, counter_set_id, set_id);
776a3906
MS		 4191 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4192 struct mlx5_ib_modify_qp_resp resp = {};
a645a89d
LR		 4193 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {};
4194 u32 min_resp_len = offsetofend(typeof(resp), dctn);
776a3906
MS		 4195
4196 if (udata->outlen < min_resp_len)
4197 return -EINVAL;
a645a89d
LR		 4198 /*
4199 * If we don't have enough space for the ECE options,
4200 * simply indicate it with resp.response_length.
4201 */
4202 resp.response_length = (udata->outlen < sizeof(resp)) ?
4203 min_resp_len :
4204 sizeof(resp);
4205
776a3906
MS		 4206 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4207 if (!is_valid_mask(attr_mask, required, 0))
4208 return -EINVAL;
4209 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4210 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4211 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4212 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4213 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4214 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4215
333fbaa0 4216 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
c5ae1954
YH		 4217 MLX5_ST_SZ_BYTES(create_dct_in), out,
4218 sizeof(out));
776a3906
MS		 4219 if (err)
4220 return err;
4221 resp.dctn = qp->dct.mdct.mqp.qpn;
a645a89d
LR		 4222 if (MLX5_CAP_GEN(dev->mdev, ece_support))
4223 resp.ece_options = MLX5_GET(create_dct_out, out, ece);
776a3906
MS		 4224 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4225 if (err) {
333fbaa0 4226 mlx5_core_destroy_dct(dev, &qp->dct.mdct);
776a3906
MS		 4227 return err;
4228 }
4229 } else {
4230 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4231 return -EINVAL;
4232 }
71cab8ef
LR		 4233
4234 qp->state = new_state;
4235 return 0;
776a3906
MS		 4236}
4237
e126ba97
EC		 4238int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4239 int attr_mask, struct ib_udata *udata)
4240{
4241 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
50aec2c3 4242 struct mlx5_ib_modify_qp_resp resp = {};
e126ba97 4243 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 4244 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 4245 enum ib_qp_type qp_type;
e126ba97
EC		 4246 enum ib_qp_state cur_state, new_state;
4247 int err = -EINVAL;
4248 int port;
4249
26e990ba
JG		 4250 if (attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT))
4251 return -EOPNOTSUPP;
4252
28d61370
YH		 4253 if (ibqp->rwq_ind_tbl)
4254 return -ENOSYS;
4255
61147f39 4256 if (udata && udata->inlen) {
5f62a521 4257 if (udata->inlen < offsetofend(typeof(ucmd), ece_options))
61147f39
BW		 4258 return -EINVAL;
4259
4260 if (udata->inlen > sizeof(ucmd) &&
4261 !ib_is_udata_cleared(udata, sizeof(ucmd),
4262 udata->inlen - sizeof(ucmd)))
4263 return -EOPNOTSUPP;
4264
4265 if (ib_copy_from_udata(&ucmd, udata,
4266 min(udata->inlen, sizeof(ucmd))))
4267 return -EFAULT;
4268
4269 if (ucmd.comp_mask ||
61147f39
BW		 4270 memchr_inv(&ucmd.burst_info.reserved, 0,
4271 sizeof(ucmd.burst_info.reserved)))
4272 return -EOPNOTSUPP;
5f62a521 4273
61147f39
BW		 4274 }
4275
d16e91da
HE		 4276 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4277 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4278
7aede1a2
LR		 4279 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4280 qp->type;
c32a4f29 4281
a645a89d
LR		 4282 if (qp_type == MLX5_IB_QPT_DCT)
4283 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata);
d16e91da 4284
e126ba97
EC		 4285 mutex_lock(&qp->mutex);
4286
4287 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4288 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4289
2811ba51
AS		 4290 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4291 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2811ba51
AS		 4292 }
4293
2be08c30 4294 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
c2e53b2c
YH		 4295 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4296 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4297 attr_mask);
4298 goto out;
4299 }
4300 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29 4301 qp_type != MLX5_IB_QPT_DCI &&
d31131bb
KH		 4302 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4303 attr_mask)) {
158abf86
HE		 4304 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4305 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 4306 goto out;
c32a4f29
MS		 4307 } else if (qp_type == MLX5_IB_QPT_DCI &&
4308 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4309 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4310 cur_state, new_state, qp_type, attr_mask);
4311 goto out;
158abf86 4312 }
e126ba97
EC		 4313
4314 if ((attr_mask & IB_QP_PORT) &&
938fe83c 4315 (attr->port_num == 0 ||
508562d6 4316 attr->port_num > dev->num_ports)) {
158abf86
HE		 4317 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4318 attr->port_num, dev->num_ports);
e126ba97 4319 goto out;
158abf86 4320 }
e126ba97
EC		 4321
4322 if (attr_mask & IB_QP_PKEY_INDEX) {
4323 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 4324 if (attr->pkey_index >=
158abf86
HE		 4325 dev->mdev->port_caps[port - 1].pkey_table_len) {
4326 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4327 attr->pkey_index);
e126ba97 4328 goto out;
158abf86 4329 }
e126ba97
EC		 4330 }
4331
4332 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 4333 attr->max_rd_atomic >
158abf86
HE		 4334 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4335 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4336 attr->max_rd_atomic);
e126ba97 4337 goto out;
158abf86 4338 }
e126ba97
EC		 4339
4340 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 4341 attr->max_dest_rd_atomic >
158abf86
HE		 4342 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4343 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4344 attr->max_dest_rd_atomic);
e126ba97 4345 goto out;
158abf86 4346 }
e126ba97
EC		 4347
4348 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4349 err = 0;
4350 goto out;
4351 }
4352
61147f39 4353 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
50aec2c3
LR		 4354 new_state, &ucmd, &resp, udata);
4355
4356 /* resp.response_length is set in ECE supported flows only */
4357 if (!err && resp.response_length &&
4358 udata->outlen >= resp.response_length)
6512f11d
LR		 4359 /* Return -EFAULT to the user and expect him to destroy QP. */
4360 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97
EC		 4361
4362out:
4363 mutex_unlock(&qp->mutex);
4364 return err;
4365}
4366
e126ba97
EC		 4367static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4368{
4369 switch (mlx5_state) {
4370 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4371 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4372 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4373 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4374 case MLX5_QP_STATE_SQ_DRAINING:
4375 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4376 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4377 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4378 default: return -1;
4379 }
4380}
4381
4382static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4383{
4384 switch (mlx5_mig_state) {
4385 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4386 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4387 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4388 default: return -1;
4389 }
4390}
4391
38349389 4392static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
70bd7fb8 4393 struct rdma_ah_attr *ah_attr, void *path)
e126ba97 4394{
70bd7fb8
LR		 4395 int port = MLX5_GET(ads, path, vhca_port_num);
4396 int static_rate;
e126ba97 4397
d8966fcd 4398 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4399
70bd7fb8 4400 if (!port || port > ibdev->num_ports)
e126ba97
EC		 4401 return;
4402
70bd7fb8 4403 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port);
ae59c3f0 4404
70bd7fb8
LR		 4405 rdma_ah_set_port_num(ah_attr, port);
4406 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl));
d8966fcd 4407
70bd7fb8
LR		 4408 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid));
4409 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid));
2d7e3ff7 4410
70bd7fb8
LR		 4411 static_rate = MLX5_GET(ads, path, stat_rate);
4412 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0);
4413 if (MLX5_GET(ads, path, grh) ||
2d7e3ff7 4414 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
70bd7fb8
LR		 4415 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label),
4416 MLX5_GET(ads, path, src_addr_index),
4417 MLX5_GET(ads, path, hop_limit),
4418 MLX5_GET(ads, path, tclass));
d4433557 4419 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip));
e126ba97
EC		 4420 }
4421}
4422
6d2f89df 4423static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4424 struct mlx5_ib_sq *sq,
4425 u8 *sq_state)
4426{
6d2f89df 4427 int err;
4428
28160771 4429 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
6d2f89df 4430 if (err)
4431 goto out;
6d2f89df 4432 sq->state = *sq_state;
4433
4434out:
6d2f89df 4435 return err;
4436}
4437
4438static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4439 struct mlx5_ib_rq *rq,
4440 u8 *rq_state)
4441{
4442 void *out;
4443 void *rqc;
4444 int inlen;
4445 int err;
4446
4447 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4448 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4449 if (!out)
4450 return -ENOMEM;
4451
4452 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4453 if (err)
4454 goto out;
4455
4456 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4457 *rq_state = MLX5_GET(rqc, rqc, state);
4458 rq->state = *rq_state;
4459
4460out:
4461 kvfree(out);
4462 return err;
4463}
4464
4465static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4466 struct mlx5_ib_qp *qp, u8 *qp_state)
4467{
4468 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4469 [MLX5_RQC_STATE_RST] = {
4470 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4471 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4472 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4473 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4474 },
4475 [MLX5_RQC_STATE_RDY] = {
c94e272b 4476 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
6d2f89df 4477 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4478 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4479 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4480 },
4481 [MLX5_RQC_STATE_ERR] = {
4482 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4483 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4484 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4485 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4486 },
4487 [MLX5_RQ_STATE_NA] = {
c94e272b 4488 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
6d2f89df 4489 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4490 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4491 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4492 },
4493 };
4494
4495 *qp_state = sqrq_trans[rq_state][sq_state];
4496
4497 if (*qp_state == MLX5_QP_STATE_BAD) {
4498 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4499 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4500 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4501 return -EINVAL;
4502 }
4503
4504 if (*qp_state == MLX5_QP_STATE)
4505 *qp_state = qp->state;
4506
4507 return 0;
4508}
4509
4510static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4511 struct mlx5_ib_qp *qp,
4512 u8 *raw_packet_qp_state)
4513{
4514 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4515 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4516 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4517 int err;
4518 u8 sq_state = MLX5_SQ_STATE_NA;
4519 u8 rq_state = MLX5_RQ_STATE_NA;
4520
4521 if (qp->sq.wqe_cnt) {
4522 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4523 if (err)
4524 return err;
4525 }
4526
4527 if (qp->rq.wqe_cnt) {
4528 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4529 if (err)
4530 return err;
4531 }
4532
4533 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4534 raw_packet_qp_state);
4535}
4536
4537static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4538 struct ib_qp_attr *qp_attr)
e126ba97 4539{
09a7d9ec 4540 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
70bd7fb8 4541 void *qpc, *pri_path, *alt_path;
09a7d9ec 4542 u32 *outb;
70bd7fb8 4543 int err;
e126ba97 4544
09a7d9ec 4545 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4546 if (!outb)
4547 return -ENOMEM;
4548
333fbaa0 4549 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
e126ba97 4550 if (err)
6d2f89df 4551 goto out;
e126ba97 4552
70bd7fb8
LR		 4553 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc);
4554
4555 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state));
4556 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING)
4557 qp_attr->sq_draining = 1;
4558
4559 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu);
4560 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state));
4561 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key);
4562 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn);
4563 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn);
4564 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn);
09a7d9ec 4565
70bd7fb8
LR		 4566 if (MLX5_GET(qpc, qpc, rre))
4567 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ;
4568 if (MLX5_GET(qpc, qpc, rwe))
4569 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE;
4570 if (MLX5_GET(qpc, qpc, rae))
4571 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC;
e126ba97 4572
70bd7fb8
LR		 4573 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max);
4574 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max);
4575 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak);
4576 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count);
4577 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry);
4578
4579 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
4580 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
e126ba97
EC		 4581
4582 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
70bd7fb8
LR		 4583 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path);
4584 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path);
4585 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index);
4586 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num);
4587 }
4588
4589 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index);
4590 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num);
4591 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout);
4592 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout);
6d2f89df 4593
4594out:
4595 kfree(outb);
4596 return err;
4597}
4598
776a3906
MS		 4599static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4600 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4601 struct ib_qp_init_attr *qp_init_attr)
4602{
4603 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4604 u32 *out;
4605 u32 access_flags = 0;
4606 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4607 void *dctc;
4608 int err;
4609 int supported_mask = IB_QP_STATE |
4610 IB_QP_ACCESS_FLAGS |
4611 IB_QP_PORT |
4612 IB_QP_MIN_RNR_TIMER |
4613 IB_QP_AV |
4614 IB_QP_PATH_MTU |
4615 IB_QP_PKEY_INDEX;
4616
4617 if (qp_attr_mask & ~supported_mask)
4618 return -EINVAL;
4619 if (mqp->state != IB_QPS_RTR)
4620 return -EINVAL;
4621
4622 out = kzalloc(outlen, GFP_KERNEL);
4623 if (!out)
4624 return -ENOMEM;
4625
333fbaa0 4626 err = mlx5_core_dct_query(dev, dct, out, outlen);
776a3906
MS		 4627 if (err)
4628 goto out;
4629
4630 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4631
4632 if (qp_attr_mask & IB_QP_STATE)
4633 qp_attr->qp_state = IB_QPS_RTR;
4634
4635 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4636 if (MLX5_GET(dctc, dctc, rre))
4637 access_flags |= IB_ACCESS_REMOTE_READ;
4638 if (MLX5_GET(dctc, dctc, rwe))
4639 access_flags |= IB_ACCESS_REMOTE_WRITE;
4640 if (MLX5_GET(dctc, dctc, rae))
4641 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4642 qp_attr->qp_access_flags = access_flags;
4643 }
4644
4645 if (qp_attr_mask & IB_QP_PORT)
4646 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4647 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4648 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4649 if (qp_attr_mask & IB_QP_AV) {
4650 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4651 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4652 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4653 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4654 }
4655 if (qp_attr_mask & IB_QP_PATH_MTU)
4656 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4657 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4658 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4659out:
4660 kfree(out);
4661 return err;
4662}
4663
6d2f89df 4664int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4665 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4666{
4667 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4668 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4669 int err = 0;
4670 u8 raw_packet_qp_state;
4671
28d61370
YH		 4672 if (ibqp->rwq_ind_tbl)
4673 return -ENOSYS;
4674
d16e91da
HE		 4675 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4676 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4677 qp_init_attr);
4678
c2e53b2c
YH		 4679 /* Not all of output fields are applicable, make sure to zero them */
4680 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4681 memset(qp_attr, 0, sizeof(*qp_attr));
4682
7aede1a2 4683 if (unlikely(qp->type == MLX5_IB_QPT_DCT))
776a3906
MS		 4684 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4685 qp_attr_mask, qp_init_attr);
4686
6d2f89df 4687 mutex_lock(&qp->mutex);
4688
c2e53b2c 4689 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 4690 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
6d2f89df 4691 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4692 if (err)
4693 goto out;
4694 qp->state = raw_packet_qp_state;
4695 qp_attr->port_num = 1;
4696 } else {
4697 err = query_qp_attr(dev, qp, qp_attr);
4698 if (err)
4699 goto out;
4700 }
4701
4702 qp_attr->qp_state = qp->state;
e126ba97
EC		 4703 qp_attr->cur_qp_state = qp_attr->qp_state;
4704 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4705 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4706
4707 if (!ibqp->uobject) {
0540d814 4708 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4709 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4710 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4711 } else {
4712 qp_attr->cap.max_send_wr = 0;
4713 qp_attr->cap.max_send_sge = 0;
4714 }
4715
0540d814
NO		 4716 qp_init_attr->qp_type = ibqp->qp_type;
4717 qp_init_attr->recv_cq = ibqp->recv_cq;
4718 qp_init_attr->send_cq = ibqp->send_cq;
4719 qp_init_attr->srq = ibqp->srq;
4720 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4721
4722 qp_init_attr->cap = qp_attr->cap;
4723
a8f3ea61 4724 qp_init_attr->create_flags = qp->flags;
051f2630 4725
e126ba97
EC		 4726 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4727 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4728
e126ba97
EC		 4729out:
4730 mutex_unlock(&qp->mutex);
4731 return err;
4732}
4733
28ad5f65 4734int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata)
e126ba97 4735{
28ad5f65
LR		 4736 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device);
4737 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd);
e126ba97 4738
938fe83c 4739 if (!MLX5_CAP_GEN(dev->mdev, xrc))
28ad5f65 4740 return -EOPNOTSUPP;
e126ba97 4741
28ad5f65 4742 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
e126ba97
EC		 4743}
4744
d0c45c85 4745int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
e126ba97
EC		 4746{
4747 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4748 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
e126ba97 4749
d0c45c85 4750 return mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
e126ba97 4751}
79b20a6c 4752
350d0e4c
YH		 4753static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4754{
4755 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4756 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4757 struct ib_event event;
4758
4759 if (rwq->ibwq.event_handler) {
4760 event.device = rwq->ibwq.device;
4761 event.element.wq = &rwq->ibwq;
4762 switch (type) {
4763 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4764 event.event = IB_EVENT_WQ_FATAL;
4765 break;
4766 default:
4767 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4768 return;
4769 }
4770
4771 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4772 }
4773}
4774
03404e8a
MG		 4775static int set_delay_drop(struct mlx5_ib_dev *dev)
4776{
4777 int err = 0;
4778
4779 mutex_lock(&dev->delay_drop.lock);
4780 if (dev->delay_drop.activate)
4781 goto out;
4782
333fbaa0 4783 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
03404e8a
MG		 4784 if (err)
4785 goto out;
4786
4787 dev->delay_drop.activate = true;
4788out:
4789 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 4790
4791 if (!err)
4792 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 4793 return err;
4794}
4795
79b20a6c
YH		 4796static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4797 struct ib_wq_init_attr *init_attr)
4798{
4799 struct mlx5_ib_dev *dev;
4be6da1e 4800 int has_net_offloads;
79b20a6c
YH		 4801 __be64 *rq_pas0;
4802 void *in;
4803 void *rqc;
4804 void *wq;
4805 int inlen;
4806 int err;
4807
4808 dev = to_mdev(pd->device);
4809
4810 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 4811 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 4812 if (!in)
4813 return -ENOMEM;
4814
34d57585 4815 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
79b20a6c
YH		 4816 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4817 MLX5_SET(rqc, rqc, mem_rq_type,
4818 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4819 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4820 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4821 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4822 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4823 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 4824 MLX5_SET(wq, wq, wq_type,
4825 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4826 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 4827 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4828 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4829 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4830 err = -EOPNOTSUPP;
4831 goto out;
4832 } else {
4833 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4834 }
4835 }
79b20a6c 4836 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087 4837 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
c16339b6
MZ		 4838 /*
4839 * In Firmware number of strides in each WQE is:
4840 * "512 * 2^single_wqe_log_num_of_strides"
4841 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
4842 * accepted as 0 to 9
4843 */
4844 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
4845 2, 3, 4, 5, 6, 7, 8, 9 };
ccc87087
NO		 4846 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4847 MLX5_SET(wq, wq, log_wqe_stride_size,
4848 rwq->single_stride_log_num_of_bytes -
4849 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
c16339b6
MZ		 4850 MLX5_SET(wq, wq, log_wqe_num_of_strides,
4851 fw_map[rwq->log_num_strides -
4852 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
ccc87087 4853 }
79b20a6c
YH		 4854 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4855 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4856 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4857 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4858 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4859 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4860 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4861 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4862 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4863 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4864 err = -EOPNOTSUPP;
4865 goto out;
4866 }
4867 } else {
4868 MLX5_SET(rqc, rqc, vsd, 1);
4869 }
4be6da1e
NO		 4870 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4871 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4872 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4873 err = -EOPNOTSUPP;
4874 goto out;
4875 }
4876 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4877 }
03404e8a
MG		 4878 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4879 if (!(dev->ib_dev.attrs.raw_packet_caps &
4880 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4881 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4882 err = -EOPNOTSUPP;
4883 goto out;
4884 }
4885 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4886 }
79b20a6c 4887 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
aab8d396 4888 mlx5_ib_populate_pas(rwq->umem, 1UL << rwq->page_shift, rq_pas0, 0);
333fbaa0 4889 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
03404e8a
MG		 4890 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4891 err = set_delay_drop(dev);
4892 if (err) {
4893 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4894 err);
333fbaa0 4895 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
03404e8a
MG		 4896 } else {
4897 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4898 }
4899 }
b1f74a84 4900out:
79b20a6c
YH		 4901 kvfree(in);
4902 return err;
4903}
4904
4905static int set_user_rq_size(struct mlx5_ib_dev *dev,
4906 struct ib_wq_init_attr *wq_init_attr,
4907 struct mlx5_ib_create_wq *ucmd,
4908 struct mlx5_ib_rwq *rwq)
4909{
4910 /* Sanity check RQ size before proceeding */
4911 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4912 return -EINVAL;
4913
4914 if (!ucmd->rq_wqe_count)
4915 return -EINVAL;
4916
4917 rwq->wqe_count = ucmd->rq_wqe_count;
4918 rwq->wqe_shift = ucmd->rq_wqe_shift;
0dfe4522
LR		 4919 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
4920 return -EINVAL;
4921
79b20a6c
YH		 4922 rwq->log_rq_stride = rwq->wqe_shift;
4923 rwq->log_rq_size = ilog2(rwq->wqe_count);
4924 return 0;
4925}
4926
c16339b6
MZ		 4927static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
4928{
4929 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4930 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4931 return false;
4932
4933 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
4934 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4935 return false;
4936
4937 return true;
4938}
4939
79b20a6c
YH		 4940static int prepare_user_rq(struct ib_pd *pd,
4941 struct ib_wq_init_attr *init_attr,
4942 struct ib_udata *udata,
4943 struct mlx5_ib_rwq *rwq)
4944{
4945 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4946 struct mlx5_ib_create_wq ucmd = {};
4947 int err;
4948 size_t required_cmd_sz;
4949
70c1430f
LR		 4950 required_cmd_sz = offsetofend(struct mlx5_ib_create_wq,
4951 single_stride_log_num_of_bytes);
79b20a6c
YH		 4952 if (udata->inlen < required_cmd_sz) {
4953 mlx5_ib_dbg(dev, "invalid inlen\n");
4954 return -EINVAL;
4955 }
4956
4957 if (udata->inlen > sizeof(ucmd) &&
4958 !ib_is_udata_cleared(udata, sizeof(ucmd),
4959 udata->inlen - sizeof(ucmd))) {
4960 mlx5_ib_dbg(dev, "inlen is not supported\n");
4961 return -EOPNOTSUPP;
4962 }
4963
4964 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4965 mlx5_ib_dbg(dev, "copy failed\n");
4966 return -EFAULT;
4967 }
4968
ccc87087 4969 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 4970 mlx5_ib_dbg(dev, "invalid comp mask\n");
4971 return -EOPNOTSUPP;
ccc87087
NO		 4972 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4973 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4974 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4975 return -EOPNOTSUPP;
4976 }
4977 if ((ucmd.single_stride_log_num_of_bytes <
4978 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4979 (ucmd.single_stride_log_num_of_bytes >
4980 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4981 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4982 ucmd.single_stride_log_num_of_bytes,
4983 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4984 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4985 return -EINVAL;
4986 }
c16339b6
MZ		 4987 if (!log_of_strides_valid(dev,
4988 ucmd.single_wqe_log_num_of_strides)) {
4989 mlx5_ib_dbg(
4990 dev,
4991 "Invalid log num strides (%u. Range is %u - %u)\n",
4992 ucmd.single_wqe_log_num_of_strides,
4993 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
4994 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
4995 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4996 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
ccc87087
NO		 4997 return -EINVAL;
4998 }
4999 rwq->single_stride_log_num_of_bytes =
5000 ucmd.single_stride_log_num_of_bytes;
5001 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5002 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5003 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5004 }
5005
5006 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5007 if (err) {
5008 mlx5_ib_dbg(dev, "err %d\n", err);
5009 return err;
5010 }
5011
b0ea0fa5 5012 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
79b20a6c
YH		 5013 if (err) {
5014 mlx5_ib_dbg(dev, "err %d\n", err);
645ba597 5015 return err;
79b20a6c
YH		 5016 }
5017
5018 rwq->user_index = ucmd.user_index;
5019 return 0;
5020}
5021
5022struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5023 struct ib_wq_init_attr *init_attr,
5024 struct ib_udata *udata)
5025{
5026 struct mlx5_ib_dev *dev;
5027 struct mlx5_ib_rwq *rwq;
5028 struct mlx5_ib_create_wq_resp resp = {};
5029 size_t min_resp_len;
5030 int err;
5031
5032 if (!udata)
5033 return ERR_PTR(-ENOSYS);
5034
70c1430f 5035 min_resp_len = offsetofend(struct mlx5_ib_create_wq_resp, reserved);
79b20a6c
YH		 5036 if (udata->outlen && udata->outlen < min_resp_len)
5037 return ERR_PTR(-EINVAL);
5038
ba80013f
MG		 5039 if (!capable(CAP_SYS_RAWIO) &&
5040 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5041 return ERR_PTR(-EPERM);
5042
79b20a6c
YH		 5043 dev = to_mdev(pd->device);
5044 switch (init_attr->wq_type) {
5045 case IB_WQT_RQ:
5046 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5047 if (!rwq)
5048 return ERR_PTR(-ENOMEM);
5049 err = prepare_user_rq(pd, init_attr, udata, rwq);
5050 if (err)
5051 goto err;
5052 err = create_rq(rwq, pd, init_attr);
5053 if (err)
5054 goto err_user_rq;
5055 break;
5056 default:
5057 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5058 init_attr->wq_type);
5059 return ERR_PTR(-EINVAL);
5060 }
5061
350d0e4c 5062 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5063 rwq->ibwq.state = IB_WQS_RESET;
5064 if (udata->outlen) {
70c1430f
LR		 5065 resp.response_length = offsetofend(
5066 struct mlx5_ib_create_wq_resp, response_length);
79b20a6c
YH		 5067 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5068 if (err)
5069 goto err_copy;
5070 }
5071
350d0e4c
YH		 5072 rwq->core_qp.event = mlx5_ib_wq_event;
5073 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5074 return &rwq->ibwq;
5075
5076err_copy:
333fbaa0 5077 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
79b20a6c 5078err_user_rq:
bdeacabd 5079 destroy_user_rq(dev, pd, rwq, udata);
79b20a6c
YH		 5080err:
5081 kfree(rwq);
5082 return ERR_PTR(err);
5083}
5084
add53535 5085int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
79b20a6c
YH		 5086{
5087 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5088 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
add53535 5089 int ret;
79b20a6c 5090
add53535
LR		 5091 ret = mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
5092 if (ret)
5093 return ret;
bdeacabd 5094 destroy_user_rq(dev, wq->pd, rwq, udata);
79b20a6c 5095 kfree(rwq);
add53535 5096 return 0;
79b20a6c
YH		 5097}
5098
c0a6b5ec
LR		 5099int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
5100 struct ib_rwq_ind_table_init_attr *init_attr,
5101 struct ib_udata *udata)
c5f90929 5102{
c0a6b5ec
LR		 5103 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl =
5104 to_mrwq_ind_table(ib_rwq_ind_table);
5105 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_table->device);
c5f90929
YH		 5106 int sz = 1 << init_attr->log_ind_tbl_size;
5107 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5108 size_t min_resp_len;
5109 int inlen;
5110 int err;
5111 int i;
5112 u32 *in;
5113 void *rqtc;
5114
5115 if (udata->inlen > 0 &&
5116 !ib_is_udata_cleared(udata, 0,
5117 udata->inlen))
c0a6b5ec 5118 return -EOPNOTSUPP;
c5f90929 5119
efd7f400
MG		 5120 if (init_attr->log_ind_tbl_size >
5121 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5122 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5123 init_attr->log_ind_tbl_size,
5124 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
c0a6b5ec 5125 return -EINVAL;
efd7f400
MG		 5126 }
5127
70c1430f
LR		 5128 min_resp_len =
5129 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp, reserved);
c5f90929 5130 if (udata->outlen && udata->outlen < min_resp_len)
c0a6b5ec 5131 return -EINVAL;
c5f90929
YH		 5132
5133 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5134 in = kvzalloc(inlen, GFP_KERNEL);
c0a6b5ec
LR		 5135 if (!in)
5136 return -ENOMEM;
c5f90929
YH		 5137
5138 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5139
5140 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5141 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5142
5143 for (i = 0; i < sz; i++)
5144 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5145
5deba86e
YH		 5146 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5147 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5148
c5f90929
YH		 5149 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5150 kvfree(in);
c5f90929 5151 if (err)
c0a6b5ec 5152 return err;
c5f90929
YH		 5153
5154 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5155 if (udata->outlen) {
70c1430f
LR		 5156 resp.response_length =
5157 offsetofend(struct mlx5_ib_create_rwq_ind_tbl_resp,
5158 response_length);
c5f90929
YH		 5159 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5160 if (err)
5161 goto err_copy;
5162 }
5163
c0a6b5ec 5164 return 0;
c5f90929
YH		 5165
5166err_copy:
5deba86e 5167 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c0a6b5ec 5168 return err;
c5f90929
YH		 5169}
5170
5171int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5172{
5173 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5174 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5175
c0a6b5ec 5176 return mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5177}
5178
79b20a6c
YH		 5179int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5180 u32 wq_attr_mask, struct ib_udata *udata)
5181{
5182 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5183 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5184 struct mlx5_ib_modify_wq ucmd = {};
5185 size_t required_cmd_sz;
5186 int curr_wq_state;
5187 int wq_state;
5188 int inlen;
5189 int err;
5190 void *rqc;
5191 void *in;
5192
70c1430f 5193 required_cmd_sz = offsetofend(struct mlx5_ib_modify_wq, reserved);
79b20a6c
YH		 5194 if (udata->inlen < required_cmd_sz)
5195 return -EINVAL;
5196
5197 if (udata->inlen > sizeof(ucmd) &&
5198 !ib_is_udata_cleared(udata, sizeof(ucmd),
5199 udata->inlen - sizeof(ucmd)))
5200 return -EOPNOTSUPP;
5201
5202 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5203 return -EFAULT;
5204
5205 if (ucmd.comp_mask || ucmd.reserved)
5206 return -EOPNOTSUPP;
5207
5208 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5209 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5210 if (!in)
5211 return -ENOMEM;
5212
5213 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5214
5215 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5216 wq_attr->curr_wq_state : wq->state;
5217 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5218 wq_attr->wq_state : curr_wq_state;
5219 if (curr_wq_state == IB_WQS_ERR)
5220 curr_wq_state = MLX5_RQC_STATE_ERR;
5221 if (wq_state == IB_WQS_ERR)
5222 wq_state = MLX5_RQC_STATE_ERR;
5223 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
34d57585 5224 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
79b20a6c
YH		 5225 MLX5_SET(rqc, rqc, state, wq_state);
5226
b1f74a84
NO		 5227 if (wq_attr_mask & IB_WQ_FLAGS) {
5228 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5229 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5230 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5231 mlx5_ib_dbg(dev, "VLAN offloads are not "
5232 "supported\n");
5233 err = -EOPNOTSUPP;
5234 goto out;
5235 }
5236 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5237 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5238 MLX5_SET(rqc, rqc, vsd,
5239 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5240 }
b1383aa6
NO		 5241
5242 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5243 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5244 err = -EOPNOTSUPP;
5245 goto out;
5246 }
b1f74a84
NO		 5247 }
5248
23a6964e 5249 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
3e1f000f
PP		 5250 u16 set_id;
5251
5252 set_id = mlx5_ib_get_counters_id(dev, 0);
23a6964e
MD		 5253 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5254 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5255 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3e1f000f 5256 MLX5_SET(rqc, rqc, counter_set_id, set_id);
23a6964e 5257 } else
5a738b5d
JG		 5258 dev_info_once(
5259 &dev->ib_dev.dev,
5260 "Receive WQ counters are not supported on current FW\n");
23a6964e
MD		 5261 }
5262
e0b4b472 5263 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
79b20a6c
YH		 5264 if (!err)
5265 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5266
b1f74a84
NO		 5267out:
5268 kvfree(in);
79b20a6c
YH		 5269 return err;
5270}
d0e84c0a
YH		 5271
5272struct mlx5_ib_drain_cqe {
5273 struct ib_cqe cqe;
5274 struct completion done;
5275};
5276
5277static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5278{
5279 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5280 struct mlx5_ib_drain_cqe,
5281 cqe);
5282
5283 complete(&cqe->done);
5284}
5285
5286/* This function returns only once the drained WR was completed */
5287static void handle_drain_completion(struct ib_cq *cq,
5288 struct mlx5_ib_drain_cqe *sdrain,
5289 struct mlx5_ib_dev *dev)
5290{
5291 struct mlx5_core_dev *mdev = dev->mdev;
5292
5293 if (cq->poll_ctx == IB_POLL_DIRECT) {
5294 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5295 ib_process_cq_direct(cq, -1);
5296 return;
5297 }
5298
5299 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5300 struct mlx5_ib_cq *mcq = to_mcq(cq);
5301 bool triggered = false;
5302 unsigned long flags;
5303
5304 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5305 /* Make sure that the CQ handler won't run if wasn't run yet */
5306 if (!mcq->mcq.reset_notify_added)
5307 mcq->mcq.reset_notify_added = 1;
5308 else
5309 triggered = true;
5310 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5311
5312 if (triggered) {
5313 /* Wait for any scheduled/running task to be ended */
5314 switch (cq->poll_ctx) {
5315 case IB_POLL_SOFTIRQ:
5316 irq_poll_disable(&cq->iop);
5317 irq_poll_enable(&cq->iop);
5318 break;
5319 case IB_POLL_WORKQUEUE:
5320 cancel_work_sync(&cq->work);
5321 break;
5322 default:
5323 WARN_ON_ONCE(1);
5324 }
5325 }
5326
5327 /* Run the CQ handler - this makes sure that the drain WR will
5328 * be processed if wasn't processed yet.
5329 */
4e0e2ea1 5330 mcq->mcq.comp(&mcq->mcq, NULL);
d0e84c0a
YH		 5331 }
5332
5333 wait_for_completion(&sdrain->done);
5334}
5335
5336void mlx5_ib_drain_sq(struct ib_qp *qp)
5337{
5338 struct ib_cq *cq = qp->send_cq;
5339 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5340 struct mlx5_ib_drain_cqe sdrain;
d34ac5cd 5341 const struct ib_send_wr *bad_swr;
d0e84c0a
YH		 5342 struct ib_rdma_wr swr = {
5343 .wr = {
5344 .next = NULL,
5345 { .wr_cqe = &sdrain.cqe, },
5346 .opcode = IB_WR_RDMA_WRITE,
5347 },
5348 };
5349 int ret;
5350 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5351 struct mlx5_core_dev *mdev = dev->mdev;
5352
5353 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5354 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5355 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5356 return;
5357 }
5358
5359 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5360 init_completion(&sdrain.done);
5361
029e88fd 5362 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr);
d0e84c0a
YH		 5363 if (ret) {
5364 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5365 return;
5366 }
5367
5368 handle_drain_completion(cq, &sdrain, dev);
5369}
5370
5371void mlx5_ib_drain_rq(struct ib_qp *qp)
5372{
5373 struct ib_cq *cq = qp->recv_cq;
5374 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5375 struct mlx5_ib_drain_cqe rdrain;
d34ac5cd
BVA		 5376 struct ib_recv_wr rwr = {};
5377 const struct ib_recv_wr *bad_rwr;
d0e84c0a
YH		 5378 int ret;
5379 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5380 struct mlx5_core_dev *mdev = dev->mdev;
5381
5382 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5383 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5384 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5385 return;
5386 }
5387
5388 rwr.wr_cqe = &rdrain.cqe;
5389 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5390 init_completion(&rdrain.done);
5391
029e88fd 5392 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr);
d0e84c0a
YH		 5393 if (ret) {
5394 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5395 return;
5396 }
5397
5398 handle_drain_completion(cq, &rdrain, dev);
5399}
d14133dd
MZ		 5400
5401/**
5402 * Bind a qp to a counter. If @counter is NULL then bind the qp to
5403 * the default counter
5404 */
5405int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
5406{
10189e8e 5407 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d14133dd
MZ		 5408 struct mlx5_ib_qp *mqp = to_mqp(qp);
5409 int err = 0;
5410
5411 mutex_lock(&mqp->mutex);
5412 if (mqp->state == IB_QPS_RESET) {
5413 qp->counter = counter;
5414 goto out;
5415 }
5416
10189e8e
MZ		 5417 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
5418 err = -EOPNOTSUPP;
5419 goto out;
5420 }
5421
d14133dd
MZ		 5422 if (mqp->state == IB_QPS_RTS) {
5423 err = __mlx5_ib_qp_set_counter(qp, counter);
5424 if (!err)
5425 qp->counter = counter;
5426
5427 goto out;
5428 }
5429
5430 mqp->counter_pending = 1;
5431 qp->counter = counter;
5432
5433out:
5434 mutex_unlock(&mqp->mutex);
5435 return err;
5436}
Ubuntu Hirsute Linux kernel mirror