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Linux 5.9-rc2
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
d14133dd 37#include <rdma/rdma_counter.h>
c2e53b2c 38#include <linux/mlx5/fs.h>
e126ba97 39#include "mlx5_ib.h"
b96c9dde 40#include "ib_rep.h"
64825827 41#include "counters.h"
443c1cf9 42#include "cmd.h"
333fbaa0 43#include "qp.h"
029e88fd 44#include "wr.h"
e126ba97 45
e126ba97
EC		 46enum {
47 MLX5_IB_ACK_REQ_FREQ = 8,
48};
49
50enum {
51 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
52 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
53 MLX5_IB_LINK_TYPE_IB = 0,
54 MLX5_IB_LINK_TYPE_ETH = 1
55};
56
eb49ab0c
AV		 57enum raw_qp_set_mask_map {
58 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 59 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 60};
61
0680efa2
AV		 62struct mlx5_modify_raw_qp_param {
63 u16 operation;
eb49ab0c
AV		 64
65 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 66
67 struct mlx5_rate_limit rl;
68
eb49ab0c 69 u8 rq_q_ctr_id;
d5ed8ac3 70 u16 port;
0680efa2
AV		 71};
72
89ea94a7
MG		 73static void get_cqs(enum ib_qp_type qp_type,
74 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
75 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
76
e126ba97
EC		 77static int is_qp0(enum ib_qp_type qp_type)
78{
79 return qp_type == IB_QPT_SMI;
80}
81
e126ba97
EC		 82static int is_sqp(enum ib_qp_type qp_type)
83{
84 return is_qp0(qp_type) || is_qp1(qp_type);
85}
86
c1395a2a 87/**
fbeb4075
MS		 88 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
89 * to kernel buffer
c1395a2a 90 *
fbeb4075
MS		 91 * @umem: User space memory where the WQ is
92 * @buffer: buffer to copy to
93 * @buflen: buffer length
94 * @wqe_index: index of WQE to copy from
95 * @wq_offset: offset to start of WQ
96 * @wq_wqe_cnt: number of WQEs in WQ
97 * @wq_wqe_shift: log2 of WQE size
98 * @bcnt: number of bytes to copy
99 * @bytes_copied: number of bytes to copy (return value)
c1395a2a 100 *
fbeb4075
MS		 101 * Copies from start of WQE bcnt or less bytes.
102 * Does not gurantee to copy the entire WQE.
c1395a2a 103 *
fbeb4075 104 * Return: zero on success, or an error code.
c1395a2a 105 */
da9ee9d8
MS		 106static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, void *buffer,
107 size_t buflen, int wqe_index,
108 int wq_offset, int wq_wqe_cnt,
109 int wq_wqe_shift, int bcnt,
fbeb4075 110 size_t *bytes_copied)
c1395a2a 111{
fbeb4075
MS		 112 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
113 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
114 size_t copy_length;
c1395a2a
HE		 115 int ret;
116
fbeb4075
MS		 117 /* don't copy more than requested, more than buffer length or
118 * beyond WQ end
119 */
120 copy_length = min_t(u32, buflen, wq_end - offset);
121 copy_length = min_t(u32, copy_length, bcnt);
122
123 ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
124 if (ret)
125 return ret;
c1395a2a 126
fbeb4075
MS		 127 if (!ret && bytes_copied)
128 *bytes_copied = copy_length;
c1395a2a 129
fbeb4075
MS		 130 return 0;
131}
c1395a2a 132
da9ee9d8
MS		 133static int mlx5_ib_read_kernel_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
134 void *buffer, size_t buflen, size_t *bc)
135{
136 struct mlx5_wqe_ctrl_seg *ctrl;
137 size_t bytes_copied = 0;
138 size_t wqe_length;
139 void *p;
140 int ds;
141
142 wqe_index = wqe_index & qp->sq.fbc.sz_m1;
143
144 /* read the control segment first */
145 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
146 ctrl = p;
147 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
148 wqe_length = ds * MLX5_WQE_DS_UNITS;
149
150 /* read rest of WQE if it spreads over more than one stride */
151 while (bytes_copied < wqe_length) {
152 size_t copy_length =
153 min_t(size_t, buflen - bytes_copied, MLX5_SEND_WQE_BB);
154
155 if (!copy_length)
156 break;
157
158 memcpy(buffer + bytes_copied, p, copy_length);
159 bytes_copied += copy_length;
160
161 wqe_index = (wqe_index + 1) & qp->sq.fbc.sz_m1;
162 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, wqe_index);
163 }
164 *bc = bytes_copied;
165 return 0;
166}
167
168static int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index,
169 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 170{
171 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
172 struct ib_umem *umem = base->ubuffer.umem;
173 struct mlx5_ib_wq *wq = &qp->sq;
174 struct mlx5_wqe_ctrl_seg *ctrl;
175 size_t bytes_copied;
176 size_t bytes_copied2;
177 size_t wqe_length;
178 int ret;
179 int ds;
180
fbeb4075 181 /* at first read as much as possible */
da9ee9d8
MS		 182 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
183 wq->offset, wq->wqe_cnt,
184 wq->wqe_shift, buflen,
fbeb4075 185 &bytes_copied);
c1395a2a
HE		 186 if (ret)
187 return ret;
188
fbeb4075
MS		 189 /* we need at least control segment size to proceed */
190 if (bytes_copied < sizeof(*ctrl))
191 return -EINVAL;
192
193 ctrl = buffer;
194 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
195 wqe_length = ds * MLX5_WQE_DS_UNITS;
c1395a2a 196
fbeb4075
MS		 197 /* if we copied enough then we are done */
198 if (bytes_copied >= wqe_length) {
199 *bc = bytes_copied;
200 return 0;
c1395a2a
HE		 201 }
202
fbeb4075
MS		 203 /* otherwise this a wrapped around wqe
204 * so read the remaining bytes starting
205 * from wqe_index 0
206 */
da9ee9d8
MS		 207 ret = mlx5_ib_read_user_wqe_common(umem, buffer + bytes_copied,
208 buflen - bytes_copied, 0, wq->offset,
209 wq->wqe_cnt, wq->wqe_shift,
fbeb4075
MS		 210 wqe_length - bytes_copied,
211 &bytes_copied2);
212
213 if (ret)
214 return ret;
215 *bc = bytes_copied + bytes_copied2;
216 return 0;
217}
218
da9ee9d8
MS		 219int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
220 size_t buflen, size_t *bc)
221{
222 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
223 struct ib_umem *umem = base->ubuffer.umem;
224
225 if (buflen < sizeof(struct mlx5_wqe_ctrl_seg))
226 return -EINVAL;
227
228 if (!umem)
229 return mlx5_ib_read_kernel_wqe_sq(qp, wqe_index, buffer,
230 buflen, bc);
231
232 return mlx5_ib_read_user_wqe_sq(qp, wqe_index, buffer, buflen, bc);
233}
234
235static int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index,
236 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 237{
238 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
239 struct ib_umem *umem = base->ubuffer.umem;
240 struct mlx5_ib_wq *wq = &qp->rq;
241 size_t bytes_copied;
242 int ret;
243
da9ee9d8
MS		 244 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index,
245 wq->offset, wq->wqe_cnt,
246 wq->wqe_shift, buflen,
fbeb4075 247 &bytes_copied);
c1395a2a 248
c1395a2a
HE		 249 if (ret)
250 return ret;
fbeb4075
MS		 251 *bc = bytes_copied;
252 return 0;
253}
254
da9ee9d8
MS		 255int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
256 size_t buflen, size_t *bc)
257{
258 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
259 struct ib_umem *umem = base->ubuffer.umem;
260 struct mlx5_ib_wq *wq = &qp->rq;
261 size_t wqe_size = 1 << wq->wqe_shift;
262
263 if (buflen < wqe_size)
264 return -EINVAL;
265
266 if (!umem)
267 return -EOPNOTSUPP;
268
269 return mlx5_ib_read_user_wqe_rq(qp, wqe_index, buffer, buflen, bc);
270}
271
272static int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index,
273 void *buffer, size_t buflen, size_t *bc)
fbeb4075
MS		 274{
275 struct ib_umem *umem = srq->umem;
276 size_t bytes_copied;
277 int ret;
c1395a2a 278
da9ee9d8
MS		 279 ret = mlx5_ib_read_user_wqe_common(umem, buffer, buflen, wqe_index, 0,
280 srq->msrq.max, srq->msrq.wqe_shift,
281 buflen, &bytes_copied);
fbeb4075
MS		 282
283 if (ret)
284 return ret;
285 *bc = bytes_copied;
286 return 0;
c1395a2a
HE		 287}
288
da9ee9d8
MS		 289int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
290 size_t buflen, size_t *bc)
291{
292 struct ib_umem *umem = srq->umem;
293 size_t wqe_size = 1 << srq->msrq.wqe_shift;
294
295 if (buflen < wqe_size)
296 return -EINVAL;
297
298 if (!umem)
299 return -EOPNOTSUPP;
300
301 return mlx5_ib_read_user_wqe_srq(srq, wqe_index, buffer, buflen, bc);
302}
303
e126ba97
EC		 304static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
305{
306 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
307 struct ib_event event;
308
19098df2 309 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
310 /* This event is only valid for trans_qps */
311 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
312 }
e126ba97
EC		 313
314 if (ibqp->event_handler) {
315 event.device = ibqp->device;
316 event.element.qp = ibqp;
317 switch (type) {
318 case MLX5_EVENT_TYPE_PATH_MIG:
319 event.event = IB_EVENT_PATH_MIG;
320 break;
321 case MLX5_EVENT_TYPE_COMM_EST:
322 event.event = IB_EVENT_COMM_EST;
323 break;
324 case MLX5_EVENT_TYPE_SQ_DRAINED:
325 event.event = IB_EVENT_SQ_DRAINED;
326 break;
327 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
328 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
329 break;
330 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
331 event.event = IB_EVENT_QP_FATAL;
332 break;
333 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
334 event.event = IB_EVENT_PATH_MIG_ERR;
335 break;
336 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
337 event.event = IB_EVENT_QP_REQ_ERR;
338 break;
339 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
340 event.event = IB_EVENT_QP_ACCESS_ERR;
341 break;
342 default:
343 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
344 return;
345 }
346
347 ibqp->event_handler(&event, ibqp->qp_context);
348 }
349}
350
351static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
352 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
353{
354 int wqe_size;
355 int wq_size;
356
357 /* Sanity check RQ size before proceeding */
938fe83c 358 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 359 return -EINVAL;
360
361 if (!has_rq) {
362 qp->rq.max_gs = 0;
363 qp->rq.wqe_cnt = 0;
364 qp->rq.wqe_shift = 0;
0540d814
NO		 365 cap->max_recv_wr = 0;
366 cap->max_recv_sge = 0;
e126ba97 367 } else {
c95e6d53
LR		 368 int wq_sig = !!(qp->flags_en & MLX5_QP_FLAG_SIGNATURE);
369
e126ba97
EC		 370 if (ucmd) {
371 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
002bf228
LR		 372 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
373 return -EINVAL;
e126ba97 374 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
c95e6d53
LR		 375 if ((1 << qp->rq.wqe_shift) /
376 sizeof(struct mlx5_wqe_data_seg) <
377 wq_sig)
002bf228 378 return -EINVAL;
c95e6d53
LR		 379 qp->rq.max_gs =
380 (1 << qp->rq.wqe_shift) /
381 sizeof(struct mlx5_wqe_data_seg) -
382 wq_sig;
e126ba97
EC		 383 qp->rq.max_post = qp->rq.wqe_cnt;
384 } else {
c95e6d53
LR		 385 wqe_size =
386 wq_sig ? sizeof(struct mlx5_wqe_signature_seg) :
387 0;
e126ba97
EC		 388 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
389 wqe_size = roundup_pow_of_two(wqe_size);
390 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
391 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
392 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 394 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
395 wqe_size,
938fe83c
SM		 396 MLX5_CAP_GEN(dev->mdev,
397 max_wqe_sz_rq));
e126ba97
EC		 398 return -EINVAL;
399 }
400 qp->rq.wqe_shift = ilog2(wqe_size);
c95e6d53
LR		 401 qp->rq.max_gs =
402 (1 << qp->rq.wqe_shift) /
403 sizeof(struct mlx5_wqe_data_seg) -
404 wq_sig;
e126ba97
EC		 405 qp->rq.max_post = qp->rq.wqe_cnt;
406 }
407 }
408
409 return 0;
410}
411
f0313965 412static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 413{
618af384 414 int size = 0;
e126ba97 415
f0313965 416 switch (attr->qp_type) {
e126ba97 417 case IB_QPT_XRC_INI:
b125a54b 418 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 419 /* fall through */
420 case IB_QPT_RC:
421 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 422 max(sizeof(struct mlx5_wqe_atomic_seg) +
423 sizeof(struct mlx5_wqe_raddr_seg),
424 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
064e5262
IB		 425 sizeof(struct mlx5_mkey_seg) +
426 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
427 MLX5_IB_UMR_OCTOWORD);
e126ba97
EC		 428 break;
429
b125a54b
EC		 430 case IB_QPT_XRC_TGT:
431 return 0;
432
e126ba97 433 case IB_QPT_UC:
b125a54b 434 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 435 max(sizeof(struct mlx5_wqe_raddr_seg),
436 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
437 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 438 break;
439
440 case IB_QPT_UD:
f0313965
ES		 441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
442 size += sizeof(struct mlx5_wqe_eth_pad) +
443 sizeof(struct mlx5_wqe_eth_seg);
444 /* fall through */
e126ba97 445 case IB_QPT_SMI:
d16e91da 446 case MLX5_IB_QPT_HW_GSI:
b125a54b 447 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 448 sizeof(struct mlx5_wqe_datagram_seg);
449 break;
450
451 case MLX5_IB_QPT_REG_UMR:
b125a54b 452 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 453 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
454 sizeof(struct mlx5_mkey_seg);
455 break;
456
457 default:
458 return -EINVAL;
459 }
460
461 return size;
462}
463
464static int calc_send_wqe(struct ib_qp_init_attr *attr)
465{
466 int inl_size = 0;
467 int size;
468
f0313965 469 size = sq_overhead(attr);
e126ba97
EC		 470 if (size < 0)
471 return size;
472
473 if (attr->cap.max_inline_data) {
474 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
475 attr->cap.max_inline_data;
476 }
477
478 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
c0a6cbb9 479 if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN &&
e1e66cc2 480 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
c0a6cbb9 481 return MLX5_SIG_WQE_SIZE;
e1e66cc2
SG		 482 else
483 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 484}
485
288c01b7
EC		 486static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
487{
488 int max_sge;
489
490 if (attr->qp_type == IB_QPT_RC)
491 max_sge = (min_t(int, wqe_size, 512) -
492 sizeof(struct mlx5_wqe_ctrl_seg) -
493 sizeof(struct mlx5_wqe_raddr_seg)) /
494 sizeof(struct mlx5_wqe_data_seg);
495 else if (attr->qp_type == IB_QPT_XRC_INI)
496 max_sge = (min_t(int, wqe_size, 512) -
497 sizeof(struct mlx5_wqe_ctrl_seg) -
498 sizeof(struct mlx5_wqe_xrc_seg) -
499 sizeof(struct mlx5_wqe_raddr_seg)) /
500 sizeof(struct mlx5_wqe_data_seg);
501 else
502 max_sge = (wqe_size - sq_overhead(attr)) /
503 sizeof(struct mlx5_wqe_data_seg);
504
505 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
506 sizeof(struct mlx5_wqe_data_seg));
507}
508
e126ba97
EC		 509static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
510 struct mlx5_ib_qp *qp)
511{
512 int wqe_size;
513 int wq_size;
514
515 if (!attr->cap.max_send_wr)
516 return 0;
517
518 wqe_size = calc_send_wqe(attr);
519 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
520 if (wqe_size < 0)
521 return wqe_size;
522
938fe83c 523 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 524 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 525 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 526 return -EINVAL;
527 }
528
f0313965
ES		 529 qp->max_inline_data = wqe_size - sq_overhead(attr) -
530 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 531 attr->cap.max_inline_data = qp->max_inline_data;
532
533 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
534 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 535 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 536 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
537 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 538 qp->sq.wqe_cnt,
539 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 540 return -ENOMEM;
541 }
e126ba97 542 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 543 qp->sq.max_gs = get_send_sge(attr, wqe_size);
544 if (qp->sq.max_gs < attr->cap.max_send_sge)
545 return -ENOMEM;
546
547 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 548 qp->sq.max_post = wq_size / wqe_size;
549 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 550
551 return wq_size;
552}
553
554static int set_user_buf_size(struct mlx5_ib_dev *dev,
555 struct mlx5_ib_qp *qp,
19098df2 556 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 557 struct mlx5_ib_qp_base *base,
558 struct ib_qp_init_attr *attr)
e126ba97
EC		 559{
560 int desc_sz = 1 << qp->sq.wqe_shift;
561
938fe83c 562 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 563 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 564 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 565 return -EINVAL;
566 }
567
af8b38ed
GP		 568 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
569 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
570 ucmd->sq_wqe_count);
e126ba97
EC		 571 return -EINVAL;
572 }
573
574 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
575
938fe83c 576 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 577 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 578 qp->sq.wqe_cnt,
579 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 580 return -EINVAL;
581 }
582
c2e53b2c 583 if (attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 584 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0fb2ed66 585 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
586 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
587 } else {
588 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
589 (qp->sq.wqe_cnt << 6);
590 }
e126ba97
EC		 591
592 return 0;
593}
594
595static int qp_has_rq(struct ib_qp_init_attr *attr)
596{
597 if (attr->qp_type == IB_QPT_XRC_INI ||
598 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
599 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
600 !attr->cap.max_recv_wr)
601 return 0;
602
603 return 1;
604}
605
0b80c14f
EC		 606enum {
607 /* this is the first blue flame register in the array of bfregs assigned
608 * to a processes. Since we do not use it for blue flame but rather
609 * regular 64 bit doorbells, we do not need a lock for maintaiing
610 * "odd/even" order
611 */
612 NUM_NON_BLUE_FLAME_BFREGS = 1,
613};
614
b037c29a
EC		 615static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
616{
31a78a5a 617 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 618}
619
620static int num_med_bfreg(struct mlx5_ib_dev *dev,
621 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 622{
623 int n;
624
b037c29a
EC		 625 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
626 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 627
628 return n >= 0 ? n : 0;
629}
630
18b0362e
YH		 631static int first_med_bfreg(struct mlx5_ib_dev *dev,
632 struct mlx5_bfreg_info *bfregi)
633{
634 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
635}
636
b037c29a
EC		 637static int first_hi_bfreg(struct mlx5_ib_dev *dev,
638 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 639{
640 int med;
c1be5232 641
b037c29a
EC		 642 med = num_med_bfreg(dev, bfregi);
643 return ++med;
c1be5232
EC		 644}
645
b037c29a
EC		 646static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
647 struct mlx5_bfreg_info *bfregi)
e126ba97 648{
e126ba97
EC		 649 int i;
650
b037c29a
EC		 651 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
652 if (!bfregi->count[i]) {
2f5ff264 653 bfregi->count[i]++;
e126ba97
EC		 654 return i;
655 }
656 }
657
658 return -ENOMEM;
659}
660
b037c29a
EC		 661static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
662 struct mlx5_bfreg_info *bfregi)
e126ba97 663{
18b0362e 664 int minidx = first_med_bfreg(dev, bfregi);
e126ba97
EC		 665 int i;
666
18b0362e
YH		 667 if (minidx < 0)
668 return minidx;
669
670 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 671 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 672 minidx = i;
0b80c14f
EC		 673 if (!bfregi->count[minidx])
674 break;
e126ba97
EC		 675 }
676
2f5ff264 677 bfregi->count[minidx]++;
e126ba97
EC		 678 return minidx;
679}
680
b037c29a 681static int alloc_bfreg(struct mlx5_ib_dev *dev,
ffaf58de 682 struct mlx5_bfreg_info *bfregi)
e126ba97 683{
ffaf58de 684 int bfregn = -ENOMEM;
e126ba97 685
0a2fd01c
YH		 686 if (bfregi->lib_uar_dyn)
687 return -EINVAL;
688
2f5ff264 689 mutex_lock(&bfregi->lock);
ffaf58de
LR		 690 if (bfregi->ver >= 2) {
691 bfregn = alloc_high_class_bfreg(dev, bfregi);
692 if (bfregn < 0)
693 bfregn = alloc_med_class_bfreg(dev, bfregi);
694 }
695
696 if (bfregn < 0) {
0b80c14f 697 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 698 bfregn = 0;
699 bfregi->count[bfregn]++;
e126ba97 700 }
2f5ff264 701 mutex_unlock(&bfregi->lock);
e126ba97 702
2f5ff264 703 return bfregn;
e126ba97
EC		 704}
705
4ed131d0 706void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 707{
2f5ff264 708 mutex_lock(&bfregi->lock);
b037c29a 709 bfregi->count[bfregn]--;
2f5ff264 710 mutex_unlock(&bfregi->lock);
e126ba97
EC		 711}
712
713static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
714{
715 switch (state) {
716 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
717 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
718 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
719 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
720 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
721 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
722 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
723 default: return -1;
724 }
725}
726
727static int to_mlx5_st(enum ib_qp_type type)
728{
729 switch (type) {
730 case IB_QPT_RC: return MLX5_QP_ST_RC;
731 case IB_QPT_UC: return MLX5_QP_ST_UC;
732 case IB_QPT_UD: return MLX5_QP_ST_UD;
733 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
734 case IB_QPT_XRC_INI:
735 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
736 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 737 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 738 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
3ae7e66a 739 case IB_QPT_RAW_PACKET: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 740 default: return -EINVAL;
741 }
742}
743
89ea94a7
MG		 744static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
745 struct mlx5_ib_cq *recv_cq);
746static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
747 struct mlx5_ib_cq *recv_cq);
748
7c043e90 749int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
05f58ceb 750 struct mlx5_bfreg_info *bfregi, u32 bfregn,
7c043e90 751 bool dyn_bfreg)
e126ba97 752{
05f58ceb
LR		 753 unsigned int bfregs_per_sys_page;
754 u32 index_of_sys_page;
755 u32 offset;
b037c29a 756
0a2fd01c
YH		 757 if (bfregi->lib_uar_dyn)
758 return -EINVAL;
759
b037c29a
EC		 760 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
761 MLX5_NON_FP_BFREGS_PER_UAR;
762 index_of_sys_page = bfregn / bfregs_per_sys_page;
763
1ee47ab3
YH		 764 if (dyn_bfreg) {
765 index_of_sys_page += bfregi->num_static_sys_pages;
05f58ceb
LR		 766
767 if (index_of_sys_page >= bfregi->num_sys_pages)
768 return -EINVAL;
769
1ee47ab3
YH		 770 if (bfregn > bfregi->num_dyn_bfregs ||
771 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
772 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
773 return -EINVAL;
774 }
775 }
b037c29a 776
1ee47ab3 777 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 778 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 779}
780
b0ea0fa5 781static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
19098df2 782 unsigned long addr, size_t size,
b0ea0fa5
JG		 783 struct ib_umem **umem, int *npages, int *page_shift,
784 int *ncont, u32 *offset)
19098df2 785{
786 int err;
787
c320e527 788 *umem = ib_umem_get(&dev->ib_dev, addr, size, 0);
19098df2 789 if (IS_ERR(*umem)) {
790 mlx5_ib_dbg(dev, "umem_get failed\n");
791 return PTR_ERR(*umem);
792 }
793
762f899a 794 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 795
796 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
797 if (err) {
798 mlx5_ib_warn(dev, "bad offset\n");
799 goto err_umem;
800 }
801
802 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
803 addr, size, *npages, *page_shift, *ncont, *offset);
804
805 return 0;
806
807err_umem:
808 ib_umem_release(*umem);
809 *umem = NULL;
810
811 return err;
812}
813
fe248c3a 814static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
bdeacabd 815 struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
79b20a6c 816{
bdeacabd
SR		 817 struct mlx5_ib_ucontext *context =
818 rdma_udata_to_drv_context(
819 udata,
820 struct mlx5_ib_ucontext,
821 ibucontext);
79b20a6c 822
fe248c3a
MG		 823 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
824 atomic_dec(&dev->delay_drop.rqs_cnt);
825
79b20a6c 826 mlx5_ib_db_unmap_user(context, &rwq->db);
836a0fbb 827 ib_umem_release(rwq->umem);
79b20a6c
YH		 828}
829
830static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
b0ea0fa5 831 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
79b20a6c
YH		 832 struct mlx5_ib_create_wq *ucmd)
833{
89944450
SR		 834 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
835 udata, struct mlx5_ib_ucontext, ibucontext);
79b20a6c
YH		 836 int page_shift = 0;
837 int npages;
838 u32 offset = 0;
839 int ncont = 0;
840 int err;
841
842 if (!ucmd->buf_addr)
843 return -EINVAL;
844
c320e527 845 rwq->umem = ib_umem_get(&dev->ib_dev, ucmd->buf_addr, rwq->buf_size, 0);
79b20a6c
YH		 846 if (IS_ERR(rwq->umem)) {
847 mlx5_ib_dbg(dev, "umem_get failed\n");
848 err = PTR_ERR(rwq->umem);
849 return err;
850 }
851
762f899a 852 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 853 &ncont, NULL);
854 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
855 &rwq->rq_page_offset);
856 if (err) {
857 mlx5_ib_warn(dev, "bad offset\n");
858 goto err_umem;
859 }
860
861 rwq->rq_num_pas = ncont;
862 rwq->page_shift = page_shift;
863 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
864 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
865
866 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
867 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
868 npages, page_shift, ncont, offset);
869
89944450 870 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
79b20a6c
YH		 871 if (err) {
872 mlx5_ib_dbg(dev, "map failed\n");
873 goto err_umem;
874 }
875
79b20a6c
YH		 876 return 0;
877
878err_umem:
879 ib_umem_release(rwq->umem);
880 return err;
881}
882
b037c29a
EC		 883static int adjust_bfregn(struct mlx5_ib_dev *dev,
884 struct mlx5_bfreg_info *bfregi, int bfregn)
885{
886 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
887 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
888}
889
98fc1126
LR		 890static int _create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
891 struct mlx5_ib_qp *qp, struct ib_udata *udata,
892 struct ib_qp_init_attr *attr, u32 **in,
893 struct mlx5_ib_create_qp_resp *resp, int *inlen,
894 struct mlx5_ib_qp_base *base,
895 struct mlx5_ib_create_qp *ucmd)
e126ba97
EC		 896{
897 struct mlx5_ib_ucontext *context;
19098df2 898 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 899 int page_shift = 0;
1ee47ab3 900 int uar_index = 0;
e126ba97 901 int npages;
9e9c47d0 902 u32 offset = 0;
2f5ff264 903 int bfregn;
9e9c47d0 904 int ncont = 0;
09a7d9ec
SM		 905 __be64 *pas;
906 void *qpc;
e126ba97 907 int err;
5aa3771d 908 u16 uid;
ac42a5ee 909 u32 uar_flags;
e126ba97 910
89944450
SR		 911 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
912 ibucontext);
76883a6c
LR		 913 uar_flags = qp->flags_en &
914 (MLX5_QP_FLAG_UAR_PAGE_INDEX | MLX5_QP_FLAG_BFREG_INDEX);
ac42a5ee
YH		 915 switch (uar_flags) {
916 case MLX5_QP_FLAG_UAR_PAGE_INDEX:
76883a6c 917 uar_index = ucmd->bfreg_index;
ac42a5ee
YH		 918 bfregn = MLX5_IB_INVALID_BFREG;
919 break;
920 case MLX5_QP_FLAG_BFREG_INDEX:
1ee47ab3 921 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
76883a6c 922 ucmd->bfreg_index, true);
1ee47ab3
YH		 923 if (uar_index < 0)
924 return uar_index;
1ee47ab3 925 bfregn = MLX5_IB_INVALID_BFREG;
ac42a5ee
YH		 926 break;
927 case 0:
2be08c30 928 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
ac42a5ee 929 return -EINVAL;
ffaf58de
LR		 930 bfregn = alloc_bfreg(dev, &context->bfregi);
931 if (bfregn < 0)
932 return bfregn;
ac42a5ee
YH		 933 break;
934 default:
935 return -EINVAL;
e126ba97
EC		 936 }
937
2f5ff264 938 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 939 if (bfregn != MLX5_IB_INVALID_BFREG)
940 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
941 false);
e126ba97 942
48fea837
HE		 943 qp->rq.offset = 0;
944 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
945 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
946
76883a6c 947 err = set_user_buf_size(dev, qp, ucmd, base, attr);
e126ba97 948 if (err)
2f5ff264 949 goto err_bfreg;
e126ba97 950
76883a6c
LR		 951 if (ucmd->buf_addr && ubuffer->buf_size) {
952 ubuffer->buf_addr = ucmd->buf_addr;
b0ea0fa5
JG		 953 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
954 ubuffer->buf_size, &ubuffer->umem,
955 &npages, &page_shift, &ncont, &offset);
19098df2 956 if (err)
2f5ff264 957 goto err_bfreg;
9e9c47d0 958 } else {
19098df2 959 ubuffer->umem = NULL;
e126ba97 960 }
e126ba97 961
09a7d9ec
SM		 962 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
963 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 964 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 965 if (!*in) {
966 err = -ENOMEM;
967 goto err_umem;
968 }
09a7d9ec 969
04bcc1c2 970 uid = (attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
5aa3771d 971 MLX5_SET(create_qp_in, *in, uid, uid);
09a7d9ec 972 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 973 if (ubuffer->umem)
09a7d9ec
SM		 974 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
975
976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
977
978 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
979 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 980
09a7d9ec 981 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 982 if (bfregn != MLX5_IB_INVALID_BFREG)
983 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
984 else
985 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 986 qp->bfregn = bfregn;
e126ba97 987
76883a6c 988 err = mlx5_ib_db_map_user(context, udata, ucmd->db_addr, &qp->db);
e126ba97
EC		 989 if (err) {
990 mlx5_ib_dbg(dev, "map failed\n");
991 goto err_free;
992 }
993
e126ba97
EC		 994 return 0;
995
e126ba97 996err_free:
479163f4 997 kvfree(*in);
e126ba97
EC		 998
999err_umem:
836a0fbb 1000 ib_umem_release(ubuffer->umem);
e126ba97 1001
2f5ff264 1002err_bfreg:
1ee47ab3
YH		 1003 if (bfregn != MLX5_IB_INVALID_BFREG)
1004 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 1005 return err;
1006}
1007
747c519c
LR		 1008static void destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1009 struct mlx5_ib_qp_base *base, struct ib_udata *udata)
e126ba97 1010{
747c519c
LR		 1011 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1012 udata, struct mlx5_ib_ucontext, ibucontext);
e126ba97 1013
747c519c
LR		 1014 if (udata) {
1015 /* User QP */
1016 mlx5_ib_db_unmap_user(context, &qp->db);
1017 ib_umem_release(base->ubuffer.umem);
1018
1019 /*
1020 * Free only the BFREGs which are handled by the kernel.
1021 * BFREGs of UARs allocated dynamically are handled by user.
1022 */
1023 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1024 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
1025 return;
1026 }
1ee47ab3 1027
747c519c
LR		 1028 /* Kernel QP */
1029 kvfree(qp->sq.wqe_head);
1030 kvfree(qp->sq.w_list);
1031 kvfree(qp->sq.wrid);
1032 kvfree(qp->sq.wr_data);
1033 kvfree(qp->rq.wrid);
1034 if (qp->db.db)
1035 mlx5_db_free(dev->mdev, &qp->db);
1036 if (qp->buf.frags)
1037 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1038}
1039
98fc1126
LR		 1040static int _create_kernel_qp(struct mlx5_ib_dev *dev,
1041 struct ib_qp_init_attr *init_attr,
1042 struct mlx5_ib_qp *qp, u32 **in, int *inlen,
1043 struct mlx5_ib_qp_base *base)
e126ba97 1044{
e126ba97 1045 int uar_index;
09a7d9ec 1046 void *qpc;
e126ba97
EC		 1047 int err;
1048
e126ba97 1049 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0 1050 qp->bf.bfreg = &dev->fp_bfreg;
2978975c 1051 else if (qp->flags & MLX5_IB_QP_CREATE_WC_TEST)
11f552e2 1052 qp->bf.bfreg = &dev->wc_bfreg;
5fe9dec0
EC		 1053 else
1054 qp->bf.bfreg = &dev->bfreg;
e126ba97 1055
d8030b0d
EC		 1056 /* We need to divide by two since each register is comprised of
1057 * two buffers of identical size, namely odd and even
1058 */
1059 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 1060 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 1061
1062 err = calc_sq_size(dev, init_attr, qp);
1063 if (err < 0) {
1064 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 1065 return err;
e126ba97
EC		 1066 }
1067
1068 qp->rq.offset = 0;
1069 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 1070 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 1071
34f4c955
GL		 1072 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1073 &qp->buf, dev->mdev->priv.numa_node);
e126ba97
EC		 1074 if (err) {
1075 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 1076 return err;
e126ba97
EC		 1077 }
1078
34f4c955
GL		 1079 if (qp->rq.wqe_cnt)
1080 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1081 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1082
1083 if (qp->sq.wqe_cnt) {
1084 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
1085 MLX5_SEND_WQE_BB;
1086 mlx5_init_fbc_offset(qp->buf.frags +
1087 (qp->sq.offset / PAGE_SIZE),
1088 ilog2(MLX5_SEND_WQE_BB),
1089 ilog2(qp->sq.wqe_cnt),
1090 sq_strides_offset, &qp->sq.fbc);
1091
1092 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1093 }
1094
09a7d9ec
SM		 1095 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1096 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 1097 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 1098 if (!*in) {
1099 err = -ENOMEM;
1100 goto err_buf;
1101 }
09a7d9ec
SM		 1102
1103 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1104 MLX5_SET(qpc, qpc, uar_page, uar_index);
1105 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1106
e126ba97 1107 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 1108 MLX5_SET(qpc, qpc, fre, 1);
1109 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 1110
2978975c 1111 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
09a7d9ec 1112 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c 1113
34f4c955
GL		 1114 mlx5_fill_page_frag_array(&qp->buf,
1115 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1116 *in, pas));
e126ba97 1117
9603b61d 1118 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 1119 if (err) {
1120 mlx5_ib_dbg(dev, "err %d\n", err);
1121 goto err_free;
1122 }
1123
b5883008
LD		 1124 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1125 sizeof(*qp->sq.wrid), GFP_KERNEL);
1126 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1127 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1128 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1129 sizeof(*qp->rq.wrid), GFP_KERNEL);
1130 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1131 sizeof(*qp->sq.w_list), GFP_KERNEL);
1132 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1133 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1134
1135 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1136 !qp->sq.w_list || !qp->sq.wqe_head) {
1137 err = -ENOMEM;
1138 goto err_wrid;
1139 }
e126ba97
EC		 1140
1141 return 0;
1142
1143err_wrid:
b5883008
LD		 1144 kvfree(qp->sq.wqe_head);
1145 kvfree(qp->sq.w_list);
1146 kvfree(qp->sq.wrid);
1147 kvfree(qp->sq.wr_data);
1148 kvfree(qp->rq.wrid);
f4044dac 1149 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1150
1151err_free:
479163f4 1152 kvfree(*in);
e126ba97
EC		 1153
1154err_buf:
34f4c955 1155 mlx5_frag_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1156 return err;
1157}
1158
09a7d9ec 1159static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97 1160{
7aede1a2
LR		 1161 if (attr->srq || (qp->type == IB_QPT_XRC_TGT) ||
1162 (qp->type == MLX5_IB_QPT_DCI) || (qp->type == IB_QPT_XRC_INI))
09a7d9ec 1163 return MLX5_SRQ_RQ;
e126ba97 1164 else if (!qp->has_rq)
09a7d9ec 1165 return MLX5_ZERO_LEN_RQ;
7aede1a2
LR		 1166
1167 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1168}
1169
0fb2ed66 1170static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1171 struct mlx5_ib_qp *qp,
1cd6dbd3
YH		 1172 struct mlx5_ib_sq *sq, u32 tdn,
1173 struct ib_pd *pd)
0fb2ed66 1174{
e0b4b472 1175 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
0fb2ed66 1176 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1177
1cd6dbd3 1178 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1179 MLX5_SET(tisc, tisc, transport_domain, tdn);
2be08c30 1180 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
c2e53b2c
YH		 1181 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1182
e0b4b472 1183 return mlx5_core_create_tis(dev->mdev, in, &sq->tisn);
0fb2ed66 1184}
1185
1186static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1cd6dbd3 1187 struct mlx5_ib_sq *sq, struct ib_pd *pd)
0fb2ed66 1188{
1cd6dbd3 1189 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
0fb2ed66 1190}
1191
d5ed8ac3 1192static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
b96c9dde
MB		 1193{
1194 if (sq->flow_rule)
1195 mlx5_del_flow_rules(sq->flow_rule);
d5ed8ac3 1196 sq->flow_rule = NULL;
b96c9dde
MB		 1197}
1198
0fb2ed66 1199static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
b0ea0fa5 1200 struct ib_udata *udata,
0fb2ed66 1201 struct mlx5_ib_sq *sq, void *qpin,
1202 struct ib_pd *pd)
1203{
1204 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1205 __be64 *pas;
1206 void *in;
1207 void *sqc;
1208 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1209 void *wq;
1210 int inlen;
1211 int err;
1212 int page_shift = 0;
1213 int npages;
1214 int ncont = 0;
1215 u32 offset = 0;
1216
b0ea0fa5
JG		 1217 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1218 &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1219 &offset);
0fb2ed66 1220 if (err)
1221 return err;
1222
1223 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1224 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1225 if (!in) {
1226 err = -ENOMEM;
1227 goto err_umem;
1228 }
1229
c14003f0 1230 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1231 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1232 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1233 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1234 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1235 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1236 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1237 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1238 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1239 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1240 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1241 MLX5_CAP_ETH(dev->mdev, swp))
1242 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1243
1244 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1245 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1246 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1247 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1248 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1249 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1250 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1251 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1252 MLX5_SET(wq, wq, page_offset, offset);
1253
1254 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1255 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1256
333fbaa0 1257 err = mlx5_core_create_sq_tracked(dev, in, inlen, &sq->base.mqp);
0fb2ed66 1258
1259 kvfree(in);
1260
1261 if (err)
1262 goto err_umem;
1263
1264 return 0;
1265
1266err_umem:
1267 ib_umem_release(sq->ubuffer.umem);
1268 sq->ubuffer.umem = NULL;
1269
1270 return err;
1271}
1272
1273static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1274 struct mlx5_ib_sq *sq)
1275{
d5ed8ac3 1276 destroy_flow_rule_vport_sq(sq);
333fbaa0 1277 mlx5_core_destroy_sq_tracked(dev, &sq->base.mqp);
0fb2ed66 1278 ib_umem_release(sq->ubuffer.umem);
1279}
1280
2c292dbb 1281static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1282{
1283 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1284 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1285 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1286 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1287 u32 po_quanta = 1 << (log_page_size - 6);
1288 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1289 u32 page_size = 1 << log_page_size;
1290 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1291 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1292
1293 return rq_num_pas * sizeof(u64);
1294}
1295
1296static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb 1297 struct mlx5_ib_rq *rq, void *qpin,
34d57585 1298 size_t qpinlen, struct ib_pd *pd)
0fb2ed66 1299{
358e42ea 1300 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1301 __be64 *pas;
1302 __be64 *qp_pas;
1303 void *in;
1304 void *rqc;
1305 void *wq;
1306 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1307 size_t rq_pas_size = get_rq_pas_size(qpc);
1308 size_t inlen;
0fb2ed66 1309 int err;
2c292dbb
BP		 1310
1311 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1312 return -EINVAL;
0fb2ed66 1313
1314 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1315 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1316 if (!in)
1317 return -ENOMEM;
1318
34d57585 1319 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1320 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1321 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1322 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1323 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1324 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1325 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1326 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1327 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1328
2be08c30 1329 if (mqp->flags & IB_QP_CREATE_SCATTER_FCS)
358e42ea
MD		 1330 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1331
0fb2ed66 1332 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1333 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1334 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1335 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1336 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1337 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1338 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1339 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1340 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1341 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1342
1343 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1344 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1345 memcpy(pas, qp_pas, rq_pas_size);
1346
333fbaa0 1347 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rq->base.mqp);
0fb2ed66 1348
1349 kvfree(in);
1350
1351 return err;
1352}
1353
1354static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1355 struct mlx5_ib_rq *rq)
1356{
333fbaa0 1357 mlx5_core_destroy_rq_tracked(dev, &rq->base.mqp);
0fb2ed66 1358}
1359
0042f9e4
MB		 1360static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1361 struct mlx5_ib_rq *rq,
443c1cf9
YH		 1362 u32 qp_flags_en,
1363 struct ib_pd *pd)
0042f9e4
MB		 1364{
1365 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1366 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1367 mlx5_ib_disable_lb(dev, false, true);
443c1cf9 1368 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
0042f9e4
MB		 1369}
1370
0fb2ed66 1371static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb 1372 struct mlx5_ib_rq *rq, u32 tdn,
e0b4b472
LR		 1373 u32 *qp_flags_en, struct ib_pd *pd,
1374 u32 *out)
0fb2ed66 1375{
175edba8 1376 u8 lb_flag = 0;
0fb2ed66 1377 u32 *in;
1378 void *tirc;
1379 int inlen;
1380 int err;
1381
1382 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1383 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1384 if (!in)
1385 return -ENOMEM;
1386
443c1cf9 1387 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
0fb2ed66 1388 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1389 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1390 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1391 MLX5_SET(tirc, tirc, transport_domain, tdn);
175edba8 1392 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb 1393 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1394
175edba8
MB		 1395 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1396 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1397
1398 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1399 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1400
6a4d00be 1401 if (dev->is_rep) {
175edba8
MB		 1402 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1403 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1404 }
1405
1406 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
e0b4b472
LR		 1407 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1408 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
1f1d6abb 1409 rq->tirn = MLX5_GET(create_tir_out, out, tirn);
0042f9e4
MB		 1410 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1411 err = mlx5_ib_enable_lb(dev, false, true);
1412
1413 if (err)
443c1cf9 1414 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
0042f9e4 1415 }
0fb2ed66 1416 kvfree(in);
1417
1418 return err;
1419}
1420
0fb2ed66 1421static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1422 u32 *in, size_t inlen,
7f72052c
YH		 1423 struct ib_pd *pd,
1424 struct ib_udata *udata,
1425 struct mlx5_ib_create_qp_resp *resp)
0fb2ed66 1426{
1427 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1428 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1429 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
89944450
SR		 1430 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1431 udata, struct mlx5_ib_ucontext, ibucontext);
0fb2ed66 1432 int err;
1433 u32 tdn = mucontext->tdn;
7f72052c 1434 u16 uid = to_mpd(pd)->uid;
1f1d6abb 1435 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {};
0fb2ed66 1436
0eacc574
AL		 1437 if (!qp->sq.wqe_cnt && !qp->rq.wqe_cnt)
1438 return -EINVAL;
0fb2ed66 1439 if (qp->sq.wqe_cnt) {
1cd6dbd3 1440 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
0fb2ed66 1441 if (err)
1442 return err;
1443
b0ea0fa5 1444 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
0fb2ed66 1445 if (err)
1446 goto err_destroy_tis;
1447
7f72052c
YH		 1448 if (uid) {
1449 resp->tisn = sq->tisn;
1450 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1451 resp->sqn = sq->base.mqp.qpn;
1452 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1453 }
1454
0fb2ed66 1455 sq->base.container_mibqp = qp;
1d31e9c0 1456 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1457 }
1458
1459 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1460 rq->base.container_mibqp = qp;
1461
2be08c30 1462 if (qp->flags & IB_QP_CREATE_CVLAN_STRIPPING)
e4cc4fa7 1463 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
2be08c30 1464 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING)
b1383aa6 1465 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
34d57585 1466 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
0fb2ed66 1467 if (err)
1468 goto err_destroy_sq;
1469
e0b4b472
LR		 1470 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd,
1471 out);
0fb2ed66 1472 if (err)
1473 goto err_destroy_rq;
7f72052c
YH		 1474
1475 if (uid) {
1476 resp->rqn = rq->base.mqp.qpn;
1477 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1478 resp->tirn = rq->tirn;
1479 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1f1d6abb
AL		 1480 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
1481 resp->tir_icm_addr = MLX5_GET(
1482 create_tir_out, out, icm_address_31_0);
1483 resp->tir_icm_addr |=
1484 (u64)MLX5_GET(create_tir_out, out,
1485 icm_address_39_32)
1486 << 32;
1487 resp->tir_icm_addr |=
1488 (u64)MLX5_GET(create_tir_out, out,
1489 icm_address_63_40)
1490 << 40;
1491 resp->comp_mask |=
1492 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1493 }
7f72052c 1494 }
0fb2ed66 1495 }
1496
1497 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1498 rq->base.mqp.qpn;
0fb2ed66 1499 return 0;
1500
1501err_destroy_rq:
1502 destroy_raw_packet_qp_rq(dev, rq);
1503err_destroy_sq:
1504 if (!qp->sq.wqe_cnt)
1505 return err;
1506 destroy_raw_packet_qp_sq(dev, sq);
1507err_destroy_tis:
1cd6dbd3 1508 destroy_raw_packet_qp_tis(dev, sq, pd);
0fb2ed66 1509
1510 return err;
1511}
1512
1513static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1514 struct mlx5_ib_qp *qp)
1515{
1516 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1517 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1518 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1519
1520 if (qp->rq.wqe_cnt) {
443c1cf9 1521 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
0fb2ed66 1522 destroy_raw_packet_qp_rq(dev, rq);
1523 }
1524
1525 if (qp->sq.wqe_cnt) {
1526 destroy_raw_packet_qp_sq(dev, sq);
1cd6dbd3 1527 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
0fb2ed66 1528 }
1529}
1530
1531static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1532 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1533{
1534 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1535 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1536
1537 sq->sq = &qp->sq;
1538 rq->rq = &qp->rq;
1539 sq->doorbell = &qp->db;
1540 rq->doorbell = &qp->db;
1541}
1542
28d61370
YH		 1543static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1544{
0042f9e4
MB		 1545 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1546 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1547 mlx5_ib_disable_lb(dev, false, true);
443c1cf9
YH		 1548 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1549 to_mpd(qp->ibqp.pd)->uid);
28d61370
YH		 1550}
1551
f78d358c
LR		 1552struct mlx5_create_qp_params {
1553 struct ib_udata *udata;
1554 size_t inlen;
6f2cf76e 1555 size_t outlen;
e383085c 1556 size_t ucmd_size;
f78d358c
LR		 1557 void *ucmd;
1558 u8 is_rss_raw : 1;
1559 struct ib_qp_init_attr *attr;
1560 u32 uidx;
08d53976 1561 struct mlx5_ib_create_qp_resp resp;
f78d358c
LR		 1562};
1563
1564static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1565 struct mlx5_ib_qp *qp,
1566 struct mlx5_create_qp_params *params)
28d61370 1567{
f78d358c
LR		 1568 struct ib_qp_init_attr *init_attr = params->attr;
1569 struct mlx5_ib_create_qp_rss *ucmd = params->ucmd;
1570 struct ib_udata *udata = params->udata;
89944450
SR		 1571 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1572 udata, struct mlx5_ib_ucontext, ibucontext);
28d61370 1573 int inlen;
1f1d6abb 1574 int outlen;
28d61370
YH		 1575 int err;
1576 u32 *in;
1f1d6abb 1577 u32 *out;
28d61370
YH		 1578 void *tirc;
1579 void *hfso;
1580 u32 selected_fields = 0;
2d93fc85 1581 u32 outer_l4;
28d61370 1582 u32 tdn = mucontext->tdn;
175edba8 1583 u8 lb_flag = 0;
28d61370 1584
5ce0592b 1585 if (ucmd->comp_mask) {
28d61370
YH		 1586 mlx5_ib_dbg(dev, "invalid comp mask\n");
1587 return -EOPNOTSUPP;
1588 }
1589
5ce0592b
LR		 1590 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1591 !(ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
309fa347
MG		 1592 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1593 return -EOPNOTSUPP;
1594 }
1595
37518fa4 1596 if (dev->is_rep)
175edba8 1597 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
175edba8 1598
37518fa4
LR		 1599 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1600 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1601
1602 if (qp->flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
175edba8 1603 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
175edba8 1604
28d61370 1605 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1f1d6abb
AL		 1606 outlen = MLX5_ST_SZ_BYTES(create_tir_out);
1607 in = kvzalloc(inlen + outlen, GFP_KERNEL);
28d61370
YH		 1608 if (!in)
1609 return -ENOMEM;
1610
1f1d6abb 1611 out = in + MLX5_ST_SZ_DW(create_tir_in);
443c1cf9 1612 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
28d61370
YH		 1613 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1614 MLX5_SET(tirc, tirc, disp_type,
1615 MLX5_TIRC_DISP_TYPE_INDIRECT);
1616 MLX5_SET(tirc, tirc, indirect_table,
1617 init_attr->rwq_ind_tbl->ind_tbl_num);
1618 MLX5_SET(tirc, tirc, transport_domain, tdn);
1619
1620 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb 1621
5ce0592b 1622 if (ucmd->flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
f95ef6cb
MG		 1623 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1624
175edba8
MB		 1625 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1626
5ce0592b 1627 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_INNER)
309fa347
MG		 1628 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1629 else
1630 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1631
5ce0592b 1632 switch (ucmd->rx_hash_function) {
28d61370
YH		 1633 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1634 {
1635 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1636 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1637
5ce0592b 1638 if (len != ucmd->rx_key_len) {
28d61370
YH		 1639 err = -EINVAL;
1640 goto err;
1641 }
1642
1643 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
5ce0592b 1644 memcpy(rss_key, ucmd->rx_hash_key, len);
28d61370
YH		 1645 break;
1646 }
1647 default:
1648 err = -EOPNOTSUPP;
1649 goto err;
1650 }
1651
5ce0592b 1652 if (!ucmd->rx_hash_fields_mask) {
28d61370
YH		 1653 /* special case when this TIR serves as steering entry without hashing */
1654 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1655 goto create_tir;
1656 err = -EINVAL;
1657 goto err;
1658 }
1659
5ce0592b
LR		 1660 if (((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1661 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1662 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1663 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
28d61370
YH		 1664 err = -EINVAL;
1665 goto err;
1666 }
1667
1668 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
5ce0592b
LR		 1669 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1670 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
28d61370
YH		 1671 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1672 MLX5_L3_PROT_TYPE_IPV4);
5ce0592b
LR		 1673 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1674 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
28d61370
YH		 1675 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1676 MLX5_L3_PROT_TYPE_IPV6);
1677
5ce0592b
LR		 1678 outer_l4 = ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1679 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1680 << 0 |
1681 ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1682 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1683 << 1 |
1684 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
2d93fc85
MB		 1685
1686 /* Check that only one l4 protocol is set */
1687 if (outer_l4 & (outer_l4 - 1)) {
28d61370
YH		 1688 err = -EINVAL;
1689 goto err;
1690 }
1691
1692 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
5ce0592b
LR		 1693 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1694 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
28d61370
YH		 1695 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1696 MLX5_L4_PROT_TYPE_TCP);
5ce0592b
LR		 1697 else if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1698 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
28d61370
YH		 1699 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1700 MLX5_L4_PROT_TYPE_UDP);
1701
5ce0592b
LR		 1702 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1703 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
28d61370
YH		 1704 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1705
5ce0592b
LR		 1706 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1707 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
28d61370
YH		 1708 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1709
5ce0592b
LR		 1710 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1711 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
28d61370
YH		 1712 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1713
5ce0592b
LR		 1714 if ((ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1715 (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
28d61370
YH		 1716 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1717
5ce0592b 1718 if (ucmd->rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
2d93fc85
MB		 1719 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1720
28d61370
YH		 1721 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1722
1723create_tir:
e0b4b472
LR		 1724 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1725 err = mlx5_cmd_exec_inout(dev->mdev, create_tir, in, out);
28d61370 1726
1f1d6abb 1727 qp->rss_qp.tirn = MLX5_GET(create_tir_out, out, tirn);
0042f9e4
MB		 1728 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1729 err = mlx5_ib_enable_lb(dev, false, true);
1730
1731 if (err)
443c1cf9
YH		 1732 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1733 to_mpd(pd)->uid);
0042f9e4
MB		 1734 }
1735
28d61370
YH		 1736 if (err)
1737 goto err;
1738
7f72052c 1739 if (mucontext->devx_uid) {
08d53976
LR		 1740 params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1741 params->resp.tirn = qp->rss_qp.tirn;
1f1d6abb 1742 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
08d53976 1743 params->resp.tir_icm_addr =
1f1d6abb 1744 MLX5_GET(create_tir_out, out, icm_address_31_0);
08d53976
LR		 1745 params->resp.tir_icm_addr |=
1746 (u64)MLX5_GET(create_tir_out, out,
1747 icm_address_39_32)
1748 << 32;
1749 params->resp.tir_icm_addr |=
1750 (u64)MLX5_GET(create_tir_out, out,
1751 icm_address_63_40)
1752 << 40;
1753 params->resp.comp_mask |=
1f1d6abb
AL		 1754 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR;
1755 }
7f72052c
YH		 1756 }
1757
28d61370
YH		 1758 kvfree(in);
1759 /* qpn is reserved for that QP */
1760 qp->trans_qp.base.mqp.qpn = 0;
2be08c30 1761 qp->is_rss = true;
28d61370
YH		 1762 return 0;
1763
1764err:
1765 kvfree(in);
1766 return err;
1767}
1768
5d6ff1ba 1769static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
81530ab0 1770 struct mlx5_ib_qp *qp,
5d6ff1ba
YC		 1771 struct ib_qp_init_attr *init_attr,
1772 void *qpc)
1773{
5d6ff1ba 1774 int scqe_sz;
2ab367a7 1775 bool allow_scat_cqe = false;
5d6ff1ba 1776
81530ab0 1777 allow_scat_cqe = qp->flags_en & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
6f4bc0ea
YC		 1778
1779 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
5d6ff1ba
YC		 1780 return;
1781
1782 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1783 if (scqe_sz == 128) {
1784 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1785 return;
1786 }
1787
1788 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1789 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1790 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1791}
1792
a60109dc
YC		 1793static int atomic_size_to_mode(int size_mask)
1794{
1795 /* driver does not support atomic_size > 256B
1796 * and does not know how to translate bigger sizes
1797 */
1798 int supported_size_mask = size_mask & 0x1ff;
1799 int log_max_size;
1800
1801 if (!supported_size_mask)
1802 return -EOPNOTSUPP;
1803
1804 log_max_size = __fls(supported_size_mask);
1805
1806 if (log_max_size > 3)
1807 return log_max_size;
1808
1809 return MLX5_ATOMIC_MODE_8B;
1810}
1811
1812static int get_atomic_mode(struct mlx5_ib_dev *dev,
1813 enum ib_qp_type qp_type)
1814{
1815 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1816 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1817 int atomic_mode = -EOPNOTSUPP;
1818 int atomic_size_mask;
1819
1820 if (!atomic)
1821 return -EOPNOTSUPP;
1822
1823 if (qp_type == MLX5_IB_QPT_DCT)
1824 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1825 else
1826 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1827
1828 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1829 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1830 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1831
1832 if (atomic_mode <= 0 &&
1833 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1834 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1835 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1836
1837 return atomic_mode;
1838}
1839
f78d358c
LR		 1840static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1841 struct mlx5_create_qp_params *params)
04bcc1c2 1842{
e383085c 1843 struct mlx5_ib_create_qp *ucmd = params->ucmd;
f78d358c 1844 struct ib_qp_init_attr *attr = params->attr;
f78d358c 1845 u32 uidx = params->uidx;
04bcc1c2 1846 struct mlx5_ib_resources *devr = &dev->devr;
3e09a427 1847 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
04bcc1c2
LR		 1848 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1849 struct mlx5_core_dev *mdev = dev->mdev;
1850 struct mlx5_ib_qp_base *base;
1851 unsigned long flags;
1852 void *qpc;
1853 u32 *in;
1854 int err;
1855
04bcc1c2
LR		 1856 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1857 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1858
1859 in = kvzalloc(inlen, GFP_KERNEL);
1860 if (!in)
1861 return -ENOMEM;
1862
6eefa839 1863 if (MLX5_CAP_GEN(mdev, ece_support) && ucmd)
e383085c 1864 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
04bcc1c2
LR		 1865 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1866
1867 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_XRC);
1868 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1869 MLX5_SET(qpc, qpc, pd, to_mpd(devr->p0)->pdn);
1870
1871 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1872 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1873 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
1874 MLX5_SET(qpc, qpc, cd_master, 1);
1875 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
1876 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1877 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
1878 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1879
1880 MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);
1881 MLX5_SET(qpc, qpc, no_sq, 1);
1882 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1883 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1884 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1885 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(attr->xrcd)->xrcdn);
1886 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1887
1888 /* 0xffffff means we ask to work with cqe version 0 */
1889 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1890 MLX5_SET(qpc, qpc, user_index, uidx);
1891
1892 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1893 MLX5_SET(qpc, qpc, end_padding_mode,
1894 MLX5_WQ_END_PAD_MODE_ALIGN);
1895 /* Special case to clean flag */
1896 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
1897 }
1898
1899 base = &qp->trans_qp.base;
3e09a427 1900 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
04bcc1c2 1901 kvfree(in);
6367da46 1902 if (err)
04bcc1c2 1903 return err;
04bcc1c2
LR		 1904
1905 base->container_mibqp = qp;
1906 base->mqp.event = mlx5_ib_qp_event;
92cd667c
LR		 1907 if (MLX5_CAP_GEN(mdev, ece_support))
1908 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
04bcc1c2
LR		 1909
1910 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1911 list_add_tail(&qp->qps_list, &dev->qp_list);
1912 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1913
968f0b6f 1914 qp->trans_qp.xrcdn = to_mxrcd(attr->xrcd)->xrcdn;
04bcc1c2
LR		 1915 return 0;
1916}
1917
98fc1126 1918static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
f78d358c
LR		 1919 struct mlx5_ib_qp *qp,
1920 struct mlx5_create_qp_params *params)
e126ba97 1921{
f78d358c
LR		 1922 struct ib_qp_init_attr *init_attr = params->attr;
1923 struct mlx5_ib_create_qp *ucmd = params->ucmd;
3e09a427 1924 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
f78d358c
LR		 1925 struct ib_udata *udata = params->udata;
1926 u32 uidx = params->uidx;
e126ba97 1927 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1928 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1929 struct mlx5_core_dev *mdev = dev->mdev;
89ea94a7
MG		 1930 struct mlx5_ib_cq *send_cq;
1931 struct mlx5_ib_cq *recv_cq;
1932 unsigned long flags;
09a7d9ec 1933 struct mlx5_ib_qp_base *base;
e7b169f3 1934 int mlx5_st;
cfb5e088 1935 void *qpc;
09a7d9ec
SM		 1936 u32 *in;
1937 int err;
e126ba97 1938
e126ba97
EC		 1939 spin_lock_init(&qp->sq.lock);
1940 spin_lock_init(&qp->rq.lock);
1941
7aede1a2 1942 mlx5_st = to_mlx5_st(qp->type);
e7b169f3
NO		 1943 if (mlx5_st < 0)
1944 return -EINVAL;
1945
e126ba97
EC		 1946 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1947 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1948
2978975c
LR		 1949 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
1950 qp->underlay_qpn = init_attr->source_qpn;
1951
c2e53b2c 1952 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 1953 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
c2e53b2c
YH		 1954 &qp->raw_packet_qp.rq.base :
1955 &qp->trans_qp.base;
1956
e126ba97 1957 qp->has_rq = qp_has_rq(init_attr);
2dfac92d 1958 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
e126ba97
EC		 1959 if (err) {
1960 mlx5_ib_dbg(dev, "err %d\n", err);
1961 return err;
1962 }
1963
98fc1126
LR		 1964 if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
1965 ucmd->rq_wqe_count != qp->rq.wqe_cnt)
1966 return -EINVAL;
04bcc1c2 1967
98fc1126
LR		 1968 if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
1969 return -EINVAL;
e126ba97 1970
08d53976
LR		 1971 err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, &params->resp,
1972 &inlen, base, ucmd);
04bcc1c2
LR		 1973 if (err)
1974 return err;
e126ba97
EC		 1975
1976 if (is_sqp(init_attr->qp_type))
1977 qp->port = init_attr->port_num;
1978
e383085c
LR		 1979 if (MLX5_CAP_GEN(mdev, ece_support))
1980 MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
09a7d9ec
SM		 1981 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1982
e7b169f3 1983 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 1984 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
98fc1126 1985 MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
e126ba97 1986
c95e6d53 1987 if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
09a7d9ec 1988 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1989
2be08c30 1990 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1991 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1992
2be08c30 1993 if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
09a7d9ec 1994 MLX5_SET(qpc, qpc, cd_master, 1);
2be08c30 1995 if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
09a7d9ec 1996 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2be08c30 1997 if (qp->flags & IB_QP_CREATE_MANAGED_RECV)
09a7d9ec 1998 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2be08c30 1999 if (qp->flags_en & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE)
569c6651 2000 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
90ecb37a
LR		 2001 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
2002 (init_attr->qp_type == IB_QPT_RC ||
2003 init_attr->qp_type == IB_QPT_UC)) {
52c81f47 2004 int rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
8bde2c50
LR		 2005
2006 MLX5_SET(qpc, qpc, cs_res,
2007 rcqe_sz == 128 ? MLX5_RES_SCAT_DATA64_CQE :
2008 MLX5_RES_SCAT_DATA32_CQE);
2009 }
90ecb37a 2010 if ((qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) &&
7aede1a2 2011 (qp->type == MLX5_IB_QPT_DCI || qp->type == IB_QPT_RC))
81530ab0 2012 configure_requester_scat_cqe(dev, qp, init_attr, qpc);
e126ba97
EC		 2013
2014 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 2015 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2016 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 2017 }
2018
09a7d9ec 2019 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 2020
3fd3307e 2021 if (qp->sq.wqe_cnt) {
09a7d9ec 2022 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 2023 } else {
09a7d9ec 2024 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 2025 if (init_attr->srq &&
2026 init_attr->srq->srq_type == IB_SRQT_TM)
2027 MLX5_SET(qpc, qpc, offload_type,
2028 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2029 }
e126ba97
EC		 2030
2031 /* Set default resources */
2032 switch (init_attr->qp_type) {
e126ba97 2033 case IB_QPT_XRC_INI:
09a7d9ec 2034 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
f4375443 2035 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
09a7d9ec 2036 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 2037 break;
2038 default:
2039 if (init_attr->srq) {
f4375443 2040 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
09a7d9ec 2041 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 2042 } else {
f4375443 2043 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
09a7d9ec 2044 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 2045 }
2046 }
2047
2048 if (init_attr->send_cq)
09a7d9ec 2049 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 2050
2051 if (init_attr->recv_cq)
09a7d9ec 2052 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 2053
09a7d9ec 2054 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 2055
09a7d9ec
SM		 2056 /* 0xffffff means we ask to work with cqe version 0 */
2057 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 2058 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 2059
2978975c
LR		 2060 if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING &&
2061 init_attr->qp_type != IB_QPT_RAW_PACKET) {
2062 MLX5_SET(qpc, qpc, end_padding_mode,
2063 MLX5_WQ_END_PAD_MODE_ALIGN);
2064 /* Special case to clean flag */
2065 qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
b1383aa6
NO		 2066 }
2067
c2e53b2c 2068 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2be08c30 2069 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
2dfac92d 2070 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd->sq_buf_addr;
0fb2ed66 2071 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
7f72052c 2072 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
08d53976 2073 &params->resp);
04bcc1c2 2074 } else
3e09a427 2075 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
e126ba97 2076
479163f4 2077 kvfree(in);
04bcc1c2
LR		 2078 if (err)
2079 goto err_create;
e126ba97 2080
19098df2 2081 base->container_mibqp = qp;
2082 base->mqp.event = mlx5_ib_qp_event;
92cd667c
LR		 2083 if (MLX5_CAP_GEN(mdev, ece_support))
2084 params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
e126ba97 2085
7aede1a2 2086 get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
89ea94a7
MG		 2087 &send_cq, &recv_cq);
2088 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2089 mlx5_ib_lock_cqs(send_cq, recv_cq);
2090 /* Maintain device to QPs access, needed for further handling via reset
2091 * flow
2092 */
2093 list_add_tail(&qp->qps_list, &dev->qp_list);
2094 /* Maintain CQ to QPs access, needed for further handling via reset flow
2095 */
2096 if (send_cq)
2097 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2098 if (recv_cq)
2099 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2100 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2101 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2102
e126ba97
EC		 2103 return 0;
2104
2105err_create:
747c519c 2106 destroy_qp(dev, qp, base, udata);
e126ba97
EC		 2107 return err;
2108}
2109
98fc1126 2110static int create_kernel_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
f78d358c
LR		 2111 struct mlx5_ib_qp *qp,
2112 struct mlx5_create_qp_params *params)
98fc1126 2113{
f78d358c
LR		 2114 struct ib_qp_init_attr *attr = params->attr;
2115 u32 uidx = params->uidx;
98fc1126 2116 struct mlx5_ib_resources *devr = &dev->devr;
3e09a427 2117 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
98fc1126
LR		 2118 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
2119 struct mlx5_core_dev *mdev = dev->mdev;
2120 struct mlx5_ib_cq *send_cq;
2121 struct mlx5_ib_cq *recv_cq;
2122 unsigned long flags;
2123 struct mlx5_ib_qp_base *base;
2124 int mlx5_st;
2125 void *qpc;
2126 u32 *in;
2127 int err;
2128
98fc1126
LR		 2129 spin_lock_init(&qp->sq.lock);
2130 spin_lock_init(&qp->rq.lock);
2131
2132 mlx5_st = to_mlx5_st(qp->type);
2133 if (mlx5_st < 0)
2134 return -EINVAL;
2135
2136 if (attr->sq_sig_type == IB_SIGNAL_ALL_WR)
2137 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
2138
2139 base = &qp->trans_qp.base;
2140
2141 qp->has_rq = qp_has_rq(attr);
2142 err = set_rq_size(dev, &attr->cap, qp->has_rq, qp, NULL);
2143 if (err) {
2144 mlx5_ib_dbg(dev, "err %d\n", err);
2145 return err;
2146 }
2147
2148 err = _create_kernel_qp(dev, attr, qp, &in, &inlen, base);
2149 if (err)
2150 return err;
2151
2152 if (is_sqp(attr->qp_type))
2153 qp->port = attr->port_num;
2154
2155 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2156
2157 MLX5_SET(qpc, qpc, st, mlx5_st);
2158 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2159
2160 if (attr->qp_type != MLX5_IB_QPT_REG_UMR)
2161 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2162 else
2163 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2164
2165
2166 if (qp->flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
2167 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2168
2169 if (qp->rq.wqe_cnt) {
2170 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2171 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2172 }
2173
2174 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, attr));
2175
2176 if (qp->sq.wqe_cnt)
2177 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2178 else
2179 MLX5_SET(qpc, qpc, no_sq, 1);
2180
2181 if (attr->srq) {
f4375443 2182 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
98fc1126
LR		 2183 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2184 to_msrq(attr->srq)->msrq.srqn);
2185 } else {
f4375443 2186 MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
98fc1126
LR		 2187 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
2188 to_msrq(devr->s1)->msrq.srqn);
2189 }
2190
2191 if (attr->send_cq)
2192 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(attr->send_cq)->mcq.cqn);
2193
2194 if (attr->recv_cq)
2195 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(attr->recv_cq)->mcq.cqn);
2196
2197 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2198
2199 /* 0xffffff means we ask to work with cqe version 0 */
2200 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2201 MLX5_SET(qpc, qpc, user_index, uidx);
2202
2203 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2204 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO)
2205 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2206
3e09a427 2207 err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
98fc1126
LR		 2208 kvfree(in);
2209 if (err)
2210 goto err_create;
2211
2212 base->container_mibqp = qp;
2213 base->mqp.event = mlx5_ib_qp_event;
2214
2215 get_cqs(qp->type, attr->send_cq, attr->recv_cq,
2216 &send_cq, &recv_cq);
2217 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2218 mlx5_ib_lock_cqs(send_cq, recv_cq);
2219 /* Maintain device to QPs access, needed for further handling via reset
2220 * flow
2221 */
2222 list_add_tail(&qp->qps_list, &dev->qp_list);
2223 /* Maintain CQ to QPs access, needed for further handling via reset flow
2224 */
2225 if (send_cq)
2226 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2227 if (recv_cq)
2228 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2229 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2230 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2231
2232 return 0;
2233
2234err_create:
747c519c 2235 destroy_qp(dev, qp, base, NULL);
98fc1126
LR		 2236 return err;
2237}
2238
e126ba97
EC		 2239static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2240 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2241{
2242 if (send_cq) {
2243 if (recv_cq) {
2244 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 2245 spin_lock(&send_cq->lock);
e126ba97
EC		 2246 spin_lock_nested(&recv_cq->lock,
2247 SINGLE_DEPTH_NESTING);
2248 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 2249 spin_lock(&send_cq->lock);
e126ba97
EC		 2250 __acquire(&recv_cq->lock);
2251 } else {
89ea94a7 2252 spin_lock(&recv_cq->lock);
e126ba97
EC		 2253 spin_lock_nested(&send_cq->lock,
2254 SINGLE_DEPTH_NESTING);
2255 }
2256 } else {
89ea94a7 2257 spin_lock(&send_cq->lock);
6a4f139a 2258 __acquire(&recv_cq->lock);
e126ba97
EC		 2259 }
2260 } else if (recv_cq) {
89ea94a7 2261 spin_lock(&recv_cq->lock);
6a4f139a
EC		 2262 __acquire(&send_cq->lock);
2263 } else {
2264 __acquire(&send_cq->lock);
2265 __acquire(&recv_cq->lock);
e126ba97
EC		 2266 }
2267}
2268
2269static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2270 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2271{
2272 if (send_cq) {
2273 if (recv_cq) {
2274 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2275 spin_unlock(&recv_cq->lock);
89ea94a7 2276 spin_unlock(&send_cq->lock);
e126ba97
EC		 2277 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2278 __release(&recv_cq->lock);
89ea94a7 2279 spin_unlock(&send_cq->lock);
e126ba97
EC		 2280 } else {
2281 spin_unlock(&send_cq->lock);
89ea94a7 2282 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2283 }
2284 } else {
6a4f139a 2285 __release(&recv_cq->lock);
89ea94a7 2286 spin_unlock(&send_cq->lock);
e126ba97
EC		 2287 }
2288 } else if (recv_cq) {
6a4f139a 2289 __release(&send_cq->lock);
89ea94a7 2290 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2291 } else {
2292 __release(&recv_cq->lock);
2293 __release(&send_cq->lock);
e126ba97
EC		 2294 }
2295}
2296
89ea94a7
MG		 2297static void get_cqs(enum ib_qp_type qp_type,
2298 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2299 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2300{
89ea94a7 2301 switch (qp_type) {
e126ba97
EC		 2302 case IB_QPT_XRC_TGT:
2303 *send_cq = NULL;
2304 *recv_cq = NULL;
2305 break;
2306 case MLX5_IB_QPT_REG_UMR:
2307 case IB_QPT_XRC_INI:
89ea94a7 2308 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2309 *recv_cq = NULL;
2310 break;
2311
2312 case IB_QPT_SMI:
d16e91da 2313 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2314 case IB_QPT_RC:
2315 case IB_QPT_UC:
2316 case IB_QPT_UD:
0fb2ed66 2317 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2318 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2319 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97 2320 break;
e126ba97
EC		 2321 default:
2322 *send_cq = NULL;
2323 *recv_cq = NULL;
2324 break;
2325 }
2326}
2327
ad5f8e96 2328static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2329 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2330 u8 lag_tx_affinity);
ad5f8e96 2331
bdeacabd
SR		 2332static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2333 struct ib_udata *udata)
e126ba97
EC		 2334{
2335 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2336 struct mlx5_ib_qp_base *base;
89ea94a7 2337 unsigned long flags;
e126ba97
EC		 2338 int err;
2339
6c41965d 2340 if (qp->is_rss) {
28d61370
YH		 2341 destroy_rss_raw_qp_tir(dev, qp);
2342 return;
2343 }
2344
6c41965d 2345 base = (qp->type == IB_QPT_RAW_PACKET ||
2be08c30 2346 qp->flags & IB_QP_CREATE_SOURCE_QPN) ?
6c41965d
LR		 2347 &qp->raw_packet_qp.rq.base :
2348 &qp->trans_qp.base;
0fb2ed66 2349
6aec21f6 2350 if (qp->state != IB_QPS_RESET) {
6c41965d 2351 if (qp->type != IB_QPT_RAW_PACKET &&
2be08c30 2352 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) {
333fbaa0 2353 err = mlx5_core_qp_modify(dev, MLX5_CMD_OP_2RST_QP, 0,
5f62a521 2354 NULL, &base->mqp, NULL);
ad5f8e96 2355 } else {
0680efa2
AV		 2356 struct mlx5_modify_raw_qp_param raw_qp_param = {
2357 .operation = MLX5_CMD_OP_2RST_QP
2358 };
2359
13eab21f 2360 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2361 }
2362 if (err)
427c1e7b 2363 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2364 base->mqp.qpn);
6aec21f6 2365 }
e126ba97 2366
6c41965d
LR		 2367 get_cqs(qp->type, qp->ibqp.send_cq, qp->ibqp.recv_cq, &send_cq,
2368 &recv_cq);
89ea94a7
MG		 2369
2370 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2371 mlx5_ib_lock_cqs(send_cq, recv_cq);
2372 /* del from lists under both locks above to protect reset flow paths */
2373 list_del(&qp->qps_list);
2374 if (send_cq)
2375 list_del(&qp->cq_send_list);
2376
2377 if (recv_cq)
2378 list_del(&qp->cq_recv_list);
e126ba97 2379
03c4077b 2380 if (!udata) {
19098df2 2381 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2382 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2383 if (send_cq != recv_cq)
19098df2 2384 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2385 NULL);
e126ba97 2386 }
89ea94a7
MG		 2387 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2388 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2389
6c41965d 2390 if (qp->type == IB_QPT_RAW_PACKET ||
2be08c30 2391 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0fb2ed66 2392 destroy_raw_packet_qp(dev, qp);
2393 } else {
333fbaa0 2394 err = mlx5_core_destroy_qp(dev, &base->mqp);
0fb2ed66 2395 if (err)
2396 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2397 base->mqp.qpn);
2398 }
e126ba97 2399
747c519c 2400 destroy_qp(dev, qp, base, udata);
e126ba97
EC		 2401}
2402
a645a89d
LR		 2403static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2404 struct mlx5_ib_qp *qp,
f78d358c 2405 struct mlx5_create_qp_params *params)
b4aaa1f0 2406{
f78d358c
LR		 2407 struct ib_qp_init_attr *attr = params->attr;
2408 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2409 u32 uidx = params->uidx;
b4aaa1f0
MS		 2410 void *dctc;
2411
b4aaa1f0 2412 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
9c2ba4ed 2413 if (!qp->dct.in)
47c80612 2414 return -ENOMEM;
b4aaa1f0 2415
a01a5860 2416 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
b4aaa1f0 2417 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
b4aaa1f0
MS		 2418 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2419 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2420 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2421 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2422 MLX5_SET(dctc, dctc, user_index, uidx);
a645a89d
LR		 2423 if (MLX5_CAP_GEN(dev->mdev, ece_support))
2424 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
b4aaa1f0 2425
37518fa4 2426 if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE) {
fd9dab7e
LR		 2427 int rcqe_sz = mlx5_ib_get_cqe_size(attr->recv_cq);
2428
2429 if (rcqe_sz == 128)
2430 MLX5_SET(dctc, dctc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
2431 }
5d6ff1ba 2432
b4aaa1f0
MS		 2433 qp->state = IB_QPS_RESET;
2434
47c80612 2435 return 0;
b4aaa1f0
MS		 2436}
2437
7aede1a2
LR		 2438static int check_qp_type(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
2439 enum ib_qp_type *type)
6eb7edff
LR		 2440{
2441 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
2442 goto out;
2443
2444 switch (attr->qp_type) {
2445 case IB_QPT_XRC_TGT:
2446 case IB_QPT_XRC_INI:
2447 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2448 goto out;
2449 fallthrough;
6eb7edff
LR		 2450 case IB_QPT_RC:
2451 case IB_QPT_UC:
6eb7edff
LR		 2452 case IB_QPT_SMI:
2453 case MLX5_IB_QPT_HW_GSI:
6eb7edff
LR		 2454 case IB_QPT_DRIVER:
2455 case IB_QPT_GSI:
42caf9cb
MB		 2456 if (dev->profile == &raw_eth_profile)
2457 goto out;
2458 case IB_QPT_RAW_PACKET:
2459 case IB_QPT_UD:
2460 case MLX5_IB_QPT_REG_UMR:
7aede1a2 2461 break;
6eb7edff
LR		 2462 default:
2463 goto out;
b4aaa1f0
MS		 2464 }
2465
7aede1a2 2466 *type = attr->qp_type;
b4aaa1f0 2467 return 0;
6eb7edff
LR		 2468
2469out:
2470 mlx5_ib_dbg(dev, "Unsupported QP type %d\n", attr->qp_type);
2471 return -EOPNOTSUPP;
b4aaa1f0
MS		 2472}
2473
2242cc25
LR		 2474static int check_valid_flow(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2475 struct ib_qp_init_attr *attr,
2476 struct ib_udata *udata)
2477{
2478 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2479 udata, struct mlx5_ib_ucontext, ibucontext);
2480
2481 if (!udata) {
2482 /* Kernel create_qp callers */
2483 if (attr->rwq_ind_tbl)
2484 return -EOPNOTSUPP;
2485
2486 switch (attr->qp_type) {
2487 case IB_QPT_RAW_PACKET:
2488 case IB_QPT_DRIVER:
2489 return -EOPNOTSUPP;
2490 default:
2491 return 0;
2492 }
2493 }
2494
2495 /* Userspace create_qp callers */
2496 if (attr->qp_type == IB_QPT_RAW_PACKET && !ucontext->cqe_version) {
2497 mlx5_ib_dbg(dev,
2498 "Raw Packet QP is only supported for CQE version > 0\n");
2499 return -EINVAL;
2500 }
2501
2502 if (attr->qp_type != IB_QPT_RAW_PACKET && attr->rwq_ind_tbl) {
2503 mlx5_ib_dbg(dev,
2504 "Wrong QP type %d for the RWQ indirect table\n",
2505 attr->qp_type);
2506 return -EINVAL;
2507 }
2508
2509 switch (attr->qp_type) {
2510 case IB_QPT_SMI:
2511 case MLX5_IB_QPT_HW_GSI:
2512 case MLX5_IB_QPT_REG_UMR:
2513 case IB_QPT_GSI:
2514 mlx5_ib_dbg(dev, "Kernel doesn't support QP type %d\n",
2515 attr->qp_type);
2516 return -EINVAL;
2517 default:
2518 break;
2519 }
2520
2521 /*
2522 * We don't need to see this warning, it means that kernel code
2523 * missing ib_pd. Placed here to catch developer's mistakes.
2524 */
2525 WARN_ONCE(!pd && attr->qp_type != IB_QPT_XRC_TGT,
2526 "There is a missing PD pointer assignment\n");
2527 return 0;
2528}
2529
37518fa4
LR		 2530static void process_vendor_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2531 bool cond, struct mlx5_ib_qp *qp)
2532{
2533 if (!(*flags & flag))
2534 return;
2535
2536 if (cond) {
2537 qp->flags_en |= flag;
2538 *flags &= ~flag;
2539 return;
2540 }
2541
81530ab0
LR		 2542 switch (flag) {
2543 case MLX5_QP_FLAG_SCATTER_CQE:
2544 case MLX5_QP_FLAG_ALLOW_SCATTER_CQE:
37518fa4 2545 /*
81530ab0
LR		 2546 * We don't return error if these flags were provided,
2547 * and mlx5 doesn't have right capability.
2548 */
2549 *flags &= ~(MLX5_QP_FLAG_SCATTER_CQE |
2550 MLX5_QP_FLAG_ALLOW_SCATTER_CQE);
37518fa4 2551 return;
81530ab0
LR		 2552 default:
2553 break;
37518fa4
LR		 2554 }
2555 mlx5_ib_dbg(dev, "Vendor create QP flag 0x%X is not supported\n", flag);
2556}
2557
2558static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5ce0592b 2559 void *ucmd, struct ib_qp_init_attr *attr)
2fdddbd5 2560{
37518fa4 2561 struct mlx5_core_dev *mdev = dev->mdev;
37518fa4 2562 bool cond;
5ce0592b
LR		 2563 int flags;
2564
2565 if (attr->rwq_ind_tbl)
2566 flags = ((struct mlx5_ib_create_qp_rss *)ucmd)->flags;
2567 else
2568 flags = ((struct mlx5_ib_create_qp *)ucmd)->flags;
37518fa4
LR		 2569
2570 switch (flags & (MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI)) {
2fdddbd5 2571 case MLX5_QP_FLAG_TYPE_DCI:
7aede1a2 2572 qp->type = MLX5_IB_QPT_DCI;
2fdddbd5
LR		 2573 break;
2574 case MLX5_QP_FLAG_TYPE_DCT:
7aede1a2 2575 qp->type = MLX5_IB_QPT_DCT;
37518fa4 2576 break;
7aede1a2
LR		 2577 default:
2578 if (qp->type != IB_QPT_DRIVER)
2579 break;
2580 /*
2581 * It is IB_QPT_DRIVER and or no subtype or
2582 * wrong subtype were provided.
2583 */
2fdddbd5 2584 return -EINVAL;
7aede1a2 2585 }
37518fa4
LR		 2586
2587 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
2588 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
2589
2590 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
2591 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
2592 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
81530ab0
LR		 2593 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_ALLOW_SCATTER_CQE,
2594 MLX5_CAP_GEN(mdev, sctr_data_cqe), qp);
37518fa4 2595
7aede1a2 2596 if (qp->type == IB_QPT_RAW_PACKET) {
37518fa4
LR		 2597 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
2598 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
2599 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
2600 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TUNNEL_OFFLOADS,
2601 cond, qp);
2602 process_vendor_flag(dev, &flags,
2603 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC, true,
2604 qp);
2605 process_vendor_flag(dev, &flags,
2606 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC, true,
2607 qp);
2fdddbd5
LR		 2608 }
2609
7aede1a2 2610 if (qp->type == IB_QPT_RC)
37518fa4
LR		 2611 process_vendor_flag(dev, &flags,
2612 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE,
2613 MLX5_CAP_GEN(mdev, qp_packet_based), qp);
2614
76883a6c
LR		 2615 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_BFREG_INDEX, true, qp);
2616 process_vendor_flag(dev, &flags, MLX5_QP_FLAG_UAR_PAGE_INDEX, true, qp);
2617
5d6fffed
LR		 2618 cond = qp->flags_en & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2619 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2620 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC);
2621 if (attr->rwq_ind_tbl && cond) {
2622 mlx5_ib_dbg(dev, "RSS RAW QP has unsupported flags 0x%X\n",
2623 cond);
2624 return -EINVAL;
2625 }
2626
37518fa4
LR		 2627 if (flags)
2628 mlx5_ib_dbg(dev, "udata has unsupported flags 0x%X\n", flags);
2629
2630 return (flags) ? -EINVAL : 0;
5d6fffed 2631 }
2fdddbd5 2632
2978975c
LR		 2633static void process_create_flag(struct mlx5_ib_dev *dev, int *flags, int flag,
2634 bool cond, struct mlx5_ib_qp *qp)
2635{
2636 if (!(*flags & flag))
2637 return;
2638
2639 if (cond) {
2640 qp->flags |= flag;
2641 *flags &= ~flag;
2642 return;
2643 }
2644
2645 if (flag == MLX5_IB_QP_CREATE_WC_TEST) {
2646 /*
2647 * Special case, if condition didn't meet, it won't be error,
2648 * just different in-kernel flow.
2649 */
2650 *flags &= ~MLX5_IB_QP_CREATE_WC_TEST;
2651 return;
2652 }
2653 mlx5_ib_dbg(dev, "Verbs create QP flag 0x%X is not supported\n", flag);
2654}
2655
2656static int process_create_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2657 struct ib_qp_init_attr *attr)
2658{
7aede1a2 2659 enum ib_qp_type qp_type = qp->type;
2978975c
LR		 2660 struct mlx5_core_dev *mdev = dev->mdev;
2661 int create_flags = attr->create_flags;
2662 bool cond;
2663
42caf9cb
MB		 2664 if (qp->type == IB_QPT_UD && dev->profile == &raw_eth_profile)
2665 if (create_flags & ~MLX5_IB_QP_CREATE_WC_TEST)
2666 return -EINVAL;
2667
7aede1a2 2668 if (qp_type == MLX5_IB_QPT_DCT)
2978975c
LR		 2669 return (create_flags) ? -EINVAL : 0;
2670
2671 if (qp_type == IB_QPT_RAW_PACKET && attr->rwq_ind_tbl)
2672 return (create_flags) ? -EINVAL : 0;
2673
f81b4565
LR		 2674 process_create_flag(dev, &create_flags, IB_QP_CREATE_NETIF_QP,
2675 mlx5_get_flow_namespace(dev->mdev,
2676 MLX5_FLOW_NAMESPACE_BYPASS),
2677 qp);
9e0dc7b9
MG		 2678 process_create_flag(dev, &create_flags,
2679 IB_QP_CREATE_INTEGRITY_EN,
2680 MLX5_CAP_GEN(mdev, sho), qp);
2978975c
LR		 2681 process_create_flag(dev, &create_flags,
2682 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
2683 MLX5_CAP_GEN(mdev, block_lb_mc), qp);
2684 process_create_flag(dev, &create_flags, IB_QP_CREATE_CROSS_CHANNEL,
2685 MLX5_CAP_GEN(mdev, cd), qp);
2686 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_SEND,
2687 MLX5_CAP_GEN(mdev, cd), qp);
2688 process_create_flag(dev, &create_flags, IB_QP_CREATE_MANAGED_RECV,
2689 MLX5_CAP_GEN(mdev, cd), qp);
2690
2691 if (qp_type == IB_QPT_UD) {
2692 process_create_flag(dev, &create_flags,
2693 IB_QP_CREATE_IPOIB_UD_LSO,
2694 MLX5_CAP_GEN(mdev, ipoib_basic_offloads),
2695 qp);
2696 cond = MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_IB;
2697 process_create_flag(dev, &create_flags, IB_QP_CREATE_SOURCE_QPN,
2698 cond, qp);
2699 }
2700
2701 if (qp_type == IB_QPT_RAW_PACKET) {
2702 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2703 MLX5_CAP_ETH(mdev, scatter_fcs);
2704 process_create_flag(dev, &create_flags,
2705 IB_QP_CREATE_SCATTER_FCS, cond, qp);
2706
2707 cond = MLX5_CAP_GEN(mdev, eth_net_offloads) &&
2708 MLX5_CAP_ETH(mdev, vlan_cap);
2709 process_create_flag(dev, &create_flags,
2710 IB_QP_CREATE_CVLAN_STRIPPING, cond, qp);
2711 }
2712
2713 process_create_flag(dev, &create_flags,
2714 IB_QP_CREATE_PCI_WRITE_END_PADDING,
2715 MLX5_CAP_GEN(mdev, end_pad), qp);
2716
2717 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_WC_TEST,
2718 qp_type != MLX5_IB_QPT_REG_UMR, qp);
2719 process_create_flag(dev, &create_flags, MLX5_IB_QP_CREATE_SQPN_QP1,
2720 true, qp);
2721
2722 if (create_flags)
2723 mlx5_ib_dbg(dev, "Create QP has unsupported flags 0x%X\n",
2724 create_flags);
2725
2726 return (create_flags) ? -EINVAL : 0;
2727}
2728
6f2cf76e
LR		 2729static int process_udata_size(struct mlx5_ib_dev *dev,
2730 struct mlx5_create_qp_params *params)
2fdddbd5
LR		 2731{
2732 size_t ucmd = sizeof(struct mlx5_ib_create_qp);
6f2cf76e
LR		 2733 struct ib_udata *udata = params->udata;
2734 size_t outlen = udata->outlen;
5ce0592b 2735 size_t inlen = udata->inlen;
2fdddbd5 2736
6f2cf76e 2737 params->outlen = min(outlen, sizeof(struct mlx5_ib_create_qp_resp));
e383085c 2738 params->ucmd_size = ucmd;
6f2cf76e 2739 if (!params->is_rss_raw) {
e383085c
LR		 2740 /* User has old rdma-core, which doesn't support ECE */
2741 size_t min_inlen =
2742 offsetof(struct mlx5_ib_create_qp, ece_options);
2743
2744 /*
2745 * We will check in check_ucmd_data() that user
2746 * cleared everything after inlen.
2747 */
2748 params->inlen = (inlen < min_inlen) ? 0 : min(inlen, ucmd);
6f2cf76e
LR		 2749 goto out;
2750 }
5ce0592b 2751
6f2cf76e 2752 /* RSS RAW QP */
5ce0592b 2753 if (inlen < offsetofend(struct mlx5_ib_create_qp_rss, flags))
6f2cf76e
LR		 2754 return -EINVAL;
2755
2756 if (outlen < offsetofend(struct mlx5_ib_create_qp_resp, bfreg_index))
2757 return -EINVAL;
5ce0592b
LR		 2758
2759 ucmd = sizeof(struct mlx5_ib_create_qp_rss);
e383085c 2760 params->ucmd_size = ucmd;
5ce0592b 2761 if (inlen > ucmd && !ib_is_udata_cleared(udata, ucmd, inlen - ucmd))
6f2cf76e
LR		 2762 return -EINVAL;
2763
2764 params->inlen = min(ucmd, inlen);
2765out:
2766 if (!params->inlen)
e383085c 2767 mlx5_ib_dbg(dev, "udata is too small\n");
2dfac92d 2768
6f2cf76e 2769 return (params->inlen) ? 0 : -EINVAL;
2fdddbd5
LR		 2770}
2771
968f0b6f
LR		 2772static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
2773 struct mlx5_ib_qp *qp,
2774 struct mlx5_create_qp_params *params)
5d0dc3d9 2775{
968f0b6f
LR		 2776 int err;
2777
2778 if (params->is_rss_raw) {
2779 err = create_rss_raw_qp_tir(dev, pd, qp, params);
2780 goto out;
2781 }
2782
2783 if (qp->type == MLX5_IB_QPT_DCT) {
a645a89d 2784 err = create_dct(dev, pd, qp, params);
968f0b6f
LR		 2785 goto out;
2786 }
2787
2788 if (qp->type == IB_QPT_XRC_TGT) {
2789 err = create_xrc_tgt_qp(dev, qp, params);
2790 goto out;
2791 }
5d0dc3d9 2792
968f0b6f
LR		 2793 if (params->udata)
2794 err = create_user_qp(dev, pd, qp, params);
2795 else
2796 err = create_kernel_qp(dev, pd, qp, params);
2797
2798out:
2799 if (err) {
2800 mlx5_ib_err(dev, "Create QP type %d failed\n", qp->type);
2801 return err;
2802 }
2803
2804 if (is_qp0(qp->type))
2805 qp->ibqp.qp_num = 0;
2806 else if (is_qp1(qp->type))
2807 qp->ibqp.qp_num = 1;
2808 else
2809 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2810
2811 mlx5_ib_dbg(dev,
3e09a427 2812 "QP type %d, ib qpn 0x%X, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x, ece 0x%x\n",
968f0b6f
LR		 2813 qp->type, qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2814 params->attr->recv_cq ? to_mcq(params->attr->recv_cq)->mcq.cqn :
2815 -1,
2816 params->attr->send_cq ? to_mcq(params->attr->send_cq)->mcq.cqn :
3e09a427
LR		 2817 -1,
2818 params->resp.ece_options);
968f0b6f
LR		 2819
2820 return 0;
5d0dc3d9
LR		 2821}
2822
7aede1a2
LR		 2823static int check_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2824 struct ib_qp_init_attr *attr)
2825{
2826 int ret = 0;
2827
2828 switch (qp->type) {
2829 case MLX5_IB_QPT_DCT:
2830 ret = (!attr->srq || !attr->recv_cq) ? -EINVAL : 0;
2831 break;
2832 case MLX5_IB_QPT_DCI:
2833 ret = (attr->cap.max_recv_wr || attr->cap.max_recv_sge) ?
2834 -EINVAL :
2835 0;
2836 break;
266424eb
LR		 2837 case IB_QPT_RAW_PACKET:
2838 ret = (attr->rwq_ind_tbl && attr->send_cq) ? -EINVAL : 0;
2839 break;
7aede1a2
LR		 2840 default:
2841 break;
2842 }
2843
2844 if (ret)
2845 mlx5_ib_dbg(dev, "QP type %d has wrong attributes\n", qp->type);
2846
2847 return ret;
2848}
2849
f78d358c
LR		 2850static int get_qp_uidx(struct mlx5_ib_qp *qp,
2851 struct mlx5_create_qp_params *params)
21aad80b 2852{
f78d358c
LR		 2853 struct mlx5_ib_create_qp *ucmd = params->ucmd;
2854 struct ib_udata *udata = params->udata;
21aad80b
LR		 2855 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2856 udata, struct mlx5_ib_ucontext, ibucontext);
2857
f78d358c 2858 if (params->is_rss_raw)
21aad80b
LR		 2859 return 0;
2860
f78d358c 2861 return get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &params->uidx);
21aad80b
LR		 2862}
2863
08d53976
LR		 2864static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2865{
2866 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2867
2868 if (mqp->state == IB_QPS_RTR) {
2869 int err;
2870
2871 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
2872 if (err) {
2873 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2874 return err;
2875 }
2876 }
2877
2878 kfree(mqp->dct.in);
2879 kfree(mqp);
2880 return 0;
2881}
2882
e383085c
LR		 2883static int check_ucmd_data(struct mlx5_ib_dev *dev,
2884 struct mlx5_create_qp_params *params)
2885{
e383085c
LR		 2886 struct ib_udata *udata = params->udata;
2887 size_t size, last;
2888 int ret;
2889
2890 if (params->is_rss_raw)
2891 /*
2892 * These QPs don't have "reserved" field in their
2893 * create_qp input struct, so their data is always valid.
2894 */
2895 last = sizeof(struct mlx5_ib_create_qp_rss);
2896 else
2c0f5292 2897 last = offsetof(struct mlx5_ib_create_qp, reserved);
e383085c
LR		 2898
2899 if (udata->inlen <= last)
2900 return 0;
2901
2902 /*
2903 * User provides different create_qp structures based on the
2904 * flow and we need to know if he cleared memory after our
2905 * struct create_qp ends.
2906 */
2907 size = udata->inlen - last;
2908 ret = ib_is_udata_cleared(params->udata, last, size);
2909 if (!ret)
2910 mlx5_ib_dbg(
2911 dev,
4f5747cf 2912 "udata is not cleared, inlen = %zu, ucmd = %zu, last = %zu, size = %zu\n",
e383085c
LR		 2913 udata->inlen, params->ucmd_size, last, size);
2914 return ret ? 0 : -EINVAL;
2915}
2916
f78d358c 2917struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attr,
e126ba97
EC		 2918 struct ib_udata *udata)
2919{
f78d358c 2920 struct mlx5_create_qp_params params = {};
e126ba97
EC		 2921 struct mlx5_ib_dev *dev;
2922 struct mlx5_ib_qp *qp;
7aede1a2 2923 enum ib_qp_type type;
e126ba97
EC		 2924 int err;
2925
6eb7edff 2926 dev = pd ? to_mdev(pd->device) :
f78d358c 2927 to_mdev(to_mxrcd(attr->xrcd)->ibxrcd.device);
0fb2ed66 2928
f78d358c
LR		 2929 err = check_qp_type(dev, attr, &type);
2930 if (err)
6eb7edff 2931 return ERR_PTR(err);
6eb7edff 2932
f78d358c 2933 err = check_valid_flow(dev, pd, attr, udata);
2242cc25
LR		 2934 if (err)
2935 return ERR_PTR(err);
e126ba97 2936
f78d358c
LR		 2937 if (attr->qp_type == IB_QPT_GSI)
2938 return mlx5_ib_gsi_create_qp(pd, attr);
9c2ba4ed 2939
f78d358c
LR		 2940 params.udata = udata;
2941 params.uidx = MLX5_IB_DEFAULT_UIDX;
2942 params.attr = attr;
2943 params.is_rss_raw = !!attr->rwq_ind_tbl;
2fdddbd5 2944
f78d358c 2945 if (udata) {
6f2cf76e
LR		 2946 err = process_udata_size(dev, &params);
2947 if (err)
2948 return ERR_PTR(err);
2fdddbd5 2949
e383085c
LR		 2950 err = check_ucmd_data(dev, &params);
2951 if (err)
2952 return ERR_PTR(err);
2953
2954 params.ucmd = kzalloc(params.ucmd_size, GFP_KERNEL);
f78d358c 2955 if (!params.ucmd)
5ce0592b
LR		 2956 return ERR_PTR(-ENOMEM);
2957
f78d358c 2958 err = ib_copy_from_udata(params.ucmd, udata, params.inlen);
2fdddbd5 2959 if (err)
5ce0592b 2960 goto free_ucmd;
2fdddbd5
LR		 2961 }
2962
9c2ba4ed 2963 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
5ce0592b
LR		 2964 if (!qp) {
2965 err = -ENOMEM;
2966 goto free_ucmd;
2967 }
9c2ba4ed 2968
7fa84b57 2969 mutex_init(&qp->mutex);
7aede1a2 2970 qp->type = type;
37518fa4 2971 if (udata) {
f78d358c 2972 err = process_vendor_flags(dev, qp, params.ucmd, attr);
b4aaa1f0 2973 if (err)
9c2ba4ed 2974 goto free_qp;
21aad80b 2975
f78d358c 2976 err = get_qp_uidx(qp, &params);
21aad80b
LR		 2977 if (err)
2978 goto free_qp;
b4aaa1f0 2979 }
f78d358c 2980 err = process_create_flags(dev, qp, attr);
2978975c
LR		 2981 if (err)
2982 goto free_qp;
b4aaa1f0 2983
f78d358c 2984 err = check_qp_attr(dev, qp, attr);
7aede1a2
LR		 2985 if (err)
2986 goto free_qp;
2987
968f0b6f
LR		 2988 err = create_qp(dev, pd, qp, &params);
2989 if (err)
9c2ba4ed 2990 goto free_qp;
e126ba97 2991
f78d358c 2992 kfree(params.ucmd);
08d53976 2993 params.ucmd = NULL;
5ce0592b 2994
08d53976
LR		 2995 if (udata)
2996 /*
2997 * It is safe to copy response for all user create QP flows,
2998 * including MLX5_IB_QPT_DCT, which doesn't need it.
2999 * In that case, resp will be filled with zeros.
3000 */
3001 err = ib_copy_to_udata(udata, &params.resp, params.outlen);
3002 if (err)
3003 goto destroy_qp;
3004
e126ba97 3005 return &qp->ibqp;
9c2ba4ed 3006
08d53976 3007destroy_qp:
6c41965d 3008 if (qp->type == MLX5_IB_QPT_DCT) {
08d53976 3009 mlx5_ib_destroy_dct(qp);
6c41965d
LR		 3010 } else {
3011 /*
0a037150 3012 * These lines below are temp solution till QP allocation
6c41965d
LR		 3013 * will be moved to be under IB/core responsiblity.
3014 */
3015 qp->ibqp.send_cq = attr->send_cq;
3016 qp->ibqp.recv_cq = attr->recv_cq;
0a037150 3017 qp->ibqp.pd = pd;
08d53976 3018 destroy_qp_common(dev, qp, udata);
6c41965d
LR		 3019 }
3020
08d53976 3021 qp = NULL;
9c2ba4ed
LR		 3022free_qp:
3023 kfree(qp);
5ce0592b 3024free_ucmd:
f78d358c 3025 kfree(params.ucmd);
9c2ba4ed 3026 return ERR_PTR(err);
e126ba97
EC		 3027}
3028
c4367a26 3029int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
e126ba97
EC		 3030{
3031 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3032 struct mlx5_ib_qp *mqp = to_mqp(qp);
3033
d16e91da
HE		 3034 if (unlikely(qp->qp_type == IB_QPT_GSI))
3035 return mlx5_ib_gsi_destroy_qp(qp);
3036
7aede1a2 3037 if (mqp->type == MLX5_IB_QPT_DCT)
776a3906
MS		 3038 return mlx5_ib_destroy_dct(mqp);
3039
bdeacabd 3040 destroy_qp_common(dev, mqp, udata);
e126ba97
EC		 3041
3042 kfree(mqp);
3043
3044 return 0;
3045}
3046
f18e26af
LR		 3047static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
3048 const struct ib_qp_attr *attr, int attr_mask,
3049 void *qpc)
e126ba97 3050{
a60109dc 3051 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
f18e26af
LR		 3052 u8 dest_rd_atomic;
3053 u32 access_flags;
a60109dc 3054
e126ba97
EC		 3055 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3056 dest_rd_atomic = attr->max_dest_rd_atomic;
3057 else
19098df2 3058 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 3059
3060 if (attr_mask & IB_QP_ACCESS_FLAGS)
3061 access_flags = attr->qp_access_flags;
3062 else
19098df2 3063 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 3064
3065 if (!dest_rd_atomic)
3066 access_flags &= IB_ACCESS_REMOTE_WRITE;
3067
f18e26af
LR		 3068 MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
3069
13f8d9c1 3070 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 3071 int atomic_mode;
3072
3073 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
3074 if (atomic_mode < 0)
3075 return -EOPNOTSUPP;
3076
f18e26af
LR		 3077 MLX5_SET(qpc, qpc, rae, 1);
3078 MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
a60109dc
YC		 3079 }
3080
f18e26af 3081 MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
a60109dc 3082 return 0;
e126ba97
EC		 3083}
3084
3085enum {
3086 MLX5_PATH_FLAG_FL = 1 << 0,
3087 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
3088 MLX5_PATH_FLAG_COUNTER = 1 << 2,
3089};
3090
3091static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
3092{
4f32ac2e 3093 if (rate == IB_RATE_PORT_CURRENT)
e126ba97 3094 return 0;
4f32ac2e 3095
a5a5d199 3096 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
e126ba97 3097 return -EINVAL;
e126ba97 3098
4f32ac2e
DG		 3099 while (rate != IB_RATE_PORT_CURRENT &&
3100 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
3101 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
3102 --rate;
3103
3104 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
e126ba97
EC		 3105}
3106
75850d0b 3107static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 3108 struct mlx5_ib_sq *sq, u8 sl,
3109 struct ib_pd *pd)
75850d0b 3110{
3111 void *in;
3112 void *tisc;
3113 int inlen;
3114 int err;
3115
3116 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 3117 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 3118 if (!in)
3119 return -ENOMEM;
3120
3121 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1cd6dbd3 3122 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
75850d0b 3123
3124 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3125 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
3126
e0b4b472 3127 err = mlx5_core_modify_tis(dev, sq->tisn, in);
75850d0b 3128
3129 kvfree(in);
3130
3131 return err;
3132}
3133
13eab21f 3134static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
1cd6dbd3
YH		 3135 struct mlx5_ib_sq *sq, u8 tx_affinity,
3136 struct ib_pd *pd)
13eab21f
AH		 3137{
3138 void *in;
3139 void *tisc;
3140 int inlen;
3141 int err;
3142
3143 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 3144 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 3145 if (!in)
3146 return -ENOMEM;
3147
3148 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
1cd6dbd3 3149 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
13eab21f
AH		 3150
3151 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
3152 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
3153
e0b4b472 3154 err = mlx5_core_modify_tis(dev, sq->tisn, in);
13eab21f
AH		 3155
3156 kvfree(in);
3157
3158 return err;
3159}
3160
f18e26af 3161static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
2b880b2e
MZ		 3162 u32 lqpn, u32 rqpn)
3163
3164{
3165 u32 fl = ah->grh.flow_label;
2b880b2e
MZ		 3166
3167 if (!fl)
3168 fl = rdma_calc_flow_label(lqpn, rqpn);
3169
f18e26af 3170 MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
2b880b2e
MZ		 3171}
3172
75850d0b 3173static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
f18e26af
LR		 3174 const struct rdma_ah_attr *ah, void *path, u8 port,
3175 int attr_mask, u32 path_flags,
3176 const struct ib_qp_attr *attr, bool alt)
e126ba97 3177{
d8966fcd 3178 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 3179 int err;
ed88451e 3180 enum ib_gid_type gid_type;
d8966fcd
DC		 3181 u8 ah_flags = rdma_ah_get_ah_flags(ah);
3182 u8 sl = rdma_ah_get_sl(ah);
e126ba97 3183
e126ba97 3184 if (attr_mask & IB_QP_PKEY_INDEX)
f18e26af
LR		 3185 MLX5_SET(ads, path, pkey_index,
3186 alt ? attr->alt_pkey_index : attr->pkey_index);
e126ba97 3187
d8966fcd
DC		 3188 if (ah_flags & IB_AH_GRH) {
3189 if (grh->sgid_index >=
938fe83c 3190 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 3191 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 3192 grh->sgid_index,
938fe83c 3193 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 3194 return -EINVAL;
3195 }
2811ba51 3196 }
44c58487
DC		 3197
3198 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 3199 if (!(ah_flags & IB_AH_GRH))
2811ba51 3200 return -EINVAL;
47ec3866 3201
f18e26af
LR		 3202 ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
3203 ah->roce.dmac);
2b880b2e
MZ		 3204 if ((qp->ibqp.qp_type == IB_QPT_RC ||
3205 qp->ibqp.qp_type == IB_QPT_UC ||
3206 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3207 qp->ibqp.qp_type == IB_QPT_XRC_TGT) &&
3208 (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) &&
3209 (attr_mask & IB_QP_DEST_QPN))
3210 mlx5_set_path_udp_sport(path, ah,
3211 qp->ibqp.qp_num,
3212 attr->dest_qp_num);
f18e26af 3213 MLX5_SET(ads, path, eth_prio, sl & 0x7);
47ec3866 3214 gid_type = ah->grh.sgid_attr->gid_type;
ed88451e 3215 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
f18e26af 3216 MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
2811ba51 3217 } else {
f18e26af
LR		 3218 MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
3219 MLX5_SET(ads, path, free_ar,
3220 !!(path_flags & MLX5_PATH_FLAG_FREE_AR));
3221 MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
3222 MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
3223 MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
3224 MLX5_SET(ads, path, sl, sl);
2811ba51
AS		 3225 }
3226
d8966fcd 3227 if (ah_flags & IB_AH_GRH) {
f18e26af
LR		 3228 MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
3229 MLX5_SET(ads, path, hop_limit, grh->hop_limit);
3230 MLX5_SET(ads, path, tclass, grh->traffic_class);
3231 MLX5_SET(ads, path, flow_label, grh->flow_label);
3232 memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
3233 sizeof(grh->dgid.raw));
e126ba97
EC		 3234 }
3235
d8966fcd 3236 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 3237 if (err < 0)
3238 return err;
f18e26af
LR		 3239 MLX5_SET(ads, path, stat_rate, err);
3240 MLX5_SET(ads, path, vhca_port_num, port);
e126ba97 3241
e126ba97 3242 if (attr_mask & IB_QP_TIMEOUT)
f18e26af
LR		 3243 MLX5_SET(ads, path, ack_timeout,
3244 alt ? attr->alt_timeout : attr->timeout);
e126ba97 3245
75850d0b 3246 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
3247 return modify_raw_packet_eth_prio(dev->mdev,
3248 &qp->raw_packet_qp.sq,
1cd6dbd3 3249 sl & 0xf, qp->ibqp.pd);
75850d0b 3250
e126ba97
EC		 3251 return 0;
3252}
3253
3254static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
3255 [MLX5_QP_STATE_INIT] = {
3256 [MLX5_QP_STATE_INIT] = {
3257 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3258 MLX5_QP_OPTPAR_RAE |
3259 MLX5_QP_OPTPAR_RWE |
3260 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3261 MLX5_QP_OPTPAR_PRI_PORT |
3262 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3263 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
3264 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3265 MLX5_QP_OPTPAR_PRI_PORT |
3266 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3267 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3268 MLX5_QP_OPTPAR_Q_KEY |
3269 MLX5_QP_OPTPAR_PRI_PORT,
8f4426aa
JM		 3270 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3271 MLX5_QP_OPTPAR_RAE |
3272 MLX5_QP_OPTPAR_RWE |
3273 MLX5_QP_OPTPAR_PKEY_INDEX |
cfc1a89e
MG		 3274 MLX5_QP_OPTPAR_PRI_PORT |
3275 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3276 },
3277 [MLX5_QP_STATE_RTR] = {
3278 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3279 MLX5_QP_OPTPAR_RRE |
3280 MLX5_QP_OPTPAR_RAE |
3281 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3282 MLX5_QP_OPTPAR_PKEY_INDEX |
3283 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3284 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3285 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3286 MLX5_QP_OPTPAR_PKEY_INDEX |
3287 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3288 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
3289 MLX5_QP_OPTPAR_Q_KEY,
3290 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
3291 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 3292 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3293 MLX5_QP_OPTPAR_RRE |
3294 MLX5_QP_OPTPAR_RAE |
3295 MLX5_QP_OPTPAR_RWE |
cfc1a89e
MG		 3296 MLX5_QP_OPTPAR_PKEY_INDEX |
3297 MLX5_QP_OPTPAR_LAG_TX_AFF,
e126ba97
EC		 3298 },
3299 },
3300 [MLX5_QP_STATE_RTR] = {
3301 [MLX5_QP_STATE_RTS] = {
3302 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3303 MLX5_QP_OPTPAR_RRE |
3304 MLX5_QP_OPTPAR_RAE |
3305 MLX5_QP_OPTPAR_RWE |
3306 MLX5_QP_OPTPAR_PM_STATE |
3307 MLX5_QP_OPTPAR_RNR_TIMEOUT,
3308 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3309 MLX5_QP_OPTPAR_RWE |
3310 MLX5_QP_OPTPAR_PM_STATE,
3311 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
8f4426aa
JM		 3312 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
3313 MLX5_QP_OPTPAR_RRE |
3314 MLX5_QP_OPTPAR_RAE |
3315 MLX5_QP_OPTPAR_RWE |
3316 MLX5_QP_OPTPAR_PM_STATE |
3317 MLX5_QP_OPTPAR_RNR_TIMEOUT,
e126ba97
EC		 3318 },
3319 },
3320 [MLX5_QP_STATE_RTS] = {
3321 [MLX5_QP_STATE_RTS] = {
3322 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3323 MLX5_QP_OPTPAR_RAE |
3324 MLX5_QP_OPTPAR_RWE |
3325 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 3326 MLX5_QP_OPTPAR_PM_STATE |
3327 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 3328 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 3329 MLX5_QP_OPTPAR_PM_STATE |
3330 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 3331 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
3332 MLX5_QP_OPTPAR_SRQN |
3333 MLX5_QP_OPTPAR_CQN_RCV,
8f4426aa
JM		 3334 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RRE |
3335 MLX5_QP_OPTPAR_RAE |
3336 MLX5_QP_OPTPAR_RWE |
3337 MLX5_QP_OPTPAR_RNR_TIMEOUT |
3338 MLX5_QP_OPTPAR_PM_STATE |
3339 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 3340 },
3341 },
3342 [MLX5_QP_STATE_SQER] = {
3343 [MLX5_QP_STATE_RTS] = {
3344 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3345 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 3346 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 3347 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3348 MLX5_QP_OPTPAR_RWE |
3349 MLX5_QP_OPTPAR_RAE |
3350 MLX5_QP_OPTPAR_RRE,
8f4426aa
JM		 3351 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3352 MLX5_QP_OPTPAR_RWE |
3353 MLX5_QP_OPTPAR_RAE |
3354 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 3355 },
3356 },
3357};
3358
3359static int ib_nr_to_mlx5_nr(int ib_mask)
3360{
3361 switch (ib_mask) {
3362 case IB_QP_STATE:
3363 return 0;
3364 case IB_QP_CUR_STATE:
3365 return 0;
3366 case IB_QP_EN_SQD_ASYNC_NOTIFY:
3367 return 0;
3368 case IB_QP_ACCESS_FLAGS:
3369 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3370 MLX5_QP_OPTPAR_RAE;
3371 case IB_QP_PKEY_INDEX:
3372 return MLX5_QP_OPTPAR_PKEY_INDEX;
3373 case IB_QP_PORT:
3374 return MLX5_QP_OPTPAR_PRI_PORT;
3375 case IB_QP_QKEY:
3376 return MLX5_QP_OPTPAR_Q_KEY;
3377 case IB_QP_AV:
3378 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3379 MLX5_QP_OPTPAR_PRI_PORT;
3380 case IB_QP_PATH_MTU:
3381 return 0;
3382 case IB_QP_TIMEOUT:
3383 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3384 case IB_QP_RETRY_CNT:
3385 return MLX5_QP_OPTPAR_RETRY_COUNT;
3386 case IB_QP_RNR_RETRY:
3387 return MLX5_QP_OPTPAR_RNR_RETRY;
3388 case IB_QP_RQ_PSN:
3389 return 0;
3390 case IB_QP_MAX_QP_RD_ATOMIC:
3391 return MLX5_QP_OPTPAR_SRA_MAX;
3392 case IB_QP_ALT_PATH:
3393 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3394 case IB_QP_MIN_RNR_TIMER:
3395 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3396 case IB_QP_SQ_PSN:
3397 return 0;
3398 case IB_QP_MAX_DEST_RD_ATOMIC:
3399 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3400 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3401 case IB_QP_PATH_MIG_STATE:
3402 return MLX5_QP_OPTPAR_PM_STATE;
3403 case IB_QP_CAP:
3404 return 0;
3405 case IB_QP_DEST_QPN:
3406 return 0;
3407 }
3408 return 0;
3409}
3410
3411static int ib_mask_to_mlx5_opt(int ib_mask)
3412{
3413 int result = 0;
3414 int i;
3415
3416 for (i = 0; i < 8 * sizeof(int); i++) {
3417 if ((1 << i) & ib_mask)
3418 result |= ib_nr_to_mlx5_nr(1 << i);
3419 }
3420
3421 return result;
3422}
3423
34d57585
YH		 3424static int modify_raw_packet_qp_rq(
3425 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3426 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3427{
3428 void *in;
3429 void *rqc;
3430 int inlen;
3431 int err;
3432
3433 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 3434 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3435 if (!in)
3436 return -ENOMEM;
3437
3438 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
34d57585 3439 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3440
3441 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3442 MLX5_SET(rqc, rqc, state, new_state);
3443
eb49ab0c
AV		 3444 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3445 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3446 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 3447 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 3448 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3449 } else
5a738b5d
JG		 3450 dev_info_once(
3451 &dev->ib_dev.dev,
3452 "RAW PACKET QP counters are not supported on current FW\n");
eb49ab0c
AV		 3453 }
3454
e0b4b472 3455 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in);
ad5f8e96 3456 if (err)
3457 goto out;
3458
3459 rq->state = new_state;
3460
3461out:
3462 kvfree(in);
3463 return err;
3464}
3465
c14003f0
YH		 3466static int modify_raw_packet_qp_sq(
3467 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3468 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
ad5f8e96 3469{
7d29f349 3470 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 3471 struct mlx5_rate_limit old_rl = ibqp->rl;
3472 struct mlx5_rate_limit new_rl = old_rl;
3473 bool new_rate_added = false;
7d29f349 3474 u16 rl_index = 0;
ad5f8e96 3475 void *in;
3476 void *sqc;
3477 int inlen;
3478 int err;
3479
3480 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 3481 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 3482 if (!in)
3483 return -ENOMEM;
3484
c14003f0 3485 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
ad5f8e96 3486 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3487
3488 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3489 MLX5_SET(sqc, sqc, state, new_state);
3490
7d29f349
BW		 3491 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3492 if (new_state != MLX5_SQC_STATE_RDY)
3493 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3494 __func__);
3495 else
61147f39 3496 new_rl = raw_qp_param->rl;
7d29f349
BW		 3497 }
3498
61147f39
BW		 3499 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3500 if (new_rl.rate) {
3501 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 3502 if (err) {
61147f39
BW		 3503 pr_err("Failed configuring rate limit(err %d): \
3504 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3505 err, new_rl.rate, new_rl.max_burst_sz,
3506 new_rl.typical_pkt_sz);
3507
7d29f349
BW		 3508 goto out;
3509 }
61147f39 3510 new_rate_added = true;
7d29f349
BW		 3511 }
3512
3513 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 3514 /* index 0 means no limit */
7d29f349
BW		 3515 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3516 }
3517
e0b4b472 3518 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in);
7d29f349
BW		 3519 if (err) {
3520 /* Remove new rate from table if failed */
61147f39
BW		 3521 if (new_rate_added)
3522 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 3523 goto out;
7d29f349
BW		 3524 }
3525
3526 /* Only remove the old rate after new rate was set */
c8973df2
RW		 3527 if ((old_rl.rate && !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3528 (new_state != MLX5_SQC_STATE_RDY)) {
61147f39 3529 mlx5_rl_remove_rate(dev, &old_rl);
c8973df2
RW		 3530 if (new_state != MLX5_SQC_STATE_RDY)
3531 memset(&new_rl, 0, sizeof(new_rl));
3532 }
ad5f8e96 3533
61147f39 3534 ibqp->rl = new_rl;
ad5f8e96 3535 sq->state = new_state;
3536
3537out:
3538 kvfree(in);
3539 return err;
3540}
3541
3542static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 3543 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3544 u8 tx_affinity)
ad5f8e96 3545{
3546 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3547 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3548 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 3549 int modify_rq = !!qp->rq.wqe_cnt;
3550 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 3551 int rq_state;
3552 int sq_state;
3553 int err;
3554
0680efa2 3555 switch (raw_qp_param->operation) {
ad5f8e96 3556 case MLX5_CMD_OP_RST2INIT_QP:
3557 rq_state = MLX5_RQC_STATE_RDY;
c94e272b 3558 sq_state = MLX5_SQC_STATE_RST;
ad5f8e96 3559 break;
3560 case MLX5_CMD_OP_2ERR_QP:
3561 rq_state = MLX5_RQC_STATE_ERR;
3562 sq_state = MLX5_SQC_STATE_ERR;
3563 break;
3564 case MLX5_CMD_OP_2RST_QP:
3565 rq_state = MLX5_RQC_STATE_RST;
3566 sq_state = MLX5_SQC_STATE_RST;
3567 break;
ad5f8e96 3568 case MLX5_CMD_OP_RTR2RTS_QP:
3569 case MLX5_CMD_OP_RTS2RTS_QP:
c94e272b
MG		 3570 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT)
3571 return -EINVAL;
3572
3573 modify_rq = 0;
3574 sq_state = MLX5_SQC_STATE_RDY;
7d29f349
BW		 3575 break;
3576 case MLX5_CMD_OP_INIT2INIT_QP:
3577 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 3578 if (raw_qp_param->set_mask)
3579 return -EINVAL;
3580 else
3581 return 0;
ad5f8e96 3582 default:
3583 WARN_ON(1);
3584 return -EINVAL;
3585 }
3586
7d29f349 3587 if (modify_rq) {
34d57585
YH		 3588 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3589 qp->ibqp.pd);
ad5f8e96 3590 if (err)
3591 return err;
3592 }
3593
7d29f349 3594 if (modify_sq) {
d5ed8ac3
MB		 3595 struct mlx5_flow_handle *flow_rule;
3596
13eab21f
AH		 3597 if (tx_affinity) {
3598 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
1cd6dbd3
YH		 3599 tx_affinity,
3600 qp->ibqp.pd);
13eab21f
AH		 3601 if (err)
3602 return err;
3603 }
3604
d5ed8ac3
MB		 3605 flow_rule = create_flow_rule_vport_sq(dev, sq,
3606 raw_qp_param->port);
3607 if (IS_ERR(flow_rule))
1db86318 3608 return PTR_ERR(flow_rule);
d5ed8ac3
MB		 3609
3610 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3611 raw_qp_param, qp->ibqp.pd);
3612 if (err) {
3613 if (flow_rule)
3614 mlx5_del_flow_rules(flow_rule);
3615 return err;
3616 }
3617
3618 if (flow_rule) {
3619 destroy_flow_rule_vport_sq(sq);
3620 sq->flow_rule = flow_rule;
3621 }
3622
3623 return err;
13eab21f 3624 }
ad5f8e96 3625
3626 return 0;
3627}
3628
5163b274
MG		 3629static unsigned int get_tx_affinity_rr(struct mlx5_ib_dev *dev,
3630 struct ib_udata *udata)
c6a21c38 3631{
89944450
SR		 3632 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3633 udata, struct mlx5_ib_ucontext, ibucontext);
5163b274
MG		 3634 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3635 atomic_t *tx_port_affinity;
c6a21c38 3636
5163b274
MG		 3637 if (ucontext)
3638 tx_port_affinity = &ucontext->tx_port_affinity;
3639 else
3640 tx_port_affinity = &dev->port[port_num].roce.tx_port_affinity;
3641
3642 return (unsigned int)atomic_add_return(1, tx_port_affinity) %
3643 MLX5_MAX_PORTS + 1;
3644}
3645
3646static bool qp_supports_affinity(struct ib_qp *qp)
3647{
5163b274 3648 if ((qp->qp_type == IB_QPT_RC) ||
cfc1a89e 3649 (qp->qp_type == IB_QPT_UD) ||
5163b274
MG		 3650 (qp->qp_type == IB_QPT_UC) ||
3651 (qp->qp_type == IB_QPT_RAW_PACKET) ||
3652 (qp->qp_type == IB_QPT_XRC_INI) ||
3653 (qp->qp_type == IB_QPT_XRC_TGT))
3654 return true;
3655 return false;
3656}
3657
cfc1a89e
MG		 3658static unsigned int get_tx_affinity(struct ib_qp *qp,
3659 const struct ib_qp_attr *attr,
3660 int attr_mask, u8 init,
5163b274
MG		 3661 struct ib_udata *udata)
3662{
3663 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3664 udata, struct mlx5_ib_ucontext, ibucontext);
3665 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3666 struct mlx5_ib_qp *mqp = to_mqp(qp);
3667 struct mlx5_ib_qp_base *qp_base;
3668 unsigned int tx_affinity;
3669
802dcc7f
MZ		 3670 if (!(mlx5_ib_lag_should_assign_affinity(dev) &&
3671 qp_supports_affinity(qp)))
5163b274
MG		 3672 return 0;
3673
cfc1a89e
MG		 3674 if (mqp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
3675 tx_affinity = mqp->gsi_lag_port;
3676 else if (init)
3677 tx_affinity = get_tx_affinity_rr(dev, udata);
3678 else if ((attr_mask & IB_QP_AV) && attr->xmit_slave)
3679 tx_affinity =
3680 mlx5_lag_get_slave_port(dev->mdev, attr->xmit_slave);
3681 else
3682 return 0;
5163b274
MG		 3683
3684 qp_base = &mqp->trans_qp.base;
3685 if (ucontext)
c6a21c38 3686 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
5163b274
MG		 3687 tx_affinity, qp_base->mqp.qpn, ucontext);
3688 else
c6a21c38 3689 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
5163b274
MG		 3690 tx_affinity, qp_base->mqp.qpn);
3691 return tx_affinity;
c6a21c38
MD		 3692}
3693
d14133dd
MZ		 3694static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
3695 struct rdma_counter *counter)
3696{
3697 struct mlx5_ib_dev *dev = to_mdev(qp->device);
64bae2d4 3698 u32 in[MLX5_ST_SZ_DW(rts2rts_qp_in)] = {};
d14133dd 3699 struct mlx5_ib_qp *mqp = to_mqp(qp);
d14133dd
MZ		 3700 struct mlx5_ib_qp_base *base;
3701 u32 set_id;
64bae2d4 3702 u32 *qpc;
d14133dd 3703
3e1f000f 3704 if (counter)
d14133dd 3705 set_id = counter->id;
3e1f000f
PP		 3706 else
3707 set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
d14133dd
MZ		 3708
3709 base = &mqp->trans_qp.base;
64bae2d4
LR		 3710 MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
3711 MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);
3712 MLX5_SET(rts2rts_qp_in, in, uid, base->mqp.uid);
3713 MLX5_SET(rts2rts_qp_in, in, opt_param_mask,
3714 MLX5_QP_OPTPAR_COUNTER_SET_ID);
3715
3716 qpc = MLX5_ADDR_OF(rts2rts_qp_in, in, qpc);
3717 MLX5_SET(qpc, qpc, counter_set_id, set_id);
3718 return mlx5_cmd_exec_in(dev->mdev, rts2rts_qp, in);
d14133dd
MZ		 3719}
3720
e126ba97
EC		 3721static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3722 const struct ib_qp_attr *attr, int attr_mask,
89944450
SR		 3723 enum ib_qp_state cur_state,
3724 enum ib_qp_state new_state,
3725 const struct mlx5_ib_modify_qp *ucmd,
50aec2c3 3726 struct mlx5_ib_modify_qp_resp *resp,
89944450 3727 struct ib_udata *udata)
e126ba97 3728{
427c1e7b 3729 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3730 [MLX5_QP_STATE_RST] = {
3731 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3732 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3733 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3734 },
3735 [MLX5_QP_STATE_INIT] = {
3736 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3737 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3738 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3739 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3740 },
3741 [MLX5_QP_STATE_RTR] = {
3742 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3743 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3744 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3745 },
3746 [MLX5_QP_STATE_RTS] = {
3747 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3748 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3749 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3750 },
3751 [MLX5_QP_STATE_SQD] = {
3752 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3753 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3754 },
3755 [MLX5_QP_STATE_SQER] = {
3756 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3757 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3758 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3759 },
3760 [MLX5_QP_STATE_ERR] = {
3761 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3762 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3763 }
3764 };
3765
e126ba97
EC		 3766 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3767 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 3768 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97 3769 struct mlx5_ib_cq *send_cq, *recv_cq;
e126ba97
EC		 3770 struct mlx5_ib_pd *pd;
3771 enum mlx5_qp_state mlx5_cur, mlx5_new;
f18e26af 3772 void *qpc, *pri_path, *alt_path;
cfc1a89e 3773 enum mlx5_qp_optpar optpar = 0;
d14133dd 3774 u32 set_id = 0;
e126ba97
EC		 3775 int mlx5_st;
3776 int err;
427c1e7b 3777 u16 op;
13eab21f 3778 u8 tx_affinity = 0;
e126ba97 3779
7aede1a2 3780 mlx5_st = to_mlx5_st(qp->type);
55de9a77
LR		 3781 if (mlx5_st < 0)
3782 return -EINVAL;
3783
f18e26af
LR		 3784 qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
3785 if (!qpc)
e126ba97
EC		 3786 return -ENOMEM;
3787
029e88fd 3788 pd = to_mpd(qp->ibqp.pd);
f18e26af 3789 MLX5_SET(qpc, qpc, st, mlx5_st);
e126ba97
EC		 3790
3791 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
f18e26af 3792 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 3793 } else {
3794 switch (attr->path_mig_state) {
3795 case IB_MIG_MIGRATED:
f18e26af 3796 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 3797 break;
3798 case IB_MIG_REARM:
f18e26af 3799 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
e126ba97
EC		 3800 break;
3801 case IB_MIG_ARMED:
f18e26af 3802 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
e126ba97
EC		 3803 break;
3804 }
3805 }
3806
cfc1a89e 3807 tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
5163b274
MG		 3808 cur_state == IB_QPS_RESET &&
3809 new_state == IB_QPS_INIT, udata);
f18e26af
LR		 3810
3811 MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
3812 if (tx_affinity && new_state == IB_QPS_RTR &&
3813 MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
3814 optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
13eab21f 3815
d16e91da 3816 if (is_sqp(ibqp->qp_type)) {
f18e26af
LR		 3817 MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
3818 MLX5_SET(qpc, qpc, log_msg_max, 8);
c2e53b2c 3819 } else if ((ibqp->qp_type == IB_QPT_UD &&
2be08c30 3820 !(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
e126ba97 3821 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
f18e26af
LR		 3822 MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
3823 MLX5_SET(qpc, qpc, log_msg_max, 12);
e126ba97
EC		 3824 } else if (attr_mask & IB_QP_PATH_MTU) {
3825 if (attr->path_mtu < IB_MTU_256 ||
3826 attr->path_mtu > IB_MTU_4096) {
3827 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3828 err = -EINVAL;
3829 goto out;
3830 }
f18e26af
LR		 3831 MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
3832 MLX5_SET(qpc, qpc, log_msg_max,
3833 MLX5_CAP_GEN(dev->mdev, log_max_msg));
e126ba97
EC		 3834 }
3835
3836 if (attr_mask & IB_QP_DEST_QPN)
f18e26af
LR		 3837 MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
3838
3839 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
3840 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
e126ba97
EC		 3841
3842 if (attr_mask & IB_QP_PKEY_INDEX)
f18e26af 3843 MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
e126ba97
EC		 3844
3845 /* todo implement counter_index functionality */
3846
3847 if (is_sqp(ibqp->qp_type))
f18e26af 3848 MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
e126ba97
EC		 3849
3850 if (attr_mask & IB_QP_PORT)
f18e26af 3851 MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
e126ba97
EC		 3852
3853 if (attr_mask & IB_QP_AV) {
f18e26af
LR		 3854 err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
3855 attr_mask & IB_QP_PORT ? attr->port_num :
3856 qp->port,
f879ee8d 3857 attr_mask, 0, attr, false);
e126ba97
EC		 3858 if (err)
3859 goto out;
3860 }
3861
3862 if (attr_mask & IB_QP_TIMEOUT)
f18e26af 3863 MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
e126ba97
EC		 3864
3865 if (attr_mask & IB_QP_ALT_PATH) {
f18e26af 3866 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
f879ee8d 3867 attr->alt_port_num,
f18e26af
LR		 3868 attr_mask | IB_QP_PKEY_INDEX |
3869 IB_QP_TIMEOUT,
f879ee8d 3870 0, attr, true);
e126ba97
EC		 3871 if (err)
3872 goto out;
3873 }
3874
89ea94a7
MG		 3875 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3876 &send_cq, &recv_cq);
e126ba97 3877
f18e26af
LR		 3878 MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3879 if (send_cq)
3880 MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
3881 if (recv_cq)
3882 MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
3883
3884 MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
e126ba97
EC		 3885
3886 if (attr_mask & IB_QP_RNR_RETRY)
f18e26af 3887 MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
e126ba97
EC		 3888
3889 if (attr_mask & IB_QP_RETRY_CNT)
f18e26af 3890 MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
e126ba97 3891
f18e26af
LR		 3892 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
3893 MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
e126ba97
EC		 3894
3895 if (attr_mask & IB_QP_SQ_PSN)
f18e26af 3896 MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
e126ba97 3897
f18e26af
LR		 3898 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
3899 MLX5_SET(qpc, qpc, log_rra_max,
3900 ilog2(attr->max_dest_rd_atomic));
e126ba97 3901
a60109dc 3902 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
f18e26af 3903 err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
a60109dc
YC		 3904 if (err)
3905 goto out;
a60109dc 3906 }
e126ba97
EC		 3907
3908 if (attr_mask & IB_QP_MIN_RNR_TIMER)
f18e26af 3909 MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
e126ba97
EC		 3910
3911 if (attr_mask & IB_QP_RQ_PSN)
f18e26af 3912 MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
e126ba97
EC		 3913
3914 if (attr_mask & IB_QP_QKEY)
f18e26af 3915 MLX5_SET(qpc, qpc, q_key, attr->qkey);
e126ba97
EC		 3916
3917 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
f18e26af 3918 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 3919
0837e86a
MB		 3920 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3921 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3922 qp->port) - 1;
c2e53b2c
YH		 3923
3924 /* Underlay port should be used - index 0 function per port */
2be08c30 3925 if (qp->flags & IB_QP_CREATE_SOURCE_QPN)
c2e53b2c
YH		 3926 port_num = 0;
3927
d14133dd
MZ		 3928 if (ibqp->counter)
3929 set_id = ibqp->counter->id;
3930 else
3e1f000f 3931 set_id = mlx5_ib_get_counters_id(dev, port_num);
f18e26af 3932 MLX5_SET(qpc, qpc, counter_set_id, set_id);
0837e86a
MB		 3933 }
3934
e126ba97 3935 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
f18e26af 3936 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 3937
2be08c30 3938 if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
f18e26af 3939 MLX5_SET(qpc, qpc, deth_sqpn, 1);
e126ba97
EC		 3940
3941 mlx5_cur = to_mlx5_state(cur_state);
3942 mlx5_new = to_mlx5_state(new_state);
e126ba97 3943
427c1e7b 3944 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3945 !optab[mlx5_cur][mlx5_new]) {
3946 err = -EINVAL;
427c1e7b 3947 goto out;
5d414b17 3948 }
427c1e7b 3949
3950 op = optab[mlx5_cur][mlx5_new];
cfc1a89e 3951 optpar |= ib_mask_to_mlx5_opt(attr_mask);
e126ba97 3952 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3953
c2e53b2c 3954 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 3955 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
0680efa2
AV		 3956 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3957
3958 raw_qp_param.operation = op;
eb49ab0c 3959 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
d14133dd 3960 raw_qp_param.rq_q_ctr_id = set_id;
eb49ab0c
AV		 3961 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3962 }
7d29f349 3963
d5ed8ac3
MB		 3964 if (attr_mask & IB_QP_PORT)
3965 raw_qp_param.port = attr->port_num;
3966
7d29f349 3967 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3968 raw_qp_param.rl.rate = attr->rate_limit;
3969
3970 if (ucmd->burst_info.max_burst_sz) {
3971 if (attr->rate_limit &&
3972 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3973 raw_qp_param.rl.max_burst_sz =
3974 ucmd->burst_info.max_burst_sz;
3975 } else {
3976 err = -EINVAL;
3977 goto out;
3978 }
3979 }
3980
3981 if (ucmd->burst_info.typical_pkt_sz) {
3982 if (attr->rate_limit &&
3983 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3984 raw_qp_param.rl.typical_pkt_sz =
3985 ucmd->burst_info.typical_pkt_sz;
3986 } else {
3987 err = -EINVAL;
3988 goto out;
3989 }
3990 }
3991
7d29f349
BW		 3992 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3993 }
3994
13eab21f 3995 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3996 } else {
50aec2c3
LR		 3997 if (udata) {
3998 /* For the kernel flows, the resp will stay zero */
3999 resp->ece_options =
4000 MLX5_CAP_GEN(dev->mdev, ece_support) ?
4001 ucmd->ece_options : 0;
4002 resp->response_length = sizeof(*resp);
4003 }
5f62a521 4004 err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp,
50aec2c3 4005 &resp->ece_options);
0680efa2
AV		 4006 }
4007
e126ba97
EC		 4008 if (err)
4009 goto out;
4010
4011 qp->state = new_state;
4012
4013 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 4014 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 4015 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 4016 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 4017 if (attr_mask & IB_QP_PORT)
4018 qp->port = attr->port_num;
4019 if (attr_mask & IB_QP_ALT_PATH)
19098df2 4020 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 4021
4022 /*
4023 * If we moved a kernel QP to RESET, clean up all old CQ
4024 * entries and reinitialize the QP.
4025 */
75a45982
LR		 4026 if (new_state == IB_QPS_RESET &&
4027 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 4028 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 4029 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
4030 if (send_cq != recv_cq)
19098df2 4031 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 4032
4033 qp->rq.head = 0;
4034 qp->rq.tail = 0;
4035 qp->sq.head = 0;
4036 qp->sq.tail = 0;
4037 qp->sq.cur_post = 0;
34f4c955
GL		 4038 if (qp->sq.wqe_cnt)
4039 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
950bf4f1 4040 qp->sq.last_poll = 0;
e126ba97
EC		 4041 qp->db.db[MLX5_RCV_DBR] = 0;
4042 qp->db.db[MLX5_SND_DBR] = 0;
4043 }
4044
d14133dd
MZ		 4045 if ((new_state == IB_QPS_RTS) && qp->counter_pending) {
4046 err = __mlx5_ib_qp_set_counter(ibqp, ibqp->counter);
4047 if (!err)
4048 qp->counter_pending = 0;
4049 }
4050
e126ba97 4051out:
f18e26af 4052 kfree(qpc);
e126ba97
EC		 4053 return err;
4054}
4055
c32a4f29
MS		 4056static inline bool is_valid_mask(int mask, int req, int opt)
4057{
4058 if ((mask & req) != req)
4059 return false;
4060
4061 if (mask & ~(req | opt))
4062 return false;
4063
4064 return true;
4065}
4066
4067/* check valid transition for driver QP types
4068 * for now the only QP type that this function supports is DCI
4069 */
4070static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
4071 enum ib_qp_attr_mask attr_mask)
4072{
4073 int req = IB_QP_STATE;
4074 int opt = 0;
4075
99ed748e
MS		 4076 if (new_state == IB_QPS_RESET) {
4077 return is_valid_mask(attr_mask, req, opt);
4078 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
c32a4f29
MS		 4079 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
4080 return is_valid_mask(attr_mask, req, opt);
4081 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4082 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
4083 return is_valid_mask(attr_mask, req, opt);
4084 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4085 req |= IB_QP_PATH_MTU;
5ec0304c 4086 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
c32a4f29
MS		 4087 return is_valid_mask(attr_mask, req, opt);
4088 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4089 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
4090 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
4091 opt = IB_QP_MIN_RNR_TIMER;
4092 return is_valid_mask(attr_mask, req, opt);
4093 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
4094 opt = IB_QP_MIN_RNR_TIMER;
4095 return is_valid_mask(attr_mask, req, opt);
4096 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
4097 return is_valid_mask(attr_mask, req, opt);
4098 }
4099 return false;
4100}
4101
776a3906
MS		 4102/* mlx5_ib_modify_dct: modify a DCT QP
4103 * valid transitions are:
4104 * RESET to INIT: must set access_flags, pkey_index and port
4105 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
4106 * mtu, gid_index and hop_limit
4107 * Other transitions and attributes are illegal
4108 */
4109static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
a645a89d
LR		 4110 int attr_mask, struct mlx5_ib_modify_qp *ucmd,
4111 struct ib_udata *udata)
776a3906
MS		 4112{
4113 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4114 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4115 enum ib_qp_state cur_state, new_state;
776a3906
MS		 4116 int required = IB_QP_STATE;
4117 void *dctc;
71cab8ef 4118 int err;
776a3906
MS		 4119
4120 if (!(attr_mask & IB_QP_STATE))
4121 return -EINVAL;
4122
4123 cur_state = qp->state;
4124 new_state = attr->qp_state;
4125
4126 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
a645a89d
LR		 4127 if (MLX5_CAP_GEN(dev->mdev, ece_support) && ucmd->ece_options)
4128 /*
4129 * DCT doesn't initialize QP till modify command is executed,
4130 * so we need to overwrite previously set ECE field if user
4131 * provided any value except zero, which means not set/not
4132 * valid.
4133 */
4134 MLX5_SET(dctc, dctc, ece, ucmd->ece_options);
4135
776a3906 4136 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3e1f000f
PP		 4137 u16 set_id;
4138
776a3906
MS		 4139 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
4140 if (!is_valid_mask(attr_mask, required, 0))
4141 return -EINVAL;
4142
4143 if (attr->port_num == 0 ||
4144 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
4145 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4146 attr->port_num, dev->num_ports);
4147 return -EINVAL;
4148 }
4149 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
4150 MLX5_SET(dctc, dctc, rre, 1);
4151 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
4152 MLX5_SET(dctc, dctc, rwe, 1);
4153 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
a60109dc
YC		 4154 int atomic_mode;
4155
4156 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
4157 if (atomic_mode < 0)
776a3906 4158 return -EOPNOTSUPP;
a60109dc
YC		 4159
4160 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
776a3906 4161 MLX5_SET(dctc, dctc, rae, 1);
776a3906
MS		 4162 }
4163 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
4164 MLX5_SET(dctc, dctc, port, attr->port_num);
3e1f000f
PP		 4165
4166 set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
4167 MLX5_SET(dctc, dctc, counter_set_id, set_id);
776a3906
MS		 4168 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4169 struct mlx5_ib_modify_qp_resp resp = {};
a645a89d
LR		 4170 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {};
4171 u32 min_resp_len = offsetofend(typeof(resp), dctn);
776a3906
MS		 4172
4173 if (udata->outlen < min_resp_len)
4174 return -EINVAL;
a645a89d
LR		 4175 /*
4176 * If we don't have enough space for the ECE options,
4177 * simply indicate it with resp.response_length.
4178 */
4179 resp.response_length = (udata->outlen < sizeof(resp)) ?
4180 min_resp_len :
4181 sizeof(resp);
4182
776a3906
MS		 4183 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
4184 if (!is_valid_mask(attr_mask, required, 0))
4185 return -EINVAL;
4186 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
4187 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
4188 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
4189 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
4190 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
4191 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
4192
333fbaa0 4193 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct.in,
c5ae1954
YH		 4194 MLX5_ST_SZ_BYTES(create_dct_in), out,
4195 sizeof(out));
776a3906
MS		 4196 if (err)
4197 return err;
4198 resp.dctn = qp->dct.mdct.mqp.qpn;
a645a89d
LR		 4199 if (MLX5_CAP_GEN(dev->mdev, ece_support))
4200 resp.ece_options = MLX5_GET(create_dct_out, out, ece);
776a3906
MS		 4201 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4202 if (err) {
333fbaa0 4203 mlx5_core_destroy_dct(dev, &qp->dct.mdct);
776a3906
MS		 4204 return err;
4205 }
4206 } else {
4207 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
4208 return -EINVAL;
4209 }
71cab8ef
LR		 4210
4211 qp->state = new_state;
4212 return 0;
776a3906
MS		 4213}
4214
e126ba97
EC		 4215int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
4216 int attr_mask, struct ib_udata *udata)
4217{
4218 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
50aec2c3 4219 struct mlx5_ib_modify_qp_resp resp = {};
e126ba97 4220 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 4221 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 4222 enum ib_qp_type qp_type;
e126ba97
EC		 4223 enum ib_qp_state cur_state, new_state;
4224 int err = -EINVAL;
4225 int port;
4226
28d61370
YH		 4227 if (ibqp->rwq_ind_tbl)
4228 return -ENOSYS;
4229
61147f39 4230 if (udata && udata->inlen) {
5f62a521 4231 if (udata->inlen < offsetofend(typeof(ucmd), ece_options))
61147f39
BW		 4232 return -EINVAL;
4233
4234 if (udata->inlen > sizeof(ucmd) &&
4235 !ib_is_udata_cleared(udata, sizeof(ucmd),
4236 udata->inlen - sizeof(ucmd)))
4237 return -EOPNOTSUPP;
4238
4239 if (ib_copy_from_udata(&ucmd, udata,
4240 min(udata->inlen, sizeof(ucmd))))
4241 return -EFAULT;
4242
4243 if (ucmd.comp_mask ||
61147f39
BW		 4244 memchr_inv(&ucmd.burst_info.reserved, 0,
4245 sizeof(ucmd.burst_info.reserved)))
4246 return -EOPNOTSUPP;
5f62a521 4247
61147f39
BW		 4248 }
4249
d16e91da
HE		 4250 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4251 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
4252
7aede1a2
LR		 4253 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? IB_QPT_GSI :
4254 qp->type;
c32a4f29 4255
a645a89d
LR		 4256 if (qp_type == MLX5_IB_QPT_DCT)
4257 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, &ucmd, udata);
d16e91da 4258
e126ba97
EC		 4259 mutex_lock(&qp->mutex);
4260
4261 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
4262 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
4263
2811ba51
AS		 4264 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
4265 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2811ba51
AS		 4266 }
4267
2be08c30 4268 if (qp->flags & IB_QP_CREATE_SOURCE_QPN) {
c2e53b2c
YH		 4269 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
4270 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
4271 attr_mask);
4272 goto out;
4273 }
4274 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29 4275 qp_type != MLX5_IB_QPT_DCI &&
d31131bb
KH		 4276 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
4277 attr_mask)) {
158abf86
HE		 4278 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4279 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 4280 goto out;
c32a4f29
MS		 4281 } else if (qp_type == MLX5_IB_QPT_DCI &&
4282 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
4283 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
4284 cur_state, new_state, qp_type, attr_mask);
4285 goto out;
158abf86 4286 }
e126ba97
EC		 4287
4288 if ((attr_mask & IB_QP_PORT) &&
938fe83c 4289 (attr->port_num == 0 ||
508562d6 4290 attr->port_num > dev->num_ports)) {
158abf86
HE		 4291 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
4292 attr->port_num, dev->num_ports);
e126ba97 4293 goto out;
158abf86 4294 }
e126ba97
EC		 4295
4296 if (attr_mask & IB_QP_PKEY_INDEX) {
4297 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 4298 if (attr->pkey_index >=
158abf86
HE		 4299 dev->mdev->port_caps[port - 1].pkey_table_len) {
4300 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
4301 attr->pkey_index);
e126ba97 4302 goto out;
158abf86 4303 }
e126ba97
EC		 4304 }
4305
4306 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 4307 attr->max_rd_atomic >
158abf86
HE		 4308 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
4309 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
4310 attr->max_rd_atomic);
e126ba97 4311 goto out;
158abf86 4312 }
e126ba97
EC		 4313
4314 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 4315 attr->max_dest_rd_atomic >
158abf86
HE		 4316 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
4317 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
4318 attr->max_dest_rd_atomic);
e126ba97 4319 goto out;
158abf86 4320 }
e126ba97
EC		 4321
4322 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
4323 err = 0;
4324 goto out;
4325 }
4326
61147f39 4327 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
50aec2c3
LR		 4328 new_state, &ucmd, &resp, udata);
4329
4330 /* resp.response_length is set in ECE supported flows only */
4331 if (!err && resp.response_length &&
4332 udata->outlen >= resp.response_length)
6512f11d
LR		 4333 /* Return -EFAULT to the user and expect him to destroy QP. */
4334 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97
EC		 4335
4336out:
4337 mutex_unlock(&qp->mutex);
4338 return err;
4339}
4340
e126ba97
EC		 4341static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4342{
4343 switch (mlx5_state) {
4344 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4345 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4346 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4347 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4348 case MLX5_QP_STATE_SQ_DRAINING:
4349 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4350 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4351 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4352 default: return -1;
4353 }
4354}
4355
4356static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4357{
4358 switch (mlx5_mig_state) {
4359 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4360 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4361 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4362 default: return -1;
4363 }
4364}
4365
38349389 4366static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
70bd7fb8 4367 struct rdma_ah_attr *ah_attr, void *path)
e126ba97 4368{
70bd7fb8
LR		 4369 int port = MLX5_GET(ads, path, vhca_port_num);
4370 int static_rate;
e126ba97 4371
d8966fcd 4372 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4373
70bd7fb8 4374 if (!port || port > ibdev->num_ports)
e126ba97
EC		 4375 return;
4376
70bd7fb8 4377 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port);
ae59c3f0 4378
70bd7fb8
LR		 4379 rdma_ah_set_port_num(ah_attr, port);
4380 rdma_ah_set_sl(ah_attr, MLX5_GET(ads, path, sl));
d8966fcd 4381
70bd7fb8
LR		 4382 rdma_ah_set_dlid(ah_attr, MLX5_GET(ads, path, rlid));
4383 rdma_ah_set_path_bits(ah_attr, MLX5_GET(ads, path, mlid));
2d7e3ff7 4384
70bd7fb8
LR		 4385 static_rate = MLX5_GET(ads, path, stat_rate);
4386 rdma_ah_set_static_rate(ah_attr, static_rate ? static_rate - 5 : 0);
4387 if (MLX5_GET(ads, path, grh) ||
2d7e3ff7 4388 ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
70bd7fb8
LR		 4389 rdma_ah_set_grh(ah_attr, NULL, MLX5_GET(ads, path, flow_label),
4390 MLX5_GET(ads, path, src_addr_index),
4391 MLX5_GET(ads, path, hop_limit),
4392 MLX5_GET(ads, path, tclass));
d4433557 4393 rdma_ah_set_dgid_raw(ah_attr, MLX5_ADDR_OF(ads, path, rgid_rip));
e126ba97
EC		 4394 }
4395}
4396
6d2f89df 4397static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4398 struct mlx5_ib_sq *sq,
4399 u8 *sq_state)
4400{
6d2f89df 4401 int err;
4402
28160771 4403 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
6d2f89df 4404 if (err)
4405 goto out;
6d2f89df 4406 sq->state = *sq_state;
4407
4408out:
6d2f89df 4409 return err;
4410}
4411
4412static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4413 struct mlx5_ib_rq *rq,
4414 u8 *rq_state)
4415{
4416 void *out;
4417 void *rqc;
4418 int inlen;
4419 int err;
4420
4421 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4422 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4423 if (!out)
4424 return -ENOMEM;
4425
4426 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4427 if (err)
4428 goto out;
4429
4430 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4431 *rq_state = MLX5_GET(rqc, rqc, state);
4432 rq->state = *rq_state;
4433
4434out:
4435 kvfree(out);
4436 return err;
4437}
4438
4439static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4440 struct mlx5_ib_qp *qp, u8 *qp_state)
4441{
4442 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4443 [MLX5_RQC_STATE_RST] = {
4444 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4445 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4446 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4447 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4448 },
4449 [MLX5_RQC_STATE_RDY] = {
c94e272b 4450 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
6d2f89df 4451 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4452 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4453 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4454 },
4455 [MLX5_RQC_STATE_ERR] = {
4456 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4457 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4458 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4459 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4460 },
4461 [MLX5_RQ_STATE_NA] = {
c94e272b 4462 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE,
6d2f89df 4463 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4464 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4465 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4466 },
4467 };
4468
4469 *qp_state = sqrq_trans[rq_state][sq_state];
4470
4471 if (*qp_state == MLX5_QP_STATE_BAD) {
4472 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4473 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4474 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4475 return -EINVAL;
4476 }
4477
4478 if (*qp_state == MLX5_QP_STATE)
4479 *qp_state = qp->state;
4480
4481 return 0;
4482}
4483
4484static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4485 struct mlx5_ib_qp *qp,
4486 u8 *raw_packet_qp_state)
4487{
4488 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4489 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4490 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4491 int err;
4492 u8 sq_state = MLX5_SQ_STATE_NA;
4493 u8 rq_state = MLX5_RQ_STATE_NA;
4494
4495 if (qp->sq.wqe_cnt) {
4496 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4497 if (err)
4498 return err;
4499 }
4500
4501 if (qp->rq.wqe_cnt) {
4502 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4503 if (err)
4504 return err;
4505 }
4506
4507 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4508 raw_packet_qp_state);
4509}
4510
4511static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4512 struct ib_qp_attr *qp_attr)
e126ba97 4513{
09a7d9ec 4514 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
70bd7fb8 4515 void *qpc, *pri_path, *alt_path;
09a7d9ec 4516 u32 *outb;
70bd7fb8 4517 int err;
e126ba97 4518
09a7d9ec 4519 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4520 if (!outb)
4521 return -ENOMEM;
4522
333fbaa0 4523 err = mlx5_core_qp_query(dev, &qp->trans_qp.base.mqp, outb, outlen);
e126ba97 4524 if (err)
6d2f89df 4525 goto out;
e126ba97 4526
70bd7fb8
LR		 4527 qpc = MLX5_ADDR_OF(query_qp_out, outb, qpc);
4528
4529 qp->state = to_ib_qp_state(MLX5_GET(qpc, qpc, state));
4530 if (MLX5_GET(qpc, qpc, state) == MLX5_QP_STATE_SQ_DRAINING)
4531 qp_attr->sq_draining = 1;
4532
4533 qp_attr->path_mtu = MLX5_GET(qpc, qpc, mtu);
4534 qp_attr->path_mig_state = to_ib_mig_state(MLX5_GET(qpc, qpc, pm_state));
4535 qp_attr->qkey = MLX5_GET(qpc, qpc, q_key);
4536 qp_attr->rq_psn = MLX5_GET(qpc, qpc, next_rcv_psn);
4537 qp_attr->sq_psn = MLX5_GET(qpc, qpc, next_send_psn);
4538 qp_attr->dest_qp_num = MLX5_GET(qpc, qpc, remote_qpn);
09a7d9ec 4539
70bd7fb8
LR		 4540 if (MLX5_GET(qpc, qpc, rre))
4541 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_READ;
4542 if (MLX5_GET(qpc, qpc, rwe))
4543 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE;
4544 if (MLX5_GET(qpc, qpc, rae))
4545 qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_ATOMIC;
e126ba97 4546
70bd7fb8
LR		 4547 qp_attr->max_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_sra_max);
4548 qp_attr->max_dest_rd_atomic = 1 << MLX5_GET(qpc, qpc, log_rra_max);
4549 qp_attr->min_rnr_timer = MLX5_GET(qpc, qpc, min_rnr_nak);
4550 qp_attr->retry_cnt = MLX5_GET(qpc, qpc, retry_count);
4551 qp_attr->rnr_retry = MLX5_GET(qpc, qpc, rnr_retry);
4552
4553 pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
4554 alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
e126ba97
EC		 4555
4556 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
70bd7fb8
LR		 4557 to_rdma_ah_attr(dev, &qp_attr->ah_attr, pri_path);
4558 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, alt_path);
4559 qp_attr->alt_pkey_index = MLX5_GET(ads, alt_path, pkey_index);
4560 qp_attr->alt_port_num = MLX5_GET(ads, alt_path, vhca_port_num);
4561 }
4562
4563 qp_attr->pkey_index = MLX5_GET(ads, pri_path, pkey_index);
4564 qp_attr->port_num = MLX5_GET(ads, pri_path, vhca_port_num);
4565 qp_attr->timeout = MLX5_GET(ads, pri_path, ack_timeout);
4566 qp_attr->alt_timeout = MLX5_GET(ads, alt_path, ack_timeout);
6d2f89df 4567
4568out:
4569 kfree(outb);
4570 return err;
4571}
4572
776a3906
MS		 4573static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4574 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4575 struct ib_qp_init_attr *qp_init_attr)
4576{
4577 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4578 u32 *out;
4579 u32 access_flags = 0;
4580 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4581 void *dctc;
4582 int err;
4583 int supported_mask = IB_QP_STATE |
4584 IB_QP_ACCESS_FLAGS |
4585 IB_QP_PORT |
4586 IB_QP_MIN_RNR_TIMER |
4587 IB_QP_AV |
4588 IB_QP_PATH_MTU |
4589 IB_QP_PKEY_INDEX;
4590
4591 if (qp_attr_mask & ~supported_mask)
4592 return -EINVAL;
4593 if (mqp->state != IB_QPS_RTR)
4594 return -EINVAL;
4595
4596 out = kzalloc(outlen, GFP_KERNEL);
4597 if (!out)
4598 return -ENOMEM;
4599
333fbaa0 4600 err = mlx5_core_dct_query(dev, dct, out, outlen);
776a3906
MS		 4601 if (err)
4602 goto out;
4603
4604 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4605
4606 if (qp_attr_mask & IB_QP_STATE)
4607 qp_attr->qp_state = IB_QPS_RTR;
4608
4609 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4610 if (MLX5_GET(dctc, dctc, rre))
4611 access_flags |= IB_ACCESS_REMOTE_READ;
4612 if (MLX5_GET(dctc, dctc, rwe))
4613 access_flags |= IB_ACCESS_REMOTE_WRITE;
4614 if (MLX5_GET(dctc, dctc, rae))
4615 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4616 qp_attr->qp_access_flags = access_flags;
4617 }
4618
4619 if (qp_attr_mask & IB_QP_PORT)
4620 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4621 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4622 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4623 if (qp_attr_mask & IB_QP_AV) {
4624 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4625 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4626 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4627 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4628 }
4629 if (qp_attr_mask & IB_QP_PATH_MTU)
4630 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4631 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4632 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4633out:
4634 kfree(out);
4635 return err;
4636}
4637
6d2f89df 4638int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4639 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4640{
4641 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4642 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4643 int err = 0;
4644 u8 raw_packet_qp_state;
4645
28d61370
YH		 4646 if (ibqp->rwq_ind_tbl)
4647 return -ENOSYS;
4648
d16e91da
HE		 4649 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4650 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4651 qp_init_attr);
4652
c2e53b2c
YH		 4653 /* Not all of output fields are applicable, make sure to zero them */
4654 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4655 memset(qp_attr, 0, sizeof(*qp_attr));
4656
7aede1a2 4657 if (unlikely(qp->type == MLX5_IB_QPT_DCT))
776a3906
MS		 4658 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4659 qp_attr_mask, qp_init_attr);
4660
6d2f89df 4661 mutex_lock(&qp->mutex);
4662
c2e53b2c 4663 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2be08c30 4664 qp->flags & IB_QP_CREATE_SOURCE_QPN) {
6d2f89df 4665 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4666 if (err)
4667 goto out;
4668 qp->state = raw_packet_qp_state;
4669 qp_attr->port_num = 1;
4670 } else {
4671 err = query_qp_attr(dev, qp, qp_attr);
4672 if (err)
4673 goto out;
4674 }
4675
4676 qp_attr->qp_state = qp->state;
e126ba97
EC		 4677 qp_attr->cur_qp_state = qp_attr->qp_state;
4678 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4679 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4680
4681 if (!ibqp->uobject) {
0540d814 4682 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4683 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4684 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4685 } else {
4686 qp_attr->cap.max_send_wr = 0;
4687 qp_attr->cap.max_send_sge = 0;
4688 }
4689
0540d814
NO		 4690 qp_init_attr->qp_type = ibqp->qp_type;
4691 qp_init_attr->recv_cq = ibqp->recv_cq;
4692 qp_init_attr->send_cq = ibqp->send_cq;
4693 qp_init_attr->srq = ibqp->srq;
4694 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4695
4696 qp_init_attr->cap = qp_attr->cap;
4697
a8f3ea61 4698 qp_init_attr->create_flags = qp->flags;
051f2630 4699
e126ba97
EC		 4700 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4701 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4702
e126ba97
EC		 4703out:
4704 mutex_unlock(&qp->mutex);
4705 return err;
4706}
4707
28ad5f65 4708int mlx5_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata)
e126ba97 4709{
28ad5f65
LR		 4710 struct mlx5_ib_dev *dev = to_mdev(ibxrcd->device);
4711 struct mlx5_ib_xrcd *xrcd = to_mxrcd(ibxrcd);
e126ba97 4712
938fe83c 4713 if (!MLX5_CAP_GEN(dev->mdev, xrc))
28ad5f65 4714 return -EOPNOTSUPP;
e126ba97 4715
28ad5f65 4716 return mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
e126ba97
EC		 4717}
4718
28ad5f65 4719void mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
e126ba97
EC		 4720{
4721 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4722 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
e126ba97 4723
28ad5f65 4724 mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
e126ba97 4725}
79b20a6c 4726
350d0e4c
YH		 4727static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4728{
4729 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4730 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4731 struct ib_event event;
4732
4733 if (rwq->ibwq.event_handler) {
4734 event.device = rwq->ibwq.device;
4735 event.element.wq = &rwq->ibwq;
4736 switch (type) {
4737 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4738 event.event = IB_EVENT_WQ_FATAL;
4739 break;
4740 default:
4741 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4742 return;
4743 }
4744
4745 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4746 }
4747}
4748
03404e8a
MG		 4749static int set_delay_drop(struct mlx5_ib_dev *dev)
4750{
4751 int err = 0;
4752
4753 mutex_lock(&dev->delay_drop.lock);
4754 if (dev->delay_drop.activate)
4755 goto out;
4756
333fbaa0 4757 err = mlx5_core_set_delay_drop(dev, dev->delay_drop.timeout);
03404e8a
MG		 4758 if (err)
4759 goto out;
4760
4761 dev->delay_drop.activate = true;
4762out:
4763 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 4764
4765 if (!err)
4766 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 4767 return err;
4768}
4769
79b20a6c
YH		 4770static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4771 struct ib_wq_init_attr *init_attr)
4772{
4773 struct mlx5_ib_dev *dev;
4be6da1e 4774 int has_net_offloads;
79b20a6c
YH		 4775 __be64 *rq_pas0;
4776 void *in;
4777 void *rqc;
4778 void *wq;
4779 int inlen;
4780 int err;
4781
4782 dev = to_mdev(pd->device);
4783
4784 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 4785 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 4786 if (!in)
4787 return -ENOMEM;
4788
34d57585 4789 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
79b20a6c
YH		 4790 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4791 MLX5_SET(rqc, rqc, mem_rq_type,
4792 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4793 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4794 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4795 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4796 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4797 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 4798 MLX5_SET(wq, wq, wq_type,
4799 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4800 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 4801 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4802 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4803 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4804 err = -EOPNOTSUPP;
4805 goto out;
4806 } else {
4807 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4808 }
4809 }
79b20a6c 4810 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087 4811 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
c16339b6
MZ		 4812 /*
4813 * In Firmware number of strides in each WQE is:
4814 * "512 * 2^single_wqe_log_num_of_strides"
4815 * Values 3 to 8 are accepted as 10 to 15, 9 to 18 are
4816 * accepted as 0 to 9
4817 */
4818 static const u8 fw_map[] = { 10, 11, 12, 13, 14, 15, 0, 1,
4819 2, 3, 4, 5, 6, 7, 8, 9 };
ccc87087
NO		 4820 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4821 MLX5_SET(wq, wq, log_wqe_stride_size,
4822 rwq->single_stride_log_num_of_bytes -
4823 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
c16339b6
MZ		 4824 MLX5_SET(wq, wq, log_wqe_num_of_strides,
4825 fw_map[rwq->log_num_strides -
4826 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES]);
ccc87087 4827 }
79b20a6c
YH		 4828 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4829 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4830 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4831 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4832 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4833 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4834 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4835 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4836 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4837 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4838 err = -EOPNOTSUPP;
4839 goto out;
4840 }
4841 } else {
4842 MLX5_SET(rqc, rqc, vsd, 1);
4843 }
4be6da1e
NO		 4844 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4845 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4846 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4847 err = -EOPNOTSUPP;
4848 goto out;
4849 }
4850 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4851 }
03404e8a
MG		 4852 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4853 if (!(dev->ib_dev.attrs.raw_packet_caps &
4854 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4855 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4856 err = -EOPNOTSUPP;
4857 goto out;
4858 }
4859 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4860 }
79b20a6c
YH		 4861 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4862 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
333fbaa0 4863 err = mlx5_core_create_rq_tracked(dev, in, inlen, &rwq->core_qp);
03404e8a
MG		 4864 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4865 err = set_delay_drop(dev);
4866 if (err) {
4867 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4868 err);
333fbaa0 4869 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
03404e8a
MG		 4870 } else {
4871 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4872 }
4873 }
b1f74a84 4874out:
79b20a6c
YH		 4875 kvfree(in);
4876 return err;
4877}
4878
4879static int set_user_rq_size(struct mlx5_ib_dev *dev,
4880 struct ib_wq_init_attr *wq_init_attr,
4881 struct mlx5_ib_create_wq *ucmd,
4882 struct mlx5_ib_rwq *rwq)
4883{
4884 /* Sanity check RQ size before proceeding */
4885 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4886 return -EINVAL;
4887
4888 if (!ucmd->rq_wqe_count)
4889 return -EINVAL;
4890
4891 rwq->wqe_count = ucmd->rq_wqe_count;
4892 rwq->wqe_shift = ucmd->rq_wqe_shift;
0dfe4522
LR		 4893 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
4894 return -EINVAL;
4895
79b20a6c
YH		 4896 rwq->log_rq_stride = rwq->wqe_shift;
4897 rwq->log_rq_size = ilog2(rwq->wqe_count);
4898 return 0;
4899}
4900
c16339b6
MZ		 4901static bool log_of_strides_valid(struct mlx5_ib_dev *dev, u32 log_num_strides)
4902{
4903 if ((log_num_strides > MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4904 (log_num_strides < MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4905 return false;
4906
4907 if (!MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) &&
4908 (log_num_strides < MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES))
4909 return false;
4910
4911 return true;
4912}
4913
79b20a6c
YH		 4914static int prepare_user_rq(struct ib_pd *pd,
4915 struct ib_wq_init_attr *init_attr,
4916 struct ib_udata *udata,
4917 struct mlx5_ib_rwq *rwq)
4918{
4919 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4920 struct mlx5_ib_create_wq ucmd = {};
4921 int err;
4922 size_t required_cmd_sz;
4923
ccc87087
NO		 4924 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4925 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 4926 if (udata->inlen < required_cmd_sz) {
4927 mlx5_ib_dbg(dev, "invalid inlen\n");
4928 return -EINVAL;
4929 }
4930
4931 if (udata->inlen > sizeof(ucmd) &&
4932 !ib_is_udata_cleared(udata, sizeof(ucmd),
4933 udata->inlen - sizeof(ucmd))) {
4934 mlx5_ib_dbg(dev, "inlen is not supported\n");
4935 return -EOPNOTSUPP;
4936 }
4937
4938 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4939 mlx5_ib_dbg(dev, "copy failed\n");
4940 return -EFAULT;
4941 }
4942
ccc87087 4943 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 4944 mlx5_ib_dbg(dev, "invalid comp mask\n");
4945 return -EOPNOTSUPP;
ccc87087
NO		 4946 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4947 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4948 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4949 return -EOPNOTSUPP;
4950 }
4951 if ((ucmd.single_stride_log_num_of_bytes <
4952 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4953 (ucmd.single_stride_log_num_of_bytes >
4954 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4955 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4956 ucmd.single_stride_log_num_of_bytes,
4957 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4958 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4959 return -EINVAL;
4960 }
c16339b6
MZ		 4961 if (!log_of_strides_valid(dev,
4962 ucmd.single_wqe_log_num_of_strides)) {
4963 mlx5_ib_dbg(
4964 dev,
4965 "Invalid log num strides (%u. Range is %u - %u)\n",
4966 ucmd.single_wqe_log_num_of_strides,
4967 MLX5_CAP_GEN(dev->mdev, ext_stride_num_range) ?
4968 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES :
4969 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4970 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
ccc87087
NO		 4971 return -EINVAL;
4972 }
4973 rwq->single_stride_log_num_of_bytes =
4974 ucmd.single_stride_log_num_of_bytes;
4975 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4976 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4977 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 4978 }
4979
4980 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4981 if (err) {
4982 mlx5_ib_dbg(dev, "err %d\n", err);
4983 return err;
4984 }
4985
b0ea0fa5 4986 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
79b20a6c
YH		 4987 if (err) {
4988 mlx5_ib_dbg(dev, "err %d\n", err);
645ba597 4989 return err;
79b20a6c
YH		 4990 }
4991
4992 rwq->user_index = ucmd.user_index;
4993 return 0;
4994}
4995
4996struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4997 struct ib_wq_init_attr *init_attr,
4998 struct ib_udata *udata)
4999{
5000 struct mlx5_ib_dev *dev;
5001 struct mlx5_ib_rwq *rwq;
5002 struct mlx5_ib_create_wq_resp resp = {};
5003 size_t min_resp_len;
5004 int err;
5005
5006 if (!udata)
5007 return ERR_PTR(-ENOSYS);
5008
5009 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5010 if (udata->outlen && udata->outlen < min_resp_len)
5011 return ERR_PTR(-EINVAL);
5012
ba80013f
MG		 5013 if (!capable(CAP_SYS_RAWIO) &&
5014 init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP)
5015 return ERR_PTR(-EPERM);
5016
79b20a6c
YH		 5017 dev = to_mdev(pd->device);
5018 switch (init_attr->wq_type) {
5019 case IB_WQT_RQ:
5020 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5021 if (!rwq)
5022 return ERR_PTR(-ENOMEM);
5023 err = prepare_user_rq(pd, init_attr, udata, rwq);
5024 if (err)
5025 goto err;
5026 err = create_rq(rwq, pd, init_attr);
5027 if (err)
5028 goto err_user_rq;
5029 break;
5030 default:
5031 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5032 init_attr->wq_type);
5033 return ERR_PTR(-EINVAL);
5034 }
5035
350d0e4c 5036 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5037 rwq->ibwq.state = IB_WQS_RESET;
5038 if (udata->outlen) {
5039 resp.response_length = offsetof(typeof(resp), response_length) +
5040 sizeof(resp.response_length);
5041 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5042 if (err)
5043 goto err_copy;
5044 }
5045
350d0e4c
YH		 5046 rwq->core_qp.event = mlx5_ib_wq_event;
5047 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5048 return &rwq->ibwq;
5049
5050err_copy:
333fbaa0 5051 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
79b20a6c 5052err_user_rq:
bdeacabd 5053 destroy_user_rq(dev, pd, rwq, udata);
79b20a6c
YH		 5054err:
5055 kfree(rwq);
5056 return ERR_PTR(err);
5057}
5058
a49b1dc7 5059void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
79b20a6c
YH		 5060{
5061 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5062 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5063
333fbaa0 5064 mlx5_core_destroy_rq_tracked(dev, &rwq->core_qp);
bdeacabd 5065 destroy_user_rq(dev, wq->pd, rwq, udata);
79b20a6c 5066 kfree(rwq);
79b20a6c
YH		 5067}
5068
c5f90929
YH		 5069struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5070 struct ib_rwq_ind_table_init_attr *init_attr,
5071 struct ib_udata *udata)
5072{
5073 struct mlx5_ib_dev *dev = to_mdev(device);
5074 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5075 int sz = 1 << init_attr->log_ind_tbl_size;
5076 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5077 size_t min_resp_len;
5078 int inlen;
5079 int err;
5080 int i;
5081 u32 *in;
5082 void *rqtc;
5083
5084 if (udata->inlen > 0 &&
5085 !ib_is_udata_cleared(udata, 0,
5086 udata->inlen))
5087 return ERR_PTR(-EOPNOTSUPP);
5088
efd7f400
MG		 5089 if (init_attr->log_ind_tbl_size >
5090 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5091 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5092 init_attr->log_ind_tbl_size,
5093 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5094 return ERR_PTR(-EINVAL);
5095 }
5096
c5f90929
YH		 5097 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5098 if (udata->outlen && udata->outlen < min_resp_len)
5099 return ERR_PTR(-EINVAL);
5100
5101 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5102 if (!rwq_ind_tbl)
5103 return ERR_PTR(-ENOMEM);
5104
5105 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5106 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5107 if (!in) {
5108 err = -ENOMEM;
5109 goto err;
5110 }
5111
5112 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5113
5114 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5115 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5116
5117 for (i = 0; i < sz; i++)
5118 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5119
5deba86e
YH		 5120 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5121 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5122
c5f90929
YH		 5123 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5124 kvfree(in);
5125
5126 if (err)
5127 goto err;
5128
5129 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5130 if (udata->outlen) {
5131 resp.response_length = offsetof(typeof(resp), response_length) +
5132 sizeof(resp.response_length);
5133 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5134 if (err)
5135 goto err_copy;
5136 }
5137
5138 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5139
5140err_copy:
5deba86e 5141 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5142err:
5143 kfree(rwq_ind_tbl);
5144 return ERR_PTR(err);
5145}
5146
5147int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5148{
5149 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5150 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5151
5deba86e 5152 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
c5f90929
YH		 5153
5154 kfree(rwq_ind_tbl);
5155 return 0;
5156}
5157
79b20a6c
YH		 5158int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5159 u32 wq_attr_mask, struct ib_udata *udata)
5160{
5161 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5162 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5163 struct mlx5_ib_modify_wq ucmd = {};
5164 size_t required_cmd_sz;
5165 int curr_wq_state;
5166 int wq_state;
5167 int inlen;
5168 int err;
5169 void *rqc;
5170 void *in;
5171
5172 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5173 if (udata->inlen < required_cmd_sz)
5174 return -EINVAL;
5175
5176 if (udata->inlen > sizeof(ucmd) &&
5177 !ib_is_udata_cleared(udata, sizeof(ucmd),
5178 udata->inlen - sizeof(ucmd)))
5179 return -EOPNOTSUPP;
5180
5181 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5182 return -EFAULT;
5183
5184 if (ucmd.comp_mask || ucmd.reserved)
5185 return -EOPNOTSUPP;
5186
5187 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5188 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5189 if (!in)
5190 return -ENOMEM;
5191
5192 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5193
5194 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5195 wq_attr->curr_wq_state : wq->state;
5196 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5197 wq_attr->wq_state : curr_wq_state;
5198 if (curr_wq_state == IB_WQS_ERR)
5199 curr_wq_state = MLX5_RQC_STATE_ERR;
5200 if (wq_state == IB_WQS_ERR)
5201 wq_state = MLX5_RQC_STATE_ERR;
5202 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
34d57585 5203 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
79b20a6c
YH		 5204 MLX5_SET(rqc, rqc, state, wq_state);
5205
b1f74a84
NO		 5206 if (wq_attr_mask & IB_WQ_FLAGS) {
5207 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5208 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5209 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5210 mlx5_ib_dbg(dev, "VLAN offloads are not "
5211 "supported\n");
5212 err = -EOPNOTSUPP;
5213 goto out;
5214 }
5215 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5216 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5217 MLX5_SET(rqc, rqc, vsd,
5218 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5219 }
b1383aa6
NO		 5220
5221 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5222 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5223 err = -EOPNOTSUPP;
5224 goto out;
5225 }
b1f74a84
NO		 5226 }
5227
23a6964e 5228 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
3e1f000f
PP		 5229 u16 set_id;
5230
5231 set_id = mlx5_ib_get_counters_id(dev, 0);
23a6964e
MD		 5232 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5233 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5234 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3e1f000f 5235 MLX5_SET(rqc, rqc, counter_set_id, set_id);
23a6964e 5236 } else
5a738b5d
JG		 5237 dev_info_once(
5238 &dev->ib_dev.dev,
5239 "Receive WQ counters are not supported on current FW\n");
23a6964e
MD		 5240 }
5241
e0b4b472 5242 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in);
79b20a6c
YH		 5243 if (!err)
5244 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5245
b1f74a84
NO		 5246out:
5247 kvfree(in);
79b20a6c
YH		 5248 return err;
5249}
d0e84c0a
YH		 5250
5251struct mlx5_ib_drain_cqe {
5252 struct ib_cqe cqe;
5253 struct completion done;
5254};
5255
5256static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5257{
5258 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5259 struct mlx5_ib_drain_cqe,
5260 cqe);
5261
5262 complete(&cqe->done);
5263}
5264
5265/* This function returns only once the drained WR was completed */
5266static void handle_drain_completion(struct ib_cq *cq,
5267 struct mlx5_ib_drain_cqe *sdrain,
5268 struct mlx5_ib_dev *dev)
5269{
5270 struct mlx5_core_dev *mdev = dev->mdev;
5271
5272 if (cq->poll_ctx == IB_POLL_DIRECT) {
5273 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5274 ib_process_cq_direct(cq, -1);
5275 return;
5276 }
5277
5278 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5279 struct mlx5_ib_cq *mcq = to_mcq(cq);
5280 bool triggered = false;
5281 unsigned long flags;
5282
5283 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5284 /* Make sure that the CQ handler won't run if wasn't run yet */
5285 if (!mcq->mcq.reset_notify_added)
5286 mcq->mcq.reset_notify_added = 1;
5287 else
5288 triggered = true;
5289 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5290
5291 if (triggered) {
5292 /* Wait for any scheduled/running task to be ended */
5293 switch (cq->poll_ctx) {
5294 case IB_POLL_SOFTIRQ:
5295 irq_poll_disable(&cq->iop);
5296 irq_poll_enable(&cq->iop);
5297 break;
5298 case IB_POLL_WORKQUEUE:
5299 cancel_work_sync(&cq->work);
5300 break;
5301 default:
5302 WARN_ON_ONCE(1);
5303 }
5304 }
5305
5306 /* Run the CQ handler - this makes sure that the drain WR will
5307 * be processed if wasn't processed yet.
5308 */
4e0e2ea1 5309 mcq->mcq.comp(&mcq->mcq, NULL);
d0e84c0a
YH		 5310 }
5311
5312 wait_for_completion(&sdrain->done);
5313}
5314
5315void mlx5_ib_drain_sq(struct ib_qp *qp)
5316{
5317 struct ib_cq *cq = qp->send_cq;
5318 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5319 struct mlx5_ib_drain_cqe sdrain;
d34ac5cd 5320 const struct ib_send_wr *bad_swr;
d0e84c0a
YH		 5321 struct ib_rdma_wr swr = {
5322 .wr = {
5323 .next = NULL,
5324 { .wr_cqe = &sdrain.cqe, },
5325 .opcode = IB_WR_RDMA_WRITE,
5326 },
5327 };
5328 int ret;
5329 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5330 struct mlx5_core_dev *mdev = dev->mdev;
5331
5332 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5333 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5334 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5335 return;
5336 }
5337
5338 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5339 init_completion(&sdrain.done);
5340
029e88fd 5341 ret = mlx5_ib_post_send_drain(qp, &swr.wr, &bad_swr);
d0e84c0a
YH		 5342 if (ret) {
5343 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5344 return;
5345 }
5346
5347 handle_drain_completion(cq, &sdrain, dev);
5348}
5349
5350void mlx5_ib_drain_rq(struct ib_qp *qp)
5351{
5352 struct ib_cq *cq = qp->recv_cq;
5353 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5354 struct mlx5_ib_drain_cqe rdrain;
d34ac5cd
BVA		 5355 struct ib_recv_wr rwr = {};
5356 const struct ib_recv_wr *bad_rwr;
d0e84c0a
YH		 5357 int ret;
5358 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5359 struct mlx5_core_dev *mdev = dev->mdev;
5360
5361 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5362 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5363 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5364 return;
5365 }
5366
5367 rwr.wr_cqe = &rdrain.cqe;
5368 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5369 init_completion(&rdrain.done);
5370
029e88fd 5371 ret = mlx5_ib_post_recv_drain(qp, &rwr, &bad_rwr);
d0e84c0a
YH		 5372 if (ret) {
5373 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5374 return;
5375 }
5376
5377 handle_drain_completion(cq, &rdrain, dev);
5378}
d14133dd
MZ		 5379
5380/**
5381 * Bind a qp to a counter. If @counter is NULL then bind the qp to
5382 * the default counter
5383 */
5384int mlx5_ib_qp_set_counter(struct ib_qp *qp, struct rdma_counter *counter)
5385{
10189e8e 5386 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d14133dd
MZ		 5387 struct mlx5_ib_qp *mqp = to_mqp(qp);
5388 int err = 0;
5389
5390 mutex_lock(&mqp->mutex);
5391 if (mqp->state == IB_QPS_RESET) {
5392 qp->counter = counter;
5393 goto out;
5394 }
5395
10189e8e
MZ		 5396 if (!MLX5_CAP_GEN(dev->mdev, rts2rts_qp_counters_set_id)) {
5397 err = -EOPNOTSUPP;
5398 goto out;
5399 }
5400
d14133dd
MZ		 5401 if (mqp->state == IB_QPS_RTS) {
5402 err = __mlx5_ib_qp_set_counter(qp, counter);
5403 if (!err)
5404 qp->counter = counter;
5405
5406 goto out;
5407 }
5408
5409 mqp->counter_pending = 1;
5410 qp->counter = counter;
5411
5412out:
5413 mutex_unlock(&mqp->mutex);
5414 return err;
5415}
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