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IB/mlx5: Fix pkey_index length in the QP path record
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97
EC		 37#include "mlx5_ib.h"
38#include "user.h"
39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97
EC		 79
80static int is_qp0(enum ib_qp_type qp_type)
81{
82 return qp_type == IB_QPT_SMI;
83}
84
e126ba97
EC		 85static int is_sqp(enum ib_qp_type qp_type)
86{
87 return is_qp0(qp_type) || is_qp1(qp_type);
88}
89
90static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
91{
92 return mlx5_buf_offset(&qp->buf, offset);
93}
94
95static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
96{
97 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
98}
99
100void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
101{
102 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
103}
104
c1395a2a
HE		 105/**
106 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
107 *
108 * @qp: QP to copy from.
109 * @send: copy from the send queue when non-zero, use the receive queue
110 * otherwise.
111 * @wqe_index: index to start copying from. For send work queues, the
112 * wqe_index is in units of MLX5_SEND_WQE_BB.
113 * For receive work queue, it is the number of work queue
114 * element in the queue.
115 * @buffer: destination buffer.
116 * @length: maximum number of bytes to copy.
117 *
118 * Copies at least a single WQE, but may copy more data.
119 *
120 * Return: the number of bytes copied, or an error code.
121 */
122int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 123 void *buffer, u32 length,
124 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 125{
126 struct ib_device *ibdev = qp->ibqp.device;
127 struct mlx5_ib_dev *dev = to_mdev(ibdev);
128 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
129 size_t offset;
130 size_t wq_end;
19098df2 131 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 132 u32 first_copy_length;
133 int wqe_length;
134 int ret;
135
136 if (wq->wqe_cnt == 0) {
137 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
138 qp->ibqp.qp_type);
139 return -EINVAL;
140 }
141
142 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
143 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
144
145 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
146 return -EINVAL;
147
148 if (offset > umem->length ||
149 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
150 return -EINVAL;
151
152 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
153 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
154 if (ret)
155 return ret;
156
157 if (send) {
158 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
159 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
160
161 wqe_length = ds * MLX5_WQE_DS_UNITS;
162 } else {
163 wqe_length = 1 << wq->wqe_shift;
164 }
165
166 if (wqe_length <= first_copy_length)
167 return first_copy_length;
168
169 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
170 wqe_length - first_copy_length);
171 if (ret)
172 return ret;
173
174 return wqe_length;
175}
176
e126ba97
EC		 177static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
178{
179 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
180 struct ib_event event;
181
19098df2 182 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
183 /* This event is only valid for trans_qps */
184 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
185 }
e126ba97
EC		 186
187 if (ibqp->event_handler) {
188 event.device = ibqp->device;
189 event.element.qp = ibqp;
190 switch (type) {
191 case MLX5_EVENT_TYPE_PATH_MIG:
192 event.event = IB_EVENT_PATH_MIG;
193 break;
194 case MLX5_EVENT_TYPE_COMM_EST:
195 event.event = IB_EVENT_COMM_EST;
196 break;
197 case MLX5_EVENT_TYPE_SQ_DRAINED:
198 event.event = IB_EVENT_SQ_DRAINED;
199 break;
200 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
201 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
202 break;
203 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
204 event.event = IB_EVENT_QP_FATAL;
205 break;
206 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
207 event.event = IB_EVENT_PATH_MIG_ERR;
208 break;
209 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
210 event.event = IB_EVENT_QP_REQ_ERR;
211 break;
212 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
213 event.event = IB_EVENT_QP_ACCESS_ERR;
214 break;
215 default:
216 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
217 return;
218 }
219
220 ibqp->event_handler(&event, ibqp->qp_context);
221 }
222}
223
224static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
225 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
226{
227 int wqe_size;
228 int wq_size;
229
230 /* Sanity check RQ size before proceeding */
938fe83c 231 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 232 return -EINVAL;
233
234 if (!has_rq) {
235 qp->rq.max_gs = 0;
236 qp->rq.wqe_cnt = 0;
237 qp->rq.wqe_shift = 0;
0540d814
NO		 238 cap->max_recv_wr = 0;
239 cap->max_recv_sge = 0;
e126ba97
EC		 240 } else {
241 if (ucmd) {
242 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
243 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
244 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
245 qp->rq.max_post = qp->rq.wqe_cnt;
246 } else {
247 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
248 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
249 wqe_size = roundup_pow_of_two(wqe_size);
250 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
251 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
252 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 253 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 254 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
255 wqe_size,
938fe83c
SM		 256 MLX5_CAP_GEN(dev->mdev,
257 max_wqe_sz_rq));
e126ba97
EC		 258 return -EINVAL;
259 }
260 qp->rq.wqe_shift = ilog2(wqe_size);
261 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
262 qp->rq.max_post = qp->rq.wqe_cnt;
263 }
264 }
265
266 return 0;
267}
268
f0313965 269static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 270{
618af384 271 int size = 0;
e126ba97 272
f0313965 273 switch (attr->qp_type) {
e126ba97 274 case IB_QPT_XRC_INI:
b125a54b 275 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 276 /* fall through */
277 case IB_QPT_RC:
278 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 279 max(sizeof(struct mlx5_wqe_atomic_seg) +
280 sizeof(struct mlx5_wqe_raddr_seg),
281 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
282 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 283 break;
284
b125a54b
EC		 285 case IB_QPT_XRC_TGT:
286 return 0;
287
e126ba97 288 case IB_QPT_UC:
b125a54b 289 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 290 max(sizeof(struct mlx5_wqe_raddr_seg),
291 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
292 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 293 break;
294
295 case IB_QPT_UD:
f0313965
ES		 296 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
297 size += sizeof(struct mlx5_wqe_eth_pad) +
298 sizeof(struct mlx5_wqe_eth_seg);
299 /* fall through */
e126ba97 300 case IB_QPT_SMI:
d16e91da 301 case MLX5_IB_QPT_HW_GSI:
b125a54b 302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 303 sizeof(struct mlx5_wqe_datagram_seg);
304 break;
305
306 case MLX5_IB_QPT_REG_UMR:
b125a54b 307 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 308 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
309 sizeof(struct mlx5_mkey_seg);
310 break;
311
312 default:
313 return -EINVAL;
314 }
315
316 return size;
317}
318
319static int calc_send_wqe(struct ib_qp_init_attr *attr)
320{
321 int inl_size = 0;
322 int size;
323
f0313965 324 size = sq_overhead(attr);
e126ba97
EC		 325 if (size < 0)
326 return size;
327
328 if (attr->cap.max_inline_data) {
329 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
330 attr->cap.max_inline_data;
331 }
332
333 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 334 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
335 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
336 return MLX5_SIG_WQE_SIZE;
337 else
338 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 339}
340
341static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
342 struct mlx5_ib_qp *qp)
343{
344 int wqe_size;
345 int wq_size;
346
347 if (!attr->cap.max_send_wr)
348 return 0;
349
350 wqe_size = calc_send_wqe(attr);
351 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
352 if (wqe_size < 0)
353 return wqe_size;
354
938fe83c 355 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 356 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 357 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 358 return -EINVAL;
359 }
360
f0313965
ES		 361 qp->max_inline_data = wqe_size - sq_overhead(attr) -
362 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 363 attr->cap.max_inline_data = qp->max_inline_data;
364
e1e66cc2
SG		 365 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
366 qp->signature_en = true;
367
e126ba97
EC		 368 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
369 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 370 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 371 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 372 qp->sq.wqe_cnt,
373 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 374 return -ENOMEM;
375 }
e126ba97
EC		 376 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
377 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 378 qp->sq.max_post = wq_size / wqe_size;
379 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 380
381 return wq_size;
382}
383
384static int set_user_buf_size(struct mlx5_ib_dev *dev,
385 struct mlx5_ib_qp *qp,
19098df2 386 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 387 struct mlx5_ib_qp_base *base,
388 struct ib_qp_init_attr *attr)
e126ba97
EC		 389{
390 int desc_sz = 1 << qp->sq.wqe_shift;
391
938fe83c 392 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 393 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 394 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 395 return -EINVAL;
396 }
397
398 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
399 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
400 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
401 return -EINVAL;
402 }
403
404 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
405
938fe83c 406 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 407 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 408 qp->sq.wqe_cnt,
409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 410 return -EINVAL;
411 }
412
0fb2ed66 413 if (attr->qp_type == IB_QPT_RAW_PACKET) {
414 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
415 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
416 } else {
417 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
418 (qp->sq.wqe_cnt << 6);
419 }
e126ba97
EC		 420
421 return 0;
422}
423
424static int qp_has_rq(struct ib_qp_init_attr *attr)
425{
426 if (attr->qp_type == IB_QPT_XRC_INI ||
427 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
428 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
429 !attr->cap.max_recv_wr)
430 return 0;
431
432 return 1;
433}
434
c1be5232
EC		 435static int first_med_uuar(void)
436{
437 return 1;
438}
439
440static int next_uuar(int n)
441{
442 n++;
443
444 while (((n % 4) & 2))
445 n++;
446
447 return n;
448}
449
450static int num_med_uuar(struct mlx5_uuar_info *uuari)
451{
452 int n;
453
454 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
455 uuari->num_low_latency_uuars - 1;
456
457 return n >= 0 ? n : 0;
458}
459
460static int max_uuari(struct mlx5_uuar_info *uuari)
461{
462 return uuari->num_uars * 4;
463}
464
465static int first_hi_uuar(struct mlx5_uuar_info *uuari)
466{
467 int med;
468 int i;
469 int t;
470
471 med = num_med_uuar(uuari);
472 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
473 t++;
474 if (t == med)
475 return next_uuar(i);
476 }
477
478 return 0;
479}
480
e126ba97
EC		 481static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
482{
e126ba97
EC		 483 int i;
484
c1be5232 485 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 486 if (!test_bit(i, uuari->bitmap)) {
487 set_bit(i, uuari->bitmap);
488 uuari->count[i]++;
489 return i;
490 }
491 }
492
493 return -ENOMEM;
494}
495
496static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
497{
c1be5232 498 int minidx = first_med_uuar();
e126ba97
EC		 499 int i;
500
c1be5232 501 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 502 if (uuari->count[i] < uuari->count[minidx])
503 minidx = i;
504 }
505
506 uuari->count[minidx]++;
507 return minidx;
508}
509
510static int alloc_uuar(struct mlx5_uuar_info *uuari,
511 enum mlx5_ib_latency_class lat)
512{
513 int uuarn = -EINVAL;
514
515 mutex_lock(&uuari->lock);
516 switch (lat) {
517 case MLX5_IB_LATENCY_CLASS_LOW:
518 uuarn = 0;
519 uuari->count[uuarn]++;
520 break;
521
522 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 523 if (uuari->ver < 2)
524 uuarn = -ENOMEM;
525 else
526 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 527 break;
528
529 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 530 if (uuari->ver < 2)
531 uuarn = -ENOMEM;
532 else
533 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 534 break;
535
536 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
537 uuarn = 2;
538 break;
539 }
540 mutex_unlock(&uuari->lock);
541
542 return uuarn;
543}
544
545static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
546{
547 clear_bit(uuarn, uuari->bitmap);
548 --uuari->count[uuarn];
549}
550
551static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
552{
553 clear_bit(uuarn, uuari->bitmap);
554 --uuari->count[uuarn];
555}
556
557static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
558{
559 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
560 int high_uuar = nuuars - uuari->num_low_latency_uuars;
561
562 mutex_lock(&uuari->lock);
563 if (uuarn == 0) {
564 --uuari->count[uuarn];
565 goto out;
566 }
567
568 if (uuarn < high_uuar) {
569 free_med_class_uuar(uuari, uuarn);
570 goto out;
571 }
572
573 free_high_class_uuar(uuari, uuarn);
574
575out:
576 mutex_unlock(&uuari->lock);
577}
578
579static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
580{
581 switch (state) {
582 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
583 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
584 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
585 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
586 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
587 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
588 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
589 default: return -1;
590 }
591}
592
593static int to_mlx5_st(enum ib_qp_type type)
594{
595 switch (type) {
596 case IB_QPT_RC: return MLX5_QP_ST_RC;
597 case IB_QPT_UC: return MLX5_QP_ST_UC;
598 case IB_QPT_UD: return MLX5_QP_ST_UD;
599 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
600 case IB_QPT_XRC_INI:
601 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
602 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 603 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 604 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 605 case IB_QPT_RAW_PACKET:
0fb2ed66 606 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 607 case IB_QPT_MAX:
608 default: return -EINVAL;
609 }
610}
611
612static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
613{
614 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
615}
616
19098df2 617static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
618 struct ib_pd *pd,
619 unsigned long addr, size_t size,
620 struct ib_umem **umem,
621 int *npages, int *page_shift, int *ncont,
622 u32 *offset)
623{
624 int err;
625
626 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
627 if (IS_ERR(*umem)) {
628 mlx5_ib_dbg(dev, "umem_get failed\n");
629 return PTR_ERR(*umem);
630 }
631
632 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
633
634 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
635 if (err) {
636 mlx5_ib_warn(dev, "bad offset\n");
637 goto err_umem;
638 }
639
640 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
641 addr, size, *npages, *page_shift, *ncont, *offset);
642
643 return 0;
644
645err_umem:
646 ib_umem_release(*umem);
647 *umem = NULL;
648
649 return err;
650}
651
e126ba97
EC		 652static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
653 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 654 struct ib_qp_init_attr *attr,
e126ba97 655 struct mlx5_create_qp_mbox_in **in,
19098df2 656 struct mlx5_ib_create_qp_resp *resp, int *inlen,
657 struct mlx5_ib_qp_base *base)
e126ba97
EC		 658{
659 struct mlx5_ib_ucontext *context;
660 struct mlx5_ib_create_qp ucmd;
19098df2 661 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 662 int page_shift = 0;
e126ba97
EC		 663 int uar_index;
664 int npages;
9e9c47d0 665 u32 offset = 0;
e126ba97 666 int uuarn;
9e9c47d0 667 int ncont = 0;
e126ba97
EC		 668 int err;
669
670 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
671 if (err) {
672 mlx5_ib_dbg(dev, "copy failed\n");
673 return err;
674 }
675
676 context = to_mucontext(pd->uobject->context);
677 /*
678 * TBD: should come from the verbs when we have the API
679 */
051f2630
LR		 680 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
681 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
682 uuarn = MLX5_CROSS_CHANNEL_UUAR;
683 else {
684 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
e126ba97 685 if (uuarn < 0) {
051f2630
LR		 686 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
687 mlx5_ib_dbg(dev, "reverting to medium latency\n");
688 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
c1be5232 689 if (uuarn < 0) {
051f2630
LR		 690 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
691 mlx5_ib_dbg(dev, "reverting to high latency\n");
692 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
693 if (uuarn < 0) {
694 mlx5_ib_warn(dev, "uuar allocation failed\n");
695 return uuarn;
696 }
c1be5232 697 }
e126ba97
EC		 698 }
699 }
700
701 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
702 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
703
48fea837
HE		 704 qp->rq.offset = 0;
705 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
706 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
707
0fb2ed66 708 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97
EC		 709 if (err)
710 goto err_uuar;
711
19098df2 712 if (ucmd.buf_addr && ubuffer->buf_size) {
713 ubuffer->buf_addr = ucmd.buf_addr;
714 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
715 ubuffer->buf_size,
716 &ubuffer->umem, &npages, &page_shift,
717 &ncont, &offset);
718 if (err)
9e9c47d0 719 goto err_uuar;
9e9c47d0 720 } else {
19098df2 721 ubuffer->umem = NULL;
e126ba97 722 }
e126ba97
EC		 723
724 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
725 *in = mlx5_vzalloc(*inlen);
726 if (!*in) {
727 err = -ENOMEM;
728 goto err_umem;
729 }
19098df2 730 if (ubuffer->umem)
731 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
732 (*in)->pas, 0);
e126ba97 733 (*in)->ctx.log_pg_sz_remote_qpn =
1b77d2bd 734 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 735 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
736
737 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
738 resp->uuar_index = uuarn;
739 qp->uuarn = uuarn;
740
741 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
742 if (err) {
743 mlx5_ib_dbg(dev, "map failed\n");
744 goto err_free;
745 }
746
747 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
748 if (err) {
749 mlx5_ib_dbg(dev, "copy failed\n");
750 goto err_unmap;
751 }
752 qp->create_type = MLX5_QP_USER;
753
754 return 0;
755
756err_unmap:
757 mlx5_ib_db_unmap_user(context, &qp->db);
758
759err_free:
479163f4 760 kvfree(*in);
e126ba97
EC		 761
762err_umem:
19098df2 763 if (ubuffer->umem)
764 ib_umem_release(ubuffer->umem);
e126ba97
EC		 765
766err_uuar:
767 free_uuar(&context->uuari, uuarn);
768 return err;
769}
770
19098df2 771static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
772 struct mlx5_ib_qp_base *base)
e126ba97
EC		 773{
774 struct mlx5_ib_ucontext *context;
775
776 context = to_mucontext(pd->uobject->context);
777 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 778 if (base->ubuffer.umem)
779 ib_umem_release(base->ubuffer.umem);
e126ba97
EC		 780 free_uuar(&context->uuari, qp->uuarn);
781}
782
783static int create_kernel_qp(struct mlx5_ib_dev *dev,
784 struct ib_qp_init_attr *init_attr,
785 struct mlx5_ib_qp *qp,
19098df2 786 struct mlx5_create_qp_mbox_in **in, int *inlen,
787 struct mlx5_ib_qp_base *base)
e126ba97
EC		 788{
789 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
790 struct mlx5_uuar_info *uuari;
791 int uar_index;
792 int uuarn;
793 int err;
794
9603b61d 795 uuari = &dev->mdev->priv.uuari;
f0313965
ES		 796 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
797 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 798 IB_QP_CREATE_IPOIB_UD_LSO |
799 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 800 return -EINVAL;
e126ba97
EC		 801
802 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
803 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
804
805 uuarn = alloc_uuar(uuari, lc);
806 if (uuarn < 0) {
807 mlx5_ib_dbg(dev, "\n");
808 return -ENOMEM;
809 }
810
811 qp->bf = &uuari->bfs[uuarn];
812 uar_index = qp->bf->uar->index;
813
814 err = calc_sq_size(dev, init_attr, qp);
815 if (err < 0) {
816 mlx5_ib_dbg(dev, "err %d\n", err);
817 goto err_uuar;
818 }
819
820 qp->rq.offset = 0;
821 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 822 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 823
19098df2 824 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 825 if (err) {
826 mlx5_ib_dbg(dev, "err %d\n", err);
827 goto err_uuar;
828 }
829
830 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
831 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
832 *in = mlx5_vzalloc(*inlen);
833 if (!*in) {
834 err = -ENOMEM;
835 goto err_buf;
836 }
837 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
1b77d2bd
EC		 838 (*in)->ctx.log_pg_sz_remote_qpn =
839 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 840 /* Set "fast registration enabled" for all kernel QPs */
841 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
842 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
843
b11a4f9c
HE		 844 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
845 (*in)->ctx.deth_sqpn = cpu_to_be32(1);
846 qp->flags |= MLX5_IB_QP_SQPN_QP1;
847 }
848
e126ba97
EC		 849 mlx5_fill_page_array(&qp->buf, (*in)->pas);
850
9603b61d 851 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 852 if (err) {
853 mlx5_ib_dbg(dev, "err %d\n", err);
854 goto err_free;
855 }
856
e126ba97
EC		 857 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
858 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
859 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
860 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
861 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
862
863 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
864 !qp->sq.w_list || !qp->sq.wqe_head) {
865 err = -ENOMEM;
866 goto err_wrid;
867 }
868 qp->create_type = MLX5_QP_KERNEL;
869
870 return 0;
871
872err_wrid:
9603b61d 873 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 874 kfree(qp->sq.wqe_head);
875 kfree(qp->sq.w_list);
876 kfree(qp->sq.wrid);
877 kfree(qp->sq.wr_data);
878 kfree(qp->rq.wrid);
879
880err_free:
479163f4 881 kvfree(*in);
e126ba97
EC		 882
883err_buf:
9603b61d 884 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 885
886err_uuar:
9603b61d 887 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 888 return err;
889}
890
891static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
892{
9603b61d 893 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 894 kfree(qp->sq.wqe_head);
895 kfree(qp->sq.w_list);
896 kfree(qp->sq.wrid);
897 kfree(qp->sq.wr_data);
898 kfree(qp->rq.wrid);
9603b61d
JM		 899 mlx5_buf_free(dev->mdev, &qp->buf);
900 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 901}
902
903static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
904{
905 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
906 (attr->qp_type == IB_QPT_XRC_INI))
907 return cpu_to_be32(MLX5_SRQ_RQ);
908 else if (!qp->has_rq)
909 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
910 else
911 return cpu_to_be32(MLX5_NON_ZERO_RQ);
912}
913
914static int is_connected(enum ib_qp_type qp_type)
915{
916 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
917 return 1;
918
919 return 0;
920}
921
0fb2ed66 922static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
923 struct mlx5_ib_sq *sq, u32 tdn)
924{
925 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
926 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
927
928 memset(in, 0, sizeof(in));
929
930 MLX5_SET(tisc, tisc, transport_domain, tdn);
931
932 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
933}
934
935static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
936 struct mlx5_ib_sq *sq)
937{
938 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
939}
940
941static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
942 struct mlx5_ib_sq *sq, void *qpin,
943 struct ib_pd *pd)
944{
945 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
946 __be64 *pas;
947 void *in;
948 void *sqc;
949 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
950 void *wq;
951 int inlen;
952 int err;
953 int page_shift = 0;
954 int npages;
955 int ncont = 0;
956 u32 offset = 0;
957
958 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
959 &sq->ubuffer.umem, &npages, &page_shift,
960 &ncont, &offset);
961 if (err)
962 return err;
963
964 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
965 in = mlx5_vzalloc(inlen);
966 if (!in) {
967 err = -ENOMEM;
968 goto err_umem;
969 }
970
971 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
972 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
973 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
974 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
975 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
976 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
977 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
978
979 wq = MLX5_ADDR_OF(sqc, sqc, wq);
980 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
981 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
982 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
983 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
984 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
985 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
986 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
987 MLX5_SET(wq, wq, page_offset, offset);
988
989 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
990 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
991
992 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
993
994 kvfree(in);
995
996 if (err)
997 goto err_umem;
998
999 return 0;
1000
1001err_umem:
1002 ib_umem_release(sq->ubuffer.umem);
1003 sq->ubuffer.umem = NULL;
1004
1005 return err;
1006}
1007
1008static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1009 struct mlx5_ib_sq *sq)
1010{
1011 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1012 ib_umem_release(sq->ubuffer.umem);
1013}
1014
1015static int get_rq_pas_size(void *qpc)
1016{
1017 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1018 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1019 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1020 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1021 u32 po_quanta = 1 << (log_page_size - 6);
1022 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1023 u32 page_size = 1 << log_page_size;
1024 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1025 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1026
1027 return rq_num_pas * sizeof(u64);
1028}
1029
1030static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1031 struct mlx5_ib_rq *rq, void *qpin)
1032{
358e42ea 1033 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1034 __be64 *pas;
1035 __be64 *qp_pas;
1036 void *in;
1037 void *rqc;
1038 void *wq;
1039 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1040 int inlen;
1041 int err;
1042 u32 rq_pas_size = get_rq_pas_size(qpc);
1043
1044 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1045 in = mlx5_vzalloc(inlen);
1046 if (!in)
1047 return -ENOMEM;
1048
1049 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1050 MLX5_SET(rqc, rqc, vsd, 1);
1051 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1052 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1053 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1054 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1055 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1056
358e42ea
MD		 1057 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1058 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1059
0fb2ed66 1060 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1061 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1062 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1063 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1064 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1065 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1066 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1067 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1068 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1069 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1070
1071 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1072 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1073 memcpy(pas, qp_pas, rq_pas_size);
1074
1075 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1076
1077 kvfree(in);
1078
1079 return err;
1080}
1081
1082static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1083 struct mlx5_ib_rq *rq)
1084{
1085 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1086}
1087
1088static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1089 struct mlx5_ib_rq *rq, u32 tdn)
1090{
1091 u32 *in;
1092 void *tirc;
1093 int inlen;
1094 int err;
1095
1096 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1097 in = mlx5_vzalloc(inlen);
1098 if (!in)
1099 return -ENOMEM;
1100
1101 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1102 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1103 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1104 MLX5_SET(tirc, tirc, transport_domain, tdn);
1105
1106 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1107
1108 kvfree(in);
1109
1110 return err;
1111}
1112
1113static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1114 struct mlx5_ib_rq *rq)
1115{
1116 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1117}
1118
1119static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1120 struct mlx5_create_qp_mbox_in *in,
1121 struct ib_pd *pd)
1122{
1123 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1124 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1125 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1126 struct ib_uobject *uobj = pd->uobject;
1127 struct ib_ucontext *ucontext = uobj->context;
1128 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1129 int err;
1130 u32 tdn = mucontext->tdn;
1131
1132 if (qp->sq.wqe_cnt) {
1133 err = create_raw_packet_qp_tis(dev, sq, tdn);
1134 if (err)
1135 return err;
1136
1137 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1138 if (err)
1139 goto err_destroy_tis;
1140
1141 sq->base.container_mibqp = qp;
1142 }
1143
1144 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1145 rq->base.container_mibqp = qp;
1146
0fb2ed66 1147 err = create_raw_packet_qp_rq(dev, rq, in);
1148 if (err)
1149 goto err_destroy_sq;
1150
0fb2ed66 1151
1152 err = create_raw_packet_qp_tir(dev, rq, tdn);
1153 if (err)
1154 goto err_destroy_rq;
1155 }
1156
1157 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1158 rq->base.mqp.qpn;
1159
1160 return 0;
1161
1162err_destroy_rq:
1163 destroy_raw_packet_qp_rq(dev, rq);
1164err_destroy_sq:
1165 if (!qp->sq.wqe_cnt)
1166 return err;
1167 destroy_raw_packet_qp_sq(dev, sq);
1168err_destroy_tis:
1169 destroy_raw_packet_qp_tis(dev, sq);
1170
1171 return err;
1172}
1173
1174static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1175 struct mlx5_ib_qp *qp)
1176{
1177 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1178 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1179 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1180
1181 if (qp->rq.wqe_cnt) {
1182 destroy_raw_packet_qp_tir(dev, rq);
1183 destroy_raw_packet_qp_rq(dev, rq);
1184 }
1185
1186 if (qp->sq.wqe_cnt) {
1187 destroy_raw_packet_qp_sq(dev, sq);
1188 destroy_raw_packet_qp_tis(dev, sq);
1189 }
1190}
1191
1192static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1193 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1194{
1195 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1196 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1197
1198 sq->sq = &qp->sq;
1199 rq->rq = &qp->rq;
1200 sq->doorbell = &qp->db;
1201 rq->doorbell = &qp->db;
1202}
1203
e126ba97
EC		 1204static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1205 struct ib_qp_init_attr *init_attr,
1206 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1207{
1208 struct mlx5_ib_resources *devr = &dev->devr;
938fe83c 1209 struct mlx5_core_dev *mdev = dev->mdev;
0fb2ed66 1210 struct mlx5_ib_qp_base *base;
e126ba97
EC		 1211 struct mlx5_ib_create_qp_resp resp;
1212 struct mlx5_create_qp_mbox_in *in;
1213 struct mlx5_ib_create_qp ucmd;
1214 int inlen = sizeof(*in);
1215 int err;
cfb5e088
HA		 1216 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1217 void *qpc;
e126ba97 1218
0fb2ed66 1219 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1220 &qp->raw_packet_qp.rq.base :
1221 &qp->trans_qp.base;
1222
1223 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1224 mlx5_ib_odp_create_qp(qp);
6aec21f6 1225
e126ba97
EC		 1226 mutex_init(&qp->mutex);
1227 spin_lock_init(&qp->sq.lock);
1228 spin_lock_init(&qp->rq.lock);
1229
f360d88a 1230 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1231 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1232 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1233 return -EINVAL;
1234 } else {
1235 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1236 }
1237 }
1238
051f2630
LR		 1239 if (init_attr->create_flags &
1240 (IB_QP_CREATE_CROSS_CHANNEL |
1241 IB_QP_CREATE_MANAGED_SEND |
1242 IB_QP_CREATE_MANAGED_RECV)) {
1243 if (!MLX5_CAP_GEN(mdev, cd)) {
1244 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1245 return -EINVAL;
1246 }
1247 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1248 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1249 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1250 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1251 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1252 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1253 }
f0313965
ES		 1254
1255 if (init_attr->qp_type == IB_QPT_UD &&
1256 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1257 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1258 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1259 return -EOPNOTSUPP;
1260 }
1261
358e42ea
MD		 1262 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1263 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1264 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1265 return -EOPNOTSUPP;
1266 }
1267 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1268 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1269 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1270 return -EOPNOTSUPP;
1271 }
1272 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1273 }
1274
e126ba97
EC		 1275 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1276 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1277
1278 if (pd && pd->uobject) {
1279 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1280 mlx5_ib_dbg(dev, "copy failed\n");
1281 return -EFAULT;
1282 }
1283
cfb5e088
HA		 1284 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1285 &ucmd, udata->inlen, &uidx);
1286 if (err)
1287 return err;
1288
e126ba97
EC		 1289 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1290 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1291 } else {
1292 qp->wq_sig = !!wq_signature;
1293 }
1294
1295 qp->has_rq = qp_has_rq(init_attr);
1296 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1297 qp, (pd && pd->uobject) ? &ucmd : NULL);
1298 if (err) {
1299 mlx5_ib_dbg(dev, "err %d\n", err);
1300 return err;
1301 }
1302
1303 if (pd) {
1304 if (pd->uobject) {
938fe83c
SM		 1305 __u32 max_wqes =
1306 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1307 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1308 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1309 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1310 mlx5_ib_dbg(dev, "invalid rq params\n");
1311 return -EINVAL;
1312 }
938fe83c 1313 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1314 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1315 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1316 return -EINVAL;
1317 }
b11a4f9c
HE		 1318 if (init_attr->create_flags &
1319 mlx5_ib_create_qp_sqpn_qp1()) {
1320 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1321 return -EINVAL;
1322 }
0fb2ed66 1323 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1324 &resp, &inlen, base);
e126ba97
EC		 1325 if (err)
1326 mlx5_ib_dbg(dev, "err %d\n", err);
1327 } else {
19098df2 1328 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1329 base);
e126ba97
EC		 1330 if (err)
1331 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1332 }
1333
1334 if (err)
1335 return err;
1336 } else {
1337 in = mlx5_vzalloc(sizeof(*in));
1338 if (!in)
1339 return -ENOMEM;
1340
1341 qp->create_type = MLX5_QP_EMPTY;
1342 }
1343
1344 if (is_sqp(init_attr->qp_type))
1345 qp->port = init_attr->port_num;
1346
1347 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1348 MLX5_QP_PM_MIGRATED << 11);
1349
1350 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1351 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1352 else
1353 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1354
1355 if (qp->wq_sig)
1356 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1357
f360d88a
EC		 1358 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1359 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1360
051f2630
LR		 1361 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1362 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1363 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1364 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1365 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1366 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1367
e126ba97
EC		 1368 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1369 int rcqe_sz;
1370 int scqe_sz;
1371
1372 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1373 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1374
1375 if (rcqe_sz == 128)
1376 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1377 else
1378 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1379
1380 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1381 if (scqe_sz == 128)
1382 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1383 else
1384 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1385 }
1386 }
1387
1388 if (qp->rq.wqe_cnt) {
1389 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1390 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1391 }
1392
1393 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1394
1395 if (qp->sq.wqe_cnt)
1396 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1397 else
1398 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1399
1400 /* Set default resources */
1401 switch (init_attr->qp_type) {
1402 case IB_QPT_XRC_TGT:
1403 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1404 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1405 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1406 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1407 break;
1408 case IB_QPT_XRC_INI:
1409 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1410 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1411 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1412 break;
1413 default:
1414 if (init_attr->srq) {
1415 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1416 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1417 } else {
1418 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
4aa17b28
HA		 1419 in->ctx.rq_type_srqn |=
1420 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1421 }
1422 }
1423
1424 if (init_attr->send_cq)
1425 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1426
1427 if (init_attr->recv_cq)
1428 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1429
1430 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1431
cfb5e088
HA		 1432 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1433 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1434 /* 0xffffff means we ask to work with cqe version 0 */
1435 MLX5_SET(qpc, qpc, user_index, uidx);
1436 }
f0313965
ES		 1437 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1438 if (init_attr->qp_type == IB_QPT_UD &&
1439 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1440 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1441 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1442 qp->flags |= MLX5_IB_QP_LSO;
1443 }
cfb5e088 1444
0fb2ed66 1445 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1446 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1447 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1448 err = create_raw_packet_qp(dev, qp, in, pd);
1449 } else {
1450 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1451 }
1452
e126ba97
EC		 1453 if (err) {
1454 mlx5_ib_dbg(dev, "create qp failed\n");
1455 goto err_create;
1456 }
1457
479163f4 1458 kvfree(in);
e126ba97 1459
19098df2 1460 base->container_mibqp = qp;
1461 base->mqp.event = mlx5_ib_qp_event;
e126ba97
EC		 1462
1463 return 0;
1464
1465err_create:
1466 if (qp->create_type == MLX5_QP_USER)
19098df2 1467 destroy_qp_user(pd, qp, base);
e126ba97
EC		 1468 else if (qp->create_type == MLX5_QP_KERNEL)
1469 destroy_qp_kernel(dev, qp);
1470
479163f4 1471 kvfree(in);
e126ba97
EC		 1472 return err;
1473}
1474
1475static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1476 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1477{
1478 if (send_cq) {
1479 if (recv_cq) {
1480 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1481 spin_lock_irq(&send_cq->lock);
1482 spin_lock_nested(&recv_cq->lock,
1483 SINGLE_DEPTH_NESTING);
1484 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1485 spin_lock_irq(&send_cq->lock);
1486 __acquire(&recv_cq->lock);
1487 } else {
1488 spin_lock_irq(&recv_cq->lock);
1489 spin_lock_nested(&send_cq->lock,
1490 SINGLE_DEPTH_NESTING);
1491 }
1492 } else {
1493 spin_lock_irq(&send_cq->lock);
6a4f139a 1494 __acquire(&recv_cq->lock);
e126ba97
EC		 1495 }
1496 } else if (recv_cq) {
1497 spin_lock_irq(&recv_cq->lock);
6a4f139a
EC		 1498 __acquire(&send_cq->lock);
1499 } else {
1500 __acquire(&send_cq->lock);
1501 __acquire(&recv_cq->lock);
e126ba97
EC		 1502 }
1503}
1504
1505static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1506 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1507{
1508 if (send_cq) {
1509 if (recv_cq) {
1510 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1511 spin_unlock(&recv_cq->lock);
1512 spin_unlock_irq(&send_cq->lock);
1513 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1514 __release(&recv_cq->lock);
1515 spin_unlock_irq(&send_cq->lock);
1516 } else {
1517 spin_unlock(&send_cq->lock);
1518 spin_unlock_irq(&recv_cq->lock);
1519 }
1520 } else {
6a4f139a 1521 __release(&recv_cq->lock);
e126ba97
EC		 1522 spin_unlock_irq(&send_cq->lock);
1523 }
1524 } else if (recv_cq) {
6a4f139a 1525 __release(&send_cq->lock);
e126ba97 1526 spin_unlock_irq(&recv_cq->lock);
6a4f139a
EC		 1527 } else {
1528 __release(&recv_cq->lock);
1529 __release(&send_cq->lock);
e126ba97
EC		 1530 }
1531}
1532
1533static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1534{
1535 return to_mpd(qp->ibqp.pd);
1536}
1537
1538static void get_cqs(struct mlx5_ib_qp *qp,
1539 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1540{
1541 switch (qp->ibqp.qp_type) {
1542 case IB_QPT_XRC_TGT:
1543 *send_cq = NULL;
1544 *recv_cq = NULL;
1545 break;
1546 case MLX5_IB_QPT_REG_UMR:
1547 case IB_QPT_XRC_INI:
1548 *send_cq = to_mcq(qp->ibqp.send_cq);
1549 *recv_cq = NULL;
1550 break;
1551
1552 case IB_QPT_SMI:
d16e91da 1553 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1554 case IB_QPT_RC:
1555 case IB_QPT_UC:
1556 case IB_QPT_UD:
1557 case IB_QPT_RAW_IPV6:
1558 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1559 case IB_QPT_RAW_PACKET:
e126ba97
EC		 1560 *send_cq = to_mcq(qp->ibqp.send_cq);
1561 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1562 break;
1563
e126ba97
EC		 1564 case IB_QPT_MAX:
1565 default:
1566 *send_cq = NULL;
1567 *recv_cq = NULL;
1568 break;
1569 }
1570}
1571
ad5f8e96 1572static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1573 u16 operation);
1574
e126ba97
EC		 1575static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1576{
1577 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1578 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
0fb2ed66 1579 struct mlx5_modify_qp_mbox_in *in;
e126ba97
EC		 1580 int err;
1581
0fb2ed66 1582 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1583 &qp->raw_packet_qp.rq.base :
1584 &qp->trans_qp.base;
1585
e126ba97
EC		 1586 in = kzalloc(sizeof(*in), GFP_KERNEL);
1587 if (!in)
1588 return;
7bef7ad2 1589
6aec21f6 1590 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1591 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1592 mlx5_ib_qp_disable_pagefaults(qp);
1593 err = mlx5_core_qp_modify(dev->mdev,
1594 MLX5_CMD_OP_2RST_QP, in, 0,
1595 &base->mqp);
1596 } else {
1597 err = modify_raw_packet_qp(dev, qp,
1598 MLX5_CMD_OP_2RST_QP);
1599 }
1600 if (err)
427c1e7b 1601 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1602 base->mqp.qpn);
6aec21f6 1603 }
e126ba97
EC		 1604
1605 get_cqs(qp, &send_cq, &recv_cq);
1606
1607 if (qp->create_type == MLX5_QP_KERNEL) {
1608 mlx5_ib_lock_cqs(send_cq, recv_cq);
19098df2 1609 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1610 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1611 if (send_cq != recv_cq)
19098df2 1612 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1613 NULL);
e126ba97
EC		 1614 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1615 }
1616
0fb2ed66 1617 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1618 destroy_raw_packet_qp(dev, qp);
1619 } else {
1620 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1621 if (err)
1622 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1623 base->mqp.qpn);
1624 }
e126ba97 1625
0fb2ed66 1626 kfree(in);
e126ba97
EC		 1627
1628 if (qp->create_type == MLX5_QP_KERNEL)
1629 destroy_qp_kernel(dev, qp);
1630 else if (qp->create_type == MLX5_QP_USER)
19098df2 1631 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1632}
1633
1634static const char *ib_qp_type_str(enum ib_qp_type type)
1635{
1636 switch (type) {
1637 case IB_QPT_SMI:
1638 return "IB_QPT_SMI";
1639 case IB_QPT_GSI:
1640 return "IB_QPT_GSI";
1641 case IB_QPT_RC:
1642 return "IB_QPT_RC";
1643 case IB_QPT_UC:
1644 return "IB_QPT_UC";
1645 case IB_QPT_UD:
1646 return "IB_QPT_UD";
1647 case IB_QPT_RAW_IPV6:
1648 return "IB_QPT_RAW_IPV6";
1649 case IB_QPT_RAW_ETHERTYPE:
1650 return "IB_QPT_RAW_ETHERTYPE";
1651 case IB_QPT_XRC_INI:
1652 return "IB_QPT_XRC_INI";
1653 case IB_QPT_XRC_TGT:
1654 return "IB_QPT_XRC_TGT";
1655 case IB_QPT_RAW_PACKET:
1656 return "IB_QPT_RAW_PACKET";
1657 case MLX5_IB_QPT_REG_UMR:
1658 return "MLX5_IB_QPT_REG_UMR";
1659 case IB_QPT_MAX:
1660 default:
1661 return "Invalid QP type";
1662 }
1663}
1664
1665struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1666 struct ib_qp_init_attr *init_attr,
1667 struct ib_udata *udata)
1668{
1669 struct mlx5_ib_dev *dev;
1670 struct mlx5_ib_qp *qp;
1671 u16 xrcdn = 0;
1672 int err;
1673
1674 if (pd) {
1675 dev = to_mdev(pd->device);
0fb2ed66 1676
1677 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1678 if (!pd->uobject) {
1679 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1680 return ERR_PTR(-EINVAL);
1681 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1682 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1683 return ERR_PTR(-EINVAL);
1684 }
1685 }
09f16cf5
MD		 1686 } else {
1687 /* being cautious here */
1688 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1689 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1690 pr_warn("%s: no PD for transport %s\n", __func__,
1691 ib_qp_type_str(init_attr->qp_type));
1692 return ERR_PTR(-EINVAL);
1693 }
1694 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 1695 }
1696
1697 switch (init_attr->qp_type) {
1698 case IB_QPT_XRC_TGT:
1699 case IB_QPT_XRC_INI:
938fe83c 1700 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 1701 mlx5_ib_dbg(dev, "XRC not supported\n");
1702 return ERR_PTR(-ENOSYS);
1703 }
1704 init_attr->recv_cq = NULL;
1705 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1706 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1707 init_attr->send_cq = NULL;
1708 }
1709
1710 /* fall through */
0fb2ed66 1711 case IB_QPT_RAW_PACKET:
e126ba97
EC		 1712 case IB_QPT_RC:
1713 case IB_QPT_UC:
1714 case IB_QPT_UD:
1715 case IB_QPT_SMI:
d16e91da 1716 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1717 case MLX5_IB_QPT_REG_UMR:
1718 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1719 if (!qp)
1720 return ERR_PTR(-ENOMEM);
1721
1722 err = create_qp_common(dev, pd, init_attr, udata, qp);
1723 if (err) {
1724 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1725 kfree(qp);
1726 return ERR_PTR(err);
1727 }
1728
1729 if (is_qp0(init_attr->qp_type))
1730 qp->ibqp.qp_num = 0;
1731 else if (is_qp1(init_attr->qp_type))
1732 qp->ibqp.qp_num = 1;
1733 else
19098df2 1734 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 1735
1736 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 1737 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
1738 to_mcq(init_attr->recv_cq)->mcq.cqn,
e126ba97
EC		 1739 to_mcq(init_attr->send_cq)->mcq.cqn);
1740
19098df2 1741 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 1742
1743 break;
1744
d16e91da
HE		 1745 case IB_QPT_GSI:
1746 return mlx5_ib_gsi_create_qp(pd, init_attr);
1747
e126ba97
EC		 1748 case IB_QPT_RAW_IPV6:
1749 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 1750 case IB_QPT_MAX:
1751 default:
1752 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1753 init_attr->qp_type);
1754 /* Don't support raw QPs */
1755 return ERR_PTR(-EINVAL);
1756 }
1757
1758 return &qp->ibqp;
1759}
1760
1761int mlx5_ib_destroy_qp(struct ib_qp *qp)
1762{
1763 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1764 struct mlx5_ib_qp *mqp = to_mqp(qp);
1765
d16e91da
HE		 1766 if (unlikely(qp->qp_type == IB_QPT_GSI))
1767 return mlx5_ib_gsi_destroy_qp(qp);
1768
e126ba97
EC		 1769 destroy_qp_common(dev, mqp);
1770
1771 kfree(mqp);
1772
1773 return 0;
1774}
1775
1776static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1777 int attr_mask)
1778{
1779 u32 hw_access_flags = 0;
1780 u8 dest_rd_atomic;
1781 u32 access_flags;
1782
1783 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1784 dest_rd_atomic = attr->max_dest_rd_atomic;
1785 else
19098df2 1786 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 1787
1788 if (attr_mask & IB_QP_ACCESS_FLAGS)
1789 access_flags = attr->qp_access_flags;
1790 else
19098df2 1791 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 1792
1793 if (!dest_rd_atomic)
1794 access_flags &= IB_ACCESS_REMOTE_WRITE;
1795
1796 if (access_flags & IB_ACCESS_REMOTE_READ)
1797 hw_access_flags |= MLX5_QP_BIT_RRE;
1798 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1799 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1800 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1801 hw_access_flags |= MLX5_QP_BIT_RWE;
1802
1803 return cpu_to_be32(hw_access_flags);
1804}
1805
1806enum {
1807 MLX5_PATH_FLAG_FL = 1 << 0,
1808 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1809 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1810};
1811
1812static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1813{
1814 if (rate == IB_RATE_PORT_CURRENT) {
1815 return 0;
1816 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1817 return -EINVAL;
1818 } else {
1819 while (rate != IB_RATE_2_5_GBPS &&
1820 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 1821 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 1822 --rate;
1823 }
1824
1825 return rate + MLX5_STAT_RATE_OFFSET;
1826}
1827
75850d0b 1828static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1829 struct mlx5_ib_sq *sq, u8 sl)
1830{
1831 void *in;
1832 void *tisc;
1833 int inlen;
1834 int err;
1835
1836 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1837 in = mlx5_vzalloc(inlen);
1838 if (!in)
1839 return -ENOMEM;
1840
1841 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1842
1843 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
1844 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
1845
1846 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
1847
1848 kvfree(in);
1849
1850 return err;
1851}
1852
1853static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1854 const struct ib_ah_attr *ah,
e126ba97
EC		 1855 struct mlx5_qp_path *path, u8 port, int attr_mask,
1856 u32 path_flags, const struct ib_qp_attr *attr)
1857{
2811ba51 1858 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97
EC		 1859 int err;
1860
e126ba97 1861 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 1862 path->pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97 1863
e126ba97 1864 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 1865 if (ah->grh.sgid_index >=
1866 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 1867 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 1868 ah->grh.sgid_index,
1869 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 1870 return -EINVAL;
1871 }
2811ba51
AS		 1872 }
1873
1874 if (ll == IB_LINK_LAYER_ETHERNET) {
1875 if (!(ah->ah_flags & IB_AH_GRH))
1876 return -EINVAL;
1877 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
1878 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
1879 ah->grh.sgid_index);
1880 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
1881 } else {
d3ae2bde
NO		 1882 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1883 path->fl_free_ar |=
1884 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 1885 path->rlid = cpu_to_be16(ah->dlid);
1886 path->grh_mlid = ah->src_path_bits & 0x7f;
1887 if (ah->ah_flags & IB_AH_GRH)
1888 path->grh_mlid |= 1 << 7;
1889 path->dci_cfi_prio_sl = ah->sl & 0xf;
1890 }
1891
1892 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 1893 path->mgid_index = ah->grh.sgid_index;
1894 path->hop_limit = ah->grh.hop_limit;
1895 path->tclass_flowlabel =
1896 cpu_to_be32((ah->grh.traffic_class << 20) |
1897 (ah->grh.flow_label));
1898 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1899 }
1900
1901 err = ib_rate_to_mlx5(dev, ah->static_rate);
1902 if (err < 0)
1903 return err;
1904 path->static_rate = err;
1905 path->port = port;
1906
e126ba97
EC		 1907 if (attr_mask & IB_QP_TIMEOUT)
1908 path->ackto_lt = attr->timeout << 3;
1909
75850d0b 1910 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
1911 return modify_raw_packet_eth_prio(dev->mdev,
1912 &qp->raw_packet_qp.sq,
1913 ah->sl & 0xf);
1914
e126ba97
EC		 1915 return 0;
1916}
1917
1918static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1919 [MLX5_QP_STATE_INIT] = {
1920 [MLX5_QP_STATE_INIT] = {
1921 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1922 MLX5_QP_OPTPAR_RAE |
1923 MLX5_QP_OPTPAR_RWE |
1924 MLX5_QP_OPTPAR_PKEY_INDEX |
1925 MLX5_QP_OPTPAR_PRI_PORT,
1926 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1927 MLX5_QP_OPTPAR_PKEY_INDEX |
1928 MLX5_QP_OPTPAR_PRI_PORT,
1929 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1930 MLX5_QP_OPTPAR_Q_KEY |
1931 MLX5_QP_OPTPAR_PRI_PORT,
1932 },
1933 [MLX5_QP_STATE_RTR] = {
1934 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1935 MLX5_QP_OPTPAR_RRE |
1936 MLX5_QP_OPTPAR_RAE |
1937 MLX5_QP_OPTPAR_RWE |
1938 MLX5_QP_OPTPAR_PKEY_INDEX,
1939 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1940 MLX5_QP_OPTPAR_RWE |
1941 MLX5_QP_OPTPAR_PKEY_INDEX,
1942 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1943 MLX5_QP_OPTPAR_Q_KEY,
1944 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1945 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 1946 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1947 MLX5_QP_OPTPAR_RRE |
1948 MLX5_QP_OPTPAR_RAE |
1949 MLX5_QP_OPTPAR_RWE |
1950 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 1951 },
1952 },
1953 [MLX5_QP_STATE_RTR] = {
1954 [MLX5_QP_STATE_RTS] = {
1955 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1956 MLX5_QP_OPTPAR_RRE |
1957 MLX5_QP_OPTPAR_RAE |
1958 MLX5_QP_OPTPAR_RWE |
1959 MLX5_QP_OPTPAR_PM_STATE |
1960 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1961 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1962 MLX5_QP_OPTPAR_RWE |
1963 MLX5_QP_OPTPAR_PM_STATE,
1964 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1965 },
1966 },
1967 [MLX5_QP_STATE_RTS] = {
1968 [MLX5_QP_STATE_RTS] = {
1969 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1970 MLX5_QP_OPTPAR_RAE |
1971 MLX5_QP_OPTPAR_RWE |
1972 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 1973 MLX5_QP_OPTPAR_PM_STATE |
1974 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 1975 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 1976 MLX5_QP_OPTPAR_PM_STATE |
1977 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 1978 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1979 MLX5_QP_OPTPAR_SRQN |
1980 MLX5_QP_OPTPAR_CQN_RCV,
1981 },
1982 },
1983 [MLX5_QP_STATE_SQER] = {
1984 [MLX5_QP_STATE_RTS] = {
1985 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1986 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 1987 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 1988 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1989 MLX5_QP_OPTPAR_RWE |
1990 MLX5_QP_OPTPAR_RAE |
1991 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 1992 },
1993 },
1994};
1995
1996static int ib_nr_to_mlx5_nr(int ib_mask)
1997{
1998 switch (ib_mask) {
1999 case IB_QP_STATE:
2000 return 0;
2001 case IB_QP_CUR_STATE:
2002 return 0;
2003 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2004 return 0;
2005 case IB_QP_ACCESS_FLAGS:
2006 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2007 MLX5_QP_OPTPAR_RAE;
2008 case IB_QP_PKEY_INDEX:
2009 return MLX5_QP_OPTPAR_PKEY_INDEX;
2010 case IB_QP_PORT:
2011 return MLX5_QP_OPTPAR_PRI_PORT;
2012 case IB_QP_QKEY:
2013 return MLX5_QP_OPTPAR_Q_KEY;
2014 case IB_QP_AV:
2015 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2016 MLX5_QP_OPTPAR_PRI_PORT;
2017 case IB_QP_PATH_MTU:
2018 return 0;
2019 case IB_QP_TIMEOUT:
2020 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2021 case IB_QP_RETRY_CNT:
2022 return MLX5_QP_OPTPAR_RETRY_COUNT;
2023 case IB_QP_RNR_RETRY:
2024 return MLX5_QP_OPTPAR_RNR_RETRY;
2025 case IB_QP_RQ_PSN:
2026 return 0;
2027 case IB_QP_MAX_QP_RD_ATOMIC:
2028 return MLX5_QP_OPTPAR_SRA_MAX;
2029 case IB_QP_ALT_PATH:
2030 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2031 case IB_QP_MIN_RNR_TIMER:
2032 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2033 case IB_QP_SQ_PSN:
2034 return 0;
2035 case IB_QP_MAX_DEST_RD_ATOMIC:
2036 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2037 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2038 case IB_QP_PATH_MIG_STATE:
2039 return MLX5_QP_OPTPAR_PM_STATE;
2040 case IB_QP_CAP:
2041 return 0;
2042 case IB_QP_DEST_QPN:
2043 return 0;
2044 }
2045 return 0;
2046}
2047
2048static int ib_mask_to_mlx5_opt(int ib_mask)
2049{
2050 int result = 0;
2051 int i;
2052
2053 for (i = 0; i < 8 * sizeof(int); i++) {
2054 if ((1 << i) & ib_mask)
2055 result |= ib_nr_to_mlx5_nr(1 << i);
2056 }
2057
2058 return result;
2059}
2060
ad5f8e96 2061static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2062 struct mlx5_ib_rq *rq, int new_state)
2063{
2064 void *in;
2065 void *rqc;
2066 int inlen;
2067 int err;
2068
2069 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2070 in = mlx5_vzalloc(inlen);
2071 if (!in)
2072 return -ENOMEM;
2073
2074 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2075
2076 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2077 MLX5_SET(rqc, rqc, state, new_state);
2078
2079 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2080 if (err)
2081 goto out;
2082
2083 rq->state = new_state;
2084
2085out:
2086 kvfree(in);
2087 return err;
2088}
2089
2090static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2091 struct mlx5_ib_sq *sq, int new_state)
2092{
2093 void *in;
2094 void *sqc;
2095 int inlen;
2096 int err;
2097
2098 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2099 in = mlx5_vzalloc(inlen);
2100 if (!in)
2101 return -ENOMEM;
2102
2103 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2104
2105 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2106 MLX5_SET(sqc, sqc, state, new_state);
2107
2108 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2109 if (err)
2110 goto out;
2111
2112 sq->state = new_state;
2113
2114out:
2115 kvfree(in);
2116 return err;
2117}
2118
2119static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2120 u16 operation)
2121{
2122 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2123 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2124 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2125 int rq_state;
2126 int sq_state;
2127 int err;
2128
2129 switch (operation) {
2130 case MLX5_CMD_OP_RST2INIT_QP:
2131 rq_state = MLX5_RQC_STATE_RDY;
2132 sq_state = MLX5_SQC_STATE_RDY;
2133 break;
2134 case MLX5_CMD_OP_2ERR_QP:
2135 rq_state = MLX5_RQC_STATE_ERR;
2136 sq_state = MLX5_SQC_STATE_ERR;
2137 break;
2138 case MLX5_CMD_OP_2RST_QP:
2139 rq_state = MLX5_RQC_STATE_RST;
2140 sq_state = MLX5_SQC_STATE_RST;
2141 break;
2142 case MLX5_CMD_OP_INIT2INIT_QP:
2143 case MLX5_CMD_OP_INIT2RTR_QP:
2144 case MLX5_CMD_OP_RTR2RTS_QP:
2145 case MLX5_CMD_OP_RTS2RTS_QP:
2146 /* Nothing to do here... */
2147 return 0;
2148 default:
2149 WARN_ON(1);
2150 return -EINVAL;
2151 }
2152
2153 if (qp->rq.wqe_cnt) {
2154 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2155 if (err)
2156 return err;
2157 }
2158
2159 if (qp->sq.wqe_cnt)
2160 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2161
2162 return 0;
2163}
2164
e126ba97
EC		 2165static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2166 const struct ib_qp_attr *attr, int attr_mask,
2167 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2168{
427c1e7b 2169 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2170 [MLX5_QP_STATE_RST] = {
2171 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2172 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2173 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2174 },
2175 [MLX5_QP_STATE_INIT] = {
2176 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2177 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2178 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2179 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2180 },
2181 [MLX5_QP_STATE_RTR] = {
2182 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2183 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2184 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2185 },
2186 [MLX5_QP_STATE_RTS] = {
2187 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2188 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2189 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2190 },
2191 [MLX5_QP_STATE_SQD] = {
2192 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2193 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2194 },
2195 [MLX5_QP_STATE_SQER] = {
2196 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2197 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2198 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2199 },
2200 [MLX5_QP_STATE_ERR] = {
2201 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2202 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2203 }
2204 };
2205
e126ba97
EC		 2206 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2207 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2208 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2209 struct mlx5_ib_cq *send_cq, *recv_cq;
2210 struct mlx5_qp_context *context;
2211 struct mlx5_modify_qp_mbox_in *in;
2212 struct mlx5_ib_pd *pd;
2213 enum mlx5_qp_state mlx5_cur, mlx5_new;
2214 enum mlx5_qp_optpar optpar;
2215 int sqd_event;
2216 int mlx5_st;
2217 int err;
427c1e7b 2218 u16 op;
e126ba97
EC		 2219
2220 in = kzalloc(sizeof(*in), GFP_KERNEL);
2221 if (!in)
2222 return -ENOMEM;
2223
2224 context = &in->ctx;
2225 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2226 if (err < 0) {
2227 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2228 goto out;
158abf86 2229 }
e126ba97
EC		 2230
2231 context->flags = cpu_to_be32(err << 16);
2232
2233 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2234 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2235 } else {
2236 switch (attr->path_mig_state) {
2237 case IB_MIG_MIGRATED:
2238 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2239 break;
2240 case IB_MIG_REARM:
2241 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2242 break;
2243 case IB_MIG_ARMED:
2244 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2245 break;
2246 }
2247 }
2248
d16e91da 2249 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2250 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2251 } else if (ibqp->qp_type == IB_QPT_UD ||
2252 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2253 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2254 } else if (attr_mask & IB_QP_PATH_MTU) {
2255 if (attr->path_mtu < IB_MTU_256 ||
2256 attr->path_mtu > IB_MTU_4096) {
2257 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2258 err = -EINVAL;
2259 goto out;
2260 }
938fe83c
SM		 2261 context->mtu_msgmax = (attr->path_mtu << 5) |
2262 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2263 }
2264
2265 if (attr_mask & IB_QP_DEST_QPN)
2266 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2267
2268 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2269 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2270
2271 /* todo implement counter_index functionality */
2272
2273 if (is_sqp(ibqp->qp_type))
2274 context->pri_path.port = qp->port;
2275
2276 if (attr_mask & IB_QP_PORT)
2277 context->pri_path.port = attr->port_num;
2278
2279 if (attr_mask & IB_QP_AV) {
75850d0b 2280 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97
EC		 2281 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2282 attr_mask, 0, attr);
2283 if (err)
2284 goto out;
2285 }
2286
2287 if (attr_mask & IB_QP_TIMEOUT)
2288 context->pri_path.ackto_lt |= attr->timeout << 3;
2289
2290 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2291 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2292 &context->alt_path,
e126ba97
EC		 2293 attr->alt_port_num, attr_mask, 0, attr);
2294 if (err)
2295 goto out;
2296 }
2297
2298 pd = get_pd(qp);
2299 get_cqs(qp, &send_cq, &recv_cq);
2300
2301 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2302 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2303 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2304 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2305
2306 if (attr_mask & IB_QP_RNR_RETRY)
2307 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2308
2309 if (attr_mask & IB_QP_RETRY_CNT)
2310 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2311
2312 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2313 if (attr->max_rd_atomic)
2314 context->params1 |=
2315 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2316 }
2317
2318 if (attr_mask & IB_QP_SQ_PSN)
2319 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2320
2321 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2322 if (attr->max_dest_rd_atomic)
2323 context->params2 |=
2324 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2325 }
2326
2327 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2328 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2329
2330 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2331 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2332
2333 if (attr_mask & IB_QP_RQ_PSN)
2334 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2335
2336 if (attr_mask & IB_QP_QKEY)
2337 context->qkey = cpu_to_be32(attr->qkey);
2338
2339 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2340 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2341
2342 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2343 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2344 sqd_event = 1;
2345 else
2346 sqd_event = 0;
2347
2348 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2349 context->sq_crq_size |= cpu_to_be16(1 << 4);
2350
b11a4f9c
HE		 2351 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2352 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2353
2354 mlx5_cur = to_mlx5_state(cur_state);
2355 mlx5_new = to_mlx5_state(new_state);
2356 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2357 if (mlx5_st < 0)
e126ba97
EC		 2358 goto out;
2359
6aec21f6
HE		 2360 /* If moving to a reset or error state, we must disable page faults on
2361 * this QP and flush all current page faults. Otherwise a stale page
2362 * fault may attempt to work on this QP after it is reset and moved
2363 * again to RTS, and may cause the driver and the device to get out of
2364 * sync. */
2365 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
ad5f8e96 2366 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2367 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2368 mlx5_ib_qp_disable_pagefaults(qp);
2369
427c1e7b 2370 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2371 !optab[mlx5_cur][mlx5_new])
2372 goto out;
2373
2374 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2375 optpar = ib_mask_to_mlx5_opt(attr_mask);
2376 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2377 in->optparam = cpu_to_be32(optpar);
ad5f8e96 2378
2379 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2380 err = modify_raw_packet_qp(dev, qp, op);
2381 else
2382 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2383 &base->mqp);
e126ba97
EC		 2384 if (err)
2385 goto out;
2386
ad5f8e96 2387 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2388 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2389 mlx5_ib_qp_enable_pagefaults(qp);
2390
e126ba97
EC		 2391 qp->state = new_state;
2392
2393 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2394 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2395 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2396 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2397 if (attr_mask & IB_QP_PORT)
2398 qp->port = attr->port_num;
2399 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2400 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2401
2402 /*
2403 * If we moved a kernel QP to RESET, clean up all old CQ
2404 * entries and reinitialize the QP.
2405 */
2406 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2407 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2408 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2409 if (send_cq != recv_cq)
19098df2 2410 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2411
2412 qp->rq.head = 0;
2413 qp->rq.tail = 0;
2414 qp->sq.head = 0;
2415 qp->sq.tail = 0;
2416 qp->sq.cur_post = 0;
2417 qp->sq.last_poll = 0;
2418 qp->db.db[MLX5_RCV_DBR] = 0;
2419 qp->db.db[MLX5_SND_DBR] = 0;
2420 }
2421
2422out:
2423 kfree(in);
2424 return err;
2425}
2426
2427int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2428 int attr_mask, struct ib_udata *udata)
2429{
2430 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2431 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2432 enum ib_qp_type qp_type;
e126ba97
EC		 2433 enum ib_qp_state cur_state, new_state;
2434 int err = -EINVAL;
2435 int port;
2811ba51 2436 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2437
d16e91da
HE		 2438 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2439 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2440
2441 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2442 IB_QPT_GSI : ibqp->qp_type;
2443
e126ba97
EC		 2444 mutex_lock(&qp->mutex);
2445
2446 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2447 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2448
2811ba51
AS		 2449 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2450 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2451 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2452 }
2453
d16e91da
HE		 2454 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2455 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2456 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2457 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2458 goto out;
158abf86 2459 }
e126ba97
EC		 2460
2461 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2462 (attr->port_num == 0 ||
158abf86
HE		 2463 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2464 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2465 attr->port_num, dev->num_ports);
e126ba97 2466 goto out;
158abf86 2467 }
e126ba97
EC		 2468
2469 if (attr_mask & IB_QP_PKEY_INDEX) {
2470 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2471 if (attr->pkey_index >=
158abf86
HE		 2472 dev->mdev->port_caps[port - 1].pkey_table_len) {
2473 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2474 attr->pkey_index);
e126ba97 2475 goto out;
158abf86 2476 }
e126ba97
EC		 2477 }
2478
2479 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2480 attr->max_rd_atomic >
158abf86
HE		 2481 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2482 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2483 attr->max_rd_atomic);
e126ba97 2484 goto out;
158abf86 2485 }
e126ba97
EC		 2486
2487 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2488 attr->max_dest_rd_atomic >
158abf86
HE		 2489 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2490 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2491 attr->max_dest_rd_atomic);
e126ba97 2492 goto out;
158abf86 2493 }
e126ba97
EC		 2494
2495 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2496 err = 0;
2497 goto out;
2498 }
2499
2500 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2501
2502out:
2503 mutex_unlock(&qp->mutex);
2504 return err;
2505}
2506
2507static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2508{
2509 struct mlx5_ib_cq *cq;
2510 unsigned cur;
2511
2512 cur = wq->head - wq->tail;
2513 if (likely(cur + nreq < wq->max_post))
2514 return 0;
2515
2516 cq = to_mcq(ib_cq);
2517 spin_lock(&cq->lock);
2518 cur = wq->head - wq->tail;
2519 spin_unlock(&cq->lock);
2520
2521 return cur + nreq >= wq->max_post;
2522}
2523
2524static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2525 u64 remote_addr, u32 rkey)
2526{
2527 rseg->raddr = cpu_to_be64(remote_addr);
2528 rseg->rkey = cpu_to_be32(rkey);
2529 rseg->reserved = 0;
2530}
2531
f0313965
ES		 2532static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2533 struct ib_send_wr *wr, void *qend,
2534 struct mlx5_ib_qp *qp, int *size)
2535{
2536 void *seg = eseg;
2537
2538 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2539
2540 if (wr->send_flags & IB_SEND_IP_CSUM)
2541 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2542 MLX5_ETH_WQE_L4_CSUM;
2543
2544 seg += sizeof(struct mlx5_wqe_eth_seg);
2545 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2546
2547 if (wr->opcode == IB_WR_LSO) {
2548 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2549 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2550 u64 left, leftlen, copysz;
2551 void *pdata = ud_wr->header;
2552
2553 left = ud_wr->hlen;
2554 eseg->mss = cpu_to_be16(ud_wr->mss);
2555 eseg->inline_hdr_sz = cpu_to_be16(left);
2556
2557 /*
2558 * check if there is space till the end of queue, if yes,
2559 * copy all in one shot, otherwise copy till the end of queue,
2560 * rollback and than the copy the left
2561 */
2562 leftlen = qend - (void *)eseg->inline_hdr_start;
2563 copysz = min_t(u64, leftlen, left);
2564
2565 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2566
2567 if (likely(copysz > size_of_inl_hdr_start)) {
2568 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2569 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2570 }
2571
2572 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2573 seg = mlx5_get_send_wqe(qp, 0);
2574 left -= copysz;
2575 pdata += copysz;
2576 memcpy(seg, pdata, left);
2577 seg += ALIGN(left, 16);
2578 *size += ALIGN(left, 16) / 16;
2579 }
2580 }
2581
2582 return seg;
2583}
2584
e126ba97
EC		 2585static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2586 struct ib_send_wr *wr)
2587{
e622f2f4
CH		 2588 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2589 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2590 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 2591}
2592
2593static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2594{
2595 dseg->byte_count = cpu_to_be32(sg->length);
2596 dseg->lkey = cpu_to_be32(sg->lkey);
2597 dseg->addr = cpu_to_be64(sg->addr);
2598}
2599
2600static __be16 get_klm_octo(int npages)
2601{
2602 return cpu_to_be16(ALIGN(npages, 8) / 2);
2603}
2604
2605static __be64 frwr_mkey_mask(void)
2606{
2607 u64 result;
2608
2609 result = MLX5_MKEY_MASK_LEN |
2610 MLX5_MKEY_MASK_PAGE_SIZE |
2611 MLX5_MKEY_MASK_START_ADDR |
2612 MLX5_MKEY_MASK_EN_RINVAL |
2613 MLX5_MKEY_MASK_KEY |
2614 MLX5_MKEY_MASK_LR |
2615 MLX5_MKEY_MASK_LW |
2616 MLX5_MKEY_MASK_RR |
2617 MLX5_MKEY_MASK_RW |
2618 MLX5_MKEY_MASK_A |
2619 MLX5_MKEY_MASK_SMALL_FENCE |
2620 MLX5_MKEY_MASK_FREE;
2621
2622 return cpu_to_be64(result);
2623}
2624
e6631814
SG		 2625static __be64 sig_mkey_mask(void)
2626{
2627 u64 result;
2628
2629 result = MLX5_MKEY_MASK_LEN |
2630 MLX5_MKEY_MASK_PAGE_SIZE |
2631 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 2632 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 2633 MLX5_MKEY_MASK_EN_RINVAL |
2634 MLX5_MKEY_MASK_KEY |
2635 MLX5_MKEY_MASK_LR |
2636 MLX5_MKEY_MASK_LW |
2637 MLX5_MKEY_MASK_RR |
2638 MLX5_MKEY_MASK_RW |
2639 MLX5_MKEY_MASK_SMALL_FENCE |
2640 MLX5_MKEY_MASK_FREE |
2641 MLX5_MKEY_MASK_BSF_EN;
2642
2643 return cpu_to_be64(result);
2644}
2645
8a187ee5
SG		 2646static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2647 struct mlx5_ib_mr *mr)
2648{
2649 int ndescs = mr->ndescs;
2650
2651 memset(umr, 0, sizeof(*umr));
b005d316
SG		 2652
2653 if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
2654 /* KLMs take twice the size of MTTs */
2655 ndescs *= 2;
2656
8a187ee5
SG		 2657 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2658 umr->klm_octowords = get_klm_octo(ndescs);
2659 umr->mkey_mask = frwr_mkey_mask();
2660}
2661
dd01e66a 2662static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 2663{
2664 memset(umr, 0, sizeof(*umr));
dd01e66a
SG		 2665 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2666 umr->flags = 1 << 7;
e126ba97
EC		 2667}
2668
968e78dd
HE		 2669static __be64 get_umr_reg_mr_mask(void)
2670{
2671 u64 result;
2672
2673 result = MLX5_MKEY_MASK_LEN |
2674 MLX5_MKEY_MASK_PAGE_SIZE |
2675 MLX5_MKEY_MASK_START_ADDR |
2676 MLX5_MKEY_MASK_PD |
2677 MLX5_MKEY_MASK_LR |
2678 MLX5_MKEY_MASK_LW |
2679 MLX5_MKEY_MASK_KEY |
2680 MLX5_MKEY_MASK_RR |
2681 MLX5_MKEY_MASK_RW |
2682 MLX5_MKEY_MASK_A |
2683 MLX5_MKEY_MASK_FREE;
2684
2685 return cpu_to_be64(result);
2686}
2687
2688static __be64 get_umr_unreg_mr_mask(void)
2689{
2690 u64 result;
2691
2692 result = MLX5_MKEY_MASK_FREE;
2693
2694 return cpu_to_be64(result);
2695}
2696
2697static __be64 get_umr_update_mtt_mask(void)
2698{
2699 u64 result;
2700
2701 result = MLX5_MKEY_MASK_FREE;
2702
2703 return cpu_to_be64(result);
2704}
2705
56e11d62
NO		 2706static __be64 get_umr_update_translation_mask(void)
2707{
2708 u64 result;
2709
2710 result = MLX5_MKEY_MASK_LEN |
2711 MLX5_MKEY_MASK_PAGE_SIZE |
2712 MLX5_MKEY_MASK_START_ADDR |
2713 MLX5_MKEY_MASK_KEY |
2714 MLX5_MKEY_MASK_FREE;
2715
2716 return cpu_to_be64(result);
2717}
2718
2719static __be64 get_umr_update_access_mask(void)
2720{
2721 u64 result;
2722
2723 result = MLX5_MKEY_MASK_LW |
2724 MLX5_MKEY_MASK_RR |
2725 MLX5_MKEY_MASK_RW |
2726 MLX5_MKEY_MASK_A |
2727 MLX5_MKEY_MASK_KEY |
2728 MLX5_MKEY_MASK_FREE;
2729
2730 return cpu_to_be64(result);
2731}
2732
2733static __be64 get_umr_update_pd_mask(void)
2734{
2735 u64 result;
2736
2737 result = MLX5_MKEY_MASK_PD |
2738 MLX5_MKEY_MASK_KEY |
2739 MLX5_MKEY_MASK_FREE;
2740
2741 return cpu_to_be64(result);
2742}
2743
e126ba97
EC		 2744static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2745 struct ib_send_wr *wr)
2746{
e622f2f4 2747 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 2748
2749 memset(umr, 0, sizeof(*umr));
2750
968e78dd
HE		 2751 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
2752 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
2753 else
2754 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
2755
e126ba97 2756 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 2757 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 2758 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
2759 umr->mkey_mask = get_umr_update_mtt_mask();
2760 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
2761 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
968e78dd 2762 }
56e11d62
NO		 2763 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
2764 umr->mkey_mask |= get_umr_update_translation_mask();
2765 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
2766 umr->mkey_mask |= get_umr_update_access_mask();
2767 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
2768 umr->mkey_mask |= get_umr_update_pd_mask();
2769 if (!umr->mkey_mask)
2770 umr->mkey_mask = get_umr_reg_mr_mask();
e126ba97 2771 } else {
968e78dd 2772 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 2773 }
2774
2775 if (!wr->num_sge)
968e78dd 2776 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 2777}
2778
2779static u8 get_umr_flags(int acc)
2780{
2781 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
2782 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
2783 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
2784 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 2785 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 2786}
2787
8a187ee5
SG		 2788static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
2789 struct mlx5_ib_mr *mr,
2790 u32 key, int access)
2791{
2792 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
2793
2794 memset(seg, 0, sizeof(*seg));
b005d316
SG		 2795
2796 if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
2797 seg->log2_page_size = ilog2(mr->ibmr.page_size);
2798 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
2799 /* KLMs take twice the size of MTTs */
2800 ndescs *= 2;
2801
2802 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 2803 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
2804 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2805 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
2806 seg->len = cpu_to_be64(mr->ibmr.length);
2807 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 2808}
2809
dd01e66a 2810static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 2811{
2812 memset(seg, 0, sizeof(*seg));
dd01e66a 2813 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2814}
2815
2816static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2817{
e622f2f4 2818 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 2819
e126ba97
EC		 2820 memset(seg, 0, sizeof(*seg));
2821 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 2822 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2823 return;
2824 }
2825
968e78dd
HE		 2826 seg->flags = convert_access(umrwr->access_flags);
2827 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
56e11d62
NO		 2828 if (umrwr->pd)
2829 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
968e78dd
HE		 2830 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2831 }
2832 seg->len = cpu_to_be64(umrwr->length);
2833 seg->log2_page_size = umrwr->page_shift;
746b5583 2834 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 2835 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 2836}
2837
8a187ee5
SG		 2838static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
2839 struct mlx5_ib_mr *mr,
2840 struct mlx5_ib_pd *pd)
2841{
2842 int bcount = mr->desc_size * mr->ndescs;
2843
2844 dseg->addr = cpu_to_be64(mr->desc_map);
2845 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
2846 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
2847}
2848
e126ba97
EC		 2849static __be32 send_ieth(struct ib_send_wr *wr)
2850{
2851 switch (wr->opcode) {
2852 case IB_WR_SEND_WITH_IMM:
2853 case IB_WR_RDMA_WRITE_WITH_IMM:
2854 return wr->ex.imm_data;
2855
2856 case IB_WR_SEND_WITH_INV:
2857 return cpu_to_be32(wr->ex.invalidate_rkey);
2858
2859 default:
2860 return 0;
2861 }
2862}
2863
2864static u8 calc_sig(void *wqe, int size)
2865{
2866 u8 *p = wqe;
2867 u8 res = 0;
2868 int i;
2869
2870 for (i = 0; i < size; i++)
2871 res ^= p[i];
2872
2873 return ~res;
2874}
2875
2876static u8 wq_sig(void *wqe)
2877{
2878 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2879}
2880
2881static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2882 void *wqe, int *sz)
2883{
2884 struct mlx5_wqe_inline_seg *seg;
2885 void *qend = qp->sq.qend;
2886 void *addr;
2887 int inl = 0;
2888 int copy;
2889 int len;
2890 int i;
2891
2892 seg = wqe;
2893 wqe += sizeof(*seg);
2894 for (i = 0; i < wr->num_sge; i++) {
2895 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2896 len = wr->sg_list[i].length;
2897 inl += len;
2898
2899 if (unlikely(inl > qp->max_inline_data))
2900 return -ENOMEM;
2901
2902 if (unlikely(wqe + len > qend)) {
2903 copy = qend - wqe;
2904 memcpy(wqe, addr, copy);
2905 addr += copy;
2906 len -= copy;
2907 wqe = mlx5_get_send_wqe(qp, 0);
2908 }
2909 memcpy(wqe, addr, len);
2910 wqe += len;
2911 }
2912
2913 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2914
2915 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2916
2917 return 0;
2918}
2919
e6631814
SG		 2920static u16 prot_field_size(enum ib_signature_type type)
2921{
2922 switch (type) {
2923 case IB_SIG_TYPE_T10_DIF:
2924 return MLX5_DIF_SIZE;
2925 default:
2926 return 0;
2927 }
2928}
2929
2930static u8 bs_selector(int block_size)
2931{
2932 switch (block_size) {
2933 case 512: return 0x1;
2934 case 520: return 0x2;
2935 case 4096: return 0x3;
2936 case 4160: return 0x4;
2937 case 1073741824: return 0x5;
2938 default: return 0;
2939 }
2940}
2941
78eda2bb
SG		 2942static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2943 struct mlx5_bsf_inl *inl)
e6631814 2944{
142537f4
SG		 2945 /* Valid inline section and allow BSF refresh */
2946 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2947 MLX5_BSF_REFRESH_DIF);
2948 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2949 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 2950 /* repeating block */
2951 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2952 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2953 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 2954
78eda2bb
SG		 2955 if (domain->sig.dif.ref_remap)
2956 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 2957
78eda2bb
SG		 2958 if (domain->sig.dif.app_escape) {
2959 if (domain->sig.dif.ref_escape)
2960 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2961 else
2962 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 2963 }
2964
78eda2bb
SG		 2965 inl->dif_app_bitmask_check =
2966 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 2967}
2968
2969static int mlx5_set_bsf(struct ib_mr *sig_mr,
2970 struct ib_sig_attrs *sig_attrs,
2971 struct mlx5_bsf *bsf, u32 data_size)
2972{
2973 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2974 struct mlx5_bsf_basic *basic = &bsf->basic;
2975 struct ib_sig_domain *mem = &sig_attrs->mem;
2976 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 2977
c7f44fbd 2978 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 2979
2980 /* Basic + Extended + Inline */
2981 basic->bsf_size_sbs = 1 << 7;
2982 /* Input domain check byte mask */
2983 basic->check_byte_mask = sig_attrs->check_mask;
2984 basic->raw_data_size = cpu_to_be32(data_size);
2985
2986 /* Memory domain */
e6631814 2987 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 2988 case IB_SIG_TYPE_NONE:
2989 break;
e6631814 2990 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 2991 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2992 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2993 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2994 break;
2995 default:
2996 return -EINVAL;
2997 }
e6631814 2998
78eda2bb
SG		 2999 /* Wire domain */
3000 switch (sig_attrs->wire.sig_type) {
3001 case IB_SIG_TYPE_NONE:
3002 break;
3003 case IB_SIG_TYPE_T10_DIF:
e6631814 3004 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3005 mem->sig_type == wire->sig_type) {
e6631814 3006 /* Same block structure */
142537f4 3007 basic->bsf_size_sbs |= 1 << 4;
e6631814 3008 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3009 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3010 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3011 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3012 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3013 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3014 } else
3015 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3016
142537f4 3017 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3018 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3019 break;
e6631814
SG		 3020 default:
3021 return -EINVAL;
3022 }
3023
3024 return 0;
3025}
3026
e622f2f4
CH		 3027static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3028 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3029{
e622f2f4
CH		 3030 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3031 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3032 struct mlx5_bsf *bsf;
e622f2f4
CH		 3033 u32 data_len = wr->wr.sg_list->length;
3034 u32 data_key = wr->wr.sg_list->lkey;
3035 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3036 int ret;
3037 int wqe_size;
3038
e622f2f4
CH		 3039 if (!wr->prot ||
3040 (data_key == wr->prot->lkey &&
3041 data_va == wr->prot->addr &&
3042 data_len == wr->prot->length)) {
e6631814
SG		 3043 /**
3044 * Source domain doesn't contain signature information
5c273b16 3045 * or data and protection are interleaved in memory.
e6631814
SG		 3046 * So need construct:
3047 * ------------------
3048 * | data_klm |
3049 * ------------------
3050 * | BSF |
3051 * ------------------
3052 **/
3053 struct mlx5_klm *data_klm = *seg;
3054
3055 data_klm->bcount = cpu_to_be32(data_len);
3056 data_klm->key = cpu_to_be32(data_key);
3057 data_klm->va = cpu_to_be64(data_va);
3058 wqe_size = ALIGN(sizeof(*data_klm), 64);
3059 } else {
3060 /**
3061 * Source domain contains signature information
3062 * So need construct a strided block format:
3063 * ---------------------------
3064 * | stride_block_ctrl |
3065 * ---------------------------
3066 * | data_klm |
3067 * ---------------------------
3068 * | prot_klm |
3069 * ---------------------------
3070 * | BSF |
3071 * ---------------------------
3072 **/
3073 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3074 struct mlx5_stride_block_entry *data_sentry;
3075 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3076 u32 prot_key = wr->prot->lkey;
3077 u64 prot_va = wr->prot->addr;
e6631814
SG		 3078 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3079 int prot_size;
3080
3081 sblock_ctrl = *seg;
3082 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3083 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3084
3085 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3086 if (!prot_size) {
3087 pr_err("Bad block size given: %u\n", block_size);
3088 return -EINVAL;
3089 }
3090 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3091 prot_size);
3092 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3093 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3094 sblock_ctrl->num_entries = cpu_to_be16(2);
3095
3096 data_sentry->bcount = cpu_to_be16(block_size);
3097 data_sentry->key = cpu_to_be32(data_key);
3098 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3099 data_sentry->stride = cpu_to_be16(block_size);
3100
e6631814
SG		 3101 prot_sentry->bcount = cpu_to_be16(prot_size);
3102 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3103 prot_sentry->va = cpu_to_be64(prot_va);
3104 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3105
e6631814
SG		 3106 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3107 sizeof(*prot_sentry), 64);
3108 }
3109
3110 *seg += wqe_size;
3111 *size += wqe_size / 16;
3112 if (unlikely((*seg == qp->sq.qend)))
3113 *seg = mlx5_get_send_wqe(qp, 0);
3114
3115 bsf = *seg;
3116 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3117 if (ret)
3118 return -EINVAL;
3119
3120 *seg += sizeof(*bsf);
3121 *size += sizeof(*bsf) / 16;
3122 if (unlikely((*seg == qp->sq.qend)))
3123 *seg = mlx5_get_send_wqe(qp, 0);
3124
3125 return 0;
3126}
3127
3128static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 3129 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 3130 u32 length, u32 pdn)
3131{
e622f2f4 3132 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3133 u32 sig_key = sig_mr->rkey;
d5436ba0 3134 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3135
3136 memset(seg, 0, sizeof(*seg));
3137
e622f2f4 3138 seg->flags = get_umr_flags(wr->access_flags) |
e6631814
SG		 3139 MLX5_ACCESS_MODE_KLM;
3140 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3141 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3142 MLX5_MKEY_BSF_EN | pdn);
3143 seg->len = cpu_to_be64(length);
3144 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3145 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3146}
3147
3148static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 3149 u32 nelements)
e6631814
SG		 3150{
3151 memset(umr, 0, sizeof(*umr));
3152
3153 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3154 umr->klm_octowords = get_klm_octo(nelements);
3155 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3156 umr->mkey_mask = sig_mkey_mask();
3157}
3158
3159
e622f2f4 3160static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3161 void **seg, int *size)
3162{
e622f2f4
CH		 3163 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3164 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 3165 u32 pdn = get_pd(qp)->pdn;
3166 u32 klm_oct_size;
3167 int region_len, ret;
3168
e622f2f4
CH		 3169 if (unlikely(wr->wr.num_sge != 1) ||
3170 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3171 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3172 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3173 return -EINVAL;
3174
3175 /* length of the protected region, data + protection */
e622f2f4
CH		 3176 region_len = wr->wr.sg_list->length;
3177 if (wr->prot &&
3178 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3179 wr->prot->addr != wr->wr.sg_list->addr ||
3180 wr->prot->length != wr->wr.sg_list->length))
3181 region_len += wr->prot->length;
e6631814
SG		 3182
3183 /**
3184 * KLM octoword size - if protection was provided
3185 * then we use strided block format (3 octowords),
3186 * else we use single KLM (1 octoword)
3187 **/
e622f2f4 3188 klm_oct_size = wr->prot ? 3 : 1;
e6631814 3189
e622f2f4 3190 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 3191 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3192 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3193 if (unlikely((*seg == qp->sq.qend)))
3194 *seg = mlx5_get_send_wqe(qp, 0);
3195
3196 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3197 *seg += sizeof(struct mlx5_mkey_seg);
3198 *size += sizeof(struct mlx5_mkey_seg) / 16;
3199 if (unlikely((*seg == qp->sq.qend)))
3200 *seg = mlx5_get_send_wqe(qp, 0);
3201
3202 ret = set_sig_data_segment(wr, qp, seg, size);
3203 if (ret)
3204 return ret;
3205
d5436ba0 3206 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3207 return 0;
3208}
3209
3210static int set_psv_wr(struct ib_sig_domain *domain,
3211 u32 psv_idx, void **seg, int *size)
3212{
3213 struct mlx5_seg_set_psv *psv_seg = *seg;
3214
3215 memset(psv_seg, 0, sizeof(*psv_seg));
3216 psv_seg->psv_num = cpu_to_be32(psv_idx);
3217 switch (domain->sig_type) {
78eda2bb
SG		 3218 case IB_SIG_TYPE_NONE:
3219 break;
e6631814
SG		 3220 case IB_SIG_TYPE_T10_DIF:
3221 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3222 domain->sig.dif.app_tag);
3223 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3224 break;
e6631814
SG		 3225 default:
3226 pr_err("Bad signature type given.\n");
3227 return 1;
3228 }
3229
78eda2bb
SG		 3230 *seg += sizeof(*psv_seg);
3231 *size += sizeof(*psv_seg) / 16;
3232
e6631814
SG		 3233 return 0;
3234}
3235
8a187ee5
SG		 3236static int set_reg_wr(struct mlx5_ib_qp *qp,
3237 struct ib_reg_wr *wr,
3238 void **seg, int *size)
3239{
3240 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3241 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3242
3243 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3244 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3245 "Invalid IB_SEND_INLINE send flag\n");
3246 return -EINVAL;
3247 }
3248
3249 set_reg_umr_seg(*seg, mr);
3250 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3251 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3252 if (unlikely((*seg == qp->sq.qend)))
3253 *seg = mlx5_get_send_wqe(qp, 0);
3254
3255 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3256 *seg += sizeof(struct mlx5_mkey_seg);
3257 *size += sizeof(struct mlx5_mkey_seg) / 16;
3258 if (unlikely((*seg == qp->sq.qend)))
3259 *seg = mlx5_get_send_wqe(qp, 0);
3260
3261 set_reg_data_seg(*seg, mr, pd);
3262 *seg += sizeof(struct mlx5_wqe_data_seg);
3263 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3264
3265 return 0;
3266}
3267
dd01e66a 3268static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3269{
dd01e66a 3270 set_linv_umr_seg(*seg);
e126ba97
EC		 3271 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3272 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3273 if (unlikely((*seg == qp->sq.qend)))
3274 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3275 set_linv_mkey_seg(*seg);
e126ba97
EC		 3276 *seg += sizeof(struct mlx5_mkey_seg);
3277 *size += sizeof(struct mlx5_mkey_seg) / 16;
3278 if (unlikely((*seg == qp->sq.qend)))
3279 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3280}
3281
3282static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3283{
3284 __be32 *p = NULL;
3285 int tidx = idx;
3286 int i, j;
3287
3288 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3289 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3290 if ((i & 0xf) == 0) {
3291 void *buf = mlx5_get_send_wqe(qp, tidx);
3292 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3293 p = buf;
3294 j = 0;
3295 }
3296 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3297 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3298 be32_to_cpu(p[j + 3]));
3299 }
3300}
3301
3302static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3303 unsigned bytecnt, struct mlx5_ib_qp *qp)
3304{
3305 while (bytecnt > 0) {
3306 __iowrite64_copy(dst++, src++, 8);
3307 __iowrite64_copy(dst++, src++, 8);
3308 __iowrite64_copy(dst++, src++, 8);
3309 __iowrite64_copy(dst++, src++, 8);
3310 __iowrite64_copy(dst++, src++, 8);
3311 __iowrite64_copy(dst++, src++, 8);
3312 __iowrite64_copy(dst++, src++, 8);
3313 __iowrite64_copy(dst++, src++, 8);
3314 bytecnt -= 64;
3315 if (unlikely(src == qp->sq.qend))
3316 src = mlx5_get_send_wqe(qp, 0);
3317 }
3318}
3319
3320static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3321{
3322 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3323 wr->send_flags & IB_SEND_FENCE))
3324 return MLX5_FENCE_MODE_STRONG_ORDERING;
3325
3326 if (unlikely(fence)) {
3327 if (wr->send_flags & IB_SEND_FENCE)
3328 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3329 else
3330 return fence;
3331
3332 } else {
3333 return 0;
3334 }
3335}
3336
6e5eadac
SG		 3337static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3338 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3339 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3340 int *size, int nreq)
3341{
3342 int err = 0;
3343
3344 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3345 err = -ENOMEM;
3346 return err;
3347 }
3348
3349 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3350 *seg = mlx5_get_send_wqe(qp, *idx);
3351 *ctrl = *seg;
3352 *(uint32_t *)(*seg + 8) = 0;
3353 (*ctrl)->imm = send_ieth(wr);
3354 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3355 (wr->send_flags & IB_SEND_SIGNALED ?
3356 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3357 (wr->send_flags & IB_SEND_SOLICITED ?
3358 MLX5_WQE_CTRL_SOLICITED : 0);
3359
3360 *seg += sizeof(**ctrl);
3361 *size = sizeof(**ctrl) / 16;
3362
3363 return err;
3364}
3365
3366static void finish_wqe(struct mlx5_ib_qp *qp,
3367 struct mlx5_wqe_ctrl_seg *ctrl,
3368 u8 size, unsigned idx, u64 wr_id,
3369 int nreq, u8 fence, u8 next_fence,
3370 u32 mlx5_opcode)
3371{
3372 u8 opmod = 0;
3373
3374 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3375 mlx5_opcode | ((u32)opmod << 24));
19098df2 3376 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3377 ctrl->fm_ce_se |= fence;
3378 qp->fm_cache = next_fence;
3379 if (unlikely(qp->wq_sig))
3380 ctrl->signature = wq_sig(ctrl);
3381
3382 qp->sq.wrid[idx] = wr_id;
3383 qp->sq.w_list[idx].opcode = mlx5_opcode;
3384 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3385 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3386 qp->sq.w_list[idx].next = qp->sq.cur_post;
3387}
3388
3389
e126ba97
EC		 3390int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3391 struct ib_send_wr **bad_wr)
3392{
3393 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3394 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
d16e91da 3395 struct mlx5_ib_qp *qp;
e6631814 3396 struct mlx5_ib_mr *mr;
e126ba97
EC		 3397 struct mlx5_wqe_data_seg *dpseg;
3398 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3399 struct mlx5_bf *bf;
e126ba97 3400 int uninitialized_var(size);
d16e91da 3401 void *qend;
e126ba97 3402 unsigned long flags;
e126ba97
EC		 3403 unsigned idx;
3404 int err = 0;
3405 int inl = 0;
3406 int num_sge;
3407 void *seg;
3408 int nreq;
3409 int i;
3410 u8 next_fence = 0;
e126ba97
EC		 3411 u8 fence;
3412
d16e91da
HE		 3413 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3414 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3415
3416 qp = to_mqp(ibqp);
3417 bf = qp->bf;
3418 qend = qp->sq.qend;
3419
e126ba97
EC		 3420 spin_lock_irqsave(&qp->sq.lock, flags);
3421
3422 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3423 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3424 mlx5_ib_warn(dev, "\n");
3425 err = -EINVAL;
3426 *bad_wr = wr;
3427 goto out;
3428 }
3429
6e5eadac
SG		 3430 fence = qp->fm_cache;
3431 num_sge = wr->num_sge;
3432 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97
EC		 3433 mlx5_ib_warn(dev, "\n");
3434 err = -ENOMEM;
3435 *bad_wr = wr;
3436 goto out;
3437 }
3438
6e5eadac
SG		 3439 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3440 if (err) {
e126ba97
EC		 3441 mlx5_ib_warn(dev, "\n");
3442 err = -ENOMEM;
3443 *bad_wr = wr;
3444 goto out;
3445 }
3446
e126ba97
EC		 3447 switch (ibqp->qp_type) {
3448 case IB_QPT_XRC_INI:
3449 xrc = seg;
e126ba97
EC		 3450 seg += sizeof(*xrc);
3451 size += sizeof(*xrc) / 16;
3452 /* fall through */
3453 case IB_QPT_RC:
3454 switch (wr->opcode) {
3455 case IB_WR_RDMA_READ:
3456 case IB_WR_RDMA_WRITE:
3457 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3458 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3459 rdma_wr(wr)->rkey);
f241e749 3460 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3461 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3462 break;
3463
3464 case IB_WR_ATOMIC_CMP_AND_SWP:
3465 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3466 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3467 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3468 err = -ENOSYS;
3469 *bad_wr = wr;
3470 goto out;
e126ba97
EC		 3471
3472 case IB_WR_LOCAL_INV:
3473 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3474 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3475 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3476 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3477 num_sge = 0;
3478 break;
3479
8a187ee5
SG		 3480 case IB_WR_REG_MR:
3481 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3482 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3483 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3484 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3485 if (err) {
3486 *bad_wr = wr;
3487 goto out;
3488 }
3489 num_sge = 0;
3490 break;
3491
e6631814
SG		 3492 case IB_WR_REG_SIG_MR:
3493 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3494 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3495
3496 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3497 err = set_sig_umr_wr(wr, qp, &seg, &size);
3498 if (err) {
3499 mlx5_ib_warn(dev, "\n");
3500 *bad_wr = wr;
3501 goto out;
3502 }
3503
3504 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3505 nreq, get_fence(fence, wr),
3506 next_fence, MLX5_OPCODE_UMR);
3507 /*
3508 * SET_PSV WQEs are not signaled and solicited
3509 * on error
3510 */
3511 wr->send_flags &= ~IB_SEND_SIGNALED;
3512 wr->send_flags |= IB_SEND_SOLICITED;
3513 err = begin_wqe(qp, &seg, &ctrl, wr,
3514 &idx, &size, nreq);
3515 if (err) {
3516 mlx5_ib_warn(dev, "\n");
3517 err = -ENOMEM;
3518 *bad_wr = wr;
3519 goto out;
3520 }
3521
e622f2f4 3522 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3523 mr->sig->psv_memory.psv_idx, &seg,
3524 &size);
3525 if (err) {
3526 mlx5_ib_warn(dev, "\n");
3527 *bad_wr = wr;
3528 goto out;
3529 }
3530
3531 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3532 nreq, get_fence(fence, wr),
3533 next_fence, MLX5_OPCODE_SET_PSV);
3534 err = begin_wqe(qp, &seg, &ctrl, wr,
3535 &idx, &size, nreq);
3536 if (err) {
3537 mlx5_ib_warn(dev, "\n");
3538 err = -ENOMEM;
3539 *bad_wr = wr;
3540 goto out;
3541 }
3542
3543 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3544 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3545 mr->sig->psv_wire.psv_idx, &seg,
3546 &size);
3547 if (err) {
3548 mlx5_ib_warn(dev, "\n");
3549 *bad_wr = wr;
3550 goto out;
3551 }
3552
3553 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3554 nreq, get_fence(fence, wr),
3555 next_fence, MLX5_OPCODE_SET_PSV);
3556 num_sge = 0;
3557 goto skip_psv;
3558
e126ba97
EC		 3559 default:
3560 break;
3561 }
3562 break;
3563
3564 case IB_QPT_UC:
3565 switch (wr->opcode) {
3566 case IB_WR_RDMA_WRITE:
3567 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3568 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3569 rdma_wr(wr)->rkey);
e126ba97
EC		 3570 seg += sizeof(struct mlx5_wqe_raddr_seg);
3571 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3572 break;
3573
3574 default:
3575 break;
3576 }
3577 break;
3578
e126ba97 3579 case IB_QPT_SMI:
d16e91da 3580 case MLX5_IB_QPT_HW_GSI:
e126ba97 3581 set_datagram_seg(seg, wr);
f241e749 3582 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 3583 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3584 if (unlikely((seg == qend)))
3585 seg = mlx5_get_send_wqe(qp, 0);
3586 break;
f0313965
ES		 3587 case IB_QPT_UD:
3588 set_datagram_seg(seg, wr);
3589 seg += sizeof(struct mlx5_wqe_datagram_seg);
3590 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3591
3592 if (unlikely((seg == qend)))
3593 seg = mlx5_get_send_wqe(qp, 0);
3594
3595 /* handle qp that supports ud offload */
3596 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3597 struct mlx5_wqe_eth_pad *pad;
e126ba97 3598
f0313965
ES		 3599 pad = seg;
3600 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3601 seg += sizeof(struct mlx5_wqe_eth_pad);
3602 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3603
3604 seg = set_eth_seg(seg, wr, qend, qp, &size);
3605
3606 if (unlikely((seg == qend)))
3607 seg = mlx5_get_send_wqe(qp, 0);
3608 }
3609 break;
e126ba97
EC		 3610 case MLX5_IB_QPT_REG_UMR:
3611 if (wr->opcode != MLX5_IB_WR_UMR) {
3612 err = -EINVAL;
3613 mlx5_ib_warn(dev, "bad opcode\n");
3614 goto out;
3615 }
3616 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 3617 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
e126ba97
EC		 3618 set_reg_umr_segment(seg, wr);
3619 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3620 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3621 if (unlikely((seg == qend)))
3622 seg = mlx5_get_send_wqe(qp, 0);
3623 set_reg_mkey_segment(seg, wr);
3624 seg += sizeof(struct mlx5_mkey_seg);
3625 size += sizeof(struct mlx5_mkey_seg) / 16;
3626 if (unlikely((seg == qend)))
3627 seg = mlx5_get_send_wqe(qp, 0);
3628 break;
3629
3630 default:
3631 break;
3632 }
3633
3634 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3635 int uninitialized_var(sz);
3636
3637 err = set_data_inl_seg(qp, wr, seg, &sz);
3638 if (unlikely(err)) {
3639 mlx5_ib_warn(dev, "\n");
3640 *bad_wr = wr;
3641 goto out;
3642 }
3643 inl = 1;
3644 size += sz;
3645 } else {
3646 dpseg = seg;
3647 for (i = 0; i < num_sge; i++) {
3648 if (unlikely(dpseg == qend)) {
3649 seg = mlx5_get_send_wqe(qp, 0);
3650 dpseg = seg;
3651 }
3652 if (likely(wr->sg_list[i].length)) {
3653 set_data_ptr_seg(dpseg, wr->sg_list + i);
3654 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3655 dpseg++;
3656 }
3657 }
3658 }
3659
6e5eadac
SG		 3660 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3661 get_fence(fence, wr), next_fence,
3662 mlx5_ib_opcode[wr->opcode]);
e6631814 3663skip_psv:
e126ba97
EC		 3664 if (0)
3665 dump_wqe(qp, idx, size);
3666 }
3667
3668out:
3669 if (likely(nreq)) {
3670 qp->sq.head += nreq;
3671
3672 /* Make sure that descriptors are written before
3673 * updating doorbell record and ringing the doorbell
3674 */
3675 wmb();
3676
3677 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
3678
ada388f7
EC		 3679 /* Make sure doorbell record is visible to the HCA before
3680 * we hit doorbell */
3681 wmb();
3682
e126ba97
EC		 3683 if (bf->need_lock)
3684 spin_lock(&bf->lock);
6a4f139a
EC		 3685 else
3686 __acquire(&bf->lock);
e126ba97
EC		 3687
3688 /* TBD enable WC */
3689 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
3690 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
3691 /* wc_wmb(); */
3692 } else {
3693 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
3694 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
3695 /* Make sure doorbells don't leak out of SQ spinlock
3696 * and reach the HCA out of order.
3697 */
3698 mmiowb();
3699 }
3700 bf->offset ^= bf->buf_size;
3701 if (bf->need_lock)
3702 spin_unlock(&bf->lock);
6a4f139a
EC		 3703 else
3704 __release(&bf->lock);
e126ba97
EC		 3705 }
3706
3707 spin_unlock_irqrestore(&qp->sq.lock, flags);
3708
3709 return err;
3710}
3711
3712static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
3713{
3714 sig->signature = calc_sig(sig, size);
3715}
3716
3717int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3718 struct ib_recv_wr **bad_wr)
3719{
3720 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3721 struct mlx5_wqe_data_seg *scat;
3722 struct mlx5_rwqe_sig *sig;
3723 unsigned long flags;
3724 int err = 0;
3725 int nreq;
3726 int ind;
3727 int i;
3728
d16e91da
HE		 3729 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3730 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
3731
e126ba97
EC		 3732 spin_lock_irqsave(&qp->rq.lock, flags);
3733
3734 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3735
3736 for (nreq = 0; wr; nreq++, wr = wr->next) {
3737 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3738 err = -ENOMEM;
3739 *bad_wr = wr;
3740 goto out;
3741 }
3742
3743 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3744 err = -EINVAL;
3745 *bad_wr = wr;
3746 goto out;
3747 }
3748
3749 scat = get_recv_wqe(qp, ind);
3750 if (qp->wq_sig)
3751 scat++;
3752
3753 for (i = 0; i < wr->num_sge; i++)
3754 set_data_ptr_seg(scat + i, wr->sg_list + i);
3755
3756 if (i < qp->rq.max_gs) {
3757 scat[i].byte_count = 0;
3758 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
3759 scat[i].addr = 0;
3760 }
3761
3762 if (qp->wq_sig) {
3763 sig = (struct mlx5_rwqe_sig *)scat;
3764 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
3765 }
3766
3767 qp->rq.wrid[ind] = wr->wr_id;
3768
3769 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3770 }
3771
3772out:
3773 if (likely(nreq)) {
3774 qp->rq.head += nreq;
3775
3776 /* Make sure that descriptors are written before
3777 * doorbell record.
3778 */
3779 wmb();
3780
3781 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3782 }
3783
3784 spin_unlock_irqrestore(&qp->rq.lock, flags);
3785
3786 return err;
3787}
3788
3789static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
3790{
3791 switch (mlx5_state) {
3792 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
3793 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
3794 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
3795 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
3796 case MLX5_QP_STATE_SQ_DRAINING:
3797 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
3798 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
3799 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
3800 default: return -1;
3801 }
3802}
3803
3804static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
3805{
3806 switch (mlx5_mig_state) {
3807 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
3808 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
3809 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3810 default: return -1;
3811 }
3812}
3813
3814static int to_ib_qp_access_flags(int mlx5_flags)
3815{
3816 int ib_flags = 0;
3817
3818 if (mlx5_flags & MLX5_QP_BIT_RRE)
3819 ib_flags |= IB_ACCESS_REMOTE_READ;
3820 if (mlx5_flags & MLX5_QP_BIT_RWE)
3821 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3822 if (mlx5_flags & MLX5_QP_BIT_RAE)
3823 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3824
3825 return ib_flags;
3826}
3827
3828static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3829 struct mlx5_qp_path *path)
3830{
9603b61d 3831 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 3832
3833 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3834 ib_ah_attr->port_num = path->port;
3835
c7a08ac7 3836 if (ib_ah_attr->port_num == 0 ||
938fe83c 3837 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 3838 return;
3839
2811ba51 3840 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 3841
3842 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3843 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3844 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3845 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3846 if (ib_ah_attr->ah_flags) {
3847 ib_ah_attr->grh.sgid_index = path->mgid_index;
3848 ib_ah_attr->grh.hop_limit = path->hop_limit;
3849 ib_ah_attr->grh.traffic_class =
3850 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3851 ib_ah_attr->grh.flow_label =
3852 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3853 memcpy(ib_ah_attr->grh.dgid.raw,
3854 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3855 }
3856}
3857
6d2f89df 3858static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
3859 struct mlx5_ib_sq *sq,
3860 u8 *sq_state)
3861{
3862 void *out;
3863 void *sqc;
3864 int inlen;
3865 int err;
3866
3867 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
3868 out = mlx5_vzalloc(inlen);
3869 if (!out)
3870 return -ENOMEM;
3871
3872 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
3873 if (err)
3874 goto out;
3875
3876 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
3877 *sq_state = MLX5_GET(sqc, sqc, state);
3878 sq->state = *sq_state;
3879
3880out:
3881 kvfree(out);
3882 return err;
3883}
3884
3885static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
3886 struct mlx5_ib_rq *rq,
3887 u8 *rq_state)
3888{
3889 void *out;
3890 void *rqc;
3891 int inlen;
3892 int err;
3893
3894 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
3895 out = mlx5_vzalloc(inlen);
3896 if (!out)
3897 return -ENOMEM;
3898
3899 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
3900 if (err)
3901 goto out;
3902
3903 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3904 *rq_state = MLX5_GET(rqc, rqc, state);
3905 rq->state = *rq_state;
3906
3907out:
3908 kvfree(out);
3909 return err;
3910}
3911
3912static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
3913 struct mlx5_ib_qp *qp, u8 *qp_state)
3914{
3915 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
3916 [MLX5_RQC_STATE_RST] = {
3917 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3918 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3919 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
3920 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
3921 },
3922 [MLX5_RQC_STATE_RDY] = {
3923 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3924 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3925 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
3926 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
3927 },
3928 [MLX5_RQC_STATE_ERR] = {
3929 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3930 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3931 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
3932 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
3933 },
3934 [MLX5_RQ_STATE_NA] = {
3935 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3936 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3937 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
3938 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
3939 },
3940 };
3941
3942 *qp_state = sqrq_trans[rq_state][sq_state];
3943
3944 if (*qp_state == MLX5_QP_STATE_BAD) {
3945 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
3946 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
3947 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
3948 return -EINVAL;
3949 }
3950
3951 if (*qp_state == MLX5_QP_STATE)
3952 *qp_state = qp->state;
3953
3954 return 0;
3955}
3956
3957static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
3958 struct mlx5_ib_qp *qp,
3959 u8 *raw_packet_qp_state)
3960{
3961 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3962 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3963 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3964 int err;
3965 u8 sq_state = MLX5_SQ_STATE_NA;
3966 u8 rq_state = MLX5_RQ_STATE_NA;
3967
3968 if (qp->sq.wqe_cnt) {
3969 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
3970 if (err)
3971 return err;
3972 }
3973
3974 if (qp->rq.wqe_cnt) {
3975 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
3976 if (err)
3977 return err;
3978 }
3979
3980 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
3981 raw_packet_qp_state);
3982}
3983
3984static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3985 struct ib_qp_attr *qp_attr)
e126ba97 3986{
e126ba97
EC		 3987 struct mlx5_query_qp_mbox_out *outb;
3988 struct mlx5_qp_context *context;
3989 int mlx5_state;
3990 int err = 0;
3991
e126ba97 3992 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
6d2f89df 3993 if (!outb)
3994 return -ENOMEM;
3995
e126ba97 3996 context = &outb->ctx;
19098df2 3997 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
3998 sizeof(*outb));
e126ba97 3999 if (err)
6d2f89df 4000 goto out;
e126ba97
EC		 4001
4002 mlx5_state = be32_to_cpu(context->flags) >> 28;
4003
4004 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4005 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4006 qp_attr->path_mig_state =
4007 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4008 qp_attr->qkey = be32_to_cpu(context->qkey);
4009 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4010 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4011 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4012 qp_attr->qp_access_flags =
4013 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4014
4015 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4016 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4017 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4018 qp_attr->alt_pkey_index =
4019 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4020 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4021 }
4022
d3ae2bde 4023 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4024 qp_attr->port_num = context->pri_path.port;
4025
4026 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4027 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4028
4029 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4030
4031 qp_attr->max_dest_rd_atomic =
4032 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4033 qp_attr->min_rnr_timer =
4034 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4035 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4036 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4037 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4038 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4039
4040out:
4041 kfree(outb);
4042 return err;
4043}
4044
4045int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4046 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4047{
4048 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4049 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4050 int err = 0;
4051 u8 raw_packet_qp_state;
4052
d16e91da
HE		 4053 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4054 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4055 qp_init_attr);
4056
6d2f89df 4057#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4058 /*
4059 * Wait for any outstanding page faults, in case the user frees memory
4060 * based upon this query's result.
4061 */
4062 flush_workqueue(mlx5_ib_page_fault_wq);
4063#endif
4064
4065 mutex_lock(&qp->mutex);
4066
4067 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4068 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4069 if (err)
4070 goto out;
4071 qp->state = raw_packet_qp_state;
4072 qp_attr->port_num = 1;
4073 } else {
4074 err = query_qp_attr(dev, qp, qp_attr);
4075 if (err)
4076 goto out;
4077 }
4078
4079 qp_attr->qp_state = qp->state;
e126ba97
EC		 4080 qp_attr->cur_qp_state = qp_attr->qp_state;
4081 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4082 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4083
4084 if (!ibqp->uobject) {
0540d814 4085 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4086 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4087 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4088 } else {
4089 qp_attr->cap.max_send_wr = 0;
4090 qp_attr->cap.max_send_sge = 0;
4091 }
4092
0540d814
NO		 4093 qp_init_attr->qp_type = ibqp->qp_type;
4094 qp_init_attr->recv_cq = ibqp->recv_cq;
4095 qp_init_attr->send_cq = ibqp->send_cq;
4096 qp_init_attr->srq = ibqp->srq;
4097 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4098
4099 qp_init_attr->cap = qp_attr->cap;
4100
4101 qp_init_attr->create_flags = 0;
4102 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4103 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4104
051f2630
LR		 4105 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4106 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4107 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4108 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4109 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4110 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4111 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4112 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4113
e126ba97
EC		 4114 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4115 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4116
e126ba97
EC		 4117out:
4118 mutex_unlock(&qp->mutex);
4119 return err;
4120}
4121
4122struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4123 struct ib_ucontext *context,
4124 struct ib_udata *udata)
4125{
4126 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4127 struct mlx5_ib_xrcd *xrcd;
4128 int err;
4129
938fe83c 4130 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4131 return ERR_PTR(-ENOSYS);
4132
4133 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4134 if (!xrcd)
4135 return ERR_PTR(-ENOMEM);
4136
9603b61d 4137 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4138 if (err) {
4139 kfree(xrcd);
4140 return ERR_PTR(-ENOMEM);
4141 }
4142
4143 return &xrcd->ibxrcd;
4144}
4145
4146int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4147{
4148 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4149 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4150 int err;
4151
9603b61d 4152 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4153 if (err) {
4154 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4155 return err;
4156 }
4157
4158 kfree(xrcd);
4159
4160 return 0;
4161}
Ubuntu Hirsute Linux kernel mirror