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IB/uverbs: Introduce RWQ Indirection table
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97
EC		 37#include "mlx5_ib.h"
38#include "user.h"
39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97
EC		 79
80static int is_qp0(enum ib_qp_type qp_type)
81{
82 return qp_type == IB_QPT_SMI;
83}
84
e126ba97
EC		 85static int is_sqp(enum ib_qp_type qp_type)
86{
87 return is_qp0(qp_type) || is_qp1(qp_type);
88}
89
90static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
91{
92 return mlx5_buf_offset(&qp->buf, offset);
93}
94
95static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
96{
97 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
98}
99
100void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
101{
102 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
103}
104
c1395a2a
HE		 105/**
106 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
107 *
108 * @qp: QP to copy from.
109 * @send: copy from the send queue when non-zero, use the receive queue
110 * otherwise.
111 * @wqe_index: index to start copying from. For send work queues, the
112 * wqe_index is in units of MLX5_SEND_WQE_BB.
113 * For receive work queue, it is the number of work queue
114 * element in the queue.
115 * @buffer: destination buffer.
116 * @length: maximum number of bytes to copy.
117 *
118 * Copies at least a single WQE, but may copy more data.
119 *
120 * Return: the number of bytes copied, or an error code.
121 */
122int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 123 void *buffer, u32 length,
124 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 125{
126 struct ib_device *ibdev = qp->ibqp.device;
127 struct mlx5_ib_dev *dev = to_mdev(ibdev);
128 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
129 size_t offset;
130 size_t wq_end;
19098df2 131 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 132 u32 first_copy_length;
133 int wqe_length;
134 int ret;
135
136 if (wq->wqe_cnt == 0) {
137 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
138 qp->ibqp.qp_type);
139 return -EINVAL;
140 }
141
142 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
143 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
144
145 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
146 return -EINVAL;
147
148 if (offset > umem->length ||
149 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
150 return -EINVAL;
151
152 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
153 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
154 if (ret)
155 return ret;
156
157 if (send) {
158 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
159 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
160
161 wqe_length = ds * MLX5_WQE_DS_UNITS;
162 } else {
163 wqe_length = 1 << wq->wqe_shift;
164 }
165
166 if (wqe_length <= first_copy_length)
167 return first_copy_length;
168
169 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
170 wqe_length - first_copy_length);
171 if (ret)
172 return ret;
173
174 return wqe_length;
175}
176
e126ba97
EC		 177static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
178{
179 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
180 struct ib_event event;
181
19098df2 182 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
183 /* This event is only valid for trans_qps */
184 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
185 }
e126ba97
EC		 186
187 if (ibqp->event_handler) {
188 event.device = ibqp->device;
189 event.element.qp = ibqp;
190 switch (type) {
191 case MLX5_EVENT_TYPE_PATH_MIG:
192 event.event = IB_EVENT_PATH_MIG;
193 break;
194 case MLX5_EVENT_TYPE_COMM_EST:
195 event.event = IB_EVENT_COMM_EST;
196 break;
197 case MLX5_EVENT_TYPE_SQ_DRAINED:
198 event.event = IB_EVENT_SQ_DRAINED;
199 break;
200 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
201 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
202 break;
203 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
204 event.event = IB_EVENT_QP_FATAL;
205 break;
206 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
207 event.event = IB_EVENT_PATH_MIG_ERR;
208 break;
209 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
210 event.event = IB_EVENT_QP_REQ_ERR;
211 break;
212 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
213 event.event = IB_EVENT_QP_ACCESS_ERR;
214 break;
215 default:
216 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
217 return;
218 }
219
220 ibqp->event_handler(&event, ibqp->qp_context);
221 }
222}
223
224static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
225 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
226{
227 int wqe_size;
228 int wq_size;
229
230 /* Sanity check RQ size before proceeding */
938fe83c 231 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 232 return -EINVAL;
233
234 if (!has_rq) {
235 qp->rq.max_gs = 0;
236 qp->rq.wqe_cnt = 0;
237 qp->rq.wqe_shift = 0;
0540d814
NO		 238 cap->max_recv_wr = 0;
239 cap->max_recv_sge = 0;
e126ba97
EC		 240 } else {
241 if (ucmd) {
242 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
243 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
244 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
245 qp->rq.max_post = qp->rq.wqe_cnt;
246 } else {
247 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
248 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
249 wqe_size = roundup_pow_of_two(wqe_size);
250 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
251 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
252 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 253 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 254 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
255 wqe_size,
938fe83c
SM		 256 MLX5_CAP_GEN(dev->mdev,
257 max_wqe_sz_rq));
e126ba97
EC		 258 return -EINVAL;
259 }
260 qp->rq.wqe_shift = ilog2(wqe_size);
261 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
262 qp->rq.max_post = qp->rq.wqe_cnt;
263 }
264 }
265
266 return 0;
267}
268
f0313965 269static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 270{
618af384 271 int size = 0;
e126ba97 272
f0313965 273 switch (attr->qp_type) {
e126ba97 274 case IB_QPT_XRC_INI:
b125a54b 275 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 276 /* fall through */
277 case IB_QPT_RC:
278 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 279 max(sizeof(struct mlx5_wqe_atomic_seg) +
280 sizeof(struct mlx5_wqe_raddr_seg),
281 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
282 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 283 break;
284
b125a54b
EC		 285 case IB_QPT_XRC_TGT:
286 return 0;
287
e126ba97 288 case IB_QPT_UC:
b125a54b 289 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 290 max(sizeof(struct mlx5_wqe_raddr_seg),
291 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
292 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 293 break;
294
295 case IB_QPT_UD:
f0313965
ES		 296 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
297 size += sizeof(struct mlx5_wqe_eth_pad) +
298 sizeof(struct mlx5_wqe_eth_seg);
299 /* fall through */
e126ba97 300 case IB_QPT_SMI:
d16e91da 301 case MLX5_IB_QPT_HW_GSI:
b125a54b 302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 303 sizeof(struct mlx5_wqe_datagram_seg);
304 break;
305
306 case MLX5_IB_QPT_REG_UMR:
b125a54b 307 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 308 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
309 sizeof(struct mlx5_mkey_seg);
310 break;
311
312 default:
313 return -EINVAL;
314 }
315
316 return size;
317}
318
319static int calc_send_wqe(struct ib_qp_init_attr *attr)
320{
321 int inl_size = 0;
322 int size;
323
f0313965 324 size = sq_overhead(attr);
e126ba97
EC		 325 if (size < 0)
326 return size;
327
328 if (attr->cap.max_inline_data) {
329 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
330 attr->cap.max_inline_data;
331 }
332
333 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 334 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
335 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
336 return MLX5_SIG_WQE_SIZE;
337 else
338 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 339}
340
341static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
342 struct mlx5_ib_qp *qp)
343{
344 int wqe_size;
345 int wq_size;
346
347 if (!attr->cap.max_send_wr)
348 return 0;
349
350 wqe_size = calc_send_wqe(attr);
351 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
352 if (wqe_size < 0)
353 return wqe_size;
354
938fe83c 355 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 356 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 357 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 358 return -EINVAL;
359 }
360
f0313965
ES		 361 qp->max_inline_data = wqe_size - sq_overhead(attr) -
362 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 363 attr->cap.max_inline_data = qp->max_inline_data;
364
e1e66cc2
SG		 365 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
366 qp->signature_en = true;
367
e126ba97
EC		 368 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
369 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 370 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
b125a54b 371 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
938fe83c
SM		 372 qp->sq.wqe_cnt,
373 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 374 return -ENOMEM;
375 }
e126ba97
EC		 376 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
377 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 378 qp->sq.max_post = wq_size / wqe_size;
379 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 380
381 return wq_size;
382}
383
384static int set_user_buf_size(struct mlx5_ib_dev *dev,
385 struct mlx5_ib_qp *qp,
19098df2 386 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 387 struct mlx5_ib_qp_base *base,
388 struct ib_qp_init_attr *attr)
e126ba97
EC		 389{
390 int desc_sz = 1 << qp->sq.wqe_shift;
391
938fe83c 392 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 393 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 394 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 395 return -EINVAL;
396 }
397
398 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
399 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
400 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
401 return -EINVAL;
402 }
403
404 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
405
938fe83c 406 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 407 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 408 qp->sq.wqe_cnt,
409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 410 return -EINVAL;
411 }
412
0fb2ed66 413 if (attr->qp_type == IB_QPT_RAW_PACKET) {
414 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
415 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
416 } else {
417 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
418 (qp->sq.wqe_cnt << 6);
419 }
e126ba97
EC		 420
421 return 0;
422}
423
424static int qp_has_rq(struct ib_qp_init_attr *attr)
425{
426 if (attr->qp_type == IB_QPT_XRC_INI ||
427 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
428 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
429 !attr->cap.max_recv_wr)
430 return 0;
431
432 return 1;
433}
434
c1be5232
EC		 435static int first_med_uuar(void)
436{
437 return 1;
438}
439
440static int next_uuar(int n)
441{
442 n++;
443
444 while (((n % 4) & 2))
445 n++;
446
447 return n;
448}
449
450static int num_med_uuar(struct mlx5_uuar_info *uuari)
451{
452 int n;
453
454 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
455 uuari->num_low_latency_uuars - 1;
456
457 return n >= 0 ? n : 0;
458}
459
460static int max_uuari(struct mlx5_uuar_info *uuari)
461{
462 return uuari->num_uars * 4;
463}
464
465static int first_hi_uuar(struct mlx5_uuar_info *uuari)
466{
467 int med;
468 int i;
469 int t;
470
471 med = num_med_uuar(uuari);
472 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
473 t++;
474 if (t == med)
475 return next_uuar(i);
476 }
477
478 return 0;
479}
480
e126ba97
EC		 481static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
482{
e126ba97
EC		 483 int i;
484
c1be5232 485 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 486 if (!test_bit(i, uuari->bitmap)) {
487 set_bit(i, uuari->bitmap);
488 uuari->count[i]++;
489 return i;
490 }
491 }
492
493 return -ENOMEM;
494}
495
496static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
497{
c1be5232 498 int minidx = first_med_uuar();
e126ba97
EC		 499 int i;
500
c1be5232 501 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 502 if (uuari->count[i] < uuari->count[minidx])
503 minidx = i;
504 }
505
506 uuari->count[minidx]++;
507 return minidx;
508}
509
510static int alloc_uuar(struct mlx5_uuar_info *uuari,
511 enum mlx5_ib_latency_class lat)
512{
513 int uuarn = -EINVAL;
514
515 mutex_lock(&uuari->lock);
516 switch (lat) {
517 case MLX5_IB_LATENCY_CLASS_LOW:
518 uuarn = 0;
519 uuari->count[uuarn]++;
520 break;
521
522 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 523 if (uuari->ver < 2)
524 uuarn = -ENOMEM;
525 else
526 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 527 break;
528
529 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 530 if (uuari->ver < 2)
531 uuarn = -ENOMEM;
532 else
533 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 534 break;
535
536 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
537 uuarn = 2;
538 break;
539 }
540 mutex_unlock(&uuari->lock);
541
542 return uuarn;
543}
544
545static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
546{
547 clear_bit(uuarn, uuari->bitmap);
548 --uuari->count[uuarn];
549}
550
551static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
552{
553 clear_bit(uuarn, uuari->bitmap);
554 --uuari->count[uuarn];
555}
556
557static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
558{
559 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
560 int high_uuar = nuuars - uuari->num_low_latency_uuars;
561
562 mutex_lock(&uuari->lock);
563 if (uuarn == 0) {
564 --uuari->count[uuarn];
565 goto out;
566 }
567
568 if (uuarn < high_uuar) {
569 free_med_class_uuar(uuari, uuarn);
570 goto out;
571 }
572
573 free_high_class_uuar(uuari, uuarn);
574
575out:
576 mutex_unlock(&uuari->lock);
577}
578
579static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
580{
581 switch (state) {
582 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
583 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
584 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
585 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
586 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
587 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
588 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
589 default: return -1;
590 }
591}
592
593static int to_mlx5_st(enum ib_qp_type type)
594{
595 switch (type) {
596 case IB_QPT_RC: return MLX5_QP_ST_RC;
597 case IB_QPT_UC: return MLX5_QP_ST_UC;
598 case IB_QPT_UD: return MLX5_QP_ST_UD;
599 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
600 case IB_QPT_XRC_INI:
601 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
602 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 603 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 604 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 605 case IB_QPT_RAW_PACKET:
0fb2ed66 606 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 607 case IB_QPT_MAX:
608 default: return -EINVAL;
609 }
610}
611
612static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
613{
614 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
615}
616
19098df2 617static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
618 struct ib_pd *pd,
619 unsigned long addr, size_t size,
620 struct ib_umem **umem,
621 int *npages, int *page_shift, int *ncont,
622 u32 *offset)
623{
624 int err;
625
626 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
627 if (IS_ERR(*umem)) {
628 mlx5_ib_dbg(dev, "umem_get failed\n");
629 return PTR_ERR(*umem);
630 }
631
632 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
633
634 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
635 if (err) {
636 mlx5_ib_warn(dev, "bad offset\n");
637 goto err_umem;
638 }
639
640 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
641 addr, size, *npages, *page_shift, *ncont, *offset);
642
643 return 0;
644
645err_umem:
646 ib_umem_release(*umem);
647 *umem = NULL;
648
649 return err;
650}
651
79b20a6c
YH		 652static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
653{
654 struct mlx5_ib_ucontext *context;
655
656 context = to_mucontext(pd->uobject->context);
657 mlx5_ib_db_unmap_user(context, &rwq->db);
658 if (rwq->umem)
659 ib_umem_release(rwq->umem);
660}
661
662static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
663 struct mlx5_ib_rwq *rwq,
664 struct mlx5_ib_create_wq *ucmd)
665{
666 struct mlx5_ib_ucontext *context;
667 int page_shift = 0;
668 int npages;
669 u32 offset = 0;
670 int ncont = 0;
671 int err;
672
673 if (!ucmd->buf_addr)
674 return -EINVAL;
675
676 context = to_mucontext(pd->uobject->context);
677 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
678 rwq->buf_size, 0, 0);
679 if (IS_ERR(rwq->umem)) {
680 mlx5_ib_dbg(dev, "umem_get failed\n");
681 err = PTR_ERR(rwq->umem);
682 return err;
683 }
684
685 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
686 &ncont, NULL);
687 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
688 &rwq->rq_page_offset);
689 if (err) {
690 mlx5_ib_warn(dev, "bad offset\n");
691 goto err_umem;
692 }
693
694 rwq->rq_num_pas = ncont;
695 rwq->page_shift = page_shift;
696 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
697 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
698
699 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
700 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
701 npages, page_shift, ncont, offset);
702
703 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
704 if (err) {
705 mlx5_ib_dbg(dev, "map failed\n");
706 goto err_umem;
707 }
708
709 rwq->create_type = MLX5_WQ_USER;
710 return 0;
711
712err_umem:
713 ib_umem_release(rwq->umem);
714 return err;
715}
716
e126ba97
EC		 717static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
718 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 719 struct ib_qp_init_attr *attr,
e126ba97 720 struct mlx5_create_qp_mbox_in **in,
19098df2 721 struct mlx5_ib_create_qp_resp *resp, int *inlen,
722 struct mlx5_ib_qp_base *base)
e126ba97
EC		 723{
724 struct mlx5_ib_ucontext *context;
725 struct mlx5_ib_create_qp ucmd;
19098df2 726 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 727 int page_shift = 0;
e126ba97
EC		 728 int uar_index;
729 int npages;
9e9c47d0 730 u32 offset = 0;
e126ba97 731 int uuarn;
9e9c47d0 732 int ncont = 0;
e126ba97
EC		 733 int err;
734
735 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
736 if (err) {
737 mlx5_ib_dbg(dev, "copy failed\n");
738 return err;
739 }
740
741 context = to_mucontext(pd->uobject->context);
742 /*
743 * TBD: should come from the verbs when we have the API
744 */
051f2630
LR		 745 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
746 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
747 uuarn = MLX5_CROSS_CHANNEL_UUAR;
748 else {
749 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
e126ba97 750 if (uuarn < 0) {
051f2630
LR		 751 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
752 mlx5_ib_dbg(dev, "reverting to medium latency\n");
753 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
c1be5232 754 if (uuarn < 0) {
051f2630
LR		 755 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
756 mlx5_ib_dbg(dev, "reverting to high latency\n");
757 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
758 if (uuarn < 0) {
759 mlx5_ib_warn(dev, "uuar allocation failed\n");
760 return uuarn;
761 }
c1be5232 762 }
e126ba97
EC		 763 }
764 }
765
766 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
767 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
768
48fea837
HE		 769 qp->rq.offset = 0;
770 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
771 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
772
0fb2ed66 773 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97
EC		 774 if (err)
775 goto err_uuar;
776
19098df2 777 if (ucmd.buf_addr && ubuffer->buf_size) {
778 ubuffer->buf_addr = ucmd.buf_addr;
779 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
780 ubuffer->buf_size,
781 &ubuffer->umem, &npages, &page_shift,
782 &ncont, &offset);
783 if (err)
9e9c47d0 784 goto err_uuar;
9e9c47d0 785 } else {
19098df2 786 ubuffer->umem = NULL;
e126ba97 787 }
e126ba97
EC		 788
789 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
790 *in = mlx5_vzalloc(*inlen);
791 if (!*in) {
792 err = -ENOMEM;
793 goto err_umem;
794 }
19098df2 795 if (ubuffer->umem)
796 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
797 (*in)->pas, 0);
e126ba97 798 (*in)->ctx.log_pg_sz_remote_qpn =
1b77d2bd 799 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 800 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
801
802 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
803 resp->uuar_index = uuarn;
804 qp->uuarn = uuarn;
805
806 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
807 if (err) {
808 mlx5_ib_dbg(dev, "map failed\n");
809 goto err_free;
810 }
811
812 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
813 if (err) {
814 mlx5_ib_dbg(dev, "copy failed\n");
815 goto err_unmap;
816 }
817 qp->create_type = MLX5_QP_USER;
818
819 return 0;
820
821err_unmap:
822 mlx5_ib_db_unmap_user(context, &qp->db);
823
824err_free:
479163f4 825 kvfree(*in);
e126ba97
EC		 826
827err_umem:
19098df2 828 if (ubuffer->umem)
829 ib_umem_release(ubuffer->umem);
e126ba97
EC		 830
831err_uuar:
832 free_uuar(&context->uuari, uuarn);
833 return err;
834}
835
19098df2 836static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
837 struct mlx5_ib_qp_base *base)
e126ba97
EC		 838{
839 struct mlx5_ib_ucontext *context;
840
841 context = to_mucontext(pd->uobject->context);
842 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 843 if (base->ubuffer.umem)
844 ib_umem_release(base->ubuffer.umem);
e126ba97
EC		 845 free_uuar(&context->uuari, qp->uuarn);
846}
847
848static int create_kernel_qp(struct mlx5_ib_dev *dev,
849 struct ib_qp_init_attr *init_attr,
850 struct mlx5_ib_qp *qp,
19098df2 851 struct mlx5_create_qp_mbox_in **in, int *inlen,
852 struct mlx5_ib_qp_base *base)
e126ba97
EC		 853{
854 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
855 struct mlx5_uuar_info *uuari;
856 int uar_index;
857 int uuarn;
858 int err;
859
9603b61d 860 uuari = &dev->mdev->priv.uuari;
f0313965
ES		 861 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
862 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 863 IB_QP_CREATE_IPOIB_UD_LSO |
864 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 865 return -EINVAL;
e126ba97
EC		 866
867 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
868 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
869
870 uuarn = alloc_uuar(uuari, lc);
871 if (uuarn < 0) {
872 mlx5_ib_dbg(dev, "\n");
873 return -ENOMEM;
874 }
875
876 qp->bf = &uuari->bfs[uuarn];
877 uar_index = qp->bf->uar->index;
878
879 err = calc_sq_size(dev, init_attr, qp);
880 if (err < 0) {
881 mlx5_ib_dbg(dev, "err %d\n", err);
882 goto err_uuar;
883 }
884
885 qp->rq.offset = 0;
886 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 887 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 888
19098df2 889 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 890 if (err) {
891 mlx5_ib_dbg(dev, "err %d\n", err);
892 goto err_uuar;
893 }
894
895 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
896 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
897 *in = mlx5_vzalloc(*inlen);
898 if (!*in) {
899 err = -ENOMEM;
900 goto err_buf;
901 }
902 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
1b77d2bd
EC		 903 (*in)->ctx.log_pg_sz_remote_qpn =
904 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 905 /* Set "fast registration enabled" for all kernel QPs */
906 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
907 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
908
b11a4f9c
HE		 909 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
910 (*in)->ctx.deth_sqpn = cpu_to_be32(1);
911 qp->flags |= MLX5_IB_QP_SQPN_QP1;
912 }
913
e126ba97
EC		 914 mlx5_fill_page_array(&qp->buf, (*in)->pas);
915
9603b61d 916 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 917 if (err) {
918 mlx5_ib_dbg(dev, "err %d\n", err);
919 goto err_free;
920 }
921
e126ba97
EC		 922 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
923 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
924 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
925 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
926 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
927
928 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
929 !qp->sq.w_list || !qp->sq.wqe_head) {
930 err = -ENOMEM;
931 goto err_wrid;
932 }
933 qp->create_type = MLX5_QP_KERNEL;
934
935 return 0;
936
937err_wrid:
9603b61d 938 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 939 kfree(qp->sq.wqe_head);
940 kfree(qp->sq.w_list);
941 kfree(qp->sq.wrid);
942 kfree(qp->sq.wr_data);
943 kfree(qp->rq.wrid);
944
945err_free:
479163f4 946 kvfree(*in);
e126ba97
EC		 947
948err_buf:
9603b61d 949 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 950
951err_uuar:
9603b61d 952 free_uuar(&dev->mdev->priv.uuari, uuarn);
e126ba97
EC		 953 return err;
954}
955
956static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
957{
9603b61d 958 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 959 kfree(qp->sq.wqe_head);
960 kfree(qp->sq.w_list);
961 kfree(qp->sq.wrid);
962 kfree(qp->sq.wr_data);
963 kfree(qp->rq.wrid);
9603b61d
JM		 964 mlx5_buf_free(dev->mdev, &qp->buf);
965 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
e126ba97
EC		 966}
967
968static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
969{
970 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
971 (attr->qp_type == IB_QPT_XRC_INI))
972 return cpu_to_be32(MLX5_SRQ_RQ);
973 else if (!qp->has_rq)
974 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
975 else
976 return cpu_to_be32(MLX5_NON_ZERO_RQ);
977}
978
979static int is_connected(enum ib_qp_type qp_type)
980{
981 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
982 return 1;
983
984 return 0;
985}
986
0fb2ed66 987static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
988 struct mlx5_ib_sq *sq, u32 tdn)
989{
990 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
991 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
992
993 memset(in, 0, sizeof(in));
994
995 MLX5_SET(tisc, tisc, transport_domain, tdn);
996
997 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
998}
999
1000static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1001 struct mlx5_ib_sq *sq)
1002{
1003 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1004}
1005
1006static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1007 struct mlx5_ib_sq *sq, void *qpin,
1008 struct ib_pd *pd)
1009{
1010 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1011 __be64 *pas;
1012 void *in;
1013 void *sqc;
1014 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1015 void *wq;
1016 int inlen;
1017 int err;
1018 int page_shift = 0;
1019 int npages;
1020 int ncont = 0;
1021 u32 offset = 0;
1022
1023 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1024 &sq->ubuffer.umem, &npages, &page_shift,
1025 &ncont, &offset);
1026 if (err)
1027 return err;
1028
1029 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1030 in = mlx5_vzalloc(inlen);
1031 if (!in) {
1032 err = -ENOMEM;
1033 goto err_umem;
1034 }
1035
1036 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1037 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1038 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1039 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1040 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1041 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1042 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1043
1044 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1045 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1046 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1047 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1048 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1049 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1050 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1051 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1052 MLX5_SET(wq, wq, page_offset, offset);
1053
1054 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1055 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1056
1057 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1058
1059 kvfree(in);
1060
1061 if (err)
1062 goto err_umem;
1063
1064 return 0;
1065
1066err_umem:
1067 ib_umem_release(sq->ubuffer.umem);
1068 sq->ubuffer.umem = NULL;
1069
1070 return err;
1071}
1072
1073static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1074 struct mlx5_ib_sq *sq)
1075{
1076 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1077 ib_umem_release(sq->ubuffer.umem);
1078}
1079
1080static int get_rq_pas_size(void *qpc)
1081{
1082 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1083 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1084 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1085 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1086 u32 po_quanta = 1 << (log_page_size - 6);
1087 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1088 u32 page_size = 1 << log_page_size;
1089 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1090 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1091
1092 return rq_num_pas * sizeof(u64);
1093}
1094
1095static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1096 struct mlx5_ib_rq *rq, void *qpin)
1097{
358e42ea 1098 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1099 __be64 *pas;
1100 __be64 *qp_pas;
1101 void *in;
1102 void *rqc;
1103 void *wq;
1104 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1105 int inlen;
1106 int err;
1107 u32 rq_pas_size = get_rq_pas_size(qpc);
1108
1109 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1110 in = mlx5_vzalloc(inlen);
1111 if (!in)
1112 return -ENOMEM;
1113
1114 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1115 MLX5_SET(rqc, rqc, vsd, 1);
1116 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1117 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1118 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1119 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1120 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1121
358e42ea
MD		 1122 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1123 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1124
0fb2ed66 1125 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1126 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1127 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1128 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1129 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1130 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1131 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1132 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1133 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1134 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1135
1136 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1137 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1138 memcpy(pas, qp_pas, rq_pas_size);
1139
1140 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1141
1142 kvfree(in);
1143
1144 return err;
1145}
1146
1147static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1148 struct mlx5_ib_rq *rq)
1149{
1150 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1151}
1152
1153static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1154 struct mlx5_ib_rq *rq, u32 tdn)
1155{
1156 u32 *in;
1157 void *tirc;
1158 int inlen;
1159 int err;
1160
1161 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1162 in = mlx5_vzalloc(inlen);
1163 if (!in)
1164 return -ENOMEM;
1165
1166 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1167 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1168 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1169 MLX5_SET(tirc, tirc, transport_domain, tdn);
1170
1171 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1172
1173 kvfree(in);
1174
1175 return err;
1176}
1177
1178static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1179 struct mlx5_ib_rq *rq)
1180{
1181 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1182}
1183
1184static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1185 struct mlx5_create_qp_mbox_in *in,
1186 struct ib_pd *pd)
1187{
1188 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1189 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1190 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1191 struct ib_uobject *uobj = pd->uobject;
1192 struct ib_ucontext *ucontext = uobj->context;
1193 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1194 int err;
1195 u32 tdn = mucontext->tdn;
1196
1197 if (qp->sq.wqe_cnt) {
1198 err = create_raw_packet_qp_tis(dev, sq, tdn);
1199 if (err)
1200 return err;
1201
1202 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1203 if (err)
1204 goto err_destroy_tis;
1205
1206 sq->base.container_mibqp = qp;
1207 }
1208
1209 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1210 rq->base.container_mibqp = qp;
1211
0fb2ed66 1212 err = create_raw_packet_qp_rq(dev, rq, in);
1213 if (err)
1214 goto err_destroy_sq;
1215
0fb2ed66 1216
1217 err = create_raw_packet_qp_tir(dev, rq, tdn);
1218 if (err)
1219 goto err_destroy_rq;
1220 }
1221
1222 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1223 rq->base.mqp.qpn;
1224
1225 return 0;
1226
1227err_destroy_rq:
1228 destroy_raw_packet_qp_rq(dev, rq);
1229err_destroy_sq:
1230 if (!qp->sq.wqe_cnt)
1231 return err;
1232 destroy_raw_packet_qp_sq(dev, sq);
1233err_destroy_tis:
1234 destroy_raw_packet_qp_tis(dev, sq);
1235
1236 return err;
1237}
1238
1239static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1240 struct mlx5_ib_qp *qp)
1241{
1242 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1243 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1244 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1245
1246 if (qp->rq.wqe_cnt) {
1247 destroy_raw_packet_qp_tir(dev, rq);
1248 destroy_raw_packet_qp_rq(dev, rq);
1249 }
1250
1251 if (qp->sq.wqe_cnt) {
1252 destroy_raw_packet_qp_sq(dev, sq);
1253 destroy_raw_packet_qp_tis(dev, sq);
1254 }
1255}
1256
1257static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1258 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1259{
1260 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1261 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1262
1263 sq->sq = &qp->sq;
1264 rq->rq = &qp->rq;
1265 sq->doorbell = &qp->db;
1266 rq->doorbell = &qp->db;
1267}
1268
e126ba97
EC		 1269static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1270 struct ib_qp_init_attr *init_attr,
1271 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1272{
1273 struct mlx5_ib_resources *devr = &dev->devr;
938fe83c 1274 struct mlx5_core_dev *mdev = dev->mdev;
0fb2ed66 1275 struct mlx5_ib_qp_base *base;
e126ba97
EC		 1276 struct mlx5_ib_create_qp_resp resp;
1277 struct mlx5_create_qp_mbox_in *in;
1278 struct mlx5_ib_create_qp ucmd;
1279 int inlen = sizeof(*in);
1280 int err;
cfb5e088
HA		 1281 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1282 void *qpc;
e126ba97 1283
0fb2ed66 1284 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1285 &qp->raw_packet_qp.rq.base :
1286 &qp->trans_qp.base;
1287
1288 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1289 mlx5_ib_odp_create_qp(qp);
6aec21f6 1290
e126ba97
EC		 1291 mutex_init(&qp->mutex);
1292 spin_lock_init(&qp->sq.lock);
1293 spin_lock_init(&qp->rq.lock);
1294
f360d88a 1295 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1296 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1297 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1298 return -EINVAL;
1299 } else {
1300 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1301 }
1302 }
1303
051f2630
LR		 1304 if (init_attr->create_flags &
1305 (IB_QP_CREATE_CROSS_CHANNEL |
1306 IB_QP_CREATE_MANAGED_SEND |
1307 IB_QP_CREATE_MANAGED_RECV)) {
1308 if (!MLX5_CAP_GEN(mdev, cd)) {
1309 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1310 return -EINVAL;
1311 }
1312 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1313 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1314 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1315 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1316 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1317 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1318 }
f0313965
ES		 1319
1320 if (init_attr->qp_type == IB_QPT_UD &&
1321 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1322 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1323 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1324 return -EOPNOTSUPP;
1325 }
1326
358e42ea
MD		 1327 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1328 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1329 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1330 return -EOPNOTSUPP;
1331 }
1332 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1333 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1334 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1335 return -EOPNOTSUPP;
1336 }
1337 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1338 }
1339
e126ba97
EC		 1340 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1341 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1342
1343 if (pd && pd->uobject) {
1344 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1345 mlx5_ib_dbg(dev, "copy failed\n");
1346 return -EFAULT;
1347 }
1348
cfb5e088
HA		 1349 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1350 &ucmd, udata->inlen, &uidx);
1351 if (err)
1352 return err;
1353
e126ba97
EC		 1354 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1355 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1356 } else {
1357 qp->wq_sig = !!wq_signature;
1358 }
1359
1360 qp->has_rq = qp_has_rq(init_attr);
1361 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1362 qp, (pd && pd->uobject) ? &ucmd : NULL);
1363 if (err) {
1364 mlx5_ib_dbg(dev, "err %d\n", err);
1365 return err;
1366 }
1367
1368 if (pd) {
1369 if (pd->uobject) {
938fe83c
SM		 1370 __u32 max_wqes =
1371 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1372 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1373 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1374 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1375 mlx5_ib_dbg(dev, "invalid rq params\n");
1376 return -EINVAL;
1377 }
938fe83c 1378 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1379 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1380 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1381 return -EINVAL;
1382 }
b11a4f9c
HE		 1383 if (init_attr->create_flags &
1384 mlx5_ib_create_qp_sqpn_qp1()) {
1385 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1386 return -EINVAL;
1387 }
0fb2ed66 1388 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1389 &resp, &inlen, base);
e126ba97
EC		 1390 if (err)
1391 mlx5_ib_dbg(dev, "err %d\n", err);
1392 } else {
19098df2 1393 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1394 base);
e126ba97
EC		 1395 if (err)
1396 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1397 }
1398
1399 if (err)
1400 return err;
1401 } else {
1402 in = mlx5_vzalloc(sizeof(*in));
1403 if (!in)
1404 return -ENOMEM;
1405
1406 qp->create_type = MLX5_QP_EMPTY;
1407 }
1408
1409 if (is_sqp(init_attr->qp_type))
1410 qp->port = init_attr->port_num;
1411
1412 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1413 MLX5_QP_PM_MIGRATED << 11);
1414
1415 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1416 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1417 else
1418 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1419
1420 if (qp->wq_sig)
1421 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1422
f360d88a
EC		 1423 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1424 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1425
051f2630
LR		 1426 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1427 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1428 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1429 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1430 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1431 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1432
e126ba97
EC		 1433 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1434 int rcqe_sz;
1435 int scqe_sz;
1436
1437 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1438 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1439
1440 if (rcqe_sz == 128)
1441 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1442 else
1443 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1444
1445 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1446 if (scqe_sz == 128)
1447 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1448 else
1449 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1450 }
1451 }
1452
1453 if (qp->rq.wqe_cnt) {
1454 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1455 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1456 }
1457
1458 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1459
1460 if (qp->sq.wqe_cnt)
1461 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1462 else
1463 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1464
1465 /* Set default resources */
1466 switch (init_attr->qp_type) {
1467 case IB_QPT_XRC_TGT:
1468 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1469 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1470 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1471 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1472 break;
1473 case IB_QPT_XRC_INI:
1474 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1475 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1476 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1477 break;
1478 default:
1479 if (init_attr->srq) {
1480 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1481 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1482 } else {
1483 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
4aa17b28
HA		 1484 in->ctx.rq_type_srqn |=
1485 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1486 }
1487 }
1488
1489 if (init_attr->send_cq)
1490 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1491
1492 if (init_attr->recv_cq)
1493 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1494
1495 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1496
cfb5e088
HA		 1497 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1498 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1499 /* 0xffffff means we ask to work with cqe version 0 */
1500 MLX5_SET(qpc, qpc, user_index, uidx);
1501 }
f0313965
ES		 1502 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1503 if (init_attr->qp_type == IB_QPT_UD &&
1504 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1505 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1506 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1507 qp->flags |= MLX5_IB_QP_LSO;
1508 }
cfb5e088 1509
0fb2ed66 1510 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1511 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1512 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1513 err = create_raw_packet_qp(dev, qp, in, pd);
1514 } else {
1515 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1516 }
1517
e126ba97
EC		 1518 if (err) {
1519 mlx5_ib_dbg(dev, "create qp failed\n");
1520 goto err_create;
1521 }
1522
479163f4 1523 kvfree(in);
e126ba97 1524
19098df2 1525 base->container_mibqp = qp;
1526 base->mqp.event = mlx5_ib_qp_event;
e126ba97
EC		 1527
1528 return 0;
1529
1530err_create:
1531 if (qp->create_type == MLX5_QP_USER)
19098df2 1532 destroy_qp_user(pd, qp, base);
e126ba97
EC		 1533 else if (qp->create_type == MLX5_QP_KERNEL)
1534 destroy_qp_kernel(dev, qp);
1535
479163f4 1536 kvfree(in);
e126ba97
EC		 1537 return err;
1538}
1539
1540static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1541 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1542{
1543 if (send_cq) {
1544 if (recv_cq) {
1545 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1546 spin_lock_irq(&send_cq->lock);
1547 spin_lock_nested(&recv_cq->lock,
1548 SINGLE_DEPTH_NESTING);
1549 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1550 spin_lock_irq(&send_cq->lock);
1551 __acquire(&recv_cq->lock);
1552 } else {
1553 spin_lock_irq(&recv_cq->lock);
1554 spin_lock_nested(&send_cq->lock,
1555 SINGLE_DEPTH_NESTING);
1556 }
1557 } else {
1558 spin_lock_irq(&send_cq->lock);
6a4f139a 1559 __acquire(&recv_cq->lock);
e126ba97
EC		 1560 }
1561 } else if (recv_cq) {
1562 spin_lock_irq(&recv_cq->lock);
6a4f139a
EC		 1563 __acquire(&send_cq->lock);
1564 } else {
1565 __acquire(&send_cq->lock);
1566 __acquire(&recv_cq->lock);
e126ba97
EC		 1567 }
1568}
1569
1570static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1571 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1572{
1573 if (send_cq) {
1574 if (recv_cq) {
1575 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1576 spin_unlock(&recv_cq->lock);
1577 spin_unlock_irq(&send_cq->lock);
1578 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1579 __release(&recv_cq->lock);
1580 spin_unlock_irq(&send_cq->lock);
1581 } else {
1582 spin_unlock(&send_cq->lock);
1583 spin_unlock_irq(&recv_cq->lock);
1584 }
1585 } else {
6a4f139a 1586 __release(&recv_cq->lock);
e126ba97
EC		 1587 spin_unlock_irq(&send_cq->lock);
1588 }
1589 } else if (recv_cq) {
6a4f139a 1590 __release(&send_cq->lock);
e126ba97 1591 spin_unlock_irq(&recv_cq->lock);
6a4f139a
EC		 1592 } else {
1593 __release(&recv_cq->lock);
1594 __release(&send_cq->lock);
e126ba97
EC		 1595 }
1596}
1597
1598static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1599{
1600 return to_mpd(qp->ibqp.pd);
1601}
1602
1603static void get_cqs(struct mlx5_ib_qp *qp,
1604 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1605{
1606 switch (qp->ibqp.qp_type) {
1607 case IB_QPT_XRC_TGT:
1608 *send_cq = NULL;
1609 *recv_cq = NULL;
1610 break;
1611 case MLX5_IB_QPT_REG_UMR:
1612 case IB_QPT_XRC_INI:
1613 *send_cq = to_mcq(qp->ibqp.send_cq);
1614 *recv_cq = NULL;
1615 break;
1616
1617 case IB_QPT_SMI:
d16e91da 1618 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1619 case IB_QPT_RC:
1620 case IB_QPT_UC:
1621 case IB_QPT_UD:
1622 case IB_QPT_RAW_IPV6:
1623 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1624 case IB_QPT_RAW_PACKET:
e126ba97
EC		 1625 *send_cq = to_mcq(qp->ibqp.send_cq);
1626 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1627 break;
1628
e126ba97
EC		 1629 case IB_QPT_MAX:
1630 default:
1631 *send_cq = NULL;
1632 *recv_cq = NULL;
1633 break;
1634 }
1635}
1636
ad5f8e96 1637static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1638 u16 operation);
1639
e126ba97
EC		 1640static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1641{
1642 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1643 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
0fb2ed66 1644 struct mlx5_modify_qp_mbox_in *in;
e126ba97
EC		 1645 int err;
1646
0fb2ed66 1647 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1648 &qp->raw_packet_qp.rq.base :
1649 &qp->trans_qp.base;
1650
e126ba97
EC		 1651 in = kzalloc(sizeof(*in), GFP_KERNEL);
1652 if (!in)
1653 return;
7bef7ad2 1654
6aec21f6 1655 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1656 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1657 mlx5_ib_qp_disable_pagefaults(qp);
1658 err = mlx5_core_qp_modify(dev->mdev,
1659 MLX5_CMD_OP_2RST_QP, in, 0,
1660 &base->mqp);
1661 } else {
1662 err = modify_raw_packet_qp(dev, qp,
1663 MLX5_CMD_OP_2RST_QP);
1664 }
1665 if (err)
427c1e7b 1666 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1667 base->mqp.qpn);
6aec21f6 1668 }
e126ba97
EC		 1669
1670 get_cqs(qp, &send_cq, &recv_cq);
1671
1672 if (qp->create_type == MLX5_QP_KERNEL) {
1673 mlx5_ib_lock_cqs(send_cq, recv_cq);
19098df2 1674 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1675 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1676 if (send_cq != recv_cq)
19098df2 1677 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1678 NULL);
e126ba97
EC		 1679 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1680 }
1681
0fb2ed66 1682 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1683 destroy_raw_packet_qp(dev, qp);
1684 } else {
1685 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1686 if (err)
1687 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1688 base->mqp.qpn);
1689 }
e126ba97 1690
0fb2ed66 1691 kfree(in);
e126ba97
EC		 1692
1693 if (qp->create_type == MLX5_QP_KERNEL)
1694 destroy_qp_kernel(dev, qp);
1695 else if (qp->create_type == MLX5_QP_USER)
19098df2 1696 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1697}
1698
1699static const char *ib_qp_type_str(enum ib_qp_type type)
1700{
1701 switch (type) {
1702 case IB_QPT_SMI:
1703 return "IB_QPT_SMI";
1704 case IB_QPT_GSI:
1705 return "IB_QPT_GSI";
1706 case IB_QPT_RC:
1707 return "IB_QPT_RC";
1708 case IB_QPT_UC:
1709 return "IB_QPT_UC";
1710 case IB_QPT_UD:
1711 return "IB_QPT_UD";
1712 case IB_QPT_RAW_IPV6:
1713 return "IB_QPT_RAW_IPV6";
1714 case IB_QPT_RAW_ETHERTYPE:
1715 return "IB_QPT_RAW_ETHERTYPE";
1716 case IB_QPT_XRC_INI:
1717 return "IB_QPT_XRC_INI";
1718 case IB_QPT_XRC_TGT:
1719 return "IB_QPT_XRC_TGT";
1720 case IB_QPT_RAW_PACKET:
1721 return "IB_QPT_RAW_PACKET";
1722 case MLX5_IB_QPT_REG_UMR:
1723 return "MLX5_IB_QPT_REG_UMR";
1724 case IB_QPT_MAX:
1725 default:
1726 return "Invalid QP type";
1727 }
1728}
1729
1730struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1731 struct ib_qp_init_attr *init_attr,
1732 struct ib_udata *udata)
1733{
1734 struct mlx5_ib_dev *dev;
1735 struct mlx5_ib_qp *qp;
1736 u16 xrcdn = 0;
1737 int err;
1738
1739 if (pd) {
1740 dev = to_mdev(pd->device);
0fb2ed66 1741
1742 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1743 if (!pd->uobject) {
1744 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1745 return ERR_PTR(-EINVAL);
1746 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1747 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1748 return ERR_PTR(-EINVAL);
1749 }
1750 }
09f16cf5
MD		 1751 } else {
1752 /* being cautious here */
1753 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1754 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1755 pr_warn("%s: no PD for transport %s\n", __func__,
1756 ib_qp_type_str(init_attr->qp_type));
1757 return ERR_PTR(-EINVAL);
1758 }
1759 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 1760 }
1761
1762 switch (init_attr->qp_type) {
1763 case IB_QPT_XRC_TGT:
1764 case IB_QPT_XRC_INI:
938fe83c 1765 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 1766 mlx5_ib_dbg(dev, "XRC not supported\n");
1767 return ERR_PTR(-ENOSYS);
1768 }
1769 init_attr->recv_cq = NULL;
1770 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1771 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1772 init_attr->send_cq = NULL;
1773 }
1774
1775 /* fall through */
0fb2ed66 1776 case IB_QPT_RAW_PACKET:
e126ba97
EC		 1777 case IB_QPT_RC:
1778 case IB_QPT_UC:
1779 case IB_QPT_UD:
1780 case IB_QPT_SMI:
d16e91da 1781 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1782 case MLX5_IB_QPT_REG_UMR:
1783 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1784 if (!qp)
1785 return ERR_PTR(-ENOMEM);
1786
1787 err = create_qp_common(dev, pd, init_attr, udata, qp);
1788 if (err) {
1789 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1790 kfree(qp);
1791 return ERR_PTR(err);
1792 }
1793
1794 if (is_qp0(init_attr->qp_type))
1795 qp->ibqp.qp_num = 0;
1796 else if (is_qp1(init_attr->qp_type))
1797 qp->ibqp.qp_num = 1;
1798 else
19098df2 1799 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 1800
1801 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 1802 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
1803 to_mcq(init_attr->recv_cq)->mcq.cqn,
e126ba97
EC		 1804 to_mcq(init_attr->send_cq)->mcq.cqn);
1805
19098df2 1806 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 1807
1808 break;
1809
d16e91da
HE		 1810 case IB_QPT_GSI:
1811 return mlx5_ib_gsi_create_qp(pd, init_attr);
1812
e126ba97
EC		 1813 case IB_QPT_RAW_IPV6:
1814 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 1815 case IB_QPT_MAX:
1816 default:
1817 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1818 init_attr->qp_type);
1819 /* Don't support raw QPs */
1820 return ERR_PTR(-EINVAL);
1821 }
1822
1823 return &qp->ibqp;
1824}
1825
1826int mlx5_ib_destroy_qp(struct ib_qp *qp)
1827{
1828 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1829 struct mlx5_ib_qp *mqp = to_mqp(qp);
1830
d16e91da
HE		 1831 if (unlikely(qp->qp_type == IB_QPT_GSI))
1832 return mlx5_ib_gsi_destroy_qp(qp);
1833
e126ba97
EC		 1834 destroy_qp_common(dev, mqp);
1835
1836 kfree(mqp);
1837
1838 return 0;
1839}
1840
1841static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1842 int attr_mask)
1843{
1844 u32 hw_access_flags = 0;
1845 u8 dest_rd_atomic;
1846 u32 access_flags;
1847
1848 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1849 dest_rd_atomic = attr->max_dest_rd_atomic;
1850 else
19098df2 1851 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 1852
1853 if (attr_mask & IB_QP_ACCESS_FLAGS)
1854 access_flags = attr->qp_access_flags;
1855 else
19098df2 1856 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 1857
1858 if (!dest_rd_atomic)
1859 access_flags &= IB_ACCESS_REMOTE_WRITE;
1860
1861 if (access_flags & IB_ACCESS_REMOTE_READ)
1862 hw_access_flags |= MLX5_QP_BIT_RRE;
1863 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1864 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1865 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1866 hw_access_flags |= MLX5_QP_BIT_RWE;
1867
1868 return cpu_to_be32(hw_access_flags);
1869}
1870
1871enum {
1872 MLX5_PATH_FLAG_FL = 1 << 0,
1873 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1874 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1875};
1876
1877static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1878{
1879 if (rate == IB_RATE_PORT_CURRENT) {
1880 return 0;
1881 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1882 return -EINVAL;
1883 } else {
1884 while (rate != IB_RATE_2_5_GBPS &&
1885 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 1886 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 1887 --rate;
1888 }
1889
1890 return rate + MLX5_STAT_RATE_OFFSET;
1891}
1892
75850d0b 1893static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
1894 struct mlx5_ib_sq *sq, u8 sl)
1895{
1896 void *in;
1897 void *tisc;
1898 int inlen;
1899 int err;
1900
1901 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1902 in = mlx5_vzalloc(inlen);
1903 if (!in)
1904 return -ENOMEM;
1905
1906 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
1907
1908 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
1909 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
1910
1911 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
1912
1913 kvfree(in);
1914
1915 return err;
1916}
1917
1918static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1919 const struct ib_ah_attr *ah,
e126ba97 1920 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 1921 u32 path_flags, const struct ib_qp_attr *attr,
1922 bool alt)
e126ba97 1923{
2811ba51 1924 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97
EC		 1925 int err;
1926
e126ba97 1927 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 1928 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
1929 attr->pkey_index);
e126ba97 1930
e126ba97 1931 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 1932 if (ah->grh.sgid_index >=
1933 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 1934 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 1935 ah->grh.sgid_index,
1936 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 1937 return -EINVAL;
1938 }
2811ba51
AS		 1939 }
1940
1941 if (ll == IB_LINK_LAYER_ETHERNET) {
1942 if (!(ah->ah_flags & IB_AH_GRH))
1943 return -EINVAL;
1944 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
1945 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
1946 ah->grh.sgid_index);
1947 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
1948 } else {
d3ae2bde
NO		 1949 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1950 path->fl_free_ar |=
1951 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 1952 path->rlid = cpu_to_be16(ah->dlid);
1953 path->grh_mlid = ah->src_path_bits & 0x7f;
1954 if (ah->ah_flags & IB_AH_GRH)
1955 path->grh_mlid |= 1 << 7;
1956 path->dci_cfi_prio_sl = ah->sl & 0xf;
1957 }
1958
1959 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 1960 path->mgid_index = ah->grh.sgid_index;
1961 path->hop_limit = ah->grh.hop_limit;
1962 path->tclass_flowlabel =
1963 cpu_to_be32((ah->grh.traffic_class << 20) |
1964 (ah->grh.flow_label));
1965 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1966 }
1967
1968 err = ib_rate_to_mlx5(dev, ah->static_rate);
1969 if (err < 0)
1970 return err;
1971 path->static_rate = err;
1972 path->port = port;
1973
e126ba97 1974 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 1975 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 1976
75850d0b 1977 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
1978 return modify_raw_packet_eth_prio(dev->mdev,
1979 &qp->raw_packet_qp.sq,
1980 ah->sl & 0xf);
1981
e126ba97
EC		 1982 return 0;
1983}
1984
1985static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1986 [MLX5_QP_STATE_INIT] = {
1987 [MLX5_QP_STATE_INIT] = {
1988 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1989 MLX5_QP_OPTPAR_RAE |
1990 MLX5_QP_OPTPAR_RWE |
1991 MLX5_QP_OPTPAR_PKEY_INDEX |
1992 MLX5_QP_OPTPAR_PRI_PORT,
1993 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1994 MLX5_QP_OPTPAR_PKEY_INDEX |
1995 MLX5_QP_OPTPAR_PRI_PORT,
1996 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1997 MLX5_QP_OPTPAR_Q_KEY |
1998 MLX5_QP_OPTPAR_PRI_PORT,
1999 },
2000 [MLX5_QP_STATE_RTR] = {
2001 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2002 MLX5_QP_OPTPAR_RRE |
2003 MLX5_QP_OPTPAR_RAE |
2004 MLX5_QP_OPTPAR_RWE |
2005 MLX5_QP_OPTPAR_PKEY_INDEX,
2006 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2007 MLX5_QP_OPTPAR_RWE |
2008 MLX5_QP_OPTPAR_PKEY_INDEX,
2009 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2010 MLX5_QP_OPTPAR_Q_KEY,
2011 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2012 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2013 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2014 MLX5_QP_OPTPAR_RRE |
2015 MLX5_QP_OPTPAR_RAE |
2016 MLX5_QP_OPTPAR_RWE |
2017 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2018 },
2019 },
2020 [MLX5_QP_STATE_RTR] = {
2021 [MLX5_QP_STATE_RTS] = {
2022 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2023 MLX5_QP_OPTPAR_RRE |
2024 MLX5_QP_OPTPAR_RAE |
2025 MLX5_QP_OPTPAR_RWE |
2026 MLX5_QP_OPTPAR_PM_STATE |
2027 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2028 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2029 MLX5_QP_OPTPAR_RWE |
2030 MLX5_QP_OPTPAR_PM_STATE,
2031 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2032 },
2033 },
2034 [MLX5_QP_STATE_RTS] = {
2035 [MLX5_QP_STATE_RTS] = {
2036 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2037 MLX5_QP_OPTPAR_RAE |
2038 MLX5_QP_OPTPAR_RWE |
2039 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2040 MLX5_QP_OPTPAR_PM_STATE |
2041 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2042 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2043 MLX5_QP_OPTPAR_PM_STATE |
2044 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2045 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2046 MLX5_QP_OPTPAR_SRQN |
2047 MLX5_QP_OPTPAR_CQN_RCV,
2048 },
2049 },
2050 [MLX5_QP_STATE_SQER] = {
2051 [MLX5_QP_STATE_RTS] = {
2052 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2053 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2054 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2055 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2056 MLX5_QP_OPTPAR_RWE |
2057 MLX5_QP_OPTPAR_RAE |
2058 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2059 },
2060 },
2061};
2062
2063static int ib_nr_to_mlx5_nr(int ib_mask)
2064{
2065 switch (ib_mask) {
2066 case IB_QP_STATE:
2067 return 0;
2068 case IB_QP_CUR_STATE:
2069 return 0;
2070 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2071 return 0;
2072 case IB_QP_ACCESS_FLAGS:
2073 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2074 MLX5_QP_OPTPAR_RAE;
2075 case IB_QP_PKEY_INDEX:
2076 return MLX5_QP_OPTPAR_PKEY_INDEX;
2077 case IB_QP_PORT:
2078 return MLX5_QP_OPTPAR_PRI_PORT;
2079 case IB_QP_QKEY:
2080 return MLX5_QP_OPTPAR_Q_KEY;
2081 case IB_QP_AV:
2082 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2083 MLX5_QP_OPTPAR_PRI_PORT;
2084 case IB_QP_PATH_MTU:
2085 return 0;
2086 case IB_QP_TIMEOUT:
2087 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2088 case IB_QP_RETRY_CNT:
2089 return MLX5_QP_OPTPAR_RETRY_COUNT;
2090 case IB_QP_RNR_RETRY:
2091 return MLX5_QP_OPTPAR_RNR_RETRY;
2092 case IB_QP_RQ_PSN:
2093 return 0;
2094 case IB_QP_MAX_QP_RD_ATOMIC:
2095 return MLX5_QP_OPTPAR_SRA_MAX;
2096 case IB_QP_ALT_PATH:
2097 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2098 case IB_QP_MIN_RNR_TIMER:
2099 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2100 case IB_QP_SQ_PSN:
2101 return 0;
2102 case IB_QP_MAX_DEST_RD_ATOMIC:
2103 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2104 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2105 case IB_QP_PATH_MIG_STATE:
2106 return MLX5_QP_OPTPAR_PM_STATE;
2107 case IB_QP_CAP:
2108 return 0;
2109 case IB_QP_DEST_QPN:
2110 return 0;
2111 }
2112 return 0;
2113}
2114
2115static int ib_mask_to_mlx5_opt(int ib_mask)
2116{
2117 int result = 0;
2118 int i;
2119
2120 for (i = 0; i < 8 * sizeof(int); i++) {
2121 if ((1 << i) & ib_mask)
2122 result |= ib_nr_to_mlx5_nr(1 << i);
2123 }
2124
2125 return result;
2126}
2127
ad5f8e96 2128static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2129 struct mlx5_ib_rq *rq, int new_state)
2130{
2131 void *in;
2132 void *rqc;
2133 int inlen;
2134 int err;
2135
2136 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2137 in = mlx5_vzalloc(inlen);
2138 if (!in)
2139 return -ENOMEM;
2140
2141 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2142
2143 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2144 MLX5_SET(rqc, rqc, state, new_state);
2145
2146 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2147 if (err)
2148 goto out;
2149
2150 rq->state = new_state;
2151
2152out:
2153 kvfree(in);
2154 return err;
2155}
2156
2157static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2158 struct mlx5_ib_sq *sq, int new_state)
2159{
2160 void *in;
2161 void *sqc;
2162 int inlen;
2163 int err;
2164
2165 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2166 in = mlx5_vzalloc(inlen);
2167 if (!in)
2168 return -ENOMEM;
2169
2170 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2171
2172 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2173 MLX5_SET(sqc, sqc, state, new_state);
2174
2175 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2176 if (err)
2177 goto out;
2178
2179 sq->state = new_state;
2180
2181out:
2182 kvfree(in);
2183 return err;
2184}
2185
2186static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2187 u16 operation)
2188{
2189 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2190 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2191 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2192 int rq_state;
2193 int sq_state;
2194 int err;
2195
2196 switch (operation) {
2197 case MLX5_CMD_OP_RST2INIT_QP:
2198 rq_state = MLX5_RQC_STATE_RDY;
2199 sq_state = MLX5_SQC_STATE_RDY;
2200 break;
2201 case MLX5_CMD_OP_2ERR_QP:
2202 rq_state = MLX5_RQC_STATE_ERR;
2203 sq_state = MLX5_SQC_STATE_ERR;
2204 break;
2205 case MLX5_CMD_OP_2RST_QP:
2206 rq_state = MLX5_RQC_STATE_RST;
2207 sq_state = MLX5_SQC_STATE_RST;
2208 break;
2209 case MLX5_CMD_OP_INIT2INIT_QP:
2210 case MLX5_CMD_OP_INIT2RTR_QP:
2211 case MLX5_CMD_OP_RTR2RTS_QP:
2212 case MLX5_CMD_OP_RTS2RTS_QP:
2213 /* Nothing to do here... */
2214 return 0;
2215 default:
2216 WARN_ON(1);
2217 return -EINVAL;
2218 }
2219
2220 if (qp->rq.wqe_cnt) {
2221 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2222 if (err)
2223 return err;
2224 }
2225
2226 if (qp->sq.wqe_cnt)
2227 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2228
2229 return 0;
2230}
2231
e126ba97
EC		 2232static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2233 const struct ib_qp_attr *attr, int attr_mask,
2234 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2235{
427c1e7b 2236 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2237 [MLX5_QP_STATE_RST] = {
2238 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2239 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2240 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2241 },
2242 [MLX5_QP_STATE_INIT] = {
2243 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2244 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2245 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2246 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2247 },
2248 [MLX5_QP_STATE_RTR] = {
2249 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2250 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2251 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2252 },
2253 [MLX5_QP_STATE_RTS] = {
2254 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2255 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2256 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2257 },
2258 [MLX5_QP_STATE_SQD] = {
2259 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2260 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2261 },
2262 [MLX5_QP_STATE_SQER] = {
2263 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2264 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2265 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2266 },
2267 [MLX5_QP_STATE_ERR] = {
2268 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2269 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2270 }
2271 };
2272
e126ba97
EC		 2273 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2274 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2275 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2276 struct mlx5_ib_cq *send_cq, *recv_cq;
2277 struct mlx5_qp_context *context;
2278 struct mlx5_modify_qp_mbox_in *in;
2279 struct mlx5_ib_pd *pd;
2280 enum mlx5_qp_state mlx5_cur, mlx5_new;
2281 enum mlx5_qp_optpar optpar;
2282 int sqd_event;
2283 int mlx5_st;
2284 int err;
427c1e7b 2285 u16 op;
e126ba97
EC		 2286
2287 in = kzalloc(sizeof(*in), GFP_KERNEL);
2288 if (!in)
2289 return -ENOMEM;
2290
2291 context = &in->ctx;
2292 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2293 if (err < 0) {
2294 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2295 goto out;
158abf86 2296 }
e126ba97
EC		 2297
2298 context->flags = cpu_to_be32(err << 16);
2299
2300 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2301 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2302 } else {
2303 switch (attr->path_mig_state) {
2304 case IB_MIG_MIGRATED:
2305 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2306 break;
2307 case IB_MIG_REARM:
2308 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2309 break;
2310 case IB_MIG_ARMED:
2311 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2312 break;
2313 }
2314 }
2315
d16e91da 2316 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2317 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2318 } else if (ibqp->qp_type == IB_QPT_UD ||
2319 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2320 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2321 } else if (attr_mask & IB_QP_PATH_MTU) {
2322 if (attr->path_mtu < IB_MTU_256 ||
2323 attr->path_mtu > IB_MTU_4096) {
2324 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2325 err = -EINVAL;
2326 goto out;
2327 }
938fe83c
SM		 2328 context->mtu_msgmax = (attr->path_mtu << 5) |
2329 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2330 }
2331
2332 if (attr_mask & IB_QP_DEST_QPN)
2333 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2334
2335 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2336 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2337
2338 /* todo implement counter_index functionality */
2339
2340 if (is_sqp(ibqp->qp_type))
2341 context->pri_path.port = qp->port;
2342
2343 if (attr_mask & IB_QP_PORT)
2344 context->pri_path.port = attr->port_num;
2345
2346 if (attr_mask & IB_QP_AV) {
75850d0b 2347 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2348 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2349 attr_mask, 0, attr, false);
e126ba97
EC		 2350 if (err)
2351 goto out;
2352 }
2353
2354 if (attr_mask & IB_QP_TIMEOUT)
2355 context->pri_path.ackto_lt |= attr->timeout << 3;
2356
2357 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2358 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2359 &context->alt_path,
f879ee8d
AS		 2360 attr->alt_port_num,
2361 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2362 0, attr, true);
e126ba97
EC		 2363 if (err)
2364 goto out;
2365 }
2366
2367 pd = get_pd(qp);
2368 get_cqs(qp, &send_cq, &recv_cq);
2369
2370 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2371 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2372 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2373 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2374
2375 if (attr_mask & IB_QP_RNR_RETRY)
2376 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2377
2378 if (attr_mask & IB_QP_RETRY_CNT)
2379 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2380
2381 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2382 if (attr->max_rd_atomic)
2383 context->params1 |=
2384 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2385 }
2386
2387 if (attr_mask & IB_QP_SQ_PSN)
2388 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2389
2390 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2391 if (attr->max_dest_rd_atomic)
2392 context->params2 |=
2393 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2394 }
2395
2396 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2397 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2398
2399 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2400 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2401
2402 if (attr_mask & IB_QP_RQ_PSN)
2403 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2404
2405 if (attr_mask & IB_QP_QKEY)
2406 context->qkey = cpu_to_be32(attr->qkey);
2407
2408 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2409 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2410
2411 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2412 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2413 sqd_event = 1;
2414 else
2415 sqd_event = 0;
2416
2417 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2418 context->sq_crq_size |= cpu_to_be16(1 << 4);
2419
b11a4f9c
HE		 2420 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2421 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2422
2423 mlx5_cur = to_mlx5_state(cur_state);
2424 mlx5_new = to_mlx5_state(new_state);
2425 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2426 if (mlx5_st < 0)
e126ba97
EC		 2427 goto out;
2428
6aec21f6
HE		 2429 /* If moving to a reset or error state, we must disable page faults on
2430 * this QP and flush all current page faults. Otherwise a stale page
2431 * fault may attempt to work on this QP after it is reset and moved
2432 * again to RTS, and may cause the driver and the device to get out of
2433 * sync. */
2434 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
ad5f8e96 2435 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2436 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2437 mlx5_ib_qp_disable_pagefaults(qp);
2438
427c1e7b 2439 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2440 !optab[mlx5_cur][mlx5_new])
2441 goto out;
2442
2443 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2444 optpar = ib_mask_to_mlx5_opt(attr_mask);
2445 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2446 in->optparam = cpu_to_be32(optpar);
ad5f8e96 2447
2448 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2449 err = modify_raw_packet_qp(dev, qp, op);
2450 else
2451 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2452 &base->mqp);
e126ba97
EC		 2453 if (err)
2454 goto out;
2455
ad5f8e96 2456 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2457 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
6aec21f6
HE		 2458 mlx5_ib_qp_enable_pagefaults(qp);
2459
e126ba97
EC		 2460 qp->state = new_state;
2461
2462 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2463 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2464 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2465 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2466 if (attr_mask & IB_QP_PORT)
2467 qp->port = attr->port_num;
2468 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2469 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2470
2471 /*
2472 * If we moved a kernel QP to RESET, clean up all old CQ
2473 * entries and reinitialize the QP.
2474 */
2475 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2476 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2477 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2478 if (send_cq != recv_cq)
19098df2 2479 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2480
2481 qp->rq.head = 0;
2482 qp->rq.tail = 0;
2483 qp->sq.head = 0;
2484 qp->sq.tail = 0;
2485 qp->sq.cur_post = 0;
2486 qp->sq.last_poll = 0;
2487 qp->db.db[MLX5_RCV_DBR] = 0;
2488 qp->db.db[MLX5_SND_DBR] = 0;
2489 }
2490
2491out:
2492 kfree(in);
2493 return err;
2494}
2495
2496int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2497 int attr_mask, struct ib_udata *udata)
2498{
2499 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2500 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2501 enum ib_qp_type qp_type;
e126ba97
EC		 2502 enum ib_qp_state cur_state, new_state;
2503 int err = -EINVAL;
2504 int port;
2811ba51 2505 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2506
d16e91da
HE		 2507 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2508 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2509
2510 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2511 IB_QPT_GSI : ibqp->qp_type;
2512
e126ba97
EC		 2513 mutex_lock(&qp->mutex);
2514
2515 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2516 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2517
2811ba51
AS		 2518 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2519 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2520 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2521 }
2522
d16e91da
HE		 2523 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2524 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2525 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2526 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2527 goto out;
158abf86 2528 }
e126ba97
EC		 2529
2530 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2531 (attr->port_num == 0 ||
158abf86
HE		 2532 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2533 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2534 attr->port_num, dev->num_ports);
e126ba97 2535 goto out;
158abf86 2536 }
e126ba97
EC		 2537
2538 if (attr_mask & IB_QP_PKEY_INDEX) {
2539 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2540 if (attr->pkey_index >=
158abf86
HE		 2541 dev->mdev->port_caps[port - 1].pkey_table_len) {
2542 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2543 attr->pkey_index);
e126ba97 2544 goto out;
158abf86 2545 }
e126ba97
EC		 2546 }
2547
2548 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2549 attr->max_rd_atomic >
158abf86
HE		 2550 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2551 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2552 attr->max_rd_atomic);
e126ba97 2553 goto out;
158abf86 2554 }
e126ba97
EC		 2555
2556 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2557 attr->max_dest_rd_atomic >
158abf86
HE		 2558 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2559 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2560 attr->max_dest_rd_atomic);
e126ba97 2561 goto out;
158abf86 2562 }
e126ba97
EC		 2563
2564 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2565 err = 0;
2566 goto out;
2567 }
2568
2569 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2570
2571out:
2572 mutex_unlock(&qp->mutex);
2573 return err;
2574}
2575
2576static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2577{
2578 struct mlx5_ib_cq *cq;
2579 unsigned cur;
2580
2581 cur = wq->head - wq->tail;
2582 if (likely(cur + nreq < wq->max_post))
2583 return 0;
2584
2585 cq = to_mcq(ib_cq);
2586 spin_lock(&cq->lock);
2587 cur = wq->head - wq->tail;
2588 spin_unlock(&cq->lock);
2589
2590 return cur + nreq >= wq->max_post;
2591}
2592
2593static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2594 u64 remote_addr, u32 rkey)
2595{
2596 rseg->raddr = cpu_to_be64(remote_addr);
2597 rseg->rkey = cpu_to_be32(rkey);
2598 rseg->reserved = 0;
2599}
2600
f0313965
ES		 2601static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2602 struct ib_send_wr *wr, void *qend,
2603 struct mlx5_ib_qp *qp, int *size)
2604{
2605 void *seg = eseg;
2606
2607 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2608
2609 if (wr->send_flags & IB_SEND_IP_CSUM)
2610 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2611 MLX5_ETH_WQE_L4_CSUM;
2612
2613 seg += sizeof(struct mlx5_wqe_eth_seg);
2614 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2615
2616 if (wr->opcode == IB_WR_LSO) {
2617 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2618 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2619 u64 left, leftlen, copysz;
2620 void *pdata = ud_wr->header;
2621
2622 left = ud_wr->hlen;
2623 eseg->mss = cpu_to_be16(ud_wr->mss);
2624 eseg->inline_hdr_sz = cpu_to_be16(left);
2625
2626 /*
2627 * check if there is space till the end of queue, if yes,
2628 * copy all in one shot, otherwise copy till the end of queue,
2629 * rollback and than the copy the left
2630 */
2631 leftlen = qend - (void *)eseg->inline_hdr_start;
2632 copysz = min_t(u64, leftlen, left);
2633
2634 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2635
2636 if (likely(copysz > size_of_inl_hdr_start)) {
2637 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2638 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2639 }
2640
2641 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2642 seg = mlx5_get_send_wqe(qp, 0);
2643 left -= copysz;
2644 pdata += copysz;
2645 memcpy(seg, pdata, left);
2646 seg += ALIGN(left, 16);
2647 *size += ALIGN(left, 16) / 16;
2648 }
2649 }
2650
2651 return seg;
2652}
2653
e126ba97
EC		 2654static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2655 struct ib_send_wr *wr)
2656{
e622f2f4
CH		 2657 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2658 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2659 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 2660}
2661
2662static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2663{
2664 dseg->byte_count = cpu_to_be32(sg->length);
2665 dseg->lkey = cpu_to_be32(sg->lkey);
2666 dseg->addr = cpu_to_be64(sg->addr);
2667}
2668
2669static __be16 get_klm_octo(int npages)
2670{
2671 return cpu_to_be16(ALIGN(npages, 8) / 2);
2672}
2673
2674static __be64 frwr_mkey_mask(void)
2675{
2676 u64 result;
2677
2678 result = MLX5_MKEY_MASK_LEN |
2679 MLX5_MKEY_MASK_PAGE_SIZE |
2680 MLX5_MKEY_MASK_START_ADDR |
2681 MLX5_MKEY_MASK_EN_RINVAL |
2682 MLX5_MKEY_MASK_KEY |
2683 MLX5_MKEY_MASK_LR |
2684 MLX5_MKEY_MASK_LW |
2685 MLX5_MKEY_MASK_RR |
2686 MLX5_MKEY_MASK_RW |
2687 MLX5_MKEY_MASK_A |
2688 MLX5_MKEY_MASK_SMALL_FENCE |
2689 MLX5_MKEY_MASK_FREE;
2690
2691 return cpu_to_be64(result);
2692}
2693
e6631814
SG		 2694static __be64 sig_mkey_mask(void)
2695{
2696 u64 result;
2697
2698 result = MLX5_MKEY_MASK_LEN |
2699 MLX5_MKEY_MASK_PAGE_SIZE |
2700 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 2701 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 2702 MLX5_MKEY_MASK_EN_RINVAL |
2703 MLX5_MKEY_MASK_KEY |
2704 MLX5_MKEY_MASK_LR |
2705 MLX5_MKEY_MASK_LW |
2706 MLX5_MKEY_MASK_RR |
2707 MLX5_MKEY_MASK_RW |
2708 MLX5_MKEY_MASK_SMALL_FENCE |
2709 MLX5_MKEY_MASK_FREE |
2710 MLX5_MKEY_MASK_BSF_EN;
2711
2712 return cpu_to_be64(result);
2713}
2714
8a187ee5
SG		 2715static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2716 struct mlx5_ib_mr *mr)
2717{
2718 int ndescs = mr->ndescs;
2719
2720 memset(umr, 0, sizeof(*umr));
b005d316
SG		 2721
2722 if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
2723 /* KLMs take twice the size of MTTs */
2724 ndescs *= 2;
2725
8a187ee5
SG		 2726 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2727 umr->klm_octowords = get_klm_octo(ndescs);
2728 umr->mkey_mask = frwr_mkey_mask();
2729}
2730
dd01e66a 2731static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 2732{
2733 memset(umr, 0, sizeof(*umr));
dd01e66a
SG		 2734 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2735 umr->flags = 1 << 7;
e126ba97
EC		 2736}
2737
968e78dd
HE		 2738static __be64 get_umr_reg_mr_mask(void)
2739{
2740 u64 result;
2741
2742 result = MLX5_MKEY_MASK_LEN |
2743 MLX5_MKEY_MASK_PAGE_SIZE |
2744 MLX5_MKEY_MASK_START_ADDR |
2745 MLX5_MKEY_MASK_PD |
2746 MLX5_MKEY_MASK_LR |
2747 MLX5_MKEY_MASK_LW |
2748 MLX5_MKEY_MASK_KEY |
2749 MLX5_MKEY_MASK_RR |
2750 MLX5_MKEY_MASK_RW |
2751 MLX5_MKEY_MASK_A |
2752 MLX5_MKEY_MASK_FREE;
2753
2754 return cpu_to_be64(result);
2755}
2756
2757static __be64 get_umr_unreg_mr_mask(void)
2758{
2759 u64 result;
2760
2761 result = MLX5_MKEY_MASK_FREE;
2762
2763 return cpu_to_be64(result);
2764}
2765
2766static __be64 get_umr_update_mtt_mask(void)
2767{
2768 u64 result;
2769
2770 result = MLX5_MKEY_MASK_FREE;
2771
2772 return cpu_to_be64(result);
2773}
2774
56e11d62
NO		 2775static __be64 get_umr_update_translation_mask(void)
2776{
2777 u64 result;
2778
2779 result = MLX5_MKEY_MASK_LEN |
2780 MLX5_MKEY_MASK_PAGE_SIZE |
2781 MLX5_MKEY_MASK_START_ADDR |
2782 MLX5_MKEY_MASK_KEY |
2783 MLX5_MKEY_MASK_FREE;
2784
2785 return cpu_to_be64(result);
2786}
2787
2788static __be64 get_umr_update_access_mask(void)
2789{
2790 u64 result;
2791
2792 result = MLX5_MKEY_MASK_LW |
2793 MLX5_MKEY_MASK_RR |
2794 MLX5_MKEY_MASK_RW |
2795 MLX5_MKEY_MASK_A |
2796 MLX5_MKEY_MASK_KEY |
2797 MLX5_MKEY_MASK_FREE;
2798
2799 return cpu_to_be64(result);
2800}
2801
2802static __be64 get_umr_update_pd_mask(void)
2803{
2804 u64 result;
2805
2806 result = MLX5_MKEY_MASK_PD |
2807 MLX5_MKEY_MASK_KEY |
2808 MLX5_MKEY_MASK_FREE;
2809
2810 return cpu_to_be64(result);
2811}
2812
e126ba97
EC		 2813static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2814 struct ib_send_wr *wr)
2815{
e622f2f4 2816 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 2817
2818 memset(umr, 0, sizeof(*umr));
2819
968e78dd
HE		 2820 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
2821 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
2822 else
2823 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
2824
e126ba97 2825 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
e126ba97 2826 umr->klm_octowords = get_klm_octo(umrwr->npages);
968e78dd
HE		 2827 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
2828 umr->mkey_mask = get_umr_update_mtt_mask();
2829 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
2830 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
968e78dd 2831 }
56e11d62
NO		 2832 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
2833 umr->mkey_mask |= get_umr_update_translation_mask();
2834 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
2835 umr->mkey_mask |= get_umr_update_access_mask();
2836 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
2837 umr->mkey_mask |= get_umr_update_pd_mask();
2838 if (!umr->mkey_mask)
2839 umr->mkey_mask = get_umr_reg_mr_mask();
e126ba97 2840 } else {
968e78dd 2841 umr->mkey_mask = get_umr_unreg_mr_mask();
e126ba97
EC		 2842 }
2843
2844 if (!wr->num_sge)
968e78dd 2845 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 2846}
2847
2848static u8 get_umr_flags(int acc)
2849{
2850 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
2851 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
2852 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
2853 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 2854 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 2855}
2856
8a187ee5
SG		 2857static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
2858 struct mlx5_ib_mr *mr,
2859 u32 key, int access)
2860{
2861 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
2862
2863 memset(seg, 0, sizeof(*seg));
b005d316
SG		 2864
2865 if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
2866 seg->log2_page_size = ilog2(mr->ibmr.page_size);
2867 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
2868 /* KLMs take twice the size of MTTs */
2869 ndescs *= 2;
2870
2871 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 2872 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
2873 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2874 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
2875 seg->len = cpu_to_be64(mr->ibmr.length);
2876 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 2877}
2878
dd01e66a 2879static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 2880{
2881 memset(seg, 0, sizeof(*seg));
dd01e66a 2882 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2883}
2884
2885static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2886{
e622f2f4 2887 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 2888
e126ba97
EC		 2889 memset(seg, 0, sizeof(*seg));
2890 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
968e78dd 2891 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 2892 return;
2893 }
2894
968e78dd
HE		 2895 seg->flags = convert_access(umrwr->access_flags);
2896 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
56e11d62
NO		 2897 if (umrwr->pd)
2898 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
968e78dd
HE		 2899 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2900 }
2901 seg->len = cpu_to_be64(umrwr->length);
2902 seg->log2_page_size = umrwr->page_shift;
746b5583 2903 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 2904 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 2905}
2906
8a187ee5
SG		 2907static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
2908 struct mlx5_ib_mr *mr,
2909 struct mlx5_ib_pd *pd)
2910{
2911 int bcount = mr->desc_size * mr->ndescs;
2912
2913 dseg->addr = cpu_to_be64(mr->desc_map);
2914 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
2915 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
2916}
2917
e126ba97
EC		 2918static __be32 send_ieth(struct ib_send_wr *wr)
2919{
2920 switch (wr->opcode) {
2921 case IB_WR_SEND_WITH_IMM:
2922 case IB_WR_RDMA_WRITE_WITH_IMM:
2923 return wr->ex.imm_data;
2924
2925 case IB_WR_SEND_WITH_INV:
2926 return cpu_to_be32(wr->ex.invalidate_rkey);
2927
2928 default:
2929 return 0;
2930 }
2931}
2932
2933static u8 calc_sig(void *wqe, int size)
2934{
2935 u8 *p = wqe;
2936 u8 res = 0;
2937 int i;
2938
2939 for (i = 0; i < size; i++)
2940 res ^= p[i];
2941
2942 return ~res;
2943}
2944
2945static u8 wq_sig(void *wqe)
2946{
2947 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2948}
2949
2950static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2951 void *wqe, int *sz)
2952{
2953 struct mlx5_wqe_inline_seg *seg;
2954 void *qend = qp->sq.qend;
2955 void *addr;
2956 int inl = 0;
2957 int copy;
2958 int len;
2959 int i;
2960
2961 seg = wqe;
2962 wqe += sizeof(*seg);
2963 for (i = 0; i < wr->num_sge; i++) {
2964 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2965 len = wr->sg_list[i].length;
2966 inl += len;
2967
2968 if (unlikely(inl > qp->max_inline_data))
2969 return -ENOMEM;
2970
2971 if (unlikely(wqe + len > qend)) {
2972 copy = qend - wqe;
2973 memcpy(wqe, addr, copy);
2974 addr += copy;
2975 len -= copy;
2976 wqe = mlx5_get_send_wqe(qp, 0);
2977 }
2978 memcpy(wqe, addr, len);
2979 wqe += len;
2980 }
2981
2982 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2983
2984 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2985
2986 return 0;
2987}
2988
e6631814
SG		 2989static u16 prot_field_size(enum ib_signature_type type)
2990{
2991 switch (type) {
2992 case IB_SIG_TYPE_T10_DIF:
2993 return MLX5_DIF_SIZE;
2994 default:
2995 return 0;
2996 }
2997}
2998
2999static u8 bs_selector(int block_size)
3000{
3001 switch (block_size) {
3002 case 512: return 0x1;
3003 case 520: return 0x2;
3004 case 4096: return 0x3;
3005 case 4160: return 0x4;
3006 case 1073741824: return 0x5;
3007 default: return 0;
3008 }
3009}
3010
78eda2bb
SG		 3011static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3012 struct mlx5_bsf_inl *inl)
e6631814 3013{
142537f4
SG		 3014 /* Valid inline section and allow BSF refresh */
3015 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3016 MLX5_BSF_REFRESH_DIF);
3017 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3018 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3019 /* repeating block */
3020 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3021 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3022 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3023
78eda2bb
SG		 3024 if (domain->sig.dif.ref_remap)
3025 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3026
78eda2bb
SG		 3027 if (domain->sig.dif.app_escape) {
3028 if (domain->sig.dif.ref_escape)
3029 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3030 else
3031 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3032 }
3033
78eda2bb
SG		 3034 inl->dif_app_bitmask_check =
3035 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3036}
3037
3038static int mlx5_set_bsf(struct ib_mr *sig_mr,
3039 struct ib_sig_attrs *sig_attrs,
3040 struct mlx5_bsf *bsf, u32 data_size)
3041{
3042 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3043 struct mlx5_bsf_basic *basic = &bsf->basic;
3044 struct ib_sig_domain *mem = &sig_attrs->mem;
3045 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3046
c7f44fbd 3047 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3048
3049 /* Basic + Extended + Inline */
3050 basic->bsf_size_sbs = 1 << 7;
3051 /* Input domain check byte mask */
3052 basic->check_byte_mask = sig_attrs->check_mask;
3053 basic->raw_data_size = cpu_to_be32(data_size);
3054
3055 /* Memory domain */
e6631814 3056 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3057 case IB_SIG_TYPE_NONE:
3058 break;
e6631814 3059 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3060 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3061 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3062 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3063 break;
3064 default:
3065 return -EINVAL;
3066 }
e6631814 3067
78eda2bb
SG		 3068 /* Wire domain */
3069 switch (sig_attrs->wire.sig_type) {
3070 case IB_SIG_TYPE_NONE:
3071 break;
3072 case IB_SIG_TYPE_T10_DIF:
e6631814 3073 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3074 mem->sig_type == wire->sig_type) {
e6631814 3075 /* Same block structure */
142537f4 3076 basic->bsf_size_sbs |= 1 << 4;
e6631814 3077 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3078 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3079 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3080 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3081 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3082 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3083 } else
3084 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3085
142537f4 3086 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3087 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3088 break;
e6631814
SG		 3089 default:
3090 return -EINVAL;
3091 }
3092
3093 return 0;
3094}
3095
e622f2f4
CH		 3096static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3097 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3098{
e622f2f4
CH		 3099 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3100 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3101 struct mlx5_bsf *bsf;
e622f2f4
CH		 3102 u32 data_len = wr->wr.sg_list->length;
3103 u32 data_key = wr->wr.sg_list->lkey;
3104 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3105 int ret;
3106 int wqe_size;
3107
e622f2f4
CH		 3108 if (!wr->prot ||
3109 (data_key == wr->prot->lkey &&
3110 data_va == wr->prot->addr &&
3111 data_len == wr->prot->length)) {
e6631814
SG		 3112 /**
3113 * Source domain doesn't contain signature information
5c273b16 3114 * or data and protection are interleaved in memory.
e6631814
SG		 3115 * So need construct:
3116 * ------------------
3117 * | data_klm |
3118 * ------------------
3119 * | BSF |
3120 * ------------------
3121 **/
3122 struct mlx5_klm *data_klm = *seg;
3123
3124 data_klm->bcount = cpu_to_be32(data_len);
3125 data_klm->key = cpu_to_be32(data_key);
3126 data_klm->va = cpu_to_be64(data_va);
3127 wqe_size = ALIGN(sizeof(*data_klm), 64);
3128 } else {
3129 /**
3130 * Source domain contains signature information
3131 * So need construct a strided block format:
3132 * ---------------------------
3133 * | stride_block_ctrl |
3134 * ---------------------------
3135 * | data_klm |
3136 * ---------------------------
3137 * | prot_klm |
3138 * ---------------------------
3139 * | BSF |
3140 * ---------------------------
3141 **/
3142 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3143 struct mlx5_stride_block_entry *data_sentry;
3144 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3145 u32 prot_key = wr->prot->lkey;
3146 u64 prot_va = wr->prot->addr;
e6631814
SG		 3147 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3148 int prot_size;
3149
3150 sblock_ctrl = *seg;
3151 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3152 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3153
3154 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3155 if (!prot_size) {
3156 pr_err("Bad block size given: %u\n", block_size);
3157 return -EINVAL;
3158 }
3159 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3160 prot_size);
3161 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3162 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3163 sblock_ctrl->num_entries = cpu_to_be16(2);
3164
3165 data_sentry->bcount = cpu_to_be16(block_size);
3166 data_sentry->key = cpu_to_be32(data_key);
3167 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3168 data_sentry->stride = cpu_to_be16(block_size);
3169
e6631814
SG		 3170 prot_sentry->bcount = cpu_to_be16(prot_size);
3171 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3172 prot_sentry->va = cpu_to_be64(prot_va);
3173 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3174
e6631814
SG		 3175 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3176 sizeof(*prot_sentry), 64);
3177 }
3178
3179 *seg += wqe_size;
3180 *size += wqe_size / 16;
3181 if (unlikely((*seg == qp->sq.qend)))
3182 *seg = mlx5_get_send_wqe(qp, 0);
3183
3184 bsf = *seg;
3185 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3186 if (ret)
3187 return -EINVAL;
3188
3189 *seg += sizeof(*bsf);
3190 *size += sizeof(*bsf) / 16;
3191 if (unlikely((*seg == qp->sq.qend)))
3192 *seg = mlx5_get_send_wqe(qp, 0);
3193
3194 return 0;
3195}
3196
3197static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
e622f2f4 3198 struct ib_sig_handover_wr *wr, u32 nelements,
e6631814
SG		 3199 u32 length, u32 pdn)
3200{
e622f2f4 3201 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3202 u32 sig_key = sig_mr->rkey;
d5436ba0 3203 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3204
3205 memset(seg, 0, sizeof(*seg));
3206
e622f2f4 3207 seg->flags = get_umr_flags(wr->access_flags) |
e6631814
SG		 3208 MLX5_ACCESS_MODE_KLM;
3209 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3210 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3211 MLX5_MKEY_BSF_EN | pdn);
3212 seg->len = cpu_to_be64(length);
3213 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3214 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3215}
3216
3217static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
e622f2f4 3218 u32 nelements)
e6631814
SG		 3219{
3220 memset(umr, 0, sizeof(*umr));
3221
3222 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3223 umr->klm_octowords = get_klm_octo(nelements);
3224 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3225 umr->mkey_mask = sig_mkey_mask();
3226}
3227
3228
e622f2f4 3229static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3230 void **seg, int *size)
3231{
e622f2f4
CH		 3232 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3233 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814
SG		 3234 u32 pdn = get_pd(qp)->pdn;
3235 u32 klm_oct_size;
3236 int region_len, ret;
3237
e622f2f4
CH		 3238 if (unlikely(wr->wr.num_sge != 1) ||
3239 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3240 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3241 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3242 return -EINVAL;
3243
3244 /* length of the protected region, data + protection */
e622f2f4
CH		 3245 region_len = wr->wr.sg_list->length;
3246 if (wr->prot &&
3247 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3248 wr->prot->addr != wr->wr.sg_list->addr ||
3249 wr->prot->length != wr->wr.sg_list->length))
3250 region_len += wr->prot->length;
e6631814
SG		 3251
3252 /**
3253 * KLM octoword size - if protection was provided
3254 * then we use strided block format (3 octowords),
3255 * else we use single KLM (1 octoword)
3256 **/
e622f2f4 3257 klm_oct_size = wr->prot ? 3 : 1;
e6631814 3258
e622f2f4 3259 set_sig_umr_segment(*seg, klm_oct_size);
e6631814
SG		 3260 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3261 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3262 if (unlikely((*seg == qp->sq.qend)))
3263 *seg = mlx5_get_send_wqe(qp, 0);
3264
3265 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3266 *seg += sizeof(struct mlx5_mkey_seg);
3267 *size += sizeof(struct mlx5_mkey_seg) / 16;
3268 if (unlikely((*seg == qp->sq.qend)))
3269 *seg = mlx5_get_send_wqe(qp, 0);
3270
3271 ret = set_sig_data_segment(wr, qp, seg, size);
3272 if (ret)
3273 return ret;
3274
d5436ba0 3275 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3276 return 0;
3277}
3278
3279static int set_psv_wr(struct ib_sig_domain *domain,
3280 u32 psv_idx, void **seg, int *size)
3281{
3282 struct mlx5_seg_set_psv *psv_seg = *seg;
3283
3284 memset(psv_seg, 0, sizeof(*psv_seg));
3285 psv_seg->psv_num = cpu_to_be32(psv_idx);
3286 switch (domain->sig_type) {
78eda2bb
SG		 3287 case IB_SIG_TYPE_NONE:
3288 break;
e6631814
SG		 3289 case IB_SIG_TYPE_T10_DIF:
3290 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3291 domain->sig.dif.app_tag);
3292 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3293 break;
e6631814
SG		 3294 default:
3295 pr_err("Bad signature type given.\n");
3296 return 1;
3297 }
3298
78eda2bb
SG		 3299 *seg += sizeof(*psv_seg);
3300 *size += sizeof(*psv_seg) / 16;
3301
e6631814
SG		 3302 return 0;
3303}
3304
8a187ee5
SG		 3305static int set_reg_wr(struct mlx5_ib_qp *qp,
3306 struct ib_reg_wr *wr,
3307 void **seg, int *size)
3308{
3309 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3310 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3311
3312 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3313 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3314 "Invalid IB_SEND_INLINE send flag\n");
3315 return -EINVAL;
3316 }
3317
3318 set_reg_umr_seg(*seg, mr);
3319 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3320 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3321 if (unlikely((*seg == qp->sq.qend)))
3322 *seg = mlx5_get_send_wqe(qp, 0);
3323
3324 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3325 *seg += sizeof(struct mlx5_mkey_seg);
3326 *size += sizeof(struct mlx5_mkey_seg) / 16;
3327 if (unlikely((*seg == qp->sq.qend)))
3328 *seg = mlx5_get_send_wqe(qp, 0);
3329
3330 set_reg_data_seg(*seg, mr, pd);
3331 *seg += sizeof(struct mlx5_wqe_data_seg);
3332 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3333
3334 return 0;
3335}
3336
dd01e66a 3337static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3338{
dd01e66a 3339 set_linv_umr_seg(*seg);
e126ba97
EC		 3340 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3341 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3342 if (unlikely((*seg == qp->sq.qend)))
3343 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3344 set_linv_mkey_seg(*seg);
e126ba97
EC		 3345 *seg += sizeof(struct mlx5_mkey_seg);
3346 *size += sizeof(struct mlx5_mkey_seg) / 16;
3347 if (unlikely((*seg == qp->sq.qend)))
3348 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3349}
3350
3351static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3352{
3353 __be32 *p = NULL;
3354 int tidx = idx;
3355 int i, j;
3356
3357 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3358 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3359 if ((i & 0xf) == 0) {
3360 void *buf = mlx5_get_send_wqe(qp, tidx);
3361 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3362 p = buf;
3363 j = 0;
3364 }
3365 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3366 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3367 be32_to_cpu(p[j + 3]));
3368 }
3369}
3370
3371static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3372 unsigned bytecnt, struct mlx5_ib_qp *qp)
3373{
3374 while (bytecnt > 0) {
3375 __iowrite64_copy(dst++, src++, 8);
3376 __iowrite64_copy(dst++, src++, 8);
3377 __iowrite64_copy(dst++, src++, 8);
3378 __iowrite64_copy(dst++, src++, 8);
3379 __iowrite64_copy(dst++, src++, 8);
3380 __iowrite64_copy(dst++, src++, 8);
3381 __iowrite64_copy(dst++, src++, 8);
3382 __iowrite64_copy(dst++, src++, 8);
3383 bytecnt -= 64;
3384 if (unlikely(src == qp->sq.qend))
3385 src = mlx5_get_send_wqe(qp, 0);
3386 }
3387}
3388
3389static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3390{
3391 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3392 wr->send_flags & IB_SEND_FENCE))
3393 return MLX5_FENCE_MODE_STRONG_ORDERING;
3394
3395 if (unlikely(fence)) {
3396 if (wr->send_flags & IB_SEND_FENCE)
3397 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3398 else
3399 return fence;
3400
3401 } else {
3402 return 0;
3403 }
3404}
3405
6e5eadac
SG		 3406static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3407 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3408 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3409 int *size, int nreq)
3410{
3411 int err = 0;
3412
3413 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3414 err = -ENOMEM;
3415 return err;
3416 }
3417
3418 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3419 *seg = mlx5_get_send_wqe(qp, *idx);
3420 *ctrl = *seg;
3421 *(uint32_t *)(*seg + 8) = 0;
3422 (*ctrl)->imm = send_ieth(wr);
3423 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3424 (wr->send_flags & IB_SEND_SIGNALED ?
3425 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3426 (wr->send_flags & IB_SEND_SOLICITED ?
3427 MLX5_WQE_CTRL_SOLICITED : 0);
3428
3429 *seg += sizeof(**ctrl);
3430 *size = sizeof(**ctrl) / 16;
3431
3432 return err;
3433}
3434
3435static void finish_wqe(struct mlx5_ib_qp *qp,
3436 struct mlx5_wqe_ctrl_seg *ctrl,
3437 u8 size, unsigned idx, u64 wr_id,
3438 int nreq, u8 fence, u8 next_fence,
3439 u32 mlx5_opcode)
3440{
3441 u8 opmod = 0;
3442
3443 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3444 mlx5_opcode | ((u32)opmod << 24));
19098df2 3445 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3446 ctrl->fm_ce_se |= fence;
3447 qp->fm_cache = next_fence;
3448 if (unlikely(qp->wq_sig))
3449 ctrl->signature = wq_sig(ctrl);
3450
3451 qp->sq.wrid[idx] = wr_id;
3452 qp->sq.w_list[idx].opcode = mlx5_opcode;
3453 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3454 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3455 qp->sq.w_list[idx].next = qp->sq.cur_post;
3456}
3457
3458
e126ba97
EC		 3459int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3460 struct ib_send_wr **bad_wr)
3461{
3462 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3463 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
d16e91da 3464 struct mlx5_ib_qp *qp;
e6631814 3465 struct mlx5_ib_mr *mr;
e126ba97
EC		 3466 struct mlx5_wqe_data_seg *dpseg;
3467 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3468 struct mlx5_bf *bf;
e126ba97 3469 int uninitialized_var(size);
d16e91da 3470 void *qend;
e126ba97 3471 unsigned long flags;
e126ba97
EC		 3472 unsigned idx;
3473 int err = 0;
3474 int inl = 0;
3475 int num_sge;
3476 void *seg;
3477 int nreq;
3478 int i;
3479 u8 next_fence = 0;
e126ba97
EC		 3480 u8 fence;
3481
d16e91da
HE		 3482 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3483 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3484
3485 qp = to_mqp(ibqp);
3486 bf = qp->bf;
3487 qend = qp->sq.qend;
3488
e126ba97
EC		 3489 spin_lock_irqsave(&qp->sq.lock, flags);
3490
3491 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3492 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3493 mlx5_ib_warn(dev, "\n");
3494 err = -EINVAL;
3495 *bad_wr = wr;
3496 goto out;
3497 }
3498
6e5eadac
SG		 3499 fence = qp->fm_cache;
3500 num_sge = wr->num_sge;
3501 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97
EC		 3502 mlx5_ib_warn(dev, "\n");
3503 err = -ENOMEM;
3504 *bad_wr = wr;
3505 goto out;
3506 }
3507
6e5eadac
SG		 3508 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3509 if (err) {
e126ba97
EC		 3510 mlx5_ib_warn(dev, "\n");
3511 err = -ENOMEM;
3512 *bad_wr = wr;
3513 goto out;
3514 }
3515
e126ba97
EC		 3516 switch (ibqp->qp_type) {
3517 case IB_QPT_XRC_INI:
3518 xrc = seg;
e126ba97
EC		 3519 seg += sizeof(*xrc);
3520 size += sizeof(*xrc) / 16;
3521 /* fall through */
3522 case IB_QPT_RC:
3523 switch (wr->opcode) {
3524 case IB_WR_RDMA_READ:
3525 case IB_WR_RDMA_WRITE:
3526 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3527 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3528 rdma_wr(wr)->rkey);
f241e749 3529 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3530 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3531 break;
3532
3533 case IB_WR_ATOMIC_CMP_AND_SWP:
3534 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3535 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3536 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3537 err = -ENOSYS;
3538 *bad_wr = wr;
3539 goto out;
e126ba97
EC		 3540
3541 case IB_WR_LOCAL_INV:
3542 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3543 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3544 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3545 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3546 num_sge = 0;
3547 break;
3548
8a187ee5
SG		 3549 case IB_WR_REG_MR:
3550 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3551 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3552 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3553 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3554 if (err) {
3555 *bad_wr = wr;
3556 goto out;
3557 }
3558 num_sge = 0;
3559 break;
3560
e6631814
SG		 3561 case IB_WR_REG_SIG_MR:
3562 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3563 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3564
3565 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3566 err = set_sig_umr_wr(wr, qp, &seg, &size);
3567 if (err) {
3568 mlx5_ib_warn(dev, "\n");
3569 *bad_wr = wr;
3570 goto out;
3571 }
3572
3573 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3574 nreq, get_fence(fence, wr),
3575 next_fence, MLX5_OPCODE_UMR);
3576 /*
3577 * SET_PSV WQEs are not signaled and solicited
3578 * on error
3579 */
3580 wr->send_flags &= ~IB_SEND_SIGNALED;
3581 wr->send_flags |= IB_SEND_SOLICITED;
3582 err = begin_wqe(qp, &seg, &ctrl, wr,
3583 &idx, &size, nreq);
3584 if (err) {
3585 mlx5_ib_warn(dev, "\n");
3586 err = -ENOMEM;
3587 *bad_wr = wr;
3588 goto out;
3589 }
3590
e622f2f4 3591 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3592 mr->sig->psv_memory.psv_idx, &seg,
3593 &size);
3594 if (err) {
3595 mlx5_ib_warn(dev, "\n");
3596 *bad_wr = wr;
3597 goto out;
3598 }
3599
3600 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3601 nreq, get_fence(fence, wr),
3602 next_fence, MLX5_OPCODE_SET_PSV);
3603 err = begin_wqe(qp, &seg, &ctrl, wr,
3604 &idx, &size, nreq);
3605 if (err) {
3606 mlx5_ib_warn(dev, "\n");
3607 err = -ENOMEM;
3608 *bad_wr = wr;
3609 goto out;
3610 }
3611
3612 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3613 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3614 mr->sig->psv_wire.psv_idx, &seg,
3615 &size);
3616 if (err) {
3617 mlx5_ib_warn(dev, "\n");
3618 *bad_wr = wr;
3619 goto out;
3620 }
3621
3622 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3623 nreq, get_fence(fence, wr),
3624 next_fence, MLX5_OPCODE_SET_PSV);
3625 num_sge = 0;
3626 goto skip_psv;
3627
e126ba97
EC		 3628 default:
3629 break;
3630 }
3631 break;
3632
3633 case IB_QPT_UC:
3634 switch (wr->opcode) {
3635 case IB_WR_RDMA_WRITE:
3636 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3637 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3638 rdma_wr(wr)->rkey);
e126ba97
EC		 3639 seg += sizeof(struct mlx5_wqe_raddr_seg);
3640 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3641 break;
3642
3643 default:
3644 break;
3645 }
3646 break;
3647
e126ba97 3648 case IB_QPT_SMI:
d16e91da 3649 case MLX5_IB_QPT_HW_GSI:
e126ba97 3650 set_datagram_seg(seg, wr);
f241e749 3651 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 3652 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3653 if (unlikely((seg == qend)))
3654 seg = mlx5_get_send_wqe(qp, 0);
3655 break;
f0313965
ES		 3656 case IB_QPT_UD:
3657 set_datagram_seg(seg, wr);
3658 seg += sizeof(struct mlx5_wqe_datagram_seg);
3659 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3660
3661 if (unlikely((seg == qend)))
3662 seg = mlx5_get_send_wqe(qp, 0);
3663
3664 /* handle qp that supports ud offload */
3665 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3666 struct mlx5_wqe_eth_pad *pad;
e126ba97 3667
f0313965
ES		 3668 pad = seg;
3669 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3670 seg += sizeof(struct mlx5_wqe_eth_pad);
3671 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3672
3673 seg = set_eth_seg(seg, wr, qend, qp, &size);
3674
3675 if (unlikely((seg == qend)))
3676 seg = mlx5_get_send_wqe(qp, 0);
3677 }
3678 break;
e126ba97
EC		 3679 case MLX5_IB_QPT_REG_UMR:
3680 if (wr->opcode != MLX5_IB_WR_UMR) {
3681 err = -EINVAL;
3682 mlx5_ib_warn(dev, "bad opcode\n");
3683 goto out;
3684 }
3685 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 3686 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
e126ba97
EC		 3687 set_reg_umr_segment(seg, wr);
3688 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3689 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3690 if (unlikely((seg == qend)))
3691 seg = mlx5_get_send_wqe(qp, 0);
3692 set_reg_mkey_segment(seg, wr);
3693 seg += sizeof(struct mlx5_mkey_seg);
3694 size += sizeof(struct mlx5_mkey_seg) / 16;
3695 if (unlikely((seg == qend)))
3696 seg = mlx5_get_send_wqe(qp, 0);
3697 break;
3698
3699 default:
3700 break;
3701 }
3702
3703 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3704 int uninitialized_var(sz);
3705
3706 err = set_data_inl_seg(qp, wr, seg, &sz);
3707 if (unlikely(err)) {
3708 mlx5_ib_warn(dev, "\n");
3709 *bad_wr = wr;
3710 goto out;
3711 }
3712 inl = 1;
3713 size += sz;
3714 } else {
3715 dpseg = seg;
3716 for (i = 0; i < num_sge; i++) {
3717 if (unlikely(dpseg == qend)) {
3718 seg = mlx5_get_send_wqe(qp, 0);
3719 dpseg = seg;
3720 }
3721 if (likely(wr->sg_list[i].length)) {
3722 set_data_ptr_seg(dpseg, wr->sg_list + i);
3723 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3724 dpseg++;
3725 }
3726 }
3727 }
3728
6e5eadac
SG		 3729 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3730 get_fence(fence, wr), next_fence,
3731 mlx5_ib_opcode[wr->opcode]);
e6631814 3732skip_psv:
e126ba97
EC		 3733 if (0)
3734 dump_wqe(qp, idx, size);
3735 }
3736
3737out:
3738 if (likely(nreq)) {
3739 qp->sq.head += nreq;
3740
3741 /* Make sure that descriptors are written before
3742 * updating doorbell record and ringing the doorbell
3743 */
3744 wmb();
3745
3746 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
3747
ada388f7
EC		 3748 /* Make sure doorbell record is visible to the HCA before
3749 * we hit doorbell */
3750 wmb();
3751
e126ba97
EC		 3752 if (bf->need_lock)
3753 spin_lock(&bf->lock);
6a4f139a
EC		 3754 else
3755 __acquire(&bf->lock);
e126ba97
EC		 3756
3757 /* TBD enable WC */
3758 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
3759 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
3760 /* wc_wmb(); */
3761 } else {
3762 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
3763 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
3764 /* Make sure doorbells don't leak out of SQ spinlock
3765 * and reach the HCA out of order.
3766 */
3767 mmiowb();
3768 }
3769 bf->offset ^= bf->buf_size;
3770 if (bf->need_lock)
3771 spin_unlock(&bf->lock);
6a4f139a
EC		 3772 else
3773 __release(&bf->lock);
e126ba97
EC		 3774 }
3775
3776 spin_unlock_irqrestore(&qp->sq.lock, flags);
3777
3778 return err;
3779}
3780
3781static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
3782{
3783 sig->signature = calc_sig(sig, size);
3784}
3785
3786int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3787 struct ib_recv_wr **bad_wr)
3788{
3789 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3790 struct mlx5_wqe_data_seg *scat;
3791 struct mlx5_rwqe_sig *sig;
3792 unsigned long flags;
3793 int err = 0;
3794 int nreq;
3795 int ind;
3796 int i;
3797
d16e91da
HE		 3798 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3799 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
3800
e126ba97
EC		 3801 spin_lock_irqsave(&qp->rq.lock, flags);
3802
3803 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3804
3805 for (nreq = 0; wr; nreq++, wr = wr->next) {
3806 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3807 err = -ENOMEM;
3808 *bad_wr = wr;
3809 goto out;
3810 }
3811
3812 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3813 err = -EINVAL;
3814 *bad_wr = wr;
3815 goto out;
3816 }
3817
3818 scat = get_recv_wqe(qp, ind);
3819 if (qp->wq_sig)
3820 scat++;
3821
3822 for (i = 0; i < wr->num_sge; i++)
3823 set_data_ptr_seg(scat + i, wr->sg_list + i);
3824
3825 if (i < qp->rq.max_gs) {
3826 scat[i].byte_count = 0;
3827 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
3828 scat[i].addr = 0;
3829 }
3830
3831 if (qp->wq_sig) {
3832 sig = (struct mlx5_rwqe_sig *)scat;
3833 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
3834 }
3835
3836 qp->rq.wrid[ind] = wr->wr_id;
3837
3838 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3839 }
3840
3841out:
3842 if (likely(nreq)) {
3843 qp->rq.head += nreq;
3844
3845 /* Make sure that descriptors are written before
3846 * doorbell record.
3847 */
3848 wmb();
3849
3850 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3851 }
3852
3853 spin_unlock_irqrestore(&qp->rq.lock, flags);
3854
3855 return err;
3856}
3857
3858static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
3859{
3860 switch (mlx5_state) {
3861 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
3862 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
3863 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
3864 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
3865 case MLX5_QP_STATE_SQ_DRAINING:
3866 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
3867 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
3868 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
3869 default: return -1;
3870 }
3871}
3872
3873static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
3874{
3875 switch (mlx5_mig_state) {
3876 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
3877 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
3878 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3879 default: return -1;
3880 }
3881}
3882
3883static int to_ib_qp_access_flags(int mlx5_flags)
3884{
3885 int ib_flags = 0;
3886
3887 if (mlx5_flags & MLX5_QP_BIT_RRE)
3888 ib_flags |= IB_ACCESS_REMOTE_READ;
3889 if (mlx5_flags & MLX5_QP_BIT_RWE)
3890 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3891 if (mlx5_flags & MLX5_QP_BIT_RAE)
3892 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3893
3894 return ib_flags;
3895}
3896
3897static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3898 struct mlx5_qp_path *path)
3899{
9603b61d 3900 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 3901
3902 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3903 ib_ah_attr->port_num = path->port;
3904
c7a08ac7 3905 if (ib_ah_attr->port_num == 0 ||
938fe83c 3906 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 3907 return;
3908
2811ba51 3909 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 3910
3911 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3912 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3913 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3914 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3915 if (ib_ah_attr->ah_flags) {
3916 ib_ah_attr->grh.sgid_index = path->mgid_index;
3917 ib_ah_attr->grh.hop_limit = path->hop_limit;
3918 ib_ah_attr->grh.traffic_class =
3919 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3920 ib_ah_attr->grh.flow_label =
3921 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3922 memcpy(ib_ah_attr->grh.dgid.raw,
3923 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3924 }
3925}
3926
6d2f89df 3927static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
3928 struct mlx5_ib_sq *sq,
3929 u8 *sq_state)
3930{
3931 void *out;
3932 void *sqc;
3933 int inlen;
3934 int err;
3935
3936 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
3937 out = mlx5_vzalloc(inlen);
3938 if (!out)
3939 return -ENOMEM;
3940
3941 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
3942 if (err)
3943 goto out;
3944
3945 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
3946 *sq_state = MLX5_GET(sqc, sqc, state);
3947 sq->state = *sq_state;
3948
3949out:
3950 kvfree(out);
3951 return err;
3952}
3953
3954static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
3955 struct mlx5_ib_rq *rq,
3956 u8 *rq_state)
3957{
3958 void *out;
3959 void *rqc;
3960 int inlen;
3961 int err;
3962
3963 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
3964 out = mlx5_vzalloc(inlen);
3965 if (!out)
3966 return -ENOMEM;
3967
3968 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
3969 if (err)
3970 goto out;
3971
3972 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3973 *rq_state = MLX5_GET(rqc, rqc, state);
3974 rq->state = *rq_state;
3975
3976out:
3977 kvfree(out);
3978 return err;
3979}
3980
3981static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
3982 struct mlx5_ib_qp *qp, u8 *qp_state)
3983{
3984 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
3985 [MLX5_RQC_STATE_RST] = {
3986 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3987 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3988 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
3989 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
3990 },
3991 [MLX5_RQC_STATE_RDY] = {
3992 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3993 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3994 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
3995 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
3996 },
3997 [MLX5_RQC_STATE_ERR] = {
3998 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3999 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4000 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4001 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4002 },
4003 [MLX5_RQ_STATE_NA] = {
4004 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4005 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4006 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4007 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4008 },
4009 };
4010
4011 *qp_state = sqrq_trans[rq_state][sq_state];
4012
4013 if (*qp_state == MLX5_QP_STATE_BAD) {
4014 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4015 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4016 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4017 return -EINVAL;
4018 }
4019
4020 if (*qp_state == MLX5_QP_STATE)
4021 *qp_state = qp->state;
4022
4023 return 0;
4024}
4025
4026static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4027 struct mlx5_ib_qp *qp,
4028 u8 *raw_packet_qp_state)
4029{
4030 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4031 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4032 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4033 int err;
4034 u8 sq_state = MLX5_SQ_STATE_NA;
4035 u8 rq_state = MLX5_RQ_STATE_NA;
4036
4037 if (qp->sq.wqe_cnt) {
4038 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4039 if (err)
4040 return err;
4041 }
4042
4043 if (qp->rq.wqe_cnt) {
4044 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4045 if (err)
4046 return err;
4047 }
4048
4049 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4050 raw_packet_qp_state);
4051}
4052
4053static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4054 struct ib_qp_attr *qp_attr)
e126ba97 4055{
e126ba97
EC		 4056 struct mlx5_query_qp_mbox_out *outb;
4057 struct mlx5_qp_context *context;
4058 int mlx5_state;
4059 int err = 0;
4060
e126ba97 4061 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
6d2f89df 4062 if (!outb)
4063 return -ENOMEM;
4064
e126ba97 4065 context = &outb->ctx;
19098df2 4066 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4067 sizeof(*outb));
e126ba97 4068 if (err)
6d2f89df 4069 goto out;
e126ba97
EC		 4070
4071 mlx5_state = be32_to_cpu(context->flags) >> 28;
4072
4073 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4074 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4075 qp_attr->path_mig_state =
4076 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4077 qp_attr->qkey = be32_to_cpu(context->qkey);
4078 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4079 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4080 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4081 qp_attr->qp_access_flags =
4082 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4083
4084 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4085 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4086 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4087 qp_attr->alt_pkey_index =
4088 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4089 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4090 }
4091
d3ae2bde 4092 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4093 qp_attr->port_num = context->pri_path.port;
4094
4095 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4096 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4097
4098 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4099
4100 qp_attr->max_dest_rd_atomic =
4101 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4102 qp_attr->min_rnr_timer =
4103 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4104 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4105 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4106 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4107 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4108
4109out:
4110 kfree(outb);
4111 return err;
4112}
4113
4114int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4115 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4116{
4117 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4118 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4119 int err = 0;
4120 u8 raw_packet_qp_state;
4121
d16e91da
HE		 4122 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4123 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4124 qp_init_attr);
4125
6d2f89df 4126#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4127 /*
4128 * Wait for any outstanding page faults, in case the user frees memory
4129 * based upon this query's result.
4130 */
4131 flush_workqueue(mlx5_ib_page_fault_wq);
4132#endif
4133
4134 mutex_lock(&qp->mutex);
4135
4136 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4137 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4138 if (err)
4139 goto out;
4140 qp->state = raw_packet_qp_state;
4141 qp_attr->port_num = 1;
4142 } else {
4143 err = query_qp_attr(dev, qp, qp_attr);
4144 if (err)
4145 goto out;
4146 }
4147
4148 qp_attr->qp_state = qp->state;
e126ba97
EC		 4149 qp_attr->cur_qp_state = qp_attr->qp_state;
4150 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4151 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4152
4153 if (!ibqp->uobject) {
0540d814 4154 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4155 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4156 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4157 } else {
4158 qp_attr->cap.max_send_wr = 0;
4159 qp_attr->cap.max_send_sge = 0;
4160 }
4161
0540d814
NO		 4162 qp_init_attr->qp_type = ibqp->qp_type;
4163 qp_init_attr->recv_cq = ibqp->recv_cq;
4164 qp_init_attr->send_cq = ibqp->send_cq;
4165 qp_init_attr->srq = ibqp->srq;
4166 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4167
4168 qp_init_attr->cap = qp_attr->cap;
4169
4170 qp_init_attr->create_flags = 0;
4171 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4172 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4173
051f2630
LR		 4174 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4175 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4176 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4177 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4178 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4179 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4180 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4181 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4182
e126ba97
EC		 4183 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4184 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4185
e126ba97
EC		 4186out:
4187 mutex_unlock(&qp->mutex);
4188 return err;
4189}
4190
4191struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4192 struct ib_ucontext *context,
4193 struct ib_udata *udata)
4194{
4195 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4196 struct mlx5_ib_xrcd *xrcd;
4197 int err;
4198
938fe83c 4199 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4200 return ERR_PTR(-ENOSYS);
4201
4202 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4203 if (!xrcd)
4204 return ERR_PTR(-ENOMEM);
4205
9603b61d 4206 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4207 if (err) {
4208 kfree(xrcd);
4209 return ERR_PTR(-ENOMEM);
4210 }
4211
4212 return &xrcd->ibxrcd;
4213}
4214
4215int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4216{
4217 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4218 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4219 int err;
4220
9603b61d 4221 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4222 if (err) {
4223 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4224 return err;
4225 }
4226
4227 kfree(xrcd);
4228
4229 return 0;
4230}
79b20a6c
YH		 4231
4232static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4233 struct ib_wq_init_attr *init_attr)
4234{
4235 struct mlx5_ib_dev *dev;
4236 __be64 *rq_pas0;
4237 void *in;
4238 void *rqc;
4239 void *wq;
4240 int inlen;
4241 int err;
4242
4243 dev = to_mdev(pd->device);
4244
4245 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4246 in = mlx5_vzalloc(inlen);
4247 if (!in)
4248 return -ENOMEM;
4249
4250 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4251 MLX5_SET(rqc, rqc, mem_rq_type,
4252 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4253 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4254 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4255 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4256 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4257 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4258 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4259 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4260 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4261 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4262 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4263 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4264 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4265 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4266 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4267 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4268 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4269 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4270 kvfree(in);
4271 return err;
4272}
4273
4274static int set_user_rq_size(struct mlx5_ib_dev *dev,
4275 struct ib_wq_init_attr *wq_init_attr,
4276 struct mlx5_ib_create_wq *ucmd,
4277 struct mlx5_ib_rwq *rwq)
4278{
4279 /* Sanity check RQ size before proceeding */
4280 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4281 return -EINVAL;
4282
4283 if (!ucmd->rq_wqe_count)
4284 return -EINVAL;
4285
4286 rwq->wqe_count = ucmd->rq_wqe_count;
4287 rwq->wqe_shift = ucmd->rq_wqe_shift;
4288 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4289 rwq->log_rq_stride = rwq->wqe_shift;
4290 rwq->log_rq_size = ilog2(rwq->wqe_count);
4291 return 0;
4292}
4293
4294static int prepare_user_rq(struct ib_pd *pd,
4295 struct ib_wq_init_attr *init_attr,
4296 struct ib_udata *udata,
4297 struct mlx5_ib_rwq *rwq)
4298{
4299 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4300 struct mlx5_ib_create_wq ucmd = {};
4301 int err;
4302 size_t required_cmd_sz;
4303
4304 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4305 if (udata->inlen < required_cmd_sz) {
4306 mlx5_ib_dbg(dev, "invalid inlen\n");
4307 return -EINVAL;
4308 }
4309
4310 if (udata->inlen > sizeof(ucmd) &&
4311 !ib_is_udata_cleared(udata, sizeof(ucmd),
4312 udata->inlen - sizeof(ucmd))) {
4313 mlx5_ib_dbg(dev, "inlen is not supported\n");
4314 return -EOPNOTSUPP;
4315 }
4316
4317 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4318 mlx5_ib_dbg(dev, "copy failed\n");
4319 return -EFAULT;
4320 }
4321
4322 if (ucmd.comp_mask) {
4323 mlx5_ib_dbg(dev, "invalid comp mask\n");
4324 return -EOPNOTSUPP;
4325 }
4326
4327 if (ucmd.reserved) {
4328 mlx5_ib_dbg(dev, "invalid reserved\n");
4329 return -EOPNOTSUPP;
4330 }
4331
4332 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4333 if (err) {
4334 mlx5_ib_dbg(dev, "err %d\n", err);
4335 return err;
4336 }
4337
4338 err = create_user_rq(dev, pd, rwq, &ucmd);
4339 if (err) {
4340 mlx5_ib_dbg(dev, "err %d\n", err);
4341 if (err)
4342 return err;
4343 }
4344
4345 rwq->user_index = ucmd.user_index;
4346 return 0;
4347}
4348
4349struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4350 struct ib_wq_init_attr *init_attr,
4351 struct ib_udata *udata)
4352{
4353 struct mlx5_ib_dev *dev;
4354 struct mlx5_ib_rwq *rwq;
4355 struct mlx5_ib_create_wq_resp resp = {};
4356 size_t min_resp_len;
4357 int err;
4358
4359 if (!udata)
4360 return ERR_PTR(-ENOSYS);
4361
4362 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4363 if (udata->outlen && udata->outlen < min_resp_len)
4364 return ERR_PTR(-EINVAL);
4365
4366 dev = to_mdev(pd->device);
4367 switch (init_attr->wq_type) {
4368 case IB_WQT_RQ:
4369 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4370 if (!rwq)
4371 return ERR_PTR(-ENOMEM);
4372 err = prepare_user_rq(pd, init_attr, udata, rwq);
4373 if (err)
4374 goto err;
4375 err = create_rq(rwq, pd, init_attr);
4376 if (err)
4377 goto err_user_rq;
4378 break;
4379 default:
4380 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4381 init_attr->wq_type);
4382 return ERR_PTR(-EINVAL);
4383 }
4384
4385 rwq->ibwq.wq_num = rwq->rqn;
4386 rwq->ibwq.state = IB_WQS_RESET;
4387 if (udata->outlen) {
4388 resp.response_length = offsetof(typeof(resp), response_length) +
4389 sizeof(resp.response_length);
4390 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4391 if (err)
4392 goto err_copy;
4393 }
4394
4395 return &rwq->ibwq;
4396
4397err_copy:
4398 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4399err_user_rq:
4400 destroy_user_rq(pd, rwq);
4401err:
4402 kfree(rwq);
4403 return ERR_PTR(err);
4404}
4405
4406int mlx5_ib_destroy_wq(struct ib_wq *wq)
4407{
4408 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4409 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4410
4411 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4412 destroy_user_rq(wq->pd, rwq);
4413 kfree(rwq);
4414
4415 return 0;
4416}
4417
4418int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4419 u32 wq_attr_mask, struct ib_udata *udata)
4420{
4421 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4422 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4423 struct mlx5_ib_modify_wq ucmd = {};
4424 size_t required_cmd_sz;
4425 int curr_wq_state;
4426 int wq_state;
4427 int inlen;
4428 int err;
4429 void *rqc;
4430 void *in;
4431
4432 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4433 if (udata->inlen < required_cmd_sz)
4434 return -EINVAL;
4435
4436 if (udata->inlen > sizeof(ucmd) &&
4437 !ib_is_udata_cleared(udata, sizeof(ucmd),
4438 udata->inlen - sizeof(ucmd)))
4439 return -EOPNOTSUPP;
4440
4441 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4442 return -EFAULT;
4443
4444 if (ucmd.comp_mask || ucmd.reserved)
4445 return -EOPNOTSUPP;
4446
4447 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4448 in = mlx5_vzalloc(inlen);
4449 if (!in)
4450 return -ENOMEM;
4451
4452 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4453
4454 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4455 wq_attr->curr_wq_state : wq->state;
4456 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4457 wq_attr->wq_state : curr_wq_state;
4458 if (curr_wq_state == IB_WQS_ERR)
4459 curr_wq_state = MLX5_RQC_STATE_ERR;
4460 if (wq_state == IB_WQS_ERR)
4461 wq_state = MLX5_RQC_STATE_ERR;
4462 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4463 MLX5_SET(rqc, rqc, state, wq_state);
4464
4465 err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4466 kvfree(in);
4467 if (!err)
4468 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4469
4470 return err;
4471}
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