]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/infiniband/hw/mlx5/qp.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IB/mlx5: Initialize mlx5_ib_qp signature-related members
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
35#include "mlx5_ib.h"
36#include "user.h"
37
38/* not supported currently */
39static int wq_signature;
40
41enum {
42 MLX5_IB_ACK_REQ_FREQ = 8,
43};
44
45enum {
46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
48 MLX5_IB_LINK_TYPE_IB = 0,
49 MLX5_IB_LINK_TYPE_ETH = 1
50};
51
52enum {
53 MLX5_IB_SQ_STRIDE = 6,
54 MLX5_IB_CACHE_LINE_SIZE = 64,
55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR,
68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
71};
72
73struct umr_wr {
74 u64 virt_addr;
75 struct ib_pd *pd;
76 unsigned int page_shift;
77 unsigned int npages;
78 u32 length;
79 int access_flags;
80 u32 mkey;
81};
82
83static int is_qp0(enum ib_qp_type qp_type)
84{
85 return qp_type == IB_QPT_SMI;
86}
87
88static int is_qp1(enum ib_qp_type qp_type)
89{
90 return qp_type == IB_QPT_GSI;
91}
92
93static int is_sqp(enum ib_qp_type qp_type)
94{
95 return is_qp0(qp_type) || is_qp1(qp_type);
96}
97
98static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99{
100 return mlx5_buf_offset(&qp->buf, offset);
101}
102
103static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104{
105 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106}
107
108void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109{
110 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111}
112
113static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
114{
115 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
116 struct ib_event event;
117
118 if (type == MLX5_EVENT_TYPE_PATH_MIG)
119 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
120
121 if (ibqp->event_handler) {
122 event.device = ibqp->device;
123 event.element.qp = ibqp;
124 switch (type) {
125 case MLX5_EVENT_TYPE_PATH_MIG:
126 event.event = IB_EVENT_PATH_MIG;
127 break;
128 case MLX5_EVENT_TYPE_COMM_EST:
129 event.event = IB_EVENT_COMM_EST;
130 break;
131 case MLX5_EVENT_TYPE_SQ_DRAINED:
132 event.event = IB_EVENT_SQ_DRAINED;
133 break;
134 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
135 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
136 break;
137 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
138 event.event = IB_EVENT_QP_FATAL;
139 break;
140 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
141 event.event = IB_EVENT_PATH_MIG_ERR;
142 break;
143 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
144 event.event = IB_EVENT_QP_REQ_ERR;
145 break;
146 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
147 event.event = IB_EVENT_QP_ACCESS_ERR;
148 break;
149 default:
150 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
151 return;
152 }
153
154 ibqp->event_handler(&event, ibqp->qp_context);
155 }
156}
157
158static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
159 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
160{
161 int wqe_size;
162 int wq_size;
163
164 /* Sanity check RQ size before proceeding */
165 if (cap->max_recv_wr > dev->mdev.caps.max_wqes)
166 return -EINVAL;
167
168 if (!has_rq) {
169 qp->rq.max_gs = 0;
170 qp->rq.wqe_cnt = 0;
171 qp->rq.wqe_shift = 0;
172 } else {
173 if (ucmd) {
174 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
175 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
176 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
177 qp->rq.max_post = qp->rq.wqe_cnt;
178 } else {
179 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
180 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
181 wqe_size = roundup_pow_of_two(wqe_size);
182 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
183 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
184 qp->rq.wqe_cnt = wq_size / wqe_size;
185 if (wqe_size > dev->mdev.caps.max_rq_desc_sz) {
186 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
187 wqe_size,
188 dev->mdev.caps.max_rq_desc_sz);
189 return -EINVAL;
190 }
191 qp->rq.wqe_shift = ilog2(wqe_size);
192 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
193 qp->rq.max_post = qp->rq.wqe_cnt;
194 }
195 }
196
197 return 0;
198}
199
200static int sq_overhead(enum ib_qp_type qp_type)
201{
618af384 202 int size = 0;
e126ba97
EC		 203
204 switch (qp_type) {
205 case IB_QPT_XRC_INI:
b125a54b 206 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 207 /* fall through */
208 case IB_QPT_RC:
209 size += sizeof(struct mlx5_wqe_ctrl_seg) +
210 sizeof(struct mlx5_wqe_atomic_seg) +
211 sizeof(struct mlx5_wqe_raddr_seg);
212 break;
213
b125a54b
EC		 214 case IB_QPT_XRC_TGT:
215 return 0;
216
e126ba97 217 case IB_QPT_UC:
b125a54b 218 size += sizeof(struct mlx5_wqe_ctrl_seg) +
9e65dc37
EC		 219 sizeof(struct mlx5_wqe_raddr_seg) +
220 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
221 sizeof(struct mlx5_mkey_seg);
e126ba97
EC		 222 break;
223
224 case IB_QPT_UD:
225 case IB_QPT_SMI:
226 case IB_QPT_GSI:
b125a54b 227 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 228 sizeof(struct mlx5_wqe_datagram_seg);
229 break;
230
231 case MLX5_IB_QPT_REG_UMR:
b125a54b 232 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 233 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
234 sizeof(struct mlx5_mkey_seg);
235 break;
236
237 default:
238 return -EINVAL;
239 }
240
241 return size;
242}
243
244static int calc_send_wqe(struct ib_qp_init_attr *attr)
245{
246 int inl_size = 0;
247 int size;
248
249 size = sq_overhead(attr->qp_type);
250 if (size < 0)
251 return size;
252
253 if (attr->cap.max_inline_data) {
254 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
255 attr->cap.max_inline_data;
256 }
257
258 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 259 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
260 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
261 return MLX5_SIG_WQE_SIZE;
262 else
263 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 264}
265
266static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
267 struct mlx5_ib_qp *qp)
268{
269 int wqe_size;
270 int wq_size;
271
272 if (!attr->cap.max_send_wr)
273 return 0;
274
275 wqe_size = calc_send_wqe(attr);
276 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
277 if (wqe_size < 0)
278 return wqe_size;
279
280 if (wqe_size > dev->mdev.caps.max_sq_desc_sz) {
b125a54b
EC		 281 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
282 wqe_size, dev->mdev.caps.max_sq_desc_sz);
e126ba97
EC		 283 return -EINVAL;
284 }
285
286 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
287 sizeof(struct mlx5_wqe_inline_seg);
288 attr->cap.max_inline_data = qp->max_inline_data;
289
e1e66cc2
SG		 290 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
291 qp->signature_en = true;
292
e126ba97
EC		 293 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
294 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
b125a54b
EC		 295 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
296 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
297 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
298 return -ENOMEM;
299 }
e126ba97
EC		 300 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
301 qp->sq.max_gs = attr->cap.max_send_sge;
b125a54b
EC		 302 qp->sq.max_post = wq_size / wqe_size;
303 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 304
305 return wq_size;
306}
307
308static int set_user_buf_size(struct mlx5_ib_dev *dev,
309 struct mlx5_ib_qp *qp,
310 struct mlx5_ib_create_qp *ucmd)
311{
312 int desc_sz = 1 << qp->sq.wqe_shift;
313
314 if (desc_sz > dev->mdev.caps.max_sq_desc_sz) {
315 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
316 desc_sz, dev->mdev.caps.max_sq_desc_sz);
317 return -EINVAL;
318 }
319
320 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
321 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
322 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
323 return -EINVAL;
324 }
325
326 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
327
328 if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
329 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
330 qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
331 return -EINVAL;
332 }
333
334 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
335 (qp->sq.wqe_cnt << 6);
336
337 return 0;
338}
339
340static int qp_has_rq(struct ib_qp_init_attr *attr)
341{
342 if (attr->qp_type == IB_QPT_XRC_INI ||
343 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
344 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
345 !attr->cap.max_recv_wr)
346 return 0;
347
348 return 1;
349}
350
c1be5232
EC		 351static int first_med_uuar(void)
352{
353 return 1;
354}
355
356static int next_uuar(int n)
357{
358 n++;
359
360 while (((n % 4) & 2))
361 n++;
362
363 return n;
364}
365
366static int num_med_uuar(struct mlx5_uuar_info *uuari)
367{
368 int n;
369
370 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
371 uuari->num_low_latency_uuars - 1;
372
373 return n >= 0 ? n : 0;
374}
375
376static int max_uuari(struct mlx5_uuar_info *uuari)
377{
378 return uuari->num_uars * 4;
379}
380
381static int first_hi_uuar(struct mlx5_uuar_info *uuari)
382{
383 int med;
384 int i;
385 int t;
386
387 med = num_med_uuar(uuari);
388 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
389 t++;
390 if (t == med)
391 return next_uuar(i);
392 }
393
394 return 0;
395}
396
e126ba97
EC		 397static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
398{
e126ba97
EC		 399 int i;
400
c1be5232 401 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
e126ba97
EC		 402 if (!test_bit(i, uuari->bitmap)) {
403 set_bit(i, uuari->bitmap);
404 uuari->count[i]++;
405 return i;
406 }
407 }
408
409 return -ENOMEM;
410}
411
412static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
413{
c1be5232 414 int minidx = first_med_uuar();
e126ba97
EC		 415 int i;
416
c1be5232 417 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
e126ba97
EC		 418 if (uuari->count[i] < uuari->count[minidx])
419 minidx = i;
420 }
421
422 uuari->count[minidx]++;
423 return minidx;
424}
425
426static int alloc_uuar(struct mlx5_uuar_info *uuari,
427 enum mlx5_ib_latency_class lat)
428{
429 int uuarn = -EINVAL;
430
431 mutex_lock(&uuari->lock);
432 switch (lat) {
433 case MLX5_IB_LATENCY_CLASS_LOW:
434 uuarn = 0;
435 uuari->count[uuarn]++;
436 break;
437
438 case MLX5_IB_LATENCY_CLASS_MEDIUM:
78c0f98c
EC		 439 if (uuari->ver < 2)
440 uuarn = -ENOMEM;
441 else
442 uuarn = alloc_med_class_uuar(uuari);
e126ba97
EC		 443 break;
444
445 case MLX5_IB_LATENCY_CLASS_HIGH:
78c0f98c
EC		 446 if (uuari->ver < 2)
447 uuarn = -ENOMEM;
448 else
449 uuarn = alloc_high_class_uuar(uuari);
e126ba97
EC		 450 break;
451
452 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
453 uuarn = 2;
454 break;
455 }
456 mutex_unlock(&uuari->lock);
457
458 return uuarn;
459}
460
461static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
462{
463 clear_bit(uuarn, uuari->bitmap);
464 --uuari->count[uuarn];
465}
466
467static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
468{
469 clear_bit(uuarn, uuari->bitmap);
470 --uuari->count[uuarn];
471}
472
473static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
474{
475 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
476 int high_uuar = nuuars - uuari->num_low_latency_uuars;
477
478 mutex_lock(&uuari->lock);
479 if (uuarn == 0) {
480 --uuari->count[uuarn];
481 goto out;
482 }
483
484 if (uuarn < high_uuar) {
485 free_med_class_uuar(uuari, uuarn);
486 goto out;
487 }
488
489 free_high_class_uuar(uuari, uuarn);
490
491out:
492 mutex_unlock(&uuari->lock);
493}
494
495static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
496{
497 switch (state) {
498 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
499 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
500 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
501 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
502 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
503 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
504 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
505 default: return -1;
506 }
507}
508
509static int to_mlx5_st(enum ib_qp_type type)
510{
511 switch (type) {
512 case IB_QPT_RC: return MLX5_QP_ST_RC;
513 case IB_QPT_UC: return MLX5_QP_ST_UC;
514 case IB_QPT_UD: return MLX5_QP_ST_UD;
515 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
516 case IB_QPT_XRC_INI:
517 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
518 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
519 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
520 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
521 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
522 case IB_QPT_RAW_PACKET:
523 case IB_QPT_MAX:
524 default: return -EINVAL;
525 }
526}
527
528static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
529{
530 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
531}
532
533static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
534 struct mlx5_ib_qp *qp, struct ib_udata *udata,
535 struct mlx5_create_qp_mbox_in **in,
536 struct mlx5_ib_create_qp_resp *resp, int *inlen)
537{
538 struct mlx5_ib_ucontext *context;
539 struct mlx5_ib_create_qp ucmd;
9e9c47d0 540 int page_shift = 0;
e126ba97
EC		 541 int uar_index;
542 int npages;
9e9c47d0 543 u32 offset = 0;
e126ba97 544 int uuarn;
9e9c47d0 545 int ncont = 0;
e126ba97
EC		 546 int err;
547
548 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
549 if (err) {
550 mlx5_ib_dbg(dev, "copy failed\n");
551 return err;
552 }
553
554 context = to_mucontext(pd->uobject->context);
555 /*
556 * TBD: should come from the verbs when we have the API
557 */
558 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
559 if (uuarn < 0) {
560 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
c1be5232
EC		 561 mlx5_ib_dbg(dev, "reverting to medium latency\n");
562 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
e126ba97 563 if (uuarn < 0) {
c1be5232
EC		 564 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
565 mlx5_ib_dbg(dev, "reverting to high latency\n");
566 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
567 if (uuarn < 0) {
568 mlx5_ib_warn(dev, "uuar allocation failed\n");
569 return uuarn;
570 }
e126ba97
EC		 571 }
572 }
573
574 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
575 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
576
577 err = set_user_buf_size(dev, qp, &ucmd);
578 if (err)
579 goto err_uuar;
580
9e9c47d0
EC		 581 if (ucmd.buf_addr && qp->buf_size) {
582 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
583 qp->buf_size, 0, 0);
584 if (IS_ERR(qp->umem)) {
585 mlx5_ib_dbg(dev, "umem_get failed\n");
586 err = PTR_ERR(qp->umem);
587 goto err_uuar;
588 }
589 } else {
590 qp->umem = NULL;
e126ba97
EC		 591 }
592
9e9c47d0
EC		 593 if (qp->umem) {
594 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
595 &ncont, NULL);
596 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
597 if (err) {
598 mlx5_ib_warn(dev, "bad offset\n");
599 goto err_umem;
600 }
601 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
602 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
e126ba97 603 }
e126ba97
EC		 604
605 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
606 *in = mlx5_vzalloc(*inlen);
607 if (!*in) {
608 err = -ENOMEM;
609 goto err_umem;
610 }
9e9c47d0
EC		 611 if (qp->umem)
612 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
e126ba97 613 (*in)->ctx.log_pg_sz_remote_qpn =
1b77d2bd 614 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 615 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
616
617 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
618 resp->uuar_index = uuarn;
619 qp->uuarn = uuarn;
620
621 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
622 if (err) {
623 mlx5_ib_dbg(dev, "map failed\n");
624 goto err_free;
625 }
626
627 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
628 if (err) {
629 mlx5_ib_dbg(dev, "copy failed\n");
630 goto err_unmap;
631 }
632 qp->create_type = MLX5_QP_USER;
633
634 return 0;
635
636err_unmap:
637 mlx5_ib_db_unmap_user(context, &qp->db);
638
639err_free:
640 mlx5_vfree(*in);
641
642err_umem:
9e9c47d0
EC		 643 if (qp->umem)
644 ib_umem_release(qp->umem);
e126ba97
EC		 645
646err_uuar:
647 free_uuar(&context->uuari, uuarn);
648 return err;
649}
650
651static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
652{
653 struct mlx5_ib_ucontext *context;
654
655 context = to_mucontext(pd->uobject->context);
656 mlx5_ib_db_unmap_user(context, &qp->db);
9e9c47d0
EC		 657 if (qp->umem)
658 ib_umem_release(qp->umem);
e126ba97
EC		 659 free_uuar(&context->uuari, qp->uuarn);
660}
661
662static int create_kernel_qp(struct mlx5_ib_dev *dev,
663 struct ib_qp_init_attr *init_attr,
664 struct mlx5_ib_qp *qp,
665 struct mlx5_create_qp_mbox_in **in, int *inlen)
666{
667 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
668 struct mlx5_uuar_info *uuari;
669 int uar_index;
670 int uuarn;
671 int err;
672
673 uuari = &dev->mdev.priv.uuari;
e1e66cc2 674 if (init_attr->create_flags & ~IB_QP_CREATE_SIGNATURE_EN)
1a4c3a3d 675 return -EINVAL;
e126ba97
EC		 676
677 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
678 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
679
680 uuarn = alloc_uuar(uuari, lc);
681 if (uuarn < 0) {
682 mlx5_ib_dbg(dev, "\n");
683 return -ENOMEM;
684 }
685
686 qp->bf = &uuari->bfs[uuarn];
687 uar_index = qp->bf->uar->index;
688
689 err = calc_sq_size(dev, init_attr, qp);
690 if (err < 0) {
691 mlx5_ib_dbg(dev, "err %d\n", err);
692 goto err_uuar;
693 }
694
695 qp->rq.offset = 0;
696 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
697 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
698
699 err = mlx5_buf_alloc(&dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf);
700 if (err) {
701 mlx5_ib_dbg(dev, "err %d\n", err);
702 goto err_uuar;
703 }
704
705 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
706 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
707 *in = mlx5_vzalloc(*inlen);
708 if (!*in) {
709 err = -ENOMEM;
710 goto err_buf;
711 }
712 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
1b77d2bd
EC		 713 (*in)->ctx.log_pg_sz_remote_qpn =
714 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
e126ba97
EC		 715 /* Set "fast registration enabled" for all kernel QPs */
716 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
717 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
718
719 mlx5_fill_page_array(&qp->buf, (*in)->pas);
720
721 err = mlx5_db_alloc(&dev->mdev, &qp->db);
722 if (err) {
723 mlx5_ib_dbg(dev, "err %d\n", err);
724 goto err_free;
725 }
726
727 qp->db.db[0] = 0;
728 qp->db.db[1] = 0;
729
730 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
731 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
732 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
733 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
734 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
735
736 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
737 !qp->sq.w_list || !qp->sq.wqe_head) {
738 err = -ENOMEM;
739 goto err_wrid;
740 }
741 qp->create_type = MLX5_QP_KERNEL;
742
743 return 0;
744
745err_wrid:
746 mlx5_db_free(&dev->mdev, &qp->db);
747 kfree(qp->sq.wqe_head);
748 kfree(qp->sq.w_list);
749 kfree(qp->sq.wrid);
750 kfree(qp->sq.wr_data);
751 kfree(qp->rq.wrid);
752
753err_free:
754 mlx5_vfree(*in);
755
756err_buf:
757 mlx5_buf_free(&dev->mdev, &qp->buf);
758
759err_uuar:
760 free_uuar(&dev->mdev.priv.uuari, uuarn);
761 return err;
762}
763
764static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
765{
766 mlx5_db_free(&dev->mdev, &qp->db);
767 kfree(qp->sq.wqe_head);
768 kfree(qp->sq.w_list);
769 kfree(qp->sq.wrid);
770 kfree(qp->sq.wr_data);
771 kfree(qp->rq.wrid);
772 mlx5_buf_free(&dev->mdev, &qp->buf);
773 free_uuar(&dev->mdev.priv.uuari, qp->bf->uuarn);
774}
775
776static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
777{
778 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
779 (attr->qp_type == IB_QPT_XRC_INI))
780 return cpu_to_be32(MLX5_SRQ_RQ);
781 else if (!qp->has_rq)
782 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
783 else
784 return cpu_to_be32(MLX5_NON_ZERO_RQ);
785}
786
787static int is_connected(enum ib_qp_type qp_type)
788{
789 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
790 return 1;
791
792 return 0;
793}
794
795static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
796 struct ib_qp_init_attr *init_attr,
797 struct ib_udata *udata, struct mlx5_ib_qp *qp)
798{
799 struct mlx5_ib_resources *devr = &dev->devr;
800 struct mlx5_ib_create_qp_resp resp;
801 struct mlx5_create_qp_mbox_in *in;
802 struct mlx5_ib_create_qp ucmd;
803 int inlen = sizeof(*in);
804 int err;
805
806 mutex_init(&qp->mutex);
807 spin_lock_init(&qp->sq.lock);
808 spin_lock_init(&qp->rq.lock);
809
810 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
811 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
812
813 if (pd && pd->uobject) {
814 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
815 mlx5_ib_dbg(dev, "copy failed\n");
816 return -EFAULT;
817 }
818
819 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
820 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
821 } else {
822 qp->wq_sig = !!wq_signature;
823 }
824
825 qp->has_rq = qp_has_rq(init_attr);
826 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
827 qp, (pd && pd->uobject) ? &ucmd : NULL);
828 if (err) {
829 mlx5_ib_dbg(dev, "err %d\n", err);
830 return err;
831 }
832
833 if (pd) {
834 if (pd->uobject) {
835 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
836 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
837 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
838 mlx5_ib_dbg(dev, "invalid rq params\n");
839 return -EINVAL;
840 }
841 if (ucmd.sq_wqe_count > dev->mdev.caps.max_wqes) {
842 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
843 ucmd.sq_wqe_count, dev->mdev.caps.max_wqes);
844 return -EINVAL;
845 }
846 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
847 if (err)
848 mlx5_ib_dbg(dev, "err %d\n", err);
849 } else {
850 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
851 if (err)
852 mlx5_ib_dbg(dev, "err %d\n", err);
853 else
854 qp->pa_lkey = to_mpd(pd)->pa_lkey;
855 }
856
857 if (err)
858 return err;
859 } else {
860 in = mlx5_vzalloc(sizeof(*in));
861 if (!in)
862 return -ENOMEM;
863
864 qp->create_type = MLX5_QP_EMPTY;
865 }
866
867 if (is_sqp(init_attr->qp_type))
868 qp->port = init_attr->port_num;
869
870 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
871 MLX5_QP_PM_MIGRATED << 11);
872
873 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
874 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
875 else
876 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
877
878 if (qp->wq_sig)
879 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
880
881 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
882 int rcqe_sz;
883 int scqe_sz;
884
885 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
886 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
887
888 if (rcqe_sz == 128)
889 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
890 else
891 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
892
893 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
894 if (scqe_sz == 128)
895 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
896 else
897 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
898 }
899 }
900
901 if (qp->rq.wqe_cnt) {
902 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
903 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
904 }
905
906 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
907
908 if (qp->sq.wqe_cnt)
909 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
910 else
911 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
912
913 /* Set default resources */
914 switch (init_attr->qp_type) {
915 case IB_QPT_XRC_TGT:
916 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
917 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
918 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
919 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
920 break;
921 case IB_QPT_XRC_INI:
922 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
923 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
924 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
925 break;
926 default:
927 if (init_attr->srq) {
928 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
929 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
930 } else {
931 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
932 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
933 }
934 }
935
936 if (init_attr->send_cq)
937 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
938
939 if (init_attr->recv_cq)
940 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
941
942 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
943
944 err = mlx5_core_create_qp(&dev->mdev, &qp->mqp, in, inlen);
945 if (err) {
946 mlx5_ib_dbg(dev, "create qp failed\n");
947 goto err_create;
948 }
949
950 mlx5_vfree(in);
951 /* Hardware wants QPN written in big-endian order (after
952 * shifting) for send doorbell. Precompute this value to save
953 * a little bit when posting sends.
954 */
955 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
956
957 qp->mqp.event = mlx5_ib_qp_event;
958
959 return 0;
960
961err_create:
962 if (qp->create_type == MLX5_QP_USER)
963 destroy_qp_user(pd, qp);
964 else if (qp->create_type == MLX5_QP_KERNEL)
965 destroy_qp_kernel(dev, qp);
966
967 mlx5_vfree(in);
968 return err;
969}
970
971static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
972 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
973{
974 if (send_cq) {
975 if (recv_cq) {
976 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
977 spin_lock_irq(&send_cq->lock);
978 spin_lock_nested(&recv_cq->lock,
979 SINGLE_DEPTH_NESTING);
980 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
981 spin_lock_irq(&send_cq->lock);
982 __acquire(&recv_cq->lock);
983 } else {
984 spin_lock_irq(&recv_cq->lock);
985 spin_lock_nested(&send_cq->lock,
986 SINGLE_DEPTH_NESTING);
987 }
988 } else {
989 spin_lock_irq(&send_cq->lock);
990 }
991 } else if (recv_cq) {
992 spin_lock_irq(&recv_cq->lock);
993 }
994}
995
996static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
997 __releases(&send_cq->lock) __releases(&recv_cq->lock)
998{
999 if (send_cq) {
1000 if (recv_cq) {
1001 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1002 spin_unlock(&recv_cq->lock);
1003 spin_unlock_irq(&send_cq->lock);
1004 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1005 __release(&recv_cq->lock);
1006 spin_unlock_irq(&send_cq->lock);
1007 } else {
1008 spin_unlock(&send_cq->lock);
1009 spin_unlock_irq(&recv_cq->lock);
1010 }
1011 } else {
1012 spin_unlock_irq(&send_cq->lock);
1013 }
1014 } else if (recv_cq) {
1015 spin_unlock_irq(&recv_cq->lock);
1016 }
1017}
1018
1019static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1020{
1021 return to_mpd(qp->ibqp.pd);
1022}
1023
1024static void get_cqs(struct mlx5_ib_qp *qp,
1025 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1026{
1027 switch (qp->ibqp.qp_type) {
1028 case IB_QPT_XRC_TGT:
1029 *send_cq = NULL;
1030 *recv_cq = NULL;
1031 break;
1032 case MLX5_IB_QPT_REG_UMR:
1033 case IB_QPT_XRC_INI:
1034 *send_cq = to_mcq(qp->ibqp.send_cq);
1035 *recv_cq = NULL;
1036 break;
1037
1038 case IB_QPT_SMI:
1039 case IB_QPT_GSI:
1040 case IB_QPT_RC:
1041 case IB_QPT_UC:
1042 case IB_QPT_UD:
1043 case IB_QPT_RAW_IPV6:
1044 case IB_QPT_RAW_ETHERTYPE:
1045 *send_cq = to_mcq(qp->ibqp.send_cq);
1046 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1047 break;
1048
1049 case IB_QPT_RAW_PACKET:
1050 case IB_QPT_MAX:
1051 default:
1052 *send_cq = NULL;
1053 *recv_cq = NULL;
1054 break;
1055 }
1056}
1057
1058static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1059{
1060 struct mlx5_ib_cq *send_cq, *recv_cq;
1061 struct mlx5_modify_qp_mbox_in *in;
1062 int err;
1063
1064 in = kzalloc(sizeof(*in), GFP_KERNEL);
1065 if (!in)
1066 return;
1067 if (qp->state != IB_QPS_RESET)
1068 if (mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(qp->state),
1069 MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp))
1070 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1071 qp->mqp.qpn);
1072
1073 get_cqs(qp, &send_cq, &recv_cq);
1074
1075 if (qp->create_type == MLX5_QP_KERNEL) {
1076 mlx5_ib_lock_cqs(send_cq, recv_cq);
1077 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1078 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1079 if (send_cq != recv_cq)
1080 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1081 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1082 }
1083
1084 err = mlx5_core_destroy_qp(&dev->mdev, &qp->mqp);
1085 if (err)
1086 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1087 kfree(in);
1088
1089
1090 if (qp->create_type == MLX5_QP_KERNEL)
1091 destroy_qp_kernel(dev, qp);
1092 else if (qp->create_type == MLX5_QP_USER)
1093 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1094}
1095
1096static const char *ib_qp_type_str(enum ib_qp_type type)
1097{
1098 switch (type) {
1099 case IB_QPT_SMI:
1100 return "IB_QPT_SMI";
1101 case IB_QPT_GSI:
1102 return "IB_QPT_GSI";
1103 case IB_QPT_RC:
1104 return "IB_QPT_RC";
1105 case IB_QPT_UC:
1106 return "IB_QPT_UC";
1107 case IB_QPT_UD:
1108 return "IB_QPT_UD";
1109 case IB_QPT_RAW_IPV6:
1110 return "IB_QPT_RAW_IPV6";
1111 case IB_QPT_RAW_ETHERTYPE:
1112 return "IB_QPT_RAW_ETHERTYPE";
1113 case IB_QPT_XRC_INI:
1114 return "IB_QPT_XRC_INI";
1115 case IB_QPT_XRC_TGT:
1116 return "IB_QPT_XRC_TGT";
1117 case IB_QPT_RAW_PACKET:
1118 return "IB_QPT_RAW_PACKET";
1119 case MLX5_IB_QPT_REG_UMR:
1120 return "MLX5_IB_QPT_REG_UMR";
1121 case IB_QPT_MAX:
1122 default:
1123 return "Invalid QP type";
1124 }
1125}
1126
1127struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1128 struct ib_qp_init_attr *init_attr,
1129 struct ib_udata *udata)
1130{
1131 struct mlx5_ib_dev *dev;
1132 struct mlx5_ib_qp *qp;
1133 u16 xrcdn = 0;
1134 int err;
1135
1136 if (pd) {
1137 dev = to_mdev(pd->device);
1138 } else {
1139 /* being cautious here */
1140 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1141 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1142 pr_warn("%s: no PD for transport %s\n", __func__,
1143 ib_qp_type_str(init_attr->qp_type));
1144 return ERR_PTR(-EINVAL);
1145 }
1146 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1147 }
1148
1149 switch (init_attr->qp_type) {
1150 case IB_QPT_XRC_TGT:
1151 case IB_QPT_XRC_INI:
1152 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC)) {
1153 mlx5_ib_dbg(dev, "XRC not supported\n");
1154 return ERR_PTR(-ENOSYS);
1155 }
1156 init_attr->recv_cq = NULL;
1157 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1158 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1159 init_attr->send_cq = NULL;
1160 }
1161
1162 /* fall through */
1163 case IB_QPT_RC:
1164 case IB_QPT_UC:
1165 case IB_QPT_UD:
1166 case IB_QPT_SMI:
1167 case IB_QPT_GSI:
1168 case MLX5_IB_QPT_REG_UMR:
1169 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1170 if (!qp)
1171 return ERR_PTR(-ENOMEM);
1172
1173 err = create_qp_common(dev, pd, init_attr, udata, qp);
1174 if (err) {
1175 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1176 kfree(qp);
1177 return ERR_PTR(err);
1178 }
1179
1180 if (is_qp0(init_attr->qp_type))
1181 qp->ibqp.qp_num = 0;
1182 else if (is_qp1(init_attr->qp_type))
1183 qp->ibqp.qp_num = 1;
1184 else
1185 qp->ibqp.qp_num = qp->mqp.qpn;
1186
1187 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1188 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1189 to_mcq(init_attr->send_cq)->mcq.cqn);
1190
1191 qp->xrcdn = xrcdn;
1192
1193 break;
1194
1195 case IB_QPT_RAW_IPV6:
1196 case IB_QPT_RAW_ETHERTYPE:
1197 case IB_QPT_RAW_PACKET:
1198 case IB_QPT_MAX:
1199 default:
1200 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1201 init_attr->qp_type);
1202 /* Don't support raw QPs */
1203 return ERR_PTR(-EINVAL);
1204 }
1205
1206 return &qp->ibqp;
1207}
1208
1209int mlx5_ib_destroy_qp(struct ib_qp *qp)
1210{
1211 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1212 struct mlx5_ib_qp *mqp = to_mqp(qp);
1213
1214 destroy_qp_common(dev, mqp);
1215
1216 kfree(mqp);
1217
1218 return 0;
1219}
1220
1221static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1222 int attr_mask)
1223{
1224 u32 hw_access_flags = 0;
1225 u8 dest_rd_atomic;
1226 u32 access_flags;
1227
1228 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1229 dest_rd_atomic = attr->max_dest_rd_atomic;
1230 else
1231 dest_rd_atomic = qp->resp_depth;
1232
1233 if (attr_mask & IB_QP_ACCESS_FLAGS)
1234 access_flags = attr->qp_access_flags;
1235 else
1236 access_flags = qp->atomic_rd_en;
1237
1238 if (!dest_rd_atomic)
1239 access_flags &= IB_ACCESS_REMOTE_WRITE;
1240
1241 if (access_flags & IB_ACCESS_REMOTE_READ)
1242 hw_access_flags |= MLX5_QP_BIT_RRE;
1243 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1244 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1245 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1246 hw_access_flags |= MLX5_QP_BIT_RWE;
1247
1248 return cpu_to_be32(hw_access_flags);
1249}
1250
1251enum {
1252 MLX5_PATH_FLAG_FL = 1 << 0,
1253 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1254 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1255};
1256
1257static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1258{
1259 if (rate == IB_RATE_PORT_CURRENT) {
1260 return 0;
1261 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1262 return -EINVAL;
1263 } else {
1264 while (rate != IB_RATE_2_5_GBPS &&
1265 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1266 dev->mdev.caps.stat_rate_support))
1267 --rate;
1268 }
1269
1270 return rate + MLX5_STAT_RATE_OFFSET;
1271}
1272
1273static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1274 struct mlx5_qp_path *path, u8 port, int attr_mask,
1275 u32 path_flags, const struct ib_qp_attr *attr)
1276{
1277 int err;
1278
1279 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1280 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1281
1282 if (attr_mask & IB_QP_PKEY_INDEX)
1283 path->pkey_index = attr->pkey_index;
1284
1285 path->grh_mlid = ah->src_path_bits & 0x7f;
1286 path->rlid = cpu_to_be16(ah->dlid);
1287
1288 if (ah->ah_flags & IB_AH_GRH) {
1289 path->grh_mlid |= 1 << 7;
1290 path->mgid_index = ah->grh.sgid_index;
1291 path->hop_limit = ah->grh.hop_limit;
1292 path->tclass_flowlabel =
1293 cpu_to_be32((ah->grh.traffic_class << 20) |
1294 (ah->grh.flow_label));
1295 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1296 }
1297
1298 err = ib_rate_to_mlx5(dev, ah->static_rate);
1299 if (err < 0)
1300 return err;
1301 path->static_rate = err;
1302 path->port = port;
1303
1304 if (ah->ah_flags & IB_AH_GRH) {
1305 if (ah->grh.sgid_index >= dev->mdev.caps.port[port - 1].gid_table_len) {
1306 pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n",
1307 ah->grh.sgid_index, dev->mdev.caps.port[port - 1].gid_table_len);
1308 return -EINVAL;
1309 }
1310
1311 path->grh_mlid |= 1 << 7;
1312 path->mgid_index = ah->grh.sgid_index;
1313 path->hop_limit = ah->grh.hop_limit;
1314 path->tclass_flowlabel =
1315 cpu_to_be32((ah->grh.traffic_class << 20) |
1316 (ah->grh.flow_label));
1317 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1318 }
1319
1320 if (attr_mask & IB_QP_TIMEOUT)
1321 path->ackto_lt = attr->timeout << 3;
1322
1323 path->sl = ah->sl & 0xf;
1324
1325 return 0;
1326}
1327
1328static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1329 [MLX5_QP_STATE_INIT] = {
1330 [MLX5_QP_STATE_INIT] = {
1331 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1332 MLX5_QP_OPTPAR_RAE |
1333 MLX5_QP_OPTPAR_RWE |
1334 MLX5_QP_OPTPAR_PKEY_INDEX |
1335 MLX5_QP_OPTPAR_PRI_PORT,
1336 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1337 MLX5_QP_OPTPAR_PKEY_INDEX |
1338 MLX5_QP_OPTPAR_PRI_PORT,
1339 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1340 MLX5_QP_OPTPAR_Q_KEY |
1341 MLX5_QP_OPTPAR_PRI_PORT,
1342 },
1343 [MLX5_QP_STATE_RTR] = {
1344 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1345 MLX5_QP_OPTPAR_RRE |
1346 MLX5_QP_OPTPAR_RAE |
1347 MLX5_QP_OPTPAR_RWE |
1348 MLX5_QP_OPTPAR_PKEY_INDEX,
1349 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1350 MLX5_QP_OPTPAR_RWE |
1351 MLX5_QP_OPTPAR_PKEY_INDEX,
1352 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1353 MLX5_QP_OPTPAR_Q_KEY,
1354 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1355 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 1356 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1357 MLX5_QP_OPTPAR_RRE |
1358 MLX5_QP_OPTPAR_RAE |
1359 MLX5_QP_OPTPAR_RWE |
1360 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 1361 },
1362 },
1363 [MLX5_QP_STATE_RTR] = {
1364 [MLX5_QP_STATE_RTS] = {
1365 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1366 MLX5_QP_OPTPAR_RRE |
1367 MLX5_QP_OPTPAR_RAE |
1368 MLX5_QP_OPTPAR_RWE |
1369 MLX5_QP_OPTPAR_PM_STATE |
1370 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1371 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1372 MLX5_QP_OPTPAR_RWE |
1373 MLX5_QP_OPTPAR_PM_STATE,
1374 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1375 },
1376 },
1377 [MLX5_QP_STATE_RTS] = {
1378 [MLX5_QP_STATE_RTS] = {
1379 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1380 MLX5_QP_OPTPAR_RAE |
1381 MLX5_QP_OPTPAR_RWE |
1382 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 1383 MLX5_QP_OPTPAR_PM_STATE |
1384 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 1385 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 1386 MLX5_QP_OPTPAR_PM_STATE |
1387 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 1388 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1389 MLX5_QP_OPTPAR_SRQN |
1390 MLX5_QP_OPTPAR_CQN_RCV,
1391 },
1392 },
1393 [MLX5_QP_STATE_SQER] = {
1394 [MLX5_QP_STATE_RTS] = {
1395 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1396 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 1397 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 1398 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1399 MLX5_QP_OPTPAR_RWE |
1400 MLX5_QP_OPTPAR_RAE |
1401 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 1402 },
1403 },
1404};
1405
1406static int ib_nr_to_mlx5_nr(int ib_mask)
1407{
1408 switch (ib_mask) {
1409 case IB_QP_STATE:
1410 return 0;
1411 case IB_QP_CUR_STATE:
1412 return 0;
1413 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1414 return 0;
1415 case IB_QP_ACCESS_FLAGS:
1416 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1417 MLX5_QP_OPTPAR_RAE;
1418 case IB_QP_PKEY_INDEX:
1419 return MLX5_QP_OPTPAR_PKEY_INDEX;
1420 case IB_QP_PORT:
1421 return MLX5_QP_OPTPAR_PRI_PORT;
1422 case IB_QP_QKEY:
1423 return MLX5_QP_OPTPAR_Q_KEY;
1424 case IB_QP_AV:
1425 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1426 MLX5_QP_OPTPAR_PRI_PORT;
1427 case IB_QP_PATH_MTU:
1428 return 0;
1429 case IB_QP_TIMEOUT:
1430 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1431 case IB_QP_RETRY_CNT:
1432 return MLX5_QP_OPTPAR_RETRY_COUNT;
1433 case IB_QP_RNR_RETRY:
1434 return MLX5_QP_OPTPAR_RNR_RETRY;
1435 case IB_QP_RQ_PSN:
1436 return 0;
1437 case IB_QP_MAX_QP_RD_ATOMIC:
1438 return MLX5_QP_OPTPAR_SRA_MAX;
1439 case IB_QP_ALT_PATH:
1440 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1441 case IB_QP_MIN_RNR_TIMER:
1442 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1443 case IB_QP_SQ_PSN:
1444 return 0;
1445 case IB_QP_MAX_DEST_RD_ATOMIC:
1446 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1447 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1448 case IB_QP_PATH_MIG_STATE:
1449 return MLX5_QP_OPTPAR_PM_STATE;
1450 case IB_QP_CAP:
1451 return 0;
1452 case IB_QP_DEST_QPN:
1453 return 0;
1454 }
1455 return 0;
1456}
1457
1458static int ib_mask_to_mlx5_opt(int ib_mask)
1459{
1460 int result = 0;
1461 int i;
1462
1463 for (i = 0; i < 8 * sizeof(int); i++) {
1464 if ((1 << i) & ib_mask)
1465 result |= ib_nr_to_mlx5_nr(1 << i);
1466 }
1467
1468 return result;
1469}
1470
1471static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1472 const struct ib_qp_attr *attr, int attr_mask,
1473 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1474{
1475 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1476 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1477 struct mlx5_ib_cq *send_cq, *recv_cq;
1478 struct mlx5_qp_context *context;
1479 struct mlx5_modify_qp_mbox_in *in;
1480 struct mlx5_ib_pd *pd;
1481 enum mlx5_qp_state mlx5_cur, mlx5_new;
1482 enum mlx5_qp_optpar optpar;
1483 int sqd_event;
1484 int mlx5_st;
1485 int err;
1486
1487 in = kzalloc(sizeof(*in), GFP_KERNEL);
1488 if (!in)
1489 return -ENOMEM;
1490
1491 context = &in->ctx;
1492 err = to_mlx5_st(ibqp->qp_type);
1493 if (err < 0)
1494 goto out;
1495
1496 context->flags = cpu_to_be32(err << 16);
1497
1498 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1499 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1500 } else {
1501 switch (attr->path_mig_state) {
1502 case IB_MIG_MIGRATED:
1503 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1504 break;
1505 case IB_MIG_REARM:
1506 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1507 break;
1508 case IB_MIG_ARMED:
1509 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1510 break;
1511 }
1512 }
1513
1514 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1515 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1516 } else if (ibqp->qp_type == IB_QPT_UD ||
1517 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1518 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1519 } else if (attr_mask & IB_QP_PATH_MTU) {
1520 if (attr->path_mtu < IB_MTU_256 ||
1521 attr->path_mtu > IB_MTU_4096) {
1522 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1523 err = -EINVAL;
1524 goto out;
1525 }
1526 context->mtu_msgmax = (attr->path_mtu << 5) | dev->mdev.caps.log_max_msg;
1527 }
1528
1529 if (attr_mask & IB_QP_DEST_QPN)
1530 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1531
1532 if (attr_mask & IB_QP_PKEY_INDEX)
1533 context->pri_path.pkey_index = attr->pkey_index;
1534
1535 /* todo implement counter_index functionality */
1536
1537 if (is_sqp(ibqp->qp_type))
1538 context->pri_path.port = qp->port;
1539
1540 if (attr_mask & IB_QP_PORT)
1541 context->pri_path.port = attr->port_num;
1542
1543 if (attr_mask & IB_QP_AV) {
1544 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1545 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1546 attr_mask, 0, attr);
1547 if (err)
1548 goto out;
1549 }
1550
1551 if (attr_mask & IB_QP_TIMEOUT)
1552 context->pri_path.ackto_lt |= attr->timeout << 3;
1553
1554 if (attr_mask & IB_QP_ALT_PATH) {
1555 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1556 attr->alt_port_num, attr_mask, 0, attr);
1557 if (err)
1558 goto out;
1559 }
1560
1561 pd = get_pd(qp);
1562 get_cqs(qp, &send_cq, &recv_cq);
1563
1564 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1565 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1566 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1567 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1568
1569 if (attr_mask & IB_QP_RNR_RETRY)
1570 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1571
1572 if (attr_mask & IB_QP_RETRY_CNT)
1573 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1574
1575 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1576 if (attr->max_rd_atomic)
1577 context->params1 |=
1578 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1579 }
1580
1581 if (attr_mask & IB_QP_SQ_PSN)
1582 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1583
1584 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1585 if (attr->max_dest_rd_atomic)
1586 context->params2 |=
1587 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1588 }
1589
1590 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1591 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1592
1593 if (attr_mask & IB_QP_MIN_RNR_TIMER)
1594 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1595
1596 if (attr_mask & IB_QP_RQ_PSN)
1597 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1598
1599 if (attr_mask & IB_QP_QKEY)
1600 context->qkey = cpu_to_be32(attr->qkey);
1601
1602 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1603 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1604
1605 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1606 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1607 sqd_event = 1;
1608 else
1609 sqd_event = 0;
1610
1611 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1612 context->sq_crq_size |= cpu_to_be16(1 << 4);
1613
1614
1615 mlx5_cur = to_mlx5_state(cur_state);
1616 mlx5_new = to_mlx5_state(new_state);
1617 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 1618 if (mlx5_st < 0)
e126ba97
EC		 1619 goto out;
1620
1621 optpar = ib_mask_to_mlx5_opt(attr_mask);
1622 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1623 in->optparam = cpu_to_be32(optpar);
1624 err = mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(cur_state),
1625 to_mlx5_state(new_state), in, sqd_event,
1626 &qp->mqp);
1627 if (err)
1628 goto out;
1629
1630 qp->state = new_state;
1631
1632 if (attr_mask & IB_QP_ACCESS_FLAGS)
1633 qp->atomic_rd_en = attr->qp_access_flags;
1634 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1635 qp->resp_depth = attr->max_dest_rd_atomic;
1636 if (attr_mask & IB_QP_PORT)
1637 qp->port = attr->port_num;
1638 if (attr_mask & IB_QP_ALT_PATH)
1639 qp->alt_port = attr->alt_port_num;
1640
1641 /*
1642 * If we moved a kernel QP to RESET, clean up all old CQ
1643 * entries and reinitialize the QP.
1644 */
1645 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1646 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1647 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1648 if (send_cq != recv_cq)
1649 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1650
1651 qp->rq.head = 0;
1652 qp->rq.tail = 0;
1653 qp->sq.head = 0;
1654 qp->sq.tail = 0;
1655 qp->sq.cur_post = 0;
1656 qp->sq.last_poll = 0;
1657 qp->db.db[MLX5_RCV_DBR] = 0;
1658 qp->db.db[MLX5_SND_DBR] = 0;
1659 }
1660
1661out:
1662 kfree(in);
1663 return err;
1664}
1665
1666int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1667 int attr_mask, struct ib_udata *udata)
1668{
1669 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1670 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1671 enum ib_qp_state cur_state, new_state;
1672 int err = -EINVAL;
1673 int port;
1674
1675 mutex_lock(&qp->mutex);
1676
1677 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1678 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1679
1680 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
dd5f03be
MB		 1681 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
1682 IB_LINK_LAYER_UNSPECIFIED))
e126ba97
EC		 1683 goto out;
1684
1685 if ((attr_mask & IB_QP_PORT) &&
1686 (attr->port_num == 0 || attr->port_num > dev->mdev.caps.num_ports))
1687 goto out;
1688
1689 if (attr_mask & IB_QP_PKEY_INDEX) {
1690 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1691 if (attr->pkey_index >= dev->mdev.caps.port[port - 1].pkey_table_len)
1692 goto out;
1693 }
1694
1695 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1696 attr->max_rd_atomic > dev->mdev.caps.max_ra_res_qp)
1697 goto out;
1698
1699 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1700 attr->max_dest_rd_atomic > dev->mdev.caps.max_ra_req_qp)
1701 goto out;
1702
1703 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1704 err = 0;
1705 goto out;
1706 }
1707
1708 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1709
1710out:
1711 mutex_unlock(&qp->mutex);
1712 return err;
1713}
1714
1715static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1716{
1717 struct mlx5_ib_cq *cq;
1718 unsigned cur;
1719
1720 cur = wq->head - wq->tail;
1721 if (likely(cur + nreq < wq->max_post))
1722 return 0;
1723
1724 cq = to_mcq(ib_cq);
1725 spin_lock(&cq->lock);
1726 cur = wq->head - wq->tail;
1727 spin_unlock(&cq->lock);
1728
1729 return cur + nreq >= wq->max_post;
1730}
1731
1732static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1733 u64 remote_addr, u32 rkey)
1734{
1735 rseg->raddr = cpu_to_be64(remote_addr);
1736 rseg->rkey = cpu_to_be32(rkey);
1737 rseg->reserved = 0;
1738}
1739
e126ba97
EC		 1740static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1741 struct ib_send_wr *wr)
1742{
1743 memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1744 dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1745 dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1746}
1747
1748static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1749{
1750 dseg->byte_count = cpu_to_be32(sg->length);
1751 dseg->lkey = cpu_to_be32(sg->lkey);
1752 dseg->addr = cpu_to_be64(sg->addr);
1753}
1754
1755static __be16 get_klm_octo(int npages)
1756{
1757 return cpu_to_be16(ALIGN(npages, 8) / 2);
1758}
1759
1760static __be64 frwr_mkey_mask(void)
1761{
1762 u64 result;
1763
1764 result = MLX5_MKEY_MASK_LEN |
1765 MLX5_MKEY_MASK_PAGE_SIZE |
1766 MLX5_MKEY_MASK_START_ADDR |
1767 MLX5_MKEY_MASK_EN_RINVAL |
1768 MLX5_MKEY_MASK_KEY |
1769 MLX5_MKEY_MASK_LR |
1770 MLX5_MKEY_MASK_LW |
1771 MLX5_MKEY_MASK_RR |
1772 MLX5_MKEY_MASK_RW |
1773 MLX5_MKEY_MASK_A |
1774 MLX5_MKEY_MASK_SMALL_FENCE |
1775 MLX5_MKEY_MASK_FREE;
1776
1777 return cpu_to_be64(result);
1778}
1779
1780static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1781 struct ib_send_wr *wr, int li)
1782{
1783 memset(umr, 0, sizeof(*umr));
1784
1785 if (li) {
1786 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1787 umr->flags = 1 << 7;
1788 return;
1789 }
1790
1791 umr->flags = (1 << 5); /* fail if not free */
1792 umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1793 umr->mkey_mask = frwr_mkey_mask();
1794}
1795
1796static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1797 struct ib_send_wr *wr)
1798{
1799 struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg;
1800 u64 mask;
1801
1802 memset(umr, 0, sizeof(*umr));
1803
1804 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1805 umr->flags = 1 << 5; /* fail if not free */
1806 umr->klm_octowords = get_klm_octo(umrwr->npages);
1807 mask = MLX5_MKEY_MASK_LEN |
1808 MLX5_MKEY_MASK_PAGE_SIZE |
1809 MLX5_MKEY_MASK_START_ADDR |
1810 MLX5_MKEY_MASK_PD |
1811 MLX5_MKEY_MASK_LR |
1812 MLX5_MKEY_MASK_LW |
746b5583 1813 MLX5_MKEY_MASK_KEY |
e126ba97
EC		 1814 MLX5_MKEY_MASK_RR |
1815 MLX5_MKEY_MASK_RW |
1816 MLX5_MKEY_MASK_A |
1817 MLX5_MKEY_MASK_FREE;
1818 umr->mkey_mask = cpu_to_be64(mask);
1819 } else {
1820 umr->flags = 2 << 5; /* fail if free */
1821 mask = MLX5_MKEY_MASK_FREE;
1822 umr->mkey_mask = cpu_to_be64(mask);
1823 }
1824
1825 if (!wr->num_sge)
1826 umr->flags |= (1 << 7); /* inline */
1827}
1828
1829static u8 get_umr_flags(int acc)
1830{
1831 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1832 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1833 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1834 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1835 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
1836}
1837
1838static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1839 int li, int *writ)
1840{
1841 memset(seg, 0, sizeof(*seg));
1842 if (li) {
1843 seg->status = 1 << 6;
1844 return;
1845 }
1846
1847 seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags);
1848 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
1849 seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
1850 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
1851 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1852 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1853 seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
1854 seg->log2_page_size = wr->wr.fast_reg.page_shift;
1855}
1856
1857static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
1858{
1859 memset(seg, 0, sizeof(*seg));
1860 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
1861 seg->status = 1 << 6;
1862 return;
1863 }
1864
1865 seg->flags = convert_access(wr->wr.fast_reg.access_flags);
1866 seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn);
1867 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1868 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1869 seg->log2_page_size = wr->wr.fast_reg.page_shift;
746b5583
EC		 1870 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
1871 mlx5_mkey_variant(wr->wr.fast_reg.rkey));
e126ba97
EC		 1872}
1873
1874static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
1875 struct ib_send_wr *wr,
1876 struct mlx5_core_dev *mdev,
1877 struct mlx5_ib_pd *pd,
1878 int writ)
1879{
1880 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1881 u64 *page_list = wr->wr.fast_reg.page_list->page_list;
1882 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
1883 int i;
1884
1885 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
1886 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
1887 dseg->addr = cpu_to_be64(mfrpl->map);
1888 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
1889 dseg->lkey = cpu_to_be32(pd->pa_lkey);
1890}
1891
1892static __be32 send_ieth(struct ib_send_wr *wr)
1893{
1894 switch (wr->opcode) {
1895 case IB_WR_SEND_WITH_IMM:
1896 case IB_WR_RDMA_WRITE_WITH_IMM:
1897 return wr->ex.imm_data;
1898
1899 case IB_WR_SEND_WITH_INV:
1900 return cpu_to_be32(wr->ex.invalidate_rkey);
1901
1902 default:
1903 return 0;
1904 }
1905}
1906
1907static u8 calc_sig(void *wqe, int size)
1908{
1909 u8 *p = wqe;
1910 u8 res = 0;
1911 int i;
1912
1913 for (i = 0; i < size; i++)
1914 res ^= p[i];
1915
1916 return ~res;
1917}
1918
1919static u8 wq_sig(void *wqe)
1920{
1921 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
1922}
1923
1924static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
1925 void *wqe, int *sz)
1926{
1927 struct mlx5_wqe_inline_seg *seg;
1928 void *qend = qp->sq.qend;
1929 void *addr;
1930 int inl = 0;
1931 int copy;
1932 int len;
1933 int i;
1934
1935 seg = wqe;
1936 wqe += sizeof(*seg);
1937 for (i = 0; i < wr->num_sge; i++) {
1938 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
1939 len = wr->sg_list[i].length;
1940 inl += len;
1941
1942 if (unlikely(inl > qp->max_inline_data))
1943 return -ENOMEM;
1944
1945 if (unlikely(wqe + len > qend)) {
1946 copy = qend - wqe;
1947 memcpy(wqe, addr, copy);
1948 addr += copy;
1949 len -= copy;
1950 wqe = mlx5_get_send_wqe(qp, 0);
1951 }
1952 memcpy(wqe, addr, len);
1953 wqe += len;
1954 }
1955
1956 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
1957
1958 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
1959
1960 return 0;
1961}
1962
1963static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
1964 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
1965{
1966 int writ = 0;
1967 int li;
1968
1969 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
1970 if (unlikely(wr->send_flags & IB_SEND_INLINE))
1971 return -EINVAL;
1972
1973 set_frwr_umr_segment(*seg, wr, li);
1974 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
1975 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
1976 if (unlikely((*seg == qp->sq.qend)))
1977 *seg = mlx5_get_send_wqe(qp, 0);
1978 set_mkey_segment(*seg, wr, li, &writ);
1979 *seg += sizeof(struct mlx5_mkey_seg);
1980 *size += sizeof(struct mlx5_mkey_seg) / 16;
1981 if (unlikely((*seg == qp->sq.qend)))
1982 *seg = mlx5_get_send_wqe(qp, 0);
1983 if (!li) {
9641b74e
EC		 1984 if (unlikely(wr->wr.fast_reg.page_list_len >
1985 wr->wr.fast_reg.page_list->max_page_list_len))
1986 return -ENOMEM;
1987
e126ba97
EC		 1988 set_frwr_pages(*seg, wr, mdev, pd, writ);
1989 *seg += sizeof(struct mlx5_wqe_data_seg);
1990 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
1991 }
1992 return 0;
1993}
1994
1995static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
1996{
1997 __be32 *p = NULL;
1998 int tidx = idx;
1999 int i, j;
2000
2001 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
2002 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
2003 if ((i & 0xf) == 0) {
2004 void *buf = mlx5_get_send_wqe(qp, tidx);
2005 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
2006 p = buf;
2007 j = 0;
2008 }
2009 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
2010 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
2011 be32_to_cpu(p[j + 3]));
2012 }
2013}
2014
2015static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2016 unsigned bytecnt, struct mlx5_ib_qp *qp)
2017{
2018 while (bytecnt > 0) {
2019 __iowrite64_copy(dst++, src++, 8);
2020 __iowrite64_copy(dst++, src++, 8);
2021 __iowrite64_copy(dst++, src++, 8);
2022 __iowrite64_copy(dst++, src++, 8);
2023 __iowrite64_copy(dst++, src++, 8);
2024 __iowrite64_copy(dst++, src++, 8);
2025 __iowrite64_copy(dst++, src++, 8);
2026 __iowrite64_copy(dst++, src++, 8);
2027 bytecnt -= 64;
2028 if (unlikely(src == qp->sq.qend))
2029 src = mlx5_get_send_wqe(qp, 0);
2030 }
2031}
2032
2033static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2034{
2035 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2036 wr->send_flags & IB_SEND_FENCE))
2037 return MLX5_FENCE_MODE_STRONG_ORDERING;
2038
2039 if (unlikely(fence)) {
2040 if (wr->send_flags & IB_SEND_FENCE)
2041 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2042 else
2043 return fence;
2044
2045 } else {
2046 return 0;
2047 }
2048}
2049
2050int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2051 struct ib_send_wr **bad_wr)
2052{
2053 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
2054 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2055 struct mlx5_core_dev *mdev = &dev->mdev;
2056 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2057 struct mlx5_wqe_data_seg *dpseg;
2058 struct mlx5_wqe_xrc_seg *xrc;
2059 struct mlx5_bf *bf = qp->bf;
2060 int uninitialized_var(size);
2061 void *qend = qp->sq.qend;
2062 unsigned long flags;
2063 u32 mlx5_opcode;
2064 unsigned idx;
2065 int err = 0;
2066 int inl = 0;
2067 int num_sge;
2068 void *seg;
2069 int nreq;
2070 int i;
2071 u8 next_fence = 0;
2072 u8 opmod = 0;
2073 u8 fence;
2074
2075 spin_lock_irqsave(&qp->sq.lock, flags);
2076
2077 for (nreq = 0; wr; nreq++, wr = wr->next) {
2078 if (unlikely(wr->opcode >= sizeof(mlx5_ib_opcode) / sizeof(mlx5_ib_opcode[0]))) {
2079 mlx5_ib_warn(dev, "\n");
2080 err = -EINVAL;
2081 *bad_wr = wr;
2082 goto out;
2083 }
2084
2085 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2086 mlx5_ib_warn(dev, "\n");
2087 err = -ENOMEM;
2088 *bad_wr = wr;
2089 goto out;
2090 }
2091
2092 fence = qp->fm_cache;
2093 num_sge = wr->num_sge;
2094 if (unlikely(num_sge > qp->sq.max_gs)) {
2095 mlx5_ib_warn(dev, "\n");
2096 err = -ENOMEM;
2097 *bad_wr = wr;
2098 goto out;
2099 }
2100
2101 idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2102 seg = mlx5_get_send_wqe(qp, idx);
2103 ctrl = seg;
2104 *(uint32_t *)(seg + 8) = 0;
2105 ctrl->imm = send_ieth(wr);
2106 ctrl->fm_ce_se = qp->sq_signal_bits |
2107 (wr->send_flags & IB_SEND_SIGNALED ?
2108 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2109 (wr->send_flags & IB_SEND_SOLICITED ?
2110 MLX5_WQE_CTRL_SOLICITED : 0);
2111
2112 seg += sizeof(*ctrl);
2113 size = sizeof(*ctrl) / 16;
2114
2115 switch (ibqp->qp_type) {
2116 case IB_QPT_XRC_INI:
2117 xrc = seg;
2118 xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2119 seg += sizeof(*xrc);
2120 size += sizeof(*xrc) / 16;
2121 /* fall through */
2122 case IB_QPT_RC:
2123 switch (wr->opcode) {
2124 case IB_WR_RDMA_READ:
2125 case IB_WR_RDMA_WRITE:
2126 case IB_WR_RDMA_WRITE_WITH_IMM:
2127 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2128 wr->wr.rdma.rkey);
2129 seg += sizeof(struct mlx5_wqe_raddr_seg);
2130 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2131 break;
2132
2133 case IB_WR_ATOMIC_CMP_AND_SWP:
2134 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 2135 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 2136 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2137 err = -ENOSYS;
2138 *bad_wr = wr;
2139 goto out;
e126ba97
EC		 2140
2141 case IB_WR_LOCAL_INV:
2142 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2143 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2144 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2145 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2146 if (err) {
2147 mlx5_ib_warn(dev, "\n");
2148 *bad_wr = wr;
2149 goto out;
2150 }
2151 num_sge = 0;
2152 break;
2153
2154 case IB_WR_FAST_REG_MR:
2155 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2156 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2157 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2158 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2159 if (err) {
2160 mlx5_ib_warn(dev, "\n");
2161 *bad_wr = wr;
2162 goto out;
2163 }
2164 num_sge = 0;
2165 break;
2166
2167 default:
2168 break;
2169 }
2170 break;
2171
2172 case IB_QPT_UC:
2173 switch (wr->opcode) {
2174 case IB_WR_RDMA_WRITE:
2175 case IB_WR_RDMA_WRITE_WITH_IMM:
2176 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2177 wr->wr.rdma.rkey);
2178 seg += sizeof(struct mlx5_wqe_raddr_seg);
2179 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2180 break;
2181
2182 default:
2183 break;
2184 }
2185 break;
2186
2187 case IB_QPT_UD:
2188 case IB_QPT_SMI:
2189 case IB_QPT_GSI:
2190 set_datagram_seg(seg, wr);
2191 seg += sizeof(struct mlx5_wqe_datagram_seg);
2192 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2193 if (unlikely((seg == qend)))
2194 seg = mlx5_get_send_wqe(qp, 0);
2195 break;
2196
2197 case MLX5_IB_QPT_REG_UMR:
2198 if (wr->opcode != MLX5_IB_WR_UMR) {
2199 err = -EINVAL;
2200 mlx5_ib_warn(dev, "bad opcode\n");
2201 goto out;
2202 }
2203 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2204 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2205 set_reg_umr_segment(seg, wr);
2206 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2207 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2208 if (unlikely((seg == qend)))
2209 seg = mlx5_get_send_wqe(qp, 0);
2210 set_reg_mkey_segment(seg, wr);
2211 seg += sizeof(struct mlx5_mkey_seg);
2212 size += sizeof(struct mlx5_mkey_seg) / 16;
2213 if (unlikely((seg == qend)))
2214 seg = mlx5_get_send_wqe(qp, 0);
2215 break;
2216
2217 default:
2218 break;
2219 }
2220
2221 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2222 int uninitialized_var(sz);
2223
2224 err = set_data_inl_seg(qp, wr, seg, &sz);
2225 if (unlikely(err)) {
2226 mlx5_ib_warn(dev, "\n");
2227 *bad_wr = wr;
2228 goto out;
2229 }
2230 inl = 1;
2231 size += sz;
2232 } else {
2233 dpseg = seg;
2234 for (i = 0; i < num_sge; i++) {
2235 if (unlikely(dpseg == qend)) {
2236 seg = mlx5_get_send_wqe(qp, 0);
2237 dpseg = seg;
2238 }
2239 if (likely(wr->sg_list[i].length)) {
2240 set_data_ptr_seg(dpseg, wr->sg_list + i);
2241 size += sizeof(struct mlx5_wqe_data_seg) / 16;
2242 dpseg++;
2243 }
2244 }
2245 }
2246
2247 mlx5_opcode = mlx5_ib_opcode[wr->opcode];
2248 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2249 mlx5_opcode |
2250 ((u32)opmod << 24));
2251 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2252 ctrl->fm_ce_se |= get_fence(fence, wr);
2253 qp->fm_cache = next_fence;
2254 if (unlikely(qp->wq_sig))
2255 ctrl->signature = wq_sig(ctrl);
2256
2257 qp->sq.wrid[idx] = wr->wr_id;
2258 qp->sq.w_list[idx].opcode = mlx5_opcode;
2259 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2260 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2261 qp->sq.w_list[idx].next = qp->sq.cur_post;
2262
2263 if (0)
2264 dump_wqe(qp, idx, size);
2265 }
2266
2267out:
2268 if (likely(nreq)) {
2269 qp->sq.head += nreq;
2270
2271 /* Make sure that descriptors are written before
2272 * updating doorbell record and ringing the doorbell
2273 */
2274 wmb();
2275
2276 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2277
ada388f7
EC		 2278 /* Make sure doorbell record is visible to the HCA before
2279 * we hit doorbell */
2280 wmb();
2281
e126ba97
EC		 2282 if (bf->need_lock)
2283 spin_lock(&bf->lock);
2284
2285 /* TBD enable WC */
2286 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2287 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2288 /* wc_wmb(); */
2289 } else {
2290 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2291 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2292 /* Make sure doorbells don't leak out of SQ spinlock
2293 * and reach the HCA out of order.
2294 */
2295 mmiowb();
2296 }
2297 bf->offset ^= bf->buf_size;
2298 if (bf->need_lock)
2299 spin_unlock(&bf->lock);
2300 }
2301
2302 spin_unlock_irqrestore(&qp->sq.lock, flags);
2303
2304 return err;
2305}
2306
2307static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2308{
2309 sig->signature = calc_sig(sig, size);
2310}
2311
2312int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2313 struct ib_recv_wr **bad_wr)
2314{
2315 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2316 struct mlx5_wqe_data_seg *scat;
2317 struct mlx5_rwqe_sig *sig;
2318 unsigned long flags;
2319 int err = 0;
2320 int nreq;
2321 int ind;
2322 int i;
2323
2324 spin_lock_irqsave(&qp->rq.lock, flags);
2325
2326 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2327
2328 for (nreq = 0; wr; nreq++, wr = wr->next) {
2329 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2330 err = -ENOMEM;
2331 *bad_wr = wr;
2332 goto out;
2333 }
2334
2335 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2336 err = -EINVAL;
2337 *bad_wr = wr;
2338 goto out;
2339 }
2340
2341 scat = get_recv_wqe(qp, ind);
2342 if (qp->wq_sig)
2343 scat++;
2344
2345 for (i = 0; i < wr->num_sge; i++)
2346 set_data_ptr_seg(scat + i, wr->sg_list + i);
2347
2348 if (i < qp->rq.max_gs) {
2349 scat[i].byte_count = 0;
2350 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
2351 scat[i].addr = 0;
2352 }
2353
2354 if (qp->wq_sig) {
2355 sig = (struct mlx5_rwqe_sig *)scat;
2356 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2357 }
2358
2359 qp->rq.wrid[ind] = wr->wr_id;
2360
2361 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2362 }
2363
2364out:
2365 if (likely(nreq)) {
2366 qp->rq.head += nreq;
2367
2368 /* Make sure that descriptors are written before
2369 * doorbell record.
2370 */
2371 wmb();
2372
2373 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2374 }
2375
2376 spin_unlock_irqrestore(&qp->rq.lock, flags);
2377
2378 return err;
2379}
2380
2381static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2382{
2383 switch (mlx5_state) {
2384 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
2385 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
2386 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
2387 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
2388 case MLX5_QP_STATE_SQ_DRAINING:
2389 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
2390 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
2391 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
2392 default: return -1;
2393 }
2394}
2395
2396static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2397{
2398 switch (mlx5_mig_state) {
2399 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
2400 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
2401 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
2402 default: return -1;
2403 }
2404}
2405
2406static int to_ib_qp_access_flags(int mlx5_flags)
2407{
2408 int ib_flags = 0;
2409
2410 if (mlx5_flags & MLX5_QP_BIT_RRE)
2411 ib_flags |= IB_ACCESS_REMOTE_READ;
2412 if (mlx5_flags & MLX5_QP_BIT_RWE)
2413 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2414 if (mlx5_flags & MLX5_QP_BIT_RAE)
2415 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2416
2417 return ib_flags;
2418}
2419
2420static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2421 struct mlx5_qp_path *path)
2422{
2423 struct mlx5_core_dev *dev = &ibdev->mdev;
2424
2425 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
2426 ib_ah_attr->port_num = path->port;
2427
2428 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2429 return;
2430
2431 ib_ah_attr->sl = path->sl & 0xf;
2432
2433 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
2434 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
2435 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
2436 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
2437 if (ib_ah_attr->ah_flags) {
2438 ib_ah_attr->grh.sgid_index = path->mgid_index;
2439 ib_ah_attr->grh.hop_limit = path->hop_limit;
2440 ib_ah_attr->grh.traffic_class =
2441 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2442 ib_ah_attr->grh.flow_label =
2443 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2444 memcpy(ib_ah_attr->grh.dgid.raw,
2445 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
2446 }
2447}
2448
2449int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2450 struct ib_qp_init_attr *qp_init_attr)
2451{
2452 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2453 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2454 struct mlx5_query_qp_mbox_out *outb;
2455 struct mlx5_qp_context *context;
2456 int mlx5_state;
2457 int err = 0;
2458
2459 mutex_lock(&qp->mutex);
2460 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
2461 if (!outb) {
2462 err = -ENOMEM;
2463 goto out;
2464 }
2465 context = &outb->ctx;
2466 err = mlx5_core_qp_query(&dev->mdev, &qp->mqp, outb, sizeof(*outb));
2467 if (err)
2468 goto out_free;
2469
2470 mlx5_state = be32_to_cpu(context->flags) >> 28;
2471
2472 qp->state = to_ib_qp_state(mlx5_state);
2473 qp_attr->qp_state = qp->state;
2474 qp_attr->path_mtu = context->mtu_msgmax >> 5;
2475 qp_attr->path_mig_state =
2476 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
2477 qp_attr->qkey = be32_to_cpu(context->qkey);
2478 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
2479 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
2480 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
2481 qp_attr->qp_access_flags =
2482 to_ib_qp_access_flags(be32_to_cpu(context->params2));
2483
2484 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2485 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
2486 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
2487 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
2488 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
2489 }
2490
2491 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
2492 qp_attr->port_num = context->pri_path.port;
2493
2494 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2495 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
2496
2497 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
2498
2499 qp_attr->max_dest_rd_atomic =
2500 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
2501 qp_attr->min_rnr_timer =
2502 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
2503 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
2504 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
2505 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
2506 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
2507 qp_attr->cur_qp_state = qp_attr->qp_state;
2508 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
2509 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
2510
2511 if (!ibqp->uobject) {
2512 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
2513 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2514 } else {
2515 qp_attr->cap.max_send_wr = 0;
2516 qp_attr->cap.max_send_sge = 0;
2517 }
2518
2519 /* We don't support inline sends for kernel QPs (yet), and we
2520 * don't know what userspace's value should be.
2521 */
2522 qp_attr->cap.max_inline_data = 0;
2523
2524 qp_init_attr->cap = qp_attr->cap;
2525
2526 qp_init_attr->create_flags = 0;
2527 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2528 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2529
2530 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
2531 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2532
2533out_free:
2534 kfree(outb);
2535
2536out:
2537 mutex_unlock(&qp->mutex);
2538 return err;
2539}
2540
2541struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
2542 struct ib_ucontext *context,
2543 struct ib_udata *udata)
2544{
2545 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2546 struct mlx5_ib_xrcd *xrcd;
2547 int err;
2548
2549 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC))
2550 return ERR_PTR(-ENOSYS);
2551
2552 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
2553 if (!xrcd)
2554 return ERR_PTR(-ENOMEM);
2555
2556 err = mlx5_core_xrcd_alloc(&dev->mdev, &xrcd->xrcdn);
2557 if (err) {
2558 kfree(xrcd);
2559 return ERR_PTR(-ENOMEM);
2560 }
2561
2562 return &xrcd->ibxrcd;
2563}
2564
2565int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
2566{
2567 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
2568 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
2569 int err;
2570
2571 err = mlx5_core_xrcd_dealloc(&dev->mdev, xrcdn);
2572 if (err) {
2573 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
2574 return err;
2575 }
2576
2577 kfree(xrcd);
2578
2579 return 0;
2580}
Ubuntu Hirsute Linux kernel mirror