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Merge tag 'ntb-4.13-bugfixes' of git://github.com/jonmason/ntb
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97 37#include "mlx5_ib.h"
e126ba97
EC		 38
39/* not supported currently */
40static int wq_signature;
41
42enum {
43 MLX5_IB_ACK_REQ_FREQ = 8,
44};
45
46enum {
47 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
48 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49 MLX5_IB_LINK_TYPE_IB = 0,
50 MLX5_IB_LINK_TYPE_ETH = 1
51};
52
53enum {
54 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 59 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 60 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
61 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
62 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
63 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
64 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
65 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
66 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
67 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 68 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 69 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
70 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
71 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
72};
73
f0313965
ES		 74struct mlx5_wqe_eth_pad {
75 u8 rsvd0[16];
76};
e126ba97 77
eb49ab0c
AV		 78enum raw_qp_set_mask_map {
79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 80 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 81};
82
0680efa2
AV		 83struct mlx5_modify_raw_qp_param {
84 u16 operation;
eb49ab0c
AV		 85
86 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 87 u32 rate_limit;
eb49ab0c 88 u8 rq_q_ctr_id;
0680efa2
AV		 89};
90
89ea94a7
MG		 91static void get_cqs(enum ib_qp_type qp_type,
92 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
93 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
94
e126ba97
EC		 95static int is_qp0(enum ib_qp_type qp_type)
96{
97 return qp_type == IB_QPT_SMI;
98}
99
e126ba97
EC		 100static int is_sqp(enum ib_qp_type qp_type)
101{
102 return is_qp0(qp_type) || is_qp1(qp_type);
103}
104
105static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
106{
107 return mlx5_buf_offset(&qp->buf, offset);
108}
109
110static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
111{
112 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
113}
114
115void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
116{
117 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
118}
119
c1395a2a
HE		 120/**
121 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
122 *
123 * @qp: QP to copy from.
124 * @send: copy from the send queue when non-zero, use the receive queue
125 * otherwise.
126 * @wqe_index: index to start copying from. For send work queues, the
127 * wqe_index is in units of MLX5_SEND_WQE_BB.
128 * For receive work queue, it is the number of work queue
129 * element in the queue.
130 * @buffer: destination buffer.
131 * @length: maximum number of bytes to copy.
132 *
133 * Copies at least a single WQE, but may copy more data.
134 *
135 * Return: the number of bytes copied, or an error code.
136 */
137int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 138 void *buffer, u32 length,
139 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 140{
141 struct ib_device *ibdev = qp->ibqp.device;
142 struct mlx5_ib_dev *dev = to_mdev(ibdev);
143 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
144 size_t offset;
145 size_t wq_end;
19098df2 146 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 147 u32 first_copy_length;
148 int wqe_length;
149 int ret;
150
151 if (wq->wqe_cnt == 0) {
152 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
153 qp->ibqp.qp_type);
154 return -EINVAL;
155 }
156
157 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
158 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
159
160 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
161 return -EINVAL;
162
163 if (offset > umem->length ||
164 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
165 return -EINVAL;
166
167 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
168 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
169 if (ret)
170 return ret;
171
172 if (send) {
173 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
174 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
175
176 wqe_length = ds * MLX5_WQE_DS_UNITS;
177 } else {
178 wqe_length = 1 << wq->wqe_shift;
179 }
180
181 if (wqe_length <= first_copy_length)
182 return first_copy_length;
183
184 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
185 wqe_length - first_copy_length);
186 if (ret)
187 return ret;
188
189 return wqe_length;
190}
191
e126ba97
EC		 192static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
193{
194 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
195 struct ib_event event;
196
19098df2 197 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
198 /* This event is only valid for trans_qps */
199 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
200 }
e126ba97
EC		 201
202 if (ibqp->event_handler) {
203 event.device = ibqp->device;
204 event.element.qp = ibqp;
205 switch (type) {
206 case MLX5_EVENT_TYPE_PATH_MIG:
207 event.event = IB_EVENT_PATH_MIG;
208 break;
209 case MLX5_EVENT_TYPE_COMM_EST:
210 event.event = IB_EVENT_COMM_EST;
211 break;
212 case MLX5_EVENT_TYPE_SQ_DRAINED:
213 event.event = IB_EVENT_SQ_DRAINED;
214 break;
215 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
216 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
217 break;
218 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
219 event.event = IB_EVENT_QP_FATAL;
220 break;
221 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
222 event.event = IB_EVENT_PATH_MIG_ERR;
223 break;
224 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
225 event.event = IB_EVENT_QP_REQ_ERR;
226 break;
227 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
228 event.event = IB_EVENT_QP_ACCESS_ERR;
229 break;
230 default:
231 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
232 return;
233 }
234
235 ibqp->event_handler(&event, ibqp->qp_context);
236 }
237}
238
239static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
240 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
241{
242 int wqe_size;
243 int wq_size;
244
245 /* Sanity check RQ size before proceeding */
938fe83c 246 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 247 return -EINVAL;
248
249 if (!has_rq) {
250 qp->rq.max_gs = 0;
251 qp->rq.wqe_cnt = 0;
252 qp->rq.wqe_shift = 0;
0540d814
NO		 253 cap->max_recv_wr = 0;
254 cap->max_recv_sge = 0;
e126ba97
EC		 255 } else {
256 if (ucmd) {
257 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
258 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
259 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
260 qp->rq.max_post = qp->rq.wqe_cnt;
261 } else {
262 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
263 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
264 wqe_size = roundup_pow_of_two(wqe_size);
265 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
266 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
267 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 268 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 269 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
270 wqe_size,
938fe83c
SM		 271 MLX5_CAP_GEN(dev->mdev,
272 max_wqe_sz_rq));
e126ba97
EC		 273 return -EINVAL;
274 }
275 qp->rq.wqe_shift = ilog2(wqe_size);
276 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
277 qp->rq.max_post = qp->rq.wqe_cnt;
278 }
279 }
280
281 return 0;
282}
283
f0313965 284static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 285{
618af384 286 int size = 0;
e126ba97 287
f0313965 288 switch (attr->qp_type) {
e126ba97 289 case IB_QPT_XRC_INI:
b125a54b 290 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 291 /* fall through */
292 case IB_QPT_RC:
293 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 294 max(sizeof(struct mlx5_wqe_atomic_seg) +
295 sizeof(struct mlx5_wqe_raddr_seg),
296 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
297 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 298 break;
299
b125a54b
EC		 300 case IB_QPT_XRC_TGT:
301 return 0;
302
e126ba97 303 case IB_QPT_UC:
b125a54b 304 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 305 max(sizeof(struct mlx5_wqe_raddr_seg),
306 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
307 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 308 break;
309
310 case IB_QPT_UD:
f0313965
ES		 311 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
312 size += sizeof(struct mlx5_wqe_eth_pad) +
313 sizeof(struct mlx5_wqe_eth_seg);
314 /* fall through */
e126ba97 315 case IB_QPT_SMI:
d16e91da 316 case MLX5_IB_QPT_HW_GSI:
b125a54b 317 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 318 sizeof(struct mlx5_wqe_datagram_seg);
319 break;
320
321 case MLX5_IB_QPT_REG_UMR:
b125a54b 322 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 323 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
324 sizeof(struct mlx5_mkey_seg);
325 break;
326
327 default:
328 return -EINVAL;
329 }
330
331 return size;
332}
333
334static int calc_send_wqe(struct ib_qp_init_attr *attr)
335{
336 int inl_size = 0;
337 int size;
338
f0313965 339 size = sq_overhead(attr);
e126ba97
EC		 340 if (size < 0)
341 return size;
342
343 if (attr->cap.max_inline_data) {
344 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
345 attr->cap.max_inline_data;
346 }
347
348 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 349 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
350 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
351 return MLX5_SIG_WQE_SIZE;
352 else
353 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 354}
355
288c01b7
EC		 356static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357{
358 int max_sge;
359
360 if (attr->qp_type == IB_QPT_RC)
361 max_sge = (min_t(int, wqe_size, 512) -
362 sizeof(struct mlx5_wqe_ctrl_seg) -
363 sizeof(struct mlx5_wqe_raddr_seg)) /
364 sizeof(struct mlx5_wqe_data_seg);
365 else if (attr->qp_type == IB_QPT_XRC_INI)
366 max_sge = (min_t(int, wqe_size, 512) -
367 sizeof(struct mlx5_wqe_ctrl_seg) -
368 sizeof(struct mlx5_wqe_xrc_seg) -
369 sizeof(struct mlx5_wqe_raddr_seg)) /
370 sizeof(struct mlx5_wqe_data_seg);
371 else
372 max_sge = (wqe_size - sq_overhead(attr)) /
373 sizeof(struct mlx5_wqe_data_seg);
374
375 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
376 sizeof(struct mlx5_wqe_data_seg));
377}
378
e126ba97
EC		 379static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
380 struct mlx5_ib_qp *qp)
381{
382 int wqe_size;
383 int wq_size;
384
385 if (!attr->cap.max_send_wr)
386 return 0;
387
388 wqe_size = calc_send_wqe(attr);
389 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
390 if (wqe_size < 0)
391 return wqe_size;
392
938fe83c 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 394 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 395 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 396 return -EINVAL;
397 }
398
f0313965
ES		 399 qp->max_inline_data = wqe_size - sq_overhead(attr) -
400 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 401 attr->cap.max_inline_data = qp->max_inline_data;
402
e1e66cc2
SG		 403 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
404 qp->signature_en = true;
405
e126ba97
EC		 406 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
407 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 408 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 409 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
410 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 411 qp->sq.wqe_cnt,
412 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 413 return -ENOMEM;
414 }
e126ba97 415 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 416 qp->sq.max_gs = get_send_sge(attr, wqe_size);
417 if (qp->sq.max_gs < attr->cap.max_send_sge)
418 return -ENOMEM;
419
420 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 421 qp->sq.max_post = wq_size / wqe_size;
422 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 423
424 return wq_size;
425}
426
427static int set_user_buf_size(struct mlx5_ib_dev *dev,
428 struct mlx5_ib_qp *qp,
19098df2 429 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 430 struct mlx5_ib_qp_base *base,
431 struct ib_qp_init_attr *attr)
e126ba97
EC		 432{
433 int desc_sz = 1 << qp->sq.wqe_shift;
434
938fe83c 435 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 436 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 437 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 438 return -EINVAL;
439 }
440
441 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
442 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
443 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
444 return -EINVAL;
445 }
446
447 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
448
938fe83c 449 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 450 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 451 qp->sq.wqe_cnt,
452 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 453 return -EINVAL;
454 }
455
0fb2ed66 456 if (attr->qp_type == IB_QPT_RAW_PACKET) {
457 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
458 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
459 } else {
460 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
461 (qp->sq.wqe_cnt << 6);
462 }
e126ba97
EC		 463
464 return 0;
465}
466
467static int qp_has_rq(struct ib_qp_init_attr *attr)
468{
469 if (attr->qp_type == IB_QPT_XRC_INI ||
470 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
471 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
472 !attr->cap.max_recv_wr)
473 return 0;
474
475 return 1;
476}
477
2f5ff264 478static int first_med_bfreg(void)
c1be5232
EC		 479{
480 return 1;
481}
482
0b80c14f
EC		 483enum {
484 /* this is the first blue flame register in the array of bfregs assigned
485 * to a processes. Since we do not use it for blue flame but rather
486 * regular 64 bit doorbells, we do not need a lock for maintaiing
487 * "odd/even" order
488 */
489 NUM_NON_BLUE_FLAME_BFREGS = 1,
490};
491
b037c29a
EC		 492static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
493{
494 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
495}
496
497static int num_med_bfreg(struct mlx5_ib_dev *dev,
498 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 499{
500 int n;
501
b037c29a
EC		 502 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
503 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 504
505 return n >= 0 ? n : 0;
506}
507
b037c29a
EC		 508static int first_hi_bfreg(struct mlx5_ib_dev *dev,
509 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 510{
511 int med;
c1be5232 512
b037c29a
EC		 513 med = num_med_bfreg(dev, bfregi);
514 return ++med;
c1be5232
EC		 515}
516
b037c29a
EC		 517static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
518 struct mlx5_bfreg_info *bfregi)
e126ba97 519{
e126ba97
EC		 520 int i;
521
b037c29a
EC		 522 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
523 if (!bfregi->count[i]) {
2f5ff264 524 bfregi->count[i]++;
e126ba97
EC		 525 return i;
526 }
527 }
528
529 return -ENOMEM;
530}
531
b037c29a
EC		 532static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
533 struct mlx5_bfreg_info *bfregi)
e126ba97 534{
2f5ff264 535 int minidx = first_med_bfreg();
e126ba97
EC		 536 int i;
537
b037c29a 538 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 539 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 540 minidx = i;
0b80c14f
EC		 541 if (!bfregi->count[minidx])
542 break;
e126ba97
EC		 543 }
544
2f5ff264 545 bfregi->count[minidx]++;
e126ba97
EC		 546 return minidx;
547}
548
b037c29a
EC		 549static int alloc_bfreg(struct mlx5_ib_dev *dev,
550 struct mlx5_bfreg_info *bfregi,
2f5ff264 551 enum mlx5_ib_latency_class lat)
e126ba97 552{
2f5ff264 553 int bfregn = -EINVAL;
e126ba97 554
2f5ff264 555 mutex_lock(&bfregi->lock);
e126ba97
EC		 556 switch (lat) {
557 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 558 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 559 bfregn = 0;
560 bfregi->count[bfregn]++;
e126ba97
EC		 561 break;
562
563 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 564 if (bfregi->ver < 2)
565 bfregn = -ENOMEM;
78c0f98c 566 else
b037c29a 567 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 568 break;
569
570 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 571 if (bfregi->ver < 2)
572 bfregn = -ENOMEM;
78c0f98c 573 else
b037c29a 574 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 575 break;
576 }
2f5ff264 577 mutex_unlock(&bfregi->lock);
e126ba97 578
2f5ff264 579 return bfregn;
e126ba97
EC		 580}
581
b037c29a 582static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 583{
2f5ff264 584 mutex_lock(&bfregi->lock);
b037c29a 585 bfregi->count[bfregn]--;
2f5ff264 586 mutex_unlock(&bfregi->lock);
e126ba97
EC		 587}
588
589static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
590{
591 switch (state) {
592 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
593 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
594 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
595 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
596 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
597 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
598 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
599 default: return -1;
600 }
601}
602
603static int to_mlx5_st(enum ib_qp_type type)
604{
605 switch (type) {
606 case IB_QPT_RC: return MLX5_QP_ST_RC;
607 case IB_QPT_UC: return MLX5_QP_ST_UC;
608 case IB_QPT_UD: return MLX5_QP_ST_UD;
609 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
610 case IB_QPT_XRC_INI:
611 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
612 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 613 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 614 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 615 case IB_QPT_RAW_PACKET:
0fb2ed66 616 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 617 case IB_QPT_MAX:
618 default: return -EINVAL;
619 }
620}
621
89ea94a7
MG		 622static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
623 struct mlx5_ib_cq *recv_cq);
624static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626
b037c29a
EC		 627static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
628 struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 629{
b037c29a
EC		 630 int bfregs_per_sys_page;
631 int index_of_sys_page;
632 int offset;
633
634 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
635 MLX5_NON_FP_BFREGS_PER_UAR;
636 index_of_sys_page = bfregn / bfregs_per_sys_page;
637
638 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
639
640 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 641}
642
19098df2 643static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
644 struct ib_pd *pd,
645 unsigned long addr, size_t size,
646 struct ib_umem **umem,
647 int *npages, int *page_shift, int *ncont,
648 u32 *offset)
649{
650 int err;
651
652 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
653 if (IS_ERR(*umem)) {
654 mlx5_ib_dbg(dev, "umem_get failed\n");
655 return PTR_ERR(*umem);
656 }
657
762f899a 658 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 659
660 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
661 if (err) {
662 mlx5_ib_warn(dev, "bad offset\n");
663 goto err_umem;
664 }
665
666 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
667 addr, size, *npages, *page_shift, *ncont, *offset);
668
669 return 0;
670
671err_umem:
672 ib_umem_release(*umem);
673 *umem = NULL;
674
675 return err;
676}
677
79b20a6c
YH		 678static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
679{
680 struct mlx5_ib_ucontext *context;
681
682 context = to_mucontext(pd->uobject->context);
683 mlx5_ib_db_unmap_user(context, &rwq->db);
684 if (rwq->umem)
685 ib_umem_release(rwq->umem);
686}
687
688static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
689 struct mlx5_ib_rwq *rwq,
690 struct mlx5_ib_create_wq *ucmd)
691{
692 struct mlx5_ib_ucontext *context;
693 int page_shift = 0;
694 int npages;
695 u32 offset = 0;
696 int ncont = 0;
697 int err;
698
699 if (!ucmd->buf_addr)
700 return -EINVAL;
701
702 context = to_mucontext(pd->uobject->context);
703 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
704 rwq->buf_size, 0, 0);
705 if (IS_ERR(rwq->umem)) {
706 mlx5_ib_dbg(dev, "umem_get failed\n");
707 err = PTR_ERR(rwq->umem);
708 return err;
709 }
710
762f899a 711 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 712 &ncont, NULL);
713 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
714 &rwq->rq_page_offset);
715 if (err) {
716 mlx5_ib_warn(dev, "bad offset\n");
717 goto err_umem;
718 }
719
720 rwq->rq_num_pas = ncont;
721 rwq->page_shift = page_shift;
722 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
723 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
724
725 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
726 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
727 npages, page_shift, ncont, offset);
728
729 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
730 if (err) {
731 mlx5_ib_dbg(dev, "map failed\n");
732 goto err_umem;
733 }
734
735 rwq->create_type = MLX5_WQ_USER;
736 return 0;
737
738err_umem:
739 ib_umem_release(rwq->umem);
740 return err;
741}
742
b037c29a
EC		 743static int adjust_bfregn(struct mlx5_ib_dev *dev,
744 struct mlx5_bfreg_info *bfregi, int bfregn)
745{
746 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
747 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
748}
749
e126ba97
EC		 750static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
751 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 752 struct ib_qp_init_attr *attr,
09a7d9ec 753 u32 **in,
19098df2 754 struct mlx5_ib_create_qp_resp *resp, int *inlen,
755 struct mlx5_ib_qp_base *base)
e126ba97
EC		 756{
757 struct mlx5_ib_ucontext *context;
758 struct mlx5_ib_create_qp ucmd;
19098df2 759 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 760 int page_shift = 0;
e126ba97
EC		 761 int uar_index;
762 int npages;
9e9c47d0 763 u32 offset = 0;
2f5ff264 764 int bfregn;
9e9c47d0 765 int ncont = 0;
09a7d9ec
SM		 766 __be64 *pas;
767 void *qpc;
e126ba97
EC		 768 int err;
769
770 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
771 if (err) {
772 mlx5_ib_dbg(dev, "copy failed\n");
773 return err;
774 }
775
776 context = to_mucontext(pd->uobject->context);
777 /*
778 * TBD: should come from the verbs when we have the API
779 */
051f2630
LR		 780 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
781 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 782 bfregn = MLX5_CROSS_CHANNEL_BFREG;
051f2630 783 else {
b037c29a 784 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 785 if (bfregn < 0) {
786 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 787 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 788 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 789 if (bfregn < 0) {
790 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 791 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 792 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 793 if (bfregn < 0) {
794 mlx5_ib_warn(dev, "bfreg allocation failed\n");
795 return bfregn;
051f2630 796 }
c1be5232 797 }
e126ba97
EC		 798 }
799 }
800
b037c29a 801 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
2f5ff264 802 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
e126ba97 803
48fea837
HE		 804 qp->rq.offset = 0;
805 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
806 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
807
0fb2ed66 808 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 809 if (err)
2f5ff264 810 goto err_bfreg;
e126ba97 811
19098df2 812 if (ucmd.buf_addr && ubuffer->buf_size) {
813 ubuffer->buf_addr = ucmd.buf_addr;
814 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
815 ubuffer->buf_size,
816 &ubuffer->umem, &npages, &page_shift,
817 &ncont, &offset);
818 if (err)
2f5ff264 819 goto err_bfreg;
9e9c47d0 820 } else {
19098df2 821 ubuffer->umem = NULL;
e126ba97 822 }
e126ba97 823
09a7d9ec
SM		 824 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
825 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 826 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 827 if (!*in) {
828 err = -ENOMEM;
829 goto err_umem;
830 }
09a7d9ec
SM		 831
832 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 833 if (ubuffer->umem)
09a7d9ec
SM		 834 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
835
836 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
837
838 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
839 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 840
09a7d9ec 841 MLX5_SET(qpc, qpc, uar_page, uar_index);
b037c29a 842 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
2f5ff264 843 qp->bfregn = bfregn;
e126ba97
EC		 844
845 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
846 if (err) {
847 mlx5_ib_dbg(dev, "map failed\n");
848 goto err_free;
849 }
850
851 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
852 if (err) {
853 mlx5_ib_dbg(dev, "copy failed\n");
854 goto err_unmap;
855 }
856 qp->create_type = MLX5_QP_USER;
857
858 return 0;
859
860err_unmap:
861 mlx5_ib_db_unmap_user(context, &qp->db);
862
863err_free:
479163f4 864 kvfree(*in);
e126ba97
EC		 865
866err_umem:
19098df2 867 if (ubuffer->umem)
868 ib_umem_release(ubuffer->umem);
e126ba97 869
2f5ff264 870err_bfreg:
b037c29a 871 free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 872 return err;
873}
874
b037c29a
EC		 875static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
876 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 877{
878 struct mlx5_ib_ucontext *context;
879
880 context = to_mucontext(pd->uobject->context);
881 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 882 if (base->ubuffer.umem)
883 ib_umem_release(base->ubuffer.umem);
b037c29a 884 free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 885}
886
887static int create_kernel_qp(struct mlx5_ib_dev *dev,
888 struct ib_qp_init_attr *init_attr,
889 struct mlx5_ib_qp *qp,
09a7d9ec 890 u32 **in, int *inlen,
19098df2 891 struct mlx5_ib_qp_base *base)
e126ba97 892{
e126ba97 893 int uar_index;
09a7d9ec 894 void *qpc;
e126ba97
EC		 895 int err;
896
f0313965
ES		 897 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
898 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 899 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 900 IB_QP_CREATE_NETIF_QP |
b11a4f9c 901 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 902 return -EINVAL;
e126ba97
EC		 903
904 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 905 qp->bf.bfreg = &dev->fp_bfreg;
906 else
907 qp->bf.bfreg = &dev->bfreg;
e126ba97 908
d8030b0d
EC		 909 /* We need to divide by two since each register is comprised of
910 * two buffers of identical size, namely odd and even
911 */
912 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 913 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 914
915 err = calc_sq_size(dev, init_attr, qp);
916 if (err < 0) {
917 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 918 return err;
e126ba97
EC		 919 }
920
921 qp->rq.offset = 0;
922 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 923 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 924
19098df2 925 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 926 if (err) {
927 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 928 return err;
e126ba97
EC		 929 }
930
931 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 932 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
933 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 934 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 935 if (!*in) {
936 err = -ENOMEM;
937 goto err_buf;
938 }
09a7d9ec
SM		 939
940 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
941 MLX5_SET(qpc, qpc, uar_page, uar_index);
942 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
943
e126ba97 944 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 945 MLX5_SET(qpc, qpc, fre, 1);
946 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 947
b11a4f9c 948 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 949 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 950 qp->flags |= MLX5_IB_QP_SQPN_QP1;
951 }
952
09a7d9ec
SM		 953 mlx5_fill_page_array(&qp->buf,
954 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 955
9603b61d 956 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 957 if (err) {
958 mlx5_ib_dbg(dev, "err %d\n", err);
959 goto err_free;
960 }
961
e126ba97
EC		 962 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
963 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
964 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
965 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
966 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
967
968 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
969 !qp->sq.w_list || !qp->sq.wqe_head) {
970 err = -ENOMEM;
971 goto err_wrid;
972 }
973 qp->create_type = MLX5_QP_KERNEL;
974
975 return 0;
976
977err_wrid:
e126ba97
EC		 978 kfree(qp->sq.wqe_head);
979 kfree(qp->sq.w_list);
980 kfree(qp->sq.wrid);
981 kfree(qp->sq.wr_data);
982 kfree(qp->rq.wrid);
f4044dac 983 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 984
985err_free:
479163f4 986 kvfree(*in);
e126ba97
EC		 987
988err_buf:
9603b61d 989 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 990 return err;
991}
992
993static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
994{
e126ba97
EC		 995 kfree(qp->sq.wqe_head);
996 kfree(qp->sq.w_list);
997 kfree(qp->sq.wrid);
998 kfree(qp->sq.wr_data);
999 kfree(qp->rq.wrid);
f4044dac 1000 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1001 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1002}
1003
09a7d9ec 1004static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1005{
1006 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1007 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1008 return MLX5_SRQ_RQ;
e126ba97 1009 else if (!qp->has_rq)
09a7d9ec 1010 return MLX5_ZERO_LEN_RQ;
e126ba97 1011 else
09a7d9ec 1012 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1013}
1014
1015static int is_connected(enum ib_qp_type qp_type)
1016{
1017 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1018 return 1;
1019
1020 return 0;
1021}
1022
0fb2ed66 1023static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1024 struct mlx5_ib_sq *sq, u32 tdn)
1025{
c4f287c4 1026 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1027 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1028
0fb2ed66 1029 MLX5_SET(tisc, tisc, transport_domain, tdn);
0fb2ed66 1030 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1031}
1032
1033static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1034 struct mlx5_ib_sq *sq)
1035{
1036 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1037}
1038
1039static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1040 struct mlx5_ib_sq *sq, void *qpin,
1041 struct ib_pd *pd)
1042{
1043 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1044 __be64 *pas;
1045 void *in;
1046 void *sqc;
1047 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1048 void *wq;
1049 int inlen;
1050 int err;
1051 int page_shift = 0;
1052 int npages;
1053 int ncont = 0;
1054 u32 offset = 0;
1055
1056 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1057 &sq->ubuffer.umem, &npages, &page_shift,
1058 &ncont, &offset);
1059 if (err)
1060 return err;
1061
1062 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1063 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1064 if (!in) {
1065 err = -ENOMEM;
1066 goto err_umem;
1067 }
1068
1069 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1070 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1071 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1072 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1073 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1074 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1075 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1076
1077 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1078 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1079 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1080 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1081 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1082 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1083 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1084 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1085 MLX5_SET(wq, wq, page_offset, offset);
1086
1087 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1088 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1089
1090 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1091
1092 kvfree(in);
1093
1094 if (err)
1095 goto err_umem;
1096
1097 return 0;
1098
1099err_umem:
1100 ib_umem_release(sq->ubuffer.umem);
1101 sq->ubuffer.umem = NULL;
1102
1103 return err;
1104}
1105
1106static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1107 struct mlx5_ib_sq *sq)
1108{
1109 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1110 ib_umem_release(sq->ubuffer.umem);
1111}
1112
1113static int get_rq_pas_size(void *qpc)
1114{
1115 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1116 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1117 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1118 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1119 u32 po_quanta = 1 << (log_page_size - 6);
1120 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1121 u32 page_size = 1 << log_page_size;
1122 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1123 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1124
1125 return rq_num_pas * sizeof(u64);
1126}
1127
1128static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1129 struct mlx5_ib_rq *rq, void *qpin)
1130{
358e42ea 1131 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1132 __be64 *pas;
1133 __be64 *qp_pas;
1134 void *in;
1135 void *rqc;
1136 void *wq;
1137 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1138 int inlen;
1139 int err;
1140 u32 rq_pas_size = get_rq_pas_size(qpc);
1141
1142 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1143 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1144 if (!in)
1145 return -ENOMEM;
1146
1147 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1148 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1149 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1150 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1151 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1152 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1153 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1154 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1155
358e42ea
MD		 1156 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1157 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1158
0fb2ed66 1159 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1160 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1161 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1162 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1163 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1164 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1165 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1166 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1167 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1168 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1169
1170 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1171 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1172 memcpy(pas, qp_pas, rq_pas_size);
1173
1174 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1175
1176 kvfree(in);
1177
1178 return err;
1179}
1180
1181static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1182 struct mlx5_ib_rq *rq)
1183{
1184 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1185}
1186
1187static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1188 struct mlx5_ib_rq *rq, u32 tdn)
1189{
1190 u32 *in;
1191 void *tirc;
1192 int inlen;
1193 int err;
1194
1195 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1196 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1197 if (!in)
1198 return -ENOMEM;
1199
1200 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1201 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1202 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1203 MLX5_SET(tirc, tirc, transport_domain, tdn);
1204
1205 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1206
1207 kvfree(in);
1208
1209 return err;
1210}
1211
1212static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1213 struct mlx5_ib_rq *rq)
1214{
1215 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1216}
1217
1218static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1219 u32 *in,
0fb2ed66 1220 struct ib_pd *pd)
1221{
1222 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1223 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1224 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1225 struct ib_uobject *uobj = pd->uobject;
1226 struct ib_ucontext *ucontext = uobj->context;
1227 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1228 int err;
1229 u32 tdn = mucontext->tdn;
1230
1231 if (qp->sq.wqe_cnt) {
1232 err = create_raw_packet_qp_tis(dev, sq, tdn);
1233 if (err)
1234 return err;
1235
1236 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1237 if (err)
1238 goto err_destroy_tis;
1239
1240 sq->base.container_mibqp = qp;
1d31e9c0 1241 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1242 }
1243
1244 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1245 rq->base.container_mibqp = qp;
1246
e4cc4fa7
NO		 1247 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1248 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
0fb2ed66 1249 err = create_raw_packet_qp_rq(dev, rq, in);
1250 if (err)
1251 goto err_destroy_sq;
1252
0fb2ed66 1253
1254 err = create_raw_packet_qp_tir(dev, rq, tdn);
1255 if (err)
1256 goto err_destroy_rq;
1257 }
1258
1259 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1260 rq->base.mqp.qpn;
1261
1262 return 0;
1263
1264err_destroy_rq:
1265 destroy_raw_packet_qp_rq(dev, rq);
1266err_destroy_sq:
1267 if (!qp->sq.wqe_cnt)
1268 return err;
1269 destroy_raw_packet_qp_sq(dev, sq);
1270err_destroy_tis:
1271 destroy_raw_packet_qp_tis(dev, sq);
1272
1273 return err;
1274}
1275
1276static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1277 struct mlx5_ib_qp *qp)
1278{
1279 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1280 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1281 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1282
1283 if (qp->rq.wqe_cnt) {
1284 destroy_raw_packet_qp_tir(dev, rq);
1285 destroy_raw_packet_qp_rq(dev, rq);
1286 }
1287
1288 if (qp->sq.wqe_cnt) {
1289 destroy_raw_packet_qp_sq(dev, sq);
1290 destroy_raw_packet_qp_tis(dev, sq);
1291 }
1292}
1293
1294static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1295 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1296{
1297 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1298 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1299
1300 sq->sq = &qp->sq;
1301 rq->rq = &qp->rq;
1302 sq->doorbell = &qp->db;
1303 rq->doorbell = &qp->db;
1304}
1305
28d61370
YH		 1306static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1307{
1308 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1309}
1310
1311static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1312 struct ib_pd *pd,
1313 struct ib_qp_init_attr *init_attr,
1314 struct ib_udata *udata)
1315{
1316 struct ib_uobject *uobj = pd->uobject;
1317 struct ib_ucontext *ucontext = uobj->context;
1318 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1319 struct mlx5_ib_create_qp_resp resp = {};
1320 int inlen;
1321 int err;
1322 u32 *in;
1323 void *tirc;
1324 void *hfso;
1325 u32 selected_fields = 0;
1326 size_t min_resp_len;
1327 u32 tdn = mucontext->tdn;
1328 struct mlx5_ib_create_qp_rss ucmd = {};
1329 size_t required_cmd_sz;
1330
1331 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1332 return -EOPNOTSUPP;
1333
1334 if (init_attr->create_flags || init_attr->send_cq)
1335 return -EINVAL;
1336
2f5ff264 1337 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1338 if (udata->outlen < min_resp_len)
1339 return -EINVAL;
1340
1341 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1342 if (udata->inlen < required_cmd_sz) {
1343 mlx5_ib_dbg(dev, "invalid inlen\n");
1344 return -EINVAL;
1345 }
1346
1347 if (udata->inlen > sizeof(ucmd) &&
1348 !ib_is_udata_cleared(udata, sizeof(ucmd),
1349 udata->inlen - sizeof(ucmd))) {
1350 mlx5_ib_dbg(dev, "inlen is not supported\n");
1351 return -EOPNOTSUPP;
1352 }
1353
1354 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1355 mlx5_ib_dbg(dev, "copy failed\n");
1356 return -EFAULT;
1357 }
1358
1359 if (ucmd.comp_mask) {
1360 mlx5_ib_dbg(dev, "invalid comp mask\n");
1361 return -EOPNOTSUPP;
1362 }
1363
1364 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1365 mlx5_ib_dbg(dev, "invalid reserved\n");
1366 return -EOPNOTSUPP;
1367 }
1368
1369 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1370 if (err) {
1371 mlx5_ib_dbg(dev, "copy failed\n");
1372 return -EINVAL;
1373 }
1374
1375 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1376 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1377 if (!in)
1378 return -ENOMEM;
1379
1380 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1381 MLX5_SET(tirc, tirc, disp_type,
1382 MLX5_TIRC_DISP_TYPE_INDIRECT);
1383 MLX5_SET(tirc, tirc, indirect_table,
1384 init_attr->rwq_ind_tbl->ind_tbl_num);
1385 MLX5_SET(tirc, tirc, transport_domain, tdn);
1386
1387 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1388 switch (ucmd.rx_hash_function) {
1389 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1390 {
1391 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1392 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1393
1394 if (len != ucmd.rx_key_len) {
1395 err = -EINVAL;
1396 goto err;
1397 }
1398
1399 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1400 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1401 memcpy(rss_key, ucmd.rx_hash_key, len);
1402 break;
1403 }
1404 default:
1405 err = -EOPNOTSUPP;
1406 goto err;
1407 }
1408
1409 if (!ucmd.rx_hash_fields_mask) {
1410 /* special case when this TIR serves as steering entry without hashing */
1411 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1412 goto create_tir;
1413 err = -EINVAL;
1414 goto err;
1415 }
1416
1417 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1418 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1419 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1420 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1421 err = -EINVAL;
1422 goto err;
1423 }
1424
1425 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1426 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1427 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1428 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1429 MLX5_L3_PROT_TYPE_IPV4);
1430 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1431 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1432 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1433 MLX5_L3_PROT_TYPE_IPV6);
1434
1435 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1436 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1437 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1439 err = -EINVAL;
1440 goto err;
1441 }
1442
1443 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1444 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1445 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1446 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1447 MLX5_L4_PROT_TYPE_TCP);
1448 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1449 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1450 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1451 MLX5_L4_PROT_TYPE_UDP);
1452
1453 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1454 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1455 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1456
1457 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1458 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1459 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1460
1461 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1462 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1463 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1464
1465 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1466 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1467 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1468
1469 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1470
1471create_tir:
1472 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1473
1474 if (err)
1475 goto err;
1476
1477 kvfree(in);
1478 /* qpn is reserved for that QP */
1479 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1480 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1481 return 0;
1482
1483err:
1484 kvfree(in);
1485 return err;
1486}
1487
e126ba97
EC		 1488static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1489 struct ib_qp_init_attr *init_attr,
1490 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1491{
1492 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1493 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1494 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1495 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1496 struct mlx5_ib_cq *send_cq;
1497 struct mlx5_ib_cq *recv_cq;
1498 unsigned long flags;
cfb5e088 1499 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1500 struct mlx5_ib_create_qp ucmd;
1501 struct mlx5_ib_qp_base *base;
cfb5e088 1502 void *qpc;
09a7d9ec
SM		 1503 u32 *in;
1504 int err;
e126ba97 1505
0fb2ed66 1506 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1507 &qp->raw_packet_qp.rq.base :
1508 &qp->trans_qp.base;
1509
e126ba97
EC		 1510 mutex_init(&qp->mutex);
1511 spin_lock_init(&qp->sq.lock);
1512 spin_lock_init(&qp->rq.lock);
1513
28d61370
YH		 1514 if (init_attr->rwq_ind_tbl) {
1515 if (!udata)
1516 return -ENOSYS;
1517
1518 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1519 return err;
1520 }
1521
f360d88a 1522 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1523 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1524 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1525 return -EINVAL;
1526 } else {
1527 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1528 }
1529 }
1530
051f2630
LR		 1531 if (init_attr->create_flags &
1532 (IB_QP_CREATE_CROSS_CHANNEL |
1533 IB_QP_CREATE_MANAGED_SEND |
1534 IB_QP_CREATE_MANAGED_RECV)) {
1535 if (!MLX5_CAP_GEN(mdev, cd)) {
1536 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1537 return -EINVAL;
1538 }
1539 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1540 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1541 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1542 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1543 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1544 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1545 }
f0313965
ES		 1546
1547 if (init_attr->qp_type == IB_QPT_UD &&
1548 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1549 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1550 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1551 return -EOPNOTSUPP;
1552 }
1553
358e42ea
MD		 1554 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1555 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1556 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1557 return -EOPNOTSUPP;
1558 }
1559 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1560 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1561 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1562 return -EOPNOTSUPP;
1563 }
1564 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1565 }
1566
e126ba97
EC		 1567 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1568 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1569
e4cc4fa7
NO		 1570 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1571 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1572 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1573 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1574 return -EOPNOTSUPP;
1575 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1576 }
1577
e126ba97
EC		 1578 if (pd && pd->uobject) {
1579 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1580 mlx5_ib_dbg(dev, "copy failed\n");
1581 return -EFAULT;
1582 }
1583
cfb5e088
HA		 1584 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1585 &ucmd, udata->inlen, &uidx);
1586 if (err)
1587 return err;
1588
e126ba97
EC		 1589 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1590 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1591 } else {
1592 qp->wq_sig = !!wq_signature;
1593 }
1594
1595 qp->has_rq = qp_has_rq(init_attr);
1596 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1597 qp, (pd && pd->uobject) ? &ucmd : NULL);
1598 if (err) {
1599 mlx5_ib_dbg(dev, "err %d\n", err);
1600 return err;
1601 }
1602
1603 if (pd) {
1604 if (pd->uobject) {
938fe83c
SM		 1605 __u32 max_wqes =
1606 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1607 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1608 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1609 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1610 mlx5_ib_dbg(dev, "invalid rq params\n");
1611 return -EINVAL;
1612 }
938fe83c 1613 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1614 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1615 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1616 return -EINVAL;
1617 }
b11a4f9c
HE		 1618 if (init_attr->create_flags &
1619 mlx5_ib_create_qp_sqpn_qp1()) {
1620 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1621 return -EINVAL;
1622 }
0fb2ed66 1623 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1624 &resp, &inlen, base);
e126ba97
EC		 1625 if (err)
1626 mlx5_ib_dbg(dev, "err %d\n", err);
1627 } else {
19098df2 1628 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1629 base);
e126ba97
EC		 1630 if (err)
1631 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1632 }
1633
1634 if (err)
1635 return err;
1636 } else {
1b9a07ee 1637 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1638 if (!in)
1639 return -ENOMEM;
1640
1641 qp->create_type = MLX5_QP_EMPTY;
1642 }
1643
1644 if (is_sqp(init_attr->qp_type))
1645 qp->port = init_attr->port_num;
1646
09a7d9ec
SM		 1647 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1648
1649 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1650 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1651
1652 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1653 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1654 else
09a7d9ec
SM		 1655 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1656
e126ba97
EC		 1657
1658 if (qp->wq_sig)
09a7d9ec 1659 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1660
f360d88a 1661 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1662 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1663
051f2630 1664 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1665 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1666 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1667 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1668 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1669 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1670
e126ba97
EC		 1671 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1672 int rcqe_sz;
1673 int scqe_sz;
1674
1675 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1676 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1677
1678 if (rcqe_sz == 128)
09a7d9ec 1679 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1680 else
09a7d9ec 1681 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1682
1683 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1684 if (scqe_sz == 128)
09a7d9ec 1685 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1686 else
09a7d9ec 1687 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1688 }
1689 }
1690
1691 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1692 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1693 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1694 }
1695
09a7d9ec 1696 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97
EC		 1697
1698 if (qp->sq.wqe_cnt)
09a7d9ec 1699 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
e126ba97 1700 else
09a7d9ec 1701 MLX5_SET(qpc, qpc, no_sq, 1);
e126ba97
EC		 1702
1703 /* Set default resources */
1704 switch (init_attr->qp_type) {
1705 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1706 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1707 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1708 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1709 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1710 break;
1711 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1712 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1713 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1714 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1715 break;
1716 default:
1717 if (init_attr->srq) {
09a7d9ec
SM		 1718 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1719 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1720 } else {
09a7d9ec
SM		 1721 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1722 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1723 }
1724 }
1725
1726 if (init_attr->send_cq)
09a7d9ec 1727 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1728
1729 if (init_attr->recv_cq)
09a7d9ec 1730 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1731
09a7d9ec 1732 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1733
09a7d9ec
SM		 1734 /* 0xffffff means we ask to work with cqe version 0 */
1735 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1736 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1737
f0313965
ES		 1738 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1739 if (init_attr->qp_type == IB_QPT_UD &&
1740 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1741 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1742 qp->flags |= MLX5_IB_QP_LSO;
1743 }
cfb5e088 1744
0fb2ed66 1745 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1746 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1747 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1748 err = create_raw_packet_qp(dev, qp, in, pd);
1749 } else {
1750 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1751 }
1752
e126ba97
EC		 1753 if (err) {
1754 mlx5_ib_dbg(dev, "create qp failed\n");
1755 goto err_create;
1756 }
1757
479163f4 1758 kvfree(in);
e126ba97 1759
19098df2 1760 base->container_mibqp = qp;
1761 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1762
89ea94a7
MG		 1763 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1764 &send_cq, &recv_cq);
1765 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1766 mlx5_ib_lock_cqs(send_cq, recv_cq);
1767 /* Maintain device to QPs access, needed for further handling via reset
1768 * flow
1769 */
1770 list_add_tail(&qp->qps_list, &dev->qp_list);
1771 /* Maintain CQ to QPs access, needed for further handling via reset flow
1772 */
1773 if (send_cq)
1774 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1775 if (recv_cq)
1776 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1777 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1778 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1779
e126ba97
EC		 1780 return 0;
1781
1782err_create:
1783 if (qp->create_type == MLX5_QP_USER)
b037c29a 1784 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1785 else if (qp->create_type == MLX5_QP_KERNEL)
1786 destroy_qp_kernel(dev, qp);
1787
479163f4 1788 kvfree(in);
e126ba97
EC		 1789 return err;
1790}
1791
1792static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1793 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1794{
1795 if (send_cq) {
1796 if (recv_cq) {
1797 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1798 spin_lock(&send_cq->lock);
e126ba97
EC		 1799 spin_lock_nested(&recv_cq->lock,
1800 SINGLE_DEPTH_NESTING);
1801 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1802 spin_lock(&send_cq->lock);
e126ba97
EC		 1803 __acquire(&recv_cq->lock);
1804 } else {
89ea94a7 1805 spin_lock(&recv_cq->lock);
e126ba97
EC		 1806 spin_lock_nested(&send_cq->lock,
1807 SINGLE_DEPTH_NESTING);
1808 }
1809 } else {
89ea94a7 1810 spin_lock(&send_cq->lock);
6a4f139a 1811 __acquire(&recv_cq->lock);
e126ba97
EC		 1812 }
1813 } else if (recv_cq) {
89ea94a7 1814 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1815 __acquire(&send_cq->lock);
1816 } else {
1817 __acquire(&send_cq->lock);
1818 __acquire(&recv_cq->lock);
e126ba97
EC		 1819 }
1820}
1821
1822static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1823 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1824{
1825 if (send_cq) {
1826 if (recv_cq) {
1827 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1828 spin_unlock(&recv_cq->lock);
89ea94a7 1829 spin_unlock(&send_cq->lock);
e126ba97
EC		 1830 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1831 __release(&recv_cq->lock);
89ea94a7 1832 spin_unlock(&send_cq->lock);
e126ba97
EC		 1833 } else {
1834 spin_unlock(&send_cq->lock);
89ea94a7 1835 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1836 }
1837 } else {
6a4f139a 1838 __release(&recv_cq->lock);
89ea94a7 1839 spin_unlock(&send_cq->lock);
e126ba97
EC		 1840 }
1841 } else if (recv_cq) {
6a4f139a 1842 __release(&send_cq->lock);
89ea94a7 1843 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1844 } else {
1845 __release(&recv_cq->lock);
1846 __release(&send_cq->lock);
e126ba97
EC		 1847 }
1848}
1849
1850static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1851{
1852 return to_mpd(qp->ibqp.pd);
1853}
1854
89ea94a7
MG		 1855static void get_cqs(enum ib_qp_type qp_type,
1856 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1857 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1858{
89ea94a7 1859 switch (qp_type) {
e126ba97
EC		 1860 case IB_QPT_XRC_TGT:
1861 *send_cq = NULL;
1862 *recv_cq = NULL;
1863 break;
1864 case MLX5_IB_QPT_REG_UMR:
1865 case IB_QPT_XRC_INI:
89ea94a7 1866 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1867 *recv_cq = NULL;
1868 break;
1869
1870 case IB_QPT_SMI:
d16e91da 1871 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1872 case IB_QPT_RC:
1873 case IB_QPT_UC:
1874 case IB_QPT_UD:
1875 case IB_QPT_RAW_IPV6:
1876 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1877 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1878 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1879 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1880 break;
1881
e126ba97
EC		 1882 case IB_QPT_MAX:
1883 default:
1884 *send_cq = NULL;
1885 *recv_cq = NULL;
1886 break;
1887 }
1888}
1889
ad5f8e96 1890static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 1891 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1892 u8 lag_tx_affinity);
ad5f8e96 1893
e126ba97
EC		 1894static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1895{
1896 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1897 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
89ea94a7 1898 unsigned long flags;
e126ba97
EC		 1899 int err;
1900
28d61370
YH		 1901 if (qp->ibqp.rwq_ind_tbl) {
1902 destroy_rss_raw_qp_tir(dev, qp);
1903 return;
1904 }
1905
0fb2ed66 1906 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1907 &qp->raw_packet_qp.rq.base :
1908 &qp->trans_qp.base;
1909
6aec21f6 1910 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1911 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
ad5f8e96 1912 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1913 MLX5_CMD_OP_2RST_QP, 0,
1914 NULL, &base->mqp);
ad5f8e96 1915 } else {
0680efa2
AV		 1916 struct mlx5_modify_raw_qp_param raw_qp_param = {
1917 .operation = MLX5_CMD_OP_2RST_QP
1918 };
1919
13eab21f 1920 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 1921 }
1922 if (err)
427c1e7b 1923 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1924 base->mqp.qpn);
6aec21f6 1925 }
e126ba97 1926
89ea94a7
MG		 1927 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1928 &send_cq, &recv_cq);
1929
1930 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1931 mlx5_ib_lock_cqs(send_cq, recv_cq);
1932 /* del from lists under both locks above to protect reset flow paths */
1933 list_del(&qp->qps_list);
1934 if (send_cq)
1935 list_del(&qp->cq_send_list);
1936
1937 if (recv_cq)
1938 list_del(&qp->cq_recv_list);
e126ba97
EC		 1939
1940 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1941 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1942 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1943 if (send_cq != recv_cq)
19098df2 1944 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1945 NULL);
e126ba97 1946 }
89ea94a7
MG		 1947 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1948 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1949
0fb2ed66 1950 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1951 destroy_raw_packet_qp(dev, qp);
1952 } else {
1953 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1954 if (err)
1955 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1956 base->mqp.qpn);
1957 }
e126ba97 1958
e126ba97
EC		 1959 if (qp->create_type == MLX5_QP_KERNEL)
1960 destroy_qp_kernel(dev, qp);
1961 else if (qp->create_type == MLX5_QP_USER)
b037c29a 1962 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1963}
1964
1965static const char *ib_qp_type_str(enum ib_qp_type type)
1966{
1967 switch (type) {
1968 case IB_QPT_SMI:
1969 return "IB_QPT_SMI";
1970 case IB_QPT_GSI:
1971 return "IB_QPT_GSI";
1972 case IB_QPT_RC:
1973 return "IB_QPT_RC";
1974 case IB_QPT_UC:
1975 return "IB_QPT_UC";
1976 case IB_QPT_UD:
1977 return "IB_QPT_UD";
1978 case IB_QPT_RAW_IPV6:
1979 return "IB_QPT_RAW_IPV6";
1980 case IB_QPT_RAW_ETHERTYPE:
1981 return "IB_QPT_RAW_ETHERTYPE";
1982 case IB_QPT_XRC_INI:
1983 return "IB_QPT_XRC_INI";
1984 case IB_QPT_XRC_TGT:
1985 return "IB_QPT_XRC_TGT";
1986 case IB_QPT_RAW_PACKET:
1987 return "IB_QPT_RAW_PACKET";
1988 case MLX5_IB_QPT_REG_UMR:
1989 return "MLX5_IB_QPT_REG_UMR";
1990 case IB_QPT_MAX:
1991 default:
1992 return "Invalid QP type";
1993 }
1994}
1995
1996struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1997 struct ib_qp_init_attr *init_attr,
1998 struct ib_udata *udata)
1999{
2000 struct mlx5_ib_dev *dev;
2001 struct mlx5_ib_qp *qp;
2002 u16 xrcdn = 0;
2003 int err;
2004
2005 if (pd) {
2006 dev = to_mdev(pd->device);
0fb2ed66 2007
2008 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2009 if (!pd->uobject) {
2010 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2011 return ERR_PTR(-EINVAL);
2012 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2013 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2014 return ERR_PTR(-EINVAL);
2015 }
2016 }
09f16cf5
MD		 2017 } else {
2018 /* being cautious here */
2019 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2020 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2021 pr_warn("%s: no PD for transport %s\n", __func__,
2022 ib_qp_type_str(init_attr->qp_type));
2023 return ERR_PTR(-EINVAL);
2024 }
2025 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2026 }
2027
2028 switch (init_attr->qp_type) {
2029 case IB_QPT_XRC_TGT:
2030 case IB_QPT_XRC_INI:
938fe83c 2031 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2032 mlx5_ib_dbg(dev, "XRC not supported\n");
2033 return ERR_PTR(-ENOSYS);
2034 }
2035 init_attr->recv_cq = NULL;
2036 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2037 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2038 init_attr->send_cq = NULL;
2039 }
2040
2041 /* fall through */
0fb2ed66 2042 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2043 case IB_QPT_RC:
2044 case IB_QPT_UC:
2045 case IB_QPT_UD:
2046 case IB_QPT_SMI:
d16e91da 2047 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2048 case MLX5_IB_QPT_REG_UMR:
2049 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2050 if (!qp)
2051 return ERR_PTR(-ENOMEM);
2052
2053 err = create_qp_common(dev, pd, init_attr, udata, qp);
2054 if (err) {
2055 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2056 kfree(qp);
2057 return ERR_PTR(err);
2058 }
2059
2060 if (is_qp0(init_attr->qp_type))
2061 qp->ibqp.qp_num = 0;
2062 else if (is_qp1(init_attr->qp_type))
2063 qp->ibqp.qp_num = 1;
2064 else
19098df2 2065 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2066
2067 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2068 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2069 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2070 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2071
19098df2 2072 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2073
2074 break;
2075
d16e91da
HE		 2076 case IB_QPT_GSI:
2077 return mlx5_ib_gsi_create_qp(pd, init_attr);
2078
e126ba97
EC		 2079 case IB_QPT_RAW_IPV6:
2080 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2081 case IB_QPT_MAX:
2082 default:
2083 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2084 init_attr->qp_type);
2085 /* Don't support raw QPs */
2086 return ERR_PTR(-EINVAL);
2087 }
2088
2089 return &qp->ibqp;
2090}
2091
2092int mlx5_ib_destroy_qp(struct ib_qp *qp)
2093{
2094 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2095 struct mlx5_ib_qp *mqp = to_mqp(qp);
2096
d16e91da
HE		 2097 if (unlikely(qp->qp_type == IB_QPT_GSI))
2098 return mlx5_ib_gsi_destroy_qp(qp);
2099
e126ba97
EC		 2100 destroy_qp_common(dev, mqp);
2101
2102 kfree(mqp);
2103
2104 return 0;
2105}
2106
2107static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2108 int attr_mask)
2109{
2110 u32 hw_access_flags = 0;
2111 u8 dest_rd_atomic;
2112 u32 access_flags;
2113
2114 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2115 dest_rd_atomic = attr->max_dest_rd_atomic;
2116 else
19098df2 2117 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2118
2119 if (attr_mask & IB_QP_ACCESS_FLAGS)
2120 access_flags = attr->qp_access_flags;
2121 else
19098df2 2122 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2123
2124 if (!dest_rd_atomic)
2125 access_flags &= IB_ACCESS_REMOTE_WRITE;
2126
2127 if (access_flags & IB_ACCESS_REMOTE_READ)
2128 hw_access_flags |= MLX5_QP_BIT_RRE;
2129 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2130 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2131 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2132 hw_access_flags |= MLX5_QP_BIT_RWE;
2133
2134 return cpu_to_be32(hw_access_flags);
2135}
2136
2137enum {
2138 MLX5_PATH_FLAG_FL = 1 << 0,
2139 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2140 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2141};
2142
2143static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2144{
2145 if (rate == IB_RATE_PORT_CURRENT) {
2146 return 0;
2147 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2148 return -EINVAL;
2149 } else {
2150 while (rate != IB_RATE_2_5_GBPS &&
2151 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2152 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2153 --rate;
2154 }
2155
2156 return rate + MLX5_STAT_RATE_OFFSET;
2157}
2158
75850d0b 2159static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2160 struct mlx5_ib_sq *sq, u8 sl)
2161{
2162 void *in;
2163 void *tisc;
2164 int inlen;
2165 int err;
2166
2167 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2168 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2169 if (!in)
2170 return -ENOMEM;
2171
2172 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2173
2174 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2175 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2176
2177 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2178
2179 kvfree(in);
2180
2181 return err;
2182}
2183
13eab21f
AH		 2184static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2185 struct mlx5_ib_sq *sq, u8 tx_affinity)
2186{
2187 void *in;
2188 void *tisc;
2189 int inlen;
2190 int err;
2191
2192 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2193 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2194 if (!in)
2195 return -ENOMEM;
2196
2197 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2198
2199 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2200 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2201
2202 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2203
2204 kvfree(in);
2205
2206 return err;
2207}
2208
75850d0b 2209static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2210 const struct rdma_ah_attr *ah,
e126ba97 2211 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2212 u32 path_flags, const struct ib_qp_attr *attr,
2213 bool alt)
e126ba97 2214{
d8966fcd 2215 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2216 int err;
ed88451e 2217 enum ib_gid_type gid_type;
d8966fcd
DC		 2218 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2219 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2220
e126ba97 2221 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2222 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2223 attr->pkey_index);
e126ba97 2224
d8966fcd
DC		 2225 if (ah_flags & IB_AH_GRH) {
2226 if (grh->sgid_index >=
938fe83c 2227 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2228 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2229 grh->sgid_index,
938fe83c 2230 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2231 return -EINVAL;
2232 }
2811ba51 2233 }
44c58487
DC		 2234
2235 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2236 if (!(ah_flags & IB_AH_GRH))
2811ba51 2237 return -EINVAL;
d8966fcd 2238 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
ed88451e
MD		 2239 &gid_type);
2240 if (err)
2241 return err;
44c58487 2242 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2811ba51 2243 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
d8966fcd
DC		 2244 grh->sgid_index);
2245 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
ed88451e 2246 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2247 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2248 } else {
d3ae2bde
NO		 2249 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2250 path->fl_free_ar |=
2251 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2252 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2253 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2254 if (ah_flags & IB_AH_GRH)
2811ba51 2255 path->grh_mlid |= 1 << 7;
d8966fcd 2256 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2257 }
2258
d8966fcd
DC		 2259 if (ah_flags & IB_AH_GRH) {
2260 path->mgid_index = grh->sgid_index;
2261 path->hop_limit = grh->hop_limit;
e126ba97 2262 path->tclass_flowlabel =
d8966fcd
DC		 2263 cpu_to_be32((grh->traffic_class << 20) |
2264 (grh->flow_label));
2265 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2266 }
2267
d8966fcd 2268 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2269 if (err < 0)
2270 return err;
2271 path->static_rate = err;
2272 path->port = port;
2273
e126ba97 2274 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2275 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2276
75850d0b 2277 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2278 return modify_raw_packet_eth_prio(dev->mdev,
2279 &qp->raw_packet_qp.sq,
d8966fcd 2280 sl & 0xf);
75850d0b 2281
e126ba97
EC		 2282 return 0;
2283}
2284
2285static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2286 [MLX5_QP_STATE_INIT] = {
2287 [MLX5_QP_STATE_INIT] = {
2288 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2289 MLX5_QP_OPTPAR_RAE |
2290 MLX5_QP_OPTPAR_RWE |
2291 MLX5_QP_OPTPAR_PKEY_INDEX |
2292 MLX5_QP_OPTPAR_PRI_PORT,
2293 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2294 MLX5_QP_OPTPAR_PKEY_INDEX |
2295 MLX5_QP_OPTPAR_PRI_PORT,
2296 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2297 MLX5_QP_OPTPAR_Q_KEY |
2298 MLX5_QP_OPTPAR_PRI_PORT,
2299 },
2300 [MLX5_QP_STATE_RTR] = {
2301 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2302 MLX5_QP_OPTPAR_RRE |
2303 MLX5_QP_OPTPAR_RAE |
2304 MLX5_QP_OPTPAR_RWE |
2305 MLX5_QP_OPTPAR_PKEY_INDEX,
2306 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2307 MLX5_QP_OPTPAR_RWE |
2308 MLX5_QP_OPTPAR_PKEY_INDEX,
2309 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2310 MLX5_QP_OPTPAR_Q_KEY,
2311 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2312 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2313 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2314 MLX5_QP_OPTPAR_RRE |
2315 MLX5_QP_OPTPAR_RAE |
2316 MLX5_QP_OPTPAR_RWE |
2317 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2318 },
2319 },
2320 [MLX5_QP_STATE_RTR] = {
2321 [MLX5_QP_STATE_RTS] = {
2322 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2323 MLX5_QP_OPTPAR_RRE |
2324 MLX5_QP_OPTPAR_RAE |
2325 MLX5_QP_OPTPAR_RWE |
2326 MLX5_QP_OPTPAR_PM_STATE |
2327 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2328 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2329 MLX5_QP_OPTPAR_RWE |
2330 MLX5_QP_OPTPAR_PM_STATE,
2331 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2332 },
2333 },
2334 [MLX5_QP_STATE_RTS] = {
2335 [MLX5_QP_STATE_RTS] = {
2336 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2337 MLX5_QP_OPTPAR_RAE |
2338 MLX5_QP_OPTPAR_RWE |
2339 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2340 MLX5_QP_OPTPAR_PM_STATE |
2341 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2342 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2343 MLX5_QP_OPTPAR_PM_STATE |
2344 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2345 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2346 MLX5_QP_OPTPAR_SRQN |
2347 MLX5_QP_OPTPAR_CQN_RCV,
2348 },
2349 },
2350 [MLX5_QP_STATE_SQER] = {
2351 [MLX5_QP_STATE_RTS] = {
2352 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2353 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2354 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2355 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2356 MLX5_QP_OPTPAR_RWE |
2357 MLX5_QP_OPTPAR_RAE |
2358 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2359 },
2360 },
2361};
2362
2363static int ib_nr_to_mlx5_nr(int ib_mask)
2364{
2365 switch (ib_mask) {
2366 case IB_QP_STATE:
2367 return 0;
2368 case IB_QP_CUR_STATE:
2369 return 0;
2370 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2371 return 0;
2372 case IB_QP_ACCESS_FLAGS:
2373 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2374 MLX5_QP_OPTPAR_RAE;
2375 case IB_QP_PKEY_INDEX:
2376 return MLX5_QP_OPTPAR_PKEY_INDEX;
2377 case IB_QP_PORT:
2378 return MLX5_QP_OPTPAR_PRI_PORT;
2379 case IB_QP_QKEY:
2380 return MLX5_QP_OPTPAR_Q_KEY;
2381 case IB_QP_AV:
2382 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2383 MLX5_QP_OPTPAR_PRI_PORT;
2384 case IB_QP_PATH_MTU:
2385 return 0;
2386 case IB_QP_TIMEOUT:
2387 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2388 case IB_QP_RETRY_CNT:
2389 return MLX5_QP_OPTPAR_RETRY_COUNT;
2390 case IB_QP_RNR_RETRY:
2391 return MLX5_QP_OPTPAR_RNR_RETRY;
2392 case IB_QP_RQ_PSN:
2393 return 0;
2394 case IB_QP_MAX_QP_RD_ATOMIC:
2395 return MLX5_QP_OPTPAR_SRA_MAX;
2396 case IB_QP_ALT_PATH:
2397 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2398 case IB_QP_MIN_RNR_TIMER:
2399 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2400 case IB_QP_SQ_PSN:
2401 return 0;
2402 case IB_QP_MAX_DEST_RD_ATOMIC:
2403 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2404 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2405 case IB_QP_PATH_MIG_STATE:
2406 return MLX5_QP_OPTPAR_PM_STATE;
2407 case IB_QP_CAP:
2408 return 0;
2409 case IB_QP_DEST_QPN:
2410 return 0;
2411 }
2412 return 0;
2413}
2414
2415static int ib_mask_to_mlx5_opt(int ib_mask)
2416{
2417 int result = 0;
2418 int i;
2419
2420 for (i = 0; i < 8 * sizeof(int); i++) {
2421 if ((1 << i) & ib_mask)
2422 result |= ib_nr_to_mlx5_nr(1 << i);
2423 }
2424
2425 return result;
2426}
2427
eb49ab0c
AV		 2428static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2429 struct mlx5_ib_rq *rq, int new_state,
2430 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2431{
2432 void *in;
2433 void *rqc;
2434 int inlen;
2435 int err;
2436
2437 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2438 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2439 if (!in)
2440 return -ENOMEM;
2441
2442 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2443
2444 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2445 MLX5_SET(rqc, rqc, state, new_state);
2446
eb49ab0c
AV		 2447 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2448 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2449 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2450 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2451 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2452 } else
2453 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2454 dev->ib_dev.name);
2455 }
2456
2457 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2458 if (err)
2459 goto out;
2460
2461 rq->state = new_state;
2462
2463out:
2464 kvfree(in);
2465 return err;
2466}
2467
2468static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2469 struct mlx5_ib_sq *sq,
2470 int new_state,
2471 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2472{
7d29f349
BW		 2473 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2474 u32 old_rate = ibqp->rate_limit;
2475 u32 new_rate = old_rate;
2476 u16 rl_index = 0;
ad5f8e96 2477 void *in;
2478 void *sqc;
2479 int inlen;
2480 int err;
2481
2482 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2483 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2484 if (!in)
2485 return -ENOMEM;
2486
2487 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2488
2489 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2490 MLX5_SET(sqc, sqc, state, new_state);
2491
7d29f349
BW		 2492 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2493 if (new_state != MLX5_SQC_STATE_RDY)
2494 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2495 __func__);
2496 else
2497 new_rate = raw_qp_param->rate_limit;
2498 }
2499
2500 if (old_rate != new_rate) {
2501 if (new_rate) {
2502 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2503 if (err) {
2504 pr_err("Failed configuring rate %u: %d\n",
2505 new_rate, err);
2506 goto out;
2507 }
2508 }
2509
2510 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2511 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2512 }
2513
ad5f8e96 2514 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2515 if (err) {
2516 /* Remove new rate from table if failed */
2517 if (new_rate &&
2518 old_rate != new_rate)
2519 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2520 goto out;
7d29f349
BW		 2521 }
2522
2523 /* Only remove the old rate after new rate was set */
2524 if ((old_rate &&
2525 (old_rate != new_rate)) ||
2526 (new_state != MLX5_SQC_STATE_RDY))
2527 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2528
7d29f349 2529 ibqp->rate_limit = new_rate;
ad5f8e96 2530 sq->state = new_state;
2531
2532out:
2533 kvfree(in);
2534 return err;
2535}
2536
2537static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2538 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2539 u8 tx_affinity)
ad5f8e96 2540{
2541 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2542 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2543 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2544 int modify_rq = !!qp->rq.wqe_cnt;
2545 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2546 int rq_state;
2547 int sq_state;
2548 int err;
2549
0680efa2 2550 switch (raw_qp_param->operation) {
ad5f8e96 2551 case MLX5_CMD_OP_RST2INIT_QP:
2552 rq_state = MLX5_RQC_STATE_RDY;
2553 sq_state = MLX5_SQC_STATE_RDY;
2554 break;
2555 case MLX5_CMD_OP_2ERR_QP:
2556 rq_state = MLX5_RQC_STATE_ERR;
2557 sq_state = MLX5_SQC_STATE_ERR;
2558 break;
2559 case MLX5_CMD_OP_2RST_QP:
2560 rq_state = MLX5_RQC_STATE_RST;
2561 sq_state = MLX5_SQC_STATE_RST;
2562 break;
ad5f8e96 2563 case MLX5_CMD_OP_RTR2RTS_QP:
2564 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2565 if (raw_qp_param->set_mask ==
2566 MLX5_RAW_QP_RATE_LIMIT) {
2567 modify_rq = 0;
2568 sq_state = sq->state;
2569 } else {
2570 return raw_qp_param->set_mask ? -EINVAL : 0;
2571 }
2572 break;
2573 case MLX5_CMD_OP_INIT2INIT_QP:
2574 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2575 if (raw_qp_param->set_mask)
2576 return -EINVAL;
2577 else
2578 return 0;
ad5f8e96 2579 default:
2580 WARN_ON(1);
2581 return -EINVAL;
2582 }
2583
7d29f349
BW		 2584 if (modify_rq) {
2585 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2586 if (err)
2587 return err;
2588 }
2589
7d29f349 2590 if (modify_sq) {
13eab21f
AH		 2591 if (tx_affinity) {
2592 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2593 tx_affinity);
2594 if (err)
2595 return err;
2596 }
2597
7d29f349 2598 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2599 }
ad5f8e96 2600
2601 return 0;
2602}
2603
e126ba97
EC		 2604static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2605 const struct ib_qp_attr *attr, int attr_mask,
2606 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2607{
427c1e7b 2608 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2609 [MLX5_QP_STATE_RST] = {
2610 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2611 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2612 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2613 },
2614 [MLX5_QP_STATE_INIT] = {
2615 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2616 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2617 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2618 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2619 },
2620 [MLX5_QP_STATE_RTR] = {
2621 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2622 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2623 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2624 },
2625 [MLX5_QP_STATE_RTS] = {
2626 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2627 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2628 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2629 },
2630 [MLX5_QP_STATE_SQD] = {
2631 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2632 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2633 },
2634 [MLX5_QP_STATE_SQER] = {
2635 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2636 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2637 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2638 },
2639 [MLX5_QP_STATE_ERR] = {
2640 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2641 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2642 }
2643 };
2644
e126ba97
EC		 2645 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2646 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2647 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2648 struct mlx5_ib_cq *send_cq, *recv_cq;
2649 struct mlx5_qp_context *context;
e126ba97 2650 struct mlx5_ib_pd *pd;
eb49ab0c 2651 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2652 enum mlx5_qp_state mlx5_cur, mlx5_new;
2653 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2654 int mlx5_st;
2655 int err;
427c1e7b 2656 u16 op;
13eab21f 2657 u8 tx_affinity = 0;
e126ba97 2658
1a412fb1
SM		 2659 context = kzalloc(sizeof(*context), GFP_KERNEL);
2660 if (!context)
e126ba97
EC		 2661 return -ENOMEM;
2662
e126ba97 2663 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2664 if (err < 0) {
2665 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2666 goto out;
158abf86 2667 }
e126ba97
EC		 2668
2669 context->flags = cpu_to_be32(err << 16);
2670
2671 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2672 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2673 } else {
2674 switch (attr->path_mig_state) {
2675 case IB_MIG_MIGRATED:
2676 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2677 break;
2678 case IB_MIG_REARM:
2679 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2680 break;
2681 case IB_MIG_ARMED:
2682 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2683 break;
2684 }
2685 }
2686
13eab21f
AH		 2687 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2688 if ((ibqp->qp_type == IB_QPT_RC) ||
2689 (ibqp->qp_type == IB_QPT_UD &&
2690 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2691 (ibqp->qp_type == IB_QPT_UC) ||
2692 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2693 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2694 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2695 if (mlx5_lag_is_active(dev->mdev)) {
2696 tx_affinity = (unsigned int)atomic_add_return(1,
2697 &dev->roce.next_port) %
2698 MLX5_MAX_PORTS + 1;
2699 context->flags |= cpu_to_be32(tx_affinity << 24);
2700 }
2701 }
2702 }
2703
d16e91da 2704 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2705 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2706 } else if (ibqp->qp_type == IB_QPT_UD ||
2707 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2708 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2709 } else if (attr_mask & IB_QP_PATH_MTU) {
2710 if (attr->path_mtu < IB_MTU_256 ||
2711 attr->path_mtu > IB_MTU_4096) {
2712 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2713 err = -EINVAL;
2714 goto out;
2715 }
938fe83c
SM		 2716 context->mtu_msgmax = (attr->path_mtu << 5) |
2717 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2718 }
2719
2720 if (attr_mask & IB_QP_DEST_QPN)
2721 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2722
2723 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2724 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2725
2726 /* todo implement counter_index functionality */
2727
2728 if (is_sqp(ibqp->qp_type))
2729 context->pri_path.port = qp->port;
2730
2731 if (attr_mask & IB_QP_PORT)
2732 context->pri_path.port = attr->port_num;
2733
2734 if (attr_mask & IB_QP_AV) {
75850d0b 2735 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2736 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2737 attr_mask, 0, attr, false);
e126ba97
EC		 2738 if (err)
2739 goto out;
2740 }
2741
2742 if (attr_mask & IB_QP_TIMEOUT)
2743 context->pri_path.ackto_lt |= attr->timeout << 3;
2744
2745 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2746 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2747 &context->alt_path,
f879ee8d
AS		 2748 attr->alt_port_num,
2749 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2750 0, attr, true);
e126ba97
EC		 2751 if (err)
2752 goto out;
2753 }
2754
2755 pd = get_pd(qp);
89ea94a7
MG		 2756 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2757 &send_cq, &recv_cq);
e126ba97
EC		 2758
2759 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2760 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2761 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2762 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2763
2764 if (attr_mask & IB_QP_RNR_RETRY)
2765 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2766
2767 if (attr_mask & IB_QP_RETRY_CNT)
2768 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2769
2770 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2771 if (attr->max_rd_atomic)
2772 context->params1 |=
2773 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2774 }
2775
2776 if (attr_mask & IB_QP_SQ_PSN)
2777 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2778
2779 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2780 if (attr->max_dest_rd_atomic)
2781 context->params2 |=
2782 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2783 }
2784
2785 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2786 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2787
2788 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2789 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2790
2791 if (attr_mask & IB_QP_RQ_PSN)
2792 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2793
2794 if (attr_mask & IB_QP_QKEY)
2795 context->qkey = cpu_to_be32(attr->qkey);
2796
2797 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2798 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2799
0837e86a
MB		 2800 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2801 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2802 qp->port) - 1;
eb49ab0c 2803 mibport = &dev->port[port_num];
0837e86a 2804 context->qp_counter_set_usr_page |=
e1f24a79 2805 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 2806 }
2807
e126ba97
EC		 2808 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2809 context->sq_crq_size |= cpu_to_be16(1 << 4);
2810
b11a4f9c
HE		 2811 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2812 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2813
2814 mlx5_cur = to_mlx5_state(cur_state);
2815 mlx5_new = to_mlx5_state(new_state);
2816 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2817 if (mlx5_st < 0)
e126ba97
EC		 2818 goto out;
2819
427c1e7b 2820 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2821 !optab[mlx5_cur][mlx5_new])
2822 goto out;
2823
2824 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2825 optpar = ib_mask_to_mlx5_opt(attr_mask);
2826 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2827
0680efa2
AV		 2828 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2829 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2830
2831 raw_qp_param.operation = op;
eb49ab0c 2832 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 2833 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 2834 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2835 }
7d29f349
BW		 2836
2837 if (attr_mask & IB_QP_RATE_LIMIT) {
2838 raw_qp_param.rate_limit = attr->rate_limit;
2839 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2840 }
2841
13eab21f 2842 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 2843 } else {
1a412fb1 2844 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2845 &base->mqp);
0680efa2
AV		 2846 }
2847
e126ba97
EC		 2848 if (err)
2849 goto out;
2850
2851 qp->state = new_state;
2852
2853 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2854 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2855 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2856 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2857 if (attr_mask & IB_QP_PORT)
2858 qp->port = attr->port_num;
2859 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2860 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2861
2862 /*
2863 * If we moved a kernel QP to RESET, clean up all old CQ
2864 * entries and reinitialize the QP.
2865 */
2866 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2867 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2868 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2869 if (send_cq != recv_cq)
19098df2 2870 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2871
2872 qp->rq.head = 0;
2873 qp->rq.tail = 0;
2874 qp->sq.head = 0;
2875 qp->sq.tail = 0;
2876 qp->sq.cur_post = 0;
2877 qp->sq.last_poll = 0;
2878 qp->db.db[MLX5_RCV_DBR] = 0;
2879 qp->db.db[MLX5_SND_DBR] = 0;
2880 }
2881
2882out:
1a412fb1 2883 kfree(context);
e126ba97
EC		 2884 return err;
2885}
2886
2887int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2888 int attr_mask, struct ib_udata *udata)
2889{
2890 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2891 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2892 enum ib_qp_type qp_type;
e126ba97
EC		 2893 enum ib_qp_state cur_state, new_state;
2894 int err = -EINVAL;
2895 int port;
2811ba51 2896 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2897
28d61370
YH		 2898 if (ibqp->rwq_ind_tbl)
2899 return -ENOSYS;
2900
d16e91da
HE		 2901 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2902 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2903
2904 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2905 IB_QPT_GSI : ibqp->qp_type;
2906
e126ba97
EC		 2907 mutex_lock(&qp->mutex);
2908
2909 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2910 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2911
2811ba51
AS		 2912 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2913 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2914 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2915 }
2916
d16e91da
HE		 2917 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2918 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2919 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2920 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2921 goto out;
158abf86 2922 }
e126ba97
EC		 2923
2924 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2925 (attr->port_num == 0 ||
158abf86
HE		 2926 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2927 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2928 attr->port_num, dev->num_ports);
e126ba97 2929 goto out;
158abf86 2930 }
e126ba97
EC		 2931
2932 if (attr_mask & IB_QP_PKEY_INDEX) {
2933 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2934 if (attr->pkey_index >=
158abf86
HE		 2935 dev->mdev->port_caps[port - 1].pkey_table_len) {
2936 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2937 attr->pkey_index);
e126ba97 2938 goto out;
158abf86 2939 }
e126ba97
EC		 2940 }
2941
2942 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2943 attr->max_rd_atomic >
158abf86
HE		 2944 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2945 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2946 attr->max_rd_atomic);
e126ba97 2947 goto out;
158abf86 2948 }
e126ba97
EC		 2949
2950 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2951 attr->max_dest_rd_atomic >
158abf86
HE		 2952 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2953 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2954 attr->max_dest_rd_atomic);
e126ba97 2955 goto out;
158abf86 2956 }
e126ba97
EC		 2957
2958 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2959 err = 0;
2960 goto out;
2961 }
2962
2963 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2964
2965out:
2966 mutex_unlock(&qp->mutex);
2967 return err;
2968}
2969
2970static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2971{
2972 struct mlx5_ib_cq *cq;
2973 unsigned cur;
2974
2975 cur = wq->head - wq->tail;
2976 if (likely(cur + nreq < wq->max_post))
2977 return 0;
2978
2979 cq = to_mcq(ib_cq);
2980 spin_lock(&cq->lock);
2981 cur = wq->head - wq->tail;
2982 spin_unlock(&cq->lock);
2983
2984 return cur + nreq >= wq->max_post;
2985}
2986
2987static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2988 u64 remote_addr, u32 rkey)
2989{
2990 rseg->raddr = cpu_to_be64(remote_addr);
2991 rseg->rkey = cpu_to_be32(rkey);
2992 rseg->reserved = 0;
2993}
2994
f0313965
ES		 2995static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2996 struct ib_send_wr *wr, void *qend,
2997 struct mlx5_ib_qp *qp, int *size)
2998{
2999 void *seg = eseg;
3000
3001 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3002
3003 if (wr->send_flags & IB_SEND_IP_CSUM)
3004 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3005 MLX5_ETH_WQE_L4_CSUM;
3006
3007 seg += sizeof(struct mlx5_wqe_eth_seg);
3008 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3009
3010 if (wr->opcode == IB_WR_LSO) {
3011 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3012 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3013 u64 left, leftlen, copysz;
3014 void *pdata = ud_wr->header;
3015
3016 left = ud_wr->hlen;
3017 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3018 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3019
3020 /*
3021 * check if there is space till the end of queue, if yes,
3022 * copy all in one shot, otherwise copy till the end of queue,
3023 * rollback and than the copy the left
3024 */
2b31f7ae 3025 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3026 copysz = min_t(u64, leftlen, left);
3027
3028 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3029
3030 if (likely(copysz > size_of_inl_hdr_start)) {
3031 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3032 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3033 }
3034
3035 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3036 seg = mlx5_get_send_wqe(qp, 0);
3037 left -= copysz;
3038 pdata += copysz;
3039 memcpy(seg, pdata, left);
3040 seg += ALIGN(left, 16);
3041 *size += ALIGN(left, 16) / 16;
3042 }
3043 }
3044
3045 return seg;
3046}
3047
e126ba97
EC		 3048static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3049 struct ib_send_wr *wr)
3050{
e622f2f4
CH		 3051 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3052 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3053 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3054}
3055
3056static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3057{
3058 dseg->byte_count = cpu_to_be32(sg->length);
3059 dseg->lkey = cpu_to_be32(sg->lkey);
3060 dseg->addr = cpu_to_be64(sg->addr);
3061}
3062
31616255 3063static u64 get_xlt_octo(u64 bytes)
e126ba97 3064{
31616255
AK		 3065 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3066 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3067}
3068
3069static __be64 frwr_mkey_mask(void)
3070{
3071 u64 result;
3072
3073 result = MLX5_MKEY_MASK_LEN |
3074 MLX5_MKEY_MASK_PAGE_SIZE |
3075 MLX5_MKEY_MASK_START_ADDR |
3076 MLX5_MKEY_MASK_EN_RINVAL |
3077 MLX5_MKEY_MASK_KEY |
3078 MLX5_MKEY_MASK_LR |
3079 MLX5_MKEY_MASK_LW |
3080 MLX5_MKEY_MASK_RR |
3081 MLX5_MKEY_MASK_RW |
3082 MLX5_MKEY_MASK_A |
3083 MLX5_MKEY_MASK_SMALL_FENCE |
3084 MLX5_MKEY_MASK_FREE;
3085
3086 return cpu_to_be64(result);
3087}
3088
e6631814
SG		 3089static __be64 sig_mkey_mask(void)
3090{
3091 u64 result;
3092
3093 result = MLX5_MKEY_MASK_LEN |
3094 MLX5_MKEY_MASK_PAGE_SIZE |
3095 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3096 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3097 MLX5_MKEY_MASK_EN_RINVAL |
3098 MLX5_MKEY_MASK_KEY |
3099 MLX5_MKEY_MASK_LR |
3100 MLX5_MKEY_MASK_LW |
3101 MLX5_MKEY_MASK_RR |
3102 MLX5_MKEY_MASK_RW |
3103 MLX5_MKEY_MASK_SMALL_FENCE |
3104 MLX5_MKEY_MASK_FREE |
3105 MLX5_MKEY_MASK_BSF_EN;
3106
3107 return cpu_to_be64(result);
3108}
3109
8a187ee5 3110static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3111 struct mlx5_ib_mr *mr)
8a187ee5 3112{
31616255 3113 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3114
3115 memset(umr, 0, sizeof(*umr));
b005d316 3116
8a187ee5 3117 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3118 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3119 umr->mkey_mask = frwr_mkey_mask();
3120}
3121
dd01e66a 3122static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3123{
3124 memset(umr, 0, sizeof(*umr));
dd01e66a 3125 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3126 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3127}
3128
31616255 3129static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3130{
3131 u64 result;
3132
31616255 3133 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3134 MLX5_MKEY_MASK_FREE;
3135
968e78dd
HE		 3136 return cpu_to_be64(result);
3137}
3138
31616255 3139static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3140{
3141 u64 result;
3142
3143 result = MLX5_MKEY_MASK_FREE;
3144
3145 return cpu_to_be64(result);
3146}
3147
56e11d62
NO		 3148static __be64 get_umr_update_translation_mask(void)
3149{
3150 u64 result;
3151
3152 result = MLX5_MKEY_MASK_LEN |
3153 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3154 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3155
3156 return cpu_to_be64(result);
3157}
3158
31616255 3159static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3160{
3161 u64 result;
3162
31616255
AK		 3163 result = MLX5_MKEY_MASK_LR |
3164 MLX5_MKEY_MASK_LW |
56e11d62 3165 MLX5_MKEY_MASK_RR |
31616255
AK		 3166 MLX5_MKEY_MASK_RW;
3167
3168 if (atomic)
3169 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3170
3171 return cpu_to_be64(result);
3172}
3173
3174static __be64 get_umr_update_pd_mask(void)
3175{
3176 u64 result;
3177
31616255 3178 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3179
3180 return cpu_to_be64(result);
3181}
3182
e126ba97 3183static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3184 struct ib_send_wr *wr, int atomic)
e126ba97 3185{
e622f2f4 3186 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3187
3188 memset(umr, 0, sizeof(*umr));
3189
968e78dd
HE		 3190 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3191 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3192 else
3193 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3194
31616255
AK		 3195 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3196 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3197 u64 offset = get_xlt_octo(umrwr->offset);
3198
3199 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3200 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3201 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3202 }
31616255
AK		 3203 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3204 umr->mkey_mask |= get_umr_update_translation_mask();
3205 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3206 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3207 umr->mkey_mask |= get_umr_update_pd_mask();
3208 }
3209 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3210 umr->mkey_mask |= get_umr_enable_mr_mask();
3211 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3212 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3213
3214 if (!wr->num_sge)
968e78dd 3215 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3216}
3217
3218static u8 get_umr_flags(int acc)
3219{
3220 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3221 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3222 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3223 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3224 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3225}
3226
8a187ee5
SG		 3227static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3228 struct mlx5_ib_mr *mr,
3229 u32 key, int access)
3230{
3231 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3232
3233 memset(seg, 0, sizeof(*seg));
b005d316 3234
ec22eb53 3235 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3236 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3237 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3238 /* KLMs take twice the size of MTTs */
3239 ndescs *= 2;
3240
3241 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3242 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3243 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3244 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3245 seg->len = cpu_to_be64(mr->ibmr.length);
3246 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3247}
3248
dd01e66a 3249static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3250{
3251 memset(seg, 0, sizeof(*seg));
dd01e66a 3252 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3253}
3254
3255static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3256{
e622f2f4 3257 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3258
e126ba97 3259 memset(seg, 0, sizeof(*seg));
31616255 3260 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3261 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3262
968e78dd 3263 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3264 if (umrwr->pd)
3265 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3266 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3267 !umrwr->length)
3268 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3269
3270 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3271 seg->len = cpu_to_be64(umrwr->length);
3272 seg->log2_page_size = umrwr->page_shift;
746b5583 3273 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3274 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3275}
3276
8a187ee5
SG		 3277static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3278 struct mlx5_ib_mr *mr,
3279 struct mlx5_ib_pd *pd)
3280{
3281 int bcount = mr->desc_size * mr->ndescs;
3282
3283 dseg->addr = cpu_to_be64(mr->desc_map);
3284 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3285 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3286}
3287
e126ba97
EC		 3288static __be32 send_ieth(struct ib_send_wr *wr)
3289{
3290 switch (wr->opcode) {
3291 case IB_WR_SEND_WITH_IMM:
3292 case IB_WR_RDMA_WRITE_WITH_IMM:
3293 return wr->ex.imm_data;
3294
3295 case IB_WR_SEND_WITH_INV:
3296 return cpu_to_be32(wr->ex.invalidate_rkey);
3297
3298 default:
3299 return 0;
3300 }
3301}
3302
3303static u8 calc_sig(void *wqe, int size)
3304{
3305 u8 *p = wqe;
3306 u8 res = 0;
3307 int i;
3308
3309 for (i = 0; i < size; i++)
3310 res ^= p[i];
3311
3312 return ~res;
3313}
3314
3315static u8 wq_sig(void *wqe)
3316{
3317 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3318}
3319
3320static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3321 void *wqe, int *sz)
3322{
3323 struct mlx5_wqe_inline_seg *seg;
3324 void *qend = qp->sq.qend;
3325 void *addr;
3326 int inl = 0;
3327 int copy;
3328 int len;
3329 int i;
3330
3331 seg = wqe;
3332 wqe += sizeof(*seg);
3333 for (i = 0; i < wr->num_sge; i++) {
3334 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3335 len = wr->sg_list[i].length;
3336 inl += len;
3337
3338 if (unlikely(inl > qp->max_inline_data))
3339 return -ENOMEM;
3340
3341 if (unlikely(wqe + len > qend)) {
3342 copy = qend - wqe;
3343 memcpy(wqe, addr, copy);
3344 addr += copy;
3345 len -= copy;
3346 wqe = mlx5_get_send_wqe(qp, 0);
3347 }
3348 memcpy(wqe, addr, len);
3349 wqe += len;
3350 }
3351
3352 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3353
3354 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3355
3356 return 0;
3357}
3358
e6631814
SG		 3359static u16 prot_field_size(enum ib_signature_type type)
3360{
3361 switch (type) {
3362 case IB_SIG_TYPE_T10_DIF:
3363 return MLX5_DIF_SIZE;
3364 default:
3365 return 0;
3366 }
3367}
3368
3369static u8 bs_selector(int block_size)
3370{
3371 switch (block_size) {
3372 case 512: return 0x1;
3373 case 520: return 0x2;
3374 case 4096: return 0x3;
3375 case 4160: return 0x4;
3376 case 1073741824: return 0x5;
3377 default: return 0;
3378 }
3379}
3380
78eda2bb
SG		 3381static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3382 struct mlx5_bsf_inl *inl)
e6631814 3383{
142537f4
SG		 3384 /* Valid inline section and allow BSF refresh */
3385 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3386 MLX5_BSF_REFRESH_DIF);
3387 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3388 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3389 /* repeating block */
3390 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3391 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3392 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3393
78eda2bb
SG		 3394 if (domain->sig.dif.ref_remap)
3395 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3396
78eda2bb
SG		 3397 if (domain->sig.dif.app_escape) {
3398 if (domain->sig.dif.ref_escape)
3399 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3400 else
3401 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3402 }
3403
78eda2bb
SG		 3404 inl->dif_app_bitmask_check =
3405 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3406}
3407
3408static int mlx5_set_bsf(struct ib_mr *sig_mr,
3409 struct ib_sig_attrs *sig_attrs,
3410 struct mlx5_bsf *bsf, u32 data_size)
3411{
3412 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3413 struct mlx5_bsf_basic *basic = &bsf->basic;
3414 struct ib_sig_domain *mem = &sig_attrs->mem;
3415 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3416
c7f44fbd 3417 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3418
3419 /* Basic + Extended + Inline */
3420 basic->bsf_size_sbs = 1 << 7;
3421 /* Input domain check byte mask */
3422 basic->check_byte_mask = sig_attrs->check_mask;
3423 basic->raw_data_size = cpu_to_be32(data_size);
3424
3425 /* Memory domain */
e6631814 3426 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3427 case IB_SIG_TYPE_NONE:
3428 break;
e6631814 3429 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3430 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3431 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3432 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3433 break;
3434 default:
3435 return -EINVAL;
3436 }
e6631814 3437
78eda2bb
SG		 3438 /* Wire domain */
3439 switch (sig_attrs->wire.sig_type) {
3440 case IB_SIG_TYPE_NONE:
3441 break;
3442 case IB_SIG_TYPE_T10_DIF:
e6631814 3443 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3444 mem->sig_type == wire->sig_type) {
e6631814 3445 /* Same block structure */
142537f4 3446 basic->bsf_size_sbs |= 1 << 4;
e6631814 3447 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3448 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3449 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3450 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3451 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3452 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3453 } else
3454 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3455
142537f4 3456 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3457 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3458 break;
e6631814
SG		 3459 default:
3460 return -EINVAL;
3461 }
3462
3463 return 0;
3464}
3465
e622f2f4
CH		 3466static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3467 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3468{
e622f2f4
CH		 3469 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3470 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3471 struct mlx5_bsf *bsf;
e622f2f4
CH		 3472 u32 data_len = wr->wr.sg_list->length;
3473 u32 data_key = wr->wr.sg_list->lkey;
3474 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3475 int ret;
3476 int wqe_size;
3477
e622f2f4
CH		 3478 if (!wr->prot ||
3479 (data_key == wr->prot->lkey &&
3480 data_va == wr->prot->addr &&
3481 data_len == wr->prot->length)) {
e6631814
SG		 3482 /**
3483 * Source domain doesn't contain signature information
5c273b16 3484 * or data and protection are interleaved in memory.
e6631814
SG		 3485 * So need construct:
3486 * ------------------
3487 * | data_klm |
3488 * ------------------
3489 * | BSF |
3490 * ------------------
3491 **/
3492 struct mlx5_klm *data_klm = *seg;
3493
3494 data_klm->bcount = cpu_to_be32(data_len);
3495 data_klm->key = cpu_to_be32(data_key);
3496 data_klm->va = cpu_to_be64(data_va);
3497 wqe_size = ALIGN(sizeof(*data_klm), 64);
3498 } else {
3499 /**
3500 * Source domain contains signature information
3501 * So need construct a strided block format:
3502 * ---------------------------
3503 * | stride_block_ctrl |
3504 * ---------------------------
3505 * | data_klm |
3506 * ---------------------------
3507 * | prot_klm |
3508 * ---------------------------
3509 * | BSF |
3510 * ---------------------------
3511 **/
3512 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3513 struct mlx5_stride_block_entry *data_sentry;
3514 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3515 u32 prot_key = wr->prot->lkey;
3516 u64 prot_va = wr->prot->addr;
e6631814
SG		 3517 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3518 int prot_size;
3519
3520 sblock_ctrl = *seg;
3521 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3522 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3523
3524 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3525 if (!prot_size) {
3526 pr_err("Bad block size given: %u\n", block_size);
3527 return -EINVAL;
3528 }
3529 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3530 prot_size);
3531 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3532 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3533 sblock_ctrl->num_entries = cpu_to_be16(2);
3534
3535 data_sentry->bcount = cpu_to_be16(block_size);
3536 data_sentry->key = cpu_to_be32(data_key);
3537 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3538 data_sentry->stride = cpu_to_be16(block_size);
3539
e6631814
SG		 3540 prot_sentry->bcount = cpu_to_be16(prot_size);
3541 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3542 prot_sentry->va = cpu_to_be64(prot_va);
3543 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3544
e6631814
SG		 3545 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3546 sizeof(*prot_sentry), 64);
3547 }
3548
3549 *seg += wqe_size;
3550 *size += wqe_size / 16;
3551 if (unlikely((*seg == qp->sq.qend)))
3552 *seg = mlx5_get_send_wqe(qp, 0);
3553
3554 bsf = *seg;
3555 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3556 if (ret)
3557 return -EINVAL;
3558
3559 *seg += sizeof(*bsf);
3560 *size += sizeof(*bsf) / 16;
3561 if (unlikely((*seg == qp->sq.qend)))
3562 *seg = mlx5_get_send_wqe(qp, 0);
3563
3564 return 0;
3565}
3566
3567static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 3568 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 3569 u32 length, u32 pdn)
3570{
e622f2f4 3571 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3572 u32 sig_key = sig_mr->rkey;
d5436ba0 3573 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3574
3575 memset(seg, 0, sizeof(*seg));
3576
e622f2f4 3577 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3578 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3579 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3580 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3581 MLX5_MKEY_BSF_EN | pdn);
3582 seg->len = cpu_to_be64(length);
31616255 3583 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 3584 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3585}
3586
3587static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3588 u32 size)
e6631814
SG		 3589{
3590 memset(umr, 0, sizeof(*umr));
3591
3592 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 3593 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 3594 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3595 umr->mkey_mask = sig_mkey_mask();
3596}
3597
3598
e622f2f4 3599static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3600 void **seg, int *size)
3601{
e622f2f4
CH		 3602 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3603 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 3604 u32 pdn = get_pd(qp)->pdn;
31616255 3605 u32 xlt_size;
e6631814
SG		 3606 int region_len, ret;
3607
e622f2f4
CH		 3608 if (unlikely(wr->wr.num_sge != 1) ||
3609 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3610 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3611 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3612 return -EINVAL;
3613
3614 /* length of the protected region, data + protection */
e622f2f4
CH		 3615 region_len = wr->wr.sg_list->length;
3616 if (wr->prot &&
3617 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3618 wr->prot->addr != wr->wr.sg_list->addr ||
3619 wr->prot->length != wr->wr.sg_list->length))
3620 region_len += wr->prot->length;
e6631814
SG		 3621
3622 /**
3623 * KLM octoword size - if protection was provided
3624 * then we use strided block format (3 octowords),
3625 * else we use single KLM (1 octoword)
3626 **/
31616255 3627 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 3628
31616255 3629 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 3630 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3631 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3632 if (unlikely((*seg == qp->sq.qend)))
3633 *seg = mlx5_get_send_wqe(qp, 0);
3634
31616255 3635 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 3636 *seg += sizeof(struct mlx5_mkey_seg);
3637 *size += sizeof(struct mlx5_mkey_seg) / 16;
3638 if (unlikely((*seg == qp->sq.qend)))
3639 *seg = mlx5_get_send_wqe(qp, 0);
3640
3641 ret = set_sig_data_segment(wr, qp, seg, size);
3642 if (ret)
3643 return ret;
3644
d5436ba0 3645 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3646 return 0;
3647}
3648
3649static int set_psv_wr(struct ib_sig_domain *domain,
3650 u32 psv_idx, void **seg, int *size)
3651{
3652 struct mlx5_seg_set_psv *psv_seg = *seg;
3653
3654 memset(psv_seg, 0, sizeof(*psv_seg));
3655 psv_seg->psv_num = cpu_to_be32(psv_idx);
3656 switch (domain->sig_type) {
78eda2bb
SG		 3657 case IB_SIG_TYPE_NONE:
3658 break;
e6631814
SG		 3659 case IB_SIG_TYPE_T10_DIF:
3660 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3661 domain->sig.dif.app_tag);
3662 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3663 break;
e6631814 3664 default:
12bbf1ea
LR		 3665 pr_err("Bad signature type (%d) is given.\n",
3666 domain->sig_type);
3667 return -EINVAL;
e6631814
SG		 3668 }
3669
78eda2bb
SG		 3670 *seg += sizeof(*psv_seg);
3671 *size += sizeof(*psv_seg) / 16;
3672
e6631814
SG		 3673 return 0;
3674}
3675
8a187ee5
SG		 3676static int set_reg_wr(struct mlx5_ib_qp *qp,
3677 struct ib_reg_wr *wr,
3678 void **seg, int *size)
3679{
3680 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3681 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3682
3683 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3684 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3685 "Invalid IB_SEND_INLINE send flag\n");
3686 return -EINVAL;
3687 }
3688
3689 set_reg_umr_seg(*seg, mr);
3690 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3691 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3692 if (unlikely((*seg == qp->sq.qend)))
3693 *seg = mlx5_get_send_wqe(qp, 0);
3694
3695 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3696 *seg += sizeof(struct mlx5_mkey_seg);
3697 *size += sizeof(struct mlx5_mkey_seg) / 16;
3698 if (unlikely((*seg == qp->sq.qend)))
3699 *seg = mlx5_get_send_wqe(qp, 0);
3700
3701 set_reg_data_seg(*seg, mr, pd);
3702 *seg += sizeof(struct mlx5_wqe_data_seg);
3703 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3704
3705 return 0;
3706}
3707
dd01e66a 3708static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3709{
dd01e66a 3710 set_linv_umr_seg(*seg);
e126ba97
EC		 3711 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3712 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3713 if (unlikely((*seg == qp->sq.qend)))
3714 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3715 set_linv_mkey_seg(*seg);
e126ba97
EC		 3716 *seg += sizeof(struct mlx5_mkey_seg);
3717 *size += sizeof(struct mlx5_mkey_seg) / 16;
3718 if (unlikely((*seg == qp->sq.qend)))
3719 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3720}
3721
3722static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3723{
3724 __be32 *p = NULL;
3725 int tidx = idx;
3726 int i, j;
3727
3728 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3729 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3730 if ((i & 0xf) == 0) {
3731 void *buf = mlx5_get_send_wqe(qp, tidx);
3732 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3733 p = buf;
3734 j = 0;
3735 }
3736 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3737 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3738 be32_to_cpu(p[j + 3]));
3739 }
3740}
3741
6e5eadac
SG		 3742static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3743 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3744 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3745 int *size, int nreq)
3746{
b2a232d2
LR		 3747 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3748 return -ENOMEM;
6e5eadac
SG		 3749
3750 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3751 *seg = mlx5_get_send_wqe(qp, *idx);
3752 *ctrl = *seg;
3753 *(uint32_t *)(*seg + 8) = 0;
3754 (*ctrl)->imm = send_ieth(wr);
3755 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3756 (wr->send_flags & IB_SEND_SIGNALED ?
3757 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3758 (wr->send_flags & IB_SEND_SOLICITED ?
3759 MLX5_WQE_CTRL_SOLICITED : 0);
3760
3761 *seg += sizeof(**ctrl);
3762 *size = sizeof(**ctrl) / 16;
3763
b2a232d2 3764 return 0;
6e5eadac
SG		 3765}
3766
3767static void finish_wqe(struct mlx5_ib_qp *qp,
3768 struct mlx5_wqe_ctrl_seg *ctrl,
3769 u8 size, unsigned idx, u64 wr_id,
6e8484c5 3770 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 3771{
3772 u8 opmod = 0;
3773
3774 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3775 mlx5_opcode | ((u32)opmod << 24));
19098df2 3776 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 3777 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 3778 if (unlikely(qp->wq_sig))
3779 ctrl->signature = wq_sig(ctrl);
3780
3781 qp->sq.wrid[idx] = wr_id;
3782 qp->sq.w_list[idx].opcode = mlx5_opcode;
3783 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3784 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3785 qp->sq.w_list[idx].next = qp->sq.cur_post;
3786}
3787
3788
e126ba97
EC		 3789int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3790 struct ib_send_wr **bad_wr)
3791{
3792 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3793 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3794 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3795 struct mlx5_ib_qp *qp;
e6631814 3796 struct mlx5_ib_mr *mr;
e126ba97
EC		 3797 struct mlx5_wqe_data_seg *dpseg;
3798 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3799 struct mlx5_bf *bf;
e126ba97 3800 int uninitialized_var(size);
d16e91da 3801 void *qend;
e126ba97 3802 unsigned long flags;
e126ba97
EC		 3803 unsigned idx;
3804 int err = 0;
3805 int inl = 0;
3806 int num_sge;
3807 void *seg;
3808 int nreq;
3809 int i;
3810 u8 next_fence = 0;
e126ba97
EC		 3811 u8 fence;
3812
d16e91da
HE		 3813 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3814 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3815
3816 qp = to_mqp(ibqp);
5fe9dec0 3817 bf = &qp->bf;
d16e91da
HE		 3818 qend = qp->sq.qend;
3819
e126ba97
EC		 3820 spin_lock_irqsave(&qp->sq.lock, flags);
3821
89ea94a7
MG		 3822 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3823 err = -EIO;
3824 *bad_wr = wr;
3825 nreq = 0;
3826 goto out;
3827 }
3828
e126ba97 3829 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3830 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3831 mlx5_ib_warn(dev, "\n");
3832 err = -EINVAL;
3833 *bad_wr = wr;
3834 goto out;
3835 }
3836
6e5eadac
SG		 3837 num_sge = wr->num_sge;
3838 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 3839 mlx5_ib_warn(dev, "\n");
24be409b 3840 err = -EINVAL;
e126ba97
EC		 3841 *bad_wr = wr;
3842 goto out;
3843 }
3844
6e5eadac
SG		 3845 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3846 if (err) {
e126ba97
EC		 3847 mlx5_ib_warn(dev, "\n");
3848 err = -ENOMEM;
3849 *bad_wr = wr;
3850 goto out;
3851 }
3852
6e8484c5
MG		 3853 if (wr->opcode == IB_WR_LOCAL_INV ||
3854 wr->opcode == IB_WR_REG_MR) {
3855 fence = dev->umr_fence;
3856 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3857 } else if (wr->send_flags & IB_SEND_FENCE) {
3858 if (qp->next_fence)
3859 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3860 else
3861 fence = MLX5_FENCE_MODE_FENCE;
3862 } else {
3863 fence = qp->next_fence;
3864 }
3865
e126ba97
EC		 3866 switch (ibqp->qp_type) {
3867 case IB_QPT_XRC_INI:
3868 xrc = seg;
e126ba97
EC		 3869 seg += sizeof(*xrc);
3870 size += sizeof(*xrc) / 16;
3871 /* fall through */
3872 case IB_QPT_RC:
3873 switch (wr->opcode) {
3874 case IB_WR_RDMA_READ:
3875 case IB_WR_RDMA_WRITE:
3876 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3877 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3878 rdma_wr(wr)->rkey);
f241e749 3879 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3880 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3881 break;
3882
3883 case IB_WR_ATOMIC_CMP_AND_SWP:
3884 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3885 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3886 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3887 err = -ENOSYS;
3888 *bad_wr = wr;
3889 goto out;
e126ba97
EC		 3890
3891 case IB_WR_LOCAL_INV:
e126ba97
EC		 3892 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3893 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3894 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3895 num_sge = 0;
3896 break;
3897
8a187ee5 3898 case IB_WR_REG_MR:
8a187ee5
SG		 3899 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3900 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3901 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3902 if (err) {
3903 *bad_wr = wr;
3904 goto out;
3905 }
3906 num_sge = 0;
3907 break;
3908
e6631814
SG		 3909 case IB_WR_REG_SIG_MR:
3910 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3911 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3912
3913 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3914 err = set_sig_umr_wr(wr, qp, &seg, &size);
3915 if (err) {
3916 mlx5_ib_warn(dev, "\n");
3917 *bad_wr = wr;
3918 goto out;
3919 }
3920
6e8484c5
MG		 3921 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3922 fence, MLX5_OPCODE_UMR);
e6631814
SG		 3923 /*
3924 * SET_PSV WQEs are not signaled and solicited
3925 * on error
3926 */
3927 wr->send_flags &= ~IB_SEND_SIGNALED;
3928 wr->send_flags |= IB_SEND_SOLICITED;
3929 err = begin_wqe(qp, &seg, &ctrl, wr,
3930 &idx, &size, nreq);
3931 if (err) {
3932 mlx5_ib_warn(dev, "\n");
3933 err = -ENOMEM;
3934 *bad_wr = wr;
3935 goto out;
3936 }
3937
e622f2f4 3938 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3939 mr->sig->psv_memory.psv_idx, &seg,
3940 &size);
3941 if (err) {
3942 mlx5_ib_warn(dev, "\n");
3943 *bad_wr = wr;
3944 goto out;
3945 }
3946
6e8484c5
MG		 3947 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3948 fence, MLX5_OPCODE_SET_PSV);
e6631814
SG		 3949 err = begin_wqe(qp, &seg, &ctrl, wr,
3950 &idx, &size, nreq);
3951 if (err) {
3952 mlx5_ib_warn(dev, "\n");
3953 err = -ENOMEM;
3954 *bad_wr = wr;
3955 goto out;
3956 }
3957
e622f2f4 3958 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3959 mr->sig->psv_wire.psv_idx, &seg,
3960 &size);
3961 if (err) {
3962 mlx5_ib_warn(dev, "\n");
3963 *bad_wr = wr;
3964 goto out;
3965 }
3966
6e8484c5
MG		 3967 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3968 fence, MLX5_OPCODE_SET_PSV);
3969 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 3970 num_sge = 0;
3971 goto skip_psv;
3972
e126ba97
EC		 3973 default:
3974 break;
3975 }
3976 break;
3977
3978 case IB_QPT_UC:
3979 switch (wr->opcode) {
3980 case IB_WR_RDMA_WRITE:
3981 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3982 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3983 rdma_wr(wr)->rkey);
e126ba97
EC		 3984 seg += sizeof(struct mlx5_wqe_raddr_seg);
3985 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3986 break;
3987
3988 default:
3989 break;
3990 }
3991 break;
3992
e126ba97 3993 case IB_QPT_SMI:
1e0e50b6
MG		 3994 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
3995 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
3996 err = -EPERM;
3997 *bad_wr = wr;
3998 goto out;
3999 }
d16e91da 4000 case MLX5_IB_QPT_HW_GSI:
e126ba97 4001 set_datagram_seg(seg, wr);
f241e749 4002 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4003 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4004 if (unlikely((seg == qend)))
4005 seg = mlx5_get_send_wqe(qp, 0);
4006 break;
f0313965
ES		 4007 case IB_QPT_UD:
4008 set_datagram_seg(seg, wr);
4009 seg += sizeof(struct mlx5_wqe_datagram_seg);
4010 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4011
4012 if (unlikely((seg == qend)))
4013 seg = mlx5_get_send_wqe(qp, 0);
4014
4015 /* handle qp that supports ud offload */
4016 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4017 struct mlx5_wqe_eth_pad *pad;
e126ba97 4018
f0313965
ES		 4019 pad = seg;
4020 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4021 seg += sizeof(struct mlx5_wqe_eth_pad);
4022 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4023
4024 seg = set_eth_seg(seg, wr, qend, qp, &size);
4025
4026 if (unlikely((seg == qend)))
4027 seg = mlx5_get_send_wqe(qp, 0);
4028 }
4029 break;
e126ba97
EC		 4030 case MLX5_IB_QPT_REG_UMR:
4031 if (wr->opcode != MLX5_IB_WR_UMR) {
4032 err = -EINVAL;
4033 mlx5_ib_warn(dev, "bad opcode\n");
4034 goto out;
4035 }
4036 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4037 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4038 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4039 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4040 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4041 if (unlikely((seg == qend)))
4042 seg = mlx5_get_send_wqe(qp, 0);
4043 set_reg_mkey_segment(seg, wr);
4044 seg += sizeof(struct mlx5_mkey_seg);
4045 size += sizeof(struct mlx5_mkey_seg) / 16;
4046 if (unlikely((seg == qend)))
4047 seg = mlx5_get_send_wqe(qp, 0);
4048 break;
4049
4050 default:
4051 break;
4052 }
4053
4054 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4055 int uninitialized_var(sz);
4056
4057 err = set_data_inl_seg(qp, wr, seg, &sz);
4058 if (unlikely(err)) {
4059 mlx5_ib_warn(dev, "\n");
4060 *bad_wr = wr;
4061 goto out;
4062 }
4063 inl = 1;
4064 size += sz;
4065 } else {
4066 dpseg = seg;
4067 for (i = 0; i < num_sge; i++) {
4068 if (unlikely(dpseg == qend)) {
4069 seg = mlx5_get_send_wqe(qp, 0);
4070 dpseg = seg;
4071 }
4072 if (likely(wr->sg_list[i].length)) {
4073 set_data_ptr_seg(dpseg, wr->sg_list + i);
4074 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4075 dpseg++;
4076 }
4077 }
4078 }
4079
6e8484c5
MG		 4080 qp->next_fence = next_fence;
4081 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4082 mlx5_ib_opcode[wr->opcode]);
e6631814 4083skip_psv:
e126ba97
EC		 4084 if (0)
4085 dump_wqe(qp, idx, size);
4086 }
4087
4088out:
4089 if (likely(nreq)) {
4090 qp->sq.head += nreq;
4091
4092 /* Make sure that descriptors are written before
4093 * updating doorbell record and ringing the doorbell
4094 */
4095 wmb();
4096
4097 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4098
ada388f7
EC		 4099 /* Make sure doorbell record is visible to the HCA before
4100 * we hit doorbell */
4101 wmb();
4102
5fe9dec0
EC		 4103 /* currently we support only regular doorbells */
4104 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4105 /* Make sure doorbells don't leak out of SQ spinlock
4106 * and reach the HCA out of order.
4107 */
4108 mmiowb();
e126ba97 4109 bf->offset ^= bf->buf_size;
e126ba97
EC		 4110 }
4111
4112 spin_unlock_irqrestore(&qp->sq.lock, flags);
4113
4114 return err;
4115}
4116
4117static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4118{
4119 sig->signature = calc_sig(sig, size);
4120}
4121
4122int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4123 struct ib_recv_wr **bad_wr)
4124{
4125 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4126 struct mlx5_wqe_data_seg *scat;
4127 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4128 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4129 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4130 unsigned long flags;
4131 int err = 0;
4132 int nreq;
4133 int ind;
4134 int i;
4135
d16e91da
HE		 4136 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4137 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4138
e126ba97
EC		 4139 spin_lock_irqsave(&qp->rq.lock, flags);
4140
89ea94a7
MG		 4141 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4142 err = -EIO;
4143 *bad_wr = wr;
4144 nreq = 0;
4145 goto out;
4146 }
4147
e126ba97
EC		 4148 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4149
4150 for (nreq = 0; wr; nreq++, wr = wr->next) {
4151 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4152 err = -ENOMEM;
4153 *bad_wr = wr;
4154 goto out;
4155 }
4156
4157 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4158 err = -EINVAL;
4159 *bad_wr = wr;
4160 goto out;
4161 }
4162
4163 scat = get_recv_wqe(qp, ind);
4164 if (qp->wq_sig)
4165 scat++;
4166
4167 for (i = 0; i < wr->num_sge; i++)
4168 set_data_ptr_seg(scat + i, wr->sg_list + i);
4169
4170 if (i < qp->rq.max_gs) {
4171 scat[i].byte_count = 0;
4172 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4173 scat[i].addr = 0;
4174 }
4175
4176 if (qp->wq_sig) {
4177 sig = (struct mlx5_rwqe_sig *)scat;
4178 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4179 }
4180
4181 qp->rq.wrid[ind] = wr->wr_id;
4182
4183 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4184 }
4185
4186out:
4187 if (likely(nreq)) {
4188 qp->rq.head += nreq;
4189
4190 /* Make sure that descriptors are written before
4191 * doorbell record.
4192 */
4193 wmb();
4194
4195 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4196 }
4197
4198 spin_unlock_irqrestore(&qp->rq.lock, flags);
4199
4200 return err;
4201}
4202
4203static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4204{
4205 switch (mlx5_state) {
4206 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4207 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4208 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4209 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4210 case MLX5_QP_STATE_SQ_DRAINING:
4211 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4212 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4213 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4214 default: return -1;
4215 }
4216}
4217
4218static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4219{
4220 switch (mlx5_mig_state) {
4221 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4222 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4223 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4224 default: return -1;
4225 }
4226}
4227
4228static int to_ib_qp_access_flags(int mlx5_flags)
4229{
4230 int ib_flags = 0;
4231
4232 if (mlx5_flags & MLX5_QP_BIT_RRE)
4233 ib_flags |= IB_ACCESS_REMOTE_READ;
4234 if (mlx5_flags & MLX5_QP_BIT_RWE)
4235 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4236 if (mlx5_flags & MLX5_QP_BIT_RAE)
4237 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4238
4239 return ib_flags;
4240}
4241
38349389 4242static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4243 struct rdma_ah_attr *ah_attr,
38349389 4244 struct mlx5_qp_path *path)
e126ba97 4245{
9603b61d 4246 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97 4247
d8966fcd 4248 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4249
44c58487 4250 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
d8966fcd
DC		 4251 rdma_ah_set_port_num(ah_attr, path->port);
4252 if (rdma_ah_get_port_num(ah_attr) == 0 ||
4253 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4254 return;
4255
d8966fcd
DC		 4256 rdma_ah_set_port_num(ah_attr, path->port);
4257 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4258
4259 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4260 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4261 rdma_ah_set_static_rate(ah_attr,
4262 path->static_rate ? path->static_rate - 5 : 0);
4263 if (path->grh_mlid & (1 << 7)) {
4264 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4265
4266 rdma_ah_set_grh(ah_attr, NULL,
4267 tc_fl & 0xfffff,
4268 path->mgid_index,
4269 path->hop_limit,
4270 (tc_fl >> 20) & 0xff);
4271 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4272 }
4273}
4274
6d2f89df 4275static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4276 struct mlx5_ib_sq *sq,
4277 u8 *sq_state)
4278{
4279 void *out;
4280 void *sqc;
4281 int inlen;
4282 int err;
4283
4284 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
1b9a07ee 4285 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4286 if (!out)
4287 return -ENOMEM;
4288
4289 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4290 if (err)
4291 goto out;
4292
4293 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4294 *sq_state = MLX5_GET(sqc, sqc, state);
4295 sq->state = *sq_state;
4296
4297out:
4298 kvfree(out);
4299 return err;
4300}
4301
4302static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4303 struct mlx5_ib_rq *rq,
4304 u8 *rq_state)
4305{
4306 void *out;
4307 void *rqc;
4308 int inlen;
4309 int err;
4310
4311 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4312 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4313 if (!out)
4314 return -ENOMEM;
4315
4316 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4317 if (err)
4318 goto out;
4319
4320 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4321 *rq_state = MLX5_GET(rqc, rqc, state);
4322 rq->state = *rq_state;
4323
4324out:
4325 kvfree(out);
4326 return err;
4327}
4328
4329static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4330 struct mlx5_ib_qp *qp, u8 *qp_state)
4331{
4332 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4333 [MLX5_RQC_STATE_RST] = {
4334 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4335 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4336 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4337 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4338 },
4339 [MLX5_RQC_STATE_RDY] = {
4340 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4341 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4342 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4343 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4344 },
4345 [MLX5_RQC_STATE_ERR] = {
4346 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4347 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4348 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4349 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4350 },
4351 [MLX5_RQ_STATE_NA] = {
4352 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4353 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4354 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4355 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4356 },
4357 };
4358
4359 *qp_state = sqrq_trans[rq_state][sq_state];
4360
4361 if (*qp_state == MLX5_QP_STATE_BAD) {
4362 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4363 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4364 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4365 return -EINVAL;
4366 }
4367
4368 if (*qp_state == MLX5_QP_STATE)
4369 *qp_state = qp->state;
4370
4371 return 0;
4372}
4373
4374static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4375 struct mlx5_ib_qp *qp,
4376 u8 *raw_packet_qp_state)
4377{
4378 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4379 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4380 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4381 int err;
4382 u8 sq_state = MLX5_SQ_STATE_NA;
4383 u8 rq_state = MLX5_RQ_STATE_NA;
4384
4385 if (qp->sq.wqe_cnt) {
4386 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4387 if (err)
4388 return err;
4389 }
4390
4391 if (qp->rq.wqe_cnt) {
4392 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4393 if (err)
4394 return err;
4395 }
4396
4397 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4398 raw_packet_qp_state);
4399}
4400
4401static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4402 struct ib_qp_attr *qp_attr)
e126ba97 4403{
09a7d9ec 4404 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4405 struct mlx5_qp_context *context;
4406 int mlx5_state;
09a7d9ec 4407 u32 *outb;
e126ba97
EC		 4408 int err = 0;
4409
09a7d9ec 4410 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4411 if (!outb)
4412 return -ENOMEM;
4413
19098df2 4414 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4415 outlen);
e126ba97 4416 if (err)
6d2f89df 4417 goto out;
e126ba97 4418
09a7d9ec
SM		 4419 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4420 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4421
e126ba97
EC		 4422 mlx5_state = be32_to_cpu(context->flags) >> 28;
4423
4424 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4425 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4426 qp_attr->path_mig_state =
4427 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4428 qp_attr->qkey = be32_to_cpu(context->qkey);
4429 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4430 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4431 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4432 qp_attr->qp_access_flags =
4433 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4434
4435 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 4436 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4437 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4438 qp_attr->alt_pkey_index =
4439 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 4440 qp_attr->alt_port_num =
4441 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 4442 }
4443
d3ae2bde 4444 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4445 qp_attr->port_num = context->pri_path.port;
4446
4447 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4448 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4449
4450 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4451
4452 qp_attr->max_dest_rd_atomic =
4453 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4454 qp_attr->min_rnr_timer =
4455 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4456 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4457 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4458 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4459 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4460
4461out:
4462 kfree(outb);
4463 return err;
4464}
4465
4466int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4467 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4468{
4469 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4470 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4471 int err = 0;
4472 u8 raw_packet_qp_state;
4473
28d61370
YH		 4474 if (ibqp->rwq_ind_tbl)
4475 return -ENOSYS;
4476
d16e91da
HE		 4477 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4478 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4479 qp_init_attr);
4480
6d2f89df 4481 mutex_lock(&qp->mutex);
4482
4483 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4484 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4485 if (err)
4486 goto out;
4487 qp->state = raw_packet_qp_state;
4488 qp_attr->port_num = 1;
4489 } else {
4490 err = query_qp_attr(dev, qp, qp_attr);
4491 if (err)
4492 goto out;
4493 }
4494
4495 qp_attr->qp_state = qp->state;
e126ba97
EC		 4496 qp_attr->cur_qp_state = qp_attr->qp_state;
4497 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4498 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4499
4500 if (!ibqp->uobject) {
0540d814 4501 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4502 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4503 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4504 } else {
4505 qp_attr->cap.max_send_wr = 0;
4506 qp_attr->cap.max_send_sge = 0;
4507 }
4508
0540d814
NO		 4509 qp_init_attr->qp_type = ibqp->qp_type;
4510 qp_init_attr->recv_cq = ibqp->recv_cq;
4511 qp_init_attr->send_cq = ibqp->send_cq;
4512 qp_init_attr->srq = ibqp->srq;
4513 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4514
4515 qp_init_attr->cap = qp_attr->cap;
4516
4517 qp_init_attr->create_flags = 0;
4518 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4519 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4520
051f2630
LR		 4521 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4522 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4523 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4524 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4525 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4526 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4527 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4528 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4529
e126ba97
EC		 4530 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4531 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4532
e126ba97
EC		 4533out:
4534 mutex_unlock(&qp->mutex);
4535 return err;
4536}
4537
4538struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4539 struct ib_ucontext *context,
4540 struct ib_udata *udata)
4541{
4542 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4543 struct mlx5_ib_xrcd *xrcd;
4544 int err;
4545
938fe83c 4546 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4547 return ERR_PTR(-ENOSYS);
4548
4549 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4550 if (!xrcd)
4551 return ERR_PTR(-ENOMEM);
4552
9603b61d 4553 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4554 if (err) {
4555 kfree(xrcd);
4556 return ERR_PTR(-ENOMEM);
4557 }
4558
4559 return &xrcd->ibxrcd;
4560}
4561
4562int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4563{
4564 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4565 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4566 int err;
4567
9603b61d 4568 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4569 if (err) {
4570 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4571 return err;
4572 }
4573
4574 kfree(xrcd);
4575
4576 return 0;
4577}
79b20a6c 4578
350d0e4c
YH		 4579static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4580{
4581 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4582 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4583 struct ib_event event;
4584
4585 if (rwq->ibwq.event_handler) {
4586 event.device = rwq->ibwq.device;
4587 event.element.wq = &rwq->ibwq;
4588 switch (type) {
4589 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4590 event.event = IB_EVENT_WQ_FATAL;
4591 break;
4592 default:
4593 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4594 return;
4595 }
4596
4597 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4598 }
4599}
4600
79b20a6c
YH		 4601static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4602 struct ib_wq_init_attr *init_attr)
4603{
4604 struct mlx5_ib_dev *dev;
4be6da1e 4605 int has_net_offloads;
79b20a6c
YH		 4606 __be64 *rq_pas0;
4607 void *in;
4608 void *rqc;
4609 void *wq;
4610 int inlen;
4611 int err;
4612
4613 dev = to_mdev(pd->device);
4614
4615 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 4616 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 4617 if (!in)
4618 return -ENOMEM;
4619
4620 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4621 MLX5_SET(rqc, rqc, mem_rq_type,
4622 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4623 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4624 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4625 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4626 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4627 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4628 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4629 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4630 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4631 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4632 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4633 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4634 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4635 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4636 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4637 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4638 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4639 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4640 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4641 err = -EOPNOTSUPP;
4642 goto out;
4643 }
4644 } else {
4645 MLX5_SET(rqc, rqc, vsd, 1);
4646 }
4be6da1e
NO		 4647 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4648 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4649 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4650 err = -EOPNOTSUPP;
4651 goto out;
4652 }
4653 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4654 }
79b20a6c
YH		 4655 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4656 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 4657 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
b1f74a84 4658out:
79b20a6c
YH		 4659 kvfree(in);
4660 return err;
4661}
4662
4663static int set_user_rq_size(struct mlx5_ib_dev *dev,
4664 struct ib_wq_init_attr *wq_init_attr,
4665 struct mlx5_ib_create_wq *ucmd,
4666 struct mlx5_ib_rwq *rwq)
4667{
4668 /* Sanity check RQ size before proceeding */
4669 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4670 return -EINVAL;
4671
4672 if (!ucmd->rq_wqe_count)
4673 return -EINVAL;
4674
4675 rwq->wqe_count = ucmd->rq_wqe_count;
4676 rwq->wqe_shift = ucmd->rq_wqe_shift;
4677 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4678 rwq->log_rq_stride = rwq->wqe_shift;
4679 rwq->log_rq_size = ilog2(rwq->wqe_count);
4680 return 0;
4681}
4682
4683static int prepare_user_rq(struct ib_pd *pd,
4684 struct ib_wq_init_attr *init_attr,
4685 struct ib_udata *udata,
4686 struct mlx5_ib_rwq *rwq)
4687{
4688 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4689 struct mlx5_ib_create_wq ucmd = {};
4690 int err;
4691 size_t required_cmd_sz;
4692
4693 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4694 if (udata->inlen < required_cmd_sz) {
4695 mlx5_ib_dbg(dev, "invalid inlen\n");
4696 return -EINVAL;
4697 }
4698
4699 if (udata->inlen > sizeof(ucmd) &&
4700 !ib_is_udata_cleared(udata, sizeof(ucmd),
4701 udata->inlen - sizeof(ucmd))) {
4702 mlx5_ib_dbg(dev, "inlen is not supported\n");
4703 return -EOPNOTSUPP;
4704 }
4705
4706 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4707 mlx5_ib_dbg(dev, "copy failed\n");
4708 return -EFAULT;
4709 }
4710
4711 if (ucmd.comp_mask) {
4712 mlx5_ib_dbg(dev, "invalid comp mask\n");
4713 return -EOPNOTSUPP;
4714 }
4715
4716 if (ucmd.reserved) {
4717 mlx5_ib_dbg(dev, "invalid reserved\n");
4718 return -EOPNOTSUPP;
4719 }
4720
4721 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4722 if (err) {
4723 mlx5_ib_dbg(dev, "err %d\n", err);
4724 return err;
4725 }
4726
4727 err = create_user_rq(dev, pd, rwq, &ucmd);
4728 if (err) {
4729 mlx5_ib_dbg(dev, "err %d\n", err);
4730 if (err)
4731 return err;
4732 }
4733
4734 rwq->user_index = ucmd.user_index;
4735 return 0;
4736}
4737
4738struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4739 struct ib_wq_init_attr *init_attr,
4740 struct ib_udata *udata)
4741{
4742 struct mlx5_ib_dev *dev;
4743 struct mlx5_ib_rwq *rwq;
4744 struct mlx5_ib_create_wq_resp resp = {};
4745 size_t min_resp_len;
4746 int err;
4747
4748 if (!udata)
4749 return ERR_PTR(-ENOSYS);
4750
4751 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4752 if (udata->outlen && udata->outlen < min_resp_len)
4753 return ERR_PTR(-EINVAL);
4754
4755 dev = to_mdev(pd->device);
4756 switch (init_attr->wq_type) {
4757 case IB_WQT_RQ:
4758 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4759 if (!rwq)
4760 return ERR_PTR(-ENOMEM);
4761 err = prepare_user_rq(pd, init_attr, udata, rwq);
4762 if (err)
4763 goto err;
4764 err = create_rq(rwq, pd, init_attr);
4765 if (err)
4766 goto err_user_rq;
4767 break;
4768 default:
4769 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4770 init_attr->wq_type);
4771 return ERR_PTR(-EINVAL);
4772 }
4773
350d0e4c 4774 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 4775 rwq->ibwq.state = IB_WQS_RESET;
4776 if (udata->outlen) {
4777 resp.response_length = offsetof(typeof(resp), response_length) +
4778 sizeof(resp.response_length);
4779 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4780 if (err)
4781 goto err_copy;
4782 }
4783
350d0e4c
YH		 4784 rwq->core_qp.event = mlx5_ib_wq_event;
4785 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 4786 return &rwq->ibwq;
4787
4788err_copy:
350d0e4c 4789 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4790err_user_rq:
4791 destroy_user_rq(pd, rwq);
4792err:
4793 kfree(rwq);
4794 return ERR_PTR(err);
4795}
4796
4797int mlx5_ib_destroy_wq(struct ib_wq *wq)
4798{
4799 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4800 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4801
350d0e4c 4802 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4803 destroy_user_rq(wq->pd, rwq);
4804 kfree(rwq);
4805
4806 return 0;
4807}
4808
c5f90929
YH		 4809struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4810 struct ib_rwq_ind_table_init_attr *init_attr,
4811 struct ib_udata *udata)
4812{
4813 struct mlx5_ib_dev *dev = to_mdev(device);
4814 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4815 int sz = 1 << init_attr->log_ind_tbl_size;
4816 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4817 size_t min_resp_len;
4818 int inlen;
4819 int err;
4820 int i;
4821 u32 *in;
4822 void *rqtc;
4823
4824 if (udata->inlen > 0 &&
4825 !ib_is_udata_cleared(udata, 0,
4826 udata->inlen))
4827 return ERR_PTR(-EOPNOTSUPP);
4828
efd7f400
MG		 4829 if (init_attr->log_ind_tbl_size >
4830 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4831 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4832 init_attr->log_ind_tbl_size,
4833 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4834 return ERR_PTR(-EINVAL);
4835 }
4836
c5f90929
YH		 4837 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4838 if (udata->outlen && udata->outlen < min_resp_len)
4839 return ERR_PTR(-EINVAL);
4840
4841 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4842 if (!rwq_ind_tbl)
4843 return ERR_PTR(-ENOMEM);
4844
4845 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 4846 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 4847 if (!in) {
4848 err = -ENOMEM;
4849 goto err;
4850 }
4851
4852 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4853
4854 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4855 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4856
4857 for (i = 0; i < sz; i++)
4858 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4859
4860 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4861 kvfree(in);
4862
4863 if (err)
4864 goto err;
4865
4866 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4867 if (udata->outlen) {
4868 resp.response_length = offsetof(typeof(resp), response_length) +
4869 sizeof(resp.response_length);
4870 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4871 if (err)
4872 goto err_copy;
4873 }
4874
4875 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4876
4877err_copy:
4878 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4879err:
4880 kfree(rwq_ind_tbl);
4881 return ERR_PTR(err);
4882}
4883
4884int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4885{
4886 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4887 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4888
4889 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4890
4891 kfree(rwq_ind_tbl);
4892 return 0;
4893}
4894
79b20a6c
YH		 4895int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4896 u32 wq_attr_mask, struct ib_udata *udata)
4897{
4898 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4899 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4900 struct mlx5_ib_modify_wq ucmd = {};
4901 size_t required_cmd_sz;
4902 int curr_wq_state;
4903 int wq_state;
4904 int inlen;
4905 int err;
4906 void *rqc;
4907 void *in;
4908
4909 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4910 if (udata->inlen < required_cmd_sz)
4911 return -EINVAL;
4912
4913 if (udata->inlen > sizeof(ucmd) &&
4914 !ib_is_udata_cleared(udata, sizeof(ucmd),
4915 udata->inlen - sizeof(ucmd)))
4916 return -EOPNOTSUPP;
4917
4918 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4919 return -EFAULT;
4920
4921 if (ucmd.comp_mask || ucmd.reserved)
4922 return -EOPNOTSUPP;
4923
4924 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 4925 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 4926 if (!in)
4927 return -ENOMEM;
4928
4929 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4930
4931 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4932 wq_attr->curr_wq_state : wq->state;
4933 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4934 wq_attr->wq_state : curr_wq_state;
4935 if (curr_wq_state == IB_WQS_ERR)
4936 curr_wq_state = MLX5_RQC_STATE_ERR;
4937 if (wq_state == IB_WQS_ERR)
4938 wq_state = MLX5_RQC_STATE_ERR;
4939 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4940 MLX5_SET(rqc, rqc, state, wq_state);
4941
b1f74a84
NO		 4942 if (wq_attr_mask & IB_WQ_FLAGS) {
4943 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4944 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
4945 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4946 mlx5_ib_dbg(dev, "VLAN offloads are not "
4947 "supported\n");
4948 err = -EOPNOTSUPP;
4949 goto out;
4950 }
4951 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4952 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
4953 MLX5_SET(rqc, rqc, vsd,
4954 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
4955 }
4956 }
4957
23a6964e
MD		 4958 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
4959 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
4960 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4961 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 4962 MLX5_SET(rqc, rqc, counter_set_id,
4963 dev->port->cnts.set_id);
23a6964e
MD		 4964 } else
4965 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
4966 dev->ib_dev.name);
4967 }
4968
350d0e4c 4969 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 4970 if (!err)
4971 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4972
b1f74a84
NO		 4973out:
4974 kvfree(in);
79b20a6c
YH		 4975 return err;
4976}
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