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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
2a1d9b7f | 3 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
4885bf64 | 4 | * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. |
1da177e4 LT |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
1da177e4 LT |
33 | */ |
34 | ||
2a214182 | 35 | #include <linux/completion.h> |
1da177e4 LT |
36 | #include <linux/pci.h> |
37 | #include <linux/errno.h> | |
e8edc6e0 | 38 | #include <linux/sched.h> |
e4dd23d7 | 39 | #include <linux/module.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
1da177e4 | 41 | #include <asm/io.h> |
a4d61e84 | 42 | #include <rdma/ib_mad.h> |
1da177e4 LT |
43 | |
44 | #include "mthca_dev.h" | |
45 | #include "mthca_config_reg.h" | |
46 | #include "mthca_cmd.h" | |
47 | #include "mthca_memfree.h" | |
48 | ||
49 | #define CMD_POLL_TOKEN 0xffff | |
50 | ||
51 | enum { | |
52 | HCR_IN_PARAM_OFFSET = 0x00, | |
53 | HCR_IN_MODIFIER_OFFSET = 0x08, | |
54 | HCR_OUT_PARAM_OFFSET = 0x0c, | |
55 | HCR_TOKEN_OFFSET = 0x14, | |
56 | HCR_STATUS_OFFSET = 0x18, | |
57 | ||
58 | HCR_OPMOD_SHIFT = 12, | |
59 | HCA_E_BIT = 22, | |
60 | HCR_GO_BIT = 23 | |
61 | }; | |
62 | ||
63 | enum { | |
64 | /* initialization and general commands */ | |
65 | CMD_SYS_EN = 0x1, | |
66 | CMD_SYS_DIS = 0x2, | |
67 | CMD_MAP_FA = 0xfff, | |
68 | CMD_UNMAP_FA = 0xffe, | |
69 | CMD_RUN_FW = 0xff6, | |
70 | CMD_MOD_STAT_CFG = 0x34, | |
71 | CMD_QUERY_DEV_LIM = 0x3, | |
72 | CMD_QUERY_FW = 0x4, | |
73 | CMD_ENABLE_LAM = 0xff8, | |
74 | CMD_DISABLE_LAM = 0xff7, | |
75 | CMD_QUERY_DDR = 0x5, | |
76 | CMD_QUERY_ADAPTER = 0x6, | |
77 | CMD_INIT_HCA = 0x7, | |
78 | CMD_CLOSE_HCA = 0x8, | |
79 | CMD_INIT_IB = 0x9, | |
80 | CMD_CLOSE_IB = 0xa, | |
81 | CMD_QUERY_HCA = 0xb, | |
82 | CMD_SET_IB = 0xc, | |
83 | CMD_ACCESS_DDR = 0x2e, | |
84 | CMD_MAP_ICM = 0xffa, | |
85 | CMD_UNMAP_ICM = 0xff9, | |
86 | CMD_MAP_ICM_AUX = 0xffc, | |
87 | CMD_UNMAP_ICM_AUX = 0xffb, | |
88 | CMD_SET_ICM_SIZE = 0xffd, | |
89 | ||
90 | /* TPT commands */ | |
91 | CMD_SW2HW_MPT = 0xd, | |
92 | CMD_QUERY_MPT = 0xe, | |
93 | CMD_HW2SW_MPT = 0xf, | |
94 | CMD_READ_MTT = 0x10, | |
95 | CMD_WRITE_MTT = 0x11, | |
96 | CMD_SYNC_TPT = 0x2f, | |
97 | ||
98 | /* EQ commands */ | |
99 | CMD_MAP_EQ = 0x12, | |
100 | CMD_SW2HW_EQ = 0x13, | |
101 | CMD_HW2SW_EQ = 0x14, | |
102 | CMD_QUERY_EQ = 0x15, | |
103 | ||
104 | /* CQ commands */ | |
105 | CMD_SW2HW_CQ = 0x16, | |
106 | CMD_HW2SW_CQ = 0x17, | |
107 | CMD_QUERY_CQ = 0x18, | |
108 | CMD_RESIZE_CQ = 0x2c, | |
109 | ||
110 | /* SRQ commands */ | |
111 | CMD_SW2HW_SRQ = 0x35, | |
112 | CMD_HW2SW_SRQ = 0x36, | |
113 | CMD_QUERY_SRQ = 0x37, | |
ec34a922 | 114 | CMD_ARM_SRQ = 0x40, |
1da177e4 LT |
115 | |
116 | /* QP/EE commands */ | |
117 | CMD_RST2INIT_QPEE = 0x19, | |
118 | CMD_INIT2RTR_QPEE = 0x1a, | |
119 | CMD_RTR2RTS_QPEE = 0x1b, | |
120 | CMD_RTS2RTS_QPEE = 0x1c, | |
121 | CMD_SQERR2RTS_QPEE = 0x1d, | |
122 | CMD_2ERR_QPEE = 0x1e, | |
123 | CMD_RTS2SQD_QPEE = 0x1f, | |
124 | CMD_SQD2SQD_QPEE = 0x38, | |
125 | CMD_SQD2RTS_QPEE = 0x20, | |
126 | CMD_ERR2RST_QPEE = 0x21, | |
127 | CMD_QUERY_QPEE = 0x22, | |
128 | CMD_INIT2INIT_QPEE = 0x2d, | |
129 | CMD_SUSPEND_QPEE = 0x32, | |
130 | CMD_UNSUSPEND_QPEE = 0x33, | |
131 | /* special QPs and management commands */ | |
132 | CMD_CONF_SPECIAL_QP = 0x23, | |
133 | CMD_MAD_IFC = 0x24, | |
134 | ||
135 | /* multicast commands */ | |
136 | CMD_READ_MGM = 0x25, | |
137 | CMD_WRITE_MGM = 0x26, | |
138 | CMD_MGID_HASH = 0x27, | |
139 | ||
140 | /* miscellaneous commands */ | |
141 | CMD_DIAG_RPRT = 0x30, | |
142 | CMD_NOP = 0x31, | |
143 | ||
144 | /* debug commands */ | |
145 | CMD_QUERY_DEBUG_MSG = 0x2a, | |
146 | CMD_SET_DEBUG_MSG = 0x2b, | |
147 | }; | |
148 | ||
149 | /* | |
150 | * According to Mellanox code, FW may be starved and never complete | |
151 | * commands. So we can't use strict timeouts described in PRM -- we | |
152 | * just arbitrarily select 60 seconds for now. | |
153 | */ | |
154 | #if 0 | |
155 | /* | |
156 | * Round up and add 1 to make sure we get the full wait time (since we | |
157 | * will be starting in the middle of a jiffy) | |
158 | */ | |
159 | enum { | |
160 | CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1, | |
161 | CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1, | |
8531f1f1 JM |
162 | CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1, |
163 | CMD_TIME_CLASS_D = 60 * HZ | |
1da177e4 LT |
164 | }; |
165 | #else | |
166 | enum { | |
167 | CMD_TIME_CLASS_A = 60 * HZ, | |
168 | CMD_TIME_CLASS_B = 60 * HZ, | |
8531f1f1 JM |
169 | CMD_TIME_CLASS_C = 60 * HZ, |
170 | CMD_TIME_CLASS_D = 60 * HZ | |
1da177e4 LT |
171 | }; |
172 | #endif | |
173 | ||
174 | enum { | |
175 | GO_BIT_TIMEOUT = HZ * 10 | |
176 | }; | |
177 | ||
178 | struct mthca_cmd_context { | |
179 | struct completion done; | |
1da177e4 LT |
180 | int result; |
181 | int next; | |
182 | u64 out_param; | |
183 | u16 token; | |
184 | u8 status; | |
185 | }; | |
186 | ||
1db76c14 | 187 | static int fw_cmd_doorbell = 0; |
14abdffc EC |
188 | module_param(fw_cmd_doorbell, int, 0644); |
189 | MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero " | |
190 | "(and supported by FW)"); | |
191 | ||
1da177e4 LT |
192 | static inline int go_bit(struct mthca_dev *dev) |
193 | { | |
194 | return readl(dev->hcr + HCR_STATUS_OFFSET) & | |
195 | swab32(1 << HCR_GO_BIT); | |
196 | } | |
197 | ||
14abdffc EC |
198 | static void mthca_cmd_post_dbell(struct mthca_dev *dev, |
199 | u64 in_param, | |
200 | u64 out_param, | |
201 | u32 in_modifier, | |
202 | u8 op_modifier, | |
203 | u16 op, | |
204 | u16 token) | |
1da177e4 | 205 | { |
14abdffc EC |
206 | void __iomem *ptr = dev->cmd.dbell_map; |
207 | u16 *offs = dev->cmd.dbell_offsets; | |
1da177e4 | 208 | |
14abdffc EC |
209 | __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]); |
210 | wmb(); | |
211 | __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]); | |
212 | wmb(); | |
213 | __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]); | |
214 | wmb(); | |
215 | __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]); | |
216 | wmb(); | |
217 | __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]); | |
218 | wmb(); | |
219 | __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]); | |
220 | wmb(); | |
221 | __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | | |
222 | (1 << HCA_E_BIT) | | |
223 | (op_modifier << HCR_OPMOD_SHIFT) | | |
b3999393 | 224 | op), ptr + offs[6]); |
14abdffc EC |
225 | wmb(); |
226 | __raw_writel((__force u32) 0, ptr + offs[7]); | |
227 | wmb(); | |
228 | } | |
1da177e4 | 229 | |
14abdffc EC |
230 | static int mthca_cmd_post_hcr(struct mthca_dev *dev, |
231 | u64 in_param, | |
232 | u64 out_param, | |
233 | u32 in_modifier, | |
234 | u8 op_modifier, | |
235 | u16 op, | |
236 | u16 token, | |
237 | int event) | |
238 | { | |
1da177e4 LT |
239 | if (event) { |
240 | unsigned long end = jiffies + GO_BIT_TIMEOUT; | |
241 | ||
242 | while (go_bit(dev) && time_before(jiffies, end)) { | |
243 | set_current_state(TASK_RUNNING); | |
244 | schedule(); | |
245 | } | |
246 | } | |
247 | ||
14abdffc EC |
248 | if (go_bit(dev)) |
249 | return -EAGAIN; | |
1da177e4 LT |
250 | |
251 | /* | |
252 | * We use writel (instead of something like memcpy_toio) | |
253 | * because writes of less than 32 bits to the HCR don't work | |
254 | * (and some architectures such as ia64 implement memcpy_toio | |
255 | * in terms of writeb). | |
256 | */ | |
97f52eb4 SH |
257 | __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); |
258 | __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); | |
259 | __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); | |
260 | __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); | |
261 | __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); | |
262 | __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); | |
1da177e4 LT |
263 | |
264 | /* __raw_writel may not order writes. */ | |
265 | wmb(); | |
266 | ||
97f52eb4 SH |
267 | __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | |
268 | (event ? (1 << HCA_E_BIT) : 0) | | |
269 | (op_modifier << HCR_OPMOD_SHIFT) | | |
270 | op), dev->hcr + 6 * 4); | |
1da177e4 | 271 | |
14abdffc EC |
272 | return 0; |
273 | } | |
274 | ||
275 | static int mthca_cmd_post(struct mthca_dev *dev, | |
276 | u64 in_param, | |
277 | u64 out_param, | |
278 | u32 in_modifier, | |
279 | u8 op_modifier, | |
280 | u16 op, | |
281 | u16 token, | |
282 | int event) | |
283 | { | |
284 | int err = 0; | |
285 | ||
286 | mutex_lock(&dev->cmd.hcr_mutex); | |
287 | ||
288 | if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell) | |
289 | mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier, | |
290 | op_modifier, op, token); | |
291 | else | |
292 | err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier, | |
293 | op_modifier, op, token, event); | |
294 | ||
76d7cc03 RD |
295 | /* |
296 | * Make sure that our HCR writes don't get mixed in with | |
297 | * writes from another CPU starting a FW command. | |
298 | */ | |
299 | mmiowb(); | |
300 | ||
fd9cfdd1 | 301 | mutex_unlock(&dev->cmd.hcr_mutex); |
1da177e4 LT |
302 | return err; |
303 | } | |
304 | ||
cdb73db0 GR |
305 | |
306 | static int mthca_status_to_errno(u8 status) | |
307 | { | |
308 | static const int trans_table[] = { | |
309 | [MTHCA_CMD_STAT_INTERNAL_ERR] = -EIO, | |
310 | [MTHCA_CMD_STAT_BAD_OP] = -EPERM, | |
311 | [MTHCA_CMD_STAT_BAD_PARAM] = -EINVAL, | |
312 | [MTHCA_CMD_STAT_BAD_SYS_STATE] = -ENXIO, | |
313 | [MTHCA_CMD_STAT_BAD_RESOURCE] = -EBADF, | |
314 | [MTHCA_CMD_STAT_RESOURCE_BUSY] = -EBUSY, | |
315 | [MTHCA_CMD_STAT_DDR_MEM_ERR] = -ENOMEM, | |
316 | [MTHCA_CMD_STAT_EXCEED_LIM] = -ENOMEM, | |
317 | [MTHCA_CMD_STAT_BAD_RES_STATE] = -EBADF, | |
318 | [MTHCA_CMD_STAT_BAD_INDEX] = -EBADF, | |
319 | [MTHCA_CMD_STAT_BAD_NVMEM] = -EFAULT, | |
320 | [MTHCA_CMD_STAT_BAD_QPEE_STATE] = -EINVAL, | |
321 | [MTHCA_CMD_STAT_BAD_SEG_PARAM] = -EFAULT, | |
322 | [MTHCA_CMD_STAT_REG_BOUND] = -EBUSY, | |
323 | [MTHCA_CMD_STAT_LAM_NOT_PRE] = -EAGAIN, | |
324 | [MTHCA_CMD_STAT_BAD_PKT] = -EBADMSG, | |
325 | [MTHCA_CMD_STAT_BAD_SIZE] = -ENOMEM, | |
326 | }; | |
327 | ||
328 | if (status >= ARRAY_SIZE(trans_table) || | |
329 | (status != MTHCA_CMD_STAT_OK | |
330 | && trans_table[status] == 0)) | |
331 | return -EINVAL; | |
332 | ||
333 | return trans_table[status]; | |
334 | } | |
335 | ||
336 | ||
1da177e4 LT |
337 | static int mthca_cmd_poll(struct mthca_dev *dev, |
338 | u64 in_param, | |
339 | u64 *out_param, | |
340 | int out_is_imm, | |
341 | u32 in_modifier, | |
342 | u8 op_modifier, | |
343 | u16 op, | |
cdb73db0 | 344 | unsigned long timeout) |
1da177e4 LT |
345 | { |
346 | int err = 0; | |
347 | unsigned long end; | |
cdb73db0 | 348 | u8 status; |
1da177e4 | 349 | |
e3aa31c5 | 350 | down(&dev->cmd.poll_sem); |
1da177e4 LT |
351 | |
352 | err = mthca_cmd_post(dev, in_param, | |
353 | out_param ? *out_param : 0, | |
354 | in_modifier, op_modifier, | |
355 | op, CMD_POLL_TOKEN, 0); | |
356 | if (err) | |
357 | goto out; | |
358 | ||
359 | end = timeout + jiffies; | |
360 | while (go_bit(dev) && time_before(jiffies, end)) { | |
361 | set_current_state(TASK_RUNNING); | |
362 | schedule(); | |
363 | } | |
364 | ||
365 | if (go_bit(dev)) { | |
366 | err = -EBUSY; | |
367 | goto out; | |
368 | } | |
369 | ||
97f52eb4 | 370 | if (out_is_imm) |
2fa5e2eb | 371 | *out_param = |
97f52eb4 SH |
372 | (u64) be32_to_cpu((__force __be32) |
373 | __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | | |
374 | (u64) be32_to_cpu((__force __be32) | |
375 | __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); | |
1da177e4 | 376 | |
cdb73db0 GR |
377 | status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; |
378 | if (status) { | |
379 | mthca_dbg(dev, "Command %02x completed with status %02x\n", | |
380 | op, status); | |
381 | err = mthca_status_to_errno(status); | |
382 | } | |
1da177e4 LT |
383 | |
384 | out: | |
385 | up(&dev->cmd.poll_sem); | |
386 | return err; | |
387 | } | |
388 | ||
389 | void mthca_cmd_event(struct mthca_dev *dev, | |
390 | u16 token, | |
391 | u8 status, | |
392 | u64 out_param) | |
393 | { | |
394 | struct mthca_cmd_context *context = | |
395 | &dev->cmd.context[token & dev->cmd.token_mask]; | |
396 | ||
397 | /* previously timed out command completing at long last */ | |
398 | if (token != context->token) | |
399 | return; | |
400 | ||
401 | context->result = 0; | |
402 | context->status = status; | |
403 | context->out_param = out_param; | |
404 | ||
1da177e4 LT |
405 | complete(&context->done); |
406 | } | |
407 | ||
1da177e4 LT |
408 | static int mthca_cmd_wait(struct mthca_dev *dev, |
409 | u64 in_param, | |
410 | u64 *out_param, | |
411 | int out_is_imm, | |
412 | u32 in_modifier, | |
413 | u8 op_modifier, | |
414 | u16 op, | |
cdb73db0 | 415 | unsigned long timeout) |
1da177e4 LT |
416 | { |
417 | int err = 0; | |
418 | struct mthca_cmd_context *context; | |
419 | ||
e3aa31c5 | 420 | down(&dev->cmd.event_sem); |
1da177e4 LT |
421 | |
422 | spin_lock(&dev->cmd.context_lock); | |
423 | BUG_ON(dev->cmd.free_head < 0); | |
424 | context = &dev->cmd.context[dev->cmd.free_head]; | |
c1f74958 | 425 | context->token += dev->cmd.token_mask + 1; |
1da177e4 LT |
426 | dev->cmd.free_head = context->next; |
427 | spin_unlock(&dev->cmd.context_lock); | |
428 | ||
429 | init_completion(&context->done); | |
430 | ||
431 | err = mthca_cmd_post(dev, in_param, | |
432 | out_param ? *out_param : 0, | |
433 | in_modifier, op_modifier, | |
434 | op, context->token, 1); | |
435 | if (err) | |
436 | goto out; | |
437 | ||
e9cd5941 RD |
438 | if (!wait_for_completion_timeout(&context->done, timeout)) { |
439 | err = -EBUSY; | |
440 | goto out; | |
441 | } | |
1da177e4 LT |
442 | |
443 | err = context->result; | |
444 | if (err) | |
445 | goto out; | |
446 | ||
cdb73db0 | 447 | if (context->status) { |
1da177e4 | 448 | mthca_dbg(dev, "Command %02x completed with status %02x\n", |
cdb73db0 GR |
449 | op, context->status); |
450 | err = mthca_status_to_errno(context->status); | |
451 | } | |
1da177e4 LT |
452 | |
453 | if (out_is_imm) | |
454 | *out_param = context->out_param; | |
455 | ||
456 | out: | |
457 | spin_lock(&dev->cmd.context_lock); | |
458 | context->next = dev->cmd.free_head; | |
459 | dev->cmd.free_head = context - dev->cmd.context; | |
460 | spin_unlock(&dev->cmd.context_lock); | |
461 | ||
462 | up(&dev->cmd.event_sem); | |
463 | return err; | |
464 | } | |
465 | ||
466 | /* Invoke a command with an output mailbox */ | |
467 | static int mthca_cmd_box(struct mthca_dev *dev, | |
468 | u64 in_param, | |
469 | u64 out_param, | |
470 | u32 in_modifier, | |
471 | u8 op_modifier, | |
472 | u16 op, | |
cdb73db0 | 473 | unsigned long timeout) |
1da177e4 | 474 | { |
14abdffc | 475 | if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) |
1da177e4 LT |
476 | return mthca_cmd_wait(dev, in_param, &out_param, 0, |
477 | in_modifier, op_modifier, op, | |
cdb73db0 | 478 | timeout); |
1da177e4 LT |
479 | else |
480 | return mthca_cmd_poll(dev, in_param, &out_param, 0, | |
481 | in_modifier, op_modifier, op, | |
cdb73db0 | 482 | timeout); |
1da177e4 LT |
483 | } |
484 | ||
485 | /* Invoke a command with no output parameter */ | |
486 | static int mthca_cmd(struct mthca_dev *dev, | |
487 | u64 in_param, | |
488 | u32 in_modifier, | |
489 | u8 op_modifier, | |
490 | u16 op, | |
cdb73db0 | 491 | unsigned long timeout) |
1da177e4 LT |
492 | { |
493 | return mthca_cmd_box(dev, in_param, 0, in_modifier, | |
cdb73db0 | 494 | op_modifier, op, timeout); |
1da177e4 LT |
495 | } |
496 | ||
497 | /* | |
498 | * Invoke a command with an immediate output parameter (and copy the | |
499 | * output into the caller's out_param pointer after the command | |
500 | * executes). | |
501 | */ | |
502 | static int mthca_cmd_imm(struct mthca_dev *dev, | |
503 | u64 in_param, | |
504 | u64 *out_param, | |
505 | u32 in_modifier, | |
506 | u8 op_modifier, | |
507 | u16 op, | |
cdb73db0 | 508 | unsigned long timeout) |
1da177e4 | 509 | { |
14abdffc | 510 | if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) |
1da177e4 LT |
511 | return mthca_cmd_wait(dev, in_param, out_param, 1, |
512 | in_modifier, op_modifier, op, | |
cdb73db0 | 513 | timeout); |
1da177e4 LT |
514 | else |
515 | return mthca_cmd_poll(dev, in_param, out_param, 1, | |
516 | in_modifier, op_modifier, op, | |
cdb73db0 | 517 | timeout); |
1da177e4 LT |
518 | } |
519 | ||
80fd8238 RD |
520 | int mthca_cmd_init(struct mthca_dev *dev) |
521 | { | |
fd9cfdd1 | 522 | mutex_init(&dev->cmd.hcr_mutex); |
80fd8238 | 523 | sema_init(&dev->cmd.poll_sem, 1); |
14abdffc | 524 | dev->cmd.flags = 0; |
80fd8238 RD |
525 | |
526 | dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, | |
527 | MTHCA_HCR_SIZE); | |
528 | if (!dev->hcr) { | |
529 | mthca_err(dev, "Couldn't map command register."); | |
530 | return -ENOMEM; | |
531 | } | |
532 | ||
ed878458 RD |
533 | dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev, |
534 | MTHCA_MAILBOX_SIZE, | |
535 | MTHCA_MAILBOX_SIZE, 0); | |
536 | if (!dev->cmd.pool) { | |
537 | iounmap(dev->hcr); | |
538 | return -ENOMEM; | |
539 | } | |
540 | ||
80fd8238 RD |
541 | return 0; |
542 | } | |
543 | ||
544 | void mthca_cmd_cleanup(struct mthca_dev *dev) | |
545 | { | |
ed878458 | 546 | pci_pool_destroy(dev->cmd.pool); |
80fd8238 | 547 | iounmap(dev->hcr); |
14abdffc EC |
548 | if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS) |
549 | iounmap(dev->cmd.dbell_map); | |
80fd8238 RD |
550 | } |
551 | ||
1da177e4 LT |
552 | /* |
553 | * Switch to using events to issue FW commands (should be called after | |
554 | * event queue to command events has been initialized). | |
555 | */ | |
556 | int mthca_cmd_use_events(struct mthca_dev *dev) | |
557 | { | |
558 | int i; | |
559 | ||
560 | dev->cmd.context = kmalloc(dev->cmd.max_cmds * | |
561 | sizeof (struct mthca_cmd_context), | |
562 | GFP_KERNEL); | |
563 | if (!dev->cmd.context) | |
564 | return -ENOMEM; | |
565 | ||
566 | for (i = 0; i < dev->cmd.max_cmds; ++i) { | |
567 | dev->cmd.context[i].token = i; | |
568 | dev->cmd.context[i].next = i + 1; | |
1da177e4 LT |
569 | } |
570 | ||
571 | dev->cmd.context[dev->cmd.max_cmds - 1].next = -1; | |
572 | dev->cmd.free_head = 0; | |
573 | ||
574 | sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds); | |
575 | spin_lock_init(&dev->cmd.context_lock); | |
576 | ||
577 | for (dev->cmd.token_mask = 1; | |
578 | dev->cmd.token_mask < dev->cmd.max_cmds; | |
579 | dev->cmd.token_mask <<= 1) | |
580 | ; /* nothing */ | |
581 | --dev->cmd.token_mask; | |
582 | ||
14abdffc EC |
583 | dev->cmd.flags |= MTHCA_CMD_USE_EVENTS; |
584 | ||
1da177e4 LT |
585 | down(&dev->cmd.poll_sem); |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | /* | |
591 | * Switch back to polling (used when shutting down the device) | |
592 | */ | |
593 | void mthca_cmd_use_polling(struct mthca_dev *dev) | |
594 | { | |
595 | int i; | |
596 | ||
14abdffc | 597 | dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS; |
1da177e4 LT |
598 | |
599 | for (i = 0; i < dev->cmd.max_cmds; ++i) | |
600 | down(&dev->cmd.event_sem); | |
601 | ||
602 | kfree(dev->cmd.context); | |
603 | ||
604 | up(&dev->cmd.poll_sem); | |
605 | } | |
606 | ||
ed878458 | 607 | struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, |
87b750dc | 608 | gfp_t gfp_mask) |
ed878458 RD |
609 | { |
610 | struct mthca_mailbox *mailbox; | |
611 | ||
612 | mailbox = kmalloc(sizeof *mailbox, gfp_mask); | |
613 | if (!mailbox) | |
614 | return ERR_PTR(-ENOMEM); | |
615 | ||
616 | mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); | |
617 | if (!mailbox->buf) { | |
618 | kfree(mailbox); | |
619 | return ERR_PTR(-ENOMEM); | |
620 | } | |
621 | ||
622 | return mailbox; | |
623 | } | |
624 | ||
625 | void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) | |
626 | { | |
627 | if (!mailbox) | |
628 | return; | |
629 | ||
630 | pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); | |
631 | kfree(mailbox); | |
632 | } | |
633 | ||
cdb73db0 | 634 | int mthca_SYS_EN(struct mthca_dev *dev) |
1da177e4 LT |
635 | { |
636 | u64 out; | |
637 | int ret; | |
638 | ||
cdb73db0 | 639 | ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D); |
1da177e4 | 640 | |
cdb73db0 | 641 | if (ret == -ENOMEM) |
1da177e4 LT |
642 | mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, " |
643 | "sladdr=%d, SPD source=%s\n", | |
644 | (int) (out >> 6) & 0xf, (int) (out >> 4) & 3, | |
645 | (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM"); | |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
cdb73db0 | 650 | int mthca_SYS_DIS(struct mthca_dev *dev) |
1da177e4 | 651 | { |
cdb73db0 | 652 | return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C); |
1da177e4 LT |
653 | } |
654 | ||
655 | static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm, | |
cdb73db0 | 656 | u64 virt) |
1da177e4 | 657 | { |
ed878458 | 658 | struct mthca_mailbox *mailbox; |
1da177e4 | 659 | struct mthca_icm_iter iter; |
ed878458 | 660 | __be64 *pages; |
1da177e4 LT |
661 | int lg; |
662 | int nent = 0; | |
663 | int i; | |
664 | int err = 0; | |
665 | int ts = 0, tc = 0; | |
666 | ||
ed878458 RD |
667 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
668 | if (IS_ERR(mailbox)) | |
669 | return PTR_ERR(mailbox); | |
670 | memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE); | |
671 | pages = mailbox->buf; | |
1da177e4 LT |
672 | |
673 | for (mthca_icm_first(icm, &iter); | |
674 | !mthca_icm_last(&iter); | |
675 | mthca_icm_next(&iter)) { | |
676 | /* | |
677 | * We have to pass pages that are aligned to their | |
678 | * size, so find the least significant 1 in the | |
679 | * address or size and use that as our log2 size. | |
680 | */ | |
681 | lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1; | |
8d3ef29d IR |
682 | if (lg < MTHCA_ICM_PAGE_SHIFT) { |
683 | mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", | |
684 | MTHCA_ICM_PAGE_SIZE, | |
1da177e4 LT |
685 | (unsigned long long) mthca_icm_addr(&iter), |
686 | mthca_icm_size(&iter)); | |
687 | err = -EINVAL; | |
688 | goto out; | |
689 | } | |
59f174fa | 690 | for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) { |
1da177e4 | 691 | if (virt != -1) { |
ed878458 | 692 | pages[nent * 2] = cpu_to_be64(virt); |
1da177e4 LT |
693 | virt += 1 << lg; |
694 | } | |
695 | ||
8d3ef29d IR |
696 | pages[nent * 2 + 1] = |
697 | cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) | | |
698 | (lg - MTHCA_ICM_PAGE_SHIFT)); | |
1da177e4 LT |
699 | ts += 1 << (lg - 10); |
700 | ++tc; | |
701 | ||
44dd823b | 702 | if (++nent == MTHCA_MAILBOX_SIZE / 16) { |
ed878458 | 703 | err = mthca_cmd(dev, mailbox->dma, nent, 0, op, |
cdb73db0 GR |
704 | CMD_TIME_CLASS_B); |
705 | if (err) | |
1da177e4 LT |
706 | goto out; |
707 | nent = 0; | |
708 | } | |
709 | } | |
710 | } | |
711 | ||
712 | if (nent) | |
ed878458 | 713 | err = mthca_cmd(dev, mailbox->dma, nent, 0, op, |
cdb73db0 | 714 | CMD_TIME_CLASS_B); |
1da177e4 LT |
715 | |
716 | switch (op) { | |
717 | case CMD_MAP_FA: | |
718 | mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
719 | break; | |
720 | case CMD_MAP_ICM_AUX: | |
721 | mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
722 | break; | |
723 | case CMD_MAP_ICM: | |
724 | mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
725 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
726 | break; | |
727 | } | |
728 | ||
729 | out: | |
ed878458 | 730 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
731 | return err; |
732 | } | |
733 | ||
cdb73db0 | 734 | int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm) |
1da177e4 | 735 | { |
cdb73db0 | 736 | return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1); |
1da177e4 LT |
737 | } |
738 | ||
cdb73db0 | 739 | int mthca_UNMAP_FA(struct mthca_dev *dev) |
1da177e4 | 740 | { |
cdb73db0 | 741 | return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B); |
1da177e4 LT |
742 | } |
743 | ||
cdb73db0 | 744 | int mthca_RUN_FW(struct mthca_dev *dev) |
1da177e4 | 745 | { |
cdb73db0 | 746 | return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A); |
1da177e4 LT |
747 | } |
748 | ||
14abdffc EC |
749 | static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base) |
750 | { | |
eb4a7cbf | 751 | phys_addr_t addr; |
14abdffc EC |
752 | u16 max_off = 0; |
753 | int i; | |
754 | ||
755 | for (i = 0; i < 8; ++i) | |
756 | max_off = max(max_off, dev->cmd.dbell_offsets[i]); | |
757 | ||
758 | if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) { | |
759 | mthca_warn(dev, "Firmware doorbell region at 0x%016llx, " | |
760 | "length 0x%x crosses a page boundary\n", | |
761 | (unsigned long long) base, max_off); | |
762 | return; | |
763 | } | |
764 | ||
765 | addr = pci_resource_start(dev->pdev, 2) + | |
766 | ((pci_resource_len(dev->pdev, 2) - 1) & base); | |
767 | dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32)); | |
768 | if (!dev->cmd.dbell_map) | |
769 | return; | |
770 | ||
771 | dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS; | |
772 | mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n"); | |
773 | } | |
774 | ||
cdb73db0 | 775 | int mthca_QUERY_FW(struct mthca_dev *dev) |
1da177e4 | 776 | { |
ed878458 | 777 | struct mthca_mailbox *mailbox; |
1da177e4 | 778 | u32 *outbox; |
14abdffc EC |
779 | u64 base; |
780 | u32 tmp; | |
1da177e4 LT |
781 | int err = 0; |
782 | u8 lg; | |
14abdffc | 783 | int i; |
1da177e4 LT |
784 | |
785 | #define QUERY_FW_OUT_SIZE 0x100 | |
786 | #define QUERY_FW_VER_OFFSET 0x00 | |
787 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f | |
788 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
789 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
790 | ||
14abdffc EC |
791 | #define QUERY_FW_CMD_DB_EN_OFFSET 0x10 |
792 | #define QUERY_FW_CMD_DB_OFFSET 0x50 | |
793 | #define QUERY_FW_CMD_DB_BASE 0x60 | |
794 | ||
1da177e4 LT |
795 | #define QUERY_FW_START_OFFSET 0x20 |
796 | #define QUERY_FW_END_OFFSET 0x28 | |
797 | ||
798 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
799 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
800 | #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40 | |
801 | #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48 | |
802 | ||
ed878458 RD |
803 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
804 | if (IS_ERR(mailbox)) | |
805 | return PTR_ERR(mailbox); | |
806 | outbox = mailbox->buf; | |
1da177e4 | 807 | |
ed878458 | 808 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW, |
cdb73db0 | 809 | CMD_TIME_CLASS_A); |
1da177e4 LT |
810 | |
811 | if (err) | |
812 | goto out; | |
813 | ||
814 | MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
815 | /* | |
3e1db334 | 816 | * FW subminor version is at more significant bits than minor |
1da177e4 LT |
817 | * version, so swap here. |
818 | */ | |
819 | dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) | | |
820 | ((dev->fw_ver & 0xffff0000ull) >> 16) | | |
821 | ((dev->fw_ver & 0x0000ffffull) << 16); | |
822 | ||
8fdf679f RD |
823 | MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
824 | dev->cmd.max_cmds = 1 << lg; | |
825 | ||
14abdffc EC |
826 | mthca_dbg(dev, "FW version %012llx, max commands %d\n", |
827 | (unsigned long long) dev->fw_ver, dev->cmd.max_cmds); | |
828 | ||
3d155f8c RD |
829 | MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET); |
830 | MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
1da177e4 | 831 | |
3d155f8c RD |
832 | mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n", |
833 | (unsigned long long) dev->catas_err.addr, dev->catas_err.size); | |
1da177e4 | 834 | |
14abdffc EC |
835 | MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET); |
836 | if (tmp & 0x1) { | |
837 | mthca_dbg(dev, "FW supports commands through doorbells\n"); | |
838 | ||
839 | MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE); | |
840 | for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i) | |
841 | MTHCA_GET(dev->cmd.dbell_offsets[i], outbox, | |
842 | QUERY_FW_CMD_DB_OFFSET + (i << 1)); | |
843 | ||
844 | mthca_setup_cmd_doorbells(dev, base); | |
845 | } | |
846 | ||
d10ddbf6 | 847 | if (mthca_is_memfree(dev)) { |
1da177e4 LT |
848 | MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
849 | MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
850 | MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET); | |
851 | MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET); | |
852 | mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2); | |
853 | ||
854 | /* | |
8d3ef29d IR |
855 | * Round up number of system pages needed in case |
856 | * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. | |
1da177e4 LT |
857 | */ |
858 | dev->fw.arbel.fw_pages = | |
8d3ef29d IR |
859 | ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> |
860 | (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); | |
1da177e4 LT |
861 | |
862 | mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n", | |
863 | (unsigned long long) dev->fw.arbel.clr_int_base, | |
864 | (unsigned long long) dev->fw.arbel.eq_arm_base, | |
865 | (unsigned long long) dev->fw.arbel.eq_set_ci_base); | |
866 | } else { | |
867 | MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET); | |
868 | MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET); | |
869 | ||
870 | mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n", | |
871 | (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10), | |
872 | (unsigned long long) dev->fw.tavor.fw_start, | |
873 | (unsigned long long) dev->fw.tavor.fw_end); | |
874 | } | |
875 | ||
876 | out: | |
ed878458 | 877 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
878 | return err; |
879 | } | |
880 | ||
cdb73db0 | 881 | int mthca_ENABLE_LAM(struct mthca_dev *dev) |
1da177e4 | 882 | { |
ed878458 | 883 | struct mthca_mailbox *mailbox; |
1da177e4 LT |
884 | u8 info; |
885 | u32 *outbox; | |
1da177e4 LT |
886 | int err = 0; |
887 | ||
888 | #define ENABLE_LAM_OUT_SIZE 0x100 | |
889 | #define ENABLE_LAM_START_OFFSET 0x00 | |
890 | #define ENABLE_LAM_END_OFFSET 0x08 | |
891 | #define ENABLE_LAM_INFO_OFFSET 0x13 | |
892 | ||
893 | #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4) | |
894 | #define ENABLE_LAM_INFO_ECC_MASK 0x3 | |
895 | ||
ed878458 RD |
896 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
897 | if (IS_ERR(mailbox)) | |
898 | return PTR_ERR(mailbox); | |
899 | outbox = mailbox->buf; | |
1da177e4 | 900 | |
ed878458 | 901 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM, |
cdb73db0 | 902 | CMD_TIME_CLASS_C); |
1da177e4 LT |
903 | |
904 | if (err) | |
905 | goto out; | |
906 | ||
1da177e4 LT |
907 | MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET); |
908 | MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET); | |
909 | MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET); | |
910 | ||
911 | if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) != | |
912 | !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { | |
913 | mthca_info(dev, "FW reports that HCA-attached memory " | |
914 | "is %s hidden; does not match PCI config\n", | |
915 | (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ? | |
916 | "" : "not"); | |
917 | } | |
918 | if (info & ENABLE_LAM_INFO_HIDDEN_FLAG) | |
919 | mthca_dbg(dev, "HCA-attached memory is hidden.\n"); | |
920 | ||
921 | mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", | |
922 | (int) ((dev->ddr_end - dev->ddr_start) >> 10), | |
923 | (unsigned long long) dev->ddr_start, | |
924 | (unsigned long long) dev->ddr_end); | |
925 | ||
926 | out: | |
ed878458 | 927 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
928 | return err; |
929 | } | |
930 | ||
cdb73db0 | 931 | int mthca_DISABLE_LAM(struct mthca_dev *dev) |
1da177e4 | 932 | { |
cdb73db0 | 933 | return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C); |
1da177e4 LT |
934 | } |
935 | ||
cdb73db0 | 936 | int mthca_QUERY_DDR(struct mthca_dev *dev) |
1da177e4 | 937 | { |
ed878458 | 938 | struct mthca_mailbox *mailbox; |
1da177e4 LT |
939 | u8 info; |
940 | u32 *outbox; | |
1da177e4 LT |
941 | int err = 0; |
942 | ||
943 | #define QUERY_DDR_OUT_SIZE 0x100 | |
944 | #define QUERY_DDR_START_OFFSET 0x00 | |
945 | #define QUERY_DDR_END_OFFSET 0x08 | |
946 | #define QUERY_DDR_INFO_OFFSET 0x13 | |
947 | ||
948 | #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4) | |
949 | #define QUERY_DDR_INFO_ECC_MASK 0x3 | |
950 | ||
ed878458 RD |
951 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
952 | if (IS_ERR(mailbox)) | |
953 | return PTR_ERR(mailbox); | |
954 | outbox = mailbox->buf; | |
1da177e4 | 955 | |
ed878458 | 956 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR, |
cdb73db0 | 957 | CMD_TIME_CLASS_A); |
1da177e4 LT |
958 | |
959 | if (err) | |
960 | goto out; | |
961 | ||
962 | MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET); | |
963 | MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET); | |
964 | MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET); | |
965 | ||
966 | if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) != | |
967 | !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { | |
968 | mthca_info(dev, "FW reports that HCA-attached memory " | |
969 | "is %s hidden; does not match PCI config\n", | |
970 | (info & QUERY_DDR_INFO_HIDDEN_FLAG) ? | |
971 | "" : "not"); | |
972 | } | |
973 | if (info & QUERY_DDR_INFO_HIDDEN_FLAG) | |
974 | mthca_dbg(dev, "HCA-attached memory is hidden.\n"); | |
975 | ||
976 | mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", | |
977 | (int) ((dev->ddr_end - dev->ddr_start) >> 10), | |
978 | (unsigned long long) dev->ddr_start, | |
979 | (unsigned long long) dev->ddr_end); | |
980 | ||
981 | out: | |
ed878458 | 982 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
983 | return err; |
984 | } | |
985 | ||
986 | int mthca_QUERY_DEV_LIM(struct mthca_dev *dev, | |
cdb73db0 | 987 | struct mthca_dev_lim *dev_lim) |
1da177e4 | 988 | { |
ed878458 | 989 | struct mthca_mailbox *mailbox; |
1da177e4 | 990 | u32 *outbox; |
1da177e4 LT |
991 | u8 field; |
992 | u16 size; | |
bf6a9e31 | 993 | u16 stat_rate; |
1da177e4 LT |
994 | int err; |
995 | ||
996 | #define QUERY_DEV_LIM_OUT_SIZE 0x100 | |
997 | #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10 | |
998 | #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11 | |
999 | #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12 | |
1000 | #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13 | |
1001 | #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14 | |
1002 | #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15 | |
1003 | #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16 | |
1004 | #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17 | |
1005 | #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19 | |
1006 | #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a | |
1007 | #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b | |
1008 | #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d | |
1009 | #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e | |
1010 | #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f | |
1011 | #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20 | |
1012 | #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21 | |
1013 | #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22 | |
1014 | #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23 | |
1015 | #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27 | |
1016 | #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29 | |
1017 | #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b | |
1018 | #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f | |
1019 | #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33 | |
1020 | #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35 | |
1021 | #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36 | |
1022 | #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37 | |
1023 | #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b | |
bf6a9e31 | 1024 | #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c |
1da177e4 LT |
1025 | #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f |
1026 | #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44 | |
1027 | #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48 | |
1028 | #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49 | |
1029 | #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b | |
1030 | #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51 | |
1031 | #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52 | |
1032 | #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55 | |
1033 | #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
1034 | #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61 | |
1035 | #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62 | |
1036 | #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63 | |
1037 | #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64 | |
1038 | #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65 | |
1039 | #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66 | |
1040 | #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67 | |
1041 | #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80 | |
1042 | #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82 | |
1043 | #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84 | |
1044 | #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86 | |
1045 | #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88 | |
1046 | #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a | |
1047 | #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c | |
1048 | #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e | |
1049 | #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90 | |
1050 | #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92 | |
1051 | #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96 | |
1052 | #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97 | |
1053 | #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98 | |
1054 | #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f | |
1055 | #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0 | |
1056 | ||
ed878458 RD |
1057 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1058 | if (IS_ERR(mailbox)) | |
1059 | return PTR_ERR(mailbox); | |
1060 | outbox = mailbox->buf; | |
1da177e4 | 1061 | |
ed878458 | 1062 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, |
cdb73db0 | 1063 | CMD_TIME_CLASS_A); |
1da177e4 LT |
1064 | |
1065 | if (err) | |
1066 | goto out; | |
1067 | ||
1da177e4 LT |
1068 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET); |
1069 | dev_lim->reserved_qps = 1 << (field & 0xf); | |
1070 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET); | |
1071 | dev_lim->max_qps = 1 << (field & 0x1f); | |
1072 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET); | |
1073 | dev_lim->reserved_srqs = 1 << (field >> 4); | |
1074 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET); | |
1075 | dev_lim->max_srqs = 1 << (field & 0x1f); | |
1076 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET); | |
1077 | dev_lim->reserved_eecs = 1 << (field & 0xf); | |
1078 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET); | |
1079 | dev_lim->max_eecs = 1 << (field & 0x1f); | |
1080 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET); | |
1081 | dev_lim->max_cq_sz = 1 << field; | |
1082 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET); | |
1083 | dev_lim->reserved_cqs = 1 << (field & 0xf); | |
1084 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET); | |
1085 | dev_lim->max_cqs = 1 << (field & 0x1f); | |
1086 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET); | |
1087 | dev_lim->max_mpts = 1 << (field & 0x3f); | |
1088 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET); | |
1089 | dev_lim->reserved_eqs = 1 << (field & 0xf); | |
1090 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET); | |
1091 | dev_lim->max_eqs = 1 << (field & 0x7); | |
1092 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); | |
c7d204e8 MT |
1093 | if (mthca_is_memfree(dev)) |
1094 | dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64), | |
c1f67a88 | 1095 | dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size; |
c7d204e8 MT |
1096 | else |
1097 | dev_lim->reserved_mtts = 1 << (field >> 4); | |
1da177e4 LT |
1098 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); |
1099 | dev_lim->max_mrw_sz = 1 << field; | |
1100 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET); | |
1101 | dev_lim->reserved_mrws = 1 << (field & 0xf); | |
1102 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET); | |
1103 | dev_lim->max_mtt_seg = 1 << (field & 0x3f); | |
1104 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET); | |
1105 | dev_lim->max_requester_per_qp = 1 << (field & 0x3f); | |
1106 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET); | |
1107 | dev_lim->max_responder_per_qp = 1 << (field & 0x3f); | |
1108 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET); | |
1109 | dev_lim->max_rdma_global = 1 << (field & 0x3f); | |
1110 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET); | |
1111 | dev_lim->local_ca_ack_delay = field & 0x1f; | |
1112 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET); | |
1113 | dev_lim->max_mtu = field >> 4; | |
1114 | dev_lim->max_port_width = field & 0xf; | |
1115 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET); | |
1116 | dev_lim->max_vl = field >> 4; | |
1117 | dev_lim->num_ports = field & 0xf; | |
1118 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET); | |
1119 | dev_lim->max_gids = 1 << (field & 0xf); | |
bf6a9e31 JM |
1120 | MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET); |
1121 | dev_lim->stat_rate_support = stat_rate; | |
1da177e4 LT |
1122 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET); |
1123 | dev_lim->max_pkeys = 1 << (field & 0xf); | |
1124 | MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET); | |
1125 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET); | |
1126 | dev_lim->reserved_uars = field >> 4; | |
1127 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET); | |
1128 | dev_lim->uar_size = 1 << ((field & 0x3f) + 20); | |
1129 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET); | |
1130 | dev_lim->min_page_sz = 1 << field; | |
1131 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET); | |
1132 | dev_lim->max_sg = field; | |
1133 | ||
1134 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET); | |
1135 | dev_lim->max_desc_sz = size; | |
1136 | ||
1137 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET); | |
1138 | dev_lim->max_qp_per_mcg = 1 << field; | |
1139 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET); | |
1140 | dev_lim->reserved_mgms = field & 0xf; | |
1141 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET); | |
1142 | dev_lim->max_mcgs = 1 << field; | |
1143 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET); | |
1144 | dev_lim->reserved_pds = field >> 4; | |
1145 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET); | |
1146 | dev_lim->max_pds = 1 << (field & 0x3f); | |
1147 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET); | |
1148 | dev_lim->reserved_rdds = field >> 4; | |
1149 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET); | |
1150 | dev_lim->max_rdds = 1 << (field & 0x3f); | |
1151 | ||
1152 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET); | |
1153 | dev_lim->eec_entry_sz = size; | |
1154 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET); | |
1155 | dev_lim->qpc_entry_sz = size; | |
1156 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET); | |
1157 | dev_lim->eeec_entry_sz = size; | |
1158 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET); | |
1159 | dev_lim->eqpc_entry_sz = size; | |
1160 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET); | |
1161 | dev_lim->eqc_entry_sz = size; | |
1162 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET); | |
1163 | dev_lim->cqc_entry_sz = size; | |
1164 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET); | |
1165 | dev_lim->srq_entry_sz = size; | |
1166 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET); | |
1167 | dev_lim->uar_scratch_entry_sz = size; | |
1168 | ||
d10ddbf6 | 1169 | if (mthca_is_memfree(dev)) { |
a3c8ab4f JM |
1170 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); |
1171 | dev_lim->max_srq_sz = 1 << field; | |
1172 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); | |
1173 | dev_lim->max_qp_sz = 1 << field; | |
1da177e4 LT |
1174 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET); |
1175 | dev_lim->hca.arbel.resize_srq = field & 1; | |
8cf2daf3 RD |
1176 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET); |
1177 | dev_lim->max_sg = min_t(int, field, dev_lim->max_sg); | |
77369ed3 JM |
1178 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET); |
1179 | dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz); | |
1da177e4 LT |
1180 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET); |
1181 | dev_lim->mpt_entry_sz = size; | |
1182 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET); | |
1183 | dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f); | |
1184 | MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox, | |
1185 | QUERY_DEV_LIM_BMME_FLAGS_OFFSET); | |
1186 | MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox, | |
1187 | QUERY_DEV_LIM_RSVD_LKEY_OFFSET); | |
1188 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET); | |
1189 | dev_lim->hca.arbel.lam_required = field & 1; | |
1190 | MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox, | |
1191 | QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET); | |
1192 | ||
1193 | if (dev_lim->hca.arbel.bmme_flags & 1) | |
1194 | mthca_dbg(dev, "Base MM extensions: yes " | |
1195 | "(flags %d, max PBL %d, rsvd L_Key %08x)\n", | |
1196 | dev_lim->hca.arbel.bmme_flags, | |
1197 | dev_lim->hca.arbel.max_pbl_sz, | |
1198 | dev_lim->hca.arbel.reserved_lkey); | |
1199 | else | |
1200 | mthca_dbg(dev, "Base MM extensions: no\n"); | |
1201 | ||
1202 | mthca_dbg(dev, "Max ICM size %lld MB\n", | |
1203 | (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20); | |
1204 | } else { | |
a3c8ab4f JM |
1205 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); |
1206 | dev_lim->max_srq_sz = (1 << field) - 1; | |
1207 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); | |
1208 | dev_lim->max_qp_sz = (1 << field) - 1; | |
1da177e4 LT |
1209 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET); |
1210 | dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f); | |
1da177e4 LT |
1211 | dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE; |
1212 | } | |
1213 | ||
f295c79b RD |
1214 | mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", |
1215 | dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz); | |
1216 | mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", | |
1217 | dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz); | |
1218 | mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", | |
1219 | dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz); | |
1220 | mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
1221 | dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz); | |
1222 | mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
1223 | dev_lim->reserved_mrws, dev_lim->reserved_mtts); | |
1224 | mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
1225 | dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars); | |
1226 | mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
1227 | dev_lim->max_pds, dev_lim->reserved_mgms); | |
1228 | mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | |
1229 | dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz); | |
1230 | ||
1231 | mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags); | |
1232 | ||
1da177e4 | 1233 | out: |
ed878458 | 1234 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1235 | return err; |
1236 | } | |
1237 | ||
2e8b981c MT |
1238 | static void get_board_id(void *vsd, char *board_id) |
1239 | { | |
1240 | int i; | |
1241 | ||
1242 | #define VSD_OFFSET_SIG1 0x00 | |
1243 | #define VSD_OFFSET_SIG2 0xde | |
1244 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
1245 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
1246 | ||
1247 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
1248 | ||
1249 | memset(board_id, 0, MTHCA_BOARD_ID_LEN); | |
1250 | ||
1251 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
1252 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
1253 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN); | |
1254 | } else { | |
1255 | /* | |
1256 | * The board ID is a string but the firmware byte | |
1257 | * swaps each 4-byte word before passing it back to | |
1258 | * us. Therefore we need to swab it before printing. | |
1259 | */ | |
1260 | for (i = 0; i < 4; ++i) | |
1261 | ((u32 *) board_id)[i] = | |
1262 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
1263 | } | |
1264 | } | |
1265 | ||
1da177e4 | 1266 | int mthca_QUERY_ADAPTER(struct mthca_dev *dev, |
cdb73db0 | 1267 | struct mthca_adapter *adapter) |
1da177e4 | 1268 | { |
ed878458 | 1269 | struct mthca_mailbox *mailbox; |
1da177e4 | 1270 | u32 *outbox; |
1da177e4 LT |
1271 | int err; |
1272 | ||
1273 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
1274 | #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 | |
1275 | #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 | |
1276 | #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 | |
1277 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 | |
2e8b981c | 1278 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
1da177e4 | 1279 | |
ed878458 RD |
1280 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1281 | if (IS_ERR(mailbox)) | |
1282 | return PTR_ERR(mailbox); | |
1283 | outbox = mailbox->buf; | |
1da177e4 | 1284 | |
ed878458 | 1285 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, |
cdb73db0 | 1286 | CMD_TIME_CLASS_A); |
1da177e4 LT |
1287 | |
1288 | if (err) | |
1289 | goto out; | |
1290 | ||
6ccef1de JM |
1291 | if (!mthca_is_memfree(dev)) { |
1292 | MTHCA_GET(adapter->vendor_id, outbox, | |
1293 | QUERY_ADAPTER_VENDOR_ID_OFFSET); | |
1294 | MTHCA_GET(adapter->device_id, outbox, | |
1295 | QUERY_ADAPTER_DEVICE_ID_OFFSET); | |
1296 | MTHCA_GET(adapter->revision_id, outbox, | |
1297 | QUERY_ADAPTER_REVISION_ID_OFFSET); | |
1298 | } | |
ed878458 | 1299 | MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
1da177e4 | 1300 | |
2e8b981c MT |
1301 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
1302 | adapter->board_id); | |
1303 | ||
1da177e4 | 1304 | out: |
ed878458 | 1305 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1306 | return err; |
1307 | } | |
1308 | ||
1309 | int mthca_INIT_HCA(struct mthca_dev *dev, | |
cdb73db0 | 1310 | struct mthca_init_hca_param *param) |
1da177e4 | 1311 | { |
ed878458 | 1312 | struct mthca_mailbox *mailbox; |
97f52eb4 | 1313 | __be32 *inbox; |
1da177e4 LT |
1314 | int err; |
1315 | ||
1316 | #define INIT_HCA_IN_SIZE 0x200 | |
651eaac9 EC |
1317 | #define INIT_HCA_FLAGS1_OFFSET 0x00c |
1318 | #define INIT_HCA_FLAGS2_OFFSET 0x014 | |
1da177e4 LT |
1319 | #define INIT_HCA_QPC_OFFSET 0x020 |
1320 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
1321 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
1322 | #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20) | |
1323 | #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27) | |
1324 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
1325 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
1326 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
1327 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
1328 | #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) | |
1329 | #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
1330 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
1331 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
1332 | #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
1333 | #define INIT_HCA_UDAV_OFFSET 0x0b0 | |
1334 | #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0) | |
1335 | #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4) | |
1336 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
1337 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
1338 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
1339 | #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
1340 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) | |
1341 | #define INIT_HCA_TPT_OFFSET 0x0f0 | |
1342 | #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
1343 | #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09) | |
1344 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) | |
1345 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
1346 | #define INIT_HCA_UAR_OFFSET 0x120 | |
1347 | #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00) | |
1348 | #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09) | |
1349 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
1350 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
1351 | #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10) | |
1352 | #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18) | |
1353 | ||
ed878458 RD |
1354 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1355 | if (IS_ERR(mailbox)) | |
1356 | return PTR_ERR(mailbox); | |
1357 | inbox = mailbox->buf; | |
1da177e4 LT |
1358 | |
1359 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
1360 | ||
651eaac9 EC |
1361 | if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT) |
1362 | MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET); | |
1363 | ||
1da177e4 | 1364 | #if defined(__LITTLE_ENDIAN) |
651eaac9 | 1365 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1); |
1da177e4 | 1366 | #elif defined(__BIG_ENDIAN) |
651eaac9 | 1367 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1); |
1da177e4 LT |
1368 | #else |
1369 | #error Host endianness not defined | |
1370 | #endif | |
1371 | /* Check port for UD address vector: */ | |
651eaac9 | 1372 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1); |
1da177e4 | 1373 | |
680b575f EC |
1374 | /* Enable IPoIB checksumming if we can: */ |
1375 | if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM) | |
1376 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3); | |
1377 | ||
1da177e4 LT |
1378 | /* We leave wqe_quota, responder_exu, etc as 0 (default) */ |
1379 | ||
1380 | /* QPC/EEC/CQC/EQC/RDB attributes */ | |
1381 | ||
1382 | MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
1383 | MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
1384 | MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET); | |
1385 | MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET); | |
1386 | MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
1387 | MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
1388 | MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
1389 | MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
1390 | MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET); | |
1391 | MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET); | |
1392 | MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
1393 | MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
1394 | MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET); | |
1395 | ||
1396 | /* UD AV attributes */ | |
1397 | ||
1398 | /* multicast attributes */ | |
1399 | ||
1400 | MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
1401 | MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1402 | MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET); | |
1403 | MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1404 | ||
1405 | /* TPT attributes */ | |
1406 | ||
1407 | MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET); | |
d10ddbf6 | 1408 | if (!mthca_is_memfree(dev)) |
1da177e4 LT |
1409 | MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET); |
1410 | MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
1411 | MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
1412 | ||
1413 | /* UAR attributes */ | |
1414 | { | |
1415 | u8 uar_page_sz = PAGE_SHIFT - 12; | |
1416 | MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
1417 | } | |
1418 | ||
1419 | MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET); | |
1420 | ||
d10ddbf6 | 1421 | if (mthca_is_memfree(dev)) { |
1da177e4 LT |
1422 | MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET); |
1423 | MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
1424 | MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET); | |
1425 | } | |
1426 | ||
cdb73db0 GR |
1427 | err = mthca_cmd(dev, mailbox->dma, 0, 0, |
1428 | CMD_INIT_HCA, CMD_TIME_CLASS_D); | |
1da177e4 | 1429 | |
ed878458 | 1430 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1431 | return err; |
1432 | } | |
1433 | ||
1434 | int mthca_INIT_IB(struct mthca_dev *dev, | |
1435 | struct mthca_init_ib_param *param, | |
cdb73db0 | 1436 | int port) |
1da177e4 | 1437 | { |
ed878458 | 1438 | struct mthca_mailbox *mailbox; |
1da177e4 | 1439 | u32 *inbox; |
1da177e4 LT |
1440 | int err; |
1441 | u32 flags; | |
1442 | ||
1443 | #define INIT_IB_IN_SIZE 56 | |
1444 | #define INIT_IB_FLAGS_OFFSET 0x00 | |
1445 | #define INIT_IB_FLAG_SIG (1 << 18) | |
1446 | #define INIT_IB_FLAG_NG (1 << 17) | |
1447 | #define INIT_IB_FLAG_G0 (1 << 16) | |
1da177e4 | 1448 | #define INIT_IB_VL_SHIFT 4 |
da6561c2 | 1449 | #define INIT_IB_PORT_WIDTH_SHIFT 8 |
1da177e4 LT |
1450 | #define INIT_IB_MTU_SHIFT 12 |
1451 | #define INIT_IB_MAX_GID_OFFSET 0x06 | |
1452 | #define INIT_IB_MAX_PKEY_OFFSET 0x0a | |
1453 | #define INIT_IB_GUID0_OFFSET 0x10 | |
1454 | #define INIT_IB_NODE_GUID_OFFSET 0x18 | |
1455 | #define INIT_IB_SI_GUID_OFFSET 0x20 | |
1456 | ||
ed878458 RD |
1457 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1458 | if (IS_ERR(mailbox)) | |
1459 | return PTR_ERR(mailbox); | |
1460 | inbox = mailbox->buf; | |
1da177e4 LT |
1461 | |
1462 | memset(inbox, 0, INIT_IB_IN_SIZE); | |
1463 | ||
1464 | flags = 0; | |
1da177e4 LT |
1465 | flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; |
1466 | flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; | |
1467 | flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; | |
1468 | flags |= param->vl_cap << INIT_IB_VL_SHIFT; | |
da6561c2 | 1469 | flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT; |
1da177e4 LT |
1470 | flags |= param->mtu_cap << INIT_IB_MTU_SHIFT; |
1471 | MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET); | |
1472 | ||
1473 | MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET); | |
1474 | MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET); | |
1475 | MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET); | |
1476 | MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET); | |
1477 | MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET); | |
1478 | ||
ed878458 | 1479 | err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, |
cdb73db0 | 1480 | CMD_TIME_CLASS_A); |
1da177e4 | 1481 | |
ed878458 | 1482 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1483 | return err; |
1484 | } | |
1485 | ||
cdb73db0 | 1486 | int mthca_CLOSE_IB(struct mthca_dev *dev, int port) |
1da177e4 | 1487 | { |
cdb73db0 | 1488 | return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A); |
1da177e4 LT |
1489 | } |
1490 | ||
cdb73db0 | 1491 | int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic) |
1da177e4 | 1492 | { |
cdb73db0 | 1493 | return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C); |
1da177e4 LT |
1494 | } |
1495 | ||
1496 | int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, | |
cdb73db0 | 1497 | int port) |
1da177e4 | 1498 | { |
ed878458 | 1499 | struct mthca_mailbox *mailbox; |
1da177e4 | 1500 | u32 *inbox; |
1da177e4 LT |
1501 | int err; |
1502 | u32 flags = 0; | |
1503 | ||
1504 | #define SET_IB_IN_SIZE 0x40 | |
1505 | #define SET_IB_FLAGS_OFFSET 0x00 | |
1506 | #define SET_IB_FLAG_SIG (1 << 18) | |
1507 | #define SET_IB_FLAG_RQK (1 << 0) | |
1508 | #define SET_IB_CAP_MASK_OFFSET 0x04 | |
1509 | #define SET_IB_SI_GUID_OFFSET 0x08 | |
1510 | ||
ed878458 RD |
1511 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1512 | if (IS_ERR(mailbox)) | |
1513 | return PTR_ERR(mailbox); | |
1514 | inbox = mailbox->buf; | |
1da177e4 LT |
1515 | |
1516 | memset(inbox, 0, SET_IB_IN_SIZE); | |
1517 | ||
1518 | flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; | |
1519 | flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; | |
1520 | MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET); | |
1521 | ||
1522 | MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET); | |
1523 | MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET); | |
1524 | ||
ed878458 | 1525 | err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, |
cdb73db0 | 1526 | CMD_TIME_CLASS_B); |
1da177e4 | 1527 | |
ed878458 | 1528 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1529 | return err; |
1530 | } | |
1531 | ||
cdb73db0 | 1532 | int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt) |
1da177e4 | 1533 | { |
cdb73db0 | 1534 | return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt); |
1da177e4 LT |
1535 | } |
1536 | ||
cdb73db0 | 1537 | int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt) |
1da177e4 | 1538 | { |
ed878458 | 1539 | struct mthca_mailbox *mailbox; |
97f52eb4 | 1540 | __be64 *inbox; |
1da177e4 LT |
1541 | int err; |
1542 | ||
ed878458 RD |
1543 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1544 | if (IS_ERR(mailbox)) | |
1545 | return PTR_ERR(mailbox); | |
1546 | inbox = mailbox->buf; | |
1da177e4 LT |
1547 | |
1548 | inbox[0] = cpu_to_be64(virt); | |
1549 | inbox[1] = cpu_to_be64(dma_addr); | |
1550 | ||
ed878458 | 1551 | err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM, |
cdb73db0 | 1552 | CMD_TIME_CLASS_B); |
1da177e4 | 1553 | |
ed878458 | 1554 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1555 | |
1556 | if (!err) | |
6bd6228e RD |
1557 | mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n", |
1558 | (unsigned long long) dma_addr, (unsigned long long) virt); | |
1da177e4 LT |
1559 | |
1560 | return err; | |
1561 | } | |
1562 | ||
cdb73db0 | 1563 | int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count) |
1da177e4 LT |
1564 | { |
1565 | mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n", | |
1566 | page_count, (unsigned long long) virt); | |
1567 | ||
cdb73db0 GR |
1568 | return mthca_cmd(dev, virt, page_count, 0, |
1569 | CMD_UNMAP_ICM, CMD_TIME_CLASS_B); | |
1da177e4 LT |
1570 | } |
1571 | ||
cdb73db0 | 1572 | int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm) |
1da177e4 | 1573 | { |
cdb73db0 | 1574 | return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1); |
1da177e4 LT |
1575 | } |
1576 | ||
cdb73db0 | 1577 | int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev) |
1da177e4 | 1578 | { |
cdb73db0 | 1579 | return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B); |
1da177e4 LT |
1580 | } |
1581 | ||
cdb73db0 | 1582 | int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages) |
1da177e4 | 1583 | { |
cdb73db0 GR |
1584 | int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, |
1585 | 0, CMD_SET_ICM_SIZE, CMD_TIME_CLASS_A); | |
1da177e4 | 1586 | |
cdb73db0 | 1587 | if (ret) |
1da177e4 LT |
1588 | return ret; |
1589 | ||
1590 | /* | |
8d3ef29d IR |
1591 | * Round up number of system pages needed in case |
1592 | * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. | |
1da177e4 | 1593 | */ |
8d3ef29d IR |
1594 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> |
1595 | (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); | |
1da177e4 LT |
1596 | |
1597 | return 0; | |
1598 | } | |
1599 | ||
ed878458 | 1600 | int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1601 | int mpt_index) |
1da177e4 | 1602 | { |
ed878458 | 1603 | return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, |
cdb73db0 | 1604 | CMD_TIME_CLASS_B); |
1da177e4 LT |
1605 | } |
1606 | ||
ed878458 | 1607 | int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1608 | int mpt_index) |
1da177e4 | 1609 | { |
ed878458 RD |
1610 | return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, |
1611 | !mailbox, CMD_HW2SW_MPT, | |
cdb73db0 | 1612 | CMD_TIME_CLASS_B); |
1da177e4 LT |
1613 | } |
1614 | ||
ed878458 | 1615 | int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1616 | int num_mtt) |
1da177e4 | 1617 | { |
ed878458 | 1618 | return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, |
cdb73db0 | 1619 | CMD_TIME_CLASS_B); |
1da177e4 LT |
1620 | } |
1621 | ||
cdb73db0 | 1622 | int mthca_SYNC_TPT(struct mthca_dev *dev) |
b8ca06f6 | 1623 | { |
cdb73db0 | 1624 | return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B); |
b8ca06f6 MT |
1625 | } |
1626 | ||
1da177e4 | 1627 | int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, |
cdb73db0 | 1628 | int eq_num) |
1da177e4 LT |
1629 | { |
1630 | mthca_dbg(dev, "%s mask %016llx for eqn %d\n", | |
1631 | unmap ? "Clearing" : "Setting", | |
1632 | (unsigned long long) event_mask, eq_num); | |
1633 | return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num, | |
cdb73db0 | 1634 | 0, CMD_MAP_EQ, CMD_TIME_CLASS_B); |
1da177e4 LT |
1635 | } |
1636 | ||
ed878458 | 1637 | int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1638 | int eq_num) |
1da177e4 | 1639 | { |
ed878458 | 1640 | return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, |
cdb73db0 | 1641 | CMD_TIME_CLASS_A); |
1da177e4 LT |
1642 | } |
1643 | ||
ed878458 | 1644 | int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1645 | int eq_num) |
1da177e4 | 1646 | { |
ed878458 RD |
1647 | return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0, |
1648 | CMD_HW2SW_EQ, | |
cdb73db0 | 1649 | CMD_TIME_CLASS_A); |
1da177e4 LT |
1650 | } |
1651 | ||
ed878458 | 1652 | int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1653 | int cq_num) |
1da177e4 | 1654 | { |
ed878458 | 1655 | return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, |
cdb73db0 | 1656 | CMD_TIME_CLASS_A); |
1da177e4 LT |
1657 | } |
1658 | ||
ed878458 | 1659 | int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1660 | int cq_num) |
1da177e4 | 1661 | { |
ed878458 RD |
1662 | return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0, |
1663 | CMD_HW2SW_CQ, | |
cdb73db0 | 1664 | CMD_TIME_CLASS_A); |
1da177e4 LT |
1665 | } |
1666 | ||
cdb73db0 | 1667 | int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size) |
4885bf64 RD |
1668 | { |
1669 | struct mthca_mailbox *mailbox; | |
1670 | __be32 *inbox; | |
1671 | int err; | |
1672 | ||
1673 | #define RESIZE_CQ_IN_SIZE 0x40 | |
1674 | #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c | |
1675 | #define RESIZE_CQ_LKEY_OFFSET 0x1c | |
1676 | ||
1677 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1678 | if (IS_ERR(mailbox)) | |
1679 | return PTR_ERR(mailbox); | |
1680 | inbox = mailbox->buf; | |
1681 | ||
1682 | memset(inbox, 0, RESIZE_CQ_IN_SIZE); | |
1683 | /* | |
1684 | * Leave start address fields zeroed out -- mthca assumes that | |
1685 | * MRs for CQs always start at virtual address 0. | |
1686 | */ | |
1687 | MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET); | |
1688 | MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET); | |
1689 | ||
1690 | err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ, | |
cdb73db0 | 1691 | CMD_TIME_CLASS_B); |
4885bf64 RD |
1692 | |
1693 | mthca_free_mailbox(dev, mailbox); | |
1694 | return err; | |
1695 | } | |
1696 | ||
ec34a922 | 1697 | int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1698 | int srq_num) |
ec34a922 RD |
1699 | { |
1700 | return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ, | |
cdb73db0 | 1701 | CMD_TIME_CLASS_A); |
ec34a922 RD |
1702 | } |
1703 | ||
1704 | int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, | |
cdb73db0 | 1705 | int srq_num) |
ec34a922 RD |
1706 | { |
1707 | return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0, | |
1708 | CMD_HW2SW_SRQ, | |
cdb73db0 | 1709 | CMD_TIME_CLASS_A); |
ec34a922 RD |
1710 | } |
1711 | ||
8ebe5077 | 1712 | int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num, |
cdb73db0 | 1713 | struct mthca_mailbox *mailbox) |
8ebe5077 EC |
1714 | { |
1715 | return mthca_cmd_box(dev, 0, mailbox->dma, num, 0, | |
cdb73db0 | 1716 | CMD_QUERY_SRQ, CMD_TIME_CLASS_A); |
8ebe5077 EC |
1717 | } |
1718 | ||
cdb73db0 | 1719 | int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit) |
ec34a922 RD |
1720 | { |
1721 | return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ, | |
cdb73db0 | 1722 | CMD_TIME_CLASS_B); |
ec34a922 RD |
1723 | } |
1724 | ||
d844183d RD |
1725 | int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur, |
1726 | enum ib_qp_state next, u32 num, int is_ee, | |
cdb73db0 | 1727 | struct mthca_mailbox *mailbox, u32 optmask) |
1da177e4 | 1728 | { |
d844183d RD |
1729 | static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = { |
1730 | [IB_QPS_RESET] = { | |
1731 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1732 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1733 | [IB_QPS_INIT] = CMD_RST2INIT_QPEE, | |
1734 | }, | |
1735 | [IB_QPS_INIT] = { | |
1736 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1737 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1738 | [IB_QPS_INIT] = CMD_INIT2INIT_QPEE, | |
1739 | [IB_QPS_RTR] = CMD_INIT2RTR_QPEE, | |
1740 | }, | |
1741 | [IB_QPS_RTR] = { | |
1742 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1743 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1744 | [IB_QPS_RTS] = CMD_RTR2RTS_QPEE, | |
1745 | }, | |
1746 | [IB_QPS_RTS] = { | |
1747 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1748 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1749 | [IB_QPS_RTS] = CMD_RTS2RTS_QPEE, | |
1750 | [IB_QPS_SQD] = CMD_RTS2SQD_QPEE, | |
1751 | }, | |
1752 | [IB_QPS_SQD] = { | |
1753 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1754 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1755 | [IB_QPS_RTS] = CMD_SQD2RTS_QPEE, | |
1756 | [IB_QPS_SQD] = CMD_SQD2SQD_QPEE, | |
1757 | }, | |
1758 | [IB_QPS_SQE] = { | |
1759 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1760 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1761 | [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE, | |
1762 | }, | |
1763 | [IB_QPS_ERR] = { | |
1764 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1765 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1766 | } | |
1da177e4 | 1767 | }; |
d844183d | 1768 | |
1da177e4 | 1769 | u8 op_mod = 0; |
ed878458 | 1770 | int my_mailbox = 0; |
1da177e4 LT |
1771 | int err; |
1772 | ||
d844183d | 1773 | if (op[cur][next] == CMD_ERR2RST_QPEE) { |
1da177e4 LT |
1774 | op_mod = 3; /* don't write outbox, any->reset */ |
1775 | ||
1776 | /* For debugging */ | |
ed878458 RD |
1777 | if (!mailbox) { |
1778 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1779 | if (!IS_ERR(mailbox)) { | |
1780 | my_mailbox = 1; | |
1781 | op_mod = 2; /* write outbox, any->reset */ | |
1782 | } else | |
1783 | mailbox = NULL; | |
1784 | } | |
d844183d RD |
1785 | |
1786 | err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, | |
1787 | (!!is_ee << 24) | num, op_mod, | |
cdb73db0 | 1788 | op[cur][next], CMD_TIME_CLASS_C); |
d844183d RD |
1789 | |
1790 | if (0 && mailbox) { | |
1da177e4 LT |
1791 | int i; |
1792 | mthca_dbg(dev, "Dumping QP context:\n"); | |
d844183d | 1793 | printk(" %08x\n", be32_to_cpup(mailbox->buf)); |
1da177e4 LT |
1794 | for (i = 0; i < 0x100 / 4; ++i) { |
1795 | if (i % 8 == 0) | |
d844183d | 1796 | printk("[%02x] ", i * 4); |
ed878458 | 1797 | printk(" %08x", |
97f52eb4 | 1798 | be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); |
1da177e4 LT |
1799 | if ((i + 1) % 8 == 0) |
1800 | printk("\n"); | |
1801 | } | |
1802 | } | |
1da177e4 | 1803 | |
d844183d RD |
1804 | if (my_mailbox) |
1805 | mthca_free_mailbox(dev, mailbox); | |
1806 | } else { | |
1807 | if (0) { | |
1da177e4 LT |
1808 | int i; |
1809 | mthca_dbg(dev, "Dumping QP context:\n"); | |
d844183d | 1810 | printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf)); |
1da177e4 LT |
1811 | for (i = 0; i < 0x100 / 4; ++i) { |
1812 | if (i % 8 == 0) | |
d844183d | 1813 | printk(" [%02x] ", i * 4); |
ed878458 | 1814 | printk(" %08x", |
97f52eb4 | 1815 | be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); |
1da177e4 LT |
1816 | if ((i + 1) % 8 == 0) |
1817 | printk("\n"); | |
1818 | } | |
1819 | } | |
1820 | ||
d844183d | 1821 | err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num, |
cdb73db0 | 1822 | op_mod, op[cur][next], CMD_TIME_CLASS_C); |
d844183d | 1823 | } |
ed878458 | 1824 | |
1da177e4 LT |
1825 | return err; |
1826 | } | |
1827 | ||
1828 | int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, | |
cdb73db0 | 1829 | struct mthca_mailbox *mailbox) |
1da177e4 | 1830 | { |
ed878458 | 1831 | return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0, |
cdb73db0 | 1832 | CMD_QUERY_QPEE, CMD_TIME_CLASS_A); |
1da177e4 LT |
1833 | } |
1834 | ||
cdb73db0 | 1835 | int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn) |
1da177e4 LT |
1836 | { |
1837 | u8 op_mod; | |
1838 | ||
1839 | switch (type) { | |
1840 | case IB_QPT_SMI: | |
1841 | op_mod = 0; | |
1842 | break; | |
1843 | case IB_QPT_GSI: | |
1844 | op_mod = 1; | |
1845 | break; | |
1846 | case IB_QPT_RAW_IPV6: | |
1847 | op_mod = 2; | |
1848 | break; | |
a2ebf07a | 1849 | case IB_QPT_RAW_ETHERTYPE: |
1da177e4 LT |
1850 | op_mod = 3; |
1851 | break; | |
1852 | default: | |
1853 | return -EINVAL; | |
1854 | } | |
1855 | ||
1856 | return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, | |
cdb73db0 | 1857 | CMD_TIME_CLASS_B); |
1da177e4 LT |
1858 | } |
1859 | ||
1860 | int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, | |
a97e2d86 IW |
1861 | int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
1862 | const void *in_mad, void *response_mad) | |
1da177e4 | 1863 | { |
ed878458 RD |
1864 | struct mthca_mailbox *inmailbox, *outmailbox; |
1865 | void *inbox; | |
1da177e4 LT |
1866 | int err; |
1867 | u32 in_modifier = port; | |
1868 | u8 op_modifier = 0; | |
1869 | ||
1870 | #define MAD_IFC_BOX_SIZE 0x400 | |
1871 | #define MAD_IFC_MY_QPN_OFFSET 0x100 | |
68586b67 MT |
1872 | #define MAD_IFC_RQPN_OFFSET 0x108 |
1873 | #define MAD_IFC_SL_OFFSET 0x10c | |
1874 | #define MAD_IFC_G_PATH_OFFSET 0x10d | |
1875 | #define MAD_IFC_RLID_OFFSET 0x10e | |
1876 | #define MAD_IFC_PKEY_OFFSET 0x112 | |
1da177e4 LT |
1877 | #define MAD_IFC_GRH_OFFSET 0x140 |
1878 | ||
ed878458 RD |
1879 | inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1880 | if (IS_ERR(inmailbox)) | |
1881 | return PTR_ERR(inmailbox); | |
1882 | inbox = inmailbox->buf; | |
1883 | ||
1884 | outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1885 | if (IS_ERR(outmailbox)) { | |
1886 | mthca_free_mailbox(dev, inmailbox); | |
1887 | return PTR_ERR(outmailbox); | |
1888 | } | |
1da177e4 | 1889 | |
ed878458 | 1890 | memcpy(inbox, in_mad, 256); |
1da177e4 LT |
1891 | |
1892 | /* | |
1893 | * Key check traps can't be generated unless we have in_wc to | |
1894 | * tell us where to send the trap. | |
1895 | */ | |
1896 | if (ignore_mkey || !in_wc) | |
1897 | op_modifier |= 0x1; | |
1898 | if (ignore_bkey || !in_wc) | |
1899 | op_modifier |= 0x2; | |
1900 | ||
1901 | if (in_wc) { | |
1902 | u8 val; | |
1903 | ||
ed878458 | 1904 | memset(inbox + 256, 0, 256); |
1da177e4 | 1905 | |
062dbb69 | 1906 | MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET); |
ed878458 | 1907 | MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET); |
1da177e4 LT |
1908 | |
1909 | val = in_wc->sl << 4; | |
ed878458 | 1910 | MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET); |
1da177e4 LT |
1911 | |
1912 | val = in_wc->dlid_path_bits | | |
1913 | (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); | |
68586b67 | 1914 | MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET); |
1da177e4 | 1915 | |
ed878458 RD |
1916 | MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET); |
1917 | MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET); | |
1da177e4 LT |
1918 | |
1919 | if (in_grh) | |
ed878458 | 1920 | memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40); |
1da177e4 | 1921 | |
68586b67 | 1922 | op_modifier |= 0x4; |
1da177e4 LT |
1923 | |
1924 | in_modifier |= in_wc->slid << 16; | |
1925 | } | |
1926 | ||
ed878458 RD |
1927 | err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma, |
1928 | in_modifier, op_modifier, | |
cdb73db0 | 1929 | CMD_MAD_IFC, CMD_TIME_CLASS_C); |
1da177e4 | 1930 | |
cdb73db0 | 1931 | if (!err) |
ed878458 | 1932 | memcpy(response_mad, outmailbox->buf, 256); |
1da177e4 | 1933 | |
ed878458 RD |
1934 | mthca_free_mailbox(dev, inmailbox); |
1935 | mthca_free_mailbox(dev, outmailbox); | |
1da177e4 LT |
1936 | return err; |
1937 | } | |
1938 | ||
ed878458 | 1939 | int mthca_READ_MGM(struct mthca_dev *dev, int index, |
cdb73db0 | 1940 | struct mthca_mailbox *mailbox) |
1da177e4 | 1941 | { |
ed878458 | 1942 | return mthca_cmd_box(dev, 0, mailbox->dma, index, 0, |
cdb73db0 | 1943 | CMD_READ_MGM, CMD_TIME_CLASS_A); |
1da177e4 LT |
1944 | } |
1945 | ||
ed878458 | 1946 | int mthca_WRITE_MGM(struct mthca_dev *dev, int index, |
cdb73db0 | 1947 | struct mthca_mailbox *mailbox) |
1da177e4 | 1948 | { |
ed878458 | 1949 | return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM, |
cdb73db0 | 1950 | CMD_TIME_CLASS_A); |
1da177e4 LT |
1951 | } |
1952 | ||
ed878458 | 1953 | int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
cdb73db0 | 1954 | u16 *hash) |
1da177e4 | 1955 | { |
1da177e4 LT |
1956 | u64 imm; |
1957 | int err; | |
1958 | ||
ed878458 | 1959 | err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH, |
cdb73db0 | 1960 | CMD_TIME_CLASS_A); |
1da177e4 | 1961 | |
ed878458 | 1962 | *hash = imm; |
1da177e4 LT |
1963 | return err; |
1964 | } | |
1965 | ||
cdb73db0 | 1966 | int mthca_NOP(struct mthca_dev *dev) |
1da177e4 | 1967 | { |
cdb73db0 | 1968 | return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100)); |
1da177e4 | 1969 | } |