]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/infiniband/hw/mthca/mthca_cmd.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mthca / mthca_cmd.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
2a1d9b7f 3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4885bf64 4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
1da177e4
LT		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
1da177e4
LT		 33 */
34
2a214182 35#include <linux/completion.h>
1da177e4
LT		 36#include <linux/pci.h>
37#include <linux/errno.h>
e8edc6e0 38#include <linux/sched.h>
5a0e3ad6 39#include <linux/slab.h>
1da177e4 40#include <asm/io.h>
a4d61e84 41#include <rdma/ib_mad.h>
1da177e4
LT		 42
43#include "mthca_dev.h"
44#include "mthca_config_reg.h"
45#include "mthca_cmd.h"
46#include "mthca_memfree.h"
47
48#define CMD_POLL_TOKEN 0xffff
49
50enum {
51 HCR_IN_PARAM_OFFSET = 0x00,
52 HCR_IN_MODIFIER_OFFSET = 0x08,
53 HCR_OUT_PARAM_OFFSET = 0x0c,
54 HCR_TOKEN_OFFSET = 0x14,
55 HCR_STATUS_OFFSET = 0x18,
56
57 HCR_OPMOD_SHIFT = 12,
58 HCA_E_BIT = 22,
59 HCR_GO_BIT = 23
60};
61
62enum {
63 /* initialization and general commands */
64 CMD_SYS_EN = 0x1,
65 CMD_SYS_DIS = 0x2,
66 CMD_MAP_FA = 0xfff,
67 CMD_UNMAP_FA = 0xffe,
68 CMD_RUN_FW = 0xff6,
69 CMD_MOD_STAT_CFG = 0x34,
70 CMD_QUERY_DEV_LIM = 0x3,
71 CMD_QUERY_FW = 0x4,
72 CMD_ENABLE_LAM = 0xff8,
73 CMD_DISABLE_LAM = 0xff7,
74 CMD_QUERY_DDR = 0x5,
75 CMD_QUERY_ADAPTER = 0x6,
76 CMD_INIT_HCA = 0x7,
77 CMD_CLOSE_HCA = 0x8,
78 CMD_INIT_IB = 0x9,
79 CMD_CLOSE_IB = 0xa,
80 CMD_QUERY_HCA = 0xb,
81 CMD_SET_IB = 0xc,
82 CMD_ACCESS_DDR = 0x2e,
83 CMD_MAP_ICM = 0xffa,
84 CMD_UNMAP_ICM = 0xff9,
85 CMD_MAP_ICM_AUX = 0xffc,
86 CMD_UNMAP_ICM_AUX = 0xffb,
87 CMD_SET_ICM_SIZE = 0xffd,
88
89 /* TPT commands */
90 CMD_SW2HW_MPT = 0xd,
91 CMD_QUERY_MPT = 0xe,
92 CMD_HW2SW_MPT = 0xf,
93 CMD_READ_MTT = 0x10,
94 CMD_WRITE_MTT = 0x11,
95 CMD_SYNC_TPT = 0x2f,
96
97 /* EQ commands */
98 CMD_MAP_EQ = 0x12,
99 CMD_SW2HW_EQ = 0x13,
100 CMD_HW2SW_EQ = 0x14,
101 CMD_QUERY_EQ = 0x15,
102
103 /* CQ commands */
104 CMD_SW2HW_CQ = 0x16,
105 CMD_HW2SW_CQ = 0x17,
106 CMD_QUERY_CQ = 0x18,
107 CMD_RESIZE_CQ = 0x2c,
108
109 /* SRQ commands */
110 CMD_SW2HW_SRQ = 0x35,
111 CMD_HW2SW_SRQ = 0x36,
112 CMD_QUERY_SRQ = 0x37,
ec34a922 113 CMD_ARM_SRQ = 0x40,
1da177e4
LT		 114
115 /* QP/EE commands */
116 CMD_RST2INIT_QPEE = 0x19,
117 CMD_INIT2RTR_QPEE = 0x1a,
118 CMD_RTR2RTS_QPEE = 0x1b,
119 CMD_RTS2RTS_QPEE = 0x1c,
120 CMD_SQERR2RTS_QPEE = 0x1d,
121 CMD_2ERR_QPEE = 0x1e,
122 CMD_RTS2SQD_QPEE = 0x1f,
123 CMD_SQD2SQD_QPEE = 0x38,
124 CMD_SQD2RTS_QPEE = 0x20,
125 CMD_ERR2RST_QPEE = 0x21,
126 CMD_QUERY_QPEE = 0x22,
127 CMD_INIT2INIT_QPEE = 0x2d,
128 CMD_SUSPEND_QPEE = 0x32,
129 CMD_UNSUSPEND_QPEE = 0x33,
130 /* special QPs and management commands */
131 CMD_CONF_SPECIAL_QP = 0x23,
132 CMD_MAD_IFC = 0x24,
133
134 /* multicast commands */
135 CMD_READ_MGM = 0x25,
136 CMD_WRITE_MGM = 0x26,
137 CMD_MGID_HASH = 0x27,
138
139 /* miscellaneous commands */
140 CMD_DIAG_RPRT = 0x30,
141 CMD_NOP = 0x31,
142
143 /* debug commands */
144 CMD_QUERY_DEBUG_MSG = 0x2a,
145 CMD_SET_DEBUG_MSG = 0x2b,
146};
147
148/*
149 * According to Mellanox code, FW may be starved and never complete
150 * commands. So we can't use strict timeouts described in PRM -- we
151 * just arbitrarily select 60 seconds for now.
152 */
153#if 0
154/*
155 * Round up and add 1 to make sure we get the full wait time (since we
156 * will be starting in the middle of a jiffy)
157 */
158enum {
159 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
160 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
8531f1f1
JM		 161 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
162 CMD_TIME_CLASS_D = 60 * HZ
1da177e4
LT		 163};
164#else
165enum {
166 CMD_TIME_CLASS_A = 60 * HZ,
167 CMD_TIME_CLASS_B = 60 * HZ,
8531f1f1
JM		 168 CMD_TIME_CLASS_C = 60 * HZ,
169 CMD_TIME_CLASS_D = 60 * HZ
1da177e4
LT		 170};
171#endif
172
173enum {
174 GO_BIT_TIMEOUT = HZ * 10
175};
176
177struct mthca_cmd_context {
178 struct completion done;
1da177e4
LT		 179 int result;
180 int next;
181 u64 out_param;
182 u16 token;
183 u8 status;
184};
185
1db76c14 186static int fw_cmd_doorbell = 0;
14abdffc
EC		 187module_param(fw_cmd_doorbell, int, 0644);
188MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
189 "(and supported by FW)");
190
1da177e4
LT		 191static inline int go_bit(struct mthca_dev *dev)
192{
193 return readl(dev->hcr + HCR_STATUS_OFFSET) &
194 swab32(1 << HCR_GO_BIT);
195}
196
14abdffc
EC		 197static void mthca_cmd_post_dbell(struct mthca_dev *dev,
198 u64 in_param,
199 u64 out_param,
200 u32 in_modifier,
201 u8 op_modifier,
202 u16 op,
203 u16 token)
1da177e4 204{
14abdffc
EC		 205 void __iomem *ptr = dev->cmd.dbell_map;
206 u16 *offs = dev->cmd.dbell_offsets;
1da177e4 207
14abdffc
EC		 208 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
209 wmb();
210 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
211 wmb();
212 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
213 wmb();
214 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
215 wmb();
216 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
217 wmb();
218 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
219 wmb();
220 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
221 (1 << HCA_E_BIT) |
222 (op_modifier << HCR_OPMOD_SHIFT) |
b3999393 223 op), ptr + offs[6]);
14abdffc
EC		 224 wmb();
225 __raw_writel((__force u32) 0, ptr + offs[7]);
226 wmb();
227}
1da177e4 228
14abdffc
EC		 229static int mthca_cmd_post_hcr(struct mthca_dev *dev,
230 u64 in_param,
231 u64 out_param,
232 u32 in_modifier,
233 u8 op_modifier,
234 u16 op,
235 u16 token,
236 int event)
237{
1da177e4
LT		 238 if (event) {
239 unsigned long end = jiffies + GO_BIT_TIMEOUT;
240
241 while (go_bit(dev) && time_before(jiffies, end)) {
242 set_current_state(TASK_RUNNING);
243 schedule();
244 }
245 }
246
14abdffc
EC		 247 if (go_bit(dev))
248 return -EAGAIN;
1da177e4
LT		 249
250 /*
251 * We use writel (instead of something like memcpy_toio)
252 * because writes of less than 32 bits to the HCR don't work
253 * (and some architectures such as ia64 implement memcpy_toio
254 * in terms of writeb).
255 */
97f52eb4
SH		 256 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
257 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
258 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
259 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
260 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
261 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
1da177e4
LT		 262
263 /* __raw_writel may not order writes. */
264 wmb();
265
97f52eb4
SH		 266 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
267 (event ? (1 << HCA_E_BIT) : 0) |
268 (op_modifier << HCR_OPMOD_SHIFT) |
269 op), dev->hcr + 6 * 4);
1da177e4 270
14abdffc
EC		 271 return 0;
272}
273
274static int mthca_cmd_post(struct mthca_dev *dev,
275 u64 in_param,
276 u64 out_param,
277 u32 in_modifier,
278 u8 op_modifier,
279 u16 op,
280 u16 token,
281 int event)
282{
283 int err = 0;
284
285 mutex_lock(&dev->cmd.hcr_mutex);
286
287 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
288 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
289 op_modifier, op, token);
290 else
291 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
292 op_modifier, op, token, event);
293
76d7cc03
RD		 294 /*
295 * Make sure that our HCR writes don't get mixed in with
296 * writes from another CPU starting a FW command.
297 */
298 mmiowb();
299
fd9cfdd1 300 mutex_unlock(&dev->cmd.hcr_mutex);
1da177e4
LT		 301 return err;
302}
303
304static int mthca_cmd_poll(struct mthca_dev *dev,
305 u64 in_param,
306 u64 *out_param,
307 int out_is_imm,
308 u32 in_modifier,
309 u8 op_modifier,
310 u16 op,
311 unsigned long timeout,
312 u8 *status)
313{
314 int err = 0;
315 unsigned long end;
316
e3aa31c5 317 down(&dev->cmd.poll_sem);
1da177e4
LT		 318
319 err = mthca_cmd_post(dev, in_param,
320 out_param ? *out_param : 0,
321 in_modifier, op_modifier,
322 op, CMD_POLL_TOKEN, 0);
323 if (err)
324 goto out;
325
326 end = timeout + jiffies;
327 while (go_bit(dev) && time_before(jiffies, end)) {
328 set_current_state(TASK_RUNNING);
329 schedule();
330 }
331
332 if (go_bit(dev)) {
333 err = -EBUSY;
334 goto out;
335 }
336
97f52eb4 337 if (out_is_imm)
2fa5e2eb 338 *out_param =
97f52eb4
SH		 339 (u64) be32_to_cpu((__force __be32)
340 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
341 (u64) be32_to_cpu((__force __be32)
342 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
1da177e4 343
97f52eb4 344 *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
1da177e4
LT		 345
346out:
347 up(&dev->cmd.poll_sem);
348 return err;
349}
350
351void mthca_cmd_event(struct mthca_dev *dev,
352 u16 token,
353 u8 status,
354 u64 out_param)
355{
356 struct mthca_cmd_context *context =
357 &dev->cmd.context[token & dev->cmd.token_mask];
358
359 /* previously timed out command completing at long last */
360 if (token != context->token)
361 return;
362
363 context->result = 0;
364 context->status = status;
365 context->out_param = out_param;
366
1da177e4
LT		 367 complete(&context->done);
368}
369
1da177e4
LT		 370static int mthca_cmd_wait(struct mthca_dev *dev,
371 u64 in_param,
372 u64 *out_param,
373 int out_is_imm,
374 u32 in_modifier,
375 u8 op_modifier,
376 u16 op,
377 unsigned long timeout,
378 u8 *status)
379{
380 int err = 0;
381 struct mthca_cmd_context *context;
382
e3aa31c5 383 down(&dev->cmd.event_sem);
1da177e4
LT		 384
385 spin_lock(&dev->cmd.context_lock);
386 BUG_ON(dev->cmd.free_head < 0);
387 context = &dev->cmd.context[dev->cmd.free_head];
c1f74958 388 context->token += dev->cmd.token_mask + 1;
1da177e4
LT		 389 dev->cmd.free_head = context->next;
390 spin_unlock(&dev->cmd.context_lock);
391
392 init_completion(&context->done);
393
394 err = mthca_cmd_post(dev, in_param,
395 out_param ? *out_param : 0,
396 in_modifier, op_modifier,
397 op, context->token, 1);
398 if (err)
399 goto out;
400
e9cd5941
RD		 401 if (!wait_for_completion_timeout(&context->done, timeout)) {
402 err = -EBUSY;
403 goto out;
404 }
1da177e4
LT		 405
406 err = context->result;
407 if (err)
408 goto out;
409
410 *status = context->status;
411 if (*status)
412 mthca_dbg(dev, "Command %02x completed with status %02x\n",
413 op, *status);
414
415 if (out_is_imm)
416 *out_param = context->out_param;
417
418out:
419 spin_lock(&dev->cmd.context_lock);
420 context->next = dev->cmd.free_head;
421 dev->cmd.free_head = context - dev->cmd.context;
422 spin_unlock(&dev->cmd.context_lock);
423
424 up(&dev->cmd.event_sem);
425 return err;
426}
427
428/* Invoke a command with an output mailbox */
429static int mthca_cmd_box(struct mthca_dev *dev,
430 u64 in_param,
431 u64 out_param,
432 u32 in_modifier,
433 u8 op_modifier,
434 u16 op,
435 unsigned long timeout,
436 u8 *status)
437{
14abdffc 438 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
1da177e4
LT		 439 return mthca_cmd_wait(dev, in_param, &out_param, 0,
440 in_modifier, op_modifier, op,
441 timeout, status);
442 else
443 return mthca_cmd_poll(dev, in_param, &out_param, 0,
444 in_modifier, op_modifier, op,
445 timeout, status);
446}
447
448/* Invoke a command with no output parameter */
449static int mthca_cmd(struct mthca_dev *dev,
450 u64 in_param,
451 u32 in_modifier,
452 u8 op_modifier,
453 u16 op,
454 unsigned long timeout,
455 u8 *status)
456{
457 return mthca_cmd_box(dev, in_param, 0, in_modifier,
458 op_modifier, op, timeout, status);
459}
460
461/*
462 * Invoke a command with an immediate output parameter (and copy the
463 * output into the caller's out_param pointer after the command
464 * executes).
465 */
466static int mthca_cmd_imm(struct mthca_dev *dev,
467 u64 in_param,
468 u64 *out_param,
469 u32 in_modifier,
470 u8 op_modifier,
471 u16 op,
472 unsigned long timeout,
473 u8 *status)
474{
14abdffc 475 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
1da177e4
LT		 476 return mthca_cmd_wait(dev, in_param, out_param, 1,
477 in_modifier, op_modifier, op,
478 timeout, status);
479 else
480 return mthca_cmd_poll(dev, in_param, out_param, 1,
481 in_modifier, op_modifier, op,
482 timeout, status);
483}
484
80fd8238
RD		 485int mthca_cmd_init(struct mthca_dev *dev)
486{
fd9cfdd1 487 mutex_init(&dev->cmd.hcr_mutex);
80fd8238 488 sema_init(&dev->cmd.poll_sem, 1);
14abdffc 489 dev->cmd.flags = 0;
80fd8238
RD		 490
491 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
492 MTHCA_HCR_SIZE);
493 if (!dev->hcr) {
494 mthca_err(dev, "Couldn't map command register.");
495 return -ENOMEM;
496 }
497
ed878458
RD		 498 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
499 MTHCA_MAILBOX_SIZE,
500 MTHCA_MAILBOX_SIZE, 0);
501 if (!dev->cmd.pool) {
502 iounmap(dev->hcr);
503 return -ENOMEM;
504 }
505
80fd8238
RD		 506 return 0;
507}
508
509void mthca_cmd_cleanup(struct mthca_dev *dev)
510{
ed878458 511 pci_pool_destroy(dev->cmd.pool);
80fd8238 512 iounmap(dev->hcr);
14abdffc
EC		 513 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
514 iounmap(dev->cmd.dbell_map);
80fd8238
RD		 515}
516
1da177e4
LT		 517/*
518 * Switch to using events to issue FW commands (should be called after
519 * event queue to command events has been initialized).
520 */
521int mthca_cmd_use_events(struct mthca_dev *dev)
522{
523 int i;
524
525 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
526 sizeof (struct mthca_cmd_context),
527 GFP_KERNEL);
528 if (!dev->cmd.context)
529 return -ENOMEM;
530
531 for (i = 0; i < dev->cmd.max_cmds; ++i) {
532 dev->cmd.context[i].token = i;
533 dev->cmd.context[i].next = i + 1;
1da177e4
LT		 534 }
535
536 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
537 dev->cmd.free_head = 0;
538
539 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
540 spin_lock_init(&dev->cmd.context_lock);
541
542 for (dev->cmd.token_mask = 1;
543 dev->cmd.token_mask < dev->cmd.max_cmds;
544 dev->cmd.token_mask <<= 1)
545 ; /* nothing */
546 --dev->cmd.token_mask;
547
14abdffc
EC		 548 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
549
1da177e4
LT		 550 down(&dev->cmd.poll_sem);
551
552 return 0;
553}
554
555/*
556 * Switch back to polling (used when shutting down the device)
557 */
558void mthca_cmd_use_polling(struct mthca_dev *dev)
559{
560 int i;
561
14abdffc 562 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
1da177e4
LT		 563
564 for (i = 0; i < dev->cmd.max_cmds; ++i)
565 down(&dev->cmd.event_sem);
566
567 kfree(dev->cmd.context);
568
569 up(&dev->cmd.poll_sem);
570}
571
ed878458 572struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
87b750dc 573 gfp_t gfp_mask)
ed878458
RD		 574{
575 struct mthca_mailbox *mailbox;
576
577 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
578 if (!mailbox)
579 return ERR_PTR(-ENOMEM);
580
581 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
582 if (!mailbox->buf) {
583 kfree(mailbox);
584 return ERR_PTR(-ENOMEM);
585 }
586
587 return mailbox;
588}
589
590void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
591{
592 if (!mailbox)
593 return;
594
595 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
596 kfree(mailbox);
597}
598
1da177e4
LT		 599int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
600{
601 u64 out;
602 int ret;
603
8531f1f1 604 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D, status);
1da177e4
LT		 605
606 if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
607 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
608 "sladdr=%d, SPD source=%s\n",
609 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
610 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
611
612 return ret;
613}
614
615int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
616{
8531f1f1 617 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
1da177e4
LT		 618}
619
620static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
621 u64 virt, u8 *status)
622{
ed878458 623 struct mthca_mailbox *mailbox;
1da177e4 624 struct mthca_icm_iter iter;
ed878458 625 __be64 *pages;
1da177e4
LT		 626 int lg;
627 int nent = 0;
628 int i;
629 int err = 0;
630 int ts = 0, tc = 0;
631
ed878458
RD		 632 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
633 if (IS_ERR(mailbox))
634 return PTR_ERR(mailbox);
635 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
636 pages = mailbox->buf;
1da177e4
LT		 637
638 for (mthca_icm_first(icm, &iter);
639 !mthca_icm_last(&iter);
640 mthca_icm_next(&iter)) {
641 /*
642 * We have to pass pages that are aligned to their
643 * size, so find the least significant 1 in the
644 * address or size and use that as our log2 size.
645 */
646 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
8d3ef29d
IR		 647 if (lg < MTHCA_ICM_PAGE_SHIFT) {
648 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
649 MTHCA_ICM_PAGE_SIZE,
1da177e4
LT		 650 (unsigned long long) mthca_icm_addr(&iter),
651 mthca_icm_size(&iter));
652 err = -EINVAL;
653 goto out;
654 }
59f174fa 655 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
1da177e4 656 if (virt != -1) {
ed878458 657 pages[nent * 2] = cpu_to_be64(virt);
1da177e4
LT		 658 virt += 1 << lg;
659 }
660
8d3ef29d
IR		 661 pages[nent * 2 + 1] =
662 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
663 (lg - MTHCA_ICM_PAGE_SHIFT));
1da177e4
LT		 664 ts += 1 << (lg - 10);
665 ++tc;
666
44dd823b 667 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
ed878458 668 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
1da177e4
LT		 669 CMD_TIME_CLASS_B, status);
670 if (err || *status)
671 goto out;
672 nent = 0;
673 }
674 }
675 }
676
677 if (nent)
ed878458 678 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
1da177e4
LT		 679 CMD_TIME_CLASS_B, status);
680
681 switch (op) {
682 case CMD_MAP_FA:
683 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
684 break;
685 case CMD_MAP_ICM_AUX:
686 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
687 break;
688 case CMD_MAP_ICM:
689 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
690 tc, ts, (unsigned long long) virt - (ts << 10));
691 break;
692 }
693
694out:
ed878458 695 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 696 return err;
697}
698
699int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
700{
701 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
702}
703
704int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
705{
706 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
707}
708
709int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
710{
711 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
712}
713
14abdffc
EC		 714static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
715{
716 unsigned long addr;
717 u16 max_off = 0;
718 int i;
719
720 for (i = 0; i < 8; ++i)
721 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
722
723 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
724 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
725 "length 0x%x crosses a page boundary\n",
726 (unsigned long long) base, max_off);
727 return;
728 }
729
730 addr = pci_resource_start(dev->pdev, 2) +
731 ((pci_resource_len(dev->pdev, 2) - 1) & base);
732 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
733 if (!dev->cmd.dbell_map)
734 return;
735
736 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
737 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
738}
739
1da177e4
LT		 740int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
741{
ed878458 742 struct mthca_mailbox *mailbox;
1da177e4 743 u32 *outbox;
14abdffc
EC		 744 u64 base;
745 u32 tmp;
1da177e4
LT		 746 int err = 0;
747 u8 lg;
14abdffc 748 int i;
1da177e4
LT		 749
750#define QUERY_FW_OUT_SIZE 0x100
751#define QUERY_FW_VER_OFFSET 0x00
752#define QUERY_FW_MAX_CMD_OFFSET 0x0f
753#define QUERY_FW_ERR_START_OFFSET 0x30
754#define QUERY_FW_ERR_SIZE_OFFSET 0x38
755
14abdffc
EC		 756#define QUERY_FW_CMD_DB_EN_OFFSET 0x10
757#define QUERY_FW_CMD_DB_OFFSET 0x50
758#define QUERY_FW_CMD_DB_BASE 0x60
759
1da177e4
LT		 760#define QUERY_FW_START_OFFSET 0x20
761#define QUERY_FW_END_OFFSET 0x28
762
763#define QUERY_FW_SIZE_OFFSET 0x00
764#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
765#define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
766#define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
767
ed878458
RD		 768 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
769 if (IS_ERR(mailbox))
770 return PTR_ERR(mailbox);
771 outbox = mailbox->buf;
1da177e4 772
ed878458 773 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
1da177e4
LT		 774 CMD_TIME_CLASS_A, status);
775
776 if (err)
777 goto out;
778
779 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
780 /*
3e1db334 781 * FW subminor version is at more significant bits than minor
1da177e4
LT		 782 * version, so swap here.
783 */
784 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
785 ((dev->fw_ver & 0xffff0000ull) >> 16) |
786 ((dev->fw_ver & 0x0000ffffull) << 16);
787
8fdf679f
RD		 788 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
789 dev->cmd.max_cmds = 1 << lg;
790
14abdffc
EC		 791 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
792 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
793
3d155f8c
RD		 794 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
795 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1da177e4 796
3d155f8c
RD		 797 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
798 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
1da177e4 799
14abdffc
EC		 800 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
801 if (tmp & 0x1) {
802 mthca_dbg(dev, "FW supports commands through doorbells\n");
803
804 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
805 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
806 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
807 QUERY_FW_CMD_DB_OFFSET + (i << 1));
808
809 mthca_setup_cmd_doorbells(dev, base);
810 }
811
d10ddbf6 812 if (mthca_is_memfree(dev)) {
1da177e4
LT		 813 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
814 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
815 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
816 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
817 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
818
819 /*
8d3ef29d
IR		 820 * Round up number of system pages needed in case
821 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1da177e4
LT		 822 */
823 dev->fw.arbel.fw_pages =
8d3ef29d
IR		 824 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
825 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1da177e4
LT		 826
827 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
828 (unsigned long long) dev->fw.arbel.clr_int_base,
829 (unsigned long long) dev->fw.arbel.eq_arm_base,
830 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
831 } else {
832 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
833 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
834
835 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
836 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
837 (unsigned long long) dev->fw.tavor.fw_start,
838 (unsigned long long) dev->fw.tavor.fw_end);
839 }
840
841out:
ed878458 842 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 843 return err;
844}
845
846int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
847{
ed878458 848 struct mthca_mailbox *mailbox;
1da177e4
LT		 849 u8 info;
850 u32 *outbox;
1da177e4
LT		 851 int err = 0;
852
853#define ENABLE_LAM_OUT_SIZE 0x100
854#define ENABLE_LAM_START_OFFSET 0x00
855#define ENABLE_LAM_END_OFFSET 0x08
856#define ENABLE_LAM_INFO_OFFSET 0x13
857
858#define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
859#define ENABLE_LAM_INFO_ECC_MASK 0x3
860
ed878458
RD		 861 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
862 if (IS_ERR(mailbox))
863 return PTR_ERR(mailbox);
864 outbox = mailbox->buf;
1da177e4 865
ed878458 866 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
1da177e4
LT		 867 CMD_TIME_CLASS_C, status);
868
869 if (err)
870 goto out;
871
872 if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
873 goto out;
874
875 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
876 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
877 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
878
879 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
880 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
881 mthca_info(dev, "FW reports that HCA-attached memory "
882 "is %s hidden; does not match PCI config\n",
883 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
884 "" : "not");
885 }
886 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
887 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
888
889 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
890 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
891 (unsigned long long) dev->ddr_start,
892 (unsigned long long) dev->ddr_end);
893
894out:
ed878458 895 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 896 return err;
897}
898
899int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
900{
901 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
902}
903
904int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
905{
ed878458 906 struct mthca_mailbox *mailbox;
1da177e4
LT		 907 u8 info;
908 u32 *outbox;
1da177e4
LT		 909 int err = 0;
910
911#define QUERY_DDR_OUT_SIZE 0x100
912#define QUERY_DDR_START_OFFSET 0x00
913#define QUERY_DDR_END_OFFSET 0x08
914#define QUERY_DDR_INFO_OFFSET 0x13
915
916#define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
917#define QUERY_DDR_INFO_ECC_MASK 0x3
918
ed878458
RD		 919 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
920 if (IS_ERR(mailbox))
921 return PTR_ERR(mailbox);
922 outbox = mailbox->buf;
1da177e4 923
ed878458 924 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
1da177e4
LT		 925 CMD_TIME_CLASS_A, status);
926
927 if (err)
928 goto out;
929
930 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
931 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
932 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
933
934 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
935 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
936 mthca_info(dev, "FW reports that HCA-attached memory "
937 "is %s hidden; does not match PCI config\n",
938 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
939 "" : "not");
940 }
941 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
942 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
943
944 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
945 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
946 (unsigned long long) dev->ddr_start,
947 (unsigned long long) dev->ddr_end);
948
949out:
ed878458 950 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 951 return err;
952}
953
954int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
955 struct mthca_dev_lim *dev_lim, u8 *status)
956{
ed878458 957 struct mthca_mailbox *mailbox;
1da177e4 958 u32 *outbox;
1da177e4
LT		 959 u8 field;
960 u16 size;
bf6a9e31 961 u16 stat_rate;
1da177e4
LT		 962 int err;
963
964#define QUERY_DEV_LIM_OUT_SIZE 0x100
965#define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
966#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
967#define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
968#define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
969#define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
970#define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
971#define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
972#define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
973#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
974#define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
975#define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
976#define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
977#define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
978#define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
979#define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
980#define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
981#define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
982#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
983#define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
984#define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
985#define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
986#define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
987#define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
988#define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
989#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
990#define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
991#define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
bf6a9e31 992#define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
1da177e4
LT		 993#define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
994#define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
995#define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
996#define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
997#define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
998#define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
999#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
1000#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
1001#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
1002#define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
1003#define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
1004#define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
1005#define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1006#define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1007#define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1008#define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1009#define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1010#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1011#define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1012#define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1013#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1014#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1015#define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1016#define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1017#define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1018#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1019#define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1020#define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1021#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1022#define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1023#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1024
ed878458
RD		 1025 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1026 if (IS_ERR(mailbox))
1027 return PTR_ERR(mailbox);
1028 outbox = mailbox->buf;
1da177e4 1029
ed878458 1030 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1da177e4
LT		 1031 CMD_TIME_CLASS_A, status);
1032
1033 if (err)
1034 goto out;
1035
1da177e4
LT		 1036 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1037 dev_lim->reserved_qps = 1 << (field & 0xf);
1038 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1039 dev_lim->max_qps = 1 << (field & 0x1f);
1040 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1041 dev_lim->reserved_srqs = 1 << (field >> 4);
1042 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1043 dev_lim->max_srqs = 1 << (field & 0x1f);
1044 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1045 dev_lim->reserved_eecs = 1 << (field & 0xf);
1046 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1047 dev_lim->max_eecs = 1 << (field & 0x1f);
1048 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1049 dev_lim->max_cq_sz = 1 << field;
1050 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1051 dev_lim->reserved_cqs = 1 << (field & 0xf);
1052 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1053 dev_lim->max_cqs = 1 << (field & 0x1f);
1054 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1055 dev_lim->max_mpts = 1 << (field & 0x3f);
1056 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1057 dev_lim->reserved_eqs = 1 << (field & 0xf);
1058 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1059 dev_lim->max_eqs = 1 << (field & 0x7);
1060 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
c7d204e8
MT		 1061 if (mthca_is_memfree(dev))
1062 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
c1f67a88 1063 dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
c7d204e8
MT		 1064 else
1065 dev_lim->reserved_mtts = 1 << (field >> 4);
1da177e4
LT		 1066 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1067 dev_lim->max_mrw_sz = 1 << field;
1068 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1069 dev_lim->reserved_mrws = 1 << (field & 0xf);
1070 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1071 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1072 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1073 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1074 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1075 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1076 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1077 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1078 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1079 dev_lim->local_ca_ack_delay = field & 0x1f;
1080 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1081 dev_lim->max_mtu = field >> 4;
1082 dev_lim->max_port_width = field & 0xf;
1083 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1084 dev_lim->max_vl = field >> 4;
1085 dev_lim->num_ports = field & 0xf;
1086 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1087 dev_lim->max_gids = 1 << (field & 0xf);
bf6a9e31
JM		 1088 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1089 dev_lim->stat_rate_support = stat_rate;
1da177e4
LT		 1090 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1091 dev_lim->max_pkeys = 1 << (field & 0xf);
1092 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1093 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1094 dev_lim->reserved_uars = field >> 4;
1095 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1096 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1097 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1098 dev_lim->min_page_sz = 1 << field;
1099 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1100 dev_lim->max_sg = field;
1101
1102 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1103 dev_lim->max_desc_sz = size;
1104
1105 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1106 dev_lim->max_qp_per_mcg = 1 << field;
1107 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1108 dev_lim->reserved_mgms = field & 0xf;
1109 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1110 dev_lim->max_mcgs = 1 << field;
1111 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1112 dev_lim->reserved_pds = field >> 4;
1113 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1114 dev_lim->max_pds = 1 << (field & 0x3f);
1115 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1116 dev_lim->reserved_rdds = field >> 4;
1117 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1118 dev_lim->max_rdds = 1 << (field & 0x3f);
1119
1120 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1121 dev_lim->eec_entry_sz = size;
1122 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1123 dev_lim->qpc_entry_sz = size;
1124 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1125 dev_lim->eeec_entry_sz = size;
1126 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1127 dev_lim->eqpc_entry_sz = size;
1128 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1129 dev_lim->eqc_entry_sz = size;
1130 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1131 dev_lim->cqc_entry_sz = size;
1132 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1133 dev_lim->srq_entry_sz = size;
1134 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1135 dev_lim->uar_scratch_entry_sz = size;
1136
d10ddbf6 1137 if (mthca_is_memfree(dev)) {
a3c8ab4f
JM		 1138 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1139 dev_lim->max_srq_sz = 1 << field;
1140 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1141 dev_lim->max_qp_sz = 1 << field;
1da177e4
LT		 1142 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1143 dev_lim->hca.arbel.resize_srq = field & 1;
8cf2daf3
RD		 1144 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1145 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
77369ed3
JM		 1146 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1147 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1da177e4
LT		 1148 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1149 dev_lim->mpt_entry_sz = size;
1150 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1151 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1152 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1153 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1154 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1155 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1156 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1157 dev_lim->hca.arbel.lam_required = field & 1;
1158 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1159 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1160
1161 if (dev_lim->hca.arbel.bmme_flags & 1)
1162 mthca_dbg(dev, "Base MM extensions: yes "
1163 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1164 dev_lim->hca.arbel.bmme_flags,
1165 dev_lim->hca.arbel.max_pbl_sz,
1166 dev_lim->hca.arbel.reserved_lkey);
1167 else
1168 mthca_dbg(dev, "Base MM extensions: no\n");
1169
1170 mthca_dbg(dev, "Max ICM size %lld MB\n",
1171 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1172 } else {
a3c8ab4f
JM		 1173 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1174 dev_lim->max_srq_sz = (1 << field) - 1;
1175 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1176 dev_lim->max_qp_sz = (1 << field) - 1;
1da177e4
LT		 1177 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1178 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1da177e4
LT		 1179 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1180 }
1181
f295c79b
RD		 1182 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1183 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1184 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1185 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1186 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1187 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1188 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1189 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1190 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1191 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1192 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1193 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1194 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1195 dev_lim->max_pds, dev_lim->reserved_mgms);
1196 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1197 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1198
1199 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1200
1da177e4 1201out:
ed878458 1202 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1203 return err;
1204}
1205
2e8b981c
MT		 1206static void get_board_id(void *vsd, char *board_id)
1207{
1208 int i;
1209
1210#define VSD_OFFSET_SIG1 0x00
1211#define VSD_OFFSET_SIG2 0xde
1212#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1213#define VSD_OFFSET_TS_BOARD_ID 0x20
1214
1215#define VSD_SIGNATURE_TOPSPIN 0x5ad
1216
1217 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1218
1219 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1220 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1221 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1222 } else {
1223 /*
1224 * The board ID is a string but the firmware byte
1225 * swaps each 4-byte word before passing it back to
1226 * us. Therefore we need to swab it before printing.
1227 */
1228 for (i = 0; i < 4; ++i)
1229 ((u32 *) board_id)[i] =
1230 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1231 }
1232}
1233
1da177e4
LT		 1234int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1235 struct mthca_adapter *adapter, u8 *status)
1236{
ed878458 1237 struct mthca_mailbox *mailbox;
1da177e4 1238 u32 *outbox;
1da177e4
LT		 1239 int err;
1240
1241#define QUERY_ADAPTER_OUT_SIZE 0x100
1242#define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1243#define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1244#define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1245#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
2e8b981c 1246#define QUERY_ADAPTER_VSD_OFFSET 0x20
1da177e4 1247
ed878458
RD		 1248 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1249 if (IS_ERR(mailbox))
1250 return PTR_ERR(mailbox);
1251 outbox = mailbox->buf;
1da177e4 1252
ed878458 1253 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1da177e4
LT		 1254 CMD_TIME_CLASS_A, status);
1255
1256 if (err)
1257 goto out;
1258
6ccef1de
JM		 1259 if (!mthca_is_memfree(dev)) {
1260 MTHCA_GET(adapter->vendor_id, outbox,
1261 QUERY_ADAPTER_VENDOR_ID_OFFSET);
1262 MTHCA_GET(adapter->device_id, outbox,
1263 QUERY_ADAPTER_DEVICE_ID_OFFSET);
1264 MTHCA_GET(adapter->revision_id, outbox,
1265 QUERY_ADAPTER_REVISION_ID_OFFSET);
1266 }
ed878458 1267 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1da177e4 1268
2e8b981c
MT		 1269 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1270 adapter->board_id);
1271
1da177e4 1272out:
ed878458 1273 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1274 return err;
1275}
1276
1277int mthca_INIT_HCA(struct mthca_dev *dev,
1278 struct mthca_init_hca_param *param,
1279 u8 *status)
1280{
ed878458 1281 struct mthca_mailbox *mailbox;
97f52eb4 1282 __be32 *inbox;
1da177e4
LT		 1283 int err;
1284
1285#define INIT_HCA_IN_SIZE 0x200
651eaac9
EC		 1286#define INIT_HCA_FLAGS1_OFFSET 0x00c
1287#define INIT_HCA_FLAGS2_OFFSET 0x014
1da177e4
LT		 1288#define INIT_HCA_QPC_OFFSET 0x020
1289#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1290#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1291#define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1292#define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1293#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1294#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1295#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1296#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1297#define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1298#define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1299#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1300#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1301#define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1302#define INIT_HCA_UDAV_OFFSET 0x0b0
1303#define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1304#define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1305#define INIT_HCA_MCAST_OFFSET 0x0c0
1306#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1307#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1308#define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1309#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1310#define INIT_HCA_TPT_OFFSET 0x0f0
1311#define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1312#define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1313#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1314#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1315#define INIT_HCA_UAR_OFFSET 0x120
1316#define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1317#define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1318#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1319#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1320#define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1321#define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1322
ed878458
RD		 1323 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1324 if (IS_ERR(mailbox))
1325 return PTR_ERR(mailbox);
1326 inbox = mailbox->buf;
1da177e4
LT		 1327
1328 memset(inbox, 0, INIT_HCA_IN_SIZE);
1329
651eaac9
EC		 1330 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1331 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1332
1da177e4 1333#if defined(__LITTLE_ENDIAN)
651eaac9 1334 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1da177e4 1335#elif defined(__BIG_ENDIAN)
651eaac9 1336 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1da177e4
LT		 1337#else
1338#error Host endianness not defined
1339#endif
1340 /* Check port for UD address vector: */
651eaac9 1341 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1da177e4 1342
680b575f
EC		 1343 /* Enable IPoIB checksumming if we can: */
1344 if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1345 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1346
1da177e4
LT		 1347 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1348
1349 /* QPC/EEC/CQC/EQC/RDB attributes */
1350
1351 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1352 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1353 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1354 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1355 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1356 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1357 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1358 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1359 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1360 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1361 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1362 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1363 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1364
1365 /* UD AV attributes */
1366
1367 /* multicast attributes */
1368
1369 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1370 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1371 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1372 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1373
1374 /* TPT attributes */
1375
1376 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
d10ddbf6 1377 if (!mthca_is_memfree(dev))
1da177e4
LT		 1378 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1379 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1380 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1381
1382 /* UAR attributes */
1383 {
1384 u8 uar_page_sz = PAGE_SHIFT - 12;
1385 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1386 }
1387
1388 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1389
d10ddbf6 1390 if (mthca_is_memfree(dev)) {
1da177e4
LT		 1391 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1392 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1393 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1394 }
1395
8531f1f1 1396 err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, CMD_TIME_CLASS_D, status);
1da177e4 1397
ed878458 1398 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1399 return err;
1400}
1401
1402int mthca_INIT_IB(struct mthca_dev *dev,
1403 struct mthca_init_ib_param *param,
1404 int port, u8 *status)
1405{
ed878458 1406 struct mthca_mailbox *mailbox;
1da177e4 1407 u32 *inbox;
1da177e4
LT		 1408 int err;
1409 u32 flags;
1410
1411#define INIT_IB_IN_SIZE 56
1412#define INIT_IB_FLAGS_OFFSET 0x00
1413#define INIT_IB_FLAG_SIG (1 << 18)
1414#define INIT_IB_FLAG_NG (1 << 17)
1415#define INIT_IB_FLAG_G0 (1 << 16)
1da177e4 1416#define INIT_IB_VL_SHIFT 4
da6561c2 1417#define INIT_IB_PORT_WIDTH_SHIFT 8
1da177e4
LT		 1418#define INIT_IB_MTU_SHIFT 12
1419#define INIT_IB_MAX_GID_OFFSET 0x06
1420#define INIT_IB_MAX_PKEY_OFFSET 0x0a
1421#define INIT_IB_GUID0_OFFSET 0x10
1422#define INIT_IB_NODE_GUID_OFFSET 0x18
1423#define INIT_IB_SI_GUID_OFFSET 0x20
1424
ed878458
RD		 1425 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1426 if (IS_ERR(mailbox))
1427 return PTR_ERR(mailbox);
1428 inbox = mailbox->buf;
1da177e4
LT		 1429
1430 memset(inbox, 0, INIT_IB_IN_SIZE);
1431
1432 flags = 0;
1da177e4
LT		 1433 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1434 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1435 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1436 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
da6561c2 1437 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1da177e4
LT		 1438 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1439 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1440
1441 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1442 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1443 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1444 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1445 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1446
ed878458 1447 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1da177e4
LT		 1448 CMD_TIME_CLASS_A, status);
1449
ed878458 1450 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1451 return err;
1452}
1453
1454int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
1455{
8531f1f1 1456 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A, status);
1da177e4
LT		 1457}
1458
1459int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
1460{
8531f1f1 1461 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C, status);
1da177e4
LT		 1462}
1463
1464int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1465 int port, u8 *status)
1466{
ed878458 1467 struct mthca_mailbox *mailbox;
1da177e4 1468 u32 *inbox;
1da177e4
LT		 1469 int err;
1470 u32 flags = 0;
1471
1472#define SET_IB_IN_SIZE 0x40
1473#define SET_IB_FLAGS_OFFSET 0x00
1474#define SET_IB_FLAG_SIG (1 << 18)
1475#define SET_IB_FLAG_RQK (1 << 0)
1476#define SET_IB_CAP_MASK_OFFSET 0x04
1477#define SET_IB_SI_GUID_OFFSET 0x08
1478
ed878458
RD		 1479 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1480 if (IS_ERR(mailbox))
1481 return PTR_ERR(mailbox);
1482 inbox = mailbox->buf;
1da177e4
LT		 1483
1484 memset(inbox, 0, SET_IB_IN_SIZE);
1485
1486 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1487 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1488 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1489
1490 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1491 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1492
ed878458 1493 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1da177e4
LT		 1494 CMD_TIME_CLASS_B, status);
1495
ed878458 1496 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1497 return err;
1498}
1499
1500int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
1501{
1502 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
1503}
1504
1505int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
1506{
ed878458 1507 struct mthca_mailbox *mailbox;
97f52eb4 1508 __be64 *inbox;
1da177e4
LT		 1509 int err;
1510
ed878458
RD		 1511 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1512 if (IS_ERR(mailbox))
1513 return PTR_ERR(mailbox);
1514 inbox = mailbox->buf;
1da177e4
LT		 1515
1516 inbox[0] = cpu_to_be64(virt);
1517 inbox[1] = cpu_to_be64(dma_addr);
1518
ed878458
RD		 1519 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1520 CMD_TIME_CLASS_B, status);
1da177e4 1521
ed878458 1522 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 1523
1524 if (!err)
6bd6228e
RD		 1525 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1526 (unsigned long long) dma_addr, (unsigned long long) virt);
1da177e4
LT		 1527
1528 return err;
1529}
1530
1531int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
1532{
1533 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1534 page_count, (unsigned long long) virt);
1535
1536 return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
1537}
1538
1539int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
1540{
1541 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
1542}
1543
1544int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
1545{
1546 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
1547}
1548
1549int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
1550 u8 *status)
1551{
1552 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
1553 CMD_TIME_CLASS_A, status);
1554
1555 if (ret || status)
1556 return ret;
1557
1558 /*
8d3ef29d
IR		 1559 * Round up number of system pages needed in case
1560 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1da177e4 1561 */
8d3ef29d
IR		 1562 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1563 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1da177e4
LT		 1564
1565 return 0;
1566}
1567
ed878458 1568int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1569 int mpt_index, u8 *status)
1570{
ed878458
RD		 1571 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1572 CMD_TIME_CLASS_B, status);
1da177e4
LT		 1573}
1574
ed878458 1575int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1576 int mpt_index, u8 *status)
1577{
ed878458
RD		 1578 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1579 !mailbox, CMD_HW2SW_MPT,
1580 CMD_TIME_CLASS_B, status);
1da177e4
LT		 1581}
1582
ed878458 1583int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1584 int num_mtt, u8 *status)
1585{
ed878458
RD		 1586 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1587 CMD_TIME_CLASS_B, status);
1da177e4
LT		 1588}
1589
b8ca06f6
MT		 1590int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
1591{
1592 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
1593}
1594
1da177e4
LT		 1595int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1596 int eq_num, u8 *status)
1597{
1598 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1599 unmap ? "Clearing" : "Setting",
1600 (unsigned long long) event_mask, eq_num);
1601 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1602 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
1603}
1604
ed878458 1605int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1606 int eq_num, u8 *status)
1607{
ed878458
RD		 1608 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1609 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1610}
1611
ed878458 1612int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1613 int eq_num, u8 *status)
1614{
ed878458
RD		 1615 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1616 CMD_HW2SW_EQ,
1617 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1618}
1619
ed878458 1620int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1621 int cq_num, u8 *status)
1622{
ed878458 1623 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1da177e4 1624 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1625}
1626
ed878458 1627int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1da177e4
LT		 1628 int cq_num, u8 *status)
1629{
ed878458
RD		 1630 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1631 CMD_HW2SW_CQ,
1632 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1633}
1634
4885bf64
RD		 1635int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
1636 u8 *status)
1637{
1638 struct mthca_mailbox *mailbox;
1639 __be32 *inbox;
1640 int err;
1641
1642#define RESIZE_CQ_IN_SIZE 0x40
1643#define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1644#define RESIZE_CQ_LKEY_OFFSET 0x1c
1645
1646 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1647 if (IS_ERR(mailbox))
1648 return PTR_ERR(mailbox);
1649 inbox = mailbox->buf;
1650
1651 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1652 /*
1653 * Leave start address fields zeroed out -- mthca assumes that
1654 * MRs for CQs always start at virtual address 0.
1655 */
1656 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1657 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1658
1659 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1660 CMD_TIME_CLASS_B, status);
1661
1662 mthca_free_mailbox(dev, mailbox);
1663 return err;
1664}
1665
ec34a922
RD		 1666int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1667 int srq_num, u8 *status)
1668{
1669 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1670 CMD_TIME_CLASS_A, status);
1671}
1672
1673int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1674 int srq_num, u8 *status)
1675{
1676 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1677 CMD_HW2SW_SRQ,
1678 CMD_TIME_CLASS_A, status);
1679}
1680
8ebe5077
EC		 1681int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1682 struct mthca_mailbox *mailbox, u8 *status)
1683{
1684 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1685 CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status);
1686}
1687
ec34a922
RD		 1688int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1689{
1690 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1691 CMD_TIME_CLASS_B, status);
1692}
1693
d844183d
RD		 1694int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1695 enum ib_qp_state next, u32 num, int is_ee,
1696 struct mthca_mailbox *mailbox, u32 optmask,
1da177e4
LT		 1697 u8 *status)
1698{
d844183d
RD		 1699 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1700 [IB_QPS_RESET] = {
1701 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1702 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1703 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1704 },
1705 [IB_QPS_INIT] = {
1706 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1707 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1708 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1709 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1710 },
1711 [IB_QPS_RTR] = {
1712 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1713 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1714 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1715 },
1716 [IB_QPS_RTS] = {
1717 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1718 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1719 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1720 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1721 },
1722 [IB_QPS_SQD] = {
1723 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1724 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1725 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1726 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1727 },
1728 [IB_QPS_SQE] = {
1729 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1730 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1731 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1732 },
1733 [IB_QPS_ERR] = {
1734 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1735 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1736 }
1da177e4 1737 };
d844183d 1738
1da177e4 1739 u8 op_mod = 0;
ed878458 1740 int my_mailbox = 0;
1da177e4
LT		 1741 int err;
1742
d844183d 1743 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1da177e4
LT		 1744 op_mod = 3; /* don't write outbox, any->reset */
1745
1746 /* For debugging */
ed878458
RD		 1747 if (!mailbox) {
1748 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1749 if (!IS_ERR(mailbox)) {
1750 my_mailbox = 1;
1751 op_mod = 2; /* write outbox, any->reset */
1752 } else
1753 mailbox = NULL;
1754 }
d844183d
RD		 1755
1756 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1757 (!!is_ee << 24) | num, op_mod,
1758 op[cur][next], CMD_TIME_CLASS_C, status);
1759
1760 if (0 && mailbox) {
1da177e4
LT		 1761 int i;
1762 mthca_dbg(dev, "Dumping QP context:\n");
d844183d 1763 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1da177e4
LT		 1764 for (i = 0; i < 0x100 / 4; ++i) {
1765 if (i % 8 == 0)
d844183d 1766 printk("[%02x] ", i * 4);
ed878458 1767 printk(" %08x",
97f52eb4 1768 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1da177e4
LT		 1769 if ((i + 1) % 8 == 0)
1770 printk("\n");
1771 }
1772 }
1da177e4 1773
d844183d
RD		 1774 if (my_mailbox)
1775 mthca_free_mailbox(dev, mailbox);
1776 } else {
1777 if (0) {
1da177e4
LT		 1778 int i;
1779 mthca_dbg(dev, "Dumping QP context:\n");
d844183d 1780 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1da177e4
LT		 1781 for (i = 0; i < 0x100 / 4; ++i) {
1782 if (i % 8 == 0)
d844183d 1783 printk(" [%02x] ", i * 4);
ed878458 1784 printk(" %08x",
97f52eb4 1785 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1da177e4
LT		 1786 if ((i + 1) % 8 == 0)
1787 printk("\n");
1788 }
1789 }
1790
d844183d
RD		 1791 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1792 op_mod, op[cur][next], CMD_TIME_CLASS_C, status);
1793 }
ed878458 1794
1da177e4
LT		 1795 return err;
1796}
1797
1798int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
ed878458 1799 struct mthca_mailbox *mailbox, u8 *status)
1da177e4 1800{
ed878458
RD		 1801 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1802 CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
1da177e4
LT		 1803}
1804
1805int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
1806 u8 *status)
1807{
1808 u8 op_mod;
1809
1810 switch (type) {
1811 case IB_QPT_SMI:
1812 op_mod = 0;
1813 break;
1814 case IB_QPT_GSI:
1815 op_mod = 1;
1816 break;
1817 case IB_QPT_RAW_IPV6:
1818 op_mod = 2;
1819 break;
1820 case IB_QPT_RAW_ETY:
1821 op_mod = 3;
1822 break;
1823 default:
1824 return -EINVAL;
1825 }
1826
1827 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1828 CMD_TIME_CLASS_B, status);
1829}
1830
1831int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
ed878458 1832 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1da177e4
LT		 1833 void *in_mad, void *response_mad, u8 *status)
1834{
ed878458
RD		 1835 struct mthca_mailbox *inmailbox, *outmailbox;
1836 void *inbox;
1da177e4
LT		 1837 int err;
1838 u32 in_modifier = port;
1839 u8 op_modifier = 0;
1840
1841#define MAD_IFC_BOX_SIZE 0x400
1842#define MAD_IFC_MY_QPN_OFFSET 0x100
68586b67
MT		 1843#define MAD_IFC_RQPN_OFFSET 0x108
1844#define MAD_IFC_SL_OFFSET 0x10c
1845#define MAD_IFC_G_PATH_OFFSET 0x10d
1846#define MAD_IFC_RLID_OFFSET 0x10e
1847#define MAD_IFC_PKEY_OFFSET 0x112
1da177e4
LT		 1848#define MAD_IFC_GRH_OFFSET 0x140
1849
ed878458
RD		 1850 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1851 if (IS_ERR(inmailbox))
1852 return PTR_ERR(inmailbox);
1853 inbox = inmailbox->buf;
1854
1855 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1856 if (IS_ERR(outmailbox)) {
1857 mthca_free_mailbox(dev, inmailbox);
1858 return PTR_ERR(outmailbox);
1859 }
1da177e4 1860
ed878458 1861 memcpy(inbox, in_mad, 256);
1da177e4
LT		 1862
1863 /*
1864 * Key check traps can't be generated unless we have in_wc to
1865 * tell us where to send the trap.
1866 */
1867 if (ignore_mkey || !in_wc)
1868 op_modifier |= 0x1;
1869 if (ignore_bkey || !in_wc)
1870 op_modifier |= 0x2;
1871
1872 if (in_wc) {
1873 u8 val;
1874
ed878458 1875 memset(inbox + 256, 0, 256);
1da177e4 1876
062dbb69 1877 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
ed878458 1878 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1da177e4
LT		 1879
1880 val = in_wc->sl << 4;
ed878458 1881 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1da177e4
LT		 1882
1883 val = in_wc->dlid_path_bits |
1884 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
68586b67 1885 MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET);
1da177e4 1886
ed878458
RD		 1887 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
1888 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1da177e4
LT		 1889
1890 if (in_grh)
ed878458 1891 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1da177e4 1892
68586b67 1893 op_modifier |= 0x4;
1da177e4
LT		 1894
1895 in_modifier |= in_wc->slid << 16;
1896 }
1897
ed878458
RD		 1898 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1899 in_modifier, op_modifier,
1da177e4
LT		 1900 CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
1901
1902 if (!err && !*status)
ed878458 1903 memcpy(response_mad, outmailbox->buf, 256);
1da177e4 1904
ed878458
RD		 1905 mthca_free_mailbox(dev, inmailbox);
1906 mthca_free_mailbox(dev, outmailbox);
1da177e4
LT		 1907 return err;
1908}
1909
ed878458
RD		 1910int mthca_READ_MGM(struct mthca_dev *dev, int index,
1911 struct mthca_mailbox *mailbox, u8 *status)
1da177e4 1912{
ed878458
RD		 1913 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1914 CMD_READ_MGM, CMD_TIME_CLASS_A, status);
1da177e4
LT		 1915}
1916
ed878458
RD		 1917int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1918 struct mthca_mailbox *mailbox, u8 *status)
1da177e4 1919{
ed878458
RD		 1920 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1921 CMD_TIME_CLASS_A, status);
1da177e4
LT		 1922}
1923
ed878458
RD		 1924int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1925 u16 *hash, u8 *status)
1da177e4 1926{
1da177e4
LT		 1927 u64 imm;
1928 int err;
1929
ed878458 1930 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1da177e4 1931 CMD_TIME_CLASS_A, status);
1da177e4 1932
ed878458 1933 *hash = imm;
1da177e4
LT		 1934 return err;
1935}
1936
1937int mthca_NOP(struct mthca_dev *dev, u8 *status)
1938{
1939 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
1940}
Ubuntu Artful kernel mirror