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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
2a1d9b7f | 3 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. |
4885bf64 | 4 | * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. |
1da177e4 LT |
5 | * |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | * | |
34 | * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $ | |
35 | */ | |
36 | ||
2a214182 | 37 | #include <linux/completion.h> |
1da177e4 LT |
38 | #include <linux/pci.h> |
39 | #include <linux/errno.h> | |
e8edc6e0 | 40 | #include <linux/sched.h> |
1da177e4 | 41 | #include <asm/io.h> |
a4d61e84 | 42 | #include <rdma/ib_mad.h> |
1da177e4 LT |
43 | |
44 | #include "mthca_dev.h" | |
45 | #include "mthca_config_reg.h" | |
46 | #include "mthca_cmd.h" | |
47 | #include "mthca_memfree.h" | |
48 | ||
49 | #define CMD_POLL_TOKEN 0xffff | |
50 | ||
51 | enum { | |
52 | HCR_IN_PARAM_OFFSET = 0x00, | |
53 | HCR_IN_MODIFIER_OFFSET = 0x08, | |
54 | HCR_OUT_PARAM_OFFSET = 0x0c, | |
55 | HCR_TOKEN_OFFSET = 0x14, | |
56 | HCR_STATUS_OFFSET = 0x18, | |
57 | ||
58 | HCR_OPMOD_SHIFT = 12, | |
59 | HCA_E_BIT = 22, | |
60 | HCR_GO_BIT = 23 | |
61 | }; | |
62 | ||
63 | enum { | |
64 | /* initialization and general commands */ | |
65 | CMD_SYS_EN = 0x1, | |
66 | CMD_SYS_DIS = 0x2, | |
67 | CMD_MAP_FA = 0xfff, | |
68 | CMD_UNMAP_FA = 0xffe, | |
69 | CMD_RUN_FW = 0xff6, | |
70 | CMD_MOD_STAT_CFG = 0x34, | |
71 | CMD_QUERY_DEV_LIM = 0x3, | |
72 | CMD_QUERY_FW = 0x4, | |
73 | CMD_ENABLE_LAM = 0xff8, | |
74 | CMD_DISABLE_LAM = 0xff7, | |
75 | CMD_QUERY_DDR = 0x5, | |
76 | CMD_QUERY_ADAPTER = 0x6, | |
77 | CMD_INIT_HCA = 0x7, | |
78 | CMD_CLOSE_HCA = 0x8, | |
79 | CMD_INIT_IB = 0x9, | |
80 | CMD_CLOSE_IB = 0xa, | |
81 | CMD_QUERY_HCA = 0xb, | |
82 | CMD_SET_IB = 0xc, | |
83 | CMD_ACCESS_DDR = 0x2e, | |
84 | CMD_MAP_ICM = 0xffa, | |
85 | CMD_UNMAP_ICM = 0xff9, | |
86 | CMD_MAP_ICM_AUX = 0xffc, | |
87 | CMD_UNMAP_ICM_AUX = 0xffb, | |
88 | CMD_SET_ICM_SIZE = 0xffd, | |
89 | ||
90 | /* TPT commands */ | |
91 | CMD_SW2HW_MPT = 0xd, | |
92 | CMD_QUERY_MPT = 0xe, | |
93 | CMD_HW2SW_MPT = 0xf, | |
94 | CMD_READ_MTT = 0x10, | |
95 | CMD_WRITE_MTT = 0x11, | |
96 | CMD_SYNC_TPT = 0x2f, | |
97 | ||
98 | /* EQ commands */ | |
99 | CMD_MAP_EQ = 0x12, | |
100 | CMD_SW2HW_EQ = 0x13, | |
101 | CMD_HW2SW_EQ = 0x14, | |
102 | CMD_QUERY_EQ = 0x15, | |
103 | ||
104 | /* CQ commands */ | |
105 | CMD_SW2HW_CQ = 0x16, | |
106 | CMD_HW2SW_CQ = 0x17, | |
107 | CMD_QUERY_CQ = 0x18, | |
108 | CMD_RESIZE_CQ = 0x2c, | |
109 | ||
110 | /* SRQ commands */ | |
111 | CMD_SW2HW_SRQ = 0x35, | |
112 | CMD_HW2SW_SRQ = 0x36, | |
113 | CMD_QUERY_SRQ = 0x37, | |
ec34a922 | 114 | CMD_ARM_SRQ = 0x40, |
1da177e4 LT |
115 | |
116 | /* QP/EE commands */ | |
117 | CMD_RST2INIT_QPEE = 0x19, | |
118 | CMD_INIT2RTR_QPEE = 0x1a, | |
119 | CMD_RTR2RTS_QPEE = 0x1b, | |
120 | CMD_RTS2RTS_QPEE = 0x1c, | |
121 | CMD_SQERR2RTS_QPEE = 0x1d, | |
122 | CMD_2ERR_QPEE = 0x1e, | |
123 | CMD_RTS2SQD_QPEE = 0x1f, | |
124 | CMD_SQD2SQD_QPEE = 0x38, | |
125 | CMD_SQD2RTS_QPEE = 0x20, | |
126 | CMD_ERR2RST_QPEE = 0x21, | |
127 | CMD_QUERY_QPEE = 0x22, | |
128 | CMD_INIT2INIT_QPEE = 0x2d, | |
129 | CMD_SUSPEND_QPEE = 0x32, | |
130 | CMD_UNSUSPEND_QPEE = 0x33, | |
131 | /* special QPs and management commands */ | |
132 | CMD_CONF_SPECIAL_QP = 0x23, | |
133 | CMD_MAD_IFC = 0x24, | |
134 | ||
135 | /* multicast commands */ | |
136 | CMD_READ_MGM = 0x25, | |
137 | CMD_WRITE_MGM = 0x26, | |
138 | CMD_MGID_HASH = 0x27, | |
139 | ||
140 | /* miscellaneous commands */ | |
141 | CMD_DIAG_RPRT = 0x30, | |
142 | CMD_NOP = 0x31, | |
143 | ||
144 | /* debug commands */ | |
145 | CMD_QUERY_DEBUG_MSG = 0x2a, | |
146 | CMD_SET_DEBUG_MSG = 0x2b, | |
147 | }; | |
148 | ||
149 | /* | |
150 | * According to Mellanox code, FW may be starved and never complete | |
151 | * commands. So we can't use strict timeouts described in PRM -- we | |
152 | * just arbitrarily select 60 seconds for now. | |
153 | */ | |
154 | #if 0 | |
155 | /* | |
156 | * Round up and add 1 to make sure we get the full wait time (since we | |
157 | * will be starting in the middle of a jiffy) | |
158 | */ | |
159 | enum { | |
160 | CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1, | |
161 | CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1, | |
162 | CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1 | |
163 | }; | |
164 | #else | |
165 | enum { | |
166 | CMD_TIME_CLASS_A = 60 * HZ, | |
167 | CMD_TIME_CLASS_B = 60 * HZ, | |
168 | CMD_TIME_CLASS_C = 60 * HZ | |
169 | }; | |
170 | #endif | |
171 | ||
172 | enum { | |
173 | GO_BIT_TIMEOUT = HZ * 10 | |
174 | }; | |
175 | ||
176 | struct mthca_cmd_context { | |
177 | struct completion done; | |
1da177e4 LT |
178 | int result; |
179 | int next; | |
180 | u64 out_param; | |
181 | u16 token; | |
182 | u8 status; | |
183 | }; | |
184 | ||
1db76c14 | 185 | static int fw_cmd_doorbell = 0; |
14abdffc EC |
186 | module_param(fw_cmd_doorbell, int, 0644); |
187 | MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero " | |
188 | "(and supported by FW)"); | |
189 | ||
1da177e4 LT |
190 | static inline int go_bit(struct mthca_dev *dev) |
191 | { | |
192 | return readl(dev->hcr + HCR_STATUS_OFFSET) & | |
193 | swab32(1 << HCR_GO_BIT); | |
194 | } | |
195 | ||
14abdffc EC |
196 | static void mthca_cmd_post_dbell(struct mthca_dev *dev, |
197 | u64 in_param, | |
198 | u64 out_param, | |
199 | u32 in_modifier, | |
200 | u8 op_modifier, | |
201 | u16 op, | |
202 | u16 token) | |
1da177e4 | 203 | { |
14abdffc EC |
204 | void __iomem *ptr = dev->cmd.dbell_map; |
205 | u16 *offs = dev->cmd.dbell_offsets; | |
1da177e4 | 206 | |
14abdffc EC |
207 | __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]); |
208 | wmb(); | |
209 | __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]); | |
210 | wmb(); | |
211 | __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]); | |
212 | wmb(); | |
213 | __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]); | |
214 | wmb(); | |
215 | __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]); | |
216 | wmb(); | |
217 | __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]); | |
218 | wmb(); | |
219 | __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | | |
220 | (1 << HCA_E_BIT) | | |
221 | (op_modifier << HCR_OPMOD_SHIFT) | | |
b3999393 | 222 | op), ptr + offs[6]); |
14abdffc EC |
223 | wmb(); |
224 | __raw_writel((__force u32) 0, ptr + offs[7]); | |
225 | wmb(); | |
226 | } | |
1da177e4 | 227 | |
14abdffc EC |
228 | static int mthca_cmd_post_hcr(struct mthca_dev *dev, |
229 | u64 in_param, | |
230 | u64 out_param, | |
231 | u32 in_modifier, | |
232 | u8 op_modifier, | |
233 | u16 op, | |
234 | u16 token, | |
235 | int event) | |
236 | { | |
1da177e4 LT |
237 | if (event) { |
238 | unsigned long end = jiffies + GO_BIT_TIMEOUT; | |
239 | ||
240 | while (go_bit(dev) && time_before(jiffies, end)) { | |
241 | set_current_state(TASK_RUNNING); | |
242 | schedule(); | |
243 | } | |
244 | } | |
245 | ||
14abdffc EC |
246 | if (go_bit(dev)) |
247 | return -EAGAIN; | |
1da177e4 LT |
248 | |
249 | /* | |
250 | * We use writel (instead of something like memcpy_toio) | |
251 | * because writes of less than 32 bits to the HCR don't work | |
252 | * (and some architectures such as ia64 implement memcpy_toio | |
253 | * in terms of writeb). | |
254 | */ | |
97f52eb4 SH |
255 | __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); |
256 | __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); | |
257 | __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); | |
258 | __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); | |
259 | __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); | |
260 | __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); | |
1da177e4 LT |
261 | |
262 | /* __raw_writel may not order writes. */ | |
263 | wmb(); | |
264 | ||
97f52eb4 SH |
265 | __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | |
266 | (event ? (1 << HCA_E_BIT) : 0) | | |
267 | (op_modifier << HCR_OPMOD_SHIFT) | | |
268 | op), dev->hcr + 6 * 4); | |
1da177e4 | 269 | |
14abdffc EC |
270 | return 0; |
271 | } | |
272 | ||
273 | static int mthca_cmd_post(struct mthca_dev *dev, | |
274 | u64 in_param, | |
275 | u64 out_param, | |
276 | u32 in_modifier, | |
277 | u8 op_modifier, | |
278 | u16 op, | |
279 | u16 token, | |
280 | int event) | |
281 | { | |
282 | int err = 0; | |
283 | ||
284 | mutex_lock(&dev->cmd.hcr_mutex); | |
285 | ||
286 | if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell) | |
287 | mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier, | |
288 | op_modifier, op, token); | |
289 | else | |
290 | err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier, | |
291 | op_modifier, op, token, event); | |
292 | ||
76d7cc03 RD |
293 | /* |
294 | * Make sure that our HCR writes don't get mixed in with | |
295 | * writes from another CPU starting a FW command. | |
296 | */ | |
297 | mmiowb(); | |
298 | ||
fd9cfdd1 | 299 | mutex_unlock(&dev->cmd.hcr_mutex); |
1da177e4 LT |
300 | return err; |
301 | } | |
302 | ||
303 | static int mthca_cmd_poll(struct mthca_dev *dev, | |
304 | u64 in_param, | |
305 | u64 *out_param, | |
306 | int out_is_imm, | |
307 | u32 in_modifier, | |
308 | u8 op_modifier, | |
309 | u16 op, | |
310 | unsigned long timeout, | |
311 | u8 *status) | |
312 | { | |
313 | int err = 0; | |
314 | unsigned long end; | |
315 | ||
e3aa31c5 | 316 | down(&dev->cmd.poll_sem); |
1da177e4 LT |
317 | |
318 | err = mthca_cmd_post(dev, in_param, | |
319 | out_param ? *out_param : 0, | |
320 | in_modifier, op_modifier, | |
321 | op, CMD_POLL_TOKEN, 0); | |
322 | if (err) | |
323 | goto out; | |
324 | ||
325 | end = timeout + jiffies; | |
326 | while (go_bit(dev) && time_before(jiffies, end)) { | |
327 | set_current_state(TASK_RUNNING); | |
328 | schedule(); | |
329 | } | |
330 | ||
331 | if (go_bit(dev)) { | |
332 | err = -EBUSY; | |
333 | goto out; | |
334 | } | |
335 | ||
97f52eb4 | 336 | if (out_is_imm) |
2fa5e2eb | 337 | *out_param = |
97f52eb4 SH |
338 | (u64) be32_to_cpu((__force __be32) |
339 | __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | | |
340 | (u64) be32_to_cpu((__force __be32) | |
341 | __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); | |
1da177e4 | 342 | |
97f52eb4 | 343 | *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; |
1da177e4 LT |
344 | |
345 | out: | |
346 | up(&dev->cmd.poll_sem); | |
347 | return err; | |
348 | } | |
349 | ||
350 | void mthca_cmd_event(struct mthca_dev *dev, | |
351 | u16 token, | |
352 | u8 status, | |
353 | u64 out_param) | |
354 | { | |
355 | struct mthca_cmd_context *context = | |
356 | &dev->cmd.context[token & dev->cmd.token_mask]; | |
357 | ||
358 | /* previously timed out command completing at long last */ | |
359 | if (token != context->token) | |
360 | return; | |
361 | ||
362 | context->result = 0; | |
363 | context->status = status; | |
364 | context->out_param = out_param; | |
365 | ||
1da177e4 LT |
366 | complete(&context->done); |
367 | } | |
368 | ||
1da177e4 LT |
369 | static int mthca_cmd_wait(struct mthca_dev *dev, |
370 | u64 in_param, | |
371 | u64 *out_param, | |
372 | int out_is_imm, | |
373 | u32 in_modifier, | |
374 | u8 op_modifier, | |
375 | u16 op, | |
376 | unsigned long timeout, | |
377 | u8 *status) | |
378 | { | |
379 | int err = 0; | |
380 | struct mthca_cmd_context *context; | |
381 | ||
e3aa31c5 | 382 | down(&dev->cmd.event_sem); |
1da177e4 LT |
383 | |
384 | spin_lock(&dev->cmd.context_lock); | |
385 | BUG_ON(dev->cmd.free_head < 0); | |
386 | context = &dev->cmd.context[dev->cmd.free_head]; | |
c1f74958 | 387 | context->token += dev->cmd.token_mask + 1; |
1da177e4 LT |
388 | dev->cmd.free_head = context->next; |
389 | spin_unlock(&dev->cmd.context_lock); | |
390 | ||
391 | init_completion(&context->done); | |
392 | ||
393 | err = mthca_cmd_post(dev, in_param, | |
394 | out_param ? *out_param : 0, | |
395 | in_modifier, op_modifier, | |
396 | op, context->token, 1); | |
397 | if (err) | |
398 | goto out; | |
399 | ||
e9cd5941 RD |
400 | if (!wait_for_completion_timeout(&context->done, timeout)) { |
401 | err = -EBUSY; | |
402 | goto out; | |
403 | } | |
1da177e4 LT |
404 | |
405 | err = context->result; | |
406 | if (err) | |
407 | goto out; | |
408 | ||
409 | *status = context->status; | |
410 | if (*status) | |
411 | mthca_dbg(dev, "Command %02x completed with status %02x\n", | |
412 | op, *status); | |
413 | ||
414 | if (out_is_imm) | |
415 | *out_param = context->out_param; | |
416 | ||
417 | out: | |
418 | spin_lock(&dev->cmd.context_lock); | |
419 | context->next = dev->cmd.free_head; | |
420 | dev->cmd.free_head = context - dev->cmd.context; | |
421 | spin_unlock(&dev->cmd.context_lock); | |
422 | ||
423 | up(&dev->cmd.event_sem); | |
424 | return err; | |
425 | } | |
426 | ||
427 | /* Invoke a command with an output mailbox */ | |
428 | static int mthca_cmd_box(struct mthca_dev *dev, | |
429 | u64 in_param, | |
430 | u64 out_param, | |
431 | u32 in_modifier, | |
432 | u8 op_modifier, | |
433 | u16 op, | |
434 | unsigned long timeout, | |
435 | u8 *status) | |
436 | { | |
14abdffc | 437 | if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) |
1da177e4 LT |
438 | return mthca_cmd_wait(dev, in_param, &out_param, 0, |
439 | in_modifier, op_modifier, op, | |
440 | timeout, status); | |
441 | else | |
442 | return mthca_cmd_poll(dev, in_param, &out_param, 0, | |
443 | in_modifier, op_modifier, op, | |
444 | timeout, status); | |
445 | } | |
446 | ||
447 | /* Invoke a command with no output parameter */ | |
448 | static int mthca_cmd(struct mthca_dev *dev, | |
449 | u64 in_param, | |
450 | u32 in_modifier, | |
451 | u8 op_modifier, | |
452 | u16 op, | |
453 | unsigned long timeout, | |
454 | u8 *status) | |
455 | { | |
456 | return mthca_cmd_box(dev, in_param, 0, in_modifier, | |
457 | op_modifier, op, timeout, status); | |
458 | } | |
459 | ||
460 | /* | |
461 | * Invoke a command with an immediate output parameter (and copy the | |
462 | * output into the caller's out_param pointer after the command | |
463 | * executes). | |
464 | */ | |
465 | static int mthca_cmd_imm(struct mthca_dev *dev, | |
466 | u64 in_param, | |
467 | u64 *out_param, | |
468 | u32 in_modifier, | |
469 | u8 op_modifier, | |
470 | u16 op, | |
471 | unsigned long timeout, | |
472 | u8 *status) | |
473 | { | |
14abdffc | 474 | if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) |
1da177e4 LT |
475 | return mthca_cmd_wait(dev, in_param, out_param, 1, |
476 | in_modifier, op_modifier, op, | |
477 | timeout, status); | |
478 | else | |
479 | return mthca_cmd_poll(dev, in_param, out_param, 1, | |
480 | in_modifier, op_modifier, op, | |
481 | timeout, status); | |
482 | } | |
483 | ||
80fd8238 RD |
484 | int mthca_cmd_init(struct mthca_dev *dev) |
485 | { | |
fd9cfdd1 | 486 | mutex_init(&dev->cmd.hcr_mutex); |
80fd8238 | 487 | sema_init(&dev->cmd.poll_sem, 1); |
14abdffc | 488 | dev->cmd.flags = 0; |
80fd8238 RD |
489 | |
490 | dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, | |
491 | MTHCA_HCR_SIZE); | |
492 | if (!dev->hcr) { | |
493 | mthca_err(dev, "Couldn't map command register."); | |
494 | return -ENOMEM; | |
495 | } | |
496 | ||
ed878458 RD |
497 | dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev, |
498 | MTHCA_MAILBOX_SIZE, | |
499 | MTHCA_MAILBOX_SIZE, 0); | |
500 | if (!dev->cmd.pool) { | |
501 | iounmap(dev->hcr); | |
502 | return -ENOMEM; | |
503 | } | |
504 | ||
80fd8238 RD |
505 | return 0; |
506 | } | |
507 | ||
508 | void mthca_cmd_cleanup(struct mthca_dev *dev) | |
509 | { | |
ed878458 | 510 | pci_pool_destroy(dev->cmd.pool); |
80fd8238 | 511 | iounmap(dev->hcr); |
14abdffc EC |
512 | if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS) |
513 | iounmap(dev->cmd.dbell_map); | |
80fd8238 RD |
514 | } |
515 | ||
1da177e4 LT |
516 | /* |
517 | * Switch to using events to issue FW commands (should be called after | |
518 | * event queue to command events has been initialized). | |
519 | */ | |
520 | int mthca_cmd_use_events(struct mthca_dev *dev) | |
521 | { | |
522 | int i; | |
523 | ||
524 | dev->cmd.context = kmalloc(dev->cmd.max_cmds * | |
525 | sizeof (struct mthca_cmd_context), | |
526 | GFP_KERNEL); | |
527 | if (!dev->cmd.context) | |
528 | return -ENOMEM; | |
529 | ||
530 | for (i = 0; i < dev->cmd.max_cmds; ++i) { | |
531 | dev->cmd.context[i].token = i; | |
532 | dev->cmd.context[i].next = i + 1; | |
1da177e4 LT |
533 | } |
534 | ||
535 | dev->cmd.context[dev->cmd.max_cmds - 1].next = -1; | |
536 | dev->cmd.free_head = 0; | |
537 | ||
538 | sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds); | |
539 | spin_lock_init(&dev->cmd.context_lock); | |
540 | ||
541 | for (dev->cmd.token_mask = 1; | |
542 | dev->cmd.token_mask < dev->cmd.max_cmds; | |
543 | dev->cmd.token_mask <<= 1) | |
544 | ; /* nothing */ | |
545 | --dev->cmd.token_mask; | |
546 | ||
14abdffc EC |
547 | dev->cmd.flags |= MTHCA_CMD_USE_EVENTS; |
548 | ||
1da177e4 LT |
549 | down(&dev->cmd.poll_sem); |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | /* | |
555 | * Switch back to polling (used when shutting down the device) | |
556 | */ | |
557 | void mthca_cmd_use_polling(struct mthca_dev *dev) | |
558 | { | |
559 | int i; | |
560 | ||
14abdffc | 561 | dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS; |
1da177e4 LT |
562 | |
563 | for (i = 0; i < dev->cmd.max_cmds; ++i) | |
564 | down(&dev->cmd.event_sem); | |
565 | ||
566 | kfree(dev->cmd.context); | |
567 | ||
568 | up(&dev->cmd.poll_sem); | |
569 | } | |
570 | ||
ed878458 | 571 | struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, |
87b750dc | 572 | gfp_t gfp_mask) |
ed878458 RD |
573 | { |
574 | struct mthca_mailbox *mailbox; | |
575 | ||
576 | mailbox = kmalloc(sizeof *mailbox, gfp_mask); | |
577 | if (!mailbox) | |
578 | return ERR_PTR(-ENOMEM); | |
579 | ||
580 | mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); | |
581 | if (!mailbox->buf) { | |
582 | kfree(mailbox); | |
583 | return ERR_PTR(-ENOMEM); | |
584 | } | |
585 | ||
586 | return mailbox; | |
587 | } | |
588 | ||
589 | void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) | |
590 | { | |
591 | if (!mailbox) | |
592 | return; | |
593 | ||
594 | pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); | |
595 | kfree(mailbox); | |
596 | } | |
597 | ||
1da177e4 LT |
598 | int mthca_SYS_EN(struct mthca_dev *dev, u8 *status) |
599 | { | |
600 | u64 out; | |
601 | int ret; | |
602 | ||
603 | ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status); | |
604 | ||
605 | if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR) | |
606 | mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, " | |
607 | "sladdr=%d, SPD source=%s\n", | |
608 | (int) (out >> 6) & 0xf, (int) (out >> 4) & 3, | |
609 | (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM"); | |
610 | ||
611 | return ret; | |
612 | } | |
613 | ||
614 | int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status) | |
615 | { | |
616 | return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status); | |
617 | } | |
618 | ||
619 | static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm, | |
620 | u64 virt, u8 *status) | |
621 | { | |
ed878458 | 622 | struct mthca_mailbox *mailbox; |
1da177e4 | 623 | struct mthca_icm_iter iter; |
ed878458 | 624 | __be64 *pages; |
1da177e4 LT |
625 | int lg; |
626 | int nent = 0; | |
627 | int i; | |
628 | int err = 0; | |
629 | int ts = 0, tc = 0; | |
630 | ||
ed878458 RD |
631 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
632 | if (IS_ERR(mailbox)) | |
633 | return PTR_ERR(mailbox); | |
634 | memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE); | |
635 | pages = mailbox->buf; | |
1da177e4 LT |
636 | |
637 | for (mthca_icm_first(icm, &iter); | |
638 | !mthca_icm_last(&iter); | |
639 | mthca_icm_next(&iter)) { | |
640 | /* | |
641 | * We have to pass pages that are aligned to their | |
642 | * size, so find the least significant 1 in the | |
643 | * address or size and use that as our log2 size. | |
644 | */ | |
645 | lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1; | |
8d3ef29d IR |
646 | if (lg < MTHCA_ICM_PAGE_SHIFT) { |
647 | mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", | |
648 | MTHCA_ICM_PAGE_SIZE, | |
1da177e4 LT |
649 | (unsigned long long) mthca_icm_addr(&iter), |
650 | mthca_icm_size(&iter)); | |
651 | err = -EINVAL; | |
652 | goto out; | |
653 | } | |
59f174fa | 654 | for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) { |
1da177e4 | 655 | if (virt != -1) { |
ed878458 | 656 | pages[nent * 2] = cpu_to_be64(virt); |
1da177e4 LT |
657 | virt += 1 << lg; |
658 | } | |
659 | ||
8d3ef29d IR |
660 | pages[nent * 2 + 1] = |
661 | cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) | | |
662 | (lg - MTHCA_ICM_PAGE_SHIFT)); | |
1da177e4 LT |
663 | ts += 1 << (lg - 10); |
664 | ++tc; | |
665 | ||
44dd823b | 666 | if (++nent == MTHCA_MAILBOX_SIZE / 16) { |
ed878458 | 667 | err = mthca_cmd(dev, mailbox->dma, nent, 0, op, |
1da177e4 LT |
668 | CMD_TIME_CLASS_B, status); |
669 | if (err || *status) | |
670 | goto out; | |
671 | nent = 0; | |
672 | } | |
673 | } | |
674 | } | |
675 | ||
676 | if (nent) | |
ed878458 | 677 | err = mthca_cmd(dev, mailbox->dma, nent, 0, op, |
1da177e4 LT |
678 | CMD_TIME_CLASS_B, status); |
679 | ||
680 | switch (op) { | |
681 | case CMD_MAP_FA: | |
682 | mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
683 | break; | |
684 | case CMD_MAP_ICM_AUX: | |
685 | mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
686 | break; | |
687 | case CMD_MAP_ICM: | |
688 | mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
689 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
690 | break; | |
691 | } | |
692 | ||
693 | out: | |
ed878458 | 694 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
695 | return err; |
696 | } | |
697 | ||
698 | int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) | |
699 | { | |
700 | return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status); | |
701 | } | |
702 | ||
703 | int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status) | |
704 | { | |
705 | return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status); | |
706 | } | |
707 | ||
708 | int mthca_RUN_FW(struct mthca_dev *dev, u8 *status) | |
709 | { | |
710 | return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status); | |
711 | } | |
712 | ||
14abdffc EC |
713 | static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base) |
714 | { | |
715 | unsigned long addr; | |
716 | u16 max_off = 0; | |
717 | int i; | |
718 | ||
719 | for (i = 0; i < 8; ++i) | |
720 | max_off = max(max_off, dev->cmd.dbell_offsets[i]); | |
721 | ||
722 | if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) { | |
723 | mthca_warn(dev, "Firmware doorbell region at 0x%016llx, " | |
724 | "length 0x%x crosses a page boundary\n", | |
725 | (unsigned long long) base, max_off); | |
726 | return; | |
727 | } | |
728 | ||
729 | addr = pci_resource_start(dev->pdev, 2) + | |
730 | ((pci_resource_len(dev->pdev, 2) - 1) & base); | |
731 | dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32)); | |
732 | if (!dev->cmd.dbell_map) | |
733 | return; | |
734 | ||
735 | dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS; | |
736 | mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n"); | |
737 | } | |
738 | ||
1da177e4 LT |
739 | int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status) |
740 | { | |
ed878458 | 741 | struct mthca_mailbox *mailbox; |
1da177e4 | 742 | u32 *outbox; |
14abdffc EC |
743 | u64 base; |
744 | u32 tmp; | |
1da177e4 LT |
745 | int err = 0; |
746 | u8 lg; | |
14abdffc | 747 | int i; |
1da177e4 LT |
748 | |
749 | #define QUERY_FW_OUT_SIZE 0x100 | |
750 | #define QUERY_FW_VER_OFFSET 0x00 | |
751 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f | |
752 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
753 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
754 | ||
14abdffc EC |
755 | #define QUERY_FW_CMD_DB_EN_OFFSET 0x10 |
756 | #define QUERY_FW_CMD_DB_OFFSET 0x50 | |
757 | #define QUERY_FW_CMD_DB_BASE 0x60 | |
758 | ||
1da177e4 LT |
759 | #define QUERY_FW_START_OFFSET 0x20 |
760 | #define QUERY_FW_END_OFFSET 0x28 | |
761 | ||
762 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
763 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
764 | #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40 | |
765 | #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48 | |
766 | ||
ed878458 RD |
767 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
768 | if (IS_ERR(mailbox)) | |
769 | return PTR_ERR(mailbox); | |
770 | outbox = mailbox->buf; | |
1da177e4 | 771 | |
ed878458 | 772 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW, |
1da177e4 LT |
773 | CMD_TIME_CLASS_A, status); |
774 | ||
775 | if (err) | |
776 | goto out; | |
777 | ||
778 | MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
779 | /* | |
3e1db334 | 780 | * FW subminor version is at more significant bits than minor |
1da177e4 LT |
781 | * version, so swap here. |
782 | */ | |
783 | dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) | | |
784 | ((dev->fw_ver & 0xffff0000ull) >> 16) | | |
785 | ((dev->fw_ver & 0x0000ffffull) << 16); | |
786 | ||
8fdf679f RD |
787 | MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
788 | dev->cmd.max_cmds = 1 << lg; | |
789 | ||
14abdffc EC |
790 | mthca_dbg(dev, "FW version %012llx, max commands %d\n", |
791 | (unsigned long long) dev->fw_ver, dev->cmd.max_cmds); | |
792 | ||
3d155f8c RD |
793 | MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET); |
794 | MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
1da177e4 | 795 | |
3d155f8c RD |
796 | mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n", |
797 | (unsigned long long) dev->catas_err.addr, dev->catas_err.size); | |
1da177e4 | 798 | |
14abdffc EC |
799 | MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET); |
800 | if (tmp & 0x1) { | |
801 | mthca_dbg(dev, "FW supports commands through doorbells\n"); | |
802 | ||
803 | MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE); | |
804 | for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i) | |
805 | MTHCA_GET(dev->cmd.dbell_offsets[i], outbox, | |
806 | QUERY_FW_CMD_DB_OFFSET + (i << 1)); | |
807 | ||
808 | mthca_setup_cmd_doorbells(dev, base); | |
809 | } | |
810 | ||
d10ddbf6 | 811 | if (mthca_is_memfree(dev)) { |
1da177e4 LT |
812 | MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
813 | MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
814 | MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET); | |
815 | MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET); | |
816 | mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2); | |
817 | ||
818 | /* | |
8d3ef29d IR |
819 | * Round up number of system pages needed in case |
820 | * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. | |
1da177e4 LT |
821 | */ |
822 | dev->fw.arbel.fw_pages = | |
8d3ef29d IR |
823 | ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> |
824 | (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); | |
1da177e4 LT |
825 | |
826 | mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n", | |
827 | (unsigned long long) dev->fw.arbel.clr_int_base, | |
828 | (unsigned long long) dev->fw.arbel.eq_arm_base, | |
829 | (unsigned long long) dev->fw.arbel.eq_set_ci_base); | |
830 | } else { | |
831 | MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET); | |
832 | MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET); | |
833 | ||
834 | mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n", | |
835 | (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10), | |
836 | (unsigned long long) dev->fw.tavor.fw_start, | |
837 | (unsigned long long) dev->fw.tavor.fw_end); | |
838 | } | |
839 | ||
840 | out: | |
ed878458 | 841 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
842 | return err; |
843 | } | |
844 | ||
845 | int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status) | |
846 | { | |
ed878458 | 847 | struct mthca_mailbox *mailbox; |
1da177e4 LT |
848 | u8 info; |
849 | u32 *outbox; | |
1da177e4 LT |
850 | int err = 0; |
851 | ||
852 | #define ENABLE_LAM_OUT_SIZE 0x100 | |
853 | #define ENABLE_LAM_START_OFFSET 0x00 | |
854 | #define ENABLE_LAM_END_OFFSET 0x08 | |
855 | #define ENABLE_LAM_INFO_OFFSET 0x13 | |
856 | ||
857 | #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4) | |
858 | #define ENABLE_LAM_INFO_ECC_MASK 0x3 | |
859 | ||
ed878458 RD |
860 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
861 | if (IS_ERR(mailbox)) | |
862 | return PTR_ERR(mailbox); | |
863 | outbox = mailbox->buf; | |
1da177e4 | 864 | |
ed878458 | 865 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM, |
1da177e4 LT |
866 | CMD_TIME_CLASS_C, status); |
867 | ||
868 | if (err) | |
869 | goto out; | |
870 | ||
871 | if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE) | |
872 | goto out; | |
873 | ||
874 | MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET); | |
875 | MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET); | |
876 | MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET); | |
877 | ||
878 | if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) != | |
879 | !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { | |
880 | mthca_info(dev, "FW reports that HCA-attached memory " | |
881 | "is %s hidden; does not match PCI config\n", | |
882 | (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ? | |
883 | "" : "not"); | |
884 | } | |
885 | if (info & ENABLE_LAM_INFO_HIDDEN_FLAG) | |
886 | mthca_dbg(dev, "HCA-attached memory is hidden.\n"); | |
887 | ||
888 | mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", | |
889 | (int) ((dev->ddr_end - dev->ddr_start) >> 10), | |
890 | (unsigned long long) dev->ddr_start, | |
891 | (unsigned long long) dev->ddr_end); | |
892 | ||
893 | out: | |
ed878458 | 894 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
895 | return err; |
896 | } | |
897 | ||
898 | int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status) | |
899 | { | |
900 | return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status); | |
901 | } | |
902 | ||
903 | int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status) | |
904 | { | |
ed878458 | 905 | struct mthca_mailbox *mailbox; |
1da177e4 LT |
906 | u8 info; |
907 | u32 *outbox; | |
1da177e4 LT |
908 | int err = 0; |
909 | ||
910 | #define QUERY_DDR_OUT_SIZE 0x100 | |
911 | #define QUERY_DDR_START_OFFSET 0x00 | |
912 | #define QUERY_DDR_END_OFFSET 0x08 | |
913 | #define QUERY_DDR_INFO_OFFSET 0x13 | |
914 | ||
915 | #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4) | |
916 | #define QUERY_DDR_INFO_ECC_MASK 0x3 | |
917 | ||
ed878458 RD |
918 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
919 | if (IS_ERR(mailbox)) | |
920 | return PTR_ERR(mailbox); | |
921 | outbox = mailbox->buf; | |
1da177e4 | 922 | |
ed878458 | 923 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR, |
1da177e4 LT |
924 | CMD_TIME_CLASS_A, status); |
925 | ||
926 | if (err) | |
927 | goto out; | |
928 | ||
929 | MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET); | |
930 | MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET); | |
931 | MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET); | |
932 | ||
933 | if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) != | |
934 | !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { | |
935 | mthca_info(dev, "FW reports that HCA-attached memory " | |
936 | "is %s hidden; does not match PCI config\n", | |
937 | (info & QUERY_DDR_INFO_HIDDEN_FLAG) ? | |
938 | "" : "not"); | |
939 | } | |
940 | if (info & QUERY_DDR_INFO_HIDDEN_FLAG) | |
941 | mthca_dbg(dev, "HCA-attached memory is hidden.\n"); | |
942 | ||
943 | mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", | |
944 | (int) ((dev->ddr_end - dev->ddr_start) >> 10), | |
945 | (unsigned long long) dev->ddr_start, | |
946 | (unsigned long long) dev->ddr_end); | |
947 | ||
948 | out: | |
ed878458 | 949 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
950 | return err; |
951 | } | |
952 | ||
953 | int mthca_QUERY_DEV_LIM(struct mthca_dev *dev, | |
954 | struct mthca_dev_lim *dev_lim, u8 *status) | |
955 | { | |
ed878458 | 956 | struct mthca_mailbox *mailbox; |
1da177e4 | 957 | u32 *outbox; |
1da177e4 LT |
958 | u8 field; |
959 | u16 size; | |
bf6a9e31 | 960 | u16 stat_rate; |
1da177e4 LT |
961 | int err; |
962 | ||
963 | #define QUERY_DEV_LIM_OUT_SIZE 0x100 | |
964 | #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10 | |
965 | #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11 | |
966 | #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12 | |
967 | #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13 | |
968 | #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14 | |
969 | #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15 | |
970 | #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16 | |
971 | #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17 | |
972 | #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19 | |
973 | #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a | |
974 | #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b | |
975 | #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d | |
976 | #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e | |
977 | #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f | |
978 | #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20 | |
979 | #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21 | |
980 | #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22 | |
981 | #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23 | |
982 | #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27 | |
983 | #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29 | |
984 | #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b | |
985 | #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f | |
986 | #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33 | |
987 | #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35 | |
988 | #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36 | |
989 | #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37 | |
990 | #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b | |
bf6a9e31 | 991 | #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c |
1da177e4 LT |
992 | #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f |
993 | #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44 | |
994 | #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48 | |
995 | #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49 | |
996 | #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b | |
997 | #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51 | |
998 | #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52 | |
999 | #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55 | |
1000 | #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
1001 | #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61 | |
1002 | #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62 | |
1003 | #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63 | |
1004 | #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64 | |
1005 | #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65 | |
1006 | #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66 | |
1007 | #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67 | |
1008 | #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80 | |
1009 | #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82 | |
1010 | #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84 | |
1011 | #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86 | |
1012 | #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88 | |
1013 | #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a | |
1014 | #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c | |
1015 | #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e | |
1016 | #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90 | |
1017 | #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92 | |
1018 | #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96 | |
1019 | #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97 | |
1020 | #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98 | |
1021 | #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f | |
1022 | #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0 | |
1023 | ||
ed878458 RD |
1024 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1025 | if (IS_ERR(mailbox)) | |
1026 | return PTR_ERR(mailbox); | |
1027 | outbox = mailbox->buf; | |
1da177e4 | 1028 | |
ed878458 | 1029 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, |
1da177e4 LT |
1030 | CMD_TIME_CLASS_A, status); |
1031 | ||
1032 | if (err) | |
1033 | goto out; | |
1034 | ||
1da177e4 LT |
1035 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET); |
1036 | dev_lim->reserved_qps = 1 << (field & 0xf); | |
1037 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET); | |
1038 | dev_lim->max_qps = 1 << (field & 0x1f); | |
1039 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET); | |
1040 | dev_lim->reserved_srqs = 1 << (field >> 4); | |
1041 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET); | |
1042 | dev_lim->max_srqs = 1 << (field & 0x1f); | |
1043 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET); | |
1044 | dev_lim->reserved_eecs = 1 << (field & 0xf); | |
1045 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET); | |
1046 | dev_lim->max_eecs = 1 << (field & 0x1f); | |
1047 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET); | |
1048 | dev_lim->max_cq_sz = 1 << field; | |
1049 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET); | |
1050 | dev_lim->reserved_cqs = 1 << (field & 0xf); | |
1051 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET); | |
1052 | dev_lim->max_cqs = 1 << (field & 0x1f); | |
1053 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET); | |
1054 | dev_lim->max_mpts = 1 << (field & 0x3f); | |
1055 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET); | |
1056 | dev_lim->reserved_eqs = 1 << (field & 0xf); | |
1057 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET); | |
1058 | dev_lim->max_eqs = 1 << (field & 0x7); | |
1059 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); | |
c7d204e8 MT |
1060 | if (mthca_is_memfree(dev)) |
1061 | dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64), | |
1062 | MTHCA_MTT_SEG_SIZE) / MTHCA_MTT_SEG_SIZE; | |
1063 | else | |
1064 | dev_lim->reserved_mtts = 1 << (field >> 4); | |
1da177e4 LT |
1065 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); |
1066 | dev_lim->max_mrw_sz = 1 << field; | |
1067 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET); | |
1068 | dev_lim->reserved_mrws = 1 << (field & 0xf); | |
1069 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET); | |
1070 | dev_lim->max_mtt_seg = 1 << (field & 0x3f); | |
1071 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET); | |
1072 | dev_lim->max_requester_per_qp = 1 << (field & 0x3f); | |
1073 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET); | |
1074 | dev_lim->max_responder_per_qp = 1 << (field & 0x3f); | |
1075 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET); | |
1076 | dev_lim->max_rdma_global = 1 << (field & 0x3f); | |
1077 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET); | |
1078 | dev_lim->local_ca_ack_delay = field & 0x1f; | |
1079 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET); | |
1080 | dev_lim->max_mtu = field >> 4; | |
1081 | dev_lim->max_port_width = field & 0xf; | |
1082 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET); | |
1083 | dev_lim->max_vl = field >> 4; | |
1084 | dev_lim->num_ports = field & 0xf; | |
1085 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET); | |
1086 | dev_lim->max_gids = 1 << (field & 0xf); | |
bf6a9e31 JM |
1087 | MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET); |
1088 | dev_lim->stat_rate_support = stat_rate; | |
1da177e4 LT |
1089 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET); |
1090 | dev_lim->max_pkeys = 1 << (field & 0xf); | |
1091 | MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET); | |
1092 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET); | |
1093 | dev_lim->reserved_uars = field >> 4; | |
1094 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET); | |
1095 | dev_lim->uar_size = 1 << ((field & 0x3f) + 20); | |
1096 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET); | |
1097 | dev_lim->min_page_sz = 1 << field; | |
1098 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET); | |
1099 | dev_lim->max_sg = field; | |
1100 | ||
1101 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET); | |
1102 | dev_lim->max_desc_sz = size; | |
1103 | ||
1104 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET); | |
1105 | dev_lim->max_qp_per_mcg = 1 << field; | |
1106 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET); | |
1107 | dev_lim->reserved_mgms = field & 0xf; | |
1108 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET); | |
1109 | dev_lim->max_mcgs = 1 << field; | |
1110 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET); | |
1111 | dev_lim->reserved_pds = field >> 4; | |
1112 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET); | |
1113 | dev_lim->max_pds = 1 << (field & 0x3f); | |
1114 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET); | |
1115 | dev_lim->reserved_rdds = field >> 4; | |
1116 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET); | |
1117 | dev_lim->max_rdds = 1 << (field & 0x3f); | |
1118 | ||
1119 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET); | |
1120 | dev_lim->eec_entry_sz = size; | |
1121 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET); | |
1122 | dev_lim->qpc_entry_sz = size; | |
1123 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET); | |
1124 | dev_lim->eeec_entry_sz = size; | |
1125 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET); | |
1126 | dev_lim->eqpc_entry_sz = size; | |
1127 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET); | |
1128 | dev_lim->eqc_entry_sz = size; | |
1129 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET); | |
1130 | dev_lim->cqc_entry_sz = size; | |
1131 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET); | |
1132 | dev_lim->srq_entry_sz = size; | |
1133 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET); | |
1134 | dev_lim->uar_scratch_entry_sz = size; | |
1135 | ||
d10ddbf6 | 1136 | if (mthca_is_memfree(dev)) { |
a3c8ab4f JM |
1137 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); |
1138 | dev_lim->max_srq_sz = 1 << field; | |
1139 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); | |
1140 | dev_lim->max_qp_sz = 1 << field; | |
1da177e4 LT |
1141 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET); |
1142 | dev_lim->hca.arbel.resize_srq = field & 1; | |
8cf2daf3 RD |
1143 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET); |
1144 | dev_lim->max_sg = min_t(int, field, dev_lim->max_sg); | |
77369ed3 JM |
1145 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET); |
1146 | dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz); | |
1da177e4 LT |
1147 | MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET); |
1148 | dev_lim->mpt_entry_sz = size; | |
1149 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET); | |
1150 | dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f); | |
1151 | MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox, | |
1152 | QUERY_DEV_LIM_BMME_FLAGS_OFFSET); | |
1153 | MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox, | |
1154 | QUERY_DEV_LIM_RSVD_LKEY_OFFSET); | |
1155 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET); | |
1156 | dev_lim->hca.arbel.lam_required = field & 1; | |
1157 | MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox, | |
1158 | QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET); | |
1159 | ||
1160 | if (dev_lim->hca.arbel.bmme_flags & 1) | |
1161 | mthca_dbg(dev, "Base MM extensions: yes " | |
1162 | "(flags %d, max PBL %d, rsvd L_Key %08x)\n", | |
1163 | dev_lim->hca.arbel.bmme_flags, | |
1164 | dev_lim->hca.arbel.max_pbl_sz, | |
1165 | dev_lim->hca.arbel.reserved_lkey); | |
1166 | else | |
1167 | mthca_dbg(dev, "Base MM extensions: no\n"); | |
1168 | ||
1169 | mthca_dbg(dev, "Max ICM size %lld MB\n", | |
1170 | (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20); | |
1171 | } else { | |
a3c8ab4f JM |
1172 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); |
1173 | dev_lim->max_srq_sz = (1 << field) - 1; | |
1174 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); | |
1175 | dev_lim->max_qp_sz = (1 << field) - 1; | |
1da177e4 LT |
1176 | MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET); |
1177 | dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f); | |
1da177e4 LT |
1178 | dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE; |
1179 | } | |
1180 | ||
f295c79b RD |
1181 | mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", |
1182 | dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz); | |
1183 | mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", | |
1184 | dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz); | |
1185 | mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", | |
1186 | dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz); | |
1187 | mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
1188 | dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz); | |
1189 | mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
1190 | dev_lim->reserved_mrws, dev_lim->reserved_mtts); | |
1191 | mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
1192 | dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars); | |
1193 | mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
1194 | dev_lim->max_pds, dev_lim->reserved_mgms); | |
1195 | mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | |
1196 | dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz); | |
1197 | ||
1198 | mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags); | |
1199 | ||
1da177e4 | 1200 | out: |
ed878458 | 1201 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1202 | return err; |
1203 | } | |
1204 | ||
2e8b981c MT |
1205 | static void get_board_id(void *vsd, char *board_id) |
1206 | { | |
1207 | int i; | |
1208 | ||
1209 | #define VSD_OFFSET_SIG1 0x00 | |
1210 | #define VSD_OFFSET_SIG2 0xde | |
1211 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
1212 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
1213 | ||
1214 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
1215 | ||
1216 | memset(board_id, 0, MTHCA_BOARD_ID_LEN); | |
1217 | ||
1218 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
1219 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
1220 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN); | |
1221 | } else { | |
1222 | /* | |
1223 | * The board ID is a string but the firmware byte | |
1224 | * swaps each 4-byte word before passing it back to | |
1225 | * us. Therefore we need to swab it before printing. | |
1226 | */ | |
1227 | for (i = 0; i < 4; ++i) | |
1228 | ((u32 *) board_id)[i] = | |
1229 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
1230 | } | |
1231 | } | |
1232 | ||
1da177e4 LT |
1233 | int mthca_QUERY_ADAPTER(struct mthca_dev *dev, |
1234 | struct mthca_adapter *adapter, u8 *status) | |
1235 | { | |
ed878458 | 1236 | struct mthca_mailbox *mailbox; |
1da177e4 | 1237 | u32 *outbox; |
1da177e4 LT |
1238 | int err; |
1239 | ||
1240 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
1241 | #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 | |
1242 | #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 | |
1243 | #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 | |
1244 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 | |
2e8b981c | 1245 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
1da177e4 | 1246 | |
ed878458 RD |
1247 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1248 | if (IS_ERR(mailbox)) | |
1249 | return PTR_ERR(mailbox); | |
1250 | outbox = mailbox->buf; | |
1da177e4 | 1251 | |
ed878458 | 1252 | err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, |
1da177e4 LT |
1253 | CMD_TIME_CLASS_A, status); |
1254 | ||
1255 | if (err) | |
1256 | goto out; | |
1257 | ||
6ccef1de JM |
1258 | if (!mthca_is_memfree(dev)) { |
1259 | MTHCA_GET(adapter->vendor_id, outbox, | |
1260 | QUERY_ADAPTER_VENDOR_ID_OFFSET); | |
1261 | MTHCA_GET(adapter->device_id, outbox, | |
1262 | QUERY_ADAPTER_DEVICE_ID_OFFSET); | |
1263 | MTHCA_GET(adapter->revision_id, outbox, | |
1264 | QUERY_ADAPTER_REVISION_ID_OFFSET); | |
1265 | } | |
ed878458 | 1266 | MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
1da177e4 | 1267 | |
2e8b981c MT |
1268 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
1269 | adapter->board_id); | |
1270 | ||
1da177e4 | 1271 | out: |
ed878458 | 1272 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1273 | return err; |
1274 | } | |
1275 | ||
1276 | int mthca_INIT_HCA(struct mthca_dev *dev, | |
1277 | struct mthca_init_hca_param *param, | |
1278 | u8 *status) | |
1279 | { | |
ed878458 | 1280 | struct mthca_mailbox *mailbox; |
97f52eb4 | 1281 | __be32 *inbox; |
1da177e4 LT |
1282 | int err; |
1283 | ||
1284 | #define INIT_HCA_IN_SIZE 0x200 | |
651eaac9 EC |
1285 | #define INIT_HCA_FLAGS1_OFFSET 0x00c |
1286 | #define INIT_HCA_FLAGS2_OFFSET 0x014 | |
1da177e4 LT |
1287 | #define INIT_HCA_QPC_OFFSET 0x020 |
1288 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
1289 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
1290 | #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20) | |
1291 | #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27) | |
1292 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
1293 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
1294 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
1295 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
1296 | #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) | |
1297 | #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
1298 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
1299 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
1300 | #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
1301 | #define INIT_HCA_UDAV_OFFSET 0x0b0 | |
1302 | #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0) | |
1303 | #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4) | |
1304 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
1305 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
1306 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
1307 | #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
1308 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) | |
1309 | #define INIT_HCA_TPT_OFFSET 0x0f0 | |
1310 | #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
1311 | #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09) | |
1312 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) | |
1313 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
1314 | #define INIT_HCA_UAR_OFFSET 0x120 | |
1315 | #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00) | |
1316 | #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09) | |
1317 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
1318 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
1319 | #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10) | |
1320 | #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18) | |
1321 | ||
ed878458 RD |
1322 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1323 | if (IS_ERR(mailbox)) | |
1324 | return PTR_ERR(mailbox); | |
1325 | inbox = mailbox->buf; | |
1da177e4 LT |
1326 | |
1327 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
1328 | ||
651eaac9 EC |
1329 | if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT) |
1330 | MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET); | |
1331 | ||
1da177e4 | 1332 | #if defined(__LITTLE_ENDIAN) |
651eaac9 | 1333 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1); |
1da177e4 | 1334 | #elif defined(__BIG_ENDIAN) |
651eaac9 | 1335 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1); |
1da177e4 LT |
1336 | #else |
1337 | #error Host endianness not defined | |
1338 | #endif | |
1339 | /* Check port for UD address vector: */ | |
651eaac9 | 1340 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1); |
1da177e4 | 1341 | |
680b575f EC |
1342 | /* Enable IPoIB checksumming if we can: */ |
1343 | if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM) | |
1344 | *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3); | |
1345 | ||
1da177e4 LT |
1346 | /* We leave wqe_quota, responder_exu, etc as 0 (default) */ |
1347 | ||
1348 | /* QPC/EEC/CQC/EQC/RDB attributes */ | |
1349 | ||
1350 | MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
1351 | MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
1352 | MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET); | |
1353 | MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET); | |
1354 | MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
1355 | MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
1356 | MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
1357 | MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
1358 | MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET); | |
1359 | MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET); | |
1360 | MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
1361 | MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
1362 | MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET); | |
1363 | ||
1364 | /* UD AV attributes */ | |
1365 | ||
1366 | /* multicast attributes */ | |
1367 | ||
1368 | MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
1369 | MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1370 | MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET); | |
1371 | MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1372 | ||
1373 | /* TPT attributes */ | |
1374 | ||
1375 | MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET); | |
d10ddbf6 | 1376 | if (!mthca_is_memfree(dev)) |
1da177e4 LT |
1377 | MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET); |
1378 | MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
1379 | MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
1380 | ||
1381 | /* UAR attributes */ | |
1382 | { | |
1383 | u8 uar_page_sz = PAGE_SHIFT - 12; | |
1384 | MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
1385 | } | |
1386 | ||
1387 | MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET); | |
1388 | ||
d10ddbf6 | 1389 | if (mthca_is_memfree(dev)) { |
1da177e4 LT |
1390 | MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET); |
1391 | MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
1392 | MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET); | |
1393 | } | |
1394 | ||
ed878458 | 1395 | err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status); |
1da177e4 | 1396 | |
ed878458 | 1397 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1398 | return err; |
1399 | } | |
1400 | ||
1401 | int mthca_INIT_IB(struct mthca_dev *dev, | |
1402 | struct mthca_init_ib_param *param, | |
1403 | int port, u8 *status) | |
1404 | { | |
ed878458 | 1405 | struct mthca_mailbox *mailbox; |
1da177e4 | 1406 | u32 *inbox; |
1da177e4 LT |
1407 | int err; |
1408 | u32 flags; | |
1409 | ||
1410 | #define INIT_IB_IN_SIZE 56 | |
1411 | #define INIT_IB_FLAGS_OFFSET 0x00 | |
1412 | #define INIT_IB_FLAG_SIG (1 << 18) | |
1413 | #define INIT_IB_FLAG_NG (1 << 17) | |
1414 | #define INIT_IB_FLAG_G0 (1 << 16) | |
1da177e4 | 1415 | #define INIT_IB_VL_SHIFT 4 |
da6561c2 | 1416 | #define INIT_IB_PORT_WIDTH_SHIFT 8 |
1da177e4 LT |
1417 | #define INIT_IB_MTU_SHIFT 12 |
1418 | #define INIT_IB_MAX_GID_OFFSET 0x06 | |
1419 | #define INIT_IB_MAX_PKEY_OFFSET 0x0a | |
1420 | #define INIT_IB_GUID0_OFFSET 0x10 | |
1421 | #define INIT_IB_NODE_GUID_OFFSET 0x18 | |
1422 | #define INIT_IB_SI_GUID_OFFSET 0x20 | |
1423 | ||
ed878458 RD |
1424 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1425 | if (IS_ERR(mailbox)) | |
1426 | return PTR_ERR(mailbox); | |
1427 | inbox = mailbox->buf; | |
1da177e4 LT |
1428 | |
1429 | memset(inbox, 0, INIT_IB_IN_SIZE); | |
1430 | ||
1431 | flags = 0; | |
1da177e4 LT |
1432 | flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; |
1433 | flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; | |
1434 | flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; | |
1435 | flags |= param->vl_cap << INIT_IB_VL_SHIFT; | |
da6561c2 | 1436 | flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT; |
1da177e4 LT |
1437 | flags |= param->mtu_cap << INIT_IB_MTU_SHIFT; |
1438 | MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET); | |
1439 | ||
1440 | MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET); | |
1441 | MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET); | |
1442 | MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET); | |
1443 | MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET); | |
1444 | MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET); | |
1445 | ||
ed878458 | 1446 | err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, |
1da177e4 LT |
1447 | CMD_TIME_CLASS_A, status); |
1448 | ||
ed878458 | 1449 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1450 | return err; |
1451 | } | |
1452 | ||
1453 | int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status) | |
1454 | { | |
1455 | return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status); | |
1456 | } | |
1457 | ||
1458 | int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status) | |
1459 | { | |
1460 | return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status); | |
1461 | } | |
1462 | ||
1463 | int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, | |
1464 | int port, u8 *status) | |
1465 | { | |
ed878458 | 1466 | struct mthca_mailbox *mailbox; |
1da177e4 | 1467 | u32 *inbox; |
1da177e4 LT |
1468 | int err; |
1469 | u32 flags = 0; | |
1470 | ||
1471 | #define SET_IB_IN_SIZE 0x40 | |
1472 | #define SET_IB_FLAGS_OFFSET 0x00 | |
1473 | #define SET_IB_FLAG_SIG (1 << 18) | |
1474 | #define SET_IB_FLAG_RQK (1 << 0) | |
1475 | #define SET_IB_CAP_MASK_OFFSET 0x04 | |
1476 | #define SET_IB_SI_GUID_OFFSET 0x08 | |
1477 | ||
ed878458 RD |
1478 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1479 | if (IS_ERR(mailbox)) | |
1480 | return PTR_ERR(mailbox); | |
1481 | inbox = mailbox->buf; | |
1da177e4 LT |
1482 | |
1483 | memset(inbox, 0, SET_IB_IN_SIZE); | |
1484 | ||
1485 | flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; | |
1486 | flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; | |
1487 | MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET); | |
1488 | ||
1489 | MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET); | |
1490 | MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET); | |
1491 | ||
ed878458 | 1492 | err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, |
1da177e4 LT |
1493 | CMD_TIME_CLASS_B, status); |
1494 | ||
ed878458 | 1495 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1496 | return err; |
1497 | } | |
1498 | ||
1499 | int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status) | |
1500 | { | |
1501 | return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status); | |
1502 | } | |
1503 | ||
1504 | int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status) | |
1505 | { | |
ed878458 | 1506 | struct mthca_mailbox *mailbox; |
97f52eb4 | 1507 | __be64 *inbox; |
1da177e4 LT |
1508 | int err; |
1509 | ||
ed878458 RD |
1510 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1511 | if (IS_ERR(mailbox)) | |
1512 | return PTR_ERR(mailbox); | |
1513 | inbox = mailbox->buf; | |
1da177e4 LT |
1514 | |
1515 | inbox[0] = cpu_to_be64(virt); | |
1516 | inbox[1] = cpu_to_be64(dma_addr); | |
1517 | ||
ed878458 RD |
1518 | err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM, |
1519 | CMD_TIME_CLASS_B, status); | |
1da177e4 | 1520 | |
ed878458 | 1521 | mthca_free_mailbox(dev, mailbox); |
1da177e4 LT |
1522 | |
1523 | if (!err) | |
6bd6228e RD |
1524 | mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n", |
1525 | (unsigned long long) dma_addr, (unsigned long long) virt); | |
1da177e4 LT |
1526 | |
1527 | return err; | |
1528 | } | |
1529 | ||
1530 | int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status) | |
1531 | { | |
1532 | mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n", | |
1533 | page_count, (unsigned long long) virt); | |
1534 | ||
1535 | return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status); | |
1536 | } | |
1537 | ||
1538 | int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) | |
1539 | { | |
1540 | return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status); | |
1541 | } | |
1542 | ||
1543 | int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status) | |
1544 | { | |
1545 | return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status); | |
1546 | } | |
1547 | ||
1548 | int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages, | |
1549 | u8 *status) | |
1550 | { | |
1551 | int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE, | |
1552 | CMD_TIME_CLASS_A, status); | |
1553 | ||
1554 | if (ret || status) | |
1555 | return ret; | |
1556 | ||
1557 | /* | |
8d3ef29d IR |
1558 | * Round up number of system pages needed in case |
1559 | * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. | |
1da177e4 | 1560 | */ |
8d3ef29d IR |
1561 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> |
1562 | (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); | |
1da177e4 LT |
1563 | |
1564 | return 0; | |
1565 | } | |
1566 | ||
ed878458 | 1567 | int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1568 | int mpt_index, u8 *status) |
1569 | { | |
ed878458 RD |
1570 | return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, |
1571 | CMD_TIME_CLASS_B, status); | |
1da177e4 LT |
1572 | } |
1573 | ||
ed878458 | 1574 | int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1575 | int mpt_index, u8 *status) |
1576 | { | |
ed878458 RD |
1577 | return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, |
1578 | !mailbox, CMD_HW2SW_MPT, | |
1579 | CMD_TIME_CLASS_B, status); | |
1da177e4 LT |
1580 | } |
1581 | ||
ed878458 | 1582 | int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1583 | int num_mtt, u8 *status) |
1584 | { | |
ed878458 RD |
1585 | return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, |
1586 | CMD_TIME_CLASS_B, status); | |
1da177e4 LT |
1587 | } |
1588 | ||
b8ca06f6 MT |
1589 | int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status) |
1590 | { | |
1591 | return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status); | |
1592 | } | |
1593 | ||
1da177e4 LT |
1594 | int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, |
1595 | int eq_num, u8 *status) | |
1596 | { | |
1597 | mthca_dbg(dev, "%s mask %016llx for eqn %d\n", | |
1598 | unmap ? "Clearing" : "Setting", | |
1599 | (unsigned long long) event_mask, eq_num); | |
1600 | return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num, | |
1601 | 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status); | |
1602 | } | |
1603 | ||
ed878458 | 1604 | int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1605 | int eq_num, u8 *status) |
1606 | { | |
ed878458 RD |
1607 | return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, |
1608 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1609 | } |
1610 | ||
ed878458 | 1611 | int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1612 | int eq_num, u8 *status) |
1613 | { | |
ed878458 RD |
1614 | return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0, |
1615 | CMD_HW2SW_EQ, | |
1616 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1617 | } |
1618 | ||
ed878458 | 1619 | int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1620 | int cq_num, u8 *status) |
1621 | { | |
ed878458 | 1622 | return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, |
1da177e4 | 1623 | CMD_TIME_CLASS_A, status); |
1da177e4 LT |
1624 | } |
1625 | ||
ed878458 | 1626 | int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1da177e4 LT |
1627 | int cq_num, u8 *status) |
1628 | { | |
ed878458 RD |
1629 | return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0, |
1630 | CMD_HW2SW_CQ, | |
1631 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1632 | } |
1633 | ||
4885bf64 RD |
1634 | int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size, |
1635 | u8 *status) | |
1636 | { | |
1637 | struct mthca_mailbox *mailbox; | |
1638 | __be32 *inbox; | |
1639 | int err; | |
1640 | ||
1641 | #define RESIZE_CQ_IN_SIZE 0x40 | |
1642 | #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c | |
1643 | #define RESIZE_CQ_LKEY_OFFSET 0x1c | |
1644 | ||
1645 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1646 | if (IS_ERR(mailbox)) | |
1647 | return PTR_ERR(mailbox); | |
1648 | inbox = mailbox->buf; | |
1649 | ||
1650 | memset(inbox, 0, RESIZE_CQ_IN_SIZE); | |
1651 | /* | |
1652 | * Leave start address fields zeroed out -- mthca assumes that | |
1653 | * MRs for CQs always start at virtual address 0. | |
1654 | */ | |
1655 | MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET); | |
1656 | MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET); | |
1657 | ||
1658 | err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ, | |
1659 | CMD_TIME_CLASS_B, status); | |
1660 | ||
1661 | mthca_free_mailbox(dev, mailbox); | |
1662 | return err; | |
1663 | } | |
1664 | ||
ec34a922 RD |
1665 | int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1666 | int srq_num, u8 *status) | |
1667 | { | |
1668 | return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ, | |
1669 | CMD_TIME_CLASS_A, status); | |
1670 | } | |
1671 | ||
1672 | int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, | |
1673 | int srq_num, u8 *status) | |
1674 | { | |
1675 | return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0, | |
1676 | CMD_HW2SW_SRQ, | |
1677 | CMD_TIME_CLASS_A, status); | |
1678 | } | |
1679 | ||
8ebe5077 EC |
1680 | int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num, |
1681 | struct mthca_mailbox *mailbox, u8 *status) | |
1682 | { | |
1683 | return mthca_cmd_box(dev, 0, mailbox->dma, num, 0, | |
1684 | CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status); | |
1685 | } | |
1686 | ||
ec34a922 RD |
1687 | int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status) |
1688 | { | |
1689 | return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ, | |
1690 | CMD_TIME_CLASS_B, status); | |
1691 | } | |
1692 | ||
d844183d RD |
1693 | int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur, |
1694 | enum ib_qp_state next, u32 num, int is_ee, | |
1695 | struct mthca_mailbox *mailbox, u32 optmask, | |
1da177e4 LT |
1696 | u8 *status) |
1697 | { | |
d844183d RD |
1698 | static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = { |
1699 | [IB_QPS_RESET] = { | |
1700 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1701 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1702 | [IB_QPS_INIT] = CMD_RST2INIT_QPEE, | |
1703 | }, | |
1704 | [IB_QPS_INIT] = { | |
1705 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1706 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1707 | [IB_QPS_INIT] = CMD_INIT2INIT_QPEE, | |
1708 | [IB_QPS_RTR] = CMD_INIT2RTR_QPEE, | |
1709 | }, | |
1710 | [IB_QPS_RTR] = { | |
1711 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1712 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1713 | [IB_QPS_RTS] = CMD_RTR2RTS_QPEE, | |
1714 | }, | |
1715 | [IB_QPS_RTS] = { | |
1716 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1717 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1718 | [IB_QPS_RTS] = CMD_RTS2RTS_QPEE, | |
1719 | [IB_QPS_SQD] = CMD_RTS2SQD_QPEE, | |
1720 | }, | |
1721 | [IB_QPS_SQD] = { | |
1722 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1723 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1724 | [IB_QPS_RTS] = CMD_SQD2RTS_QPEE, | |
1725 | [IB_QPS_SQD] = CMD_SQD2SQD_QPEE, | |
1726 | }, | |
1727 | [IB_QPS_SQE] = { | |
1728 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1729 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1730 | [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE, | |
1731 | }, | |
1732 | [IB_QPS_ERR] = { | |
1733 | [IB_QPS_RESET] = CMD_ERR2RST_QPEE, | |
1734 | [IB_QPS_ERR] = CMD_2ERR_QPEE, | |
1735 | } | |
1da177e4 | 1736 | }; |
d844183d | 1737 | |
1da177e4 | 1738 | u8 op_mod = 0; |
ed878458 | 1739 | int my_mailbox = 0; |
1da177e4 LT |
1740 | int err; |
1741 | ||
d844183d | 1742 | if (op[cur][next] == CMD_ERR2RST_QPEE) { |
1da177e4 LT |
1743 | op_mod = 3; /* don't write outbox, any->reset */ |
1744 | ||
1745 | /* For debugging */ | |
ed878458 RD |
1746 | if (!mailbox) { |
1747 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1748 | if (!IS_ERR(mailbox)) { | |
1749 | my_mailbox = 1; | |
1750 | op_mod = 2; /* write outbox, any->reset */ | |
1751 | } else | |
1752 | mailbox = NULL; | |
1753 | } | |
d844183d RD |
1754 | |
1755 | err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, | |
1756 | (!!is_ee << 24) | num, op_mod, | |
1757 | op[cur][next], CMD_TIME_CLASS_C, status); | |
1758 | ||
1759 | if (0 && mailbox) { | |
1da177e4 LT |
1760 | int i; |
1761 | mthca_dbg(dev, "Dumping QP context:\n"); | |
d844183d | 1762 | printk(" %08x\n", be32_to_cpup(mailbox->buf)); |
1da177e4 LT |
1763 | for (i = 0; i < 0x100 / 4; ++i) { |
1764 | if (i % 8 == 0) | |
d844183d | 1765 | printk("[%02x] ", i * 4); |
ed878458 | 1766 | printk(" %08x", |
97f52eb4 | 1767 | be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); |
1da177e4 LT |
1768 | if ((i + 1) % 8 == 0) |
1769 | printk("\n"); | |
1770 | } | |
1771 | } | |
1da177e4 | 1772 | |
d844183d RD |
1773 | if (my_mailbox) |
1774 | mthca_free_mailbox(dev, mailbox); | |
1775 | } else { | |
1776 | if (0) { | |
1da177e4 LT |
1777 | int i; |
1778 | mthca_dbg(dev, "Dumping QP context:\n"); | |
d844183d | 1779 | printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf)); |
1da177e4 LT |
1780 | for (i = 0; i < 0x100 / 4; ++i) { |
1781 | if (i % 8 == 0) | |
d844183d | 1782 | printk(" [%02x] ", i * 4); |
ed878458 | 1783 | printk(" %08x", |
97f52eb4 | 1784 | be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); |
1da177e4 LT |
1785 | if ((i + 1) % 8 == 0) |
1786 | printk("\n"); | |
1787 | } | |
1788 | } | |
1789 | ||
d844183d RD |
1790 | err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num, |
1791 | op_mod, op[cur][next], CMD_TIME_CLASS_C, status); | |
1792 | } | |
ed878458 | 1793 | |
1da177e4 LT |
1794 | return err; |
1795 | } | |
1796 | ||
1797 | int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, | |
ed878458 | 1798 | struct mthca_mailbox *mailbox, u8 *status) |
1da177e4 | 1799 | { |
ed878458 RD |
1800 | return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0, |
1801 | CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1802 | } |
1803 | ||
1804 | int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn, | |
1805 | u8 *status) | |
1806 | { | |
1807 | u8 op_mod; | |
1808 | ||
1809 | switch (type) { | |
1810 | case IB_QPT_SMI: | |
1811 | op_mod = 0; | |
1812 | break; | |
1813 | case IB_QPT_GSI: | |
1814 | op_mod = 1; | |
1815 | break; | |
1816 | case IB_QPT_RAW_IPV6: | |
1817 | op_mod = 2; | |
1818 | break; | |
1819 | case IB_QPT_RAW_ETY: | |
1820 | op_mod = 3; | |
1821 | break; | |
1822 | default: | |
1823 | return -EINVAL; | |
1824 | } | |
1825 | ||
1826 | return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, | |
1827 | CMD_TIME_CLASS_B, status); | |
1828 | } | |
1829 | ||
1830 | int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, | |
ed878458 | 1831 | int port, struct ib_wc *in_wc, struct ib_grh *in_grh, |
1da177e4 LT |
1832 | void *in_mad, void *response_mad, u8 *status) |
1833 | { | |
ed878458 RD |
1834 | struct mthca_mailbox *inmailbox, *outmailbox; |
1835 | void *inbox; | |
1da177e4 LT |
1836 | int err; |
1837 | u32 in_modifier = port; | |
1838 | u8 op_modifier = 0; | |
1839 | ||
1840 | #define MAD_IFC_BOX_SIZE 0x400 | |
1841 | #define MAD_IFC_MY_QPN_OFFSET 0x100 | |
68586b67 MT |
1842 | #define MAD_IFC_RQPN_OFFSET 0x108 |
1843 | #define MAD_IFC_SL_OFFSET 0x10c | |
1844 | #define MAD_IFC_G_PATH_OFFSET 0x10d | |
1845 | #define MAD_IFC_RLID_OFFSET 0x10e | |
1846 | #define MAD_IFC_PKEY_OFFSET 0x112 | |
1da177e4 LT |
1847 | #define MAD_IFC_GRH_OFFSET 0x140 |
1848 | ||
ed878458 RD |
1849 | inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); |
1850 | if (IS_ERR(inmailbox)) | |
1851 | return PTR_ERR(inmailbox); | |
1852 | inbox = inmailbox->buf; | |
1853 | ||
1854 | outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
1855 | if (IS_ERR(outmailbox)) { | |
1856 | mthca_free_mailbox(dev, inmailbox); | |
1857 | return PTR_ERR(outmailbox); | |
1858 | } | |
1da177e4 | 1859 | |
ed878458 | 1860 | memcpy(inbox, in_mad, 256); |
1da177e4 LT |
1861 | |
1862 | /* | |
1863 | * Key check traps can't be generated unless we have in_wc to | |
1864 | * tell us where to send the trap. | |
1865 | */ | |
1866 | if (ignore_mkey || !in_wc) | |
1867 | op_modifier |= 0x1; | |
1868 | if (ignore_bkey || !in_wc) | |
1869 | op_modifier |= 0x2; | |
1870 | ||
1871 | if (in_wc) { | |
1872 | u8 val; | |
1873 | ||
ed878458 | 1874 | memset(inbox + 256, 0, 256); |
1da177e4 | 1875 | |
062dbb69 | 1876 | MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET); |
ed878458 | 1877 | MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET); |
1da177e4 LT |
1878 | |
1879 | val = in_wc->sl << 4; | |
ed878458 | 1880 | MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET); |
1da177e4 LT |
1881 | |
1882 | val = in_wc->dlid_path_bits | | |
1883 | (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); | |
68586b67 | 1884 | MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET); |
1da177e4 | 1885 | |
ed878458 RD |
1886 | MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET); |
1887 | MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET); | |
1da177e4 LT |
1888 | |
1889 | if (in_grh) | |
ed878458 | 1890 | memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40); |
1da177e4 | 1891 | |
68586b67 | 1892 | op_modifier |= 0x4; |
1da177e4 LT |
1893 | |
1894 | in_modifier |= in_wc->slid << 16; | |
1895 | } | |
1896 | ||
ed878458 RD |
1897 | err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma, |
1898 | in_modifier, op_modifier, | |
1da177e4 LT |
1899 | CMD_MAD_IFC, CMD_TIME_CLASS_C, status); |
1900 | ||
1901 | if (!err && !*status) | |
ed878458 | 1902 | memcpy(response_mad, outmailbox->buf, 256); |
1da177e4 | 1903 | |
ed878458 RD |
1904 | mthca_free_mailbox(dev, inmailbox); |
1905 | mthca_free_mailbox(dev, outmailbox); | |
1da177e4 LT |
1906 | return err; |
1907 | } | |
1908 | ||
ed878458 RD |
1909 | int mthca_READ_MGM(struct mthca_dev *dev, int index, |
1910 | struct mthca_mailbox *mailbox, u8 *status) | |
1da177e4 | 1911 | { |
ed878458 RD |
1912 | return mthca_cmd_box(dev, 0, mailbox->dma, index, 0, |
1913 | CMD_READ_MGM, CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1914 | } |
1915 | ||
ed878458 RD |
1916 | int mthca_WRITE_MGM(struct mthca_dev *dev, int index, |
1917 | struct mthca_mailbox *mailbox, u8 *status) | |
1da177e4 | 1918 | { |
ed878458 RD |
1919 | return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM, |
1920 | CMD_TIME_CLASS_A, status); | |
1da177e4 LT |
1921 | } |
1922 | ||
ed878458 RD |
1923 | int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, |
1924 | u16 *hash, u8 *status) | |
1da177e4 | 1925 | { |
1da177e4 LT |
1926 | u64 imm; |
1927 | int err; | |
1928 | ||
ed878458 | 1929 | err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH, |
1da177e4 | 1930 | CMD_TIME_CLASS_A, status); |
1da177e4 | 1931 | |
ed878458 | 1932 | *hash = imm; |
1da177e4 LT |
1933 | return err; |
1934 | } | |
1935 | ||
1936 | int mthca_NOP(struct mthca_dev *dev, u8 *status) | |
1937 | { | |
1938 | return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status); | |
1939 | } |