[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mthca / mthca_cmd.h

/*
 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2006 Cisco Systems.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MTHCA_CMD_H
#define MTHCA_CMD_H

#include <rdma/ib_verbs.h>

#define MTHCA_MAILBOX_SIZE 4096

enum {
	/* command completed successfully: */
	MTHCA_CMD_STAT_OK 	      = 0x00,
	/* Internal error (such as a bus error) occurred while processing command: */
	MTHCA_CMD_STAT_INTERNAL_ERR   = 0x01,
	/* Operation/command not supported or opcode modifier not supported: */
	MTHCA_CMD_STAT_BAD_OP 	      = 0x02,
	/* Parameter not supported or parameter out of range: */
	MTHCA_CMD_STAT_BAD_PARAM      = 0x03,
	/* System not enabled or bad system state: */
	MTHCA_CMD_STAT_BAD_SYS_STATE  = 0x04,
	/* Attempt to access reserved or unallocaterd resource: */
	MTHCA_CMD_STAT_BAD_RESOURCE   = 0x05,
	/* Requested resource is currently executing a command, or is otherwise busy: */
	MTHCA_CMD_STAT_RESOURCE_BUSY  = 0x06,
	/* memory error: */
	MTHCA_CMD_STAT_DDR_MEM_ERR    = 0x07,
	/* Required capability exceeds device limits: */
	MTHCA_CMD_STAT_EXCEED_LIM     = 0x08,
	/* Resource is not in the appropriate state or ownership: */
	MTHCA_CMD_STAT_BAD_RES_STATE  = 0x09,
	/* Index out of range: */
	MTHCA_CMD_STAT_BAD_INDEX      = 0x0a,
	/* FW image corrupted: */
	MTHCA_CMD_STAT_BAD_NVMEM      = 0x0b,
	/* Attempt to modify a QP/EE which is not in the presumed state: */
	MTHCA_CMD_STAT_BAD_QPEE_STATE = 0x10,
	/* Bad segment parameters (Address/Size): */
	MTHCA_CMD_STAT_BAD_SEG_PARAM  = 0x20,
	/* Memory Region has Memory Windows bound to: */
	MTHCA_CMD_STAT_REG_BOUND      = 0x21,
	/* HCA local attached memory not present: */
	MTHCA_CMD_STAT_LAM_NOT_PRE    = 0x22,
	/* Bad management packet (silently discarded): */
	MTHCA_CMD_STAT_BAD_PKT 	      = 0x30,
	/* More outstanding CQEs in CQ than new CQ size: */
	MTHCA_CMD_STAT_BAD_SIZE       = 0x40
};

enum {
	MTHCA_TRANS_INVALID = 0,
	MTHCA_TRANS_RST2INIT,
	MTHCA_TRANS_INIT2INIT,
	MTHCA_TRANS_INIT2RTR,
	MTHCA_TRANS_RTR2RTS,
	MTHCA_TRANS_RTS2RTS,
	MTHCA_TRANS_SQERR2RTS,
	MTHCA_TRANS_ANY2ERR,
	MTHCA_TRANS_RTS2SQD,
	MTHCA_TRANS_SQD2SQD,
	MTHCA_TRANS_SQD2RTS,
	MTHCA_TRANS_ANY2RST,
};

enum {
	DEV_LIM_FLAG_RC                 = 1 << 0,
	DEV_LIM_FLAG_UC                 = 1 << 1,
	DEV_LIM_FLAG_UD                 = 1 << 2,
	DEV_LIM_FLAG_RD                 = 1 << 3,
	DEV_LIM_FLAG_RAW_IPV6           = 1 << 4,
	DEV_LIM_FLAG_RAW_ETHER          = 1 << 5,
	DEV_LIM_FLAG_SRQ                = 1 << 6,
	DEV_LIM_FLAG_IPOIB_CSUM		= 1 << 7,
	DEV_LIM_FLAG_BAD_PKEY_CNTR      = 1 << 8,
	DEV_LIM_FLAG_BAD_QKEY_CNTR      = 1 << 9,
	DEV_LIM_FLAG_MW                 = 1 << 16,
	DEV_LIM_FLAG_AUTO_PATH_MIG      = 1 << 17,
	DEV_LIM_FLAG_ATOMIC             = 1 << 18,
	DEV_LIM_FLAG_RAW_MULTI          = 1 << 19,
	DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20,
	DEV_LIM_FLAG_UD_MULTI           = 1 << 21,
};

struct mthca_mailbox {
	dma_addr_t dma;
	void      *buf;
};

struct mthca_dev_lim {
	int max_srq_sz;
	int max_qp_sz;
	int reserved_qps;
	int max_qps;
	int reserved_srqs;
	int max_srqs;
	int reserved_eecs;
	int max_eecs;
	int max_cq_sz;
	int reserved_cqs;
	int max_cqs;
	int max_mpts;
	int reserved_eqs;
	int max_eqs;
	int reserved_mtts;
	int max_mrw_sz;
	int reserved_mrws;
	int max_mtt_seg;
	int max_requester_per_qp;
	int max_responder_per_qp;
	int max_rdma_global;
	int local_ca_ack_delay;
	int max_mtu;
	int max_port_width;
	int max_vl;
	int num_ports;
	int max_gids;
	u16 stat_rate_support;
	int max_pkeys;
	u32 flags;
	int reserved_uars;
	int uar_size;
	int min_page_sz;
	int max_sg;
	int max_desc_sz;
	int max_qp_per_mcg;
	int reserved_mgms;
	int max_mcgs;
	int reserved_pds;
	int max_pds;
	int reserved_rdds;
	int max_rdds;
	int eec_entry_sz;
	int qpc_entry_sz;
	int eeec_entry_sz;
	int eqpc_entry_sz;
	int eqc_entry_sz;
	int cqc_entry_sz;
	int srq_entry_sz;
	int uar_scratch_entry_sz;
	int mpt_entry_sz;
	union {
		struct {
			int max_avs;
		} tavor;
		struct {
			int resize_srq;
			int max_pbl_sz;
			u8  bmme_flags;
			u32 reserved_lkey;
			int lam_required;
			u64 max_icm_sz;
		} arbel;
	} hca;
};

struct mthca_adapter {
	u32  vendor_id;
	u32  device_id;
	u32  revision_id;
	char board_id[MTHCA_BOARD_ID_LEN];
	u8   inta_pin;
};

struct mthca_init_hca_param {
	u64 qpc_base;
	u64 eec_base;
	u64 srqc_base;
	u64 cqc_base;
	u64 eqpc_base;
	u64 eeec_base;
	u64 eqc_base;
	u64 rdb_base;
	u64 mc_base;
	u64 mpt_base;
	u64 mtt_base;
	u64 uar_scratch_base;
	u64 uarc_base;
	u16 log_mc_entry_sz;
	u16 mc_hash_sz;
	u8  log_num_qps;
	u8  log_num_eecs;
	u8  log_num_srqs;
	u8  log_num_cqs;
	u8  log_num_eqs;
	u8  log_mc_table_sz;
	u8  mtt_seg_sz;
	u8  log_mpt_sz;
	u8  log_uar_sz;
	u8  log_uarc_sz;
};

struct mthca_init_ib_param {
	int port_width;
	int vl_cap;
	int mtu_cap;
	u16 gid_cap;
	u16 pkey_cap;
	int set_guid0;
	u64 guid0;
	int set_node_guid;
	u64 node_guid;
	int set_si_guid;
	u64 si_guid;
};

struct mthca_set_ib_param {
	int set_si_guid;
	int reset_qkey_viol;
	u64 si_guid;
	u32 cap_mask;
};

int mthca_cmd_init(struct mthca_dev *dev);
void mthca_cmd_cleanup(struct mthca_dev *dev);
int mthca_cmd_use_events(struct mthca_dev *dev);
void mthca_cmd_use_polling(struct mthca_dev *dev);
void mthca_cmd_event(struct mthca_dev *dev, u16 token,
		     u8  status, u64 out_param);

struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
					  gfp_t gfp_mask);
void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox);

int mthca_SYS_EN(struct mthca_dev *dev, u8 *status);
int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status);
int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status);
int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status);
int mthca_RUN_FW(struct mthca_dev *dev, u8 *status);
int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status);
int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status);
int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status);
int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status);
int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
			struct mthca_dev_lim *dev_lim, u8 *status);
int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
			struct mthca_adapter *adapter, u8 *status);
int mthca_INIT_HCA(struct mthca_dev *dev,
		   struct mthca_init_hca_param *param,
		   u8 *status);
int mthca_INIT_IB(struct mthca_dev *dev,
		  struct mthca_init_ib_param *param,
		  int port, u8 *status);
int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status);
int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status);
int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
		 int port, u8 *status);
int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status);
int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status);
int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status);
int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status);
int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status);
int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
		       u8 *status);
int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		    int mpt_index, u8 *status);
int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		    int mpt_index, u8 *status);
int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		    int num_mtt, u8 *status);
int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status);
int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
		 int eq_num, u8 *status);
int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		   int eq_num, u8 *status);
int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		   int eq_num, u8 *status);
int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		   int cq_num, u8 *status);
int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		   int cq_num, u8 *status);
int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
		    u8 *status);
int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		    int srq_num, u8 *status);
int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		    int srq_num, u8 *status);
int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
		    struct mthca_mailbox *mailbox, u8 *status);
int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status);
int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
		    enum ib_qp_state next, u32 num, int is_ee,
		    struct mthca_mailbox *mailbox, u32 optmask,
		    u8 *status);
int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
		   struct mthca_mailbox *mailbox, u8 *status);
int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
			  u8 *status);
int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
		  int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
		  void *in_mad, void *response_mad, u8 *status);
int mthca_READ_MGM(struct mthca_dev *dev, int index,
		   struct mthca_mailbox *mailbox, u8 *status);
int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
		    struct mthca_mailbox *mailbox, u8 *status);
int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
		    u16 *hash, u8 *status);
int mthca_NOP(struct mthca_dev *dev, u8 *status);

#endif /* MTHCA_CMD_H */
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
2a1d9b7f	3	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4885bf64	4	* Copyright (c) 2006 Cisco Systems. All rights reserved.
1da177e4 LT	5	*
	6	* This software is available to you under a choice of one of two
	7	* licenses. You may choose to be licensed under the terms of the GNU
	8	* General Public License (GPL) Version 2, available from the file
	9	* COPYING in the main directory of this source tree, or the
	10	* OpenIB.org BSD license below:
	11	*
	12	* Redistribution and use in source and binary forms, with or
	13	* without modification, are permitted provided that the following
	14	* conditions are met:
	15	*
	16	* - Redistributions of source code must retain the above
	17	* copyright notice, this list of conditions and the following
	18	* disclaimer.
	19	*
	20	* - Redistributions in binary form must reproduce the above
	21	* copyright notice, this list of conditions and the following
	22	* disclaimer in the documentation and/or other materials
	23	* provided with the distribution.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	26	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	27	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	28	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	29	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	30	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	31	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	32	* SOFTWARE.
1da177e4 LT	33	*/
	34
	35	#ifndef MTHCA_CMD_H
	36	#define MTHCA_CMD_H
	37
a4d61e84	38	#include <rdma/ib_verbs.h>
1da177e4	39
ed878458	40	#define MTHCA_MAILBOX_SIZE 4096
1da177e4 LT	41
	42	enum {
	43	/* command completed successfully: */
	44	MTHCA_CMD_STAT_OK = 0x00,
	45	/* Internal error (such as a bus error) occurred while processing command: */
	46	MTHCA_CMD_STAT_INTERNAL_ERR = 0x01,
	47	/* Operation/command not supported or opcode modifier not supported: */
	48	MTHCA_CMD_STAT_BAD_OP = 0x02,
	49	/* Parameter not supported or parameter out of range: */
	50	MTHCA_CMD_STAT_BAD_PARAM = 0x03,
	51	/* System not enabled or bad system state: */
	52	MTHCA_CMD_STAT_BAD_SYS_STATE = 0x04,
	53	/* Attempt to access reserved or unallocaterd resource: */
	54	MTHCA_CMD_STAT_BAD_RESOURCE = 0x05,
	55	/* Requested resource is currently executing a command, or is otherwise busy: */
	56	MTHCA_CMD_STAT_RESOURCE_BUSY = 0x06,
	57	/* memory error: */
	58	MTHCA_CMD_STAT_DDR_MEM_ERR = 0x07,
	59	/* Required capability exceeds device limits: */
	60	MTHCA_CMD_STAT_EXCEED_LIM = 0x08,
	61	/* Resource is not in the appropriate state or ownership: */
	62	MTHCA_CMD_STAT_BAD_RES_STATE = 0x09,
	63	/* Index out of range: */
	64	MTHCA_CMD_STAT_BAD_INDEX = 0x0a,
	65	/* FW image corrupted: */
	66	MTHCA_CMD_STAT_BAD_NVMEM = 0x0b,
	67	/* Attempt to modify a QP/EE which is not in the presumed state: */
	68	MTHCA_CMD_STAT_BAD_QPEE_STATE = 0x10,
	69	/* Bad segment parameters (Address/Size): */
	70	MTHCA_CMD_STAT_BAD_SEG_PARAM = 0x20,
	71	/* Memory Region has Memory Windows bound to: */
	72	MTHCA_CMD_STAT_REG_BOUND = 0x21,
	73	/* HCA local attached memory not present: */
	74	MTHCA_CMD_STAT_LAM_NOT_PRE = 0x22,
2fa5e2eb	75	/* Bad management packet (silently discarded): */
1da177e4	76	MTHCA_CMD_STAT_BAD_PKT = 0x30,
2fa5e2eb	77	/* More outstanding CQEs in CQ than new CQ size: */
1da177e4 LT	78	MTHCA_CMD_STAT_BAD_SIZE = 0x40
	79	};
	80
	81	enum {
	82	MTHCA_TRANS_INVALID = 0,
	83	MTHCA_TRANS_RST2INIT,
	84	MTHCA_TRANS_INIT2INIT,
	85	MTHCA_TRANS_INIT2RTR,
	86	MTHCA_TRANS_RTR2RTS,
	87	MTHCA_TRANS_RTS2RTS,
	88	MTHCA_TRANS_SQERR2RTS,
	89	MTHCA_TRANS_ANY2ERR,
	90	MTHCA_TRANS_RTS2SQD,
	91	MTHCA_TRANS_SQD2SQD,
	92	MTHCA_TRANS_SQD2RTS,
	93	MTHCA_TRANS_ANY2RST,
	94	};
	95
	96	enum {
	97	DEV_LIM_FLAG_RC = 1 << 0,
	98	DEV_LIM_FLAG_UC = 1 << 1,
	99	DEV_LIM_FLAG_UD = 1 << 2,
	100	DEV_LIM_FLAG_RD = 1 << 3,
	101	DEV_LIM_FLAG_RAW_IPV6 = 1 << 4,
	102	DEV_LIM_FLAG_RAW_ETHER = 1 << 5,
	103	DEV_LIM_FLAG_SRQ = 1 << 6,
680b575f	104	DEV_LIM_FLAG_IPOIB_CSUM = 1 << 7,
1da177e4 LT	105	DEV_LIM_FLAG_BAD_PKEY_CNTR = 1 << 8,
	106	DEV_LIM_FLAG_BAD_QKEY_CNTR = 1 << 9,
	107	DEV_LIM_FLAG_MW = 1 << 16,
	108	DEV_LIM_FLAG_AUTO_PATH_MIG = 1 << 17,
	109	DEV_LIM_FLAG_ATOMIC = 1 << 18,
	110	DEV_LIM_FLAG_RAW_MULTI = 1 << 19,
	111	DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20,
	112	DEV_LIM_FLAG_UD_MULTI = 1 << 21,
	113	};
	114
ed878458 RD	115	struct mthca_mailbox {
	116	dma_addr_t dma;
	117	void *buf;
	118	};
	119
1da177e4 LT	120	struct mthca_dev_lim {
	121	int max_srq_sz;
	122	int max_qp_sz;
	123	int reserved_qps;
	124	int max_qps;
	125	int reserved_srqs;
	126	int max_srqs;
	127	int reserved_eecs;
	128	int max_eecs;
	129	int max_cq_sz;
	130	int reserved_cqs;
	131	int max_cqs;
	132	int max_mpts;
	133	int reserved_eqs;
	134	int max_eqs;
	135	int reserved_mtts;
	136	int max_mrw_sz;
	137	int reserved_mrws;
	138	int max_mtt_seg;
	139	int max_requester_per_qp;
	140	int max_responder_per_qp;
	141	int max_rdma_global;
	142	int local_ca_ack_delay;
	143	int max_mtu;
	144	int max_port_width;
	145	int max_vl;
	146	int num_ports;
	147	int max_gids;
bf6a9e31	148	u16 stat_rate_support;
1da177e4 LT	149	int max_pkeys;
	150	u32 flags;
	151	int reserved_uars;
	152	int uar_size;
	153	int min_page_sz;
	154	int max_sg;
	155	int max_desc_sz;
	156	int max_qp_per_mcg;
	157	int reserved_mgms;
	158	int max_mcgs;
	159	int reserved_pds;
	160	int max_pds;
	161	int reserved_rdds;
	162	int max_rdds;
	163	int eec_entry_sz;
	164	int qpc_entry_sz;
	165	int eeec_entry_sz;
	166	int eqpc_entry_sz;
	167	int eqc_entry_sz;
	168	int cqc_entry_sz;
	169	int srq_entry_sz;
	170	int uar_scratch_entry_sz;
1da177e4 LT	171	int mpt_entry_sz;
	172	union {
	173	struct {
	174	int max_avs;
	175	} tavor;
	176	struct {
	177	int resize_srq;
	178	int max_pbl_sz;
	179	u8 bmme_flags;
	180	u32 reserved_lkey;
	181	int lam_required;
	182	u64 max_icm_sz;
	183	} arbel;
	184	} hca;
	185	};
	186
	187	struct mthca_adapter {
2e8b981c MT	188	u32 vendor_id;
	189	u32 device_id;
	190	u32 revision_id;
	191	char board_id[MTHCA_BOARD_ID_LEN];
	192	u8 inta_pin;
1da177e4 LT	193	};
	194
	195	struct mthca_init_hca_param {
	196	u64 qpc_base;
	197	u64 eec_base;
	198	u64 srqc_base;
	199	u64 cqc_base;
	200	u64 eqpc_base;
	201	u64 eeec_base;
	202	u64 eqc_base;
	203	u64 rdb_base;
	204	u64 mc_base;
	205	u64 mpt_base;
	206	u64 mtt_base;
	207	u64 uar_scratch_base;
	208	u64 uarc_base;
	209	u16 log_mc_entry_sz;
	210	u16 mc_hash_sz;
	211	u8 log_num_qps;
	212	u8 log_num_eecs;
	213	u8 log_num_srqs;
	214	u8 log_num_cqs;
	215	u8 log_num_eqs;
	216	u8 log_mc_table_sz;
	217	u8 mtt_seg_sz;
	218	u8 log_mpt_sz;
	219	u8 log_uar_sz;
	220	u8 log_uarc_sz;
	221	};
	222
	223	struct mthca_init_ib_param {
da6561c2	224	int port_width;
1da177e4 LT	225	int vl_cap;
	226	int mtu_cap;
	227	u16 gid_cap;
	228	u16 pkey_cap;
	229	int set_guid0;
	230	u64 guid0;
	231	int set_node_guid;
	232	u64 node_guid;
	233	int set_si_guid;
	234	u64 si_guid;
	235	};
	236
	237	struct mthca_set_ib_param {
	238	int set_si_guid;
	239	int reset_qkey_viol;
	240	u64 si_guid;
	241	u32 cap_mask;
	242	};
	243
80fd8238 RD	244	int mthca_cmd_init(struct mthca_dev *dev);
80fd8238 RD	245	void mthca_cmd_cleanup(struct mthca_dev *dev);
1da177e4 LT	246	int mthca_cmd_use_events(struct mthca_dev *dev);
	247	void mthca_cmd_use_polling(struct mthca_dev *dev);
	248	void mthca_cmd_event(struct mthca_dev *dev, u16 token,
	249	u8 status, u64 out_param);
	250
ed878458	251	struct mthca_mailbox mthca_alloc_mailbox(struct mthca_dev dev,
87b750dc	252	gfp_t gfp_mask);
ed878458 RD	253	void mthca_free_mailbox(struct mthca_dev dev, struct mthca_mailbox mailbox);
ed878458 RD	254
1da177e4 LT	255	int mthca_SYS_EN(struct mthca_dev dev, u8 status);
	256	int mthca_SYS_DIS(struct mthca_dev dev, u8 status);
	257	int mthca_MAP_FA(struct mthca_dev dev, struct mthca_icm icm, u8 *status);
	258	int mthca_UNMAP_FA(struct mthca_dev dev, u8 status);
	259	int mthca_RUN_FW(struct mthca_dev dev, u8 status);
	260	int mthca_QUERY_FW(struct mthca_dev dev, u8 status);
	261	int mthca_ENABLE_LAM(struct mthca_dev dev, u8 status);
	262	int mthca_DISABLE_LAM(struct mthca_dev dev, u8 status);
	263	int mthca_QUERY_DDR(struct mthca_dev dev, u8 status);
	264	int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
	265	struct mthca_dev_lim dev_lim, u8 status);
	266	int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
	267	struct mthca_adapter adapter, u8 status);
	268	int mthca_INIT_HCA(struct mthca_dev *dev,
	269	struct mthca_init_hca_param *param,
	270	u8 *status);
	271	int mthca_INIT_IB(struct mthca_dev *dev,
	272	struct mthca_init_ib_param *param,
	273	int port, u8 *status);
	274	int mthca_CLOSE_IB(struct mthca_dev dev, int port, u8 status);
	275	int mthca_CLOSE_HCA(struct mthca_dev dev, int panic, u8 status);
	276	int mthca_SET_IB(struct mthca_dev dev, struct mthca_set_ib_param param,
	277	int port, u8 *status);
	278	int mthca_MAP_ICM(struct mthca_dev dev, struct mthca_icm icm, u64 virt, u8 *status);
	279	int mthca_MAP_ICM_page(struct mthca_dev dev, u64 dma_addr, u64 virt, u8 status);
	280	int mthca_UNMAP_ICM(struct mthca_dev dev, u64 virt, u32 page_count, u8 status);
	281	int mthca_MAP_ICM_AUX(struct mthca_dev dev, struct mthca_icm icm, u8 *status);
	282	int mthca_UNMAP_ICM_AUX(struct mthca_dev dev, u8 status);
	283	int mthca_SET_ICM_SIZE(struct mthca_dev dev, u64 icm_size, u64 aux_pages,
	284	u8 *status);
ed878458	285	int mthca_SW2HW_MPT(struct mthca_dev dev, struct mthca_mailbox mailbox,
1da177e4	286	int mpt_index, u8 *status);
ed878458	287	int mthca_HW2SW_MPT(struct mthca_dev dev, struct mthca_mailbox mailbox,
1da177e4	288	int mpt_index, u8 *status);
ed878458	289	int mthca_WRITE_MTT(struct mthca_dev dev, struct mthca_mailbox mailbox,
1da177e4	290	int num_mtt, u8 *status);
b8ca06f6	291	int mthca_SYNC_TPT(struct mthca_dev dev, u8 status);
1da177e4 LT	292	int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1da177e4 LT	293	int eq_num, u8 *status);
ed878458	294	int mthca_SW2HW_EQ(struct mthca_dev dev, struct mthca_mailbox mailbox,
1da177e4	295	int eq_num, u8 *status);
ed878458	296	int mthca_HW2SW_EQ(struct mthca_dev dev, struct mthca_mailbox mailbox,
1da177e4	297	int eq_num, u8 *status);
ed878458	298	int mthca_SW2HW_CQ(struct mthca_dev dev, struct mthca_mailbox mailbox,
1da177e4	299	int cq_num, u8 *status);
ed878458	300	int mthca_HW2SW_CQ(struct mthca_dev dev, struct mthca_mailbox mailbox,
1da177e4	301	int cq_num, u8 *status);
4885bf64 RD	302	int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
4885bf64 RD	303	u8 *status);
ec34a922 RD	304	int mthca_SW2HW_SRQ(struct mthca_dev dev, struct mthca_mailbox mailbox,
	305	int srq_num, u8 *status);
	306	int mthca_HW2SW_SRQ(struct mthca_dev dev, struct mthca_mailbox mailbox,
	307	int srq_num, u8 *status);
8ebe5077 EC	308	int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
8ebe5077 EC	309	struct mthca_mailbox mailbox, u8 status);
ec34a922	310	int mthca_ARM_SRQ(struct mthca_dev dev, int srq_num, int limit, u8 status);
d844183d RD	311	int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
	312	enum ib_qp_state next, u32 num, int is_ee,
	313	struct mthca_mailbox *mailbox, u32 optmask,
1da177e4 LT	314	u8 *status);
1da177e4 LT	315	int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
ed878458	316	struct mthca_mailbox mailbox, u8 status);
1da177e4 LT	317	int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
	318	u8 *status);
	319	int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
ed878458	320	int port, struct ib_wc in_wc, struct ib_grh in_grh,
1da177e4	321	void in_mad, void response_mad, u8 *status);
ed878458 RD	322	int mthca_READ_MGM(struct mthca_dev *dev, int index,
	323	struct mthca_mailbox mailbox, u8 status);
	324	int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
	325	struct mthca_mailbox mailbox, u8 status);
	326	int mthca_MGID_HASH(struct mthca_dev dev, struct mthca_mailbox mailbox,
	327	u16 hash, u8 status);
1da177e4 LT	328	int mthca_NOP(struct mthca_dev dev, u8 status);
1da177e4 LT	329
1da177e4	330	#endif /* MTHCA_CMD_H */