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[mirror_ubuntu-focal-kernel.git] / drivers / infiniband / hw / mthca / mthca_dev.h
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1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
99264c1e 4 * Copyright (c) 2005 Cisco Systems. All rights reserved.
2a1d9b7f
RD		 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_dev.h 1349 2004-12-16 21:09:43Z roland $
37 */
38
39#ifndef MTHCA_DEV_H
40#define MTHCA_DEV_H
41
42#include <linux/spinlock.h>
43#include <linux/kernel.h>
44#include <linux/pci.h>
45#include <linux/dma-mapping.h>
de25968c 46#include <linux/timer.h>
1da177e4
LT		 47#include <asm/semaphore.h>
48
49#include "mthca_provider.h"
50#include "mthca_doorbell.h"
51
52#define DRV_NAME "ib_mthca"
53#define PFX DRV_NAME ": "
cae54bdf
RD		 54#define DRV_VERSION "0.06"
55#define DRV_RELDATE "June 23, 2005"
1da177e4 56
1da177e4
LT		 57enum {
58 MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
59 MTHCA_FLAG_SRQ = 1 << 2,
60 MTHCA_FLAG_MSI = 1 << 3,
61 MTHCA_FLAG_MSI_X = 1 << 4,
e0f5fdca 62 MTHCA_FLAG_NO_LAM = 1 << 5,
68a3c212
RD		 63 MTHCA_FLAG_FMR = 1 << 6,
64 MTHCA_FLAG_MEMFREE = 1 << 7,
65 MTHCA_FLAG_PCIE = 1 << 8
1da177e4
LT		 66};
67
68enum {
69 MTHCA_MAX_PORTS = 2
70};
71
2e8b981c
MT		 72enum {
73 MTHCA_BOARD_ID_LEN = 64
74};
75
1da177e4
LT		 76enum {
77 MTHCA_EQ_CONTEXT_SIZE = 0x40,
78 MTHCA_CQ_CONTEXT_SIZE = 0x40,
79 MTHCA_QP_CONTEXT_SIZE = 0x200,
80 MTHCA_RDB_ENTRY_SIZE = 0x20,
81 MTHCA_AV_SIZE = 0x20,
82 MTHCA_MGM_ENTRY_SIZE = 0x40,
83
84 /* Arbel FW gives us these, but we need them for Tavor */
85 MTHCA_MPT_ENTRY_SIZE = 0x40,
86 MTHCA_MTT_SEG_SIZE = 0x40,
efaae8f7
JM		 87
88 MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
1da177e4
LT		 89};
90
91enum {
92 MTHCA_EQ_CMD,
93 MTHCA_EQ_ASYNC,
94 MTHCA_EQ_COMP,
95 MTHCA_NUM_EQ
96};
97
2a4443a6
MT		 98enum {
99 MTHCA_OPCODE_NOP = 0x00,
100 MTHCA_OPCODE_RDMA_WRITE = 0x08,
101 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
102 MTHCA_OPCODE_SEND = 0x0a,
103 MTHCA_OPCODE_SEND_IMM = 0x0b,
104 MTHCA_OPCODE_RDMA_READ = 0x10,
105 MTHCA_OPCODE_ATOMIC_CS = 0x11,
106 MTHCA_OPCODE_ATOMIC_FA = 0x12,
107 MTHCA_OPCODE_BIND_MW = 0x18,
108 MTHCA_OPCODE_INVALID = 0xff
109};
110
1da177e4 111struct mthca_cmd {
ed878458 112 struct pci_pool *pool;
1da177e4
LT		 113 int use_events;
114 struct semaphore hcr_sem;
115 struct semaphore poll_sem;
116 struct semaphore event_sem;
117 int max_cmds;
118 spinlock_t context_lock;
119 int free_head;
120 struct mthca_cmd_context *context;
121 u16 token_mask;
122};
123
124struct mthca_limits {
125 int num_ports;
126 int vl_cap;
127 int mtu_cap;
128 int gid_table_len;
129 int pkey_table_len;
130 int local_ca_ack_delay;
131 int num_uars;
132 int max_sg;
133 int num_qps;
efaae8f7 134 int max_wqes;
77369ed3 135 int max_desc_sz;
efaae8f7 136 int max_qp_init_rdma;
1da177e4
LT		 137 int reserved_qps;
138 int num_srqs;
efaae8f7 139 int max_srq_wqes;
1da177e4
LT		 140 int reserved_srqs;
141 int num_eecs;
142 int reserved_eecs;
143 int num_cqs;
efaae8f7 144 int max_cqes;
1da177e4
LT		 145 int reserved_cqs;
146 int num_eqs;
147 int reserved_eqs;
148 int num_mpts;
149 int num_mtt_segs;
e0f5fdca 150 int fmr_reserved_mtts;
1da177e4
LT		 151 int reserved_mtts;
152 int reserved_mrws;
153 int reserved_uars;
154 int num_mgms;
155 int num_amgms;
156 int reserved_mcgs;
157 int num_pds;
158 int reserved_pds;
0f69ce1e 159 u32 page_size_cap;
33033b79 160 u32 flags;
da6561c2 161 u8 port_width_cap;
1da177e4
LT		 162};
163
164struct mthca_alloc {
165 u32 last;
166 u32 top;
167 u32 max;
168 u32 mask;
169 spinlock_t lock;
170 unsigned long *table;
171};
172
173struct mthca_array {
174 struct {
175 void **page;
176 int used;
177 } *page_list;
178};
179
180struct mthca_uar_table {
181 struct mthca_alloc alloc;
182 u64 uarc_base;
183 int uarc_size;
184};
185
186struct mthca_pd_table {
187 struct mthca_alloc alloc;
188};
189
9095e208
MT		 190struct mthca_buddy {
191 unsigned long **bits;
192 int max_order;
193 spinlock_t lock;
194};
195
1da177e4
LT		 196struct mthca_mr_table {
197 struct mthca_alloc mpt_alloc;
e0f5fdca
MT		 198 struct mthca_buddy mtt_buddy;
199 struct mthca_buddy *fmr_mtt_buddy;
1da177e4 200 u64 mtt_base;
e0f5fdca 201 u64 mpt_base;
1da177e4
LT		 202 struct mthca_icm_table *mtt_table;
203 struct mthca_icm_table *mpt_table;
e0f5fdca
MT		 204 struct {
205 void __iomem *mpt_base;
206 void __iomem *mtt_base;
207 struct mthca_buddy mtt_buddy;
208 } tavor_fmr;
1da177e4
LT		 209};
210
211struct mthca_eq_table {
212 struct mthca_alloc alloc;
213 void __iomem *clr_int;
214 u32 clr_mask;
215 u32 arm_mask;
216 struct mthca_eq eq[MTHCA_NUM_EQ];
217 u64 icm_virt;
218 struct page *icm_page;
219 dma_addr_t icm_dma;
220 int have_irq;
221 u8 inta_pin;
222};
223
224struct mthca_cq_table {
225 struct mthca_alloc alloc;
226 spinlock_t lock;
227 struct mthca_array cq;
228 struct mthca_icm_table *table;
229};
230
ec34a922
RD		 231struct mthca_srq_table {
232 struct mthca_alloc alloc;
233 spinlock_t lock;
234 struct mthca_array srq;
235 struct mthca_icm_table *table;
236};
237
1da177e4
LT		 238struct mthca_qp_table {
239 struct mthca_alloc alloc;
240 u32 rdb_base;
241 int rdb_shift;
242 int sqp_start;
243 spinlock_t lock;
244 struct mthca_array qp;
245 struct mthca_icm_table *qp_table;
246 struct mthca_icm_table *eqp_table;
08aeb14e 247 struct mthca_icm_table *rdb_table;
1da177e4
LT		 248};
249
250struct mthca_av_table {
251 struct pci_pool *pool;
252 int num_ddr_avs;
253 u64 ddr_av_base;
254 void __iomem *av_map;
255 struct mthca_alloc alloc;
256};
257
258struct mthca_mcg_table {
259 struct semaphore sem;
260 struct mthca_alloc alloc;
261 struct mthca_icm_table *table;
262};
263
3d155f8c
RD		 264struct mthca_catas_err {
265 u64 addr;
266 u32 __iomem *map;
267 unsigned long stop;
268 u32 size;
269 struct timer_list timer;
270};
271
1da177e4
LT		 272struct mthca_dev {
273 struct ib_device ib_dev;
274 struct pci_dev *pdev;
275
276 int hca_type;
277 unsigned long mthca_flags;
278 unsigned long device_cap_flags;
279
280 u32 rev_id;
2e8b981c 281 char board_id[MTHCA_BOARD_ID_LEN];
1da177e4
LT		 282
283 /* firmware info */
284 u64 fw_ver;
285 union {
286 struct {
287 u64 fw_start;
288 u64 fw_end;
289 } tavor;
290 struct {
291 u64 clr_int_base;
292 u64 eq_arm_base;
293 u64 eq_set_ci_base;
294 struct mthca_icm *fw_icm;
295 struct mthca_icm *aux_icm;
296 u16 fw_pages;
297 } arbel;
298 } fw;
299
300 u64 ddr_start;
301 u64 ddr_end;
302
303 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
304 struct semaphore cap_mask_mutex;
305
306 void __iomem *hcr;
307 void __iomem *kar;
308 void __iomem *clr_base;
309 union {
310 struct {
311 void __iomem *ecr_base;
312 } tavor;
313 struct {
314 void __iomem *eq_arm;
315 void __iomem *eq_set_ci_base;
316 } arbel;
317 } eq_regs;
318
319 struct mthca_cmd cmd;
320 struct mthca_limits limits;
321
322 struct mthca_uar_table uar_table;
323 struct mthca_pd_table pd_table;
324 struct mthca_mr_table mr_table;
325 struct mthca_eq_table eq_table;
326 struct mthca_cq_table cq_table;
ec34a922 327 struct mthca_srq_table srq_table;
1da177e4
LT		 328 struct mthca_qp_table qp_table;
329 struct mthca_av_table av_table;
330 struct mthca_mcg_table mcg_table;
331
3d155f8c
RD		 332 struct mthca_catas_err catas_err;
333
1da177e4
LT		 334 struct mthca_uar driver_uar;
335 struct mthca_db_table *db_tab;
336 struct mthca_pd driver_pd;
337 struct mthca_mr driver_mr;
338
339 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
340 struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
341 spinlock_t sm_lock;
342};
343
344#define mthca_dbg(mdev, format, arg...) \
345 dev_dbg(&mdev->pdev->dev, format, ## arg)
346#define mthca_err(mdev, format, arg...) \
347 dev_err(&mdev->pdev->dev, format, ## arg)
348#define mthca_info(mdev, format, arg...) \
349 dev_info(&mdev->pdev->dev, format, ## arg)
350#define mthca_warn(mdev, format, arg...) \
351 dev_warn(&mdev->pdev->dev, format, ## arg)
352
353extern void __buggy_use_of_MTHCA_GET(void);
354extern void __buggy_use_of_MTHCA_PUT(void);
355
356#define MTHCA_GET(dest, source, offset) \
357 do { \
358 void *__p = (char *) (source) + (offset); \
359 switch (sizeof (dest)) { \
360 case 1: (dest) = *(u8 *) __p; break; \
361 case 2: (dest) = be16_to_cpup(__p); break; \
362 case 4: (dest) = be32_to_cpup(__p); break; \
363 case 8: (dest) = be64_to_cpup(__p); break; \
364 default: __buggy_use_of_MTHCA_GET(); \
365 } \
366 } while (0)
367
368#define MTHCA_PUT(dest, source, offset) \
369 do { \
97f52eb4 370 void *__d = ((char *) (dest) + (offset)); \
1da177e4 371 switch (sizeof(source)) { \
97f52eb4
SH		 372 case 1: *(u8 *) __d = (source); break; \
373 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
374 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
375 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
376 default: __buggy_use_of_MTHCA_PUT(); \
1da177e4
LT		 377 } \
378 } while (0)
379
380int mthca_reset(struct mthca_dev *mdev);
381
382u32 mthca_alloc(struct mthca_alloc *alloc);
383void mthca_free(struct mthca_alloc *alloc, u32 obj);
384int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
385 u32 reserved);
386void mthca_alloc_cleanup(struct mthca_alloc *alloc);
387void *mthca_array_get(struct mthca_array *array, int index);
388int mthca_array_set(struct mthca_array *array, int index, void *value);
389void mthca_array_clear(struct mthca_array *array, int index);
390int mthca_array_init(struct mthca_array *array, int nent);
391void mthca_array_cleanup(struct mthca_array *array, int nent);
87b81670
RD		 392int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
393 union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
394 int hca_write, struct mthca_mr *mr);
395void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
396 int is_direct, struct mthca_mr *mr);
1da177e4
LT		 397
398int mthca_init_uar_table(struct mthca_dev *dev);
399int mthca_init_pd_table(struct mthca_dev *dev);
400int mthca_init_mr_table(struct mthca_dev *dev);
401int mthca_init_eq_table(struct mthca_dev *dev);
402int mthca_init_cq_table(struct mthca_dev *dev);
ec34a922 403int mthca_init_srq_table(struct mthca_dev *dev);
1da177e4
LT		 404int mthca_init_qp_table(struct mthca_dev *dev);
405int mthca_init_av_table(struct mthca_dev *dev);
406int mthca_init_mcg_table(struct mthca_dev *dev);
407
408void mthca_cleanup_uar_table(struct mthca_dev *dev);
409void mthca_cleanup_pd_table(struct mthca_dev *dev);
410void mthca_cleanup_mr_table(struct mthca_dev *dev);
411void mthca_cleanup_eq_table(struct mthca_dev *dev);
412void mthca_cleanup_cq_table(struct mthca_dev *dev);
ec34a922 413void mthca_cleanup_srq_table(struct mthca_dev *dev);
1da177e4
LT		 414void mthca_cleanup_qp_table(struct mthca_dev *dev);
415void mthca_cleanup_av_table(struct mthca_dev *dev);
416void mthca_cleanup_mcg_table(struct mthca_dev *dev);
417
418int mthca_register_device(struct mthca_dev *dev);
419void mthca_unregister_device(struct mthca_dev *dev);
420
3d155f8c
RD		 421void mthca_start_catas_poll(struct mthca_dev *dev);
422void mthca_stop_catas_poll(struct mthca_dev *dev);
423
1da177e4
LT		 424int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
425void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
426
99264c1e 427int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
1da177e4
LT		 428void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
429
d56d6f95
RD		 430struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
431void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
432int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
433 int start_index, u64 *buffer_list, int list_len);
434int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
435 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
1da177e4
LT		 436int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
437 u32 access, struct mthca_mr *mr);
438int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
439 u64 *buffer_list, int buffer_size_shift,
440 int list_len, u64 iova, u64 total_size,
441 u32 access, struct mthca_mr *mr);
e0f5fdca
MT		 442void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
443
444int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
445 u32 access, struct mthca_fmr *fmr);
446int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
447 int list_len, u64 iova);
448void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
449int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
450 int list_len, u64 iova);
451void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr);
452int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr);
1da177e4
LT		 453
454int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
455void mthca_unmap_eq_icm(struct mthca_dev *dev);
456
457int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
458 struct ib_wc *entry);
459int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
460int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify);
461int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e 462 struct mthca_ucontext *ctx, u32 pdn,
1da177e4
LT		 463 struct mthca_cq *cq);
464void mthca_free_cq(struct mthca_dev *dev,
465 struct mthca_cq *cq);
affcd505
MT		 466void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
467void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
468 enum ib_event_type event_type);
ec34a922
RD		 469void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
470 struct mthca_srq *srq);
471
472int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
473 struct ib_srq_attr *attr, struct mthca_srq *srq);
474void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
90f104da
RD		 475int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
476 enum ib_srq_attr_mask attr_mask);
ec34a922
RD		 477void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
478 enum ib_event_type event_type);
479void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
480int mthca_tavor_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
481 struct ib_recv_wr **bad_wr);
482int mthca_arbel_post_srq_recv(struct ib_srq *srq, struct ib_recv_wr *wr,
483 struct ib_recv_wr **bad_wr);
1da177e4
LT		 484
485void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
486 enum ib_event_type event_type);
487int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask);
488int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
489 struct ib_send_wr **bad_wr);
490int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
491 struct ib_recv_wr **bad_wr);
492int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
493 struct ib_send_wr **bad_wr);
494int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
495 struct ib_recv_wr **bad_wr);
496int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
97f52eb4 497 int index, int *dbd, __be32 *new_wqe);
1da177e4
LT		 498int mthca_alloc_qp(struct mthca_dev *dev,
499 struct mthca_pd *pd,
500 struct mthca_cq *send_cq,
501 struct mthca_cq *recv_cq,
502 enum ib_qp_type type,
503 enum ib_sig_type send_policy,
80c8ec2c 504 struct ib_qp_cap *cap,
1da177e4
LT		 505 struct mthca_qp *qp);
506int mthca_alloc_sqp(struct mthca_dev *dev,
507 struct mthca_pd *pd,
508 struct mthca_cq *send_cq,
509 struct mthca_cq *recv_cq,
510 enum ib_sig_type send_policy,
80c8ec2c 511 struct ib_qp_cap *cap,
1da177e4
LT		 512 int qpn,
513 int port,
514 struct mthca_sqp *sqp);
515void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
516int mthca_create_ah(struct mthca_dev *dev,
517 struct mthca_pd *pd,
518 struct ib_ah_attr *ah_attr,
519 struct mthca_ah *ah);
520int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
521int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
522 struct ib_ud_header *header);
523
524int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
525int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
526
527int mthca_process_mad(struct ib_device *ibdev,
528 int mad_flags,
529 u8 port_num,
530 struct ib_wc *in_wc,
531 struct ib_grh *in_grh,
532 struct ib_mad *in_mad,
533 struct ib_mad *out_mad);
534int mthca_create_agents(struct mthca_dev *dev);
535void mthca_free_agents(struct mthca_dev *dev);
536
537static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
538{
539 return container_of(ibdev, struct mthca_dev, ib_dev);
540}
541
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RD		 542static inline int mthca_is_memfree(struct mthca_dev *dev)
543{
68a3c212 544 return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
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RD		 545}
546
1da177e4 547#endif /* MTHCA_DEV_H */
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