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ec34a922 RD |
1 | /* |
2 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $ | |
33 | */ | |
34 | ||
8c65b4a6 TS |
35 | #include <linux/slab.h> |
36 | #include <linux/string.h> | |
37 | ||
ec34a922 RD |
38 | #include "mthca_dev.h" |
39 | #include "mthca_cmd.h" | |
40 | #include "mthca_memfree.h" | |
41 | #include "mthca_wqe.h" | |
42 | ||
43 | enum { | |
44 | MTHCA_MAX_DIRECT_SRQ_SIZE = 4 * PAGE_SIZE | |
45 | }; | |
46 | ||
47 | struct mthca_tavor_srq_context { | |
48 | __be64 wqe_base_ds; /* low 6 bits is descriptor size */ | |
49 | __be32 state_pd; | |
50 | __be32 lkey; | |
51 | __be32 uar; | |
fd02e803 EC |
52 | __be16 limit_watermark; |
53 | __be16 wqe_cnt; | |
ec34a922 RD |
54 | u32 reserved[2]; |
55 | }; | |
56 | ||
57 | struct mthca_arbel_srq_context { | |
58 | __be32 state_logsize_srqn; | |
59 | __be32 lkey; | |
60 | __be32 db_index; | |
61 | __be32 logstride_usrpage; | |
62 | __be64 wqe_base; | |
63 | __be32 eq_pd; | |
64 | __be16 limit_watermark; | |
65 | __be16 wqe_cnt; | |
66 | u16 reserved1; | |
67 | __be16 wqe_counter; | |
68 | u32 reserved2[3]; | |
69 | }; | |
70 | ||
71 | static void *get_wqe(struct mthca_srq *srq, int n) | |
72 | { | |
73 | if (srq->is_direct) | |
74 | return srq->queue.direct.buf + (n << srq->wqe_shift); | |
75 | else | |
76 | return srq->queue.page_list[(n << srq->wqe_shift) >> PAGE_SHIFT].buf + | |
77 | ((n << srq->wqe_shift) & (PAGE_SIZE - 1)); | |
78 | } | |
79 | ||
80 | /* | |
81 | * Return a pointer to the location within a WQE that we're using as a | |
e5b251a2 RD |
82 | * link when the WQE is in the free list. We use the imm field |
83 | * because in the Tavor case, posting a WQE may overwrite the next | |
84 | * segment of the previous WQE, but a receive WQE will never touch the | |
85 | * imm field. This avoids corrupting our free list if the previous | |
86 | * WQE has already completed and been put on the free list when we | |
87 | * post the next WQE. | |
ec34a922 RD |
88 | */ |
89 | static inline int *wqe_to_link(void *wqe) | |
90 | { | |
e5b251a2 | 91 | return (int *) (wqe + offsetof(struct mthca_next_seg, imm)); |
ec34a922 RD |
92 | } |
93 | ||
94 | static void mthca_tavor_init_srq_context(struct mthca_dev *dev, | |
95 | struct mthca_pd *pd, | |
96 | struct mthca_srq *srq, | |
97 | struct mthca_tavor_srq_context *context) | |
98 | { | |
99 | memset(context, 0, sizeof *context); | |
100 | ||
101 | context->wqe_base_ds = cpu_to_be64(1 << (srq->wqe_shift - 4)); | |
102 | context->state_pd = cpu_to_be32(pd->pd_num); | |
103 | context->lkey = cpu_to_be32(srq->mr.ibmr.lkey); | |
104 | ||
105 | if (pd->ibpd.uobject) | |
106 | context->uar = | |
107 | cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index); | |
108 | else | |
109 | context->uar = cpu_to_be32(dev->driver_uar.index); | |
110 | } | |
111 | ||
112 | static void mthca_arbel_init_srq_context(struct mthca_dev *dev, | |
113 | struct mthca_pd *pd, | |
114 | struct mthca_srq *srq, | |
115 | struct mthca_arbel_srq_context *context) | |
116 | { | |
117 | int logsize; | |
118 | ||
119 | memset(context, 0, sizeof *context); | |
120 | ||
121 | logsize = long_log2(srq->max) + srq->wqe_shift; | |
122 | context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn); | |
123 | context->lkey = cpu_to_be32(srq->mr.ibmr.lkey); | |
124 | context->db_index = cpu_to_be32(srq->db_index); | |
125 | context->logstride_usrpage = cpu_to_be32((srq->wqe_shift - 4) << 29); | |
126 | if (pd->ibpd.uobject) | |
127 | context->logstride_usrpage |= | |
128 | cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index); | |
129 | else | |
130 | context->logstride_usrpage |= cpu_to_be32(dev->driver_uar.index); | |
131 | context->eq_pd = cpu_to_be32(MTHCA_EQ_ASYNC << 24 | pd->pd_num); | |
132 | } | |
133 | ||
134 | static void mthca_free_srq_buf(struct mthca_dev *dev, struct mthca_srq *srq) | |
135 | { | |
136 | mthca_buf_free(dev, srq->max << srq->wqe_shift, &srq->queue, | |
137 | srq->is_direct, &srq->mr); | |
138 | kfree(srq->wrid); | |
139 | } | |
140 | ||
141 | static int mthca_alloc_srq_buf(struct mthca_dev *dev, struct mthca_pd *pd, | |
142 | struct mthca_srq *srq) | |
143 | { | |
144 | struct mthca_data_seg *scatter; | |
145 | void *wqe; | |
146 | int err; | |
147 | int i; | |
148 | ||
149 | if (pd->ibpd.uobject) | |
150 | return 0; | |
151 | ||
152 | srq->wrid = kmalloc(srq->max * sizeof (u64), GFP_KERNEL); | |
153 | if (!srq->wrid) | |
154 | return -ENOMEM; | |
155 | ||
156 | err = mthca_buf_alloc(dev, srq->max << srq->wqe_shift, | |
157 | MTHCA_MAX_DIRECT_SRQ_SIZE, | |
158 | &srq->queue, &srq->is_direct, pd, 1, &srq->mr); | |
159 | if (err) { | |
160 | kfree(srq->wrid); | |
161 | return err; | |
162 | } | |
163 | ||
164 | /* | |
165 | * Now initialize the SRQ buffer so that all of the WQEs are | |
166 | * linked into the list of free WQEs. In addition, set the | |
167 | * scatter list L_Keys to the sentry value of 0x100. | |
168 | */ | |
169 | for (i = 0; i < srq->max; ++i) { | |
170 | wqe = get_wqe(srq, i); | |
171 | ||
172 | *wqe_to_link(wqe) = i < srq->max - 1 ? i + 1 : -1; | |
173 | ||
174 | for (scatter = wqe + sizeof (struct mthca_next_seg); | |
175 | (void *) scatter < wqe + (1 << srq->wqe_shift); | |
176 | ++scatter) | |
177 | scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); | |
178 | } | |
179 | ||
6577ae51 RD |
180 | srq->last = get_wqe(srq, srq->max - 1); |
181 | ||
ec34a922 RD |
182 | return 0; |
183 | } | |
184 | ||
185 | int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd, | |
186 | struct ib_srq_attr *attr, struct mthca_srq *srq) | |
187 | { | |
188 | struct mthca_mailbox *mailbox; | |
189 | u8 status; | |
190 | int ds; | |
191 | int err; | |
192 | ||
193 | /* Sanity check SRQ size before proceeding */ | |
efaae8f7 | 194 | if (attr->max_wr > dev->limits.max_srq_wqes || |
59fef3b1 | 195 | attr->max_sge > dev->limits.max_srq_sge) |
ec34a922 RD |
196 | return -EINVAL; |
197 | ||
198 | srq->max = attr->max_wr; | |
199 | srq->max_gs = attr->max_sge; | |
ec34a922 RD |
200 | srq->counter = 0; |
201 | ||
202 | if (mthca_is_memfree(dev)) | |
203 | srq->max = roundup_pow_of_two(srq->max + 1); | |
204 | ||
1d7d2f6f | 205 | ds = max(64UL, |
ec34a922 RD |
206 | roundup_pow_of_two(sizeof (struct mthca_next_seg) + |
207 | srq->max_gs * sizeof (struct mthca_data_seg))); | |
ded9ad72 | 208 | |
a07bacca | 209 | if (!mthca_is_memfree(dev) && (ds > dev->limits.max_desc_sz)) |
ded9ad72 JM |
210 | return -EINVAL; |
211 | ||
ec34a922 RD |
212 | srq->wqe_shift = long_log2(ds); |
213 | ||
214 | srq->srqn = mthca_alloc(&dev->srq_table.alloc); | |
215 | if (srq->srqn == -1) | |
216 | return -ENOMEM; | |
217 | ||
218 | if (mthca_is_memfree(dev)) { | |
219 | err = mthca_table_get(dev, dev->srq_table.table, srq->srqn); | |
220 | if (err) | |
221 | goto err_out; | |
222 | ||
223 | if (!pd->ibpd.uobject) { | |
224 | srq->db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SRQ, | |
225 | srq->srqn, &srq->db); | |
226 | if (srq->db_index < 0) { | |
227 | err = -ENOMEM; | |
228 | goto err_out_icm; | |
229 | } | |
230 | } | |
231 | } | |
232 | ||
233 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
234 | if (IS_ERR(mailbox)) { | |
235 | err = PTR_ERR(mailbox); | |
236 | goto err_out_db; | |
237 | } | |
238 | ||
239 | err = mthca_alloc_srq_buf(dev, pd, srq); | |
240 | if (err) | |
241 | goto err_out_mailbox; | |
242 | ||
243 | spin_lock_init(&srq->lock); | |
a3285aa4 | 244 | srq->refcount = 1; |
ec34a922 RD |
245 | init_waitqueue_head(&srq->wait); |
246 | ||
247 | if (mthca_is_memfree(dev)) | |
248 | mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf); | |
249 | else | |
250 | mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf); | |
251 | ||
252 | err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn, &status); | |
253 | ||
254 | if (err) { | |
255 | mthca_warn(dev, "SW2HW_SRQ failed (%d)\n", err); | |
256 | goto err_out_free_buf; | |
257 | } | |
258 | if (status) { | |
259 | mthca_warn(dev, "SW2HW_SRQ returned status 0x%02x\n", | |
260 | status); | |
261 | err = -EINVAL; | |
262 | goto err_out_free_buf; | |
263 | } | |
264 | ||
265 | spin_lock_irq(&dev->srq_table.lock); | |
266 | if (mthca_array_set(&dev->srq_table.srq, | |
267 | srq->srqn & (dev->limits.num_srqs - 1), | |
268 | srq)) { | |
269 | spin_unlock_irq(&dev->srq_table.lock); | |
270 | goto err_out_free_srq; | |
271 | } | |
272 | spin_unlock_irq(&dev->srq_table.lock); | |
273 | ||
274 | mthca_free_mailbox(dev, mailbox); | |
275 | ||
276 | srq->first_free = 0; | |
277 | srq->last_free = srq->max - 1; | |
278 | ||
e10e271b | 279 | attr->max_wr = (mthca_is_memfree(dev)) ? srq->max - 1 : srq->max; |
abb6e9ba DB |
280 | attr->max_sge = srq->max_gs; |
281 | ||
ec34a922 RD |
282 | return 0; |
283 | ||
284 | err_out_free_srq: | |
285 | err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status); | |
286 | if (err) | |
287 | mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err); | |
288 | else if (status) | |
289 | mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status); | |
290 | ||
291 | err_out_free_buf: | |
292 | if (!pd->ibpd.uobject) | |
293 | mthca_free_srq_buf(dev, srq); | |
294 | ||
295 | err_out_mailbox: | |
296 | mthca_free_mailbox(dev, mailbox); | |
297 | ||
298 | err_out_db: | |
299 | if (!pd->ibpd.uobject && mthca_is_memfree(dev)) | |
300 | mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index); | |
301 | ||
302 | err_out_icm: | |
303 | mthca_table_put(dev, dev->srq_table.table, srq->srqn); | |
304 | ||
305 | err_out: | |
306 | mthca_free(&dev->srq_table.alloc, srq->srqn); | |
307 | ||
308 | return err; | |
309 | } | |
310 | ||
a3285aa4 RD |
311 | static inline int get_srq_refcount(struct mthca_dev *dev, struct mthca_srq *srq) |
312 | { | |
313 | int c; | |
314 | ||
315 | spin_lock_irq(&dev->srq_table.lock); | |
316 | c = srq->refcount; | |
317 | spin_unlock_irq(&dev->srq_table.lock); | |
318 | ||
319 | return c; | |
320 | } | |
321 | ||
ec34a922 RD |
322 | void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq) |
323 | { | |
324 | struct mthca_mailbox *mailbox; | |
325 | int err; | |
326 | u8 status; | |
327 | ||
328 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
329 | if (IS_ERR(mailbox)) { | |
330 | mthca_warn(dev, "No memory for mailbox to free SRQ.\n"); | |
331 | return; | |
332 | } | |
333 | ||
334 | err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status); | |
335 | if (err) | |
336 | mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err); | |
337 | else if (status) | |
338 | mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status); | |
339 | ||
340 | spin_lock_irq(&dev->srq_table.lock); | |
341 | mthca_array_clear(&dev->srq_table.srq, | |
342 | srq->srqn & (dev->limits.num_srqs - 1)); | |
a3285aa4 | 343 | --srq->refcount; |
ec34a922 RD |
344 | spin_unlock_irq(&dev->srq_table.lock); |
345 | ||
a3285aa4 | 346 | wait_event(srq->wait, !get_srq_refcount(dev, srq)); |
ec34a922 RD |
347 | |
348 | if (!srq->ibsrq.uobject) { | |
349 | mthca_free_srq_buf(dev, srq); | |
350 | if (mthca_is_memfree(dev)) | |
351 | mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index); | |
352 | } | |
353 | ||
354 | mthca_table_put(dev, dev->srq_table.table, srq->srqn); | |
355 | mthca_free(&dev->srq_table.alloc, srq->srqn); | |
356 | mthca_free_mailbox(dev, mailbox); | |
357 | } | |
358 | ||
90f104da RD |
359 | int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, |
360 | enum ib_srq_attr_mask attr_mask) | |
2fa5e2eb | 361 | { |
90f104da RD |
362 | struct mthca_dev *dev = to_mdev(ibsrq->device); |
363 | struct mthca_srq *srq = to_msrq(ibsrq); | |
364 | int ret; | |
365 | u8 status; | |
366 | ||
367 | /* We don't support resizing SRQs (yet?) */ | |
368 | if (attr_mask & IB_SRQ_MAX_WR) | |
369 | return -EINVAL; | |
370 | ||
371 | if (attr_mask & IB_SRQ_LIMIT) { | |
d4301e2c JM |
372 | if (attr->srq_limit > srq->max) |
373 | return -EINVAL; | |
90f104da RD |
374 | ret = mthca_ARM_SRQ(dev, srq->srqn, attr->srq_limit, &status); |
375 | if (ret) | |
376 | return ret; | |
377 | if (status) | |
378 | return -EINVAL; | |
379 | } | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
8ebe5077 EC |
384 | int mthca_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr) |
385 | { | |
386 | struct mthca_dev *dev = to_mdev(ibsrq->device); | |
387 | struct mthca_srq *srq = to_msrq(ibsrq); | |
388 | struct mthca_mailbox *mailbox; | |
389 | struct mthca_arbel_srq_context *arbel_ctx; | |
fd02e803 | 390 | struct mthca_tavor_srq_context *tavor_ctx; |
8ebe5077 EC |
391 | u8 status; |
392 | int err; | |
393 | ||
394 | mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); | |
395 | if (IS_ERR(mailbox)) | |
396 | return PTR_ERR(mailbox); | |
397 | ||
398 | err = mthca_QUERY_SRQ(dev, srq->srqn, mailbox, &status); | |
399 | if (err) | |
400 | goto out; | |
401 | ||
402 | if (mthca_is_memfree(dev)) { | |
403 | arbel_ctx = mailbox->buf; | |
fd02e803 EC |
404 | srq_attr->srq_limit = be16_to_cpu(arbel_ctx->limit_watermark); |
405 | } else { | |
406 | tavor_ctx = mailbox->buf; | |
407 | srq_attr->srq_limit = be16_to_cpu(tavor_ctx->limit_watermark); | |
408 | } | |
8ebe5077 | 409 | |
e10e271b | 410 | srq_attr->max_wr = (mthca_is_memfree(dev)) ? srq->max - 1 : srq->max; |
8ebe5077 EC |
411 | srq_attr->max_sge = srq->max_gs; |
412 | ||
413 | out: | |
414 | mthca_free_mailbox(dev, mailbox); | |
415 | ||
416 | return err; | |
417 | } | |
418 | ||
ec34a922 RD |
419 | void mthca_srq_event(struct mthca_dev *dev, u32 srqn, |
420 | enum ib_event_type event_type) | |
421 | { | |
422 | struct mthca_srq *srq; | |
423 | struct ib_event event; | |
424 | ||
425 | spin_lock(&dev->srq_table.lock); | |
426 | srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1)); | |
427 | if (srq) | |
a3285aa4 | 428 | ++srq->refcount; |
ec34a922 RD |
429 | spin_unlock(&dev->srq_table.lock); |
430 | ||
431 | if (!srq) { | |
432 | mthca_warn(dev, "Async event for bogus SRQ %08x\n", srqn); | |
433 | return; | |
434 | } | |
435 | ||
436 | if (!srq->ibsrq.event_handler) | |
437 | goto out; | |
438 | ||
439 | event.device = &dev->ib_dev; | |
440 | event.event = event_type; | |
90f104da | 441 | event.element.srq = &srq->ibsrq; |
ec34a922 RD |
442 | srq->ibsrq.event_handler(&event, srq->ibsrq.srq_context); |
443 | ||
444 | out: | |
a3285aa4 RD |
445 | spin_lock(&dev->srq_table.lock); |
446 | if (!--srq->refcount) | |
ec34a922 | 447 | wake_up(&srq->wait); |
a3285aa4 | 448 | spin_unlock(&dev->srq_table.lock); |
ec34a922 RD |
449 | } |
450 | ||
451 | /* | |
452 | * This function must be called with IRQs disabled. | |
453 | */ | |
454 | void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr) | |
455 | { | |
456 | int ind; | |
457 | ||
458 | ind = wqe_addr >> srq->wqe_shift; | |
459 | ||
460 | spin_lock(&srq->lock); | |
461 | ||
462 | if (likely(srq->first_free >= 0)) | |
463 | *wqe_to_link(get_wqe(srq, srq->last_free)) = ind; | |
464 | else | |
465 | srq->first_free = ind; | |
466 | ||
467 | *wqe_to_link(get_wqe(srq, ind)) = -1; | |
468 | srq->last_free = ind; | |
469 | ||
470 | spin_unlock(&srq->lock); | |
471 | } | |
472 | ||
473 | int mthca_tavor_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, | |
474 | struct ib_recv_wr **bad_wr) | |
475 | { | |
476 | struct mthca_dev *dev = to_mdev(ibsrq->device); | |
477 | struct mthca_srq *srq = to_msrq(ibsrq); | |
ae57e24a | 478 | __be32 doorbell[2]; |
ec34a922 RD |
479 | unsigned long flags; |
480 | int err = 0; | |
481 | int first_ind; | |
482 | int ind; | |
483 | int next_ind; | |
484 | int nreq; | |
485 | int i; | |
486 | void *wqe; | |
487 | void *prev_wqe; | |
488 | ||
489 | spin_lock_irqsave(&srq->lock, flags); | |
490 | ||
491 | first_ind = srq->first_free; | |
492 | ||
ab28b171 | 493 | for (nreq = 0; wr; wr = wr->next) { |
ec34a922 RD |
494 | ind = srq->first_free; |
495 | ||
496 | if (ind < 0) { | |
497 | mthca_err(dev, "SRQ %06x full\n", srq->srqn); | |
498 | err = -ENOMEM; | |
499 | *bad_wr = wr; | |
3853194c | 500 | break; |
ec34a922 RD |
501 | } |
502 | ||
503 | wqe = get_wqe(srq, ind); | |
504 | next_ind = *wqe_to_link(wqe); | |
e23d6d2b RD |
505 | |
506 | if (next_ind < 0) { | |
507 | mthca_err(dev, "SRQ %06x full\n", srq->srqn); | |
508 | err = -ENOMEM; | |
509 | *bad_wr = wr; | |
510 | break; | |
511 | } | |
512 | ||
ec34a922 RD |
513 | prev_wqe = srq->last; |
514 | srq->last = wqe; | |
515 | ||
516 | ((struct mthca_next_seg *) wqe)->nda_op = 0; | |
517 | ((struct mthca_next_seg *) wqe)->ee_nds = 0; | |
518 | /* flags field will always remain 0 */ | |
519 | ||
520 | wqe += sizeof (struct mthca_next_seg); | |
521 | ||
522 | if (unlikely(wr->num_sge > srq->max_gs)) { | |
523 | err = -EINVAL; | |
524 | *bad_wr = wr; | |
525 | srq->last = prev_wqe; | |
3853194c | 526 | break; |
ec34a922 RD |
527 | } |
528 | ||
529 | for (i = 0; i < wr->num_sge; ++i) { | |
530 | ((struct mthca_data_seg *) wqe)->byte_count = | |
531 | cpu_to_be32(wr->sg_list[i].length); | |
532 | ((struct mthca_data_seg *) wqe)->lkey = | |
533 | cpu_to_be32(wr->sg_list[i].lkey); | |
534 | ((struct mthca_data_seg *) wqe)->addr = | |
535 | cpu_to_be64(wr->sg_list[i].addr); | |
536 | wqe += sizeof (struct mthca_data_seg); | |
537 | } | |
538 | ||
539 | if (i < srq->max_gs) { | |
540 | ((struct mthca_data_seg *) wqe)->byte_count = 0; | |
541 | ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); | |
542 | ((struct mthca_data_seg *) wqe)->addr = 0; | |
543 | } | |
544 | ||
d6cff021 RD |
545 | ((struct mthca_next_seg *) prev_wqe)->nda_op = |
546 | cpu_to_be32((ind << srq->wqe_shift) | 1); | |
547 | wmb(); | |
548 | ((struct mthca_next_seg *) prev_wqe)->ee_nds = | |
549 | cpu_to_be32(MTHCA_NEXT_DBD); | |
ec34a922 RD |
550 | |
551 | srq->wrid[ind] = wr->wr_id; | |
552 | srq->first_free = next_ind; | |
ab28b171 MT |
553 | |
554 | ++nreq; | |
555 | if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) { | |
556 | nreq = 0; | |
557 | ||
558 | doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift); | |
559 | doorbell[1] = cpu_to_be32(srq->srqn << 8); | |
560 | ||
561 | /* | |
562 | * Make sure that descriptors are written | |
563 | * before doorbell is rung. | |
564 | */ | |
565 | wmb(); | |
566 | ||
567 | mthca_write64(doorbell, | |
568 | dev->kar + MTHCA_RECEIVE_DOORBELL, | |
569 | MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); | |
570 | ||
571 | first_ind = srq->first_free; | |
572 | } | |
ec34a922 RD |
573 | } |
574 | ||
ec34a922 | 575 | if (likely(nreq)) { |
ec34a922 RD |
576 | doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift); |
577 | doorbell[1] = cpu_to_be32((srq->srqn << 8) | nreq); | |
578 | ||
579 | /* | |
580 | * Make sure that descriptors are written before | |
581 | * doorbell is rung. | |
582 | */ | |
583 | wmb(); | |
584 | ||
585 | mthca_write64(doorbell, | |
586 | dev->kar + MTHCA_RECEIVE_DOORBELL, | |
587 | MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); | |
588 | } | |
589 | ||
590 | spin_unlock_irqrestore(&srq->lock, flags); | |
591 | return err; | |
592 | } | |
593 | ||
594 | int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, | |
595 | struct ib_recv_wr **bad_wr) | |
596 | { | |
597 | struct mthca_dev *dev = to_mdev(ibsrq->device); | |
598 | struct mthca_srq *srq = to_msrq(ibsrq); | |
599 | unsigned long flags; | |
600 | int err = 0; | |
601 | int ind; | |
602 | int next_ind; | |
603 | int nreq; | |
604 | int i; | |
605 | void *wqe; | |
606 | ||
607 | spin_lock_irqsave(&srq->lock, flags); | |
608 | ||
609 | for (nreq = 0; wr; ++nreq, wr = wr->next) { | |
610 | ind = srq->first_free; | |
611 | ||
612 | if (ind < 0) { | |
613 | mthca_err(dev, "SRQ %06x full\n", srq->srqn); | |
614 | err = -ENOMEM; | |
615 | *bad_wr = wr; | |
3853194c | 616 | break; |
ec34a922 RD |
617 | } |
618 | ||
619 | wqe = get_wqe(srq, ind); | |
620 | next_ind = *wqe_to_link(wqe); | |
621 | ||
e23d6d2b RD |
622 | if (next_ind < 0) { |
623 | mthca_err(dev, "SRQ %06x full\n", srq->srqn); | |
624 | err = -ENOMEM; | |
625 | *bad_wr = wr; | |
626 | break; | |
627 | } | |
628 | ||
ec34a922 RD |
629 | ((struct mthca_next_seg *) wqe)->nda_op = |
630 | cpu_to_be32((next_ind << srq->wqe_shift) | 1); | |
631 | ((struct mthca_next_seg *) wqe)->ee_nds = 0; | |
632 | /* flags field will always remain 0 */ | |
633 | ||
634 | wqe += sizeof (struct mthca_next_seg); | |
635 | ||
636 | if (unlikely(wr->num_sge > srq->max_gs)) { | |
637 | err = -EINVAL; | |
638 | *bad_wr = wr; | |
3853194c | 639 | break; |
ec34a922 RD |
640 | } |
641 | ||
642 | for (i = 0; i < wr->num_sge; ++i) { | |
643 | ((struct mthca_data_seg *) wqe)->byte_count = | |
644 | cpu_to_be32(wr->sg_list[i].length); | |
645 | ((struct mthca_data_seg *) wqe)->lkey = | |
646 | cpu_to_be32(wr->sg_list[i].lkey); | |
647 | ((struct mthca_data_seg *) wqe)->addr = | |
648 | cpu_to_be64(wr->sg_list[i].addr); | |
649 | wqe += sizeof (struct mthca_data_seg); | |
650 | } | |
651 | ||
652 | if (i < srq->max_gs) { | |
653 | ((struct mthca_data_seg *) wqe)->byte_count = 0; | |
654 | ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY); | |
655 | ((struct mthca_data_seg *) wqe)->addr = 0; | |
656 | } | |
657 | ||
658 | srq->wrid[ind] = wr->wr_id; | |
659 | srq->first_free = next_ind; | |
660 | } | |
661 | ||
662 | if (likely(nreq)) { | |
663 | srq->counter += nreq; | |
664 | ||
665 | /* | |
666 | * Make sure that descriptors are written before | |
667 | * we write doorbell record. | |
668 | */ | |
669 | wmb(); | |
670 | *srq->db = cpu_to_be32(srq->counter); | |
671 | } | |
672 | ||
673 | spin_unlock_irqrestore(&srq->lock, flags); | |
674 | return err; | |
675 | } | |
676 | ||
59fef3b1 JM |
677 | int mthca_max_srq_sge(struct mthca_dev *dev) |
678 | { | |
679 | if (mthca_is_memfree(dev)) | |
680 | return dev->limits.max_sg; | |
681 | ||
682 | /* | |
683 | * SRQ allocations are based on powers of 2 for Tavor, | |
684 | * (although they only need to be multiples of 16 bytes). | |
685 | * | |
686 | * Therefore, we need to base the max number of sg entries on | |
687 | * the largest power of 2 descriptor size that is <= to the | |
688 | * actual max WQE descriptor size, rather than return the | |
689 | * max_sg value given by the firmware (which is based on WQE | |
690 | * sizes as multiples of 16, not powers of 2). | |
691 | * | |
692 | * If SRQ implementation is changed for Tavor to be based on | |
693 | * multiples of 16, the calculation below can be deleted and | |
694 | * the FW max_sg value returned. | |
695 | */ | |
696 | return min_t(int, dev->limits.max_sg, | |
697 | ((1 << (fls(dev->limits.max_desc_sz) - 1)) - | |
698 | sizeof (struct mthca_next_seg)) / | |
699 | sizeof (struct mthca_data_seg)); | |
700 | } | |
701 | ||
ec34a922 RD |
702 | int __devinit mthca_init_srq_table(struct mthca_dev *dev) |
703 | { | |
704 | int err; | |
705 | ||
706 | if (!(dev->mthca_flags & MTHCA_FLAG_SRQ)) | |
707 | return 0; | |
708 | ||
709 | spin_lock_init(&dev->srq_table.lock); | |
710 | ||
711 | err = mthca_alloc_init(&dev->srq_table.alloc, | |
712 | dev->limits.num_srqs, | |
713 | dev->limits.num_srqs - 1, | |
714 | dev->limits.reserved_srqs); | |
715 | if (err) | |
716 | return err; | |
717 | ||
718 | err = mthca_array_init(&dev->srq_table.srq, | |
719 | dev->limits.num_srqs); | |
720 | if (err) | |
721 | mthca_alloc_cleanup(&dev->srq_table.alloc); | |
722 | ||
723 | return err; | |
724 | } | |
725 | ||
e1f7868c | 726 | void mthca_cleanup_srq_table(struct mthca_dev *dev) |
ec34a922 RD |
727 | { |
728 | if (!(dev->mthca_flags & MTHCA_FLAG_SRQ)) | |
729 | return; | |
730 | ||
731 | mthca_array_cleanup(&dev->srq_table.srq, dev->limits.num_srqs); | |
732 | mthca_alloc_cleanup(&dev->srq_table.alloc); | |
733 | } |