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RDMA/nes: Print IP address for critcal errors
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / nes / nes_hw.c
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3c2d774c 1/*
fa6c87d5 2 * Copyright (c) 2006 - 2009 Intel Corporation. All rights reserved.
3c2d774c
GS		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/ip.h>
39#include <linux/tcp.h>
40#include <linux/if_vlan.h>
37dab411 41#include <linux/inet_lro.h>
5a0e3ad6 42#include <linux/slab.h>
3c2d774c
GS		 43
44#include "nes.h"
45
dd37818d
RD		 46static unsigned int nes_lro_max_aggr = NES_LRO_MAX_AGGR;
47module_param(nes_lro_max_aggr, uint, 0444);
48MODULE_PARM_DESC(nes_lro_max_aggr, "NIC LRO max packet aggregation");
49
a4849fc1
CT		 50static int wide_ppm_offset;
51module_param(wide_ppm_offset, int, 0644);
52MODULE_PARM_DESC(wide_ppm_offset, "Increase CX4 interface clock ppm offset, 0=100ppm (default), 1=300ppm");
53
1a855fbf 54static u32 crit_err_count;
3c2d774c
GS		 55u32 int_mod_timer_init;
56u32 int_mod_cq_depth_256;
57u32 int_mod_cq_depth_128;
58u32 int_mod_cq_depth_32;
59u32 int_mod_cq_depth_24;
60u32 int_mod_cq_depth_16;
61u32 int_mod_cq_depth_4;
62u32 int_mod_cq_depth_1;
9d156947 63static const u8 nes_max_critical_error_count = 100;
3c2d774c
GS		 64#include "nes_cm.h"
65
1a855fbf
RD		 66static void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq);
67static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count);
68static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
fcb7ad31 69 struct nes_adapter *nesadapter, u8 OneG_Mode);
1a855fbf
RD		 70static void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
71static void nes_process_aeq(struct nes_device *nesdev, struct nes_hw_aeq *aeq);
72static void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq);
73static void nes_process_iwarp_aeqe(struct nes_device *nesdev,
74 struct nes_hw_aeqe *aeqe);
9d156947 75static void process_critical_error(struct nes_device *nesdev);
1a855fbf
RD		 76static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number);
77static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_Mode);
8b1c9dc4
DW		 78static void nes_terminate_timeout(unsigned long context);
79static void nes_terminate_start_timer(struct nes_qp *nesqp);
3c2d774c
GS		 80
81#ifdef CONFIG_INFINIBAND_NES_DEBUG
82static unsigned char *nes_iwarp_state_str[] = {
25985edc 83 "Non-Existent",
3c2d774c
GS		 84 "Idle",
85 "RTS",
86 "Closing",
87 "RSVD1",
88 "Terminate",
89 "Error",
90 "RSVD2",
91};
92
93static unsigned char *nes_tcp_state_str[] = {
25985edc 94 "Non-Existent",
3c2d774c
GS		 95 "Closed",
96 "Listen",
97 "SYN Sent",
98 "SYN Rcvd",
99 "Established",
100 "Close Wait",
101 "FIN Wait 1",
102 "Closing",
103 "Last Ack",
104 "FIN Wait 2",
105 "Time Wait",
106 "RSVD1",
107 "RSVD2",
108 "RSVD3",
109 "RSVD4",
110};
111#endif
112
6224c7ee
FL		 113static inline void print_ip(struct nes_cm_node *cm_node)
114{
115 unsigned char *rem_addr;
116 if (cm_node) {
117 rem_addr = (unsigned char *)&cm_node->rem_addr;
118 printk(KERN_ERR PFX "Remote IP addr: %pI4\n", rem_addr);
119 }
120}
3c2d774c
GS		 121
122/**
123 * nes_nic_init_timer_defaults
124 */
125void nes_nic_init_timer_defaults(struct nes_device *nesdev, u8 jumbomode)
126{
127 unsigned long flags;
128 struct nes_adapter *nesadapter = nesdev->nesadapter;
129 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
130
131 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
132
133 shared_timer->timer_in_use_min = NES_NIC_FAST_TIMER_LOW;
134 shared_timer->timer_in_use_max = NES_NIC_FAST_TIMER_HIGH;
135 if (jumbomode) {
136 shared_timer->threshold_low = DEFAULT_JUMBO_NES_QL_LOW;
137 shared_timer->threshold_target = DEFAULT_JUMBO_NES_QL_TARGET;
138 shared_timer->threshold_high = DEFAULT_JUMBO_NES_QL_HIGH;
139 } else {
140 shared_timer->threshold_low = DEFAULT_NES_QL_LOW;
141 shared_timer->threshold_target = DEFAULT_NES_QL_TARGET;
142 shared_timer->threshold_high = DEFAULT_NES_QL_HIGH;
143 }
144
145 /* todo use netdev->mtu to set thresholds */
146 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
147}
148
149
150/**
151 * nes_nic_init_timer
152 */
153static void nes_nic_init_timer(struct nes_device *nesdev)
154{
155 unsigned long flags;
156 struct nes_adapter *nesadapter = nesdev->nesadapter;
157 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
158
159 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
160
161 if (shared_timer->timer_in_use_old == 0) {
162 nesdev->deepcq_count = 0;
163 shared_timer->timer_direction_upward = 0;
164 shared_timer->timer_direction_downward = 0;
165 shared_timer->timer_in_use = NES_NIC_FAST_TIMER;
166 shared_timer->timer_in_use_old = 0;
167
168 }
169 if (shared_timer->timer_in_use != shared_timer->timer_in_use_old) {
170 shared_timer->timer_in_use_old = shared_timer->timer_in_use;
171 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL,
172 0x80000000 | ((u32)(shared_timer->timer_in_use*8)));
173 }
174 /* todo use netdev->mtu to set thresholds */
175 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
176}
177
178
179/**
180 * nes_nic_tune_timer
181 */
182static void nes_nic_tune_timer(struct nes_device *nesdev)
183{
184 unsigned long flags;
185 struct nes_adapter *nesadapter = nesdev->nesadapter;
186 struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
187 u16 cq_count = nesdev->currcq_count;
188
189 spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
190
4b1cc7e7
JL		 191 if (shared_timer->cq_count_old <= cq_count)
192 shared_timer->cq_direction_downward = 0;
193 else
3c2d774c
GS		 194 shared_timer->cq_direction_downward++;
195 shared_timer->cq_count_old = cq_count;
196 if (shared_timer->cq_direction_downward > NES_NIC_CQ_DOWNWARD_TREND) {
4b1cc7e7
JL		 197 if (cq_count <= shared_timer->threshold_low &&
198 shared_timer->threshold_low > 4) {
3c2d774c
GS		 199 shared_timer->threshold_low = shared_timer->threshold_low/2;
200 shared_timer->cq_direction_downward=0;
201 nesdev->currcq_count = 0;
202 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
203 return;
204 }
205 }
206
207 if (cq_count > 1) {
208 nesdev->deepcq_count += cq_count;
209 if (cq_count <= shared_timer->threshold_low) { /* increase timer gently */
210 shared_timer->timer_direction_upward++;
211 shared_timer->timer_direction_downward = 0;
212 } else if (cq_count <= shared_timer->threshold_target) { /* balanced */
213 shared_timer->timer_direction_upward = 0;
214 shared_timer->timer_direction_downward = 0;
215 } else if (cq_count <= shared_timer->threshold_high) { /* decrease timer gently */
216 shared_timer->timer_direction_downward++;
217 shared_timer->timer_direction_upward = 0;
218 } else if (cq_count <= (shared_timer->threshold_high) * 2) {
219 shared_timer->timer_in_use -= 2;
220 shared_timer->timer_direction_upward = 0;
221 shared_timer->timer_direction_downward++;
222 } else {
223 shared_timer->timer_in_use -= 4;
224 shared_timer->timer_direction_upward = 0;
225 shared_timer->timer_direction_downward++;
226 }
227
228 if (shared_timer->timer_direction_upward > 3 ) { /* using history */
229 shared_timer->timer_in_use += 3;
230 shared_timer->timer_direction_upward = 0;
231 shared_timer->timer_direction_downward = 0;
232 }
233 if (shared_timer->timer_direction_downward > 5) { /* using history */
234 shared_timer->timer_in_use -= 4 ;
235 shared_timer->timer_direction_downward = 0;
236 shared_timer->timer_direction_upward = 0;
237 }
238 }
239
240 /* boundary checking */
27ffed60
JL		 241 if (shared_timer->timer_in_use > shared_timer->threshold_high)
242 shared_timer->timer_in_use = shared_timer->threshold_high;
243 else if (shared_timer->timer_in_use < shared_timer->threshold_low)
244 shared_timer->timer_in_use = shared_timer->threshold_low;
3c2d774c
GS		 245
246 nesdev->currcq_count = 0;
247
248 spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
249}
250
251
252/**
253 * nes_init_adapter - initialize adapter
254 */
255struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
256 struct nes_adapter *nesadapter = NULL;
257 unsigned long num_pds;
258 u32 u32temp;
259 u32 port_count;
260 u16 max_rq_wrs;
261 u16 max_sq_wrs;
262 u32 max_mr;
263 u32 max_256pbl;
264 u32 max_4kpbl;
265 u32 max_qp;
266 u32 max_irrq;
267 u32 max_cq;
268 u32 hte_index_mask;
269 u32 adapter_size;
270 u32 arp_table_size;
271 u16 vendor_id;
b9c367e7 272 u16 device_id;
3c2d774c
GS		 273 u8 OneG_Mode;
274 u8 func_index;
275
276 /* search the list of existing adapters */
277 list_for_each_entry(nesadapter, &nes_adapter_list, list) {
278 nes_debug(NES_DBG_INIT, "Searching Adapter list for PCI devfn = 0x%X,"
279 " adapter PCI slot/bus = %u/%u, pci devices PCI slot/bus = %u/%u, .\n",
280 nesdev->pcidev->devfn,
281 PCI_SLOT(nesadapter->devfn),
282 nesadapter->bus_number,
283 PCI_SLOT(nesdev->pcidev->devfn),
284 nesdev->pcidev->bus->number );
285 if ((PCI_SLOT(nesadapter->devfn) == PCI_SLOT(nesdev->pcidev->devfn)) &&
286 (nesadapter->bus_number == nesdev->pcidev->bus->number)) {
287 nesadapter->ref_count++;
288 return nesadapter;
289 }
290 }
291
292 /* no adapter found */
293 num_pds = pci_resource_len(nesdev->pcidev, BAR_1) >> PAGE_SHIFT;
294 if ((hw_rev != NE020_REV) && (hw_rev != NE020_REV1)) {
295 nes_debug(NES_DBG_INIT, "NE020 driver detected unknown hardware revision 0x%x\n",
296 hw_rev);
297 return NULL;
298 }
299
300 nes_debug(NES_DBG_INIT, "Determine Soft Reset, QP_control=0x%x, CPU0=0x%x, CPU1=0x%x, CPU2=0x%x\n",
301 nes_read_indexed(nesdev, NES_IDX_QP_CONTROL + PCI_FUNC(nesdev->pcidev->devfn) * 8),
302 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS),
303 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 4),
304 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS + 8));
305
306 nes_debug(NES_DBG_INIT, "Reset and init NE020\n");
307
308
309 if ((port_count = nes_reset_adapter_ne020(nesdev, &OneG_Mode)) == 0)
310 return NULL;
3c2d774c
GS		 311
312 max_qp = nes_read_indexed(nesdev, NES_IDX_QP_CTX_SIZE);
313 nes_debug(NES_DBG_INIT, "QP_CTX_SIZE=%u\n", max_qp);
314
315 u32temp = nes_read_indexed(nesdev, NES_IDX_QUAD_HASH_TABLE_SIZE);
316 if (max_qp > ((u32)1 << (u32temp & 0x001f))) {
317 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to hash table size = 0x%08X\n",
318 max_qp, u32temp);
319 max_qp = (u32)1 << (u32temp & 0x001f);
320 }
321
322 hte_index_mask = ((u32)1 << ((u32temp & 0x001f)+1))-1;
323 nes_debug(NES_DBG_INIT, "Max QP = %u, hte_index_mask = 0x%08X.\n",
324 max_qp, hte_index_mask);
325
326 u32temp = nes_read_indexed(nesdev, NES_IDX_IRRQ_COUNT);
327
328 max_irrq = 1 << (u32temp & 0x001f);
329
330 if (max_qp > max_irrq) {
331 max_qp = max_irrq;
332 nes_debug(NES_DBG_INIT, "Reducing Max QPs to %u due to Available Q1s.\n",
333 max_qp);
334 }
335
336 /* there should be no reason to allocate more pds than qps */
337 if (num_pds > max_qp)
338 num_pds = max_qp;
339
340 u32temp = nes_read_indexed(nesdev, NES_IDX_MRT_SIZE);
341 max_mr = (u32)8192 << (u32temp & 0x7);
342
343 u32temp = nes_read_indexed(nesdev, NES_IDX_PBL_REGION_SIZE);
344 max_256pbl = (u32)1 << (u32temp & 0x0000001f);
345 max_4kpbl = (u32)1 << ((u32temp >> 16) & 0x0000001f);
346 max_cq = nes_read_indexed(nesdev, NES_IDX_CQ_CTX_SIZE);
347
348 u32temp = nes_read_indexed(nesdev, NES_IDX_ARP_CACHE_SIZE);
349 arp_table_size = 1 << u32temp;
350
351 adapter_size = (sizeof(struct nes_adapter) +
352 (sizeof(unsigned long)-1)) & (~(sizeof(unsigned long)-1));
353 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
354 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
355 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
356 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
357 adapter_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
358 adapter_size += sizeof(struct nes_qp **) * max_qp;
359
360 /* allocate a new adapter struct */
361 nesadapter = kzalloc(adapter_size, GFP_KERNEL);
362 if (nesadapter == NULL) {
363 return NULL;
364 }
365
366 nes_debug(NES_DBG_INIT, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
367 nesadapter, (u32)sizeof(struct nes_adapter), adapter_size);
368
fcb7ad31
CT		 369 if (nes_read_eeprom_values(nesdev, nesadapter)) {
370 printk(KERN_ERR PFX "Unable to read EEPROM data.\n");
371 kfree(nesadapter);
372 return NULL;
373 }
374
b9c367e7
CT		 375 nesadapter->vendor_id = (((u32) nesadapter->mac_addr_high) << 8) |
376 (nesadapter->mac_addr_low >> 24);
377
378 pci_bus_read_config_word(nesdev->pcidev->bus, nesdev->pcidev->devfn,
379 PCI_DEVICE_ID, &device_id);
380 nesadapter->vendor_part_id = device_id;
381
fcb7ad31
CT		 382 if (nes_init_serdes(nesdev, hw_rev, port_count, nesadapter,
383 OneG_Mode)) {
384 kfree(nesadapter);
385 return NULL;
386 }
387 nes_init_csr_ne020(nesdev, hw_rev, port_count);
388
7e36d3d7
VM		 389 memset(nesadapter->pft_mcast_map, 255,
390 sizeof nesadapter->pft_mcast_map);
391
3c2d774c
GS		 392 /* populate the new nesadapter */
393 nesadapter->devfn = nesdev->pcidev->devfn;
394 nesadapter->bus_number = nesdev->pcidev->bus->number;
395 nesadapter->ref_count = 1;
396 nesadapter->timer_int_req = 0xffff0000;
397 nesadapter->OneG_Mode = OneG_Mode;
398 nesadapter->doorbell_start = nesdev->doorbell_region;
399
400 /* nesadapter->tick_delta = clk_divisor; */
401 nesadapter->hw_rev = hw_rev;
402 nesadapter->port_count = port_count;
403
404 nesadapter->max_qp = max_qp;
405 nesadapter->hte_index_mask = hte_index_mask;
406 nesadapter->max_irrq = max_irrq;
407 nesadapter->max_mr = max_mr;
408 nesadapter->max_256pbl = max_256pbl - 1;
409 nesadapter->max_4kpbl = max_4kpbl - 1;
410 nesadapter->max_cq = max_cq;
411 nesadapter->free_256pbl = max_256pbl - 1;
412 nesadapter->free_4kpbl = max_4kpbl - 1;
413 nesadapter->max_pd = num_pds;
414 nesadapter->arp_table_size = arp_table_size;
415
416 nesadapter->et_pkt_rate_low = NES_TIMER_ENABLE_LIMIT;
417 if (nes_drv_opt & NES_DRV_OPT_DISABLE_INT_MOD) {
418 nesadapter->et_use_adaptive_rx_coalesce = 0;
419 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT;
420 nesadapter->et_rx_coalesce_usecs_irq = interrupt_mod_interval;
421 } else {
422 nesadapter->et_use_adaptive_rx_coalesce = 1;
423 nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT_DYNAMIC;
424 nesadapter->et_rx_coalesce_usecs_irq = 0;
33718363 425 printk(PFX "%s: Using Adaptive Interrupt Moderation\n", __func__);
3c2d774c
GS		 426 }
427 /* Setup and enable the periodic timer */
428 if (nesadapter->et_rx_coalesce_usecs_irq)
429 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x80000000 |
430 ((u32)(nesadapter->et_rx_coalesce_usecs_irq * 8)));
431 else
432 nes_write32(nesdev->regs+NES_PERIODIC_CONTROL, 0x00000000);
433
434 nesadapter->base_pd = 1;
435
e293a26f
CT		 436 nesadapter->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
437 IB_DEVICE_MEM_WINDOW |
438 IB_DEVICE_MEM_MGT_EXTENSIONS;
3c2d774c
GS		 439
440 nesadapter->allocated_qps = (unsigned long *)&(((unsigned char *)nesadapter)
441 [(sizeof(struct nes_adapter)+(sizeof(unsigned long)-1))&(~(sizeof(unsigned long)-1))]);
442 nesadapter->allocated_cqs = &nesadapter->allocated_qps[BITS_TO_LONGS(max_qp)];
443 nesadapter->allocated_mrs = &nesadapter->allocated_cqs[BITS_TO_LONGS(max_cq)];
444 nesadapter->allocated_pds = &nesadapter->allocated_mrs[BITS_TO_LONGS(max_mr)];
445 nesadapter->allocated_arps = &nesadapter->allocated_pds[BITS_TO_LONGS(num_pds)];
446 nesadapter->qp_table = (struct nes_qp **)(&nesadapter->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
447
448
fd000e12 449 /* mark the usual suspect QPs, MR and CQs as in use */
3c2d774c
GS		 450 for (u32temp = 0; u32temp < NES_FIRST_QPN; u32temp++) {
451 set_bit(u32temp, nesadapter->allocated_qps);
452 set_bit(u32temp, nesadapter->allocated_cqs);
453 }
fd000e12 454 set_bit(0, nesadapter->allocated_mrs);
3c2d774c
GS		 455
456 for (u32temp = 0; u32temp < 20; u32temp++)
457 set_bit(u32temp, nesadapter->allocated_pds);
458 u32temp = nes_read_indexed(nesdev, NES_IDX_QP_MAX_CFG_SIZES);
459
460 max_rq_wrs = ((u32temp >> 8) & 3);
461 switch (max_rq_wrs) {
462 case 0:
463 max_rq_wrs = 4;
464 break;
465 case 1:
466 max_rq_wrs = 16;
467 break;
468 case 2:
469 max_rq_wrs = 32;
470 break;
471 case 3:
472 max_rq_wrs = 512;
473 break;
474 }
475
476 max_sq_wrs = (u32temp & 3);
477 switch (max_sq_wrs) {
478 case 0:
479 max_sq_wrs = 4;
480 break;
481 case 1:
482 max_sq_wrs = 16;
483 break;
484 case 2:
485 max_sq_wrs = 32;
486 break;
487 case 3:
488 max_sq_wrs = 512;
489 break;
490 }
491 nesadapter->max_qp_wr = min(max_rq_wrs, max_sq_wrs);
492 nesadapter->max_irrq_wr = (u32temp >> 16) & 3;
493
494 nesadapter->max_sge = 4;
5924aea6 495 nesadapter->max_cqe = 32766;
3c2d774c
GS		 496
497 if (nes_read_eeprom_values(nesdev, nesadapter)) {
498 printk(KERN_ERR PFX "Unable to read EEPROM data.\n");
499 kfree(nesadapter);
500 return NULL;
501 }
502
503 u32temp = nes_read_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG);
504 nes_write_indexed(nesdev, NES_IDX_TCP_TIMER_CONFIG,
505 (u32temp & 0xff000000) | (nesadapter->tcp_timer_core_clk_divisor & 0x00ffffff));
506
507 /* setup port configuration */
508 if (nesadapter->port_count == 1) {
fcb7ad31 509 nesadapter->log_port = 0x00000000;
3c2d774c
GS		 510 if (nes_drv_opt & NES_DRV_OPT_DUAL_LOGICAL_PORT)
511 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000002);
512 else
513 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
514 } else {
fcb7ad31
CT		 515 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
516 nesadapter->log_port = 0x000000D8;
517 } else {
518 if (nesadapter->port_count == 2)
519 nesadapter->log_port = 0x00000044;
520 else
521 nesadapter->log_port = 0x000000e4;
522 }
3c2d774c
GS		 523 nes_write_indexed(nesdev, NES_IDX_TX_POOL_SIZE, 0x00000003);
524 }
525
fcb7ad31
CT		 526 nes_write_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT,
527 nesadapter->log_port);
3c2d774c
GS		 528 nes_debug(NES_DBG_INIT, "Probe time, LOG2PHY=%u\n",
529 nes_read_indexed(nesdev, NES_IDX_NIC_LOGPORT_TO_PHYPORT));
530
531 spin_lock_init(&nesadapter->resource_lock);
532 spin_lock_init(&nesadapter->phy_lock);
533 spin_lock_init(&nesadapter->pbl_lock);
534 spin_lock_init(&nesadapter->periodic_timer_lock);
535
536 INIT_LIST_HEAD(&nesadapter->nesvnic_list[0]);
537 INIT_LIST_HEAD(&nesadapter->nesvnic_list[1]);
538 INIT_LIST_HEAD(&nesadapter->nesvnic_list[2]);
539 INIT_LIST_HEAD(&nesadapter->nesvnic_list[3]);
540
541 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
542 u32 pcs_control_status0, pcs_control_status1;
543 u32 reset_value;
544 u32 i = 0;
545 u32 int_cnt = 0;
546 u32 ext_cnt = 0;
547 unsigned long flags;
548 u32 j = 0;
549
550 pcs_control_status0 = nes_read_indexed(nesdev,
551 NES_IDX_PHY_PCS_CONTROL_STATUS0);
552 pcs_control_status1 = nes_read_indexed(nesdev,
553 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
554
555 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
556 pcs_control_status0 = nes_read_indexed(nesdev,
557 NES_IDX_PHY_PCS_CONTROL_STATUS0);
558 pcs_control_status1 = nes_read_indexed(nesdev,
559 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
560 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
561 || (0x0F000100 == (pcs_control_status1 & 0x0F000100)))
562 int_cnt++;
563 msleep(1);
564 }
565 if (int_cnt > 1) {
566 spin_lock_irqsave(&nesadapter->phy_lock, flags);
010db4d1 567 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
3c2d774c
GS		 568 mh_detected++;
569 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
570 reset_value |= 0x0000003d;
571 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
572
573 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
574 & 0x00000040) != 0x00000040) && (j++ < 5000));
575 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
576
577 pcs_control_status0 = nes_read_indexed(nesdev,
578 NES_IDX_PHY_PCS_CONTROL_STATUS0);
579 pcs_control_status1 = nes_read_indexed(nesdev,
580 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
581
582 for (i = 0; i < NES_MAX_LINK_CHECK; i++) {
583 pcs_control_status0 = nes_read_indexed(nesdev,
584 NES_IDX_PHY_PCS_CONTROL_STATUS0);
585 pcs_control_status1 = nes_read_indexed(nesdev,
586 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
587 if ((0x0F000100 == (pcs_control_status0 & 0x0F000100))
588 || (0x0F000100 == (pcs_control_status1 & 0x0F000100))) {
589 if (++ext_cnt > int_cnt) {
590 spin_lock_irqsave(&nesadapter->phy_lock, flags);
591 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1,
010db4d1 592 0x0000F088);
3c2d774c
GS		 593 mh_detected++;
594 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
595 reset_value |= 0x0000003d;
596 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
597
598 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
599 & 0x00000040) != 0x00000040) && (j++ < 5000));
600 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
601 break;
602 }
603 }
604 msleep(1);
605 }
606 }
607 }
608
609 if (nesadapter->hw_rev == NE020_REV) {
610 init_timer(&nesadapter->mh_timer);
611 nesadapter->mh_timer.function = nes_mh_fix;
612 nesadapter->mh_timer.expires = jiffies + (HZ/5); /* 1 second */
613 nesadapter->mh_timer.data = (unsigned long)nesdev;
614 add_timer(&nesadapter->mh_timer);
615 } else {
616 nes_write32(nesdev->regs+NES_INTF_INT_STAT, 0x0f000000);
617 }
618
619 init_timer(&nesadapter->lc_timer);
620 nesadapter->lc_timer.function = nes_clc;
621 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
622 nesadapter->lc_timer.data = (unsigned long)nesdev;
623 add_timer(&nesadapter->lc_timer);
624
625 list_add_tail(&nesadapter->list, &nes_adapter_list);
626
627 for (func_index = 0; func_index < 8; func_index++) {
628 pci_bus_read_config_word(nesdev->pcidev->bus,
629 PCI_DEVFN(PCI_SLOT(nesdev->pcidev->devfn),
630 func_index), 0, &vendor_id);
631 if (vendor_id == 0xffff)
632 break;
633 }
33718363 634 nes_debug(NES_DBG_INIT, "%s %d functions found for %s.\n", __func__,
3c2d774c
GS		 635 func_index, pci_name(nesdev->pcidev));
636 nesadapter->adapter_fcn_count = func_index;
637
638 return nesadapter;
639}
640
641
642/**
643 * nes_reset_adapter_ne020
644 */
1a855fbf 645static unsigned int nes_reset_adapter_ne020(struct nes_device *nesdev, u8 *OneG_Mode)
3c2d774c
GS		 646{
647 u32 port_count;
648 u32 u32temp;
649 u32 i;
650
651 u32temp = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
652 port_count = ((u32temp & 0x00000300) >> 8) + 1;
653 /* TODO: assuming that both SERDES are set the same for now */
654 *OneG_Mode = (u32temp & 0x00003c00) ? 0 : 1;
655 nes_debug(NES_DBG_INIT, "Initial Software Reset = 0x%08X, port_count=%u\n",
656 u32temp, port_count);
657 if (*OneG_Mode)
658 nes_debug(NES_DBG_INIT, "Running in 1G mode.\n");
659 u32temp &= 0xff00ffc0;
660 switch (port_count) {
661 case 1:
662 u32temp |= 0x00ee0000;
663 break;
664 case 2:
665 u32temp |= 0x00cc0000;
666 break;
667 case 4:
668 u32temp |= 0x00000000;
669 break;
670 default:
671 return 0;
672 break;
673 }
674
675 /* check and do full reset if needed */
676 if (nes_read_indexed(nesdev, NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8))) {
677 nes_debug(NES_DBG_INIT, "Issuing Full Soft reset = 0x%08X\n", u32temp | 0xd);
678 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
679
680 i = 0;
681 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
682 mdelay(1);
28e43a51 683 if (i > 10000) {
3c2d774c
GS		 684 nes_debug(NES_DBG_INIT, "Did not see full soft reset done.\n");
685 return 0;
686 }
bc5698f3
CT		 687
688 i = 0;
689 while ((nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS) != 0x80) && i++ < 10000)
690 mdelay(1);
28e43a51 691 if (i > 10000) {
bc5698f3
CT		 692 printk(KERN_ERR PFX "Internal CPU not ready, status = %02X\n",
693 nes_read_indexed(nesdev, NES_IDX_INT_CPU_STATUS));
694 return 0;
695 }
3c2d774c
GS		 696 }
697
698 /* port reset */
699 switch (port_count) {
700 case 1:
701 u32temp |= 0x00ee0010;
702 break;
703 case 2:
704 u32temp |= 0x00cc0030;
705 break;
706 case 4:
707 u32temp |= 0x00000030;
708 break;
709 }
710
711 nes_debug(NES_DBG_INIT, "Issuing Port Soft reset = 0x%08X\n", u32temp | 0xd);
712 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, u32temp | 0xd);
713
714 i = 0;
715 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET) & 0x00000040) == 0) && i++ < 10000)
716 mdelay(1);
28e43a51 717 if (i > 10000) {
3c2d774c
GS		 718 nes_debug(NES_DBG_INIT, "Did not see port soft reset done.\n");
719 return 0;
720 }
721
722 /* serdes 0 */
723 i = 0;
724 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
725 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
726 mdelay(1);
28e43a51 727 if (i > 5000) {
3c2d774c
GS		 728 nes_debug(NES_DBG_INIT, "Serdes 0 not ready, status=%x\n", u32temp);
729 return 0;
730 }
731
732 /* serdes 1 */
733 if (port_count > 1) {
734 i = 0;
735 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
736 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
737 mdelay(1);
28e43a51 738 if (i > 5000) {
3c2d774c
GS		 739 nes_debug(NES_DBG_INIT, "Serdes 1 not ready, status=%x\n", u32temp);
740 return 0;
741 }
742 }
743
3c2d774c
GS		 744 return port_count;
745}
746
747
748/**
749 * nes_init_serdes
750 */
1a855fbf 751static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
fcb7ad31 752 struct nes_adapter *nesadapter, u8 OneG_Mode)
3c2d774c
GS		 753{
754 int i;
755 u32 u32temp;
a4849fc1 756 u32 sds;
3c2d774c
GS		 757
758 if (hw_rev != NE020_REV) {
759 /* init serdes 0 */
09124e19
CT		 760 switch (nesadapter->phy_type[0]) {
761 case NES_PHY_TYPE_CX4:
762 if (wide_ppm_offset)
763 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA);
764 else
765 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
766 break;
767 case NES_PHY_TYPE_KR:
768 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
769 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
770 break;
771 case NES_PHY_TYPE_PUMA_1G:
a4849fc1 772 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
a4849fc1
CT		 773 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0);
774 sds |= 0x00000100;
775 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds);
09124e19
CT		 776 break;
777 default:
778 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
779 break;
fcb7ad31 780 }
09124e19 781
a4849fc1
CT		 782 if (!OneG_Mode)
783 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
784
785 if (port_count < 2)
786 return 0;
787
788 /* init serdes 1 */
366835e2
CT		 789 if (!(OneG_Mode && (nesadapter->phy_type[1] != NES_PHY_TYPE_PUMA_1G)))
790 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
791
a4849fc1 792 switch (nesadapter->phy_type[1]) {
4303565d
CT		 793 case NES_PHY_TYPE_ARGUS:
794 case NES_PHY_TYPE_SFP_D:
a4849fc1
CT		 795 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
796 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
797 break;
798 case NES_PHY_TYPE_CX4:
a4849fc1
CT		 799 if (wide_ppm_offset)
800 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA);
a4849fc1 801 break;
09124e19
CT		 802 case NES_PHY_TYPE_KR:
803 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
804 break;
a4849fc1
CT		 805 case NES_PHY_TYPE_PUMA_1G:
806 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
807 sds |= 0x000000100;
808 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
fcb7ad31 809 }
366835e2 810 if (!OneG_Mode) {
a4849fc1 811 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
366835e2
CT		 812 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
813 sds &= 0xFFFFFFBF;
814 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
815 }
3c2d774c
GS		 816 } else {
817 /* init serdes 0 */
818 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
819 i = 0;
820 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0)
821 & 0x0000000f)) != 0x0000000f) && i++ < 5000)
822 mdelay(1);
28e43a51 823 if (i > 5000) {
3c2d774c
GS		 824 nes_debug(NES_DBG_PHY, "Init: serdes 0 not ready, status=%x\n", u32temp);
825 return 1;
826 }
827 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
828 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
829 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
830 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
831 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
832 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
833 if (OneG_Mode)
834 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
835 else
836 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
837
838 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
839 if (port_count > 1) {
840 /* init serdes 1 */
841 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x00000048);
842 i = 0;
843 while (((u32temp = (nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS1)
844 & 0x0000000f)) != 0x0000000f) && (i++ < 5000))
845 mdelay(1);
28e43a51 846 if (i > 5000) {
33718363 847 printk("%s: Init: serdes 1 not ready, status=%x\n", __func__, u32temp);
3c2d774c
GS		 848 /* return 1; */
849 }
850 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x000bdef7);
851 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE1, 0x9ce73000);
852 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE1, 0x0ff00000);
853 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET1, 0x00000000);
854 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS1, 0x00000000);
855 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1, 0x00000000);
856 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL1, 0xf0002222);
857 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000ff);
858 }
859 }
860 return 0;
861}
862
863
864/**
865 * nes_init_csr_ne020
866 * Initialize registers for ne020 hardware
867 */
1a855fbf 868static void nes_init_csr_ne020(struct nes_device *nesdev, u8 hw_rev, u8 port_count)
3c2d774c
GS		 869{
870 u32 u32temp;
871
872 nes_debug(NES_DBG_INIT, "port_count=%d\n", port_count);
873
874 nes_write_indexed(nesdev, 0x000001E4, 0x00000007);
875 /* nes_write_indexed(nesdev, 0x000001E8, 0x000208C4); */
876 nes_write_indexed(nesdev, 0x000001E8, 0x00020874);
877 nes_write_indexed(nesdev, 0x000001D8, 0x00048002);
878 /* nes_write_indexed(nesdev, 0x000001D8, 0x0004B002); */
879 nes_write_indexed(nesdev, 0x000001FC, 0x00050005);
880 nes_write_indexed(nesdev, 0x00000600, 0x55555555);
881 nes_write_indexed(nesdev, 0x00000604, 0x55555555);
882
883 /* TODO: move these MAC register settings to NIC bringup */
884 nes_write_indexed(nesdev, 0x00002000, 0x00000001);
885 nes_write_indexed(nesdev, 0x00002004, 0x00000001);
886 nes_write_indexed(nesdev, 0x00002008, 0x0000FFFF);
887 nes_write_indexed(nesdev, 0x0000200C, 0x00000001);
888 nes_write_indexed(nesdev, 0x00002010, 0x000003c1);
889 nes_write_indexed(nesdev, 0x0000201C, 0x75345678);
890 if (port_count > 1) {
891 nes_write_indexed(nesdev, 0x00002200, 0x00000001);
892 nes_write_indexed(nesdev, 0x00002204, 0x00000001);
893 nes_write_indexed(nesdev, 0x00002208, 0x0000FFFF);
894 nes_write_indexed(nesdev, 0x0000220C, 0x00000001);
895 nes_write_indexed(nesdev, 0x00002210, 0x000003c1);
896 nes_write_indexed(nesdev, 0x0000221C, 0x75345678);
897 nes_write_indexed(nesdev, 0x00000908, 0x20000001);
898 }
899 if (port_count > 2) {
900 nes_write_indexed(nesdev, 0x00002400, 0x00000001);
901 nes_write_indexed(nesdev, 0x00002404, 0x00000001);
902 nes_write_indexed(nesdev, 0x00002408, 0x0000FFFF);
903 nes_write_indexed(nesdev, 0x0000240C, 0x00000001);
904 nes_write_indexed(nesdev, 0x00002410, 0x000003c1);
905 nes_write_indexed(nesdev, 0x0000241C, 0x75345678);
906 nes_write_indexed(nesdev, 0x00000910, 0x20000001);
907
908 nes_write_indexed(nesdev, 0x00002600, 0x00000001);
909 nes_write_indexed(nesdev, 0x00002604, 0x00000001);
910 nes_write_indexed(nesdev, 0x00002608, 0x0000FFFF);
911 nes_write_indexed(nesdev, 0x0000260C, 0x00000001);
912 nes_write_indexed(nesdev, 0x00002610, 0x000003c1);
913 nes_write_indexed(nesdev, 0x0000261C, 0x75345678);
914 nes_write_indexed(nesdev, 0x00000918, 0x20000001);
915 }
916
917 nes_write_indexed(nesdev, 0x00005000, 0x00018000);
918 /* nes_write_indexed(nesdev, 0x00005000, 0x00010000); */
2b537c28
CT		 919 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG1, (wqm_quanta << 1) |
920 0x00000001);
3c2d774c
GS		 921 nes_write_indexed(nesdev, 0x00005008, 0x1F1F1F1F);
922 nes_write_indexed(nesdev, 0x00005010, 0x1F1F1F1F);
923 nes_write_indexed(nesdev, 0x00005018, 0x1F1F1F1F);
924 nes_write_indexed(nesdev, 0x00005020, 0x1F1F1F1F);
925 nes_write_indexed(nesdev, 0x00006090, 0xFFFFFFFF);
926
927 /* TODO: move this to code, get from EEPROM */
928 nes_write_indexed(nesdev, 0x00000900, 0x20000001);
929 nes_write_indexed(nesdev, 0x000060C0, 0x0000028e);
930 nes_write_indexed(nesdev, 0x000060C8, 0x00000020);
7495ab68 931
3c2d774c
GS		 932 nes_write_indexed(nesdev, 0x000001EC, 0x7b2625a0);
933 /* nes_write_indexed(nesdev, 0x000001EC, 0x5f2625a0); */
934
935 if (hw_rev != NE020_REV) {
936 u32temp = nes_read_indexed(nesdev, 0x000008e8);
937 u32temp |= 0x80000000;
938 nes_write_indexed(nesdev, 0x000008e8, u32temp);
939 u32temp = nes_read_indexed(nesdev, 0x000021f8);
940 u32temp &= 0x7fffffff;
941 u32temp |= 0x7fff0010;
942 nes_write_indexed(nesdev, 0x000021f8, u32temp);
e998c25b
CT		 943 if (port_count > 1) {
944 u32temp = nes_read_indexed(nesdev, 0x000023f8);
945 u32temp &= 0x7fffffff;
946 u32temp |= 0x7fff0010;
947 nes_write_indexed(nesdev, 0x000023f8, u32temp);
948 }
3c2d774c
GS		 949 }
950}
951
952
953/**
954 * nes_destroy_adapter - destroy the adapter structure
955 */
956void nes_destroy_adapter(struct nes_adapter *nesadapter)
957{
958 struct nes_adapter *tmp_adapter;
959
960 list_for_each_entry(tmp_adapter, &nes_adapter_list, list) {
961 nes_debug(NES_DBG_SHUTDOWN, "Nes Adapter list entry = 0x%p.\n",
962 tmp_adapter);
963 }
964
965 nesadapter->ref_count--;
966 if (!nesadapter->ref_count) {
967 if (nesadapter->hw_rev == NE020_REV) {
968 del_timer(&nesadapter->mh_timer);
969 }
970 del_timer(&nesadapter->lc_timer);
971
972 list_del(&nesadapter->list);
973 kfree(nesadapter);
974 }
975}
976
977
978/**
979 * nes_init_cqp
980 */
981int nes_init_cqp(struct nes_device *nesdev)
982{
983 struct nes_adapter *nesadapter = nesdev->nesadapter;
984 struct nes_hw_cqp_qp_context *cqp_qp_context;
985 struct nes_hw_cqp_wqe *cqp_wqe;
986 struct nes_hw_ceq *ceq;
987 struct nes_hw_ceq *nic_ceq;
988 struct nes_hw_aeq *aeq;
989 void *vmem;
990 dma_addr_t pmem;
991 u32 count=0;
992 u32 cqp_head;
993 u64 u64temp;
994 u32 u32temp;
995
996 /* allocate CQP memory */
997 /* Need to add max_cq to the aeq size once cq overflow checking is added back */
998 /* SQ is 512 byte aligned, others are 256 byte aligned */
999 nesdev->cqp_mem_size = 512 +
1000 (sizeof(struct nes_hw_cqp_wqe) * NES_CQP_SQ_SIZE) +
1001 (sizeof(struct nes_hw_cqe) * NES_CCQ_SIZE) +
1002 max(((u32)sizeof(struct nes_hw_ceqe) * NES_CCEQ_SIZE), (u32)256) +
1003 max(((u32)sizeof(struct nes_hw_ceqe) * NES_NIC_CEQ_SIZE), (u32)256) +
1004 (sizeof(struct nes_hw_aeqe) * nesadapter->max_qp) +
1005 sizeof(struct nes_hw_cqp_qp_context);
1006
1007 nesdev->cqp_vbase = pci_alloc_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1008 &nesdev->cqp_pbase);
1009 if (!nesdev->cqp_vbase) {
1010 nes_debug(NES_DBG_INIT, "Unable to allocate memory for host descriptor rings\n");
1011 return -ENOMEM;
1012 }
1013 memset(nesdev->cqp_vbase, 0, nesdev->cqp_mem_size);
1014
1015 /* Allocate a twice the number of CQP requests as the SQ size */
1016 nesdev->nes_cqp_requests = kzalloc(sizeof(struct nes_cqp_request) *
1017 2 * NES_CQP_SQ_SIZE, GFP_KERNEL);
1018 if (nesdev->nes_cqp_requests == NULL) {
1019 nes_debug(NES_DBG_INIT, "Unable to allocate memory CQP request entries.\n");
1020 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1021 nesdev->cqp.sq_pbase);
1022 return -ENOMEM;
1023 }
1024
1025 nes_debug(NES_DBG_INIT, "Allocated CQP structures at %p (phys = %016lX), size = %u.\n",
1026 nesdev->cqp_vbase, (unsigned long)nesdev->cqp_pbase, nesdev->cqp_mem_size);
1027
1028 spin_lock_init(&nesdev->cqp.lock);
1029 init_waitqueue_head(&nesdev->cqp.waitq);
1030
1031 /* Setup Various Structures */
1032 vmem = (void *)(((unsigned long)nesdev->cqp_vbase + (512 - 1)) &
1033 ~(unsigned long)(512 - 1));
1034 pmem = (dma_addr_t)(((unsigned long long)nesdev->cqp_pbase + (512 - 1)) &
1035 ~(unsigned long long)(512 - 1));
1036
1037 nesdev->cqp.sq_vbase = vmem;
1038 nesdev->cqp.sq_pbase = pmem;
1039 nesdev->cqp.sq_size = NES_CQP_SQ_SIZE;
1040 nesdev->cqp.sq_head = 0;
1041 nesdev->cqp.sq_tail = 0;
1042 nesdev->cqp.qp_id = PCI_FUNC(nesdev->pcidev->devfn);
1043
1044 vmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
1045 pmem += (sizeof(struct nes_hw_cqp_wqe) * nesdev->cqp.sq_size);
1046
1047 nesdev->ccq.cq_vbase = vmem;
1048 nesdev->ccq.cq_pbase = pmem;
1049 nesdev->ccq.cq_size = NES_CCQ_SIZE;
1050 nesdev->ccq.cq_head = 0;
1051 nesdev->ccq.ce_handler = nes_cqp_ce_handler;
1052 nesdev->ccq.cq_number = PCI_FUNC(nesdev->pcidev->devfn);
1053
1054 vmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
1055 pmem += (sizeof(struct nes_hw_cqe) * nesdev->ccq.cq_size);
1056
1057 nesdev->ceq_index = PCI_FUNC(nesdev->pcidev->devfn);
1058 ceq = &nesadapter->ceq[nesdev->ceq_index];
1059 ceq->ceq_vbase = vmem;
1060 ceq->ceq_pbase = pmem;
1061 ceq->ceq_size = NES_CCEQ_SIZE;
1062 ceq->ceq_head = 0;
1063
1064 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
1065 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * ceq->ceq_size), (u32)256);
1066
1067 nesdev->nic_ceq_index = PCI_FUNC(nesdev->pcidev->devfn) + 8;
1068 nic_ceq = &nesadapter->ceq[nesdev->nic_ceq_index];
1069 nic_ceq->ceq_vbase = vmem;
1070 nic_ceq->ceq_pbase = pmem;
1071 nic_ceq->ceq_size = NES_NIC_CEQ_SIZE;
1072 nic_ceq->ceq_head = 0;
1073
1074 vmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
1075 pmem += max(((u32)sizeof(struct nes_hw_ceqe) * nic_ceq->ceq_size), (u32)256);
1076
1077 aeq = &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)];
1078 aeq->aeq_vbase = vmem;
1079 aeq->aeq_pbase = pmem;
1080 aeq->aeq_size = nesadapter->max_qp;
1081 aeq->aeq_head = 0;
1082
1083 /* Setup QP Context */
1084 vmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
1085 pmem += (sizeof(struct nes_hw_aeqe) * aeq->aeq_size);
1086
1087 cqp_qp_context = vmem;
1088 cqp_qp_context->context_words[0] =
1089 cpu_to_le32((PCI_FUNC(nesdev->pcidev->devfn) << 12) + (2 << 10));
1090 cqp_qp_context->context_words[1] = 0;
1091 cqp_qp_context->context_words[2] = cpu_to_le32((u32)nesdev->cqp.sq_pbase);
1092 cqp_qp_context->context_words[3] = cpu_to_le32(((u64)nesdev->cqp.sq_pbase) >> 32);
1093
1094
1095 /* Write the address to Create CQP */
1096 if ((sizeof(dma_addr_t) > 4)) {
1097 nes_write_indexed(nesdev,
1098 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
1099 ((u64)pmem) >> 32);
1100 } else {
1101 nes_write_indexed(nesdev,
1102 NES_IDX_CREATE_CQP_HIGH + (PCI_FUNC(nesdev->pcidev->devfn) * 8), 0);
1103 }
1104 nes_write_indexed(nesdev,
1105 NES_IDX_CREATE_CQP_LOW + (PCI_FUNC(nesdev->pcidev->devfn) * 8),
1106 (u32)pmem);
1107
1108 INIT_LIST_HEAD(&nesdev->cqp_avail_reqs);
1109 INIT_LIST_HEAD(&nesdev->cqp_pending_reqs);
1110
1111 for (count = 0; count < 2*NES_CQP_SQ_SIZE; count++) {
1112 init_waitqueue_head(&nesdev->nes_cqp_requests[count].waitq);
1113 list_add_tail(&nesdev->nes_cqp_requests[count].list, &nesdev->cqp_avail_reqs);
1114 }
1115
1116 /* Write Create CCQ WQE */
1117 cqp_head = nesdev->cqp.sq_head++;
1118 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1119 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1120 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1121 (NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1122 NES_CQP_CQ_CHK_OVERFLOW | ((u32)nesdev->ccq.cq_size << 16)));
1123 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1124 (nesdev->ccq.cq_number |
1125 ((u32)nesdev->ceq_index << 16)));
1126 u64temp = (u64)nesdev->ccq.cq_pbase;
1127 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1128 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1129 u64temp = (unsigned long)&nesdev->ccq;
1130 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] =
1131 cpu_to_le32((u32)(u64temp >> 1));
1132 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1133 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1134 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1135
1136 /* Write Create CEQ WQE */
1137 cqp_head = nesdev->cqp.sq_head++;
1138 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1139 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1140 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1141 (NES_CQP_CREATE_CEQ + ((u32)nesdev->ceq_index << 8)));
1142 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, ceq->ceq_size);
1143 u64temp = (u64)ceq->ceq_pbase;
1144 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1145
1146 /* Write Create AEQ WQE */
1147 cqp_head = nesdev->cqp.sq_head++;
1148 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1149 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1150 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1151 (NES_CQP_CREATE_AEQ + ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8)));
1152 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX, aeq->aeq_size);
1153 u64temp = (u64)aeq->aeq_pbase;
1154 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1155
1156 /* Write Create NIC CEQ WQE */
1157 cqp_head = nesdev->cqp.sq_head++;
1158 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1159 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1160 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1161 (NES_CQP_CREATE_CEQ + ((u32)nesdev->nic_ceq_index << 8)));
1162 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX, nic_ceq->ceq_size);
1163 u64temp = (u64)nic_ceq->ceq_pbase;
1164 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1165
1166 /* Poll until CCQP done */
1167 count = 0;
1168 do {
1169 if (count++ > 1000) {
1170 printk(KERN_ERR PFX "Error creating CQP\n");
1171 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1172 nesdev->cqp_vbase, nesdev->cqp_pbase);
1173 return -1;
1174 }
1175 udelay(10);
1176 } while (!(nes_read_indexed(nesdev,
1177 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn) * 8)) & (1 << 8)));
1178
1179 nes_debug(NES_DBG_INIT, "CQP Status = 0x%08X\n", nes_read_indexed(nesdev,
1180 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1181
1182 u32temp = 0x04800000;
1183 nes_write32(nesdev->regs+NES_WQE_ALLOC, u32temp | nesdev->cqp.qp_id);
1184
1185 /* wait for the CCQ, CEQ, and AEQ to get created */
1186 count = 0;
1187 do {
1188 if (count++ > 1000) {
1189 printk(KERN_ERR PFX "Error creating CCQ, CEQ, and AEQ\n");
1190 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size,
1191 nesdev->cqp_vbase, nesdev->cqp_pbase);
1192 return -1;
1193 }
1194 udelay(10);
1195 } while (((nes_read_indexed(nesdev,
1196 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15<<8)) != (15<<8)));
1197
1198 /* dump the QP status value */
1199 nes_debug(NES_DBG_INIT, "QP Status = 0x%08X\n", nes_read_indexed(nesdev,
1200 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1201
1202 nesdev->cqp.sq_tail++;
1203
1204 return 0;
1205}
1206
1207
1208/**
1209 * nes_destroy_cqp
1210 */
1211int nes_destroy_cqp(struct nes_device *nesdev)
1212{
1213 struct nes_hw_cqp_wqe *cqp_wqe;
1214 u32 count = 0;
1215 u32 cqp_head;
1216 unsigned long flags;
1217
1218 do {
1219 if (count++ > 1000)
1220 break;
1221 udelay(10);
1222 } while (!(nesdev->cqp.sq_head == nesdev->cqp.sq_tail));
1223
1224 /* Reset CCQ */
1225 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_RESET |
1226 nesdev->ccq.cq_number);
1227
1228 /* Disable device interrupts */
1229 nes_write32(nesdev->regs+NES_INT_MASK, 0x7fffffff);
1230
1231 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1232
1233 /* Destroy the AEQ */
1234 cqp_head = nesdev->cqp.sq_head++;
1235 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1236 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1237 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_AEQ |
1238 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 8));
1239 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
1240
1241 /* Destroy the NIC CEQ */
1242 cqp_head = nesdev->cqp.sq_head++;
1243 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1244 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1245 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1246 ((u32)nesdev->nic_ceq_index << 8));
1247
1248 /* Destroy the CEQ */
1249 cqp_head = nesdev->cqp.sq_head++;
1250 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1251 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1252 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CEQ |
1253 (nesdev->ceq_index << 8));
1254
1255 /* Destroy the CCQ */
1256 cqp_head = nesdev->cqp.sq_head++;
1257 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1258 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1259 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_CQ);
1260 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->ccq.cq_number |
1261 ((u32)nesdev->ceq_index << 16));
1262
1263 /* Destroy CQP */
1264 cqp_head = nesdev->cqp.sq_head++;
1265 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
1266 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1267 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_DESTROY_QP |
1268 NES_CQP_QP_TYPE_CQP);
1269 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesdev->cqp.qp_id);
1270
1271 barrier();
1272 /* Ring doorbell (5 WQEs) */
1273 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x05800000 | nesdev->cqp.qp_id);
1274
1275 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1276
1277 /* wait for the CCQ, CEQ, and AEQ to get destroyed */
1278 count = 0;
1279 do {
1280 if (count++ > 1000) {
1281 printk(KERN_ERR PFX "Function%d: Error destroying CCQ, CEQ, and AEQ\n",
1282 PCI_FUNC(nesdev->pcidev->devfn));
1283 break;
1284 }
1285 udelay(10);
1286 } while (((nes_read_indexed(nesdev,
1287 NES_IDX_QP_CONTROL + (PCI_FUNC(nesdev->pcidev->devfn)*8)) & (15 << 8)) != 0));
1288
1289 /* dump the QP status value */
1290 nes_debug(NES_DBG_SHUTDOWN, "Function%d: QP Status = 0x%08X\n",
1291 PCI_FUNC(nesdev->pcidev->devfn),
1292 nes_read_indexed(nesdev,
1293 NES_IDX_QP_CONTROL+(PCI_FUNC(nesdev->pcidev->devfn)*8)));
1294
1295 kfree(nesdev->nes_cqp_requests);
1296
1297 /* Free the control structures */
1298 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1299 nesdev->cqp.sq_pbase);
1300
1301 return 0;
1302}
1303
1304
1305/**
09124e19 1306 * nes_init_1g_phy
3c2d774c 1307 */
53978b46 1308static int nes_init_1g_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index)
3c2d774c 1309{
3c2d774c 1310 u32 counter = 0;
3c2d774c 1311 u16 phy_data;
09124e19 1312 int ret = 0;
3c2d774c 1313
09124e19
CT		 1314 nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data);
1315 nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000);
3c2d774c 1316
09124e19
CT		 1317 /* Reset the PHY */
1318 nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000);
1319 udelay(100);
1320 counter = 0;
1321 do {
1b949324 1322 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
09124e19
CT		 1323 if (counter++ > 100) {
1324 ret = -1;
1325 break;
1326 }
1327 } while (phy_data & 0x8000);
1328
1329 /* Setting no phy loopback */
1330 phy_data &= 0xbfff;
1331 phy_data |= 0x1140;
1332 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
1333 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1334 nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data);
1335 nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data);
1336
1337 /* Setting the interrupt mask */
1338 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1339 nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee);
1340 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1341
1342 /* turning on flow control */
1343 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1344 nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00);
1345 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1346
1347 /* Clear Half duplex */
1348 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1349 nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100));
1350 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1351
1352 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1353 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300);
1354
1355 return ret;
1356}
0e1de5d6 1357
0e1de5d6 1358
09124e19
CT		 1359/**
1360 * nes_init_2025_phy
1361 */
53978b46 1362static int nes_init_2025_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index)
09124e19
CT		 1363{
1364 u32 temp_phy_data = 0;
1365 u32 temp_phy_data2 = 0;
1366 u32 counter = 0;
1367 u32 sds;
1368 u32 mac_index = nesdev->mac_index;
1369 int ret = 0;
1370 unsigned int first_attempt = 1;
1371
1372 /* Check firmware heartbeat */
1373 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1374 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1375 udelay(1500);
1376 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1377 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1378
1379 if (temp_phy_data != temp_phy_data2) {
1380 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1381 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1382 if ((temp_phy_data & 0xff) > 0x20)
1383 return 0;
1384 printk(PFX "Reinitialize external PHY\n");
1b949324 1385 }
0e1de5d6 1386
09124e19
CT		 1387 /* no heartbeat, configure the PHY */
1388 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000);
1389 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000);
1390 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1391 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
a2765103 1392
09124e19
CT		 1393 switch (phy_type) {
1394 case NES_PHY_TYPE_ARGUS:
1395 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1396 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1397 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1398 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
1399 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1400 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1401 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1b949324 1402
09124e19
CT		 1403 /* setup LEDs */
1404 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1405 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1406 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1407 break;
0e1de5d6 1408
09124e19 1409 case NES_PHY_TYPE_SFP_D:
1b949324
CT		 1410 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1411 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
09124e19
CT		 1412 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004);
1413 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038);
1414 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1b949324
CT		 1415 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1416 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
0e1de5d6 1417
1b949324
CT		 1418 /* setup LEDs */
1419 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1420 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1421 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
09124e19
CT		 1422 break;
1423
1424 case NES_PHY_TYPE_KR:
1425 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1426 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1427 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1428 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0010);
1429 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013);
1430 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0080);
1431 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1432
1433 /* setup LEDs */
1434 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x000B);
1435 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x0003);
1436 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0004);
1437
1438 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0022, 0x406D);
1439 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0023, 0x0020);
1440 break;
1441 }
0e1de5d6 1442
09124e19 1443 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528);
0e1de5d6 1444
09124e19
CT		 1445 /* Bring PHY out of reset */
1446 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002);
0e1de5d6 1447
09124e19
CT		 1448 /* Check for heartbeat */
1449 counter = 0;
1450 mdelay(690);
1451 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1452 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1453 do {
1454 if (counter++ > 150) {
1455 printk(PFX "No PHY heartbeat\n");
1456 break;
1457 }
1458 mdelay(1);
1b949324 1459 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
09124e19
CT		 1460 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1461 } while ((temp_phy_data2 == temp_phy_data));
1462
1463 /* wait for tracking */
1464 counter = 0;
1465 do {
1466 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1b949324 1467 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
09124e19
CT		 1468 if (counter++ > 300) {
1469 if (((temp_phy_data & 0xff) == 0x0) && first_attempt) {
1470 first_attempt = 0;
1471 counter = 0;
1472 /* reset AMCC PHY and try again */
1473 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x00c0);
1474 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x0040);
1475 continue;
1476 } else {
1477 ret = 1;
1b949324
CT		 1478 break;
1479 }
09124e19
CT		 1480 }
1481 mdelay(10);
1482 } while ((temp_phy_data & 0xff) < 0x30);
1483
1484 /* setup signal integrity */
1485 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000);
1486 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE);
1487 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032);
1488 if (phy_type == NES_PHY_TYPE_KR) {
1489 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x000C);
1490 } else {
1b949324
CT		 1491 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002);
1492 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063);
09124e19
CT		 1493 }
1494
1495 /* reset serdes */
1496 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200);
1497 sds |= 0x1;
1498 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds);
1499 sds &= 0xfffffffe;
1500 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds);
1501
1502 counter = 0;
1503 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
1504 && (counter++ < 5000))
1505 ;
1b949324 1506
09124e19
CT		 1507 return ret;
1508}
1509
1510
1511/**
1512 * nes_init_phy
1513 */
1514int nes_init_phy(struct nes_device *nesdev)
1515{
1516 struct nes_adapter *nesadapter = nesdev->nesadapter;
1517 u32 mac_index = nesdev->mac_index;
1518 u32 tx_config = 0;
1519 unsigned long flags;
1520 u8 phy_type = nesadapter->phy_type[mac_index];
1521 u8 phy_index = nesadapter->phy_index[mac_index];
1522 int ret = 0;
1523
1524 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1525 if (phy_type == NES_PHY_TYPE_1G) {
1526 /* setup 1G MDIO operation */
1527 tx_config &= 0xFFFFFFE3;
1528 tx_config |= 0x04;
1529 } else {
1530 /* setup 10G MDIO operation */
1531 tx_config &= 0xFFFFFFE3;
1532 tx_config |= 0x15;
3c2d774c 1533 }
09124e19
CT		 1534 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1535
1536 spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags);
1537
1538 switch (phy_type) {
1539 case NES_PHY_TYPE_1G:
1540 ret = nes_init_1g_phy(nesdev, phy_type, phy_index);
1541 break;
1542 case NES_PHY_TYPE_ARGUS:
1543 case NES_PHY_TYPE_SFP_D:
1544 case NES_PHY_TYPE_KR:
1545 ret = nes_init_2025_phy(nesdev, phy_type, phy_index);
1546 break;
1547 }
1548
1549 spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags);
1550
1551 return ret;
3c2d774c
GS		 1552}
1553
1554
1555/**
1556 * nes_replenish_nic_rq
1557 */
1558static void nes_replenish_nic_rq(struct nes_vnic *nesvnic)
1559{
1560 unsigned long flags;
1561 dma_addr_t bus_address;
1562 struct sk_buff *skb;
1563 struct nes_hw_nic_rq_wqe *nic_rqe;
1564 struct nes_hw_nic *nesnic;
1565 struct nes_device *nesdev;
1566 u32 rx_wqes_posted = 0;
1567
1568 nesnic = &nesvnic->nic;
1569 nesdev = nesvnic->nesdev;
1570 spin_lock_irqsave(&nesnic->rq_lock, flags);
1571 if (nesnic->replenishing_rq !=0) {
1572 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1573 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1574 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1575 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1576 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1577 add_timer(&nesvnic->rq_wqes_timer);
1578 } else
1579 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1580 return;
1581 }
1582 nesnic->replenishing_rq = 1;
1583 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1584 do {
1585 skb = dev_alloc_skb(nesvnic->max_frame_size);
1586 if (skb) {
1587 skb->dev = nesvnic->netdev;
1588
1589 bus_address = pci_map_single(nesdev->pcidev,
1590 skb->data, nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1591
1592 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_head];
1593 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] =
1594 cpu_to_le32(nesvnic->max_frame_size);
1595 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
1596 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] =
1597 cpu_to_le32((u32)bus_address);
1598 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] =
1599 cpu_to_le32((u32)((u64)bus_address >> 32));
1600 nesnic->rx_skb[nesnic->rq_head] = skb;
1601 nesnic->rq_head++;
1602 nesnic->rq_head &= nesnic->rq_size - 1;
1603 atomic_dec(&nesvnic->rx_skbs_needed);
1604 barrier();
1605 if (++rx_wqes_posted == 255) {
1606 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1607 rx_wqes_posted = 0;
1608 }
1609 } else {
1610 spin_lock_irqsave(&nesnic->rq_lock, flags);
1611 if (((nesnic->rq_size-1) == atomic_read(&nesvnic->rx_skbs_needed)) &&
1612 (atomic_read(&nesvnic->rx_skb_timer_running) == 0)) {
1613 atomic_set(&nesvnic->rx_skb_timer_running, 1);
1614 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1615 nesvnic->rq_wqes_timer.expires = jiffies + (HZ/2); /* 1/2 second */
1616 add_timer(&nesvnic->rq_wqes_timer);
1617 } else
1618 spin_unlock_irqrestore(&nesnic->rq_lock, flags);
1619 break;
1620 }
1621 } while (atomic_read(&nesvnic->rx_skbs_needed));
1622 barrier();
1623 if (rx_wqes_posted)
1624 nes_write32(nesdev->regs+NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesnic->qp_id);
1625 nesnic->replenishing_rq = 0;
1626}
1627
1628
1629/**
1630 * nes_rq_wqes_timeout
1631 */
1632static void nes_rq_wqes_timeout(unsigned long parm)
1633{
1634 struct nes_vnic *nesvnic = (struct nes_vnic *)parm;
33718363 1635 printk("%s: Timer fired.\n", __func__);
3c2d774c
GS		 1636 atomic_set(&nesvnic->rx_skb_timer_running, 0);
1637 if (atomic_read(&nesvnic->rx_skbs_needed))
1638 nes_replenish_nic_rq(nesvnic);
1639}
1640
1641
37dab411
FL		 1642static int nes_lro_get_skb_hdr(struct sk_buff *skb, void **iphdr,
1643 void **tcph, u64 *hdr_flags, void *priv)
1644{
1645 unsigned int ip_len;
1646 struct iphdr *iph;
1647 skb_reset_network_header(skb);
1648 iph = ip_hdr(skb);
1649 if (iph->protocol != IPPROTO_TCP)
1650 return -1;
1651 ip_len = ip_hdrlen(skb);
1652 skb_set_transport_header(skb, ip_len);
1653 *tcph = tcp_hdr(skb);
1654
1655 *hdr_flags = LRO_IPV4 | LRO_TCP;
1656 *iphdr = iph;
1657 return 0;
1658}
1659
1660
3c2d774c
GS		 1661/**
1662 * nes_init_nic_qp
1663 */
1664int nes_init_nic_qp(struct nes_device *nesdev, struct net_device *netdev)
1665{
1666 struct nes_hw_cqp_wqe *cqp_wqe;
1667 struct nes_hw_nic_sq_wqe *nic_sqe;
1668 struct nes_hw_nic_qp_context *nic_context;
1669 struct sk_buff *skb;
1670 struct nes_hw_nic_rq_wqe *nic_rqe;
1671 struct nes_vnic *nesvnic = netdev_priv(netdev);
1672 unsigned long flags;
1673 void *vmem;
1674 dma_addr_t pmem;
1675 u64 u64temp;
1676 int ret;
1677 u32 cqp_head;
1678 u32 counter;
1679 u32 wqe_count;
1680 u8 jumbomode=0;
1681
1682 /* Allocate fragment, SQ, RQ, and CQ; Reuse CEQ based on the PCI function */
1683 nesvnic->nic_mem_size = 256 +
1684 (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag)) +
1685 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe)) +
1686 (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe)) +
1687 (NES_NIC_WQ_SIZE * 2 * sizeof(struct nes_hw_nic_cqe)) +
1688 sizeof(struct nes_hw_nic_qp_context);
1689
1690 nesvnic->nic_vbase = pci_alloc_consistent(nesdev->pcidev, nesvnic->nic_mem_size,
1691 &nesvnic->nic_pbase);
1692 if (!nesvnic->nic_vbase) {
1693 nes_debug(NES_DBG_INIT, "Unable to allocate memory for NIC host descriptor rings\n");
1694 return -ENOMEM;
1695 }
1696 memset(nesvnic->nic_vbase, 0, nesvnic->nic_mem_size);
1697 nes_debug(NES_DBG_INIT, "Allocated NIC QP structures at %p (phys = %016lX), size = %u.\n",
1698 nesvnic->nic_vbase, (unsigned long)nesvnic->nic_pbase, nesvnic->nic_mem_size);
1699
1700 vmem = (void *)(((unsigned long)nesvnic->nic_vbase + (256 - 1)) &
1701 ~(unsigned long)(256 - 1));
1702 pmem = (dma_addr_t)(((unsigned long long)nesvnic->nic_pbase + (256 - 1)) &
1703 ~(unsigned long long)(256 - 1));
1704
1705 /* Setup the first Fragment buffers */
1706 nesvnic->nic.first_frag_vbase = vmem;
1707
1708 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1709 nesvnic->nic.frag_paddr[counter] = pmem;
1710 pmem += sizeof(struct nes_first_frag);
1711 }
1712
1713 /* setup the SQ */
1714 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_first_frag));
1715
1716 nesvnic->nic.sq_vbase = (void *)vmem;
1717 nesvnic->nic.sq_pbase = pmem;
1718 nesvnic->nic.sq_head = 0;
1719 nesvnic->nic.sq_tail = 0;
1720 nesvnic->nic.sq_size = NES_NIC_WQ_SIZE;
1721 for (counter = 0; counter < NES_NIC_WQ_SIZE; counter++) {
1722 nic_sqe = &nesvnic->nic.sq_vbase[counter];
1723 nic_sqe->wqe_words[NES_NIC_SQ_WQE_MISC_IDX] =
1724 cpu_to_le32(NES_NIC_SQ_WQE_DISABLE_CHKSUM |
1725 NES_NIC_SQ_WQE_COMPLETION);
1726 nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX] =
1727 cpu_to_le32((u32)NES_FIRST_FRAG_SIZE << 16);
1728 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX] =
1729 cpu_to_le32((u32)nesvnic->nic.frag_paddr[counter]);
1730 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX] =
1731 cpu_to_le32((u32)((u64)nesvnic->nic.frag_paddr[counter] >> 32));
1732 }
1733
1734 nesvnic->get_cqp_request = nes_get_cqp_request;
1735 nesvnic->post_cqp_request = nes_post_cqp_request;
1736 nesvnic->mcrq_mcast_filter = NULL;
1737
3c2d774c
GS		 1738 spin_lock_init(&nesvnic->nic.rq_lock);
1739
1740 /* setup the RQ */
1741 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1742 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_sq_wqe));
1743
1744
1745 nesvnic->nic.rq_vbase = vmem;
1746 nesvnic->nic.rq_pbase = pmem;
1747 nesvnic->nic.rq_head = 0;
1748 nesvnic->nic.rq_tail = 0;
1749 nesvnic->nic.rq_size = NES_NIC_WQ_SIZE;
1750
1751 /* setup the CQ */
1752 vmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1753 pmem += (NES_NIC_WQ_SIZE * sizeof(struct nes_hw_nic_rq_wqe));
1754
1755 if (nesdev->nesadapter->netdev_count > 2)
1756 nesvnic->mcrq_qp_id = nesvnic->nic_index + 32;
1757 else
1758 nesvnic->mcrq_qp_id = nesvnic->nic.qp_id + 4;
1759
1760 nesvnic->nic_cq.cq_vbase = vmem;
1761 nesvnic->nic_cq.cq_pbase = pmem;
1762 nesvnic->nic_cq.cq_head = 0;
1763 nesvnic->nic_cq.cq_size = NES_NIC_WQ_SIZE * 2;
1764
1765 nesvnic->nic_cq.ce_handler = nes_nic_napi_ce_handler;
1766
1767 /* Send CreateCQ request to CQP */
1768 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1769 cqp_head = nesdev->cqp.sq_head;
1770
1771 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1772 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1773
1774 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
1775 NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
1776 ((u32)nesvnic->nic_cq.cq_size << 16));
1777 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(
1778 nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16));
1779 u64temp = (u64)nesvnic->nic_cq.cq_pbase;
1780 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
1781 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
1782 u64temp = (unsigned long)&nesvnic->nic_cq;
1783 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp >> 1));
1784 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
1785 cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
1786 cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
1787 if (++cqp_head >= nesdev->cqp.sq_size)
1788 cqp_head = 0;
1789 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1790 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1791
1792 /* Send CreateQP request to CQP */
1793 nic_context = (void *)(&nesvnic->nic_cq.cq_vbase[nesvnic->nic_cq.cq_size]);
1794 nic_context->context_words[NES_NIC_CTX_MISC_IDX] =
1795 cpu_to_le32((u32)NES_NIC_CTX_SIZE |
1796 ((u32)PCI_FUNC(nesdev->pcidev->devfn) << 12));
1797 nes_debug(NES_DBG_INIT, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
1798 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE),
1799 nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE));
1800 if (nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE) != 0) {
1801 nic_context->context_words[NES_NIC_CTX_MISC_IDX] |= cpu_to_le32(NES_NIC_BACK_STORE);
1802 }
1803
1804 u64temp = (u64)nesvnic->nic.sq_pbase;
7495ab68 1805 nic_context->context_words[NES_NIC_CTX_SQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
3c2d774c
GS		 1806 nic_context->context_words[NES_NIC_CTX_SQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1807 u64temp = (u64)nesvnic->nic.rq_pbase;
7495ab68 1808 nic_context->context_words[NES_NIC_CTX_RQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
3c2d774c
GS		 1809 nic_context->context_words[NES_NIC_CTX_RQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
1810
1811 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_QP |
1812 NES_CQP_QP_TYPE_NIC);
1813 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesvnic->nic.qp_id);
1814 u64temp = (u64)nesvnic->nic_cq.cq_pbase +
1815 (nesvnic->nic_cq.cq_size * sizeof(struct nes_hw_nic_cqe));
1816 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
1817
1818 if (++cqp_head >= nesdev->cqp.sq_size)
1819 cqp_head = 0;
1820 nesdev->cqp.sq_head = cqp_head;
1821
1822 barrier();
1823
1824 /* Ring doorbell (2 WQEs) */
1825 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
1826
1827 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
1828 nes_debug(NES_DBG_INIT, "Waiting for create NIC QP%u to complete.\n",
1829 nesvnic->nic.qp_id);
1830
1831 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
1832 NES_EVENT_TIMEOUT);
1833 nes_debug(NES_DBG_INIT, "Create NIC QP%u completed, wait_event_timeout ret = %u.\n",
1834 nesvnic->nic.qp_id, ret);
1835 if (!ret) {
1836 nes_debug(NES_DBG_INIT, "NIC QP%u create timeout expired\n", nesvnic->nic.qp_id);
1837 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
1838 nesvnic->nic_pbase);
1839 return -EIO;
1840 }
1841
1842 /* Populate the RQ */
1843 for (counter = 0; counter < (NES_NIC_WQ_SIZE - 1); counter++) {
1844 skb = dev_alloc_skb(nesvnic->max_frame_size);
1845 if (!skb) {
1846 nes_debug(NES_DBG_INIT, "%s: out of memory for receive skb\n", netdev->name);
1847
1848 nes_destroy_nic_qp(nesvnic);
1849 return -ENOMEM;
1850 }
1851
1852 skb->dev = netdev;
1853
1854 pmem = pci_map_single(nesdev->pcidev, skb->data,
1855 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1856
1857 nic_rqe = &nesvnic->nic.rq_vbase[counter];
1858 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] = cpu_to_le32(nesvnic->max_frame_size);
1859 nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
7495ab68 1860 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] = cpu_to_le32((u32)pmem);
3c2d774c
GS		 1861 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] = cpu_to_le32((u32)((u64)pmem >> 32));
1862 nesvnic->nic.rx_skb[counter] = skb;
1863 }
1864
1865 wqe_count = NES_NIC_WQ_SIZE - 1;
1866 nesvnic->nic.rq_head = wqe_count;
1867 barrier();
1868 do {
1869 counter = min(wqe_count, ((u32)255));
1870 wqe_count -= counter;
1871 nes_write32(nesdev->regs+NES_WQE_ALLOC, (counter << 24) | nesvnic->nic.qp_id);
1872 } while (wqe_count);
1873 init_timer(&nesvnic->rq_wqes_timer);
1874 nesvnic->rq_wqes_timer.function = nes_rq_wqes_timeout;
1875 nesvnic->rq_wqes_timer.data = (unsigned long)nesvnic;
1876 nes_debug(NES_DBG_INIT, "NAPI support Enabled\n");
3c2d774c
GS		 1877 if (nesdev->nesadapter->et_use_adaptive_rx_coalesce)
1878 {
1879 nes_nic_init_timer(nesdev);
1880 if (netdev->mtu > 1500)
1881 jumbomode = 1;
37dab411 1882 nes_nic_init_timer_defaults(nesdev, jumbomode);
3c2d774c 1883 }
dd37818d 1884 nesvnic->lro_mgr.max_aggr = nes_lro_max_aggr;
7495ab68
GS		 1885 nesvnic->lro_mgr.max_desc = NES_MAX_LRO_DESCRIPTORS;
1886 nesvnic->lro_mgr.lro_arr = nesvnic->lro_desc;
37dab411 1887 nesvnic->lro_mgr.get_skb_header = nes_lro_get_skb_hdr;
7495ab68
GS		 1888 nesvnic->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1889 nesvnic->lro_mgr.dev = netdev;
1890 nesvnic->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
37dab411 1891 nesvnic->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
3c2d774c
GS		 1892 return 0;
1893}
1894
1895
1896/**
1897 * nes_destroy_nic_qp
1898 */
1899void nes_destroy_nic_qp(struct nes_vnic *nesvnic)
1900{
7a8d1407
BS		 1901 u64 u64temp;
1902 dma_addr_t bus_address;
3c2d774c
GS		 1903 struct nes_device *nesdev = nesvnic->nesdev;
1904 struct nes_hw_cqp_wqe *cqp_wqe;
7a8d1407 1905 struct nes_hw_nic_sq_wqe *nic_sqe;
3c2d774c 1906 struct nes_hw_nic_rq_wqe *nic_rqe;
7a8d1407
BS		 1907 __le16 *wqe_fragment_length;
1908 u16 wqe_fragment_index;
3c2d774c
GS		 1909 u64 wqe_frag;
1910 u32 cqp_head;
9f29006a 1911 u32 wqm_cfg0;
3c2d774c
GS		 1912 unsigned long flags;
1913 int ret;
1914
9f29006a
CT		 1915 /* clear wqe stall before destroying NIC QP */
1916 wqm_cfg0 = nes_read_indexed(nesdev, NES_IDX_WQM_CONFIG0);
1917 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0 & 0xFFFF7FFF);
1918
3c2d774c
GS		 1919 /* Free remaining NIC receive buffers */
1920 while (nesvnic->nic.rq_head != nesvnic->nic.rq_tail) {
7495ab68 1921 nic_rqe = &nesvnic->nic.rq_vbase[nesvnic->nic.rq_tail];
7a8d1407
BS		 1922 wqe_frag = (u64)le32_to_cpu(
1923 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX]);
1924 wqe_frag |= ((u64)le32_to_cpu(
1925 nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX]))<<32;
3c2d774c
GS		 1926 pci_unmap_single(nesdev->pcidev, (dma_addr_t)wqe_frag,
1927 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
1928 dev_kfree_skb(nesvnic->nic.rx_skb[nesvnic->nic.rq_tail++]);
1929 nesvnic->nic.rq_tail &= (nesvnic->nic.rq_size - 1);
1930 }
1931
7a8d1407
BS		 1932 /* Free remaining NIC transmit buffers */
1933 while (nesvnic->nic.sq_head != nesvnic->nic.sq_tail) {
1934 nic_sqe = &nesvnic->nic.sq_vbase[nesvnic->nic.sq_tail];
1935 wqe_fragment_index = 1;
1936 wqe_fragment_length = (__le16 *)
1937 &nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
1938 /* bump past the vlan tag */
1939 wqe_fragment_length++;
1940 if (le16_to_cpu(wqe_fragment_length[wqe_fragment_index]) != 0) {
1941 u64temp = (u64)le32_to_cpu(
1942 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX+
1943 wqe_fragment_index*2]);
1944 u64temp += ((u64)le32_to_cpu(
1945 nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
1946 + wqe_fragment_index*2]))<<32;
1947 bus_address = (dma_addr_t)u64temp;
1948 if (test_and_clear_bit(nesvnic->nic.sq_tail,
1949 nesvnic->nic.first_frag_overflow)) {
1950 pci_unmap_single(nesdev->pcidev,
1951 bus_address,
1952 le16_to_cpu(wqe_fragment_length[
1953 wqe_fragment_index++]),
1954 PCI_DMA_TODEVICE);
1955 }
1956 for (; wqe_fragment_index < 5; wqe_fragment_index++) {
1957 if (wqe_fragment_length[wqe_fragment_index]) {
1958 u64temp = le32_to_cpu(
1959 nic_sqe->wqe_words[
1960 NES_NIC_SQ_WQE_FRAG0_LOW_IDX+
1961 wqe_fragment_index*2]);
1962 u64temp += ((u64)le32_to_cpu(
1963 nic_sqe->wqe_words[
1964 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX+
1965 wqe_fragment_index*2]))<<32;
1966 bus_address = (dma_addr_t)u64temp;
1967 pci_unmap_page(nesdev->pcidev,
1968 bus_address,
1969 le16_to_cpu(
1970 wqe_fragment_length[
1971 wqe_fragment_index]),
1972 PCI_DMA_TODEVICE);
1973 } else
1974 break;
1975 }
1976 }
1977 if (nesvnic->nic.tx_skb[nesvnic->nic.sq_tail])
1978 dev_kfree_skb(
1979 nesvnic->nic.tx_skb[nesvnic->nic.sq_tail]);
1980
ea9f3bc6 1981 nesvnic->nic.sq_tail = (nesvnic->nic.sq_tail + 1)
7a8d1407
BS		 1982 & (nesvnic->nic.sq_size - 1);
1983 }
1984
3c2d774c
GS		 1985 spin_lock_irqsave(&nesdev->cqp.lock, flags);
1986
1987 /* Destroy NIC QP */
1988 cqp_head = nesdev->cqp.sq_head;
1989 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
1990 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
1991
1992 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
1993 (NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_NIC));
1994 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
1995 nesvnic->nic.qp_id);
1996
1997 if (++cqp_head >= nesdev->cqp.sq_size)
1998 cqp_head = 0;
1999
2000 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
2001
2002 /* Destroy NIC CQ */
2003 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
2004 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
2005 (NES_CQP_DESTROY_CQ | ((u32)nesvnic->nic_cq.cq_size << 16)));
2006 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
2007 (nesvnic->nic_cq.cq_number | ((u32)nesdev->nic_ceq_index << 16)));
2008
2009 if (++cqp_head >= nesdev->cqp.sq_size)
2010 cqp_head = 0;
2011
2012 nesdev->cqp.sq_head = cqp_head;
2013 barrier();
2014
2015 /* Ring doorbell (2 WQEs) */
2016 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
2017
2018 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
2019 nes_debug(NES_DBG_SHUTDOWN, "Waiting for CQP, cqp_head=%u, cqp.sq_head=%u,"
2020 " cqp.sq_tail=%u, cqp.sq_size=%u\n",
2021 cqp_head, nesdev->cqp.sq_head,
2022 nesdev->cqp.sq_tail, nesdev->cqp.sq_size);
2023
2024 ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
2025 NES_EVENT_TIMEOUT);
2026
2027 nes_debug(NES_DBG_SHUTDOWN, "Destroy NIC QP returned, wait_event_timeout ret = %u, cqp_head=%u,"
2028 " cqp.sq_head=%u, cqp.sq_tail=%u\n",
2029 ret, cqp_head, nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
2030 if (!ret) {
2031 nes_debug(NES_DBG_SHUTDOWN, "NIC QP%u destroy timeout expired\n",
2032 nesvnic->nic.qp_id);
2033 }
2034
2035 pci_free_consistent(nesdev->pcidev, nesvnic->nic_mem_size, nesvnic->nic_vbase,
2036 nesvnic->nic_pbase);
9f29006a
CT		 2037
2038 /* restore old wqm_cfg0 value */
2039 nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG0, wqm_cfg0);
3c2d774c
GS		 2040}
2041
2042/**
2043 * nes_napi_isr
2044 */
2045int nes_napi_isr(struct nes_device *nesdev)
2046{
2047 struct nes_adapter *nesadapter = nesdev->nesadapter;
2048 u32 int_stat;
2049
2050 if (nesdev->napi_isr_ran) {
2051 /* interrupt status has already been read in ISR */
2052 int_stat = nesdev->int_stat;
2053 } else {
2054 int_stat = nes_read32(nesdev->regs + NES_INT_STAT);
2055 nesdev->int_stat = int_stat;
2056 nesdev->napi_isr_ran = 1;
2057 }
2058
2059 int_stat &= nesdev->int_req;
2060 /* iff NIC, process here, else wait for DPC */
2061 if ((int_stat) && ((int_stat & 0x0000ff00) == int_stat)) {
2062 nesdev->napi_isr_ran = 0;
7495ab68
GS		 2063 nes_write32(nesdev->regs + NES_INT_STAT,
2064 (int_stat &
2065 ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0 | NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3)));
3c2d774c
GS		 2066
2067 /* Process the CEQs */
2068 nes_process_ceq(nesdev, &nesdev->nesadapter->ceq[nesdev->nic_ceq_index]);
2069
2070 if (unlikely((((nesadapter->et_rx_coalesce_usecs_irq) &&
7495ab68
GS		 2071 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
2072 ((nesadapter->et_use_adaptive_rx_coalesce) &&
2073 (nesdev->deepcq_count > nesadapter->et_pkt_rate_low))))) {
3c2d774c
GS		 2074 if ((nesdev->int_req & NES_INT_TIMER) == 0) {
2075 /* Enable Periodic timer interrupts */
2076 nesdev->int_req |= NES_INT_TIMER;
2077 /* ack any pending periodic timer interrupts so we don't get an immediate interrupt */
2078 /* TODO: need to also ack other unused periodic timer values, get from nesadapter */
2079 nes_write32(nesdev->regs+NES_TIMER_STAT,
2080 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2081 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
2082 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
2083 }
2084
2085 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2086 {
2087 nes_nic_init_timer(nesdev);
2088 }
2089 /* Enable interrupts, except CEQs */
2090 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2091 } else {
2092 /* Enable interrupts, make sure timer is off */
2093 nesdev->int_req &= ~NES_INT_TIMER;
2094 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2095 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
3c2d774c
GS		 2096 }
2097 nesdev->deepcq_count = 0;
2098 return 1;
2099 } else {
2100 return 0;
2101 }
2102}
2103
9d156947
CT		 2104static void process_critical_error(struct nes_device *nesdev)
2105{
2106 u32 debug_error;
2107 u32 nes_idx_debug_error_masks0 = 0;
2108 u16 error_module = 0;
2109
2110 debug_error = nes_read_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS);
2111 printk(KERN_ERR PFX "Critical Error reported by device!!! 0x%02X\n",
2112 (u16)debug_error);
2113 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_CONTROL_STATUS,
2114 0x01010000 | (debug_error & 0x0000ffff));
2115 if (crit_err_count++ > 10)
2116 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS1, 1 << 0x17);
e2f5e733 2117 error_module = (u16) (debug_error & 0x1F00) >> 8;
9d156947
CT		 2118 if (++nesdev->nesadapter->crit_error_count[error_module-1] >=
2119 nes_max_critical_error_count) {
2120 printk(KERN_ERR PFX "Masking off critical error for module "
2121 "0x%02X\n", (u16)error_module);
2122 nes_idx_debug_error_masks0 = nes_read_indexed(nesdev,
2123 NES_IDX_DEBUG_ERROR_MASKS0);
2124 nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS0,
2125 nes_idx_debug_error_masks0 | (1 << error_module));
2126 }
2127}
3c2d774c
GS		 2128/**
2129 * nes_dpc
2130 */
2131void nes_dpc(unsigned long param)
2132{
2133 struct nes_device *nesdev = (struct nes_device *)param;
2134 struct nes_adapter *nesadapter = nesdev->nesadapter;
2135 u32 counter;
2136 u32 loop_counter = 0;
2137 u32 int_status_bit;
2138 u32 int_stat;
2139 u32 timer_stat;
2140 u32 temp_int_stat;
2141 u32 intf_int_stat;
3c2d774c
GS		 2142 u32 processed_intf_int = 0;
2143 u16 processed_timer_int = 0;
2144 u16 completion_ints = 0;
2145 u16 timer_ints = 0;
2146
2147 /* nes_debug(NES_DBG_ISR, "\n"); */
2148
2149 do {
2150 timer_stat = 0;
2151 if (nesdev->napi_isr_ran) {
2152 nesdev->napi_isr_ran = 0;
2153 int_stat = nesdev->int_stat;
2154 } else
2155 int_stat = nes_read32(nesdev->regs+NES_INT_STAT);
2156 if (processed_intf_int != 0)
2157 int_stat &= nesdev->int_req & ~NES_INT_INTF;
2158 else
2159 int_stat &= nesdev->int_req;
2160 if (processed_timer_int == 0) {
2161 processed_timer_int = 1;
2162 if (int_stat & NES_INT_TIMER) {
2163 timer_stat = nes_read32(nesdev->regs + NES_TIMER_STAT);
2164 if ((timer_stat & nesdev->timer_int_req) == 0) {
2165 int_stat &= ~NES_INT_TIMER;
2166 }
2167 }
2168 } else {
2169 int_stat &= ~NES_INT_TIMER;
2170 }
2171
2172 if (int_stat) {
7495ab68
GS		 2173 if (int_stat & ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0|
2174 NES_INT_MAC1|NES_INT_MAC2 | NES_INT_MAC3)) {
3c2d774c
GS		 2175 /* Ack the interrupts */
2176 nes_write32(nesdev->regs+NES_INT_STAT,
7495ab68
GS		 2177 (int_stat & ~(NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0|
2178 NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3)));
3c2d774c
GS		 2179 }
2180
2181 temp_int_stat = int_stat;
2182 for (counter = 0, int_status_bit = 1; counter < 16; counter++) {
2183 if (int_stat & int_status_bit) {
2184 nes_process_ceq(nesdev, &nesadapter->ceq[counter]);
2185 temp_int_stat &= ~int_status_bit;
2186 completion_ints = 1;
2187 }
2188 if (!(temp_int_stat & 0x0000ffff))
2189 break;
2190 int_status_bit <<= 1;
2191 }
2192
2193 /* Process the AEQ for this pci function */
2194 int_status_bit = 1 << (16 + PCI_FUNC(nesdev->pcidev->devfn));
2195 if (int_stat & int_status_bit) {
2196 nes_process_aeq(nesdev, &nesadapter->aeq[PCI_FUNC(nesdev->pcidev->devfn)]);
2197 }
2198
2199 /* Process the MAC interrupt for this pci function */
2200 int_status_bit = 1 << (24 + nesdev->mac_index);
2201 if (int_stat & int_status_bit) {
2202 nes_process_mac_intr(nesdev, nesdev->mac_index);
2203 }
2204
2205 if (int_stat & NES_INT_TIMER) {
2206 if (timer_stat & nesdev->timer_int_req) {
2207 nes_write32(nesdev->regs + NES_TIMER_STAT,
2208 (timer_stat & nesdev->timer_int_req) |
2209 ~(nesdev->nesadapter->timer_int_req));
2210 timer_ints = 1;
2211 }
2212 }
2213
2214 if (int_stat & NES_INT_INTF) {
2215 processed_intf_int = 1;
2216 intf_int_stat = nes_read32(nesdev->regs+NES_INTF_INT_STAT);
2217 intf_int_stat &= nesdev->intf_int_req;
2218 if (NES_INTF_INT_CRITERR & intf_int_stat) {
9d156947 2219 process_critical_error(nesdev);
3c2d774c
GS		 2220 }
2221 if (NES_INTF_INT_PCIERR & intf_int_stat) {
2222 printk(KERN_ERR PFX "PCI Error reported by device!!!\n");
2223 BUG();
2224 }
2225 if (NES_INTF_INT_AEQ_OFLOW & intf_int_stat) {
2226 printk(KERN_ERR PFX "AEQ Overflow reported by device!!!\n");
2227 BUG();
2228 }
2229 nes_write32(nesdev->regs+NES_INTF_INT_STAT, intf_int_stat);
2230 }
2231
2232 if (int_stat & NES_INT_TSW) {
2233 }
2234 }
2235 /* Don't use the interface interrupt bit stay in loop */
7495ab68
GS		 2236 int_stat &= ~NES_INT_INTF | NES_INT_TIMER | NES_INT_MAC0 |
2237 NES_INT_MAC1 | NES_INT_MAC2 | NES_INT_MAC3;
3c2d774c
GS		 2238 } while ((int_stat != 0) && (loop_counter++ < MAX_DPC_ITERATIONS));
2239
2240 if (timer_ints == 1) {
2241 if ((nesadapter->et_rx_coalesce_usecs_irq) || (nesadapter->et_use_adaptive_rx_coalesce)) {
2242 if (completion_ints == 0) {
2243 nesdev->timer_only_int_count++;
2244 if (nesdev->timer_only_int_count>=nesadapter->timer_int_limit) {
2245 nesdev->timer_only_int_count = 0;
2246 nesdev->int_req &= ~NES_INT_TIMER;
2247 nes_write32(nesdev->regs + NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
7495ab68 2248 nes_write32(nesdev->regs + NES_INT_MASK, ~nesdev->int_req);
3c2d774c 2249 } else {
7495ab68 2250 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
3c2d774c
GS		 2251 }
2252 } else {
2253 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2254 {
2255 nes_nic_init_timer(nesdev);
2256 }
2257 nesdev->timer_only_int_count = 0;
7495ab68 2258 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
3c2d774c
GS		 2259 }
2260 } else {
2261 nesdev->timer_only_int_count = 0;
2262 nesdev->int_req &= ~NES_INT_TIMER;
2263 nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
2264 nes_write32(nesdev->regs+NES_TIMER_STAT,
2265 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2266 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2267 }
2268 } else {
2269 if ( (completion_ints == 1) &&
2270 (((nesadapter->et_rx_coalesce_usecs_irq) &&
2271 (!nesadapter->et_use_adaptive_rx_coalesce)) ||
2272 ((nesdev->deepcq_count > nesadapter->et_pkt_rate_low) &&
2273 (nesadapter->et_use_adaptive_rx_coalesce) )) ) {
2274 /* nes_debug(NES_DBG_ISR, "Enabling periodic timer interrupt.\n" ); */
2275 nesdev->timer_only_int_count = 0;
2276 nesdev->int_req |= NES_INT_TIMER;
2277 nes_write32(nesdev->regs+NES_TIMER_STAT,
2278 nesdev->timer_int_req | ~(nesdev->nesadapter->timer_int_req));
2279 nes_write32(nesdev->regs+NES_INTF_INT_MASK,
2280 ~(nesdev->intf_int_req | NES_INTF_PERIODIC_TIMER));
2281 nes_write32(nesdev->regs+NES_INT_MASK, 0x0000ffff | (~nesdev->int_req));
2282 } else {
2283 nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
2284 }
2285 }
2286 nesdev->deepcq_count = 0;
2287}
2288
2289
2290/**
2291 * nes_process_ceq
2292 */
1a855fbf 2293static void nes_process_ceq(struct nes_device *nesdev, struct nes_hw_ceq *ceq)
3c2d774c
GS		 2294{
2295 u64 u64temp;
2296 struct nes_hw_cq *cq;
2297 u32 head;
2298 u32 ceq_size;
2299
2300 /* nes_debug(NES_DBG_CQ, "\n"); */
2301 head = ceq->ceq_head;
2302 ceq_size = ceq->ceq_size;
2303
2304 do {
2305 if (le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX]) &
2306 NES_CEQE_VALID) {
7495ab68 2307 u64temp = (((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX]))) << 32) |
3c2d774c
GS		 2308 ((u64)(le32_to_cpu(ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_LOW_IDX])));
2309 u64temp <<= 1;
2310 cq = *((struct nes_hw_cq **)&u64temp);
2311 /* nes_debug(NES_DBG_CQ, "pCQ = %p\n", cq); */
2312 barrier();
2313 ceq->ceq_vbase[head].ceqe_words[NES_CEQE_CQ_CTX_HIGH_IDX] = 0;
2314
2315 /* call the event handler */
2316 cq->ce_handler(nesdev, cq);
2317
2318 if (++head >= ceq_size)
2319 head = 0;
2320 } else {
2321 break;
2322 }
2323
2324 } while (1);
2325
2326 ceq->ceq_head = head;
2327}
2328
2329
2330/**
2331 * nes_process_aeq
2332 */
1a855fbf 2333static void nes_process_aeq(struct nes_device *nesdev, struct nes_hw_aeq *aeq)
3c2d774c 2334{
7495ab68 2335 /* u64 u64temp; */
3c2d774c
GS		 2336 u32 head;
2337 u32 aeq_size;
2338 u32 aeqe_misc;
2339 u32 aeqe_cq_id;
2340 struct nes_hw_aeqe volatile *aeqe;
2341
2342 head = aeq->aeq_head;
2343 aeq_size = aeq->aeq_size;
2344
2345 do {
2346 aeqe = &aeq->aeq_vbase[head];
2347 if ((le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]) & NES_AEQE_VALID) == 0)
2348 break;
2349 aeqe_misc = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
2350 aeqe_cq_id = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]);
2351 if (aeqe_misc & (NES_AEQE_QP|NES_AEQE_CQ)) {
2352 if (aeqe_cq_id >= NES_FIRST_QPN) {
2353 /* dealing with an accelerated QP related AE */
7495ab68
GS		 2354 /*
2355 * u64temp = (((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX]))) << 32) |
2356 * ((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX])));
2357 */
3c2d774c
GS		 2358 nes_process_iwarp_aeqe(nesdev, (struct nes_hw_aeqe *)aeqe);
2359 } else {
2360 /* TODO: dealing with a CQP related AE */
2361 nes_debug(NES_DBG_AEQ, "Processing CQP related AE, misc = 0x%04X\n",
2362 (u16)(aeqe_misc >> 16));
2363 }
2364 }
2365
2366 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = 0;
2367
2368 if (++head >= aeq_size)
2369 head = 0;
fd87778c
DW		 2370
2371 nes_write32(nesdev->regs + NES_AEQ_ALLOC, 1 << 16);
3c2d774c
GS		 2372 }
2373 while (1);
2374 aeq->aeq_head = head;
2375}
2376
2377static void nes_reset_link(struct nes_device *nesdev, u32 mac_index)
2378{
2379 struct nes_adapter *nesadapter = nesdev->nesadapter;
2380 u32 reset_value;
2381 u32 i=0;
2382 u32 u32temp;
2383
2384 if (nesadapter->hw_rev == NE020_REV) {
2385 return;
2386 }
2387 mh_detected++;
2388
2389 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
2390
2391 if ((mac_index == 0) || ((mac_index == 1) && (nesadapter->OneG_Mode)))
2392 reset_value |= 0x0000001d;
2393 else
2394 reset_value |= 0x0000002d;
2395
2396 if (4 <= (nesadapter->link_interrupt_count[mac_index] / ((u16)NES_MAX_LINK_INTERRUPTS))) {
2397 if ((!nesadapter->OneG_Mode) && (nesadapter->port_count == 2)) {
2398 nesadapter->link_interrupt_count[0] = 0;
2399 nesadapter->link_interrupt_count[1] = 0;
2400 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2401 if (0x00000040 & u32temp)
2402 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2403 else
2404 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2405
2406 reset_value |= 0x0000003d;
2407 }
2408 nesadapter->link_interrupt_count[mac_index] = 0;
2409 }
2410
2411 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2412
2413 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
2414 & 0x00000040) != 0x00000040) && (i++ < 5000));
2415
2416 if (0x0000003d == (reset_value & 0x0000003d)) {
2417 u32 pcs_control_status0, pcs_control_status1;
2418
2419 for (i = 0; i < 10; i++) {
2420 pcs_control_status0 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0);
2421 pcs_control_status1 = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
2422 if (((0x0F000000 == (pcs_control_status0 & 0x0F000000))
2423 && (pcs_control_status0 & 0x00100000))
2424 || ((0x0F000000 == (pcs_control_status1 & 0x0F000000))
2425 && (pcs_control_status1 & 0x00100000)))
2426 continue;
2427 else
2428 break;
2429 }
2430 if (10 == i) {
2431 u32temp = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
2432 if (0x00000040 & u32temp)
2433 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088);
2434 else
2435 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F0C8);
2436
2437 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value);
2438
2439 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET)
2440 & 0x00000040) != 0x00000040) && (i++ < 5000));
2441 }
2442 }
2443}
2444
2445/**
2446 * nes_process_mac_intr
2447 */
1a855fbf 2448static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
3c2d774c
GS		 2449{
2450 unsigned long flags;
2451 u32 pcs_control_status;
2452 struct nes_adapter *nesadapter = nesdev->nesadapter;
2453 struct nes_vnic *nesvnic;
2454 u32 mac_status;
2455 u32 mac_index = nesdev->mac_index;
2456 u32 u32temp;
2457 u16 phy_data;
2458 u16 temp_phy_data;
0e1de5d6
ES		 2459 u32 pcs_val = 0x0f0f0000;
2460 u32 pcs_mask = 0x0f1f0000;
a4849fc1 2461 u32 cdr_ctrl;
3c2d774c
GS		 2462
2463 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2464 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) {
2465 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2466 return;
2467 }
2468 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_INTERRUPT;
3c2d774c
GS		 2469
2470 /* ack the MAC interrupt */
2471 mac_status = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200));
2472 /* Clear the interrupt */
2473 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (mac_index * 0x200), mac_status);
2474
2475 nes_debug(NES_DBG_PHY, "MAC%u interrupt status = 0x%X.\n", mac_number, mac_status);
2476
2477 if (mac_status & (NES_MAC_INT_LINK_STAT_CHG | NES_MAC_INT_XGMII_EXT)) {
2478 nesdev->link_status_interrupts++;
ce6e74f2 2479 if (0 == (++nesadapter->link_interrupt_count[mac_index] % ((u16)NES_MAX_LINK_INTERRUPTS)))
3c2d774c 2480 nes_reset_link(nesdev, mac_index);
ce6e74f2 2481
3c2d774c 2482 /* read the PHY interrupt status register */
fcb7ad31
CT		 2483 if ((nesadapter->OneG_Mode) &&
2484 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) {
3c2d774c
GS		 2485 do {
2486 nes_read_1G_phy_reg(nesdev, 0x1a,
2487 nesadapter->phy_index[mac_index], &phy_data);
2488 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1a = 0x%X.\n",
2489 nesadapter->phy_index[mac_index], phy_data);
2490 } while (phy_data&0x8000);
2491
2492 temp_phy_data = 0;
2493 do {
2494 nes_read_1G_phy_reg(nesdev, 0x11,
2495 nesadapter->phy_index[mac_index], &phy_data);
2496 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x11 = 0x%X.\n",
2497 nesadapter->phy_index[mac_index], phy_data);
2498 if (temp_phy_data == phy_data)
2499 break;
2500 temp_phy_data = phy_data;
2501 } while (1);
2502
2503 nes_read_1G_phy_reg(nesdev, 0x1e,
2504 nesadapter->phy_index[mac_index], &phy_data);
2505 nes_debug(NES_DBG_PHY, "Phy%d data from register 0x1e = 0x%X.\n",
2506 nesadapter->phy_index[mac_index], phy_data);
2507
2508 nes_read_1G_phy_reg(nesdev, 1,
2509 nesadapter->phy_index[mac_index], &phy_data);
2510 nes_debug(NES_DBG_PHY, "1G phy%u data from register 1 = 0x%X\n",
2511 nesadapter->phy_index[mac_index], phy_data);
2512
2513 if (temp_phy_data & 0x1000) {
2514 nes_debug(NES_DBG_PHY, "The Link is up according to the PHY\n");
2515 phy_data = 4;
2516 } else {
2517 nes_debug(NES_DBG_PHY, "The Link is down according to the PHY\n");
2518 }
2519 }
2520 nes_debug(NES_DBG_PHY, "Eth SERDES Common Status: 0=0x%08X, 1=0x%08X\n",
2521 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0),
2522 nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0+0x200));
0e1de5d6
ES		 2523
2524 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_PUMA_1G) {
2525 switch (mac_index) {
2526 case 1:
2527 case 3:
2528 pcs_control_status = nes_read_indexed(nesdev,
2529 NES_IDX_PHY_PCS_CONTROL_STATUS0 + 0x200);
2530 break;
2531 default:
2532 pcs_control_status = nes_read_indexed(nesdev,
2533 NES_IDX_PHY_PCS_CONTROL_STATUS0);
2534 break;
2535 }
2536 } else {
2537 pcs_control_status = nes_read_indexed(nesdev,
2538 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index & 1) * 0x200));
2539 pcs_control_status = nes_read_indexed(nesdev,
2540 NES_IDX_PHY_PCS_CONTROL_STATUS0 + ((mac_index & 1) * 0x200));
2541 }
2542
3c2d774c
GS		 2543 nes_debug(NES_DBG_PHY, "PCS PHY Control/Status%u: 0x%08X\n",
2544 mac_index, pcs_control_status);
0e1de5d6
ES		 2545 if ((nesadapter->OneG_Mode) &&
2546 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) {
3c2d774c
GS		 2547 u32temp = 0x01010000;
2548 if (nesadapter->port_count > 2) {
2549 u32temp |= 0x02020000;
2550 }
2551 if ((pcs_control_status & u32temp)!= u32temp) {
2552 phy_data = 0;
2553 nes_debug(NES_DBG_PHY, "PCS says the link is down\n");
2554 }
3c2d774c 2555 } else {
0e1de5d6 2556 switch (nesadapter->phy_type[mac_index]) {
0e1de5d6 2557 case NES_PHY_TYPE_ARGUS:
4303565d 2558 case NES_PHY_TYPE_SFP_D:
09124e19 2559 case NES_PHY_TYPE_KR:
0e1de5d6
ES		 2560 /* clear the alarms */
2561 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008);
2562 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001);
2563 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc002);
2564 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc005);
2565 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc006);
2566 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2567 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004);
2568 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005);
2569 /* check link status */
1b949324 2570 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
0e1de5d6 2571 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
0e1de5d6 2572
1b949324
CT		 2573 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2574 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2575 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2576 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2577
2578 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2579
0e1de5d6 2580 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
1b949324 2581 __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
0e1de5d6
ES		 2582 break;
2583
2584 case NES_PHY_TYPE_PUMA_1G:
2585 if (mac_index < 2)
2586 pcs_val = pcs_mask = 0x01010000;
2587 else
2588 pcs_val = pcs_mask = 0x02020000;
2589 /* fall through */
2590 default:
2591 phy_data = (pcs_val == (pcs_control_status & pcs_mask)) ? 0x4 : 0x0;
2592 break;
2593 }
3c2d774c
GS		 2594 }
2595
2596 if (phy_data & 0x0004) {
a4849fc1
CT		 2597 if (wide_ppm_offset &&
2598 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2599 (nesadapter->hw_rev != NE020_REV)) {
2600 cdr_ctrl = nes_read_indexed(nesdev,
2601 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2602 mac_index * 0x200);
2603 nes_write_indexed(nesdev,
2604 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2605 mac_index * 0x200,
2606 cdr_ctrl | 0x000F0000);
2607 }
3c2d774c
GS		 2608 nesadapter->mac_link_down[mac_index] = 0;
2609 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2610 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n",
2611 nesvnic->linkup);
2612 if (nesvnic->linkup == 0) {
0e1de5d6
ES		 2613 printk(PFX "The Link is now up for port %s, netdev %p.\n",
2614 nesvnic->netdev->name, nesvnic->netdev);
3c2d774c
GS		 2615 if (netif_queue_stopped(nesvnic->netdev))
2616 netif_start_queue(nesvnic->netdev);
2617 nesvnic->linkup = 1;
2618 netif_carrier_on(nesvnic->netdev);
ea623455
MS		 2619
2620 spin_lock(&nesvnic->port_ibevent_lock);
25a54a6b
MS		 2621 if (nesvnic->of_device_registered) {
2622 if (nesdev->iw_status == 0) {
2623 nesdev->iw_status = 1;
2624 nes_port_ibevent(nesvnic);
2625 }
ea623455
MS		 2626 }
2627 spin_unlock(&nesvnic->port_ibevent_lock);
3c2d774c
GS		 2628 }
2629 }
2630 } else {
a4849fc1
CT		 2631 if (wide_ppm_offset &&
2632 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2633 (nesadapter->hw_rev != NE020_REV)) {
2634 cdr_ctrl = nes_read_indexed(nesdev,
2635 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2636 mac_index * 0x200);
2637 nes_write_indexed(nesdev,
2638 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2639 mac_index * 0x200,
2640 cdr_ctrl & 0xFFF0FFFF);
2641 }
3c2d774c
GS		 2642 nesadapter->mac_link_down[mac_index] = 1;
2643 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2644 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n",
2645 nesvnic->linkup);
2646 if (nesvnic->linkup == 1) {
0e1de5d6
ES		 2647 printk(PFX "The Link is now down for port %s, netdev %p.\n",
2648 nesvnic->netdev->name, nesvnic->netdev);
3c2d774c
GS		 2649 if (!(netif_queue_stopped(nesvnic->netdev)))
2650 netif_stop_queue(nesvnic->netdev);
2651 nesvnic->linkup = 0;
2652 netif_carrier_off(nesvnic->netdev);
ea623455
MS		 2653
2654 spin_lock(&nesvnic->port_ibevent_lock);
25a54a6b
MS		 2655 if (nesvnic->of_device_registered) {
2656 if (nesdev->iw_status == 1) {
2657 nesdev->iw_status = 0;
2658 nes_port_ibevent(nesvnic);
2659 }
ea623455
MS		 2660 }
2661 spin_unlock(&nesvnic->port_ibevent_lock);
3c2d774c
GS		 2662 }
2663 }
2664 }
5f61b2c6
MS		 2665 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_SFP_D) {
2666 if (nesdev->link_recheck)
2667 cancel_delayed_work(&nesdev->work);
2668 nesdev->link_recheck = 1;
2669 schedule_delayed_work(&nesdev->work,
2670 NES_LINK_RECHECK_DELAY);
2671 }
3c2d774c
GS		 2672 }
2673
b17e0969
CT		 2674 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2675
3c2d774c
GS		 2676 nesadapter->mac_sw_state[mac_number] = NES_MAC_SW_IDLE;
2677}
2678
5f61b2c6
MS		 2679void nes_recheck_link_status(struct work_struct *work)
2680{
2681 unsigned long flags;
2682 struct nes_device *nesdev = container_of(work, struct nes_device, work.work);
2683 struct nes_adapter *nesadapter = nesdev->nesadapter;
2684 struct nes_vnic *nesvnic;
2685 u32 mac_index = nesdev->mac_index;
2686 u16 phy_data;
2687 u16 temp_phy_data;
2688
2689 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2690
2691 /* check link status */
2692 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2693 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2694
2695 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2696 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2697 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2698 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2699
2700 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2701
2702 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2703 __func__, phy_data,
2704 nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2705
2706 if (phy_data & 0x0004) {
2707 nesadapter->mac_link_down[mac_index] = 0;
2708 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2709 if (nesvnic->linkup == 0) {
2710 printk(PFX "The Link is now up for port %s, netdev %p.\n",
2711 nesvnic->netdev->name, nesvnic->netdev);
2712 if (netif_queue_stopped(nesvnic->netdev))
2713 netif_start_queue(nesvnic->netdev);
2714 nesvnic->linkup = 1;
2715 netif_carrier_on(nesvnic->netdev);
2716
2717 spin_lock(&nesvnic->port_ibevent_lock);
25a54a6b
MS		 2718 if (nesvnic->of_device_registered) {
2719 if (nesdev->iw_status == 0) {
2720 nesdev->iw_status = 1;
2721 nes_port_ibevent(nesvnic);
2722 }
5f61b2c6
MS		 2723 }
2724 spin_unlock(&nesvnic->port_ibevent_lock);
2725 }
2726 }
2727
2728 } else {
2729 nesadapter->mac_link_down[mac_index] = 1;
2730 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2731 if (nesvnic->linkup == 1) {
2732 printk(PFX "The Link is now down for port %s, netdev %p.\n",
2733 nesvnic->netdev->name, nesvnic->netdev);
2734 if (!(netif_queue_stopped(nesvnic->netdev)))
2735 netif_stop_queue(nesvnic->netdev);
2736 nesvnic->linkup = 0;
2737 netif_carrier_off(nesvnic->netdev);
2738
2739 spin_lock(&nesvnic->port_ibevent_lock);
25a54a6b
MS		 2740 if (nesvnic->of_device_registered) {
2741 if (nesdev->iw_status == 1) {
2742 nesdev->iw_status = 0;
2743 nes_port_ibevent(nesvnic);
2744 }
5f61b2c6
MS		 2745 }
2746 spin_unlock(&nesvnic->port_ibevent_lock);
2747 }
2748 }
2749 }
2750 if (nesdev->link_recheck++ < NES_LINK_RECHECK_MAX)
2751 schedule_delayed_work(&nesdev->work, NES_LINK_RECHECK_DELAY);
2752 else
2753 nesdev->link_recheck = 0;
2754
2755 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
2756}
3c2d774c
GS		 2757
2758
1a855fbf 2759static void nes_nic_napi_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
3c2d774c
GS		 2760{
2761 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2762
288379f0 2763 napi_schedule(&nesvnic->napi);
3c2d774c
GS		 2764}
2765
2766
2767/* The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
2768* getting out of nic_ce_handler
2769*/
2770#define MAX_RQES_TO_PROCESS 384
2771
2772/**
2773 * nes_nic_ce_handler
2774 */
2775void nes_nic_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
2776{
2777 u64 u64temp;
2778 dma_addr_t bus_address;
2779 struct nes_hw_nic *nesnic;
2780 struct nes_vnic *nesvnic = container_of(cq, struct nes_vnic, nic_cq);
2781 struct nes_adapter *nesadapter = nesdev->nesadapter;
2782 struct nes_hw_nic_rq_wqe *nic_rqe;
2783 struct nes_hw_nic_sq_wqe *nic_sqe;
2784 struct sk_buff *skb;
2785 struct sk_buff *rx_skb;
2786 __le16 *wqe_fragment_length;
2787 u32 head;
2788 u32 cq_size;
2789 u32 rx_pkt_size;
2790 u32 cqe_count=0;
2791 u32 cqe_errv;
2792 u32 cqe_misc;
2793 u16 wqe_fragment_index = 1; /* first fragment (0) is used by copy buffer */
2794 u16 vlan_tag;
2795 u16 pkt_type;
2796 u16 rqes_processed = 0;
2797 u8 sq_cqes = 0;
37dab411 2798 u8 nes_use_lro = 0;
3c2d774c
GS		 2799
2800 head = cq->cq_head;
2801 cq_size = cq->cq_size;
2802 cq->cqes_pending = 1;
37dab411
FL		 2803 if (nesvnic->netdev->features & NETIF_F_LRO)
2804 nes_use_lro = 1;
3c2d774c
GS		 2805 do {
2806 if (le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]) &
2807 NES_NIC_CQE_VALID) {
2808 nesnic = &nesvnic->nic;
2809 cqe_misc = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]);
2810 if (cqe_misc & NES_NIC_CQE_SQ) {
2811 sq_cqes++;
2812 wqe_fragment_index = 1;
2813 nic_sqe = &nesnic->sq_vbase[nesnic->sq_tail];
2814 skb = nesnic->tx_skb[nesnic->sq_tail];
2815 wqe_fragment_length = (__le16 *)&nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
2816 /* bump past the vlan tag */
2817 wqe_fragment_length++;
2818 if (le16_to_cpu(wqe_fragment_length[wqe_fragment_index]) != 0) {
7495ab68
GS		 2819 u64temp = (u64) le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX +
2820 wqe_fragment_index * 2]);
2821 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX +
2822 wqe_fragment_index * 2])) << 32;
3c2d774c
GS		 2823 bus_address = (dma_addr_t)u64temp;
2824 if (test_and_clear_bit(nesnic->sq_tail, nesnic->first_frag_overflow)) {
2825 pci_unmap_single(nesdev->pcidev,
2826 bus_address,
2827 le16_to_cpu(wqe_fragment_length[wqe_fragment_index++]),
2828 PCI_DMA_TODEVICE);
2829 }
2830 for (; wqe_fragment_index < 5; wqe_fragment_index++) {
2831 if (wqe_fragment_length[wqe_fragment_index]) {
7495ab68
GS		 2832 u64temp = le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX +
2833 wqe_fragment_index * 2]);
2834 u64temp += ((u64)le32_to_cpu(nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
2835 + wqe_fragment_index * 2])) <<32;
3c2d774c
GS		 2836 bus_address = (dma_addr_t)u64temp;
2837 pci_unmap_page(nesdev->pcidev,
2838 bus_address,
2839 le16_to_cpu(wqe_fragment_length[wqe_fragment_index]),
2840 PCI_DMA_TODEVICE);
2841 } else
2842 break;
2843 }
3c2d774c 2844 }
2869975c
FL		 2845 if (skb)
2846 dev_kfree_skb_any(skb);
3c2d774c
GS		 2847 nesnic->sq_tail++;
2848 nesnic->sq_tail &= nesnic->sq_size-1;
2849 if (sq_cqes > 128) {
2850 barrier();
817979ac
RD		 2851 /* restart the queue if it had been stopped */
2852 if (netif_queue_stopped(nesvnic->netdev))
2853 netif_wake_queue(nesvnic->netdev);
3c2d774c
GS		 2854 sq_cqes = 0;
2855 }
2856 } else {
2857 rqes_processed ++;
2858
2859 cq->rx_cqes_completed++;
2860 cq->rx_pkts_indicated++;
2861 rx_pkt_size = cqe_misc & 0x0000ffff;
2862 nic_rqe = &nesnic->rq_vbase[nesnic->rq_tail];
2863 /* Get the skb */
2864 rx_skb = nesnic->rx_skb[nesnic->rq_tail];
2865 nic_rqe = &nesnic->rq_vbase[nesvnic->nic.rq_tail];
2866 bus_address = (dma_addr_t)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX]);
2867 bus_address += ((u64)le32_to_cpu(nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX])) << 32;
2868 pci_unmap_single(nesdev->pcidev, bus_address,
2869 nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
2870 /* rx_skb->tail = rx_skb->data + rx_pkt_size; */
2871 /* rx_skb->len = rx_pkt_size; */
2872 rx_skb->len = 0; /* TODO: see if this is necessary */
2873 skb_put(rx_skb, rx_pkt_size);
2874 rx_skb->protocol = eth_type_trans(rx_skb, nesvnic->netdev);
2875 nesnic->rq_tail++;
2876 nesnic->rq_tail &= nesnic->rq_size - 1;
2877
2878 atomic_inc(&nesvnic->rx_skbs_needed);
2879 if (atomic_read(&nesvnic->rx_skbs_needed) > (nesvnic->nic.rq_size>>1)) {
2880 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2881 cq->cq_number | (cqe_count << 16));
7495ab68 2882 /* nesadapter->tune_timer.cq_count += cqe_count; */
3c2d774c
GS		 2883 nesdev->currcq_count += cqe_count;
2884 cqe_count = 0;
2885 nes_replenish_nic_rq(nesvnic);
2886 }
2887 pkt_type = (u16)(le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX]));
2888 cqe_errv = (cqe_misc & NES_NIC_CQE_ERRV_MASK) >> NES_NIC_CQE_ERRV_SHIFT;
2889 rx_skb->ip_summed = CHECKSUM_NONE;
2890
2891 if ((NES_PKT_TYPE_TCPV4_BITS == (pkt_type & NES_PKT_TYPE_TCPV4_MASK)) ||
2892 (NES_PKT_TYPE_UDPV4_BITS == (pkt_type & NES_PKT_TYPE_UDPV4_MASK))) {
2893 if ((cqe_errv &
2894 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR |
2895 NES_NIC_ERRV_BITS_IPH_ERR | NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
dd6f6d02 2896 if (nesvnic->netdev->features & NETIF_F_RXCSUM)
3c2d774c 2897 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
3c2d774c
GS		 2898 } else
2899 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2900 " errv = 0x%X, pkt_type = 0x%X.\n",
2901 nesvnic->netdev->name, cqe_errv, pkt_type);
2902
2903 } else if ((pkt_type & NES_PKT_TYPE_IPV4_MASK) == NES_PKT_TYPE_IPV4_BITS) {
2904 if ((cqe_errv &
2905 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR | NES_NIC_ERRV_BITS_IPH_ERR |
2906 NES_NIC_ERRV_BITS_WQE_OVERRUN)) == 0) {
dd6f6d02 2907 if (nesvnic->netdev->features & NETIF_F_RXCSUM) {
3c2d774c
GS		 2908 rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
2909 /* nes_debug(NES_DBG_CQ, "%s: Reporting successfully checksummed IPv4 packet.\n",
2910 nesvnic->netdev->name); */
2911 }
2912 } else
2913 nes_debug(NES_DBG_CQ, "%s: unsuccessfully checksummed TCP or UDP packet."
2914 " errv = 0x%X, pkt_type = 0x%X.\n",
2915 nesvnic->netdev->name, cqe_errv, pkt_type);
2916 }
2917 /* nes_debug(NES_DBG_CQ, "pkt_type=%x, APBVT_MASK=%x\n",
2918 pkt_type, (pkt_type & NES_PKT_TYPE_APBVT_MASK)); */
2919
2920 if ((pkt_type & NES_PKT_TYPE_APBVT_MASK) == NES_PKT_TYPE_APBVT_BITS) {
4a14f6a7
FL		 2921 if (nes_cm_recv(rx_skb, nesvnic->netdev))
2922 rx_skb = NULL;
2923 }
2924 if (rx_skb == NULL)
2925 goto skip_rx_indicate0;
2926
2927
7033c4ad 2928 if (cqe_misc & NES_NIC_CQE_TAG_VALID) {
4a14f6a7
FL		 2929 vlan_tag = (u16)(le32_to_cpu(
2930 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_TAG_PKT_TYPE_IDX])
2931 >> 16);
2932 nes_debug(NES_DBG_CQ, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n",
2933 nesvnic->netdev->name, vlan_tag);
7033c4ad
JP		 2934
2935 __vlan_hwaccel_put_tag(rx_skb, vlan_tag);
3c2d774c 2936 }
7033c4ad
JP		 2937 if (nes_use_lro)
2938 lro_receive_skb(&nesvnic->lro_mgr, rx_skb, NULL);
2939 else
2940 netif_receive_skb(rx_skb);
3c2d774c 2941
4a14f6a7 2942skip_rx_indicate0:
451f1443 2943 ;
3c2d774c
GS		 2944 /* nesvnic->netstats.rx_packets++; */
2945 /* nesvnic->netstats.rx_bytes += rx_pkt_size; */
2946 }
2947
2948 cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX] = 0;
2949 /* Accounting... */
2950 cqe_count++;
2951 if (++head >= cq_size)
2952 head = 0;
2953 if (cqe_count == 255) {
2954 /* Replenish Nic CQ */
2955 nes_write32(nesdev->regs+NES_CQE_ALLOC,
2956 cq->cq_number | (cqe_count << 16));
7495ab68 2957 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
3c2d774c
GS		 2958 nesdev->currcq_count += cqe_count;
2959 cqe_count = 0;
2960 }
2961
2962 if (cq->rx_cqes_completed >= nesvnic->budget)
2963 break;
2964 } else {
2965 cq->cqes_pending = 0;
2966 break;
2967 }
2968
2969 } while (1);
2970
37dab411
FL		 2971 if (nes_use_lro)
2972 lro_flush_all(&nesvnic->lro_mgr);
3c2d774c
GS		 2973 if (sq_cqes) {
2974 barrier();
2975 /* restart the queue if it had been stopped */
2976 if (netif_queue_stopped(nesvnic->netdev))
2977 netif_wake_queue(nesvnic->netdev);
2978 }
3c2d774c
GS		 2979 cq->cq_head = head;
2980 /* nes_debug(NES_DBG_CQ, "CQ%u Processed = %u cqes, new head = %u.\n",
2981 cq->cq_number, cqe_count, cq->cq_head); */
2982 cq->cqe_allocs_pending = cqe_count;
2983 if (unlikely(nesadapter->et_use_adaptive_rx_coalesce))
2984 {
7495ab68 2985 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
3c2d774c
GS		 2986 nesdev->currcq_count += cqe_count;
2987 nes_nic_tune_timer(nesdev);
2988 }
2989 if (atomic_read(&nesvnic->rx_skbs_needed))
2990 nes_replenish_nic_rq(nesvnic);
37dab411 2991}
3c2d774c
GS		 2992
2993
2994/**
2995 * nes_cqp_ce_handler
2996 */
1a855fbf 2997static void nes_cqp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *cq)
3c2d774c
GS		 2998{
2999 u64 u64temp;
3000 unsigned long flags;
3001 struct nes_hw_cqp *cqp = NULL;
3002 struct nes_cqp_request *cqp_request;
3003 struct nes_hw_cqp_wqe *cqp_wqe;
3004 u32 head;
3005 u32 cq_size;
3006 u32 cqe_count=0;
3007 u32 error_code;
3008 /* u32 counter; */
3009
3010 head = cq->cq_head;
3011 cq_size = cq->cq_size;
3012
3013 do {
3014 /* process the CQE */
3015 /* nes_debug(NES_DBG_CQP, "head=%u cqe_words=%08X\n", head,
3016 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])); */
3017
3018 if (le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX]) & NES_CQE_VALID) {
3019 u64temp = (((u64)(le32_to_cpu(cq->cq_vbase[head].
7495ab68 3020 cqe_words[NES_CQE_COMP_COMP_CTX_HIGH_IDX]))) << 32) |
3c2d774c
GS		 3021 ((u64)(le32_to_cpu(cq->cq_vbase[head].
3022 cqe_words[NES_CQE_COMP_COMP_CTX_LOW_IDX])));
3023 cqp = *((struct nes_hw_cqp **)&u64temp);
3024
3025 error_code = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_ERROR_CODE_IDX]);
3026 if (error_code) {
3027 nes_debug(NES_DBG_CQP, "Bad Completion code for opcode 0x%02X from CQP,"
3028 " Major/Minor codes = 0x%04X:%04X.\n",
3029 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])&0x3f,
3030 (u16)(error_code >> 16),
3031 (u16)error_code);
3032 nes_debug(NES_DBG_CQP, "cqp: qp_id=%u, sq_head=%u, sq_tail=%u\n",
3033 cqp->qp_id, cqp->sq_head, cqp->sq_tail);
3034 }
3035
3036 u64temp = (((u64)(le32_to_cpu(nesdev->cqp.sq_vbase[cqp->sq_tail].
7495ab68 3037 wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX]))) << 32) |
3c2d774c
GS		 3038 ((u64)(le32_to_cpu(nesdev->cqp.sq_vbase[cqp->sq_tail].
3039 wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX])));
3040 cqp_request = *((struct nes_cqp_request **)&u64temp);
3041 if (cqp_request) {
3042 if (cqp_request->waiting) {
3043 /* nes_debug(NES_DBG_CQP, "%s: Waking up requestor\n"); */
3044 cqp_request->major_code = (u16)(error_code >> 16);
3045 cqp_request->minor_code = (u16)error_code;
3046 barrier();
3047 cqp_request->request_done = 1;
3048 wake_up(&cqp_request->waitq);
1ff66e8c 3049 nes_put_cqp_request(nesdev, cqp_request);
3c2d774c 3050 } else {
1ff66e8c
RD		 3051 if (cqp_request->callback)
3052 cqp_request->cqp_callback(nesdev, cqp_request);
3053 nes_free_cqp_request(nesdev, cqp_request);
3c2d774c
GS		 3054 }
3055 } else {
3056 wake_up(&nesdev->cqp.waitq);
3057 }
3058
3059 cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX] = 0;
7495ab68 3060 nes_write32(nesdev->regs + NES_CQE_ALLOC, cq->cq_number | (1 << 16));
3c2d774c
GS		 3061 if (++cqp->sq_tail >= cqp->sq_size)
3062 cqp->sq_tail = 0;
3063
3064 /* Accounting... */
3065 cqe_count++;
3066 if (++head >= cq_size)
3067 head = 0;
3068 } else {
3069 break;
3070 }
3071 } while (1);
3072 cq->cq_head = head;
3073
3074 spin_lock_irqsave(&nesdev->cqp.lock, flags);
3075 while ((!list_empty(&nesdev->cqp_pending_reqs)) &&
3076 ((((nesdev->cqp.sq_tail+nesdev->cqp.sq_size)-nesdev->cqp.sq_head) &
3077 (nesdev->cqp.sq_size - 1)) != 1)) {
3078 cqp_request = list_entry(nesdev->cqp_pending_reqs.next,
3079 struct nes_cqp_request, list);
3080 list_del_init(&cqp_request->list);
3081 head = nesdev->cqp.sq_head++;
3082 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
3083 cqp_wqe = &nesdev->cqp.sq_vbase[head];
3084 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
3085 barrier();
3086 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] =
3087 cpu_to_le32((u32)((unsigned long)cqp_request));
3088 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] =
3089 cpu_to_le32((u32)(upper_32_bits((unsigned long)cqp_request)));
3090 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) put on CQPs SQ wqe%u.\n",
3091 cqp_request, le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f, head);
3092 /* Ring doorbell (1 WQEs) */
3093 barrier();
3094 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
3095 }
3096 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
3097
3098 /* Arm the CCQ */
3099 nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
3100 cq->cq_number);
3101 nes_read32(nesdev->regs+NES_CQE_ALLOC);
3102}
3103
3104
8b1c9dc4
DW		 3105static u8 *locate_mpa(u8 *pkt, u32 aeq_info)
3106{
8b1c9dc4
DW		 3107 if (aeq_info & NES_AEQE_Q2_DATA_ETHERNET) {
3108 /* skip over ethernet header */
8b1c9dc4
DW		 3109 pkt += ETH_HLEN;
3110
3111 /* Skip over IP and TCP headers */
3112 pkt += 4 * (pkt[0] & 0x0f);
3113 pkt += 4 * ((pkt[12] >> 4) & 0x0f);
3114 }
3115 return pkt;
3116}
3117
3118/* Determine if incoming error pkt is rdma layer */
3119static u32 iwarp_opcode(struct nes_qp *nesqp, u32 aeq_info)
3120{
3121 u8 *pkt;
3122 u16 *mpa;
3123 u32 opcode = 0xffffffff;
3124
3125 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3126 pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3127 mpa = (u16 *)locate_mpa(pkt, aeq_info);
3128 opcode = be16_to_cpu(mpa[1]) & 0xf;
3129 }
3130
3131 return opcode;
3132}
3133
3134/* Build iWARP terminate header */
3135static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 aeq_info)
3136{
3137 u8 *pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3138 u16 ddp_seg_len;
3139 int copy_len = 0;
3140 u8 is_tagged = 0;
4b281fae 3141 u8 flush_code = 0;
8b1c9dc4
DW		 3142 struct nes_terminate_hdr *termhdr;
3143
3144 termhdr = (struct nes_terminate_hdr *)nesqp->hwqp.q2_vbase;
3145 memset(termhdr, 0, 64);
3146
3147 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3148
3149 /* Use data from offending packet to fill in ddp & rdma hdrs */
3150 pkt = locate_mpa(pkt, aeq_info);
3151 ddp_seg_len = be16_to_cpu(*(u16 *)pkt);
3152 if (ddp_seg_len) {
3153 copy_len = 2;
3154 termhdr->hdrct = DDP_LEN_FLAG;
3155 if (pkt[2] & 0x80) {
3156 is_tagged = 1;
3157 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
3158 copy_len += TERM_DDP_LEN_TAGGED;
3159 termhdr->hdrct |= DDP_HDR_FLAG;
3160 }
3161 } else {
3162 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
3163 copy_len += TERM_DDP_LEN_UNTAGGED;
3164 termhdr->hdrct |= DDP_HDR_FLAG;
3165 }
3166
3167 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN)) {
3168 if ((pkt[3] & RDMA_OPCODE_MASK) == RDMA_READ_REQ_OPCODE) {
3169 copy_len += TERM_RDMA_LEN;
3170 termhdr->hdrct |= RDMA_HDR_FLAG;
3171 }
3172 }
3173 }
3174 }
3175 }
3176
3177 switch (async_event_id) {
3178 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
3179 switch (iwarp_opcode(nesqp, aeq_info)) {
3180 case IWARP_OPCODE_WRITE:
4b281fae 3181 flush_code = IB_WC_LOC_PROT_ERR;
8b1c9dc4
DW		 3182 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3183 termhdr->error_code = DDP_TAGGED_INV_STAG;
3184 break;
3185 default:
4b281fae 3186 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3187 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3188 termhdr->error_code = RDMAP_INV_STAG;
3189 }
3190 break;
3191 case NES_AEQE_AEID_AMP_INVALID_STAG:
4b281fae 3192 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3193 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3194 termhdr->error_code = RDMAP_INV_STAG;
3195 break;
3196 case NES_AEQE_AEID_AMP_BAD_QP:
4b281fae 3197 flush_code = IB_WC_LOC_QP_OP_ERR;
8b1c9dc4
DW		 3198 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3199 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3200 break;
3201 case NES_AEQE_AEID_AMP_BAD_STAG_KEY:
3202 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX:
3203 switch (iwarp_opcode(nesqp, aeq_info)) {
3204 case IWARP_OPCODE_SEND_INV:
3205 case IWARP_OPCODE_SEND_SE_INV:
4b281fae 3206 flush_code = IB_WC_REM_OP_ERR;
8b1c9dc4
DW		 3207 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3208 termhdr->error_code = RDMAP_CANT_INV_STAG;
3209 break;
3210 default:
4b281fae 3211 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3212 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3213 termhdr->error_code = RDMAP_INV_STAG;
3214 }
3215 break;
3216 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION:
3217 if (aeq_info & (NES_AEQE_Q2_DATA_ETHERNET | NES_AEQE_Q2_DATA_MPA)) {
4b281fae 3218 flush_code = IB_WC_LOC_PROT_ERR;
8b1c9dc4
DW		 3219 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3220 termhdr->error_code = DDP_TAGGED_BOUNDS;
3221 } else {
4b281fae 3222 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3223 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3224 termhdr->error_code = RDMAP_INV_BOUNDS;
3225 }
3226 break;
3227 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION:
3228 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
3229 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
4b281fae 3230 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3231 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3232 termhdr->error_code = RDMAP_ACCESS;
3233 break;
3234 case NES_AEQE_AEID_AMP_TO_WRAP:
4b281fae 3235 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3236 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3237 termhdr->error_code = RDMAP_TO_WRAP;
3238 break;
3239 case NES_AEQE_AEID_AMP_BAD_PD:
3240 switch (iwarp_opcode(nesqp, aeq_info)) {
3241 case IWARP_OPCODE_WRITE:
4b281fae 3242 flush_code = IB_WC_LOC_PROT_ERR;
8b1c9dc4
DW		 3243 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3244 termhdr->error_code = DDP_TAGGED_UNASSOC_STAG;
3245 break;
3246 case IWARP_OPCODE_SEND_INV:
3247 case IWARP_OPCODE_SEND_SE_INV:
4b281fae 3248 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3249 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3250 termhdr->error_code = RDMAP_CANT_INV_STAG;
3251 break;
3252 default:
4b281fae 3253 flush_code = IB_WC_REM_ACCESS_ERR;
8b1c9dc4
DW		 3254 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3255 termhdr->error_code = RDMAP_UNASSOC_STAG;
3256 }
3257 break;
3258 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
4b281fae 3259 flush_code = IB_WC_LOC_LEN_ERR;
8b1c9dc4
DW		 3260 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3261 termhdr->error_code = MPA_MARKER;
3262 break;
3263 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
4b281fae 3264 flush_code = IB_WC_GENERAL_ERR;
8b1c9dc4
DW		 3265 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3266 termhdr->error_code = MPA_CRC;
3267 break;
3268 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE:
3269 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL:
4b281fae 3270 flush_code = IB_WC_LOC_LEN_ERR;
8b1c9dc4
DW		 3271 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3272 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3273 break;
3274 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC:
3275 case NES_AEQE_AEID_DDP_NO_L_BIT:
4b281fae 3276 flush_code = IB_WC_FATAL_ERR;
8b1c9dc4
DW		 3277 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3278 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3279 break;
3280 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN:
3281 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
4b281fae 3282 flush_code = IB_WC_GENERAL_ERR;
8b1c9dc4
DW		 3283 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3284 termhdr->error_code = DDP_UNTAGGED_INV_MSN_RANGE;
3285 break;
3286 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
4b281fae 3287 flush_code = IB_WC_LOC_LEN_ERR;
8b1c9dc4
DW		 3288 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3289 termhdr->error_code = DDP_UNTAGGED_INV_TOO_LONG;
3290 break;
3291 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION:
4b281fae 3292 flush_code = IB_WC_GENERAL_ERR;
8b1c9dc4
DW		 3293 if (is_tagged) {
3294 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3295 termhdr->error_code = DDP_TAGGED_INV_DDP_VER;
3296 } else {
3297 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3298 termhdr->error_code = DDP_UNTAGGED_INV_DDP_VER;
3299 }
3300 break;
3301 case NES_AEQE_AEID_DDP_UBE_INVALID_MO:
4b281fae 3302 flush_code = IB_WC_GENERAL_ERR;
8b1c9dc4
DW		 3303 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3304 termhdr->error_code = DDP_UNTAGGED_INV_MO;
3305 break;
3306 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
4b281fae 3307 flush_code = IB_WC_REM_OP_ERR;
8b1c9dc4
DW		 3308 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3309 termhdr->error_code = DDP_UNTAGGED_INV_MSN_NO_BUF;
3310 break;
3311 case NES_AEQE_AEID_DDP_UBE_INVALID_QN:
4b281fae 3312 flush_code = IB_WC_GENERAL_ERR;
8b1c9dc4
DW		 3313 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3314 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3315 break;
3316 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION:
4b281fae 3317 flush_code = IB_WC_GENERAL_ERR;
8b1c9dc4
DW		 3318 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3319 termhdr->error_code = RDMAP_INV_RDMAP_VER;
3320 break;
3321 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE:
4b281fae 3322 flush_code = IB_WC_LOC_QP_OP_ERR;
8b1c9dc4
DW		 3323 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3324 termhdr->error_code = RDMAP_UNEXPECTED_OP;
3325 break;
3326 default:
4b281fae 3327 flush_code = IB_WC_FATAL_ERR;
8b1c9dc4
DW		 3328 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3329 termhdr->error_code = RDMAP_UNSPECIFIED;
3330 break;
3331 }
3332
3333 if (copy_len)
3334 memcpy(termhdr + 1, pkt, copy_len);
3335
4b281fae
DW		 3336 if ((flush_code) && ((NES_AEQE_INBOUND_RDMA & aeq_info) == 0)) {
3337 if (aeq_info & NES_AEQE_SQ)
3338 nesqp->term_sq_flush_code = flush_code;
3339 else
3340 nesqp->term_rq_flush_code = flush_code;
3341 }
3342
8b1c9dc4
DW		 3343 return sizeof(struct nes_terminate_hdr) + copy_len;
3344}
3345
3346static void nes_terminate_connection(struct nes_device *nesdev, struct nes_qp *nesqp,
3347 struct nes_hw_aeqe *aeqe, enum ib_event_type eventtype)
3348{
3349 u64 context;
3350 unsigned long flags;
3351 u32 aeq_info;
3352 u16 async_event_id;
3353 u8 tcp_state;
3354 u8 iwarp_state;
3355 u32 termlen = 0;
3356 u32 mod_qp_flags = NES_CQP_QP_IWARP_STATE_TERMINATE |
3357 NES_CQP_QP_TERM_DONT_SEND_FIN;
3358 struct nes_adapter *nesadapter = nesdev->nesadapter;
3359
3360 if (nesqp->term_flags & NES_TERM_SENT)
3361 return; /* Sanity check */
3362
3363 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3364 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3365 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3366 async_event_id = (u16)aeq_info;
3367
3368 context = (unsigned long)nesadapter->qp_table[le32_to_cpu(
3369 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]) - NES_FIRST_QPN];
3370 if (!context) {
3371 WARN_ON(!context);
3372 return;
3373 }
3374
3375 nesqp = (struct nes_qp *)(unsigned long)context;
3376 spin_lock_irqsave(&nesqp->lock, flags);
3377 nesqp->hw_iwarp_state = iwarp_state;
3378 nesqp->hw_tcp_state = tcp_state;
3379 nesqp->last_aeq = async_event_id;
3380 nesqp->terminate_eventtype = eventtype;
3381 spin_unlock_irqrestore(&nesqp->lock, flags);
3382
3383 if (nesadapter->send_term_ok)
3384 termlen = nes_bld_terminate_hdr(nesqp, async_event_id, aeq_info);
3385 else
3386 mod_qp_flags |= NES_CQP_QP_TERM_DONT_SEND_TERM_MSG;
3387
cd6860eb
FL		 3388 if (!nesdev->iw_status) {
3389 nesqp->term_flags = NES_TERM_DONE;
3390 nes_hw_modify_qp(nesdev, nesqp, NES_CQP_QP_IWARP_STATE_ERROR, 0, 0);
3391 nes_cm_disconn(nesqp);
3392 } else {
3393 nes_terminate_start_timer(nesqp);
3394 nesqp->term_flags |= NES_TERM_SENT;
3395 nes_hw_modify_qp(nesdev, nesqp, mod_qp_flags, termlen, 0);
3396 }
8b1c9dc4
DW		 3397}
3398
3399static void nes_terminate_send_fin(struct nes_device *nesdev,
3400 struct nes_qp *nesqp, struct nes_hw_aeqe *aeqe)
3401{
3402 u32 aeq_info;
3403 u16 async_event_id;
3404 u8 tcp_state;
3405 u8 iwarp_state;
3406 unsigned long flags;
3407
3408 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3409 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3410 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3411 async_event_id = (u16)aeq_info;
3412
3413 spin_lock_irqsave(&nesqp->lock, flags);
3414 nesqp->hw_iwarp_state = iwarp_state;
3415 nesqp->hw_tcp_state = tcp_state;
3416 nesqp->last_aeq = async_event_id;
3417 spin_unlock_irqrestore(&nesqp->lock, flags);
3418
3419 /* Send the fin only */
3420 nes_hw_modify_qp(nesdev, nesqp, NES_CQP_QP_IWARP_STATE_TERMINATE |
3421 NES_CQP_QP_TERM_DONT_SEND_TERM_MSG, 0, 0);
3422}
3423
3424/* Cleanup after a terminate sent or received */
3425static void nes_terminate_done(struct nes_qp *nesqp, int timeout_occurred)
3426{
3427 u32 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR;
3428 unsigned long flags;
3429 struct nes_vnic *nesvnic = to_nesvnic(nesqp->ibqp.device);
3430 struct nes_device *nesdev = nesvnic->nesdev;
3431 u8 first_time = 0;
3432
3433 spin_lock_irqsave(&nesqp->lock, flags);
3434 if (nesqp->hte_added) {
3435 nesqp->hte_added = 0;
3436 next_iwarp_state |= NES_CQP_QP_DEL_HTE;
3437 }
3438
3439 first_time = (nesqp->term_flags & NES_TERM_DONE) == 0;
3440 nesqp->term_flags |= NES_TERM_DONE;
3441 spin_unlock_irqrestore(&nesqp->lock, flags);
3442
3443 /* Make sure we go through this only once */
3444 if (first_time) {
3445 if (timeout_occurred == 0)
3446 del_timer(&nesqp->terminate_timer);
3447 else
3448 next_iwarp_state |= NES_CQP_QP_RESET;
3449
3450 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3451 nes_cm_disconn(nesqp);
3452 }
3453}
3454
3455static void nes_terminate_received(struct nes_device *nesdev,
3456 struct nes_qp *nesqp, struct nes_hw_aeqe *aeqe)
3457{
3458 u32 aeq_info;
3459 u8 *pkt;
3460 u32 *mpa;
3461 u8 ddp_ctl;
3462 u8 rdma_ctl;
3463 u16 aeq_id = 0;
3464
3465 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
3466 if (aeq_info & NES_AEQE_Q2_DATA_WRITTEN) {
3467 /* Terminate is not a performance path so the silicon */
3468 /* did not validate the frame - do it now */
3469 pkt = nesqp->hwqp.q2_vbase + BAD_FRAME_OFFSET;
3470 mpa = (u32 *)locate_mpa(pkt, aeq_info);
3471 ddp_ctl = (be32_to_cpu(mpa[0]) >> 8) & 0xff;
3472 rdma_ctl = be32_to_cpu(mpa[0]) & 0xff;
3473 if ((ddp_ctl & 0xc0) != 0x40)
3474 aeq_id = NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC;
3475 else if ((ddp_ctl & 0x03) != 1)
3476 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION;
3477 else if (be32_to_cpu(mpa[2]) != 2)
3478 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_QN;
3479 else if (be32_to_cpu(mpa[3]) != 1)
3480 aeq_id = NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN;
3481 else if (be32_to_cpu(mpa[4]) != 0)
3482 aeq_id = NES_AEQE_AEID_DDP_UBE_INVALID_MO;
3483 else if ((rdma_ctl & 0xc0) != 0x40)
3484 aeq_id = NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION;
3485
3486 if (aeq_id) {
3487 /* Bad terminate recvd - send back a terminate */
3488 aeq_info = (aeq_info & 0xffff0000) | aeq_id;
3489 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info);
3490 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL);
3491 return;
3492 }
3493 }
3494
3495 nesqp->term_flags |= NES_TERM_RCVD;
3496 nesqp->terminate_eventtype = IB_EVENT_QP_FATAL;
3497 nes_terminate_start_timer(nesqp);
3498 nes_terminate_send_fin(nesdev, nesqp, aeqe);
3499}
3500
3501/* Timeout routine in case terminate fails to complete */
3502static void nes_terminate_timeout(unsigned long context)
3503{
3504 struct nes_qp *nesqp = (struct nes_qp *)(unsigned long)context;
3505
3506 nes_terminate_done(nesqp, 1);
3507}
3508
3509/* Set a timer in case hw cannot complete the terminate sequence */
3510static void nes_terminate_start_timer(struct nes_qp *nesqp)
3511{
3512 init_timer(&nesqp->terminate_timer);
3513 nesqp->terminate_timer.function = nes_terminate_timeout;
3514 nesqp->terminate_timer.expires = jiffies + HZ;
3515 nesqp->terminate_timer.data = (unsigned long)nesqp;
3516 add_timer(&nesqp->terminate_timer);
3517}
3518
3c2d774c
GS		 3519/**
3520 * nes_process_iwarp_aeqe
3521 */
1a855fbf
RD		 3522static void nes_process_iwarp_aeqe(struct nes_device *nesdev,
3523 struct nes_hw_aeqe *aeqe)
3c2d774c
GS		 3524{
3525 u64 context;
3c2d774c
GS		 3526 unsigned long flags;
3527 struct nes_qp *nesqp;
3c28b445
DW		 3528 struct nes_hw_cq *hw_cq;
3529 struct nes_cq *nescq;
3c2d774c 3530 int resource_allocated;
3c2d774c 3531 struct nes_adapter *nesadapter = nesdev->nesadapter;
3c2d774c
GS		 3532 u32 aeq_info;
3533 u32 next_iwarp_state = 0;
df029023 3534 u32 aeqe_cq_id;
3c2d774c
GS		 3535 u16 async_event_id;
3536 u8 tcp_state;
3537 u8 iwarp_state;
8b1c9dc4 3538 struct ib_event ibevent;
3c2d774c
GS		 3539
3540 nes_debug(NES_DBG_AEQ, "\n");
3541 aeq_info = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_MISC_IDX]);
8b1c9dc4 3542 if ((NES_AEQE_INBOUND_RDMA & aeq_info) || (!(NES_AEQE_QP & aeq_info))) {
7495ab68 3543 context = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX]);
3c2d774c
GS		 3544 context += ((u64)le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX])) << 32;
3545 } else {
3c2d774c 3546 context = (unsigned long)nesadapter->qp_table[le32_to_cpu(
7495ab68 3547 aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]) - NES_FIRST_QPN];
3c2d774c
GS		 3548 BUG_ON(!context);
3549 }
3550
30b172ff
FL		 3551 /* context is nesqp unless async_event_id == CQ ERROR */
3552 nesqp = (struct nes_qp *)(unsigned long)context;
3c2d774c
GS		 3553 async_event_id = (u16)aeq_info;
3554 tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT;
3555 iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT;
3556 nes_debug(NES_DBG_AEQ, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p,"
3557 " Tcp state = %s, iWARP state = %s\n",
3558 async_event_id,
3559 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), aeqe,
3560 nes_tcp_state_str[tcp_state], nes_iwarp_state_str[iwarp_state]);
3561
df029023
FL		 3562 aeqe_cq_id = le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]);
3563 if (aeq_info & NES_AEQE_QP) {
bab3a9f4
FL		 3564 if (!nes_is_resource_allocated(nesadapter,
3565 nesadapter->allocated_qps,
3566 aeqe_cq_id))
df029023
FL		 3567 return;
3568 }
3569
3c2d774c
GS		 3570 switch (async_event_id) {
3571 case NES_AEQE_AEID_LLP_FIN_RECEIVED:
8b1c9dc4
DW		 3572 if (nesqp->term_flags)
3573 return; /* Ignore it, wait for close complete */
3574
3c2d774c 3575 if (atomic_inc_return(&nesqp->close_timer_started) == 1) {
67d70721 3576 if ((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) &&
bab3a9f4 3577 (nesqp->ibqp_state == IB_QPS_RTS)) {
67d70721
FL		 3578 spin_lock_irqsave(&nesqp->lock, flags);
3579 nesqp->hw_iwarp_state = iwarp_state;
3580 nesqp->hw_tcp_state = tcp_state;
3581 nesqp->last_aeq = async_event_id;
3582 next_iwarp_state = NES_CQP_QP_IWARP_STATE_CLOSING;
3583 nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_CLOSING;
3584 spin_unlock_irqrestore(&nesqp->lock, flags);
3585 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3586 nes_cm_disconn(nesqp);
3587 }
3c2d774c 3588 nesqp->cm_id->add_ref(nesqp->cm_id);
3c2d774c
GS		 3589 schedule_nes_timer(nesqp->cm_node, (struct sk_buff *)nesqp,
3590 NES_TIMER_TYPE_CLOSE, 1, 0);
3591 nes_debug(NES_DBG_AEQ, "QP%u Not decrementing QP refcount (%d),"
3592 " need ae to finish up, original_last_aeq = 0x%04X."
3593 " last_aeq = 0x%04X, scheduling timer. TCP state = %d\n",
3594 nesqp->hwqp.qp_id, atomic_read(&nesqp->refcount),
3595 async_event_id, nesqp->last_aeq, tcp_state);
3596 }
30b172ff 3597 break;
3c2d774c 3598 case NES_AEQE_AEID_LLP_CLOSE_COMPLETE:
8b1c9dc4
DW		 3599 if (nesqp->term_flags) {
3600 nes_terminate_done(nesqp, 0);
3601 return;
3602 }
30b172ff 3603 spin_lock_irqsave(&nesqp->lock, flags);
bab3a9f4
FL		 3604 nesqp->hw_iwarp_state = iwarp_state;
3605 nesqp->hw_tcp_state = tcp_state;
3606 nesqp->last_aeq = async_event_id;
30b172ff 3607 spin_unlock_irqrestore(&nesqp->lock, flags);
30b172ff
FL		 3608 nes_cm_disconn(nesqp);
3609 break;
8b1c9dc4 3610
3c2d774c 3611 case NES_AEQE_AEID_RESET_SENT:
30b172ff 3612 tcp_state = NES_AEQE_TCP_STATE_CLOSED;
3c2d774c
GS		 3613 spin_lock_irqsave(&nesqp->lock, flags);
3614 nesqp->hw_iwarp_state = iwarp_state;
3615 nesqp->hw_tcp_state = tcp_state;
3616 nesqp->last_aeq = async_event_id;
30b172ff 3617 nesqp->hte_added = 0;
3c2d774c 3618 spin_unlock_irqrestore(&nesqp->lock, flags);
30b172ff
FL		 3619 next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR | NES_CQP_QP_DEL_HTE;
3620 nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0);
3621 nes_cm_disconn(nesqp);
3622 break;
8b1c9dc4 3623
30b172ff
FL		 3624 case NES_AEQE_AEID_LLP_CONNECTION_RESET:
3625 if (atomic_read(&nesqp->close_timer_started))
3626 return;
3627 spin_lock_irqsave(&nesqp->lock, flags);
3628 nesqp->hw_iwarp_state = iwarp_state;
3629 nesqp->hw_tcp_state = tcp_state;
3630 nesqp->last_aeq = async_event_id;
3631 spin_unlock_irqrestore(&nesqp->lock, flags);
3632 nes_cm_disconn(nesqp);
3c2d774c 3633 break;
8b1c9dc4
DW		 3634
3635 case NES_AEQE_AEID_TERMINATE_SENT:
8b1c9dc4 3636 nes_terminate_send_fin(nesdev, nesqp, aeqe);
3c2d774c 3637 break;
8b1c9dc4
DW		 3638
3639 case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED:
8b1c9dc4 3640 nes_terminate_received(nesdev, nesqp, aeqe);
3c2d774c 3641 break;
8b1c9dc4
DW		 3642
3643 case NES_AEQE_AEID_AMP_BAD_STAG_KEY:
3644 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX:
3c2d774c 3645 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
8b1c9dc4
DW		 3646 case NES_AEQE_AEID_AMP_INVALID_STAG:
3647 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION:
3648 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
3c2d774c 3649 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
8b1c9dc4
DW		 3650 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
3651 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION:
3652 case NES_AEQE_AEID_AMP_TO_WRAP:
30b172ff
FL		 3653 printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_ACCESS_ERR\n",
3654 nesqp->hwqp.qp_id, async_event_id);
8b1c9dc4
DW		 3655 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_ACCESS_ERR);
3656 break;
3657
3658 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE:
3659 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL:
3660 case NES_AEQE_AEID_DDP_UBE_INVALID_MO:
3661 case NES_AEQE_AEID_DDP_UBE_INVALID_QN:
8b1c9dc4
DW		 3662 if (iwarp_opcode(nesqp, aeq_info) > IWARP_OPCODE_TERM) {
3663 aeq_info &= 0xffff0000;
3664 aeq_info |= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE;
3665 aeqe->aeqe_words[NES_AEQE_MISC_IDX] = cpu_to_le32(aeq_info);
3c2d774c 3666 }
8b1c9dc4
DW		 3667
3668 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE:
3669 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES:
3670 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
3671 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
3672 case NES_AEQE_AEID_AMP_BAD_QP:
3673 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
3674 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC:
3675 case NES_AEQE_AEID_DDP_NO_L_BIT:
3676 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN:
3677 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
3678 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION:
3679 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION:
3680 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE:
3681 case NES_AEQE_AEID_AMP_BAD_PD:
3682 case NES_AEQE_AEID_AMP_FASTREG_SHARED:
3683 case NES_AEQE_AEID_AMP_FASTREG_VALID_STAG:
3684 case NES_AEQE_AEID_AMP_FASTREG_MW_STAG:
3685 case NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS:
3686 case NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW:
3687 case NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH:
3688 case NES_AEQE_AEID_AMP_INVALIDATE_SHARED:
3689 case NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS:
3690 case NES_AEQE_AEID_AMP_MWBIND_VALID_STAG:
3691 case NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG:
3692 case NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG:
3693 case NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG:
3694 case NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS:
3695 case NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS:
3696 case NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT:
3697 case NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED:
3698 case NES_AEQE_AEID_BAD_CLOSE:
3699 case NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO:
3700 case NES_AEQE_AEID_STAG_ZERO_INVALID:
3701 case NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST:
3702 case NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
30b172ff
FL		 3703 printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_FATAL\n",
3704 nesqp->hwqp.qp_id, async_event_id);
6224c7ee 3705 print_ip(nesqp->cm_node);
bab3a9f4
FL		 3706 if (!atomic_read(&nesqp->close_timer_started))
3707 nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL);
3c2d774c 3708 break;
8b1c9dc4 3709
3c2d774c
GS		 3710 case NES_AEQE_AEID_CQ_OPERATION_ERROR:
3711 context <<= 1;
3712 nes_debug(NES_DBG_AEQ, "Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u, %p\n",
3713 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]), (void *)(unsigned long)context);
3714 resource_allocated = nes_is_resource_allocated(nesadapter, nesadapter->allocated_cqs,
3715 le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
3716 if (resource_allocated) {
3717 printk(KERN_ERR PFX "%s: Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u\n",
33718363 3718 __func__, le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_QP_CQ_ID_IDX]));
3c28b445
DW		 3719 hw_cq = (struct nes_hw_cq *)(unsigned long)context;
3720 if (hw_cq) {
3721 nescq = container_of(hw_cq, struct nes_cq, hw_cq);
3722 if (nescq->ibcq.event_handler) {
3723 ibevent.device = nescq->ibcq.device;
3724 ibevent.event = IB_EVENT_CQ_ERR;
3725 ibevent.element.cq = &nescq->ibcq;
3726 nescq->ibcq.event_handler(&ibevent, nescq->ibcq.cq_context);
3727 }
3728 }
3c2d774c
GS		 3729 }
3730 break;
8b1c9dc4 3731
3c2d774c
GS		 3732 default:
3733 nes_debug(NES_DBG_AEQ, "Processing an iWARP related AE for QP, misc = 0x%04X\n",
3734 async_event_id);
3735 break;
3736 }
3737
3738}
3739
3c2d774c
GS		 3740/**
3741 * nes_iwarp_ce_handler
3742 */
3743void nes_iwarp_ce_handler(struct nes_device *nesdev, struct nes_hw_cq *hw_cq)
3744{
3745 struct nes_cq *nescq = container_of(hw_cq, struct nes_cq, hw_cq);
3746
3747 /* nes_debug(NES_DBG_CQ, "Processing completion event for iWARP CQ%u.\n",
3748 nescq->hw_cq.cq_number); */
3749 nes_write32(nesdev->regs+NES_CQ_ACK, nescq->hw_cq.cq_number);
3750
3751 if (nescq->ibcq.comp_handler)
3752 nescq->ibcq.comp_handler(&nescq->ibcq, nescq->ibcq.cq_context);
3753
3754 return;
3755}
3756
3757
3758/**
3759 * nes_manage_apbvt()
3760 */
3761int nes_manage_apbvt(struct nes_vnic *nesvnic, u32 accel_local_port,
3762 u32 nic_index, u32 add_port)
3763{
3764 struct nes_device *nesdev = nesvnic->nesdev;
3765 struct nes_hw_cqp_wqe *cqp_wqe;
3c2d774c
GS		 3766 struct nes_cqp_request *cqp_request;
3767 int ret = 0;
3768 u16 major_code;
3769
3770 /* Send manage APBVT request to CQP */
3771 cqp_request = nes_get_cqp_request(nesdev);
3772 if (cqp_request == NULL) {
3773 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
3774 return -ENOMEM;
3775 }
3776 cqp_request->waiting = 1;
3777 cqp_wqe = &cqp_request->cqp_wqe;
3778
3779 nes_debug(NES_DBG_QP, "%s APBV for local port=%u(0x%04x), nic_index=%u\n",
3780 (add_port == NES_MANAGE_APBVT_ADD) ? "ADD" : "DEL",
3781 accel_local_port, accel_local_port, nic_index);
3782
3783 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3784 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX, (NES_CQP_MANAGE_APBVT |
3785 ((add_port == NES_MANAGE_APBVT_ADD) ? NES_CQP_APBVT_ADD : 0)));
3786 set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
3787 ((nic_index << NES_CQP_APBVT_NIC_SHIFT) | accel_local_port));
3788
3789 nes_debug(NES_DBG_QP, "Waiting for CQP completion for APBVT.\n");
3790
3791 atomic_set(&cqp_request->refcount, 2);
8294f297 3792 nes_post_cqp_request(nesdev, cqp_request);
3c2d774c
GS		 3793
3794 if (add_port == NES_MANAGE_APBVT_ADD)
3795 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
3796 NES_EVENT_TIMEOUT);
3797 nes_debug(NES_DBG_QP, "Completed, ret=%u, CQP Major:Minor codes = 0x%04X:0x%04X\n",
3798 ret, cqp_request->major_code, cqp_request->minor_code);
3799 major_code = cqp_request->major_code;
1ff66e8c
RD		 3800
3801 nes_put_cqp_request(nesdev, cqp_request);
3802
3c2d774c
GS		 3803 if (!ret)
3804 return -ETIME;
3805 else if (major_code)
3806 return -EIO;
3807 else
3808 return 0;
3809}
3810
3811
3812/**
3813 * nes_manage_arp_cache
3814 */
3815void nes_manage_arp_cache(struct net_device *netdev, unsigned char *mac_addr,
3816 u32 ip_addr, u32 action)
3817{
3818 struct nes_hw_cqp_wqe *cqp_wqe;
3819 struct nes_vnic *nesvnic = netdev_priv(netdev);
3820 struct nes_device *nesdev;
3821 struct nes_cqp_request *cqp_request;
3822 int arp_index;
3823
3824 nesdev = nesvnic->nesdev;
3825 arp_index = nes_arp_table(nesdev, ip_addr, mac_addr, action);
3826 if (arp_index == -1) {
3827 return;
3828 }
3829
3830 /* update the ARP entry */
3831 cqp_request = nes_get_cqp_request(nesdev);
3832 if (cqp_request == NULL) {
3833 nes_debug(NES_DBG_NETDEV, "Failed to get a cqp_request.\n");
3834 return;
3835 }
3836 cqp_request->waiting = 0;
3837 cqp_wqe = &cqp_request->cqp_wqe;
3838 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3839
3840 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
3841 NES_CQP_MANAGE_ARP_CACHE | NES_CQP_ARP_PERM);
3842 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(
3843 (u32)PCI_FUNC(nesdev->pcidev->devfn) << NES_CQP_ARP_AEQ_INDEX_SHIFT);
3844 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(arp_index);
3845
3846 if (action == NES_ARP_ADD) {
3847 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] |= cpu_to_le32(NES_CQP_ARP_VALID);
3848 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = cpu_to_le32(
3849 (((u32)mac_addr[2]) << 24) | (((u32)mac_addr[3]) << 16) |
7495ab68 3850 (((u32)mac_addr[4]) << 8) | (u32)mac_addr[5]);
3c2d774c
GS		 3851 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = cpu_to_le32(
3852 (((u32)mac_addr[0]) << 16) | (u32)mac_addr[1]);
3853 } else {
3854 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX] = 0;
3855 cqp_wqe->wqe_words[NES_CQP_ARP_WQE_MAC_HIGH_IDX] = 0;
3856 }
3857
3858 nes_debug(NES_DBG_NETDEV, "Not waiting for CQP, cqp.sq_head=%u, cqp.sq_tail=%u\n",
3859 nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
3860
3861 atomic_set(&cqp_request->refcount, 1);
8294f297 3862 nes_post_cqp_request(nesdev, cqp_request);
3c2d774c
GS		 3863}
3864
3865
3866/**
3867 * flush_wqes
3868 */
3869void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
3870 u32 which_wq, u32 wait_completion)
3871{
3c2d774c
GS		 3872 struct nes_cqp_request *cqp_request;
3873 struct nes_hw_cqp_wqe *cqp_wqe;
4b281fae
DW		 3874 u32 sq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3875 u32 rq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3c2d774c
GS		 3876 int ret;
3877
3878 cqp_request = nes_get_cqp_request(nesdev);
3879 if (cqp_request == NULL) {
3880 nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
3881 return;
3882 }
3883 if (wait_completion) {
3884 cqp_request->waiting = 1;
3885 atomic_set(&cqp_request->refcount, 2);
3886 } else {
3887 cqp_request->waiting = 0;
3888 }
3889 cqp_wqe = &cqp_request->cqp_wqe;
3890 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3891
4b281fae
DW		 3892 /* If wqe in error was identified, set code to be put into cqe */
3893 if ((nesqp->term_sq_flush_code) && (which_wq & NES_CQP_FLUSH_SQ)) {
3894 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3895 sq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_sq_flush_code;
3896 nesqp->term_sq_flush_code = 0;
3897 }
3898
3899 if ((nesqp->term_rq_flush_code) && (which_wq & NES_CQP_FLUSH_RQ)) {
3900 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3901 rq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_rq_flush_code;
3902 nesqp->term_rq_flush_code = 0;
3903 }
3904
3905 if (which_wq & NES_CQP_FLUSH_MAJ_MIN) {
3906 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_SQ_CODE] = cpu_to_le32(sq_code);
3907 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_RQ_CODE] = cpu_to_le32(rq_code);
3908 }
3909
3c2d774c
GS		 3910 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
3911 cpu_to_le32(NES_CQP_FLUSH_WQES | which_wq);
3912 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesqp->hwqp.qp_id);
3913
8294f297 3914 nes_post_cqp_request(nesdev, cqp_request);
3c2d774c
GS		 3915
3916 if (wait_completion) {
3917 /* Wait for CQP */
3918 ret = wait_event_timeout(cqp_request->waitq, (cqp_request->request_done != 0),
3919 NES_EVENT_TIMEOUT);
3920 nes_debug(NES_DBG_QP, "Flush SQ QP WQEs completed, ret=%u,"
3921 " CQP Major:Minor codes = 0x%04X:0x%04X\n",
3922 ret, cqp_request->major_code, cqp_request->minor_code);
1ff66e8c 3923 nes_put_cqp_request(nesdev, cqp_request);
3c2d774c
GS		 3924 }
3925}
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