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Merge branch 'sbp2-spindown' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee139...
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / nes / nes_utils.c
CommitLineData
3c2d774c
GS		 1/*
2 * Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
40#include <linux/if_vlan.h>
41#include <linux/crc32.h>
42#include <linux/in.h>
43#include <linux/ip.h>
44#include <linux/tcp.h>
45#include <linux/init.h>
46
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/byteorder.h>
50
51#include "nes.h"
52
53
54
55static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
56
57u32 mh_detected;
58u32 mh_pauses_sent;
59
60/**
61 * nes_read_eeprom_values -
62 */
63int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
64{
65 u32 mac_addr_low;
66 u16 mac_addr_high;
67 u16 eeprom_data;
68 u16 eeprom_offset;
69 u16 next_section_address;
70 u16 sw_section_ver;
71 u8 major_ver = 0;
72 u8 minor_ver = 0;
73
74 /* TODO: deal with EEPROM endian issues */
75 if (nesadapter->firmware_eeprom_offset == 0) {
76 /* Read the EEPROM Parameters */
77 eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
78 nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
79 eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
80 ((eeprom_data & 0x0080) >> 7));
81 nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
82 nesadapter->firmware_eeprom_offset = eeprom_offset;
83 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
84 if (eeprom_data != 0x5746) {
85 nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
86 return -1;
87 }
88
89 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
90 nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
91 eeprom_offset + 2, eeprom_data);
92 eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
93 nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
94 nesadapter->software_eeprom_offset = eeprom_offset;
95 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
96 if (eeprom_data != 0x5753) {
97 printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
98 return -1;
99 }
100 sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
101 nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
102 sw_section_ver);
103
104 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
105 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
106 eeprom_offset + 2, eeprom_data);
107 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
108 ((eeprom_data & 0x0100) >> 8));
109 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
110 if (eeprom_data != 0x414d) {
111 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
112 eeprom_data);
113 goto no_fw_rev;
114 }
115 eeprom_offset = next_section_address;
116
117 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
118 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
119 eeprom_offset + 2, eeprom_data);
120 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
121 ((eeprom_data & 0x0100) >> 8));
122 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
123 if (eeprom_data != 0x4f52) {
124 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
125 eeprom_data);
126 goto no_fw_rev;
127 }
128 eeprom_offset = next_section_address;
129
130 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
131 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
132 eeprom_offset + 2, eeprom_data);
133 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
134 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
135 if (eeprom_data != 0x5746) {
136 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
137 eeprom_data);
138 goto no_fw_rev;
139 }
140 eeprom_offset = next_section_address;
141
142 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
143 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
144 eeprom_offset + 2, eeprom_data);
145 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
146 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
147 if (eeprom_data != 0x5753) {
148 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
149 eeprom_data);
150 goto no_fw_rev;
151 }
152 eeprom_offset = next_section_address;
153
154 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
155 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
156 eeprom_offset + 2, eeprom_data);
157 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
158 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
159 if (eeprom_data != 0x414d) {
160 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
161 eeprom_data);
162 goto no_fw_rev;
163 }
164 eeprom_offset = next_section_address;
165
166 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
167 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
168 eeprom_offset + 2, eeprom_data);
169 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
170 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
171 if (eeprom_data != 0x464e) {
172 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
173 eeprom_data);
174 goto no_fw_rev;
175 }
176 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
177 printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
178 major_ver = (u8)(eeprom_data >> 8);
179 minor_ver = (u8)(eeprom_data);
180
181 if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
182 nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
183 } else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
184 nesadapter->virtwq = 1;
185 }
186 nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
187 (u32)((u8)eeprom_data);
188
189no_fw_rev:
190 /* eeprom is valid */
191 eeprom_offset = nesadapter->software_eeprom_offset;
192 eeprom_offset += 8;
193 nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
194 eeprom_offset += 2;
195 mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
196 eeprom_offset += 2;
197 mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
198 eeprom_offset += 2;
199 mac_addr_low <<= 16;
200 mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
201 nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
202 mac_addr_high, mac_addr_low);
203 nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
204
205 nesadapter->mac_addr_low = mac_addr_low;
206 nesadapter->mac_addr_high = mac_addr_high;
207
208 /* Read the Phy Type array */
209 eeprom_offset += 10;
210 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
211 nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
212 nesadapter->phy_type[1] = (u8)eeprom_data;
213
214 /* Read the port array */
215 eeprom_offset += 2;
216 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
217 nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
218 nesadapter->phy_type[3] = (u8)eeprom_data;
219 /* port_count is set by soft reset reg */
220 nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
221 " port 2 -> %u, port 3 -> %u\n",
222 nesadapter->port_count,
223 nesadapter->phy_type[0], nesadapter->phy_type[1],
224 nesadapter->phy_type[2], nesadapter->phy_type[3]);
225
226 /* Read PD config array */
227 eeprom_offset += 10;
228 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
229 nesadapter->pd_config_size[0] = eeprom_data;
230 eeprom_offset += 2;
231 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
232 nesadapter->pd_config_base[0] = eeprom_data;
233 nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
234 nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
235
236 eeprom_offset += 2;
237 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
238 nesadapter->pd_config_size[1] = eeprom_data;
239 eeprom_offset += 2;
240 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
241 nesadapter->pd_config_base[1] = eeprom_data;
242 nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
243 nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
244
245 eeprom_offset += 2;
246 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
247 nesadapter->pd_config_size[2] = eeprom_data;
248 eeprom_offset += 2;
249 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
250 nesadapter->pd_config_base[2] = eeprom_data;
251 nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
252 nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
253
254 eeprom_offset += 2;
255 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
256 nesadapter->pd_config_size[3] = eeprom_data;
257 eeprom_offset += 2;
258 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
259 nesadapter->pd_config_base[3] = eeprom_data;
260 nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
261 nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
262
263 /* Read Rx Pool Size */
264 eeprom_offset += 22; /* 46 */
265 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
266 eeprom_offset += 2;
267 nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
268 nes_read16_eeprom(nesdev->regs, eeprom_offset);
269 nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
270
271 eeprom_offset += 2;
272 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
273 eeprom_offset += 2;
274 nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
275 nes_read16_eeprom(nesdev->regs, eeprom_offset);
276 nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
277
278 eeprom_offset += 2;
279 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
280 eeprom_offset += 2;
281 nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
282 nes_read16_eeprom(nesdev->regs, eeprom_offset);
283 nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
284
285 eeprom_offset += 2;
286 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
287 eeprom_offset += 2;
288 nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
289 nes_read16_eeprom(nesdev->regs, eeprom_offset);
290 nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
291 nesadapter->tcp_timer_core_clk_divisor);
292
293 eeprom_offset += 2;
294 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
295 eeprom_offset += 2;
296 nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
297 nes_read16_eeprom(nesdev->regs, eeprom_offset);
298 nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
299
300 eeprom_offset += 2;
301 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
302 eeprom_offset += 2;
303 nesadapter->cm_config = (((u32)eeprom_data) << 16) +
304 nes_read16_eeprom(nesdev->regs, eeprom_offset);
305 nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
306
307 eeprom_offset += 2;
308 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
309 eeprom_offset += 2;
310 nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
311 nes_read16_eeprom(nesdev->regs, eeprom_offset);
312 nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
313
314 eeprom_offset += 2;
315 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
316 eeprom_offset += 2;
317 nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
318 nes_read16_eeprom(nesdev->regs, eeprom_offset);
319 nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
320
321 eeprom_offset += 2;
322 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
323 eeprom_offset += 2;
324 nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
325 nes_read16_eeprom(nesdev->regs, eeprom_offset);
326 nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
327
328 eeprom_offset += 2;
329 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
330 eeprom_offset += 2;
331 nesadapter->core_clock = (((u32)eeprom_data) << 16) +
332 nes_read16_eeprom(nesdev->regs, eeprom_offset);
333 nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
334
335 if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
336 eeprom_offset += 2;
337 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
338 nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
339 nesadapter->phy_index[1] = eeprom_data & 0x00ff;
340 eeprom_offset += 2;
341 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
342 nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
343 nesadapter->phy_index[3] = eeprom_data & 0x00ff;
344 } else {
345 nesadapter->phy_index[0] = 4;
346 nesadapter->phy_index[1] = 5;
347 nesadapter->phy_index[2] = 6;
348 nesadapter->phy_index[3] = 7;
349 }
350 nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
351 nesadapter->phy_index[0],nesadapter->phy_index[1],
352 nesadapter->phy_index[2],nesadapter->phy_index[3]);
353 }
354
355 return 0;
356}
357
358
359/**
360 * nes_read16_eeprom
361 */
362static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
363{
364 writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
365 (void __iomem *)addr + NES_EEPROM_COMMAND);
366
367 do {
368 } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
369 NES_EEPROM_READ_REQUEST);
370
371 return readw((void __iomem *)addr + NES_EEPROM_DATA);
372}
373
374
375/**
376 * nes_write_1G_phy_reg
377 */
378void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
379{
380 struct nes_adapter *nesadapter = nesdev->nesadapter;
381 u32 u32temp;
382 u32 counter;
383 unsigned long flags;
384
385 spin_lock_irqsave(&nesadapter->phy_lock, flags);
386
387 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
388 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
389 for (counter = 0; counter < 100 ; counter++) {
390 udelay(30);
391 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
392 if (u32temp & 1) {
393 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
394 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
395 break;
396 }
397 }
398 if (!(u32temp & 1))
399 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
400 u32temp);
401
402 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
403}
404
405
406/**
407 * nes_read_1G_phy_reg
408 * This routine only issues the read, the data must be read
409 * separately.
410 */
411void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
412{
413 struct nes_adapter *nesadapter = nesdev->nesadapter;
414 u32 u32temp;
415 u32 counter;
416 unsigned long flags;
417
418 /* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
419 phy_addr, nesdev->mac_index); */
420 spin_lock_irqsave(&nesadapter->phy_lock, flags);
421
422 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
423 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
424 for (counter = 0; counter < 100 ; counter++) {
425 udelay(30);
426 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
427 if (u32temp & 1) {
428 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
429 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
430 break;
431 }
432 }
433 if (!(u32temp & 1)) {
434 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
435 u32temp);
436 *data = 0xffff;
437 } else {
438 *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
439 }
440 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
441}
442
443
444/**
445 * nes_write_10G_phy_reg
446 */
0e1de5d6
ES		 447void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
448 u16 data)
3c2d774c 449{
3c2d774c
GS		 450 u32 port_addr;
451 u32 u32temp;
452 u32 counter;
453
3c2d774c
GS		 454 port_addr = phy_addr;
455
456 /* set address */
457 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
458 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
459 for (counter = 0; counter < 100 ; counter++) {
460 udelay(30);
461 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
462 if (u32temp & 1) {
463 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
464 break;
465 }
466 }
467 if (!(u32temp & 1))
468 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
469 u32temp);
470
471 /* set data */
472 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
473 0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
474 for (counter = 0; counter < 100 ; counter++) {
475 udelay(30);
476 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
477 if (u32temp & 1) {
478 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
479 break;
480 }
481 }
482 if (!(u32temp & 1))
483 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
484 u32temp);
485}
486
487
488/**
489 * nes_read_10G_phy_reg
490 * This routine only issues the read, the data must be read
491 * separately.
492 */
0e1de5d6 493void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
3c2d774c 494{
3c2d774c
GS		 495 u32 port_addr;
496 u32 u32temp;
497 u32 counter;
498
3c2d774c
GS		 499 port_addr = phy_addr;
500
501 /* set address */
502 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
503 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
504 for (counter = 0; counter < 100 ; counter++) {
505 udelay(30);
506 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
507 if (u32temp & 1) {
508 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
509 break;
510 }
511 }
512 if (!(u32temp & 1))
513 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
514 u32temp);
515
516 /* issue read */
517 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
518 0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
519 for (counter = 0; counter < 100 ; counter++) {
520 udelay(30);
521 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
522 if (u32temp & 1) {
523 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
524 break;
525 }
526 }
527 if (!(u32temp & 1))
528 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
529 u32temp);
530}
531
532
533/**
534 * nes_get_cqp_request
535 */
536struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
537{
538 unsigned long flags;
539 struct nes_cqp_request *cqp_request = NULL;
540
541 if (!list_empty(&nesdev->cqp_avail_reqs)) {
542 spin_lock_irqsave(&nesdev->cqp.lock, flags);
543 cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
544 struct nes_cqp_request, list);
545 list_del_init(&cqp_request->list);
546 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
547 } else {
548 cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_KERNEL);
549 if (cqp_request) {
550 cqp_request->dynamic = 1;
551 INIT_LIST_HEAD(&cqp_request->list);
552 }
553 }
554
555 if (cqp_request) {
556 init_waitqueue_head(&cqp_request->waitq);
557 cqp_request->waiting = 0;
558 cqp_request->request_done = 0;
559 cqp_request->callback = 0;
560 init_waitqueue_head(&cqp_request->waitq);
561 nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
562 cqp_request);
563 } else
564 printk(KERN_ERR PFX "%s: Could not allocated a CQP request.\n",
33718363 565 __func__);
3c2d774c
GS		 566
567 return cqp_request;
568}
569
1ff66e8c
RD		 570void nes_free_cqp_request(struct nes_device *nesdev,
571 struct nes_cqp_request *cqp_request)
572{
573 unsigned long flags;
574
575 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
576 cqp_request,
577 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
578
579 if (cqp_request->dynamic) {
580 kfree(cqp_request);
581 } else {
582 spin_lock_irqsave(&nesdev->cqp.lock, flags);
583 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
584 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
585 }
586}
587
588void nes_put_cqp_request(struct nes_device *nesdev,
589 struct nes_cqp_request *cqp_request)
590{
591 if (atomic_dec_and_test(&cqp_request->refcount))
592 nes_free_cqp_request(nesdev, cqp_request);
593}
3c2d774c
GS		 594
595/**
596 * nes_post_cqp_request
597 */
598void nes_post_cqp_request(struct nes_device *nesdev,
8294f297 599 struct nes_cqp_request *cqp_request)
3c2d774c
GS		 600{
601 struct nes_hw_cqp_wqe *cqp_wqe;
602 unsigned long flags;
603 u32 cqp_head;
604 u64 u64temp;
605
606 spin_lock_irqsave(&nesdev->cqp.lock, flags);
607
608 if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
609 (nesdev->cqp.sq_size - 1)) != 1)
610 && (list_empty(&nesdev->cqp_pending_reqs))) {
611 cqp_head = nesdev->cqp.sq_head++;
612 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
613 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
614 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
615 barrier();
616 u64temp = (unsigned long)cqp_request;
617 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_SCRATCH_LOW_IDX,
618 u64temp);
619 nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
620 " request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
621 " waiting = %d, refcount = %d.\n",
622 le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
623 le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
624 nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
625 cqp_request->waiting, atomic_read(&cqp_request->refcount));
626 barrier();
8294f297
RD		 627
628 /* Ring doorbell (1 WQEs) */
629 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
3c2d774c
GS		 630
631 barrier();
632 } else {
633 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
634 " put on the pending queue.\n",
635 cqp_request,
636 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
637 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
638 list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
639 }
640
641 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
642
643 return;
644}
645
646
647/**
648 * nes_arp_table
649 */
650int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
651{
652 struct nes_adapter *nesadapter = nesdev->nesadapter;
653 int arp_index;
654 int err = 0;
655
656 for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
657 if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
658 break;
659 }
660
661 if (action == NES_ARP_ADD) {
662 if (arp_index != nesadapter->arp_table_size) {
663 return -1;
664 }
665
666 arp_index = 0;
667 err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
668 nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index);
669 if (err) {
670 nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
671 return err;
672 }
673 nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
674
675 nesadapter->arp_table[arp_index].ip_addr = ip_addr;
676 memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
677 return arp_index;
678 }
679
680 /* DELETE or RESOLVE */
681 if (arp_index == nesadapter->arp_table_size) {
e4477031
RD		 682 nes_debug(NES_DBG_NETDEV, "MAC for " NIPQUAD_FMT " not in ARP table - cannot %s\n",
683 HIPQUAD(ip_addr),
684 action == NES_ARP_RESOLVE ? "resolve" : "delete");
3c2d774c
GS		 685 return -1;
686 }
687
688 if (action == NES_ARP_RESOLVE) {
689 nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
690 return arp_index;
691 }
692
693 if (action == NES_ARP_DELETE) {
694 nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
695 nesadapter->arp_table[arp_index].ip_addr = 0;
696 memset(nesadapter->arp_table[arp_index].mac_addr, 0x00, ETH_ALEN);
697 nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
698 return arp_index;
699 }
700
701 return -1;
702}
703
704
705/**
706 * nes_mh_fix
707 */
708void nes_mh_fix(unsigned long parm)
709{
710 unsigned long flags;
711 struct nes_device *nesdev = (struct nes_device *)parm;
712 struct nes_adapter *nesadapter = nesdev->nesadapter;
713 struct nes_vnic *nesvnic;
714 u32 used_chunks_tx;
715 u32 temp_used_chunks_tx;
716 u32 temp_last_used_chunks_tx;
717 u32 used_chunks_mask;
718 u32 mac_tx_frames_low;
719 u32 mac_tx_frames_high;
720 u32 mac_tx_pauses;
721 u32 serdes_status;
722 u32 reset_value;
723 u32 tx_control;
724 u32 tx_config;
725 u32 tx_pause_quanta;
726 u32 rx_control;
727 u32 rx_config;
728 u32 mac_exact_match;
729 u32 mpp_debug;
730 u32 i=0;
731 u32 chunks_tx_progress = 0;
732
733 spin_lock_irqsave(&nesadapter->phy_lock, flags);
734 if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
735 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
736 goto no_mh_work;
737 }
738 nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
739 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
740 do {
741 mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
742 mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
743 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
744 used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
745 nesdev->mac_pause_frames_sent += mac_tx_pauses;
746 used_chunks_mask = 0;
747 temp_used_chunks_tx = used_chunks_tx;
748 temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
749
750 if (nesdev->netdev[0]) {
751 nesvnic = netdev_priv(nesdev->netdev[0]);
752 } else {
753 break;
754 }
755
756 for (i=0; i<4; i++) {
757 used_chunks_mask <<= 8;
758 if (nesvnic->qp_nic_index[i] != 0xff) {
759 used_chunks_mask |= 0xff;
760 if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
761 chunks_tx_progress = 1;
762 }
763 }
764 temp_used_chunks_tx >>= 8;
765 temp_last_used_chunks_tx >>= 8;
766 }
767 if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
768 (!(used_chunks_tx&used_chunks_mask)) ||
769 (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
770 (chunks_tx_progress) ) {
771 nesdev->last_used_chunks_tx = used_chunks_tx;
772 break;
773 }
774 nesdev->last_used_chunks_tx = used_chunks_tx;
775 barrier();
776
777 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
778 mh_pauses_sent++;
779 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
780 if (mac_tx_pauses) {
781 nesdev->mac_pause_frames_sent += mac_tx_pauses;
782 break;
783 }
784
785 tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
786 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
787 tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
788 rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
789 rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
790 mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
791 mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
792
793 /* one last ditch effort to avoid a false positive */
794 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
795 if (mac_tx_pauses) {
796 nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
797 nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
798 break;
799 }
800 mh_detected++;
801
802 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
803 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
804 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
805
806 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
807
808 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
809 & 0x00000040) != 0x00000040) && (i++ < 5000)) {
810 /* mdelay(1); */
811 }
812
813 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
814 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
815
816 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
817 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
818 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
819 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
820 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
821 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
822 if (nesadapter->OneG_Mode) {
823 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
824 } else {
825 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
826 }
827 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
828 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
829
830 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
831 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
832 nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
833 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
834 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
835 nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
836 nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
837
838 } while (0);
839
840 nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
841no_mh_work:
842 nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
843 add_timer(&nesdev->nesadapter->mh_timer);
844}
845
846/**
847 * nes_clc
848 */
849void nes_clc(unsigned long parm)
850{
851 unsigned long flags;
852 struct nes_device *nesdev = (struct nes_device *)parm;
853 struct nes_adapter *nesadapter = nesdev->nesadapter;
854
855 spin_lock_irqsave(&nesadapter->phy_lock, flags);
856 nesadapter->link_interrupt_count[0] = 0;
857 nesadapter->link_interrupt_count[1] = 0;
858 nesadapter->link_interrupt_count[2] = 0;
859 nesadapter->link_interrupt_count[3] = 0;
860 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
861
862 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
863 add_timer(&nesadapter->lc_timer);
864}
865
866
867/**
868 * nes_dump_mem
869 */
870void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
871{
872 char xlate[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
873 'a', 'b', 'c', 'd', 'e', 'f'};
874 char *ptr;
875 char hex_buf[80];
876 char ascii_buf[20];
877 int num_char;
878 int num_ascii;
879 int num_hex;
880
881 if (!(nes_debug_level & dump_debug_level)) {
882 return;
883 }
884
885 ptr = addr;
886 if (length > 0x100) {
887 nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
888 length = 0x100;
889 }
890 nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", ptr, length, length);
891
892 memset(ascii_buf, 0, 20);
893 memset(hex_buf, 0, 80);
894
895 num_ascii = 0;
896 num_hex = 0;
897 for (num_char = 0; num_char < length; num_char++) {
898 if (num_ascii == 8) {
899 ascii_buf[num_ascii++] = ' ';
900 hex_buf[num_hex++] = '-';
901 hex_buf[num_hex++] = ' ';
902 }
903
904 if (*ptr < 0x20 || *ptr > 0x7e)
905 ascii_buf[num_ascii++] = '.';
906 else
907 ascii_buf[num_ascii++] = *ptr;
908 hex_buf[num_hex++] = xlate[((*ptr & 0xf0) >> 4)];
909 hex_buf[num_hex++] = xlate[*ptr & 0x0f];
910 hex_buf[num_hex++] = ' ';
911 ptr++;
912
913 if (num_ascii >= 17) {
914 /* output line and reset */
915 nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
916 memset(ascii_buf, 0, 20);
917 memset(hex_buf, 0, 80);
918 num_ascii = 0;
919 num_hex = 0;
920 }
921 }
922
923 /* output the rest */
924 if (num_ascii) {
925 while (num_ascii < 17) {
926 if (num_ascii == 8) {
927 hex_buf[num_hex++] = ' ';
928 hex_buf[num_hex++] = ' ';
929 }
930 hex_buf[num_hex++] = ' ';
931 hex_buf[num_hex++] = ' ';
932 hex_buf[num_hex++] = ' ';
933 num_ascii++;
934 }
935
936 nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
937 }
938}
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