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RDMA/nes: Convert pci_table entries to PCI_VDEVICE
[mirror_ubuntu-zesty-kernel.git] / drivers / infiniband / hw / nes / nes_utils.c
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3c2d774c 1/*
fa6c87d5 2 * Copyright (c) 2006 - 2009 Intel Corporation. All rights reserved.
3c2d774c
GS		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
40#include <linux/if_vlan.h>
5a0e3ad6 41#include <linux/slab.h>
3c2d774c
GS		 42#include <linux/crc32.h>
43#include <linux/in.h>
44#include <linux/ip.h>
45#include <linux/tcp.h>
46#include <linux/init.h>
47
48#include <asm/io.h>
49#include <asm/irq.h>
50#include <asm/byteorder.h>
51
52#include "nes.h"
53
54
55
56static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
57
58u32 mh_detected;
59u32 mh_pauses_sent;
60
61/**
62 * nes_read_eeprom_values -
63 */
64int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
65{
66 u32 mac_addr_low;
67 u16 mac_addr_high;
68 u16 eeprom_data;
69 u16 eeprom_offset;
70 u16 next_section_address;
71 u16 sw_section_ver;
72 u8 major_ver = 0;
73 u8 minor_ver = 0;
74
75 /* TODO: deal with EEPROM endian issues */
76 if (nesadapter->firmware_eeprom_offset == 0) {
77 /* Read the EEPROM Parameters */
78 eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
79 nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
80 eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
81 ((eeprom_data & 0x0080) >> 7));
82 nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
83 nesadapter->firmware_eeprom_offset = eeprom_offset;
84 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
85 if (eeprom_data != 0x5746) {
86 nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
87 return -1;
88 }
89
90 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
91 nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
92 eeprom_offset + 2, eeprom_data);
93 eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
94 nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
95 nesadapter->software_eeprom_offset = eeprom_offset;
96 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
97 if (eeprom_data != 0x5753) {
98 printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
99 return -1;
100 }
101 sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
102 nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
103 sw_section_ver);
104
105 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
106 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
107 eeprom_offset + 2, eeprom_data);
108 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
109 ((eeprom_data & 0x0100) >> 8));
110 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
111 if (eeprom_data != 0x414d) {
112 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
113 eeprom_data);
114 goto no_fw_rev;
115 }
116 eeprom_offset = next_section_address;
117
118 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
119 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
120 eeprom_offset + 2, eeprom_data);
121 next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
122 ((eeprom_data & 0x0100) >> 8));
123 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
124 if (eeprom_data != 0x4f52) {
125 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
126 eeprom_data);
127 goto no_fw_rev;
128 }
129 eeprom_offset = next_section_address;
130
131 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
132 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
133 eeprom_offset + 2, eeprom_data);
134 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
135 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
136 if (eeprom_data != 0x5746) {
137 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
138 eeprom_data);
139 goto no_fw_rev;
140 }
141 eeprom_offset = next_section_address;
142
143 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
144 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
145 eeprom_offset + 2, eeprom_data);
146 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
147 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
148 if (eeprom_data != 0x5753) {
149 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
150 eeprom_data);
151 goto no_fw_rev;
152 }
153 eeprom_offset = next_section_address;
154
155 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
156 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
157 eeprom_offset + 2, eeprom_data);
158 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
159 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
160 if (eeprom_data != 0x414d) {
161 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
162 eeprom_data);
163 goto no_fw_rev;
164 }
165 eeprom_offset = next_section_address;
166
167 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
168 nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
169 eeprom_offset + 2, eeprom_data);
170 next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
171 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
172 if (eeprom_data != 0x464e) {
173 nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
174 eeprom_data);
175 goto no_fw_rev;
176 }
177 eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
178 printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
179 major_ver = (u8)(eeprom_data >> 8);
180 minor_ver = (u8)(eeprom_data);
181
182 if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
183 nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
184 } else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
185 nesadapter->virtwq = 1;
186 }
8b1c9dc4
DW		 187 if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
188 nesadapter->send_term_ok = 1;
189
3c2d774c
GS		 190 nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
191 (u32)((u8)eeprom_data);
192
193no_fw_rev:
194 /* eeprom is valid */
195 eeprom_offset = nesadapter->software_eeprom_offset;
196 eeprom_offset += 8;
197 nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
198 eeprom_offset += 2;
199 mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
200 eeprom_offset += 2;
201 mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
202 eeprom_offset += 2;
203 mac_addr_low <<= 16;
204 mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
205 nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
206 mac_addr_high, mac_addr_low);
207 nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
208
209 nesadapter->mac_addr_low = mac_addr_low;
210 nesadapter->mac_addr_high = mac_addr_high;
211
212 /* Read the Phy Type array */
213 eeprom_offset += 10;
214 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
215 nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
216 nesadapter->phy_type[1] = (u8)eeprom_data;
217
218 /* Read the port array */
219 eeprom_offset += 2;
220 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
221 nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
222 nesadapter->phy_type[3] = (u8)eeprom_data;
223 /* port_count is set by soft reset reg */
224 nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
225 " port 2 -> %u, port 3 -> %u\n",
226 nesadapter->port_count,
227 nesadapter->phy_type[0], nesadapter->phy_type[1],
228 nesadapter->phy_type[2], nesadapter->phy_type[3]);
229
230 /* Read PD config array */
231 eeprom_offset += 10;
232 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
233 nesadapter->pd_config_size[0] = eeprom_data;
234 eeprom_offset += 2;
235 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
236 nesadapter->pd_config_base[0] = eeprom_data;
237 nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
238 nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
239
240 eeprom_offset += 2;
241 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
242 nesadapter->pd_config_size[1] = eeprom_data;
243 eeprom_offset += 2;
244 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
245 nesadapter->pd_config_base[1] = eeprom_data;
246 nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
247 nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
248
249 eeprom_offset += 2;
250 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
251 nesadapter->pd_config_size[2] = eeprom_data;
252 eeprom_offset += 2;
253 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
254 nesadapter->pd_config_base[2] = eeprom_data;
255 nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
256 nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
257
258 eeprom_offset += 2;
259 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
260 nesadapter->pd_config_size[3] = eeprom_data;
261 eeprom_offset += 2;
262 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
263 nesadapter->pd_config_base[3] = eeprom_data;
264 nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
265 nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
266
267 /* Read Rx Pool Size */
268 eeprom_offset += 22; /* 46 */
269 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
270 eeprom_offset += 2;
271 nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
272 nes_read16_eeprom(nesdev->regs, eeprom_offset);
273 nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
274
275 eeprom_offset += 2;
276 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
277 eeprom_offset += 2;
278 nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
279 nes_read16_eeprom(nesdev->regs, eeprom_offset);
280 nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
281
282 eeprom_offset += 2;
283 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
284 eeprom_offset += 2;
285 nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
286 nes_read16_eeprom(nesdev->regs, eeprom_offset);
287 nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
288
289 eeprom_offset += 2;
290 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
291 eeprom_offset += 2;
292 nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
293 nes_read16_eeprom(nesdev->regs, eeprom_offset);
294 nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
295 nesadapter->tcp_timer_core_clk_divisor);
296
297 eeprom_offset += 2;
298 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
299 eeprom_offset += 2;
300 nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
301 nes_read16_eeprom(nesdev->regs, eeprom_offset);
302 nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
303
304 eeprom_offset += 2;
305 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
306 eeprom_offset += 2;
307 nesadapter->cm_config = (((u32)eeprom_data) << 16) +
308 nes_read16_eeprom(nesdev->regs, eeprom_offset);
309 nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
310
311 eeprom_offset += 2;
312 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
313 eeprom_offset += 2;
314 nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
315 nes_read16_eeprom(nesdev->regs, eeprom_offset);
316 nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
317
318 eeprom_offset += 2;
319 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
320 eeprom_offset += 2;
321 nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
322 nes_read16_eeprom(nesdev->regs, eeprom_offset);
323 nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
324
325 eeprom_offset += 2;
326 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
327 eeprom_offset += 2;
328 nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
329 nes_read16_eeprom(nesdev->regs, eeprom_offset);
330 nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
331
332 eeprom_offset += 2;
333 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
334 eeprom_offset += 2;
335 nesadapter->core_clock = (((u32)eeprom_data) << 16) +
336 nes_read16_eeprom(nesdev->regs, eeprom_offset);
337 nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
338
339 if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
340 eeprom_offset += 2;
341 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
342 nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
343 nesadapter->phy_index[1] = eeprom_data & 0x00ff;
344 eeprom_offset += 2;
345 eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
346 nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
347 nesadapter->phy_index[3] = eeprom_data & 0x00ff;
348 } else {
349 nesadapter->phy_index[0] = 4;
350 nesadapter->phy_index[1] = 5;
351 nesadapter->phy_index[2] = 6;
352 nesadapter->phy_index[3] = 7;
353 }
354 nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
355 nesadapter->phy_index[0],nesadapter->phy_index[1],
356 nesadapter->phy_index[2],nesadapter->phy_index[3]);
357 }
358
359 return 0;
360}
361
362
363/**
364 * nes_read16_eeprom
365 */
366static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
367{
368 writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
369 (void __iomem *)addr + NES_EEPROM_COMMAND);
370
371 do {
372 } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
373 NES_EEPROM_READ_REQUEST);
374
375 return readw((void __iomem *)addr + NES_EEPROM_DATA);
376}
377
378
379/**
380 * nes_write_1G_phy_reg
381 */
382void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
383{
3c2d774c
GS		 384 u32 u32temp;
385 u32 counter;
3c2d774c
GS		 386
387 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
388 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
389 for (counter = 0; counter < 100 ; counter++) {
390 udelay(30);
391 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
392 if (u32temp & 1) {
393 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
394 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
395 break;
396 }
397 }
398 if (!(u32temp & 1))
399 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
400 u32temp);
3c2d774c
GS		 401}
402
403
404/**
405 * nes_read_1G_phy_reg
406 * This routine only issues the read, the data must be read
407 * separately.
408 */
409void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
410{
3c2d774c
GS		 411 u32 u32temp;
412 u32 counter;
3c2d774c
GS		 413
414 /* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
415 phy_addr, nesdev->mac_index); */
3c2d774c
GS		 416
417 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
418 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
419 for (counter = 0; counter < 100 ; counter++) {
420 udelay(30);
421 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
422 if (u32temp & 1) {
423 /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
424 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
425 break;
426 }
427 }
428 if (!(u32temp & 1)) {
429 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
430 u32temp);
431 *data = 0xffff;
432 } else {
433 *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
434 }
3c2d774c
GS		 435}
436
437
438/**
439 * nes_write_10G_phy_reg
440 */
0e1de5d6
ES		 441void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
442 u16 data)
3c2d774c 443{
3c2d774c
GS		 444 u32 port_addr;
445 u32 u32temp;
446 u32 counter;
447
3c2d774c
GS		 448 port_addr = phy_addr;
449
450 /* set address */
451 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
452 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
453 for (counter = 0; counter < 100 ; counter++) {
454 udelay(30);
455 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
456 if (u32temp & 1) {
457 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
458 break;
459 }
460 }
461 if (!(u32temp & 1))
462 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
463 u32temp);
464
465 /* set data */
466 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
467 0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
468 for (counter = 0; counter < 100 ; counter++) {
469 udelay(30);
470 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
471 if (u32temp & 1) {
472 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
473 break;
474 }
475 }
476 if (!(u32temp & 1))
477 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
478 u32temp);
479}
480
481
482/**
483 * nes_read_10G_phy_reg
484 * This routine only issues the read, the data must be read
485 * separately.
486 */
0e1de5d6 487void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
3c2d774c 488{
3c2d774c
GS		 489 u32 port_addr;
490 u32 u32temp;
491 u32 counter;
492
3c2d774c
GS		 493 port_addr = phy_addr;
494
495 /* set address */
496 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
497 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
498 for (counter = 0; counter < 100 ; counter++) {
499 udelay(30);
500 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
501 if (u32temp & 1) {
502 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
503 break;
504 }
505 }
506 if (!(u32temp & 1))
507 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
508 u32temp);
509
510 /* issue read */
511 nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
512 0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
513 for (counter = 0; counter < 100 ; counter++) {
514 udelay(30);
515 u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
516 if (u32temp & 1) {
517 nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
518 break;
519 }
520 }
521 if (!(u32temp & 1))
522 nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
523 u32temp);
524}
525
526
527/**
528 * nes_get_cqp_request
529 */
530struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
531{
532 unsigned long flags;
533 struct nes_cqp_request *cqp_request = NULL;
534
535 if (!list_empty(&nesdev->cqp_avail_reqs)) {
536 spin_lock_irqsave(&nesdev->cqp.lock, flags);
f3181a10
FL		 537 if (!list_empty(&nesdev->cqp_avail_reqs)) {
538 cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
3c2d774c 539 struct nes_cqp_request, list);
f3181a10
FL		 540 list_del_init(&cqp_request->list);
541 }
3c2d774c 542 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
f3181a10
FL		 543 }
544 if (cqp_request == NULL) {
ba0c5d9a 545 cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
3c2d774c
GS		 546 if (cqp_request) {
547 cqp_request->dynamic = 1;
548 INIT_LIST_HEAD(&cqp_request->list);
549 }
550 }
551
552 if (cqp_request) {
553 init_waitqueue_head(&cqp_request->waitq);
554 cqp_request->waiting = 0;
555 cqp_request->request_done = 0;
556 cqp_request->callback = 0;
557 init_waitqueue_head(&cqp_request->waitq);
558 nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
559 cqp_request);
560 } else
561 printk(KERN_ERR PFX "%s: Could not allocated a CQP request.\n",
33718363 562 __func__);
3c2d774c
GS		 563
564 return cqp_request;
565}
566
1ff66e8c
RD		 567void nes_free_cqp_request(struct nes_device *nesdev,
568 struct nes_cqp_request *cqp_request)
569{
570 unsigned long flags;
571
572 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
573 cqp_request,
574 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
575
576 if (cqp_request->dynamic) {
577 kfree(cqp_request);
578 } else {
579 spin_lock_irqsave(&nesdev->cqp.lock, flags);
580 list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
581 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
582 }
583}
584
585void nes_put_cqp_request(struct nes_device *nesdev,
586 struct nes_cqp_request *cqp_request)
587{
588 if (atomic_dec_and_test(&cqp_request->refcount))
589 nes_free_cqp_request(nesdev, cqp_request);
590}
3c2d774c
GS		 591
592/**
593 * nes_post_cqp_request
594 */
595void nes_post_cqp_request(struct nes_device *nesdev,
8294f297 596 struct nes_cqp_request *cqp_request)
3c2d774c
GS		 597{
598 struct nes_hw_cqp_wqe *cqp_wqe;
599 unsigned long flags;
600 u32 cqp_head;
601 u64 u64temp;
602
603 spin_lock_irqsave(&nesdev->cqp.lock, flags);
604
605 if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
606 (nesdev->cqp.sq_size - 1)) != 1)
607 && (list_empty(&nesdev->cqp_pending_reqs))) {
608 cqp_head = nesdev->cqp.sq_head++;
609 nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
610 cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
611 memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
612 barrier();
613 u64temp = (unsigned long)cqp_request;
614 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_SCRATCH_LOW_IDX,
615 u64temp);
616 nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
617 " request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
618 " waiting = %d, refcount = %d.\n",
619 le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
620 le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
621 nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
622 cqp_request->waiting, atomic_read(&cqp_request->refcount));
623 barrier();
8294f297
RD		 624
625 /* Ring doorbell (1 WQEs) */
626 nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
3c2d774c
GS		 627
628 barrier();
629 } else {
630 nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
631 " put on the pending queue.\n",
632 cqp_request,
633 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
634 le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
635 list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
636 }
637
638 spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
639
640 return;
641}
642
643
644/**
645 * nes_arp_table
646 */
647int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
648{
649 struct nes_adapter *nesadapter = nesdev->nesadapter;
650 int arp_index;
651 int err = 0;
03080e5c 652 __be32 tmp_addr;
3c2d774c
GS		 653
654 for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
655 if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
656 break;
657 }
658
659 if (action == NES_ARP_ADD) {
660 if (arp_index != nesadapter->arp_table_size) {
661 return -1;
662 }
663
664 arp_index = 0;
665 err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
666 nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index);
667 if (err) {
668 nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
669 return err;
670 }
671 nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
672
673 nesadapter->arp_table[arp_index].ip_addr = ip_addr;
674 memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
675 return arp_index;
676 }
677
678 /* DELETE or RESOLVE */
679 if (arp_index == nesadapter->arp_table_size) {
03080e5c 680 tmp_addr = cpu_to_be32(ip_addr);
63779436 681 nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
03080e5c 682 &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
3c2d774c
GS		 683 return -1;
684 }
685
686 if (action == NES_ARP_RESOLVE) {
687 nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
688 return arp_index;
689 }
690
691 if (action == NES_ARP_DELETE) {
692 nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
693 nesadapter->arp_table[arp_index].ip_addr = 0;
694 memset(nesadapter->arp_table[arp_index].mac_addr, 0x00, ETH_ALEN);
695 nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
696 return arp_index;
697 }
698
699 return -1;
700}
701
702
703/**
704 * nes_mh_fix
705 */
706void nes_mh_fix(unsigned long parm)
707{
708 unsigned long flags;
709 struct nes_device *nesdev = (struct nes_device *)parm;
710 struct nes_adapter *nesadapter = nesdev->nesadapter;
711 struct nes_vnic *nesvnic;
712 u32 used_chunks_tx;
713 u32 temp_used_chunks_tx;
714 u32 temp_last_used_chunks_tx;
715 u32 used_chunks_mask;
716 u32 mac_tx_frames_low;
717 u32 mac_tx_frames_high;
718 u32 mac_tx_pauses;
719 u32 serdes_status;
720 u32 reset_value;
721 u32 tx_control;
722 u32 tx_config;
723 u32 tx_pause_quanta;
724 u32 rx_control;
725 u32 rx_config;
726 u32 mac_exact_match;
727 u32 mpp_debug;
728 u32 i=0;
729 u32 chunks_tx_progress = 0;
730
731 spin_lock_irqsave(&nesadapter->phy_lock, flags);
732 if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
733 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
734 goto no_mh_work;
735 }
736 nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
737 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
738 do {
739 mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
740 mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
741 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
742 used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
743 nesdev->mac_pause_frames_sent += mac_tx_pauses;
744 used_chunks_mask = 0;
745 temp_used_chunks_tx = used_chunks_tx;
746 temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
747
748 if (nesdev->netdev[0]) {
749 nesvnic = netdev_priv(nesdev->netdev[0]);
750 } else {
751 break;
752 }
753
754 for (i=0; i<4; i++) {
755 used_chunks_mask <<= 8;
756 if (nesvnic->qp_nic_index[i] != 0xff) {
757 used_chunks_mask |= 0xff;
758 if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
759 chunks_tx_progress = 1;
760 }
761 }
762 temp_used_chunks_tx >>= 8;
763 temp_last_used_chunks_tx >>= 8;
764 }
765 if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
766 (!(used_chunks_tx&used_chunks_mask)) ||
767 (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
768 (chunks_tx_progress) ) {
769 nesdev->last_used_chunks_tx = used_chunks_tx;
770 break;
771 }
772 nesdev->last_used_chunks_tx = used_chunks_tx;
773 barrier();
774
775 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
776 mh_pauses_sent++;
777 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
778 if (mac_tx_pauses) {
779 nesdev->mac_pause_frames_sent += mac_tx_pauses;
780 break;
781 }
782
783 tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
784 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
785 tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
786 rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
787 rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
788 mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
789 mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
790
791 /* one last ditch effort to avoid a false positive */
792 mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
793 if (mac_tx_pauses) {
794 nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
795 nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
796 break;
797 }
798 mh_detected++;
799
800 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
801 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
802 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
803
804 nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
805
806 while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
807 & 0x00000040) != 0x00000040) && (i++ < 5000)) {
808 /* mdelay(1); */
809 }
810
811 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
812 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
813
814 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
815 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
816 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
817 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
818 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
819 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
820 if (nesadapter->OneG_Mode) {
821 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
822 } else {
823 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
824 }
825 serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
826 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
827
828 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
829 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
830 nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
831 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
832 nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
833 nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
834 nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
835
836 } while (0);
837
838 nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
839no_mh_work:
840 nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
841 add_timer(&nesdev->nesadapter->mh_timer);
842}
843
844/**
845 * nes_clc
846 */
847void nes_clc(unsigned long parm)
848{
849 unsigned long flags;
850 struct nes_device *nesdev = (struct nes_device *)parm;
851 struct nes_adapter *nesadapter = nesdev->nesadapter;
852
853 spin_lock_irqsave(&nesadapter->phy_lock, flags);
854 nesadapter->link_interrupt_count[0] = 0;
855 nesadapter->link_interrupt_count[1] = 0;
856 nesadapter->link_interrupt_count[2] = 0;
857 nesadapter->link_interrupt_count[3] = 0;
858 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
859
860 nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
861 add_timer(&nesadapter->lc_timer);
862}
863
864
865/**
866 * nes_dump_mem
867 */
868void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
869{
870 char xlate[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
871 'a', 'b', 'c', 'd', 'e', 'f'};
872 char *ptr;
873 char hex_buf[80];
874 char ascii_buf[20];
875 int num_char;
876 int num_ascii;
877 int num_hex;
878
879 if (!(nes_debug_level & dump_debug_level)) {
880 return;
881 }
882
883 ptr = addr;
884 if (length > 0x100) {
885 nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
886 length = 0x100;
887 }
888 nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", ptr, length, length);
889
890 memset(ascii_buf, 0, 20);
891 memset(hex_buf, 0, 80);
892
893 num_ascii = 0;
894 num_hex = 0;
895 for (num_char = 0; num_char < length; num_char++) {
896 if (num_ascii == 8) {
897 ascii_buf[num_ascii++] = ' ';
898 hex_buf[num_hex++] = '-';
899 hex_buf[num_hex++] = ' ';
900 }
901
902 if (*ptr < 0x20 || *ptr > 0x7e)
903 ascii_buf[num_ascii++] = '.';
904 else
905 ascii_buf[num_ascii++] = *ptr;
906 hex_buf[num_hex++] = xlate[((*ptr & 0xf0) >> 4)];
907 hex_buf[num_hex++] = xlate[*ptr & 0x0f];
908 hex_buf[num_hex++] = ' ';
909 ptr++;
910
911 if (num_ascii >= 17) {
912 /* output line and reset */
913 nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
914 memset(ascii_buf, 0, 20);
915 memset(hex_buf, 0, 80);
916 num_ascii = 0;
917 num_hex = 0;
918 }
919 }
920
921 /* output the rest */
922 if (num_ascii) {
923 while (num_ascii < 17) {
924 if (num_ascii == 8) {
925 hex_buf[num_hex++] = ' ';
926 hex_buf[num_hex++] = ' ';
927 }
928 hex_buf[num_hex++] = ' ';
929 hex_buf[num_hex++] = ' ';
930 hex_buf[num_hex++] = ' ';
931 num_ascii++;
932 }
933
934 nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
935 }
936}
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