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RDMA/ocrdma: Remove the MTU check based on Ethernet MTU
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
CommitLineData
fe2caefc
PP		 1/*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/log2.h>
31#include <linux/dma-mapping.h>
32
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_user_verbs.h>
35#include <rdma/ib_addr.h>
36
37#include "ocrdma.h"
38#include "ocrdma_hw.h"
39#include "ocrdma_verbs.h"
40#include "ocrdma_ah.h"
41
42enum mbx_status {
43 OCRDMA_MBX_STATUS_FAILED = 1,
44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
45 OCRDMA_MBX_STATUS_OOR = 100,
46 OCRDMA_MBX_STATUS_INVALID_PD = 101,
47 OCRDMA_MBX_STATUS_PD_INUSE = 102,
48 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
49 OCRDMA_MBX_STATUS_INVALID_QP = 104,
50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
59 OCRDMA_MBX_STATUS_MW_BOUND = 114,
60 OCRDMA_MBX_STATUS_INVALID_VA = 115,
61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
62 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
74 OCRDMA_MBX_STATUS_QP_BOUND = 130,
75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
81};
82
83enum additional_status {
84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
85};
86
87enum cqe_status {
88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
93};
94
95static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
96{
f99b1649 97 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
fe2caefc
PP		 98}
99
100static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
101{
102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
103}
104
105static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
106{
107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
f99b1649 108 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
fe2caefc
PP		 109
110 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
111 return NULL;
112 return cqe;
113}
114
115static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
116{
117 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
118}
119
120static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
121{
f99b1649 122 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 123}
124
125static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
126{
127 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
fe2caefc
PP		 128}
129
130static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
131{
f99b1649 132 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
fe2caefc
PP		 133}
134
135enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
136{
137 switch (qps) {
138 case OCRDMA_QPS_RST:
139 return IB_QPS_RESET;
140 case OCRDMA_QPS_INIT:
141 return IB_QPS_INIT;
142 case OCRDMA_QPS_RTR:
143 return IB_QPS_RTR;
144 case OCRDMA_QPS_RTS:
145 return IB_QPS_RTS;
146 case OCRDMA_QPS_SQD:
147 case OCRDMA_QPS_SQ_DRAINING:
148 return IB_QPS_SQD;
149 case OCRDMA_QPS_SQE:
150 return IB_QPS_SQE;
151 case OCRDMA_QPS_ERR:
152 return IB_QPS_ERR;
153 };
154 return IB_QPS_ERR;
155}
156
abe3afac 157static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
fe2caefc
PP		 158{
159 switch (qps) {
160 case IB_QPS_RESET:
161 return OCRDMA_QPS_RST;
162 case IB_QPS_INIT:
163 return OCRDMA_QPS_INIT;
164 case IB_QPS_RTR:
165 return OCRDMA_QPS_RTR;
166 case IB_QPS_RTS:
167 return OCRDMA_QPS_RTS;
168 case IB_QPS_SQD:
169 return OCRDMA_QPS_SQD;
170 case IB_QPS_SQE:
171 return OCRDMA_QPS_SQE;
172 case IB_QPS_ERR:
173 return OCRDMA_QPS_ERR;
174 };
175 return OCRDMA_QPS_ERR;
176}
177
178static int ocrdma_get_mbx_errno(u32 status)
179{
f99b1649 180 int err_num;
fe2caefc
PP		 181 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
182 OCRDMA_MBX_RSP_STATUS_SHIFT;
183 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
184 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
185
186 switch (mbox_status) {
187 case OCRDMA_MBX_STATUS_OOR:
188 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
189 err_num = -EAGAIN;
190 break;
191
192 case OCRDMA_MBX_STATUS_INVALID_PD:
193 case OCRDMA_MBX_STATUS_INVALID_CQ:
194 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
195 case OCRDMA_MBX_STATUS_INVALID_QP:
196 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
197 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
198 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
199 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
200 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
201 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
202 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
203 case OCRDMA_MBX_STATUS_INVALID_LKEY:
204 case OCRDMA_MBX_STATUS_INVALID_VA:
205 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
206 case OCRDMA_MBX_STATUS_INVALID_FBO:
207 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
208 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
209 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
210 case OCRDMA_MBX_STATUS_SRQ_ERROR:
211 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
212 err_num = -EINVAL;
213 break;
214
215 case OCRDMA_MBX_STATUS_PD_INUSE:
216 case OCRDMA_MBX_STATUS_QP_BOUND:
217 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
218 case OCRDMA_MBX_STATUS_MW_BOUND:
219 err_num = -EBUSY;
220 break;
221
222 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
223 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
224 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
225 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
226 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
227 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
228 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
230 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
231 err_num = -ENOBUFS;
232 break;
233
234 case OCRDMA_MBX_STATUS_FAILED:
235 switch (add_status) {
236 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
237 err_num = -EAGAIN;
238 break;
239 }
240 default:
241 err_num = -EFAULT;
242 }
243 return err_num;
244}
245
246static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
247{
248 int err_num = -EINVAL;
249
250 switch (cqe_status) {
251 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
252 err_num = -EPERM;
253 break;
254 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
255 err_num = -EINVAL;
256 break;
257 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
258 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
259 err_num = -EAGAIN;
260 break;
261 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
43a6b402 262 default:
fe2caefc
PP		 263 err_num = -EIO;
264 break;
265 }
266 return err_num;
267}
268
269void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
270 bool solicited, u16 cqe_popped)
271{
272 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
273
274 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
275 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
276
277 if (armed)
278 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
279 if (solicited)
280 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
281 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
282 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
283}
284
285static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
286{
287 u32 val = 0;
288
289 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
290 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
291 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
292}
293
294static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
295 bool arm, bool clear_int, u16 num_eqe)
296{
297 u32 val = 0;
298
299 val |= eq_id & OCRDMA_EQ_ID_MASK;
300 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
301 if (arm)
302 val |= (1 << OCRDMA_REARM_SHIFT);
303 if (clear_int)
304 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
305 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
306 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
307 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
308}
309
310static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
311 u8 opcode, u8 subsys, u32 cmd_len)
312{
313 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
314 cmd_hdr->timeout = 20; /* seconds */
315 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
316}
317
318static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
319{
320 struct ocrdma_mqe *mqe;
321
322 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
323 if (!mqe)
324 return NULL;
325 mqe->hdr.spcl_sge_cnt_emb |=
326 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
327 OCRDMA_MQE_HDR_EMB_MASK;
328 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
329
330 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
331 mqe->hdr.pyld_len);
332 return mqe;
333}
334
335static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
336{
337 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
338}
339
340static int ocrdma_alloc_q(struct ocrdma_dev *dev,
341 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
342{
343 memset(q, 0, sizeof(*q));
344 q->len = len;
345 q->entry_size = entry_size;
346 q->size = len * entry_size;
347 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
348 &q->dma, GFP_KERNEL);
349 if (!q->va)
350 return -ENOMEM;
351 memset(q->va, 0, q->size);
352 return 0;
353}
354
355static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
356 dma_addr_t host_pa, int hw_page_size)
357{
358 int i;
359
360 for (i = 0; i < cnt; i++) {
361 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
362 q_pa[i].hi = (u32) upper_32_bits(host_pa);
363 host_pa += hw_page_size;
364 }
365}
366
367static void ocrdma_assign_eq_vect_gen2(struct ocrdma_dev *dev,
368 struct ocrdma_eq *eq)
369{
370 /* assign vector and update vector id for next EQ */
371 eq->vector = dev->nic_info.msix.start_vector;
372 dev->nic_info.msix.start_vector += 1;
373}
374
375static void ocrdma_free_eq_vect_gen2(struct ocrdma_dev *dev)
376{
377 /* this assumes that EQs are freed in exactly reverse order
378 * as its allocation.
379 */
380 dev->nic_info.msix.start_vector -= 1;
381}
382
abe3afac
RD		 383static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
384 int queue_type)
fe2caefc
PP		 385{
386 u8 opcode = 0;
387 int status;
388 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
389
390 switch (queue_type) {
391 case QTYPE_MCCQ:
392 opcode = OCRDMA_CMD_DELETE_MQ;
393 break;
394 case QTYPE_CQ:
395 opcode = OCRDMA_CMD_DELETE_CQ;
396 break;
397 case QTYPE_EQ:
398 opcode = OCRDMA_CMD_DELETE_EQ;
399 break;
400 default:
401 BUG();
402 }
403 memset(cmd, 0, sizeof(*cmd));
404 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
405 cmd->id = q->id;
406
407 status = be_roce_mcc_cmd(dev->nic_info.netdev,
408 cmd, sizeof(*cmd), NULL, NULL);
409 if (!status)
410 q->created = false;
411 return status;
412}
413
414static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
415{
416 int status;
417 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
418 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
419
420 memset(cmd, 0, sizeof(*cmd));
421 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
422 sizeof(*cmd));
423 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
424 cmd->req.rsvd_version = 0;
425 else
426 cmd->req.rsvd_version = 2;
427
428 cmd->num_pages = 4;
429 cmd->valid = OCRDMA_CREATE_EQ_VALID;
430 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
431
432 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
433 PAGE_SIZE_4K);
434 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
435 NULL);
436 if (!status) {
437 eq->q.id = rsp->vector_eqid & 0xffff;
f99b1649 438 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
fe2caefc 439 ocrdma_assign_eq_vect_gen2(dev, eq);
f99b1649 440 } else {
fe2caefc
PP		 441 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
442 dev->nic_info.msix.start_vector += 1;
443 }
444 eq->q.created = true;
445 }
446 return status;
447}
448
449static int ocrdma_create_eq(struct ocrdma_dev *dev,
450 struct ocrdma_eq *eq, u16 q_len)
451{
452 int status;
453
454 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
455 sizeof(struct ocrdma_eqe));
456 if (status)
457 return status;
458
459 status = ocrdma_mbx_create_eq(dev, eq);
460 if (status)
461 goto mbx_err;
462 eq->dev = dev;
463 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
464
465 return 0;
466mbx_err:
467 ocrdma_free_q(dev, &eq->q);
468 return status;
469}
470
471static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
472{
473 int irq;
474
475 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
476 irq = dev->nic_info.pdev->irq;
477 else
478 irq = dev->nic_info.msix.vector_list[eq->vector];
479 return irq;
480}
481
482static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
483{
484 if (eq->q.created) {
485 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
486 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
487 ocrdma_free_eq_vect_gen2(dev);
488 ocrdma_free_q(dev, &eq->q);
489 }
490}
491
492static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
493{
494 int irq;
495
496 /* disarm EQ so that interrupts are not generated
497 * during freeing and EQ delete is in progress.
498 */
499 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
500
501 irq = ocrdma_get_irq(dev, eq);
502 free_irq(irq, eq);
503 _ocrdma_destroy_eq(dev, eq);
504}
505
506static void ocrdma_destroy_qp_eqs(struct ocrdma_dev *dev)
507{
508 int i;
509
510 /* deallocate the data path eqs */
511 for (i = 0; i < dev->eq_cnt; i++)
512 ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
513}
514
abe3afac
RD		 515static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
516 struct ocrdma_queue_info *cq,
517 struct ocrdma_queue_info *eq)
fe2caefc
PP		 518{
519 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
520 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
521 int status;
522
523 memset(cmd, 0, sizeof(*cmd));
524 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
525 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
526
1afc0454
NG		 527 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
528 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
529 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
530 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
531
fe2caefc 532 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1afc0454
NG		 533 cmd->eqn = eq->id;
534 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
fe2caefc 535
1afc0454 536 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
fe2caefc
PP		 537 cq->dma, PAGE_SIZE_4K);
538 status = be_roce_mcc_cmd(dev->nic_info.netdev,
539 cmd, sizeof(*cmd), NULL, NULL);
540 if (!status) {
1afc0454 541 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
fe2caefc
PP		 542 cq->created = true;
543 }
544 return status;
545}
546
547static u32 ocrdma_encoded_q_len(int q_len)
548{
549 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
550
551 if (len_encoded == 16)
552 len_encoded = 0;
553 return len_encoded;
554}
555
556static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
557 struct ocrdma_queue_info *mq,
558 struct ocrdma_queue_info *cq)
559{
560 int num_pages, status;
561 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
562 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
563 struct ocrdma_pa *pa;
564
565 memset(cmd, 0, sizeof(*cmd));
566 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
567
b1d58b99
NG		 568 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
569 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
570 cmd->req.rsvd_version = 1;
571 cmd->cqid_pages = num_pages;
572 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
573 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
574 cmd->async_event_bitmap = Bit(20);
575 cmd->async_cqid_ringsize = cq->id;
576 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
577 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
578 cmd->valid = OCRDMA_CREATE_MQ_VALID;
579 pa = &cmd->pa[0];
580
fe2caefc
PP		 581 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
582 status = be_roce_mcc_cmd(dev->nic_info.netdev,
583 cmd, sizeof(*cmd), NULL, NULL);
584 if (!status) {
585 mq->id = rsp->id;
586 mq->created = true;
587 }
588 return status;
589}
590
591static int ocrdma_create_mq(struct ocrdma_dev *dev)
592{
593 int status;
594
595 /* Alloc completion queue for Mailbox queue */
596 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
597 sizeof(struct ocrdma_mcqe));
598 if (status)
599 goto alloc_err;
600
601 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->meq.q);
602 if (status)
603 goto mbx_cq_free;
604
605 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
606 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
607 mutex_init(&dev->mqe_ctx.lock);
608
609 /* Alloc Mailbox queue */
610 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
611 sizeof(struct ocrdma_mqe));
612 if (status)
613 goto mbx_cq_destroy;
614 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
615 if (status)
616 goto mbx_q_free;
617 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
618 return 0;
619
620mbx_q_free:
621 ocrdma_free_q(dev, &dev->mq.sq);
622mbx_cq_destroy:
623 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
624mbx_cq_free:
625 ocrdma_free_q(dev, &dev->mq.cq);
626alloc_err:
627 return status;
628}
629
630static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
631{
632 struct ocrdma_queue_info *mbxq, *cq;
633
634 /* mqe_ctx lock synchronizes with any other pending cmds. */
635 mutex_lock(&dev->mqe_ctx.lock);
636 mbxq = &dev->mq.sq;
637 if (mbxq->created) {
638 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
639 ocrdma_free_q(dev, mbxq);
640 }
641 mutex_unlock(&dev->mqe_ctx.lock);
642
643 cq = &dev->mq.cq;
644 if (cq->created) {
645 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
646 ocrdma_free_q(dev, cq);
647 }
648}
649
650static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
651 struct ocrdma_qp *qp)
652{
653 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
654 enum ib_qp_state old_ib_qps;
655
656 if (qp == NULL)
657 BUG();
057729cb 658 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
fe2caefc
PP		 659}
660
661static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
662 struct ocrdma_ae_mcqe *cqe)
663{
664 struct ocrdma_qp *qp = NULL;
665 struct ocrdma_cq *cq = NULL;
e9db2953 666 struct ib_event ib_evt;
fe2caefc
PP		 667 int cq_event = 0;
668 int qp_event = 1;
669 int srq_event = 0;
670 int dev_event = 0;
671 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
672 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
673
674 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
675 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
676 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
677 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
678
e9db2953
RD		 679 ib_evt.device = &dev->ibdev;
680
fe2caefc
PP		 681 switch (type) {
682 case OCRDMA_CQ_ERROR:
683 ib_evt.element.cq = &cq->ibcq;
684 ib_evt.event = IB_EVENT_CQ_ERR;
685 cq_event = 1;
686 qp_event = 0;
687 break;
688 case OCRDMA_CQ_OVERRUN_ERROR:
689 ib_evt.element.cq = &cq->ibcq;
690 ib_evt.event = IB_EVENT_CQ_ERR;
691 break;
692 case OCRDMA_CQ_QPCAT_ERROR:
693 ib_evt.element.qp = &qp->ibqp;
694 ib_evt.event = IB_EVENT_QP_FATAL;
695 ocrdma_process_qpcat_error(dev, qp);
696 break;
697 case OCRDMA_QP_ACCESS_ERROR:
698 ib_evt.element.qp = &qp->ibqp;
699 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
700 break;
701 case OCRDMA_QP_COMM_EST_EVENT:
702 ib_evt.element.qp = &qp->ibqp;
703 ib_evt.event = IB_EVENT_COMM_EST;
704 break;
705 case OCRDMA_SQ_DRAINED_EVENT:
706 ib_evt.element.qp = &qp->ibqp;
707 ib_evt.event = IB_EVENT_SQ_DRAINED;
708 break;
709 case OCRDMA_DEVICE_FATAL_EVENT:
710 ib_evt.element.port_num = 1;
711 ib_evt.event = IB_EVENT_DEVICE_FATAL;
712 qp_event = 0;
713 dev_event = 1;
714 break;
715 case OCRDMA_SRQCAT_ERROR:
716 ib_evt.element.srq = &qp->srq->ibsrq;
717 ib_evt.event = IB_EVENT_SRQ_ERR;
718 srq_event = 1;
719 qp_event = 0;
720 break;
721 case OCRDMA_SRQ_LIMIT_EVENT:
722 ib_evt.element.srq = &qp->srq->ibsrq;
804eaf29 723 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
fe2caefc
PP		 724 srq_event = 1;
725 qp_event = 0;
726 break;
727 case OCRDMA_QP_LAST_WQE_EVENT:
728 ib_evt.element.qp = &qp->ibqp;
729 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
730 break;
731 default:
732 cq_event = 0;
733 qp_event = 0;
734 srq_event = 0;
735 dev_event = 0;
ef99c4c2 736 pr_err("%s() unknown type=0x%x\n", __func__, type);
fe2caefc
PP		 737 break;
738 }
739
740 if (qp_event) {
741 if (qp->ibqp.event_handler)
742 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
743 } else if (cq_event) {
744 if (cq->ibcq.event_handler)
745 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
746 } else if (srq_event) {
747 if (qp->srq->ibsrq.event_handler)
748 qp->srq->ibsrq.event_handler(&ib_evt,
749 qp->srq->ibsrq.
750 srq_context);
f99b1649 751 } else if (dev_event) {
fe2caefc 752 ib_dispatch_event(&ib_evt);
f99b1649 753 }
fe2caefc
PP		 754
755}
756
757static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
758{
759 /* async CQE processing */
760 struct ocrdma_ae_mcqe *cqe = ae_cqe;
761 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
762 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
763
764 if (evt_code == OCRDMA_ASYNC_EVE_CODE)
765 ocrdma_dispatch_ibevent(dev, cqe);
766 else
ef99c4c2
NG		 767 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
768 dev->id, evt_code);
fe2caefc
PP		 769}
770
771static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
772{
773 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
774 dev->mqe_ctx.cqe_status = (cqe->status &
775 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
776 dev->mqe_ctx.ext_status =
777 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
778 >> OCRDMA_MCQE_ESTATUS_SHIFT;
779 dev->mqe_ctx.cmd_done = true;
780 wake_up(&dev->mqe_ctx.cmd_wait);
781 } else
ef99c4c2
NG		 782 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
783 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
fe2caefc
PP		 784}
785
786static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
787{
788 u16 cqe_popped = 0;
789 struct ocrdma_mcqe *cqe;
790
791 while (1) {
792 cqe = ocrdma_get_mcqe(dev);
793 if (cqe == NULL)
794 break;
795 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
796 cqe_popped += 1;
797 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
798 ocrdma_process_acqe(dev, cqe);
799 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
800 ocrdma_process_mcqe(dev, cqe);
801 else
ef99c4c2 802 pr_err("%s() cqe->compl is not set.\n", __func__);
fe2caefc
PP		 803 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
804 ocrdma_mcq_inc_tail(dev);
805 }
806 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
807 return 0;
808}
809
810static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
811 struct ocrdma_cq *cq)
812{
813 unsigned long flags;
814 struct ocrdma_qp *qp;
815 bool buddy_cq_found = false;
816 /* Go through list of QPs in error state which are using this CQ
817 * and invoke its callback handler to trigger CQE processing for
818 * error/flushed CQE. It is rare to find more than few entries in
819 * this list as most consumers stops after getting error CQE.
820 * List is traversed only once when a matching buddy cq found for a QP.
821 */
822 spin_lock_irqsave(&dev->flush_q_lock, flags);
823 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
824 if (qp->srq)
825 continue;
826 /* if wq and rq share the same cq, than comp_handler
827 * is already invoked.
828 */
829 if (qp->sq_cq == qp->rq_cq)
830 continue;
831 /* if completion came on sq, rq's cq is buddy cq.
832 * if completion came on rq, sq's cq is buddy cq.
833 */
834 if (qp->sq_cq == cq)
835 cq = qp->rq_cq;
836 else
837 cq = qp->sq_cq;
838 buddy_cq_found = true;
839 break;
840 }
841 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
842 if (buddy_cq_found == false)
843 return;
844 if (cq->ibcq.comp_handler) {
845 spin_lock_irqsave(&cq->comp_handler_lock, flags);
846 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
847 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
848 }
849}
850
851static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
852{
853 unsigned long flags;
854 struct ocrdma_cq *cq;
855
856 if (cq_idx >= OCRDMA_MAX_CQ)
857 BUG();
858
859 cq = dev->cq_tbl[cq_idx];
860 if (cq == NULL) {
ef99c4c2 861 pr_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx);
fe2caefc
PP		 862 return;
863 }
864 spin_lock_irqsave(&cq->cq_lock, flags);
865 cq->armed = false;
866 cq->solicited = false;
867 spin_unlock_irqrestore(&cq->cq_lock, flags);
868
869 ocrdma_ring_cq_db(dev, cq->id, false, false, 0);
870
871 if (cq->ibcq.comp_handler) {
872 spin_lock_irqsave(&cq->comp_handler_lock, flags);
873 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
874 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
875 }
876 ocrdma_qp_buddy_cq_handler(dev, cq);
877}
878
879static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
880{
881 /* process the MQ-CQE. */
882 if (cq_id == dev->mq.cq.id)
883 ocrdma_mq_cq_handler(dev, cq_id);
884 else
885 ocrdma_qp_cq_handler(dev, cq_id);
886}
887
888static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
889{
890 struct ocrdma_eq *eq = handle;
891 struct ocrdma_dev *dev = eq->dev;
892 struct ocrdma_eqe eqe;
893 struct ocrdma_eqe *ptr;
894 u16 eqe_popped = 0;
895 u16 cq_id;
896 while (1) {
897 ptr = ocrdma_get_eqe(eq);
898 eqe = *ptr;
899 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
900 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
901 break;
902 eqe_popped += 1;
903 ptr->id_valid = 0;
904 /* check whether its CQE or not. */
905 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
906 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
907 ocrdma_cq_handler(dev, cq_id);
908 }
909 ocrdma_eq_inc_tail(eq);
910 }
911 ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped);
912 /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */
913 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
914 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
915 return IRQ_HANDLED;
916}
917
918static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
919{
920 struct ocrdma_mqe *mqe;
921
922 dev->mqe_ctx.tag = dev->mq.sq.head;
923 dev->mqe_ctx.cmd_done = false;
924 mqe = ocrdma_get_mqe(dev);
925 cmd->hdr.tag_lo = dev->mq.sq.head;
926 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
927 /* make sure descriptor is written before ringing doorbell */
928 wmb();
929 ocrdma_mq_inc_head(dev);
930 ocrdma_ring_mq_db(dev);
931}
932
933static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
934{
935 long status;
936 /* 30 sec timeout */
937 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
938 (dev->mqe_ctx.cmd_done != false),
939 msecs_to_jiffies(30000));
940 if (status)
941 return 0;
942 else
943 return -1;
944}
945
946/* issue a mailbox command on the MQ */
947static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
948{
949 int status = 0;
950 u16 cqe_status, ext_status;
951 struct ocrdma_mqe *rsp;
952
953 mutex_lock(&dev->mqe_ctx.lock);
954 ocrdma_post_mqe(dev, mqe);
955 status = ocrdma_wait_mqe_cmpl(dev);
956 if (status)
957 goto mbx_err;
958 cqe_status = dev->mqe_ctx.cqe_status;
959 ext_status = dev->mqe_ctx.ext_status;
960 rsp = ocrdma_get_mqe_rsp(dev);
961 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
962 if (cqe_status || ext_status) {
f99b1649
NG		 963 pr_err("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
964 __func__,
fe2caefc
PP		 965 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
966 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
967 status = ocrdma_get_mbx_cqe_errno(cqe_status);
968 goto mbx_err;
969 }
970 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
971 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
972mbx_err:
973 mutex_unlock(&dev->mqe_ctx.lock);
974 return status;
975}
976
977static void ocrdma_get_attr(struct ocrdma_dev *dev,
978 struct ocrdma_dev_attr *attr,
979 struct ocrdma_mbx_query_config *rsp)
980{
fe2caefc
PP		 981 attr->max_pd =
982 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
983 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
984 attr->max_qp =
985 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
986 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
987 attr->max_send_sge = ((rsp->max_write_send_sge &
988 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
989 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
990 attr->max_recv_sge = (rsp->max_write_send_sge &
991 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
992 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
634c5796
MV		 993 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
994 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
995 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
45e86b33
NG		 996 attr->max_rdma_sge = (rsp->max_write_send_sge &
997 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
998 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
fe2caefc
PP		 999 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1000 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1001 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
7c33880c
NG		 1002 attr->max_srq =
1003 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1004 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
fe2caefc
PP		 1005 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1006 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1007 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1008 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1009 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1010 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1011 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1012 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1013 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1014 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1015 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1016 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1017 attr->max_mr = rsp->max_mr;
1018 attr->max_mr_size = ~0ull;
1019 attr->max_fmr = 0;
1020 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1021 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1022 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1023 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1024 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1025 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1026 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1027 OCRDMA_WQE_STRIDE;
1028 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1029 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1030 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1031 OCRDMA_WQE_STRIDE;
1032 attr->max_inline_data =
1033 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1034 sizeof(struct ocrdma_sge));
fe2caefc 1035 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
fe2caefc
PP		 1036 attr->ird = 1;
1037 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1038 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
07bb5424
MV		 1039 }
1040 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1041 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1042 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1043 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
fe2caefc
PP		 1044}
1045
1046static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1047 struct ocrdma_fw_conf_rsp *conf)
1048{
1049 u32 fn_mode;
1050
1051 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1052 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1053 return -EINVAL;
1054 dev->base_eqid = conf->base_eqid;
1055 dev->max_eq = conf->max_eq;
1056 dev->attr.max_cq = OCRDMA_MAX_CQ - 1;
1057 return 0;
1058}
1059
1060/* can be issued only during init time. */
1061static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1062{
1063 int status = -ENOMEM;
1064 struct ocrdma_mqe *cmd;
1065 struct ocrdma_fw_ver_rsp *rsp;
1066
1067 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1068 if (!cmd)
1069 return -ENOMEM;
1070 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1071 OCRDMA_CMD_GET_FW_VER,
1072 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1073
1074 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1075 if (status)
1076 goto mbx_err;
1077 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1078 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1079 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1080 sizeof(rsp->running_ver));
1081 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1082mbx_err:
1083 kfree(cmd);
1084 return status;
1085}
1086
1087/* can be issued only during init time. */
1088static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1089{
1090 int status = -ENOMEM;
1091 struct ocrdma_mqe *cmd;
1092 struct ocrdma_fw_conf_rsp *rsp;
1093
1094 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1095 if (!cmd)
1096 return -ENOMEM;
1097 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1098 OCRDMA_CMD_GET_FW_CONFIG,
1099 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1100 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1101 if (status)
1102 goto mbx_err;
1103 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1104 status = ocrdma_check_fw_config(dev, rsp);
1105mbx_err:
1106 kfree(cmd);
1107 return status;
1108}
1109
1110static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1111{
1112 int status = -ENOMEM;
1113 struct ocrdma_mbx_query_config *rsp;
1114 struct ocrdma_mqe *cmd;
1115
1116 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1117 if (!cmd)
1118 return status;
1119 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1120 if (status)
1121 goto mbx_err;
1122 rsp = (struct ocrdma_mbx_query_config *)cmd;
1123 ocrdma_get_attr(dev, &dev->attr, rsp);
1124mbx_err:
1125 kfree(cmd);
1126 return status;
1127}
1128
1129int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1130{
1131 int status = -ENOMEM;
1132 struct ocrdma_alloc_pd *cmd;
1133 struct ocrdma_alloc_pd_rsp *rsp;
1134
1135 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1136 if (!cmd)
1137 return status;
1138 if (pd->dpp_enabled)
1139 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1140 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1141 if (status)
1142 goto mbx_err;
1143 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1144 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1145 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1146 pd->dpp_enabled = true;
1147 pd->dpp_page = rsp->dpp_page_pdid >>
1148 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1149 } else {
1150 pd->dpp_enabled = false;
1151 pd->num_dpp_qp = 0;
1152 }
1153mbx_err:
1154 kfree(cmd);
1155 return status;
1156}
1157
1158int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1159{
1160 int status = -ENOMEM;
1161 struct ocrdma_dealloc_pd *cmd;
1162
1163 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1164 if (!cmd)
1165 return status;
1166 cmd->id = pd->id;
1167 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1168 kfree(cmd);
1169 return status;
1170}
1171
1172static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1173 int *num_pages, int *page_size)
1174{
1175 int i;
1176 int mem_size;
1177
1178 *num_entries = roundup_pow_of_two(*num_entries);
1179 mem_size = *num_entries * entry_size;
1180 /* find the possible lowest possible multiplier */
1181 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1182 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1183 break;
1184 }
1185 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1186 return -EINVAL;
1187 mem_size = roundup(mem_size,
1188 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1189 *num_pages =
1190 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1191 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1192 *num_entries = mem_size / entry_size;
1193 return 0;
1194}
1195
1196static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1197{
1198 int i ;
1199 int status = 0;
1200 int max_ah;
1201 struct ocrdma_create_ah_tbl *cmd;
1202 struct ocrdma_create_ah_tbl_rsp *rsp;
1203 struct pci_dev *pdev = dev->nic_info.pdev;
1204 dma_addr_t pa;
1205 struct ocrdma_pbe *pbes;
1206
1207 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1208 if (!cmd)
1209 return status;
1210
1211 max_ah = OCRDMA_MAX_AH;
1212 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1213
1214 /* number of PBEs in PBL */
1215 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1216 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1217 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1218
1219 /* page size */
1220 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1221 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1222 break;
1223 }
1224 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1225 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1226
1227 /* ah_entry size */
1228 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1229 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1230 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1231
1232 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1233 &dev->av_tbl.pbl.pa,
1234 GFP_KERNEL);
1235 if (dev->av_tbl.pbl.va == NULL)
1236 goto mem_err;
1237
1238 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1239 &pa, GFP_KERNEL);
1240 if (dev->av_tbl.va == NULL)
1241 goto mem_err_ah;
1242 dev->av_tbl.pa = pa;
1243 dev->av_tbl.num_ah = max_ah;
1244 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1245
1246 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1247 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1248 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1249 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1250 pa += PAGE_SIZE;
1251 }
1252 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1253 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1254 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1255 if (status)
1256 goto mbx_err;
1257 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1258 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1259 kfree(cmd);
1260 return 0;
1261
1262mbx_err:
1263 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1264 dev->av_tbl.pa);
1265 dev->av_tbl.va = NULL;
1266mem_err_ah:
1267 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1268 dev->av_tbl.pbl.pa);
1269 dev->av_tbl.pbl.va = NULL;
1270 dev->av_tbl.size = 0;
1271mem_err:
1272 kfree(cmd);
1273 return status;
1274}
1275
1276static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1277{
1278 struct ocrdma_delete_ah_tbl *cmd;
1279 struct pci_dev *pdev = dev->nic_info.pdev;
1280
1281 if (dev->av_tbl.va == NULL)
1282 return;
1283
1284 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1285 if (!cmd)
1286 return;
1287 cmd->ahid = dev->av_tbl.ahid;
1288
1289 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1290 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1291 dev->av_tbl.pa);
1292 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1293 dev->av_tbl.pbl.pa);
1294 kfree(cmd);
1295}
1296
1297/* Multiple CQs uses the EQ. This routine returns least used
1298 * EQ to associate with CQ. This will distributes the interrupt
1299 * processing and CPU load to associated EQ, vector and so to that CPU.
1300 */
1301static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1302{
1303 int i, selected_eq = 0, cq_cnt = 0;
1304 u16 eq_id;
1305
1306 mutex_lock(&dev->dev_lock);
1307 cq_cnt = dev->qp_eq_tbl[0].cq_cnt;
1308 eq_id = dev->qp_eq_tbl[0].q.id;
1309 /* find the EQ which is has the least number of
1310 * CQs associated with it.
1311 */
1312 for (i = 0; i < dev->eq_cnt; i++) {
1313 if (dev->qp_eq_tbl[i].cq_cnt < cq_cnt) {
1314 cq_cnt = dev->qp_eq_tbl[i].cq_cnt;
1315 eq_id = dev->qp_eq_tbl[i].q.id;
1316 selected_eq = i;
1317 }
1318 }
1319 dev->qp_eq_tbl[selected_eq].cq_cnt += 1;
1320 mutex_unlock(&dev->dev_lock);
1321 return eq_id;
1322}
1323
1324static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1325{
1326 int i;
1327
1328 mutex_lock(&dev->dev_lock);
1329 for (i = 0; i < dev->eq_cnt; i++) {
1330 if (dev->qp_eq_tbl[i].q.id != eq_id)
1331 continue;
1332 dev->qp_eq_tbl[i].cq_cnt -= 1;
1333 break;
1334 }
1335 mutex_unlock(&dev->dev_lock);
1336}
1337
1338int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1339 int entries, int dpp_cq)
1340{
1341 int status = -ENOMEM; int max_hw_cqe;
1342 struct pci_dev *pdev = dev->nic_info.pdev;
1343 struct ocrdma_create_cq *cmd;
1344 struct ocrdma_create_cq_rsp *rsp;
1345 u32 hw_pages, cqe_size, page_size, cqe_count;
1346
fe2caefc 1347 if (entries > dev->attr.max_cqe) {
ef99c4c2
NG		 1348 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1349 __func__, dev->id, dev->attr.max_cqe, entries);
fe2caefc
PP		 1350 return -EINVAL;
1351 }
1352 if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY))
1353 return -EINVAL;
1354
1355 if (dpp_cq) {
1356 cq->max_hw_cqe = 1;
1357 max_hw_cqe = 1;
1358 cqe_size = OCRDMA_DPP_CQE_SIZE;
1359 hw_pages = 1;
1360 } else {
1361 cq->max_hw_cqe = dev->attr.max_cqe;
1362 max_hw_cqe = dev->attr.max_cqe;
1363 cqe_size = sizeof(struct ocrdma_cqe);
1364 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1365 }
1366
1367 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1368
1369 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1370 if (!cmd)
1371 return -ENOMEM;
1372 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1373 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1374 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1375 if (!cq->va) {
1376 status = -ENOMEM;
1377 goto mem_err;
1378 }
1379 memset(cq->va, 0, cq->len);
1380 page_size = cq->len / hw_pages;
1381 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1382 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1383 cmd->cmd.pgsz_pgcnt |= hw_pages;
1384 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1385
fe2caefc
PP		 1386 cq->eqn = ocrdma_bind_eq(dev);
1387 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
1388 cqe_count = cq->len / cqe_size;
f99b1649 1389 if (cqe_count > 1024) {
fe2caefc
PP		 1390 /* Set cnt to 3 to indicate more than 1024 cq entries */
1391 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
f99b1649 1392 } else {
fe2caefc
PP		 1393 u8 count = 0;
1394 switch (cqe_count) {
1395 case 256:
1396 count = 0;
1397 break;
1398 case 512:
1399 count = 1;
1400 break;
1401 case 1024:
1402 count = 2;
1403 break;
1404 default:
1405 goto mbx_err;
1406 }
1407 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1408 }
1409 /* shared eq between all the consumer cqs. */
1410 cmd->cmd.eqn = cq->eqn;
1411 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1412 if (dpp_cq)
1413 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1414 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1415 cq->phase_change = false;
1416 cmd->cmd.cqe_count = (cq->len / cqe_size);
1417 } else {
1418 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1419 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1420 cq->phase_change = true;
1421 }
1422
1423 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1424 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1425 if (status)
1426 goto mbx_err;
1427
1428 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1429 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1430 kfree(cmd);
1431 return 0;
1432mbx_err:
1433 ocrdma_unbind_eq(dev, cq->eqn);
fe2caefc
PP		 1434 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1435mem_err:
1436 kfree(cmd);
1437 return status;
1438}
1439
1440int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1441{
1442 int status = -ENOMEM;
1443 struct ocrdma_destroy_cq *cmd;
1444
1445 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1446 if (!cmd)
1447 return status;
1448 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1449 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1450
1451 cmd->bypass_flush_qid |=
1452 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1453 OCRDMA_DESTROY_CQ_QID_MASK;
1454
1455 ocrdma_unbind_eq(dev, cq->eqn);
1456 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1457 if (status)
1458 goto mbx_err;
1459 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1460mbx_err:
1461 kfree(cmd);
1462 return status;
1463}
1464
1465int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1466 u32 pdid, int addr_check)
1467{
1468 int status = -ENOMEM;
1469 struct ocrdma_alloc_lkey *cmd;
1470 struct ocrdma_alloc_lkey_rsp *rsp;
1471
1472 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1473 if (!cmd)
1474 return status;
1475 cmd->pdid = pdid;
1476 cmd->pbl_sz_flags |= addr_check;
1477 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1478 cmd->pbl_sz_flags |=
1479 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1480 cmd->pbl_sz_flags |=
1481 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1482 cmd->pbl_sz_flags |=
1483 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1484 cmd->pbl_sz_flags |=
1485 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1486 cmd->pbl_sz_flags |=
1487 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1488
1489 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1490 if (status)
1491 goto mbx_err;
1492 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1493 hwmr->lkey = rsp->lrkey;
1494mbx_err:
1495 kfree(cmd);
1496 return status;
1497}
1498
1499int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1500{
1501 int status = -ENOMEM;
1502 struct ocrdma_dealloc_lkey *cmd;
1503
1504 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1505 if (!cmd)
1506 return -ENOMEM;
1507 cmd->lkey = lkey;
1508 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1509 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1510 if (status)
1511 goto mbx_err;
1512mbx_err:
1513 kfree(cmd);
1514 return status;
1515}
1516
1517static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1518 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1519{
1520 int status = -ENOMEM;
1521 int i;
1522 struct ocrdma_reg_nsmr *cmd;
1523 struct ocrdma_reg_nsmr_rsp *rsp;
1524
1525 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1526 if (!cmd)
1527 return -ENOMEM;
1528 cmd->num_pbl_pdid =
1529 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1530
1531 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1532 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1533 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1534 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1535 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1536 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1537 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1538 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1539 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1540 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1541 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1542
1543 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1544 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1545 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1546 cmd->totlen_low = hwmr->len;
1547 cmd->totlen_high = upper_32_bits(hwmr->len);
1548 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1549 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1550 cmd->va_loaddr = (u32) hwmr->va;
1551 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1552
1553 for (i = 0; i < pbl_cnt; i++) {
1554 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1555 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1556 }
1557 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1558 if (status)
1559 goto mbx_err;
1560 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1561 hwmr->lkey = rsp->lrkey;
1562mbx_err:
1563 kfree(cmd);
1564 return status;
1565}
1566
1567static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1568 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1569 u32 pbl_offset, u32 last)
1570{
1571 int status = -ENOMEM;
1572 int i;
1573 struct ocrdma_reg_nsmr_cont *cmd;
1574
1575 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1576 if (!cmd)
1577 return -ENOMEM;
1578 cmd->lrkey = hwmr->lkey;
1579 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1580 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1581 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1582
1583 for (i = 0; i < pbl_cnt; i++) {
1584 cmd->pbl[i].lo =
1585 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1586 cmd->pbl[i].hi =
1587 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1588 }
1589 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1590 if (status)
1591 goto mbx_err;
1592mbx_err:
1593 kfree(cmd);
1594 return status;
1595}
1596
1597int ocrdma_reg_mr(struct ocrdma_dev *dev,
1598 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1599{
1600 int status;
1601 u32 last = 0;
1602 u32 cur_pbl_cnt, pbl_offset;
1603 u32 pending_pbl_cnt = hwmr->num_pbls;
1604
1605 pbl_offset = 0;
1606 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1607 if (cur_pbl_cnt == pending_pbl_cnt)
1608 last = 1;
1609
1610 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1611 cur_pbl_cnt, hwmr->pbe_size, last);
1612 if (status) {
ef99c4c2 1613 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 1614 return status;
1615 }
1616 /* if there is no more pbls to register then exit. */
1617 if (last)
1618 return 0;
1619
1620 while (!last) {
1621 pbl_offset += cur_pbl_cnt;
1622 pending_pbl_cnt -= cur_pbl_cnt;
1623 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1624 /* if we reach the end of the pbls, then need to set the last
1625 * bit, indicating no more pbls to register for this memory key.
1626 */
1627 if (cur_pbl_cnt == pending_pbl_cnt)
1628 last = 1;
1629
1630 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1631 pbl_offset, last);
1632 if (status)
1633 break;
1634 }
1635 if (status)
ef99c4c2 1636 pr_err("%s() err. status=%d\n", __func__, status);
fe2caefc
PP		 1637
1638 return status;
1639}
1640
1641bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1642{
1643 struct ocrdma_qp *tmp;
1644 bool found = false;
1645 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1646 if (qp == tmp) {
1647 found = true;
1648 break;
1649 }
1650 }
1651 return found;
1652}
1653
1654bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1655{
1656 struct ocrdma_qp *tmp;
1657 bool found = false;
1658 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1659 if (qp == tmp) {
1660 found = true;
1661 break;
1662 }
1663 }
1664 return found;
1665}
1666
1667void ocrdma_flush_qp(struct ocrdma_qp *qp)
1668{
1669 bool found;
1670 unsigned long flags;
1671
1672 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1673 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1674 if (!found)
1675 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1676 if (!qp->srq) {
1677 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1678 if (!found)
1679 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1680 }
1681 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1682}
1683
057729cb
NG		 1684int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1685 enum ib_qp_state *old_ib_state)
fe2caefc
PP		 1686{
1687 unsigned long flags;
1688 int status = 0;
1689 enum ocrdma_qp_state new_state;
1690 new_state = get_ocrdma_qp_state(new_ib_state);
1691
1692 /* sync with wqe and rqe posting */
1693 spin_lock_irqsave(&qp->q_lock, flags);
1694
1695 if (old_ib_state)
1696 *old_ib_state = get_ibqp_state(qp->state);
1697 if (new_state == qp->state) {
1698 spin_unlock_irqrestore(&qp->q_lock, flags);
1699 return 1;
1700 }
1701
057729cb
NG		 1702
1703 if (new_state == OCRDMA_QPS_ERR)
1704 ocrdma_flush_qp(qp);
1705
1706 qp->state = new_state;
fe2caefc
PP		 1707
1708 spin_unlock_irqrestore(&qp->q_lock, flags);
1709 return status;
1710}
1711
1712static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1713{
1714 u32 flags = 0;
1715 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1716 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1717 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1718 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1719 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1720 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1721 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1722 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1723 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1724 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1725 return flags;
1726}
1727
1728static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1729 struct ib_qp_init_attr *attrs,
1730 struct ocrdma_qp *qp)
1731{
1732 int status;
1733 u32 len, hw_pages, hw_page_size;
1734 dma_addr_t pa;
1735 struct ocrdma_dev *dev = qp->dev;
1736 struct pci_dev *pdev = dev->nic_info.pdev;
1737 u32 max_wqe_allocated;
1738 u32 max_sges = attrs->cap.max_send_sge;
1739
43a6b402
NG		 1740 /* QP1 may exceed 127 */
1741 max_wqe_allocated = min_t(int, attrs->cap.max_send_wr + 1,
1742 dev->attr.max_wqe);
fe2caefc
PP		 1743
1744 status = ocrdma_build_q_conf(&max_wqe_allocated,
1745 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1746 if (status) {
ef99c4c2
NG		 1747 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1748 max_wqe_allocated);
fe2caefc
PP		 1749 return -EINVAL;
1750 }
1751 qp->sq.max_cnt = max_wqe_allocated;
1752 len = (hw_pages * hw_page_size);
1753
1754 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1755 if (!qp->sq.va)
1756 return -EINVAL;
1757 memset(qp->sq.va, 0, len);
1758 qp->sq.len = len;
1759 qp->sq.pa = pa;
1760 qp->sq.entry_size = dev->attr.wqe_size;
1761 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1762
1763 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1764 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1765 cmd->num_wq_rq_pages |= (hw_pages <<
1766 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1767 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1768 cmd->max_sge_send_write |= (max_sges <<
1769 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1770 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1771 cmd->max_sge_send_write |= (max_sges <<
1772 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1773 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1774 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1775 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1776 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1777 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1778 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1779 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1780 return 0;
1781}
1782
1783static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1784 struct ib_qp_init_attr *attrs,
1785 struct ocrdma_qp *qp)
1786{
1787 int status;
1788 u32 len, hw_pages, hw_page_size;
1789 dma_addr_t pa = 0;
1790 struct ocrdma_dev *dev = qp->dev;
1791 struct pci_dev *pdev = dev->nic_info.pdev;
1792 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1793
1794 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1795 &hw_pages, &hw_page_size);
1796 if (status) {
ef99c4c2
NG		 1797 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
1798 attrs->cap.max_recv_wr + 1);
fe2caefc
PP		 1799 return status;
1800 }
1801 qp->rq.max_cnt = max_rqe_allocated;
1802 len = (hw_pages * hw_page_size);
1803
1804 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1805 if (!qp->rq.va)
c94e15c5 1806 return -ENOMEM;
fe2caefc
PP		 1807 memset(qp->rq.va, 0, len);
1808 qp->rq.pa = pa;
1809 qp->rq.len = len;
1810 qp->rq.entry_size = dev->attr.rqe_size;
1811
1812 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1813 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1814 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1815 cmd->num_wq_rq_pages |=
1816 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1817 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1818 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1819 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1820 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1821 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1822 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1823 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1824 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1825 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1826 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1827 return 0;
1828}
1829
1830static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1831 struct ocrdma_pd *pd,
1832 struct ocrdma_qp *qp,
1833 u8 enable_dpp_cq, u16 dpp_cq_id)
1834{
1835 pd->num_dpp_qp--;
1836 qp->dpp_enabled = true;
1837 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1838 if (!enable_dpp_cq)
1839 return;
1840 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1841 cmd->dpp_credits_cqid = dpp_cq_id;
1842 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1843 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1844}
1845
1846static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1847 struct ocrdma_qp *qp)
1848{
1849 struct ocrdma_dev *dev = qp->dev;
1850 struct pci_dev *pdev = dev->nic_info.pdev;
1851 dma_addr_t pa = 0;
1852 int ird_page_size = dev->attr.ird_page_size;
1853 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
43a6b402
NG		 1854 struct ocrdma_hdr_wqe *rqe;
1855 int i = 0;
fe2caefc
PP		 1856
1857 if (dev->attr.ird == 0)
1858 return 0;
1859
1860 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1861 &pa, GFP_KERNEL);
1862 if (!qp->ird_q_va)
1863 return -ENOMEM;
1864 memset(qp->ird_q_va, 0, ird_q_len);
1865 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1866 pa, ird_page_size);
43a6b402
NG		 1867 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
1868 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
1869 (i * dev->attr.rqe_size));
1870 rqe->cw = 0;
1871 rqe->cw |= 2;
1872 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
1873 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
1874 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
1875 }
fe2caefc
PP		 1876 return 0;
1877}
1878
1879static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1880 struct ocrdma_qp *qp,
1881 struct ib_qp_init_attr *attrs,
1882 u16 *dpp_offset, u16 *dpp_credit_lmt)
1883{
1884 u32 max_wqe_allocated, max_rqe_allocated;
1885 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1886 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1887 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1888 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1889 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1890 qp->dpp_enabled = false;
1891 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1892 qp->dpp_enabled = true;
1893 *dpp_credit_lmt = (rsp->dpp_response &
1894 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1895 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1896 *dpp_offset = (rsp->dpp_response &
1897 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1898 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1899 }
1900 max_wqe_allocated =
1901 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1902 max_wqe_allocated = 1 << max_wqe_allocated;
1903 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1904
fe2caefc
PP		 1905 qp->sq.max_cnt = max_wqe_allocated;
1906 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1907
1908 if (!attrs->srq) {
1909 qp->rq.max_cnt = max_rqe_allocated;
1910 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
fe2caefc
PP		 1911 }
1912}
1913
1914int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
1915 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
1916 u16 *dpp_credit_lmt)
1917{
1918 int status = -ENOMEM;
1919 u32 flags = 0;
1920 struct ocrdma_dev *dev = qp->dev;
1921 struct ocrdma_pd *pd = qp->pd;
1922 struct pci_dev *pdev = dev->nic_info.pdev;
1923 struct ocrdma_cq *cq;
1924 struct ocrdma_create_qp_req *cmd;
1925 struct ocrdma_create_qp_rsp *rsp;
1926 int qptype;
1927
1928 switch (attrs->qp_type) {
1929 case IB_QPT_GSI:
1930 qptype = OCRDMA_QPT_GSI;
1931 break;
1932 case IB_QPT_RC:
1933 qptype = OCRDMA_QPT_RC;
1934 break;
1935 case IB_QPT_UD:
1936 qptype = OCRDMA_QPT_UD;
1937 break;
1938 default:
1939 return -EINVAL;
1940 };
1941
1942 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
1943 if (!cmd)
1944 return status;
1945 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
1946 OCRDMA_CREATE_QP_REQ_QPT_MASK;
1947 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
1948 if (status)
1949 goto sq_err;
1950
1951 if (attrs->srq) {
1952 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
1953 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
1954 cmd->rq_addr[0].lo = srq->id;
1955 qp->srq = srq;
1956 } else {
1957 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
1958 if (status)
1959 goto rq_err;
1960 }
1961
1962 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
1963 if (status)
1964 goto mbx_err;
1965
1966 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
1967 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
1968
1969 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
1970
1971 cmd->max_sge_recv_flags |= flags;
1972 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
1973 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
1974 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
1975 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
1976 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
1977 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
1978 cq = get_ocrdma_cq(attrs->send_cq);
1979 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
1980 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
1981 qp->sq_cq = cq;
1982 cq = get_ocrdma_cq(attrs->recv_cq);
1983 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
1984 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
1985 qp->rq_cq = cq;
1986
1987 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
f99b1649 1988 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
fe2caefc
PP		 1989 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
1990 dpp_cq_id);
f99b1649 1991 }
fe2caefc
PP		 1992
1993 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1994 if (status)
1995 goto mbx_err;
1996 rsp = (struct ocrdma_create_qp_rsp *)cmd;
1997 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
1998 qp->state = OCRDMA_QPS_RST;
1999 kfree(cmd);
2000 return 0;
2001mbx_err:
2002 if (qp->rq.va)
2003 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2004rq_err:
ef99c4c2 2005 pr_err("%s(%d) rq_err\n", __func__, dev->id);
fe2caefc
PP		 2006 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2007sq_err:
ef99c4c2 2008 pr_err("%s(%d) sq_err\n", __func__, dev->id);
fe2caefc
PP		 2009 kfree(cmd);
2010 return status;
2011}
2012
2013int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2014 struct ocrdma_qp_params *param)
2015{
2016 int status = -ENOMEM;
2017 struct ocrdma_query_qp *cmd;
2018 struct ocrdma_query_qp_rsp *rsp;
2019
2020 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2021 if (!cmd)
2022 return status;
2023 cmd->qp_id = qp->id;
2024 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2025 if (status)
2026 goto mbx_err;
2027 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2028 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2029mbx_err:
2030 kfree(cmd);
2031 return status;
2032}
2033
2034int ocrdma_resolve_dgid(struct ocrdma_dev *dev, union ib_gid *dgid,
2035 u8 *mac_addr)
2036{
2037 struct in6_addr in6;
2038
2039 memcpy(&in6, dgid, sizeof in6);
f99b1649 2040 if (rdma_is_multicast_addr(&in6)) {
fe2caefc 2041 rdma_get_mcast_mac(&in6, mac_addr);
f99b1649 2042 } else if (rdma_link_local_addr(&in6)) {
fe2caefc 2043 rdma_get_ll_mac(&in6, mac_addr);
f99b1649 2044 } else {
ef99c4c2 2045 pr_err("%s() fail to resolve mac_addr.\n", __func__);
fe2caefc
PP		 2046 return -EINVAL;
2047 }
2048 return 0;
2049}
2050
f99b1649 2051static int ocrdma_set_av_params(struct ocrdma_qp *qp,
fe2caefc
PP		 2052 struct ocrdma_modify_qp *cmd,
2053 struct ib_qp_attr *attrs)
2054{
f99b1649 2055 int status;
fe2caefc 2056 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
9c58726b 2057 union ib_gid sgid, zgid;
fe2caefc
PP		 2058 u32 vlan_id;
2059 u8 mac_addr[6];
9c58726b 2060
fe2caefc 2061 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
f99b1649 2062 return -EINVAL;
fe2caefc
PP		 2063 cmd->params.tclass_sq_psn |=
2064 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2065 cmd->params.rnt_rc_sl_fl |=
2066 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2067 cmd->params.hop_lmt_rq_psn |=
2068 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2069 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2070 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2071 sizeof(cmd->params.dgid));
f99b1649 2072 status = ocrdma_query_gid(&qp->dev->ibdev, 1,
fe2caefc 2073 ah_attr->grh.sgid_index, &sgid);
f99b1649
NG		 2074 if (status)
2075 return status;
9c58726b
NG		 2076
2077 memset(&zgid, 0, sizeof(zgid));
2078 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2079 return -EINVAL;
2080
fe2caefc
PP		 2081 qp->sgid_idx = ah_attr->grh.sgid_index;
2082 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2083 ocrdma_resolve_dgid(qp->dev, &ah_attr->grh.dgid, &mac_addr[0]);
2084 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2085 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2086 /* convert them to LE format. */
2087 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2088 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2089 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2090 vlan_id = rdma_get_vlan_id(&sgid);
2091 if (vlan_id && (vlan_id < 0x1000)) {
2092 cmd->params.vlan_dmac_b4_to_b5 |=
2093 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2094 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2095 }
f99b1649 2096 return 0;
fe2caefc
PP		 2097}
2098
2099static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2100 struct ocrdma_modify_qp *cmd,
2101 struct ib_qp_attr *attrs, int attr_mask,
2102 enum ib_qp_state old_qps)
2103{
2104 int status = 0;
fe2caefc
PP		 2105
2106 if (attr_mask & IB_QP_PKEY_INDEX) {
2107 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2108 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2109 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2110 }
2111 if (attr_mask & IB_QP_QKEY) {
2112 qp->qkey = attrs->qkey;
2113 cmd->params.qkey = attrs->qkey;
2114 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2115 }
f99b1649
NG		 2116 if (attr_mask & IB_QP_AV) {
2117 status = ocrdma_set_av_params(qp, cmd, attrs);
2118 if (status)
2119 return status;
2120 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
fe2caefc
PP		 2121 /* set the default mac address for UD, GSI QPs */
2122 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2123 (qp->dev->nic_info.mac_addr[1] << 8) |
2124 (qp->dev->nic_info.mac_addr[2] << 16) |
2125 (qp->dev->nic_info.mac_addr[3] << 24);
2126 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2127 (qp->dev->nic_info.mac_addr[5] << 8);
2128 }
2129 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2130 attrs->en_sqd_async_notify) {
2131 cmd->params.max_sge_recv_flags |=
2132 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2133 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2134 }
2135 if (attr_mask & IB_QP_DEST_QPN) {
2136 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2137 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2138 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2139 }
2140 if (attr_mask & IB_QP_PATH_MTU) {
d3cb6c0b
NG		 2141 if (attrs->path_mtu < IB_MTU_256 ||
2142 attrs->path_mtu > IB_MTU_4096) {
fe2caefc
PP		 2143 status = -EINVAL;
2144 goto pmtu_err;
2145 }
2146 cmd->params.path_mtu_pkey_indx |=
2147 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2148 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2149 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2150 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2151 }
2152 if (attr_mask & IB_QP_TIMEOUT) {
2153 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2154 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2155 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2156 }
2157 if (attr_mask & IB_QP_RETRY_CNT) {
2158 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2159 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2160 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2161 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2162 }
2163 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2164 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2165 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2166 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2167 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2168 }
2169 if (attr_mask & IB_QP_RNR_RETRY) {
2170 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2171 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2172 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2173 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2174 }
2175 if (attr_mask & IB_QP_SQ_PSN) {
2176 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2177 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2178 }
2179 if (attr_mask & IB_QP_RQ_PSN) {
2180 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2181 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2182 }
2183 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2184 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2185 status = -EINVAL;
2186 goto pmtu_err;
2187 }
2188 qp->max_ord = attrs->max_rd_atomic;
2189 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2190 }
2191 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2192 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2193 status = -EINVAL;
2194 goto pmtu_err;
2195 }
2196 qp->max_ird = attrs->max_dest_rd_atomic;
2197 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2198 }
2199 cmd->params.max_ord_ird = (qp->max_ord <<
2200 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2201 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2202pmtu_err:
2203 return status;
2204}
2205
2206int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2207 struct ib_qp_attr *attrs, int attr_mask,
2208 enum ib_qp_state old_qps)
2209{
2210 int status = -ENOMEM;
2211 struct ocrdma_modify_qp *cmd;
fe2caefc
PP		 2212
2213 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2214 if (!cmd)
2215 return status;
2216
2217 cmd->params.id = qp->id;
2218 cmd->flags = 0;
2219 if (attr_mask & IB_QP_STATE) {
2220 cmd->params.max_sge_recv_flags |=
2221 (get_ocrdma_qp_state(attrs->qp_state) <<
2222 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2223 OCRDMA_QP_PARAMS_STATE_MASK;
2224 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
f99b1649 2225 } else {
fe2caefc
PP		 2226 cmd->params.max_sge_recv_flags |=
2227 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2228 OCRDMA_QP_PARAMS_STATE_MASK;
f99b1649
NG		 2229 }
2230
fe2caefc
PP		 2231 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask, old_qps);
2232 if (status)
2233 goto mbx_err;
2234 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2235 if (status)
2236 goto mbx_err;
c592c423 2237
fe2caefc
PP		 2238mbx_err:
2239 kfree(cmd);
2240 return status;
2241}
2242
2243int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2244{
2245 int status = -ENOMEM;
2246 struct ocrdma_destroy_qp *cmd;
fe2caefc
PP		 2247 struct pci_dev *pdev = dev->nic_info.pdev;
2248
2249 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2250 if (!cmd)
2251 return status;
2252 cmd->qp_id = qp->id;
2253 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2254 if (status)
2255 goto mbx_err;
c592c423 2256
fe2caefc
PP		 2257mbx_err:
2258 kfree(cmd);
2259 if (qp->sq.va)
2260 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2261 if (!qp->srq && qp->rq.va)
2262 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2263 if (qp->dpp_enabled)
2264 qp->pd->num_dpp_qp++;
2265 return status;
2266}
2267
1afc0454 2268int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
fe2caefc
PP		 2269 struct ib_srq_init_attr *srq_attr,
2270 struct ocrdma_pd *pd)
2271{
2272 int status = -ENOMEM;
2273 int hw_pages, hw_page_size;
2274 int len;
2275 struct ocrdma_create_srq_rsp *rsp;
2276 struct ocrdma_create_srq *cmd;
2277 dma_addr_t pa;
fe2caefc
PP		 2278 struct pci_dev *pdev = dev->nic_info.pdev;
2279 u32 max_rqe_allocated;
2280
2281 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2282 if (!cmd)
2283 return status;
2284
2285 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2286 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2287 status = ocrdma_build_q_conf(&max_rqe_allocated,
2288 dev->attr.rqe_size,
2289 &hw_pages, &hw_page_size);
2290 if (status) {
ef99c4c2
NG		 2291 pr_err("%s() req. max_wr=0x%x\n", __func__,
2292 srq_attr->attr.max_wr);
fe2caefc
PP		 2293 status = -EINVAL;
2294 goto ret;
2295 }
2296 len = hw_pages * hw_page_size;
2297 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2298 if (!srq->rq.va) {
2299 status = -ENOMEM;
2300 goto ret;
2301 }
2302 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2303
2304 srq->rq.entry_size = dev->attr.rqe_size;
2305 srq->rq.pa = pa;
2306 srq->rq.len = len;
2307 srq->rq.max_cnt = max_rqe_allocated;
2308
2309 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2310 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2311 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2312
2313 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2314 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2315 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2316 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2317 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2318 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2319
2320 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2321 if (status)
2322 goto mbx_err;
2323 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2324 srq->id = rsp->id;
2325 srq->rq.dbid = rsp->id;
2326 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2327 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2328 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2329 max_rqe_allocated = (1 << max_rqe_allocated);
2330 srq->rq.max_cnt = max_rqe_allocated;
2331 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2332 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2333 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2334 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2335 goto ret;
2336mbx_err:
2337 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2338ret:
2339 kfree(cmd);
2340 return status;
2341}
2342
2343int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2344{
2345 int status = -ENOMEM;
2346 struct ocrdma_modify_srq *cmd;
1afc0454
NG		 2347 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2348
fe2caefc
PP		 2349 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2350 if (!cmd)
2351 return status;
2352 cmd->id = srq->id;
2353 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2354 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
1afc0454 2355 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2356 kfree(cmd);
2357 return status;
2358}
2359
2360int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2361{
2362 int status = -ENOMEM;
2363 struct ocrdma_query_srq *cmd;
1afc0454
NG		 2364 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2365
fe2caefc
PP		 2366 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2367 if (!cmd)
2368 return status;
2369 cmd->id = srq->rq.dbid;
1afc0454 2370 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2371 if (status == 0) {
2372 struct ocrdma_query_srq_rsp *rsp =
2373 (struct ocrdma_query_srq_rsp *)cmd;
2374 srq_attr->max_sge =
2375 rsp->srq_lmt_max_sge &
2376 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2377 srq_attr->max_wr =
2378 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2379 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2380 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2381 }
2382 kfree(cmd);
2383 return status;
2384}
2385
2386int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2387{
2388 int status = -ENOMEM;
2389 struct ocrdma_destroy_srq *cmd;
2390 struct pci_dev *pdev = dev->nic_info.pdev;
2391 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2392 if (!cmd)
2393 return status;
2394 cmd->id = srq->id;
1afc0454 2395 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
fe2caefc
PP		 2396 if (srq->rq.va)
2397 dma_free_coherent(&pdev->dev, srq->rq.len,
2398 srq->rq.va, srq->rq.pa);
2399 kfree(cmd);
2400 return status;
2401}
2402
2403int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2404{
2405 int i;
2406 int status = -EINVAL;
2407 struct ocrdma_av *av;
2408 unsigned long flags;
2409
2410 av = dev->av_tbl.va;
2411 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2412 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2413 if (av->valid == 0) {
2414 av->valid = OCRDMA_AV_VALID;
2415 ah->av = av;
2416 ah->id = i;
2417 status = 0;
2418 break;
2419 }
2420 av++;
2421 }
2422 if (i == dev->av_tbl.num_ah)
2423 status = -EAGAIN;
2424 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2425 return status;
2426}
2427
2428int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2429{
2430 unsigned long flags;
2431 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2432 ah->av->valid = 0;
2433 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2434 return 0;
2435}
2436
2437static int ocrdma_create_mq_eq(struct ocrdma_dev *dev)
2438{
2439 int status;
2440 int irq;
2441 unsigned long flags = 0;
2442 int num_eq = 0;
2443
f99b1649 2444 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
fe2caefc 2445 flags = IRQF_SHARED;
f99b1649 2446 } else {
fe2caefc
PP		 2447 num_eq = dev->nic_info.msix.num_vectors -
2448 dev->nic_info.msix.start_vector;
2449 /* minimum two vectors/eq are required for rdma to work.
2450 * one for control path and one for data path.
2451 */
2452 if (num_eq < 2)
2453 return -EBUSY;
2454 }
2455
2456 status = ocrdma_create_eq(dev, &dev->meq, OCRDMA_EQ_LEN);
2457 if (status)
2458 return status;
2459 sprintf(dev->meq.irq_name, "ocrdma_mq%d", dev->id);
2460 irq = ocrdma_get_irq(dev, &dev->meq);
2461 status = request_irq(irq, ocrdma_irq_handler, flags, dev->meq.irq_name,
2462 &dev->meq);
2463 if (status)
2464 _ocrdma_destroy_eq(dev, &dev->meq);
2465 return status;
2466}
2467
2468static int ocrdma_create_qp_eqs(struct ocrdma_dev *dev)
2469{
da496438 2470 int num_eq, i, status = 0;
fe2caefc
PP		 2471 int irq;
2472 unsigned long flags = 0;
2473
2474 num_eq = dev->nic_info.msix.num_vectors -
2475 dev->nic_info.msix.start_vector;
2476 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2477 num_eq = 1;
2478 flags = IRQF_SHARED;
f99b1649 2479 } else {
fe2caefc 2480 num_eq = min_t(u32, num_eq, num_online_cpus());
f99b1649
NG		 2481 }
2482
fe2caefc
PP		 2483 dev->qp_eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2484 if (!dev->qp_eq_tbl)
2485 return -ENOMEM;
2486
2487 for (i = 0; i < num_eq; i++) {
2488 status = ocrdma_create_eq(dev, &dev->qp_eq_tbl[i],
2489 OCRDMA_EQ_LEN);
2490 if (status) {
2491 status = -EINVAL;
2492 break;
2493 }
2494 sprintf(dev->qp_eq_tbl[i].irq_name, "ocrdma_qp%d-%d",
2495 dev->id, i);
2496 irq = ocrdma_get_irq(dev, &dev->qp_eq_tbl[i]);
2497 status = request_irq(irq, ocrdma_irq_handler, flags,
2498 dev->qp_eq_tbl[i].irq_name,
2499 &dev->qp_eq_tbl[i]);
2500 if (status) {
2501 _ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
2502 status = -EINVAL;
2503 break;
2504 }
2505 dev->eq_cnt += 1;
2506 }
2507 /* one eq is sufficient for data path to work */
2508 if (dev->eq_cnt >= 1)
2509 return 0;
f99b1649 2510 ocrdma_destroy_qp_eqs(dev);
fe2caefc
PP		 2511 return status;
2512}
2513
2514int ocrdma_init_hw(struct ocrdma_dev *dev)
2515{
2516 int status;
2517 /* set up control path eq */
2518 status = ocrdma_create_mq_eq(dev);
2519 if (status)
2520 return status;
2521 /* set up data path eq */
2522 status = ocrdma_create_qp_eqs(dev);
2523 if (status)
2524 goto qpeq_err;
2525 status = ocrdma_create_mq(dev);
2526 if (status)
2527 goto mq_err;
2528 status = ocrdma_mbx_query_fw_config(dev);
2529 if (status)
2530 goto conf_err;
2531 status = ocrdma_mbx_query_dev(dev);
2532 if (status)
2533 goto conf_err;
2534 status = ocrdma_mbx_query_fw_ver(dev);
2535 if (status)
2536 goto conf_err;
2537 status = ocrdma_mbx_create_ah_tbl(dev);
2538 if (status)
2539 goto conf_err;
2540 return 0;
2541
2542conf_err:
2543 ocrdma_destroy_mq(dev);
2544mq_err:
2545 ocrdma_destroy_qp_eqs(dev);
2546qpeq_err:
2547 ocrdma_destroy_eq(dev, &dev->meq);
ef99c4c2 2548 pr_err("%s() status=%d\n", __func__, status);
fe2caefc
PP		 2549 return status;
2550}
2551
2552void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2553{
2554 ocrdma_mbx_delete_ah_tbl(dev);
2555
2556 /* cleanup the data path eqs */
2557 ocrdma_destroy_qp_eqs(dev);
2558
2559 /* cleanup the control path */
2560 ocrdma_destroy_mq(dev);
2561 ocrdma_destroy_eq(dev, &dev->meq);
2562}
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