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fe2caefc PP |
1 | /******************************************************************* |
2 | * This file is part of the Emulex RoCE Device Driver for * | |
3 | * RoCE (RDMA over Converged Ethernet) CNA Adapters. * | |
4 | * Copyright (C) 2008-2012 Emulex. All rights reserved. * | |
5 | * EMULEX and SLI are trademarks of Emulex. * | |
6 | * www.emulex.com * | |
7 | * * | |
8 | * This program is free software; you can redistribute it and/or * | |
9 | * modify it under the terms of version 2 of the GNU General * | |
10 | * Public License as published by the Free Software Foundation. * | |
11 | * This program is distributed in the hope that it will be useful. * | |
12 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * | |
13 | * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * | |
14 | * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * | |
15 | * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * | |
16 | * TO BE LEGALLY INVALID. See the GNU General Public License for * | |
17 | * more details, a copy of which can be found in the file COPYING * | |
18 | * included with this package. * | |
19 | * | |
20 | * Contact Information: | |
21 | * linux-drivers@emulex.com | |
22 | * | |
23 | * Emulex | |
24 | * 3333 Susan Street | |
25 | * Costa Mesa, CA 92626 | |
26 | *******************************************************************/ | |
27 | ||
28 | #include <linux/sched.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/log2.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | ||
33 | #include <rdma/ib_verbs.h> | |
34 | #include <rdma/ib_user_verbs.h> | |
fe2caefc PP |
35 | |
36 | #include "ocrdma.h" | |
37 | #include "ocrdma_hw.h" | |
38 | #include "ocrdma_verbs.h" | |
39 | #include "ocrdma_ah.h" | |
40 | ||
41 | enum mbx_status { | |
42 | OCRDMA_MBX_STATUS_FAILED = 1, | |
43 | OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3, | |
44 | OCRDMA_MBX_STATUS_OOR = 100, | |
45 | OCRDMA_MBX_STATUS_INVALID_PD = 101, | |
46 | OCRDMA_MBX_STATUS_PD_INUSE = 102, | |
47 | OCRDMA_MBX_STATUS_INVALID_CQ = 103, | |
48 | OCRDMA_MBX_STATUS_INVALID_QP = 104, | |
49 | OCRDMA_MBX_STATUS_INVALID_LKEY = 105, | |
50 | OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106, | |
51 | OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107, | |
52 | OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108, | |
53 | OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109, | |
54 | OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110, | |
55 | OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111, | |
56 | OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112, | |
57 | OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113, | |
58 | OCRDMA_MBX_STATUS_MW_BOUND = 114, | |
59 | OCRDMA_MBX_STATUS_INVALID_VA = 115, | |
60 | OCRDMA_MBX_STATUS_INVALID_LENGTH = 116, | |
61 | OCRDMA_MBX_STATUS_INVALID_FBO = 117, | |
62 | OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118, | |
63 | OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119, | |
64 | OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120, | |
65 | OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121, | |
66 | OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129, | |
67 | OCRDMA_MBX_STATUS_SRQ_ERROR = 133, | |
68 | OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134, | |
69 | OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135, | |
70 | OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136, | |
71 | OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137, | |
72 | OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138, | |
73 | OCRDMA_MBX_STATUS_QP_BOUND = 130, | |
74 | OCRDMA_MBX_STATUS_INVALID_CHANGE = 139, | |
75 | OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140, | |
76 | OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141, | |
77 | OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142, | |
78 | OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143, | |
79 | OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144 | |
80 | }; | |
81 | ||
82 | enum additional_status { | |
83 | OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22 | |
84 | }; | |
85 | ||
86 | enum cqe_status { | |
87 | OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1, | |
88 | OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2, | |
89 | OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3, | |
90 | OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4, | |
91 | OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5 | |
92 | }; | |
93 | ||
94 | static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq) | |
95 | { | |
f99b1649 | 96 | return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe)); |
fe2caefc PP |
97 | } |
98 | ||
99 | static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq) | |
100 | { | |
101 | eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1); | |
102 | } | |
103 | ||
104 | static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev) | |
105 | { | |
106 | struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *) | |
f99b1649 | 107 | (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe))); |
fe2caefc PP |
108 | |
109 | if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK)) | |
110 | return NULL; | |
111 | return cqe; | |
112 | } | |
113 | ||
114 | static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev) | |
115 | { | |
116 | dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1); | |
117 | } | |
118 | ||
119 | static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev) | |
120 | { | |
f99b1649 | 121 | return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe)); |
fe2caefc PP |
122 | } |
123 | ||
124 | static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev) | |
125 | { | |
126 | dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1); | |
fe2caefc PP |
127 | } |
128 | ||
129 | static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev) | |
130 | { | |
f99b1649 | 131 | return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe)); |
fe2caefc PP |
132 | } |
133 | ||
134 | enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps) | |
135 | { | |
136 | switch (qps) { | |
137 | case OCRDMA_QPS_RST: | |
138 | return IB_QPS_RESET; | |
139 | case OCRDMA_QPS_INIT: | |
140 | return IB_QPS_INIT; | |
141 | case OCRDMA_QPS_RTR: | |
142 | return IB_QPS_RTR; | |
143 | case OCRDMA_QPS_RTS: | |
144 | return IB_QPS_RTS; | |
145 | case OCRDMA_QPS_SQD: | |
146 | case OCRDMA_QPS_SQ_DRAINING: | |
147 | return IB_QPS_SQD; | |
148 | case OCRDMA_QPS_SQE: | |
149 | return IB_QPS_SQE; | |
150 | case OCRDMA_QPS_ERR: | |
151 | return IB_QPS_ERR; | |
2b50176d | 152 | } |
fe2caefc PP |
153 | return IB_QPS_ERR; |
154 | } | |
155 | ||
abe3afac | 156 | static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps) |
fe2caefc PP |
157 | { |
158 | switch (qps) { | |
159 | case IB_QPS_RESET: | |
160 | return OCRDMA_QPS_RST; | |
161 | case IB_QPS_INIT: | |
162 | return OCRDMA_QPS_INIT; | |
163 | case IB_QPS_RTR: | |
164 | return OCRDMA_QPS_RTR; | |
165 | case IB_QPS_RTS: | |
166 | return OCRDMA_QPS_RTS; | |
167 | case IB_QPS_SQD: | |
168 | return OCRDMA_QPS_SQD; | |
169 | case IB_QPS_SQE: | |
170 | return OCRDMA_QPS_SQE; | |
171 | case IB_QPS_ERR: | |
172 | return OCRDMA_QPS_ERR; | |
2b50176d | 173 | } |
fe2caefc PP |
174 | return OCRDMA_QPS_ERR; |
175 | } | |
176 | ||
177 | static int ocrdma_get_mbx_errno(u32 status) | |
178 | { | |
f99b1649 | 179 | int err_num; |
fe2caefc PP |
180 | u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >> |
181 | OCRDMA_MBX_RSP_STATUS_SHIFT; | |
182 | u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >> | |
183 | OCRDMA_MBX_RSP_ASTATUS_SHIFT; | |
184 | ||
185 | switch (mbox_status) { | |
186 | case OCRDMA_MBX_STATUS_OOR: | |
187 | case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS: | |
188 | err_num = -EAGAIN; | |
189 | break; | |
190 | ||
191 | case OCRDMA_MBX_STATUS_INVALID_PD: | |
192 | case OCRDMA_MBX_STATUS_INVALID_CQ: | |
193 | case OCRDMA_MBX_STATUS_INVALID_SRQ_ID: | |
194 | case OCRDMA_MBX_STATUS_INVALID_QP: | |
195 | case OCRDMA_MBX_STATUS_INVALID_CHANGE: | |
196 | case OCRDMA_MBX_STATUS_MTU_EXCEEDS: | |
197 | case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER: | |
198 | case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID: | |
199 | case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS: | |
200 | case OCRDMA_MBX_STATUS_ILLEGAL_FIELD: | |
201 | case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY: | |
202 | case OCRDMA_MBX_STATUS_INVALID_LKEY: | |
203 | case OCRDMA_MBX_STATUS_INVALID_VA: | |
204 | case OCRDMA_MBX_STATUS_INVALID_LENGTH: | |
205 | case OCRDMA_MBX_STATUS_INVALID_FBO: | |
206 | case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS: | |
207 | case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE: | |
208 | case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP: | |
209 | case OCRDMA_MBX_STATUS_SRQ_ERROR: | |
210 | case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS: | |
211 | err_num = -EINVAL; | |
212 | break; | |
213 | ||
214 | case OCRDMA_MBX_STATUS_PD_INUSE: | |
215 | case OCRDMA_MBX_STATUS_QP_BOUND: | |
216 | case OCRDMA_MBX_STATUS_MW_STILL_BOUND: | |
217 | case OCRDMA_MBX_STATUS_MW_BOUND: | |
218 | err_num = -EBUSY; | |
219 | break; | |
220 | ||
221 | case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS: | |
222 | case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS: | |
223 | case OCRDMA_MBX_STATUS_RQE_EXCEEDS: | |
224 | case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS: | |
225 | case OCRDMA_MBX_STATUS_ORD_EXCEEDS: | |
226 | case OCRDMA_MBX_STATUS_IRD_EXCEEDS: | |
227 | case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS: | |
228 | case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS: | |
229 | case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS: | |
230 | err_num = -ENOBUFS; | |
231 | break; | |
232 | ||
233 | case OCRDMA_MBX_STATUS_FAILED: | |
234 | switch (add_status) { | |
235 | case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES: | |
236 | err_num = -EAGAIN; | |
237 | break; | |
238 | } | |
239 | default: | |
240 | err_num = -EFAULT; | |
241 | } | |
242 | return err_num; | |
243 | } | |
244 | ||
a51f06e1 SX |
245 | char *port_speed_string(struct ocrdma_dev *dev) |
246 | { | |
247 | char *str = ""; | |
248 | u16 speeds_supported; | |
249 | ||
250 | speeds_supported = dev->phy.fixed_speeds_supported | | |
251 | dev->phy.auto_speeds_supported; | |
252 | if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS) | |
253 | str = "40Gbps "; | |
254 | else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS) | |
255 | str = "10Gbps "; | |
256 | else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS) | |
257 | str = "1Gbps "; | |
258 | ||
259 | return str; | |
260 | } | |
261 | ||
fe2caefc PP |
262 | static int ocrdma_get_mbx_cqe_errno(u16 cqe_status) |
263 | { | |
264 | int err_num = -EINVAL; | |
265 | ||
266 | switch (cqe_status) { | |
267 | case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES: | |
268 | err_num = -EPERM; | |
269 | break; | |
270 | case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER: | |
271 | err_num = -EINVAL; | |
272 | break; | |
273 | case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES: | |
274 | case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING: | |
f11220ee | 275 | err_num = -EINVAL; |
fe2caefc PP |
276 | break; |
277 | case OCRDMA_MBX_CQE_STATUS_DMA_FAILED: | |
43a6b402 | 278 | default: |
f11220ee | 279 | err_num = -EINVAL; |
fe2caefc PP |
280 | break; |
281 | } | |
282 | return err_num; | |
283 | } | |
284 | ||
285 | void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed, | |
286 | bool solicited, u16 cqe_popped) | |
287 | { | |
288 | u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK; | |
289 | ||
290 | val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) << | |
291 | OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT); | |
292 | ||
293 | if (armed) | |
294 | val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT); | |
295 | if (solicited) | |
296 | val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT); | |
297 | val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT); | |
298 | iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET); | |
299 | } | |
300 | ||
301 | static void ocrdma_ring_mq_db(struct ocrdma_dev *dev) | |
302 | { | |
303 | u32 val = 0; | |
304 | ||
305 | val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK; | |
306 | val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT; | |
307 | iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET); | |
308 | } | |
309 | ||
310 | static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id, | |
311 | bool arm, bool clear_int, u16 num_eqe) | |
312 | { | |
313 | u32 val = 0; | |
314 | ||
315 | val |= eq_id & OCRDMA_EQ_ID_MASK; | |
316 | val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT); | |
317 | if (arm) | |
318 | val |= (1 << OCRDMA_REARM_SHIFT); | |
319 | if (clear_int) | |
320 | val |= (1 << OCRDMA_EQ_CLR_SHIFT); | |
321 | val |= (1 << OCRDMA_EQ_TYPE_SHIFT); | |
322 | val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT); | |
323 | iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET); | |
324 | } | |
325 | ||
326 | static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr, | |
327 | u8 opcode, u8 subsys, u32 cmd_len) | |
328 | { | |
329 | cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT)); | |
330 | cmd_hdr->timeout = 20; /* seconds */ | |
331 | cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr); | |
332 | } | |
333 | ||
334 | static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len) | |
335 | { | |
336 | struct ocrdma_mqe *mqe; | |
337 | ||
338 | mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL); | |
339 | if (!mqe) | |
340 | return NULL; | |
341 | mqe->hdr.spcl_sge_cnt_emb |= | |
342 | (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) & | |
343 | OCRDMA_MQE_HDR_EMB_MASK; | |
344 | mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr); | |
345 | ||
346 | ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE, | |
347 | mqe->hdr.pyld_len); | |
348 | return mqe; | |
349 | } | |
350 | ||
351 | static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q) | |
352 | { | |
353 | dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma); | |
354 | } | |
355 | ||
356 | static int ocrdma_alloc_q(struct ocrdma_dev *dev, | |
357 | struct ocrdma_queue_info *q, u16 len, u16 entry_size) | |
358 | { | |
359 | memset(q, 0, sizeof(*q)); | |
360 | q->len = len; | |
361 | q->entry_size = entry_size; | |
362 | q->size = len * entry_size; | |
363 | q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size, | |
364 | &q->dma, GFP_KERNEL); | |
365 | if (!q->va) | |
366 | return -ENOMEM; | |
367 | memset(q->va, 0, q->size); | |
368 | return 0; | |
369 | } | |
370 | ||
371 | static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt, | |
372 | dma_addr_t host_pa, int hw_page_size) | |
373 | { | |
374 | int i; | |
375 | ||
376 | for (i = 0; i < cnt; i++) { | |
377 | q_pa[i].lo = (u32) (host_pa & 0xffffffff); | |
378 | q_pa[i].hi = (u32) upper_32_bits(host_pa); | |
379 | host_pa += hw_page_size; | |
380 | } | |
381 | } | |
382 | ||
fad51b7d DS |
383 | static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, |
384 | struct ocrdma_queue_info *q, int queue_type) | |
fe2caefc PP |
385 | { |
386 | u8 opcode = 0; | |
387 | int status; | |
388 | struct ocrdma_delete_q_req *cmd = dev->mbx_cmd; | |
389 | ||
390 | switch (queue_type) { | |
391 | case QTYPE_MCCQ: | |
392 | opcode = OCRDMA_CMD_DELETE_MQ; | |
393 | break; | |
394 | case QTYPE_CQ: | |
395 | opcode = OCRDMA_CMD_DELETE_CQ; | |
396 | break; | |
397 | case QTYPE_EQ: | |
398 | opcode = OCRDMA_CMD_DELETE_EQ; | |
399 | break; | |
400 | default: | |
401 | BUG(); | |
402 | } | |
403 | memset(cmd, 0, sizeof(*cmd)); | |
404 | ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
405 | cmd->id = q->id; | |
406 | ||
407 | status = be_roce_mcc_cmd(dev->nic_info.netdev, | |
408 | cmd, sizeof(*cmd), NULL, NULL); | |
409 | if (!status) | |
410 | q->created = false; | |
411 | return status; | |
412 | } | |
413 | ||
414 | static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) | |
415 | { | |
416 | int status; | |
417 | struct ocrdma_create_eq_req *cmd = dev->mbx_cmd; | |
418 | struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd; | |
419 | ||
420 | memset(cmd, 0, sizeof(*cmd)); | |
421 | ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON, | |
422 | sizeof(*cmd)); | |
fe2caefc | 423 | |
c88bd03f | 424 | cmd->req.rsvd_version = 2; |
fe2caefc PP |
425 | cmd->num_pages = 4; |
426 | cmd->valid = OCRDMA_CREATE_EQ_VALID; | |
427 | cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT; | |
428 | ||
429 | ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma, | |
430 | PAGE_SIZE_4K); | |
431 | status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL, | |
432 | NULL); | |
433 | if (!status) { | |
434 | eq->q.id = rsp->vector_eqid & 0xffff; | |
c88bd03f | 435 | eq->vector = (rsp->vector_eqid >> 16) & 0xffff; |
fe2caefc PP |
436 | eq->q.created = true; |
437 | } | |
438 | return status; | |
439 | } | |
440 | ||
441 | static int ocrdma_create_eq(struct ocrdma_dev *dev, | |
442 | struct ocrdma_eq *eq, u16 q_len) | |
443 | { | |
444 | int status; | |
445 | ||
446 | status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN, | |
447 | sizeof(struct ocrdma_eqe)); | |
448 | if (status) | |
449 | return status; | |
450 | ||
451 | status = ocrdma_mbx_create_eq(dev, eq); | |
452 | if (status) | |
453 | goto mbx_err; | |
454 | eq->dev = dev; | |
455 | ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0); | |
456 | ||
457 | return 0; | |
458 | mbx_err: | |
459 | ocrdma_free_q(dev, &eq->q); | |
460 | return status; | |
461 | } | |
462 | ||
ea617626 | 463 | int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) |
fe2caefc PP |
464 | { |
465 | int irq; | |
466 | ||
467 | if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) | |
468 | irq = dev->nic_info.pdev->irq; | |
469 | else | |
470 | irq = dev->nic_info.msix.vector_list[eq->vector]; | |
471 | return irq; | |
472 | } | |
473 | ||
474 | static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) | |
475 | { | |
476 | if (eq->q.created) { | |
477 | ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ); | |
fe2caefc PP |
478 | ocrdma_free_q(dev, &eq->q); |
479 | } | |
480 | } | |
481 | ||
482 | static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq) | |
483 | { | |
484 | int irq; | |
485 | ||
486 | /* disarm EQ so that interrupts are not generated | |
487 | * during freeing and EQ delete is in progress. | |
488 | */ | |
489 | ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0); | |
490 | ||
491 | irq = ocrdma_get_irq(dev, eq); | |
492 | free_irq(irq, eq); | |
493 | _ocrdma_destroy_eq(dev, eq); | |
494 | } | |
495 | ||
c88bd03f | 496 | static void ocrdma_destroy_eqs(struct ocrdma_dev *dev) |
fe2caefc PP |
497 | { |
498 | int i; | |
499 | ||
fe2caefc | 500 | for (i = 0; i < dev->eq_cnt; i++) |
c88bd03f | 501 | ocrdma_destroy_eq(dev, &dev->eq_tbl[i]); |
fe2caefc PP |
502 | } |
503 | ||
abe3afac RD |
504 | static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev, |
505 | struct ocrdma_queue_info *cq, | |
506 | struct ocrdma_queue_info *eq) | |
fe2caefc PP |
507 | { |
508 | struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd; | |
509 | struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd; | |
510 | int status; | |
511 | ||
512 | memset(cmd, 0, sizeof(*cmd)); | |
513 | ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ, | |
514 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
515 | ||
1afc0454 NG |
516 | cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2; |
517 | cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) << | |
518 | OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT; | |
519 | cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size); | |
520 | ||
fe2caefc | 521 | cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS; |
1afc0454 | 522 | cmd->eqn = eq->id; |
8ac0c7c7 | 523 | cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe); |
fe2caefc | 524 | |
1afc0454 | 525 | ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE, |
fe2caefc PP |
526 | cq->dma, PAGE_SIZE_4K); |
527 | status = be_roce_mcc_cmd(dev->nic_info.netdev, | |
528 | cmd, sizeof(*cmd), NULL, NULL); | |
529 | if (!status) { | |
1afc0454 | 530 | cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK); |
fe2caefc PP |
531 | cq->created = true; |
532 | } | |
533 | return status; | |
534 | } | |
535 | ||
536 | static u32 ocrdma_encoded_q_len(int q_len) | |
537 | { | |
538 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
539 | ||
540 | if (len_encoded == 16) | |
541 | len_encoded = 0; | |
542 | return len_encoded; | |
543 | } | |
544 | ||
545 | static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev, | |
546 | struct ocrdma_queue_info *mq, | |
547 | struct ocrdma_queue_info *cq) | |
548 | { | |
549 | int num_pages, status; | |
550 | struct ocrdma_create_mq_req *cmd = dev->mbx_cmd; | |
551 | struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd; | |
552 | struct ocrdma_pa *pa; | |
553 | ||
554 | memset(cmd, 0, sizeof(*cmd)); | |
555 | num_pages = PAGES_4K_SPANNED(mq->va, mq->size); | |
556 | ||
b1d58b99 NG |
557 | ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT, |
558 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
559 | cmd->req.rsvd_version = 1; | |
560 | cmd->cqid_pages = num_pages; | |
561 | cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT); | |
562 | cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID; | |
84b105db | 563 | |
de123485 JS |
564 | cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE); |
565 | cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE); | |
84b105db | 566 | |
b1d58b99 NG |
567 | cmd->async_cqid_ringsize = cq->id; |
568 | cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) << | |
569 | OCRDMA_CREATE_MQ_RING_SIZE_SHIFT); | |
570 | cmd->valid = OCRDMA_CREATE_MQ_VALID; | |
571 | pa = &cmd->pa[0]; | |
572 | ||
fe2caefc PP |
573 | ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K); |
574 | status = be_roce_mcc_cmd(dev->nic_info.netdev, | |
575 | cmd, sizeof(*cmd), NULL, NULL); | |
576 | if (!status) { | |
577 | mq->id = rsp->id; | |
578 | mq->created = true; | |
579 | } | |
580 | return status; | |
581 | } | |
582 | ||
583 | static int ocrdma_create_mq(struct ocrdma_dev *dev) | |
584 | { | |
585 | int status; | |
586 | ||
587 | /* Alloc completion queue for Mailbox queue */ | |
588 | status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN, | |
589 | sizeof(struct ocrdma_mcqe)); | |
590 | if (status) | |
591 | goto alloc_err; | |
592 | ||
ea617626 | 593 | dev->eq_tbl[0].cq_cnt++; |
c88bd03f | 594 | status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q); |
fe2caefc PP |
595 | if (status) |
596 | goto mbx_cq_free; | |
597 | ||
598 | memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx)); | |
599 | init_waitqueue_head(&dev->mqe_ctx.cmd_wait); | |
600 | mutex_init(&dev->mqe_ctx.lock); | |
601 | ||
602 | /* Alloc Mailbox queue */ | |
603 | status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN, | |
604 | sizeof(struct ocrdma_mqe)); | |
605 | if (status) | |
606 | goto mbx_cq_destroy; | |
607 | status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq); | |
608 | if (status) | |
609 | goto mbx_q_free; | |
610 | ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0); | |
611 | return 0; | |
612 | ||
613 | mbx_q_free: | |
614 | ocrdma_free_q(dev, &dev->mq.sq); | |
615 | mbx_cq_destroy: | |
616 | ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ); | |
617 | mbx_cq_free: | |
618 | ocrdma_free_q(dev, &dev->mq.cq); | |
619 | alloc_err: | |
620 | return status; | |
621 | } | |
622 | ||
623 | static void ocrdma_destroy_mq(struct ocrdma_dev *dev) | |
624 | { | |
625 | struct ocrdma_queue_info *mbxq, *cq; | |
626 | ||
627 | /* mqe_ctx lock synchronizes with any other pending cmds. */ | |
628 | mutex_lock(&dev->mqe_ctx.lock); | |
629 | mbxq = &dev->mq.sq; | |
630 | if (mbxq->created) { | |
631 | ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ); | |
632 | ocrdma_free_q(dev, mbxq); | |
633 | } | |
634 | mutex_unlock(&dev->mqe_ctx.lock); | |
635 | ||
636 | cq = &dev->mq.cq; | |
637 | if (cq->created) { | |
638 | ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ); | |
639 | ocrdma_free_q(dev, cq); | |
640 | } | |
641 | } | |
642 | ||
643 | static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev, | |
644 | struct ocrdma_qp *qp) | |
645 | { | |
646 | enum ib_qp_state new_ib_qps = IB_QPS_ERR; | |
647 | enum ib_qp_state old_ib_qps; | |
648 | ||
649 | if (qp == NULL) | |
650 | BUG(); | |
057729cb | 651 | ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps); |
fe2caefc PP |
652 | } |
653 | ||
654 | static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev, | |
655 | struct ocrdma_ae_mcqe *cqe) | |
656 | { | |
657 | struct ocrdma_qp *qp = NULL; | |
658 | struct ocrdma_cq *cq = NULL; | |
1b09a0c2 | 659 | struct ib_event ib_evt; |
fe2caefc PP |
660 | int cq_event = 0; |
661 | int qp_event = 1; | |
662 | int srq_event = 0; | |
663 | int dev_event = 0; | |
664 | int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >> | |
665 | OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT; | |
666 | ||
667 | if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID) | |
668 | qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK]; | |
669 | if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID) | |
670 | cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK]; | |
671 | ||
1b09a0c2 SX |
672 | memset(&ib_evt, 0, sizeof(ib_evt)); |
673 | ||
e9db2953 RD |
674 | ib_evt.device = &dev->ibdev; |
675 | ||
fe2caefc PP |
676 | switch (type) { |
677 | case OCRDMA_CQ_ERROR: | |
678 | ib_evt.element.cq = &cq->ibcq; | |
679 | ib_evt.event = IB_EVENT_CQ_ERR; | |
680 | cq_event = 1; | |
681 | qp_event = 0; | |
682 | break; | |
683 | case OCRDMA_CQ_OVERRUN_ERROR: | |
684 | ib_evt.element.cq = &cq->ibcq; | |
685 | ib_evt.event = IB_EVENT_CQ_ERR; | |
1228056b SX |
686 | cq_event = 1; |
687 | qp_event = 0; | |
fe2caefc PP |
688 | break; |
689 | case OCRDMA_CQ_QPCAT_ERROR: | |
690 | ib_evt.element.qp = &qp->ibqp; | |
691 | ib_evt.event = IB_EVENT_QP_FATAL; | |
692 | ocrdma_process_qpcat_error(dev, qp); | |
693 | break; | |
694 | case OCRDMA_QP_ACCESS_ERROR: | |
695 | ib_evt.element.qp = &qp->ibqp; | |
696 | ib_evt.event = IB_EVENT_QP_ACCESS_ERR; | |
697 | break; | |
698 | case OCRDMA_QP_COMM_EST_EVENT: | |
699 | ib_evt.element.qp = &qp->ibqp; | |
700 | ib_evt.event = IB_EVENT_COMM_EST; | |
701 | break; | |
702 | case OCRDMA_SQ_DRAINED_EVENT: | |
703 | ib_evt.element.qp = &qp->ibqp; | |
704 | ib_evt.event = IB_EVENT_SQ_DRAINED; | |
705 | break; | |
706 | case OCRDMA_DEVICE_FATAL_EVENT: | |
707 | ib_evt.element.port_num = 1; | |
708 | ib_evt.event = IB_EVENT_DEVICE_FATAL; | |
709 | qp_event = 0; | |
710 | dev_event = 1; | |
711 | break; | |
712 | case OCRDMA_SRQCAT_ERROR: | |
713 | ib_evt.element.srq = &qp->srq->ibsrq; | |
714 | ib_evt.event = IB_EVENT_SRQ_ERR; | |
715 | srq_event = 1; | |
716 | qp_event = 0; | |
717 | break; | |
718 | case OCRDMA_SRQ_LIMIT_EVENT: | |
719 | ib_evt.element.srq = &qp->srq->ibsrq; | |
804eaf29 | 720 | ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED; |
fe2caefc PP |
721 | srq_event = 1; |
722 | qp_event = 0; | |
723 | break; | |
724 | case OCRDMA_QP_LAST_WQE_EVENT: | |
725 | ib_evt.element.qp = &qp->ibqp; | |
726 | ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED; | |
727 | break; | |
728 | default: | |
729 | cq_event = 0; | |
730 | qp_event = 0; | |
731 | srq_event = 0; | |
732 | dev_event = 0; | |
ef99c4c2 | 733 | pr_err("%s() unknown type=0x%x\n", __func__, type); |
fe2caefc PP |
734 | break; |
735 | } | |
736 | ||
ad56ebb4 SX |
737 | if (type < OCRDMA_MAX_ASYNC_ERRORS) |
738 | atomic_inc(&dev->async_err_stats[type]); | |
739 | ||
fe2caefc PP |
740 | if (qp_event) { |
741 | if (qp->ibqp.event_handler) | |
742 | qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context); | |
743 | } else if (cq_event) { | |
744 | if (cq->ibcq.event_handler) | |
745 | cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context); | |
746 | } else if (srq_event) { | |
747 | if (qp->srq->ibsrq.event_handler) | |
748 | qp->srq->ibsrq.event_handler(&ib_evt, | |
749 | qp->srq->ibsrq. | |
750 | srq_context); | |
f99b1649 | 751 | } else if (dev_event) { |
1228056b | 752 | pr_err("%s: Fatal event received\n", dev->ibdev.name); |
fe2caefc | 753 | ib_dispatch_event(&ib_evt); |
f99b1649 | 754 | } |
fe2caefc PP |
755 | |
756 | } | |
757 | ||
84b105db NG |
758 | static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev, |
759 | struct ocrdma_ae_mcqe *cqe) | |
760 | { | |
761 | struct ocrdma_ae_pvid_mcqe *evt; | |
762 | int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >> | |
763 | OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT; | |
764 | ||
765 | switch (type) { | |
766 | case OCRDMA_ASYNC_EVENT_PVID_STATE: | |
767 | evt = (struct ocrdma_ae_pvid_mcqe *)cqe; | |
768 | if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >> | |
769 | OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT) | |
770 | dev->pvid = ((evt->tag_enabled & | |
771 | OCRDMA_AE_PVID_MCQE_TAG_MASK) >> | |
772 | OCRDMA_AE_PVID_MCQE_TAG_SHIFT); | |
773 | break; | |
31dbdd9a SX |
774 | |
775 | case OCRDMA_ASYNC_EVENT_COS_VALUE: | |
776 | atomic_set(&dev->update_sl, 1); | |
777 | break; | |
84b105db NG |
778 | default: |
779 | /* Not interested evts. */ | |
780 | break; | |
781 | } | |
782 | } | |
783 | ||
fe2caefc PP |
784 | static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe) |
785 | { | |
786 | /* async CQE processing */ | |
787 | struct ocrdma_ae_mcqe *cqe = ae_cqe; | |
788 | u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >> | |
789 | OCRDMA_AE_MCQE_EVENT_CODE_SHIFT; | |
790 | ||
84b105db | 791 | if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE) |
fe2caefc | 792 | ocrdma_dispatch_ibevent(dev, cqe); |
84b105db NG |
793 | else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE) |
794 | ocrdma_process_grp5_aync(dev, cqe); | |
fe2caefc | 795 | else |
ef99c4c2 NG |
796 | pr_err("%s(%d) invalid evt code=0x%x\n", __func__, |
797 | dev->id, evt_code); | |
fe2caefc PP |
798 | } |
799 | ||
800 | static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe) | |
801 | { | |
802 | if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) { | |
803 | dev->mqe_ctx.cqe_status = (cqe->status & | |
804 | OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT; | |
805 | dev->mqe_ctx.ext_status = | |
806 | (cqe->status & OCRDMA_MCQE_ESTATUS_MASK) | |
807 | >> OCRDMA_MCQE_ESTATUS_SHIFT; | |
808 | dev->mqe_ctx.cmd_done = true; | |
809 | wake_up(&dev->mqe_ctx.cmd_wait); | |
810 | } else | |
ef99c4c2 NG |
811 | pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n", |
812 | __func__, cqe->tag_lo, dev->mqe_ctx.tag); | |
fe2caefc PP |
813 | } |
814 | ||
815 | static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id) | |
816 | { | |
817 | u16 cqe_popped = 0; | |
818 | struct ocrdma_mcqe *cqe; | |
819 | ||
820 | while (1) { | |
821 | cqe = ocrdma_get_mcqe(dev); | |
822 | if (cqe == NULL) | |
823 | break; | |
824 | ocrdma_le32_to_cpu(cqe, sizeof(*cqe)); | |
825 | cqe_popped += 1; | |
826 | if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK) | |
827 | ocrdma_process_acqe(dev, cqe); | |
828 | else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK) | |
829 | ocrdma_process_mcqe(dev, cqe); | |
fe2caefc PP |
830 | memset(cqe, 0, sizeof(struct ocrdma_mcqe)); |
831 | ocrdma_mcq_inc_tail(dev); | |
832 | } | |
833 | ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped); | |
834 | return 0; | |
835 | } | |
836 | ||
043e9dee SX |
837 | static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev, |
838 | struct ocrdma_cq *cq, bool sq) | |
fe2caefc | 839 | { |
fe2caefc | 840 | struct ocrdma_qp *qp; |
043e9dee SX |
841 | struct list_head *cur; |
842 | struct ocrdma_cq *bcq = NULL; | |
843 | struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head); | |
844 | ||
845 | list_for_each(cur, head) { | |
846 | if (sq) | |
847 | qp = list_entry(cur, struct ocrdma_qp, sq_entry); | |
848 | else | |
849 | qp = list_entry(cur, struct ocrdma_qp, rq_entry); | |
850 | ||
fe2caefc PP |
851 | if (qp->srq) |
852 | continue; | |
853 | /* if wq and rq share the same cq, than comp_handler | |
854 | * is already invoked. | |
855 | */ | |
856 | if (qp->sq_cq == qp->rq_cq) | |
857 | continue; | |
858 | /* if completion came on sq, rq's cq is buddy cq. | |
859 | * if completion came on rq, sq's cq is buddy cq. | |
860 | */ | |
861 | if (qp->sq_cq == cq) | |
043e9dee | 862 | bcq = qp->rq_cq; |
fe2caefc | 863 | else |
043e9dee SX |
864 | bcq = qp->sq_cq; |
865 | return bcq; | |
fe2caefc | 866 | } |
043e9dee SX |
867 | return NULL; |
868 | } | |
869 | ||
870 | static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev, | |
871 | struct ocrdma_cq *cq) | |
872 | { | |
873 | unsigned long flags; | |
874 | struct ocrdma_cq *bcq = NULL; | |
875 | ||
876 | /* Go through list of QPs in error state which are using this CQ | |
877 | * and invoke its callback handler to trigger CQE processing for | |
878 | * error/flushed CQE. It is rare to find more than few entries in | |
879 | * this list as most consumers stops after getting error CQE. | |
880 | * List is traversed only once when a matching buddy cq found for a QP. | |
881 | */ | |
882 | spin_lock_irqsave(&dev->flush_q_lock, flags); | |
883 | /* Check if buddy CQ is present. | |
884 | * true - Check for SQ CQ | |
885 | * false - Check for RQ CQ | |
886 | */ | |
887 | bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true); | |
888 | if (bcq == NULL) | |
889 | bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false); | |
fe2caefc | 890 | spin_unlock_irqrestore(&dev->flush_q_lock, flags); |
043e9dee SX |
891 | |
892 | /* if there is valid buddy cq, look for its completion handler */ | |
893 | if (bcq && bcq->ibcq.comp_handler) { | |
894 | spin_lock_irqsave(&bcq->comp_handler_lock, flags); | |
895 | (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context); | |
896 | spin_unlock_irqrestore(&bcq->comp_handler_lock, flags); | |
fe2caefc PP |
897 | } |
898 | } | |
899 | ||
900 | static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx) | |
901 | { | |
902 | unsigned long flags; | |
903 | struct ocrdma_cq *cq; | |
904 | ||
905 | if (cq_idx >= OCRDMA_MAX_CQ) | |
906 | BUG(); | |
907 | ||
908 | cq = dev->cq_tbl[cq_idx]; | |
ea617626 | 909 | if (cq == NULL) |
fe2caefc | 910 | return; |
fe2caefc PP |
911 | |
912 | if (cq->ibcq.comp_handler) { | |
913 | spin_lock_irqsave(&cq->comp_handler_lock, flags); | |
914 | (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); | |
915 | spin_unlock_irqrestore(&cq->comp_handler_lock, flags); | |
916 | } | |
917 | ocrdma_qp_buddy_cq_handler(dev, cq); | |
918 | } | |
919 | ||
920 | static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id) | |
921 | { | |
922 | /* process the MQ-CQE. */ | |
923 | if (cq_id == dev->mq.cq.id) | |
924 | ocrdma_mq_cq_handler(dev, cq_id); | |
925 | else | |
926 | ocrdma_qp_cq_handler(dev, cq_id); | |
927 | } | |
928 | ||
929 | static irqreturn_t ocrdma_irq_handler(int irq, void *handle) | |
930 | { | |
931 | struct ocrdma_eq *eq = handle; | |
932 | struct ocrdma_dev *dev = eq->dev; | |
933 | struct ocrdma_eqe eqe; | |
934 | struct ocrdma_eqe *ptr; | |
fe2caefc | 935 | u16 cq_id; |
5e6f9237 | 936 | u8 mcode; |
ea617626 DS |
937 | int budget = eq->cq_cnt; |
938 | ||
939 | do { | |
fe2caefc PP |
940 | ptr = ocrdma_get_eqe(eq); |
941 | eqe = *ptr; | |
942 | ocrdma_le32_to_cpu(&eqe, sizeof(eqe)); | |
5e6f9237 DS |
943 | mcode = (eqe.id_valid & OCRDMA_EQE_MAJOR_CODE_MASK) |
944 | >> OCRDMA_EQE_MAJOR_CODE_SHIFT; | |
945 | if (mcode == OCRDMA_MAJOR_CODE_SENTINAL) | |
946 | pr_err("EQ full on eqid = 0x%x, eqe = 0x%x\n", | |
947 | eq->q.id, eqe.id_valid); | |
fe2caefc PP |
948 | if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0) |
949 | break; | |
ea617626 | 950 | |
fe2caefc | 951 | ptr->id_valid = 0; |
ea617626 DS |
952 | /* ring eq doorbell as soon as its consumed. */ |
953 | ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1); | |
fe2caefc PP |
954 | /* check whether its CQE or not. */ |
955 | if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) { | |
956 | cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT; | |
957 | ocrdma_cq_handler(dev, cq_id); | |
958 | } | |
959 | ocrdma_eq_inc_tail(eq); | |
ea617626 DS |
960 | |
961 | /* There can be a stale EQE after the last bound CQ is | |
962 | * destroyed. EQE valid and budget == 0 implies this. | |
963 | */ | |
964 | if (budget) | |
965 | budget--; | |
966 | ||
967 | } while (budget); | |
968 | ||
b4dbe8d5 | 969 | eq->aic_obj.eq_intr_cnt++; |
ea617626 | 970 | ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0); |
fe2caefc PP |
971 | return IRQ_HANDLED; |
972 | } | |
973 | ||
974 | static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd) | |
975 | { | |
976 | struct ocrdma_mqe *mqe; | |
977 | ||
978 | dev->mqe_ctx.tag = dev->mq.sq.head; | |
979 | dev->mqe_ctx.cmd_done = false; | |
980 | mqe = ocrdma_get_mqe(dev); | |
981 | cmd->hdr.tag_lo = dev->mq.sq.head; | |
982 | ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe)); | |
983 | /* make sure descriptor is written before ringing doorbell */ | |
984 | wmb(); | |
985 | ocrdma_mq_inc_head(dev); | |
986 | ocrdma_ring_mq_db(dev); | |
987 | } | |
988 | ||
989 | static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev) | |
990 | { | |
991 | long status; | |
992 | /* 30 sec timeout */ | |
993 | status = wait_event_timeout(dev->mqe_ctx.cmd_wait, | |
994 | (dev->mqe_ctx.cmd_done != false), | |
995 | msecs_to_jiffies(30000)); | |
996 | if (status) | |
997 | return 0; | |
6dab0264 MA |
998 | else { |
999 | dev->mqe_ctx.fw_error_state = true; | |
1000 | pr_err("%s(%d) mailbox timeout: fw not responding\n", | |
1001 | __func__, dev->id); | |
fe2caefc | 1002 | return -1; |
6dab0264 | 1003 | } |
fe2caefc PP |
1004 | } |
1005 | ||
1006 | /* issue a mailbox command on the MQ */ | |
1007 | static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe) | |
1008 | { | |
1009 | int status = 0; | |
1010 | u16 cqe_status, ext_status; | |
bbc5ec52 SX |
1011 | struct ocrdma_mqe *rsp_mqe; |
1012 | struct ocrdma_mbx_rsp *rsp = NULL; | |
fe2caefc PP |
1013 | |
1014 | mutex_lock(&dev->mqe_ctx.lock); | |
6dab0264 MA |
1015 | if (dev->mqe_ctx.fw_error_state) |
1016 | goto mbx_err; | |
fe2caefc PP |
1017 | ocrdma_post_mqe(dev, mqe); |
1018 | status = ocrdma_wait_mqe_cmpl(dev); | |
1019 | if (status) | |
1020 | goto mbx_err; | |
1021 | cqe_status = dev->mqe_ctx.cqe_status; | |
1022 | ext_status = dev->mqe_ctx.ext_status; | |
bbc5ec52 SX |
1023 | rsp_mqe = ocrdma_get_mqe_rsp(dev); |
1024 | ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe))); | |
1025 | if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >> | |
1026 | OCRDMA_MQE_HDR_EMB_SHIFT) | |
1027 | rsp = &mqe->u.rsp; | |
1028 | ||
fe2caefc | 1029 | if (cqe_status || ext_status) { |
bbc5ec52 SX |
1030 | pr_err("%s() cqe_status=0x%x, ext_status=0x%x,", |
1031 | __func__, cqe_status, ext_status); | |
1032 | if (rsp) { | |
1033 | /* This is for embedded cmds. */ | |
1034 | pr_err("opcode=0x%x, subsystem=0x%x\n", | |
1035 | (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >> | |
1036 | OCRDMA_MBX_RSP_OPCODE_SHIFT, | |
1037 | (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >> | |
1038 | OCRDMA_MBX_RSP_SUBSYS_SHIFT); | |
1039 | } | |
fe2caefc PP |
1040 | status = ocrdma_get_mbx_cqe_errno(cqe_status); |
1041 | goto mbx_err; | |
1042 | } | |
bbc5ec52 SX |
1043 | /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */ |
1044 | if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)) | |
fe2caefc PP |
1045 | status = ocrdma_get_mbx_errno(mqe->u.rsp.status); |
1046 | mbx_err: | |
1047 | mutex_unlock(&dev->mqe_ctx.lock); | |
1048 | return status; | |
1049 | } | |
1050 | ||
bbc5ec52 SX |
1051 | static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe, |
1052 | void *payload_va) | |
1053 | { | |
1054 | int status = 0; | |
1055 | struct ocrdma_mbx_rsp *rsp = payload_va; | |
1056 | ||
1057 | if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >> | |
1058 | OCRDMA_MQE_HDR_EMB_SHIFT) | |
1059 | BUG(); | |
1060 | ||
1061 | status = ocrdma_mbx_cmd(dev, mqe); | |
1062 | if (!status) | |
1063 | /* For non embedded, only CQE failures are handled in | |
1064 | * ocrdma_mbx_cmd. We need to check for RSP errors. | |
1065 | */ | |
1066 | if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK) | |
1067 | status = ocrdma_get_mbx_errno(rsp->status); | |
1068 | ||
1069 | if (status) | |
1070 | pr_err("opcode=0x%x, subsystem=0x%x\n", | |
1071 | (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >> | |
1072 | OCRDMA_MBX_RSP_OPCODE_SHIFT, | |
1073 | (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >> | |
1074 | OCRDMA_MBX_RSP_SUBSYS_SHIFT); | |
1075 | return status; | |
1076 | } | |
1077 | ||
fe2caefc PP |
1078 | static void ocrdma_get_attr(struct ocrdma_dev *dev, |
1079 | struct ocrdma_dev_attr *attr, | |
1080 | struct ocrdma_mbx_query_config *rsp) | |
1081 | { | |
fe2caefc PP |
1082 | attr->max_pd = |
1083 | (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >> | |
1084 | OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT; | |
9ba1377d MA |
1085 | attr->max_dpp_pds = |
1086 | (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >> | |
1087 | OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET; | |
fe2caefc PP |
1088 | attr->max_qp = |
1089 | (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >> | |
1090 | OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT; | |
fad51b7d DS |
1091 | attr->max_srq = |
1092 | (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >> | |
1093 | OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET; | |
fe2caefc PP |
1094 | attr->max_send_sge = ((rsp->max_write_send_sge & |
1095 | OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >> | |
1096 | OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT); | |
1097 | attr->max_recv_sge = (rsp->max_write_send_sge & | |
1098 | OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >> | |
1099 | OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT; | |
634c5796 MV |
1100 | attr->max_srq_sge = (rsp->max_srq_rqe_sge & |
1101 | OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >> | |
1102 | OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET; | |
45e86b33 NG |
1103 | attr->max_rdma_sge = (rsp->max_write_send_sge & |
1104 | OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >> | |
1105 | OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT; | |
fe2caefc PP |
1106 | attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp & |
1107 | OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >> | |
1108 | OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT; | |
1109 | attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp & | |
1110 | OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >> | |
1111 | OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT; | |
1112 | attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord & | |
1113 | OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >> | |
1114 | OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT; | |
1115 | attr->srq_supported = (rsp->qp_srq_cq_ird_ord & | |
1116 | OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >> | |
1117 | OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT; | |
1118 | attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay & | |
1119 | OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >> | |
1120 | OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT; | |
ac578aef | 1121 | attr->max_mw = rsp->max_mw; |
fe2caefc | 1122 | attr->max_mr = rsp->max_mr; |
033edd4d MA |
1123 | attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) | |
1124 | rsp->max_mr_size_lo; | |
fe2caefc PP |
1125 | attr->max_fmr = 0; |
1126 | attr->max_pages_per_frmr = rsp->max_pages_per_frmr; | |
1127 | attr->max_num_mr_pbl = rsp->max_num_mr_pbl; | |
1128 | attr->max_cqe = rsp->max_cq_cqes_per_cq & | |
1129 | OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK; | |
c43e9ab8 NG |
1130 | attr->max_cq = (rsp->max_cq_cqes_per_cq & |
1131 | OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >> | |
1132 | OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET; | |
fe2caefc PP |
1133 | attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs & |
1134 | OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >> | |
1135 | OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) * | |
1136 | OCRDMA_WQE_STRIDE; | |
1137 | attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs & | |
1138 | OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >> | |
1139 | OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) * | |
1140 | OCRDMA_WQE_STRIDE; | |
1141 | attr->max_inline_data = | |
1142 | attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) + | |
1143 | sizeof(struct ocrdma_sge)); | |
21c3391a | 1144 | if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) { |
fe2caefc PP |
1145 | attr->ird = 1; |
1146 | attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE; | |
1147 | attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES; | |
07bb5424 MV |
1148 | } |
1149 | dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >> | |
1150 | OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET; | |
1151 | dev->attr.max_rqe = rsp->max_wqes_rqes_per_q & | |
1152 | OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK; | |
fe2caefc PP |
1153 | } |
1154 | ||
1155 | static int ocrdma_check_fw_config(struct ocrdma_dev *dev, | |
1156 | struct ocrdma_fw_conf_rsp *conf) | |
1157 | { | |
1158 | u32 fn_mode; | |
1159 | ||
1160 | fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA; | |
1161 | if (fn_mode != OCRDMA_FN_MODE_RDMA) | |
1162 | return -EINVAL; | |
1163 | dev->base_eqid = conf->base_eqid; | |
1164 | dev->max_eq = conf->max_eq; | |
fe2caefc PP |
1165 | return 0; |
1166 | } | |
1167 | ||
1168 | /* can be issued only during init time. */ | |
1169 | static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev) | |
1170 | { | |
1171 | int status = -ENOMEM; | |
1172 | struct ocrdma_mqe *cmd; | |
1173 | struct ocrdma_fw_ver_rsp *rsp; | |
1174 | ||
1175 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd)); | |
1176 | if (!cmd) | |
1177 | return -ENOMEM; | |
1178 | ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0], | |
1179 | OCRDMA_CMD_GET_FW_VER, | |
1180 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
1181 | ||
1182 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1183 | if (status) | |
1184 | goto mbx_err; | |
1185 | rsp = (struct ocrdma_fw_ver_rsp *)cmd; | |
1186 | memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver)); | |
1187 | memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0], | |
1188 | sizeof(rsp->running_ver)); | |
1189 | ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver)); | |
1190 | mbx_err: | |
1191 | kfree(cmd); | |
1192 | return status; | |
1193 | } | |
1194 | ||
1195 | /* can be issued only during init time. */ | |
1196 | static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev) | |
1197 | { | |
1198 | int status = -ENOMEM; | |
1199 | struct ocrdma_mqe *cmd; | |
1200 | struct ocrdma_fw_conf_rsp *rsp; | |
1201 | ||
1202 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd)); | |
1203 | if (!cmd) | |
1204 | return -ENOMEM; | |
1205 | ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0], | |
1206 | OCRDMA_CMD_GET_FW_CONFIG, | |
1207 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
1208 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1209 | if (status) | |
1210 | goto mbx_err; | |
1211 | rsp = (struct ocrdma_fw_conf_rsp *)cmd; | |
1212 | status = ocrdma_check_fw_config(dev, rsp); | |
1213 | mbx_err: | |
1214 | kfree(cmd); | |
1215 | return status; | |
1216 | } | |
1217 | ||
a51f06e1 SX |
1218 | int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset) |
1219 | { | |
1220 | struct ocrdma_rdma_stats_req *req = dev->stats_mem.va; | |
1221 | struct ocrdma_mqe *mqe = &dev->stats_mem.mqe; | |
beb9b703 | 1222 | struct ocrdma_rdma_stats_resp *old_stats; |
a51f06e1 SX |
1223 | int status; |
1224 | ||
beb9b703 | 1225 | old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL); |
a51f06e1 SX |
1226 | if (old_stats == NULL) |
1227 | return -ENOMEM; | |
1228 | ||
1229 | memset(mqe, 0, sizeof(*mqe)); | |
1230 | mqe->hdr.pyld_len = dev->stats_mem.size; | |
1231 | mqe->hdr.spcl_sge_cnt_emb |= | |
1232 | (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) & | |
1233 | OCRDMA_MQE_HDR_SGE_CNT_MASK; | |
1234 | mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff); | |
1235 | mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa); | |
1236 | mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size; | |
1237 | ||
1238 | /* Cache the old stats */ | |
1239 | memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp)); | |
1240 | memset(req, 0, dev->stats_mem.size); | |
1241 | ||
1242 | ocrdma_init_mch((struct ocrdma_mbx_hdr *)req, | |
1243 | OCRDMA_CMD_GET_RDMA_STATS, | |
1244 | OCRDMA_SUBSYS_ROCE, | |
1245 | dev->stats_mem.size); | |
1246 | if (reset) | |
1247 | req->reset_stats = reset; | |
1248 | ||
1249 | status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va); | |
1250 | if (status) | |
1251 | /* Copy from cache, if mbox fails */ | |
1252 | memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp)); | |
1253 | else | |
1254 | ocrdma_le32_to_cpu(req, dev->stats_mem.size); | |
1255 | ||
1256 | kfree(old_stats); | |
1257 | return status; | |
1258 | } | |
1259 | ||
1260 | static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev) | |
1261 | { | |
1262 | int status = -ENOMEM; | |
1263 | struct ocrdma_dma_mem dma; | |
1264 | struct ocrdma_mqe *mqe; | |
1265 | struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp; | |
1266 | struct mgmt_hba_attribs *hba_attribs; | |
1267 | ||
beb9b703 | 1268 | mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL); |
a51f06e1 SX |
1269 | if (!mqe) |
1270 | return status; | |
a51f06e1 SX |
1271 | |
1272 | dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp); | |
1273 | dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev, | |
1274 | dma.size, &dma.pa, GFP_KERNEL); | |
1275 | if (!dma.va) | |
1276 | goto free_mqe; | |
1277 | ||
1278 | mqe->hdr.pyld_len = dma.size; | |
1279 | mqe->hdr.spcl_sge_cnt_emb |= | |
1280 | (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) & | |
1281 | OCRDMA_MQE_HDR_SGE_CNT_MASK; | |
1282 | mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff); | |
1283 | mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa); | |
1284 | mqe->u.nonemb_req.sge[0].len = dma.size; | |
1285 | ||
1286 | memset(dma.va, 0, dma.size); | |
1287 | ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va, | |
1288 | OCRDMA_CMD_GET_CTRL_ATTRIBUTES, | |
1289 | OCRDMA_SUBSYS_COMMON, | |
1290 | dma.size); | |
1291 | ||
1292 | status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va); | |
1293 | if (!status) { | |
1294 | ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va; | |
1295 | hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs; | |
1296 | ||
8ac0c7c7 DS |
1297 | dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv & |
1298 | OCRDMA_HBA_ATTRB_PTNUM_MASK) | |
1299 | >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT; | |
a51f06e1 SX |
1300 | strncpy(dev->model_number, |
1301 | hba_attribs->controller_model_number, 31); | |
1302 | } | |
1303 | dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa); | |
1304 | free_mqe: | |
1305 | kfree(mqe); | |
1306 | return status; | |
1307 | } | |
1308 | ||
fe2caefc PP |
1309 | static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev) |
1310 | { | |
1311 | int status = -ENOMEM; | |
1312 | struct ocrdma_mbx_query_config *rsp; | |
1313 | struct ocrdma_mqe *cmd; | |
1314 | ||
1315 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd)); | |
1316 | if (!cmd) | |
1317 | return status; | |
1318 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1319 | if (status) | |
1320 | goto mbx_err; | |
1321 | rsp = (struct ocrdma_mbx_query_config *)cmd; | |
1322 | ocrdma_get_attr(dev, &dev->attr, rsp); | |
1323 | mbx_err: | |
1324 | kfree(cmd); | |
1325 | return status; | |
1326 | } | |
1327 | ||
f24ceba6 NG |
1328 | int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed) |
1329 | { | |
1330 | int status = -ENOMEM; | |
1331 | struct ocrdma_get_link_speed_rsp *rsp; | |
1332 | struct ocrdma_mqe *cmd; | |
1333 | ||
1334 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1, | |
1335 | sizeof(*cmd)); | |
1336 | if (!cmd) | |
1337 | return status; | |
1338 | ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0], | |
1339 | OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1, | |
1340 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
1341 | ||
1342 | ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1; | |
1343 | ||
1344 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1345 | if (status) | |
1346 | goto mbx_err; | |
1347 | ||
1348 | rsp = (struct ocrdma_get_link_speed_rsp *)cmd; | |
8ac0c7c7 DS |
1349 | *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK) |
1350 | >> OCRDMA_PHY_PS_SHIFT; | |
f24ceba6 NG |
1351 | |
1352 | mbx_err: | |
1353 | kfree(cmd); | |
1354 | return status; | |
1355 | } | |
1356 | ||
a51f06e1 SX |
1357 | static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev) |
1358 | { | |
1359 | int status = -ENOMEM; | |
1360 | struct ocrdma_mqe *cmd; | |
1361 | struct ocrdma_get_phy_info_rsp *rsp; | |
1362 | ||
1363 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd)); | |
1364 | if (!cmd) | |
1365 | return status; | |
1366 | ||
1367 | ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0], | |
1368 | OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON, | |
1369 | sizeof(*cmd)); | |
1370 | ||
1371 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1372 | if (status) | |
1373 | goto mbx_err; | |
1374 | ||
1375 | rsp = (struct ocrdma_get_phy_info_rsp *)cmd; | |
8ac0c7c7 DS |
1376 | dev->phy.phy_type = |
1377 | (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK); | |
1378 | dev->phy.interface_type = | |
1379 | (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK) | |
1380 | >> OCRDMA_IF_TYPE_SHIFT; | |
a51f06e1 | 1381 | dev->phy.auto_speeds_supported = |
8ac0c7c7 | 1382 | (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK); |
a51f06e1 | 1383 | dev->phy.fixed_speeds_supported = |
8ac0c7c7 DS |
1384 | (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK) |
1385 | >> OCRDMA_FSPEED_SUPP_SHIFT; | |
a51f06e1 SX |
1386 | mbx_err: |
1387 | kfree(cmd); | |
1388 | return status; | |
1389 | } | |
1390 | ||
fe2caefc PP |
1391 | int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd) |
1392 | { | |
1393 | int status = -ENOMEM; | |
1394 | struct ocrdma_alloc_pd *cmd; | |
1395 | struct ocrdma_alloc_pd_rsp *rsp; | |
1396 | ||
1397 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd)); | |
1398 | if (!cmd) | |
1399 | return status; | |
1400 | if (pd->dpp_enabled) | |
1401 | cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP; | |
1402 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1403 | if (status) | |
1404 | goto mbx_err; | |
1405 | rsp = (struct ocrdma_alloc_pd_rsp *)cmd; | |
1406 | pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK; | |
1407 | if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) { | |
1408 | pd->dpp_enabled = true; | |
1409 | pd->dpp_page = rsp->dpp_page_pdid >> | |
1410 | OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT; | |
1411 | } else { | |
1412 | pd->dpp_enabled = false; | |
1413 | pd->num_dpp_qp = 0; | |
1414 | } | |
1415 | mbx_err: | |
1416 | kfree(cmd); | |
1417 | return status; | |
1418 | } | |
1419 | ||
1420 | int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd) | |
1421 | { | |
1422 | int status = -ENOMEM; | |
1423 | struct ocrdma_dealloc_pd *cmd; | |
1424 | ||
1425 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd)); | |
1426 | if (!cmd) | |
1427 | return status; | |
1428 | cmd->id = pd->id; | |
1429 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1430 | kfree(cmd); | |
1431 | return status; | |
1432 | } | |
1433 | ||
9ba1377d MA |
1434 | |
1435 | static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev) | |
1436 | { | |
1437 | int status = -ENOMEM; | |
1438 | size_t pd_bitmap_size; | |
1439 | struct ocrdma_alloc_pd_range *cmd; | |
1440 | struct ocrdma_alloc_pd_range_rsp *rsp; | |
1441 | ||
1442 | /* Pre allocate the DPP PDs */ | |
1443 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd)); | |
1444 | if (!cmd) | |
1445 | return -ENOMEM; | |
1446 | cmd->pd_count = dev->attr.max_dpp_pds; | |
1447 | cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP; | |
1448 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1449 | if (status) | |
1450 | goto mbx_err; | |
1451 | rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd; | |
1452 | ||
1453 | if ((rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) && rsp->pd_count) { | |
1454 | dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >> | |
1455 | OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT; | |
1456 | dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid & | |
1457 | OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK; | |
1458 | dev->pd_mgr->max_dpp_pd = rsp->pd_count; | |
1459 | pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long); | |
1460 | dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size, | |
1461 | GFP_KERNEL); | |
1462 | } | |
1463 | kfree(cmd); | |
1464 | ||
1465 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd)); | |
1466 | if (!cmd) | |
1467 | return -ENOMEM; | |
1468 | ||
1469 | cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds; | |
1470 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1471 | if (status) | |
1472 | goto mbx_err; | |
1473 | rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd; | |
1474 | if (rsp->pd_count) { | |
1475 | dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid & | |
1476 | OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK; | |
1477 | dev->pd_mgr->max_normal_pd = rsp->pd_count; | |
1478 | pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long); | |
1479 | dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size, | |
1480 | GFP_KERNEL); | |
1481 | } | |
1482 | ||
1483 | if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) { | |
1484 | /* Enable PD resource manager */ | |
1485 | dev->pd_mgr->pd_prealloc_valid = true; | |
1486 | } else { | |
1487 | return -ENOMEM; | |
1488 | } | |
1489 | mbx_err: | |
1490 | kfree(cmd); | |
1491 | return status; | |
1492 | } | |
1493 | ||
1494 | static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev) | |
1495 | { | |
1496 | struct ocrdma_dealloc_pd_range *cmd; | |
1497 | ||
1498 | /* return normal PDs to firmware */ | |
1499 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd)); | |
1500 | if (!cmd) | |
1501 | goto mbx_err; | |
1502 | ||
1503 | if (dev->pd_mgr->max_normal_pd) { | |
1504 | cmd->start_pd_id = dev->pd_mgr->pd_norm_start; | |
1505 | cmd->pd_count = dev->pd_mgr->max_normal_pd; | |
1506 | ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1507 | } | |
1508 | ||
1509 | if (dev->pd_mgr->max_dpp_pd) { | |
1510 | kfree(cmd); | |
1511 | /* return DPP PDs to firmware */ | |
1512 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, | |
1513 | sizeof(*cmd)); | |
1514 | if (!cmd) | |
1515 | goto mbx_err; | |
1516 | ||
1517 | cmd->start_pd_id = dev->pd_mgr->pd_dpp_start; | |
1518 | cmd->pd_count = dev->pd_mgr->max_dpp_pd; | |
1519 | ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1520 | } | |
1521 | mbx_err: | |
1522 | kfree(cmd); | |
1523 | } | |
1524 | ||
1525 | void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev) | |
1526 | { | |
1527 | int status; | |
1528 | ||
1529 | dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr), | |
1530 | GFP_KERNEL); | |
1531 | if (!dev->pd_mgr) { | |
1532 | pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id); | |
1533 | return; | |
1534 | } | |
1535 | status = ocrdma_mbx_alloc_pd_range(dev); | |
1536 | if (status) { | |
1537 | pr_err("%s(%d) Unable to initialize PD pool, using default.\n", | |
1538 | __func__, dev->id); | |
1539 | } | |
1540 | } | |
1541 | ||
1542 | static void ocrdma_free_pd_pool(struct ocrdma_dev *dev) | |
1543 | { | |
1544 | ocrdma_mbx_dealloc_pd_range(dev); | |
1545 | kfree(dev->pd_mgr->pd_norm_bitmap); | |
1546 | kfree(dev->pd_mgr->pd_dpp_bitmap); | |
1547 | kfree(dev->pd_mgr); | |
1548 | } | |
1549 | ||
fe2caefc PP |
1550 | static int ocrdma_build_q_conf(u32 *num_entries, int entry_size, |
1551 | int *num_pages, int *page_size) | |
1552 | { | |
1553 | int i; | |
1554 | int mem_size; | |
1555 | ||
1556 | *num_entries = roundup_pow_of_two(*num_entries); | |
1557 | mem_size = *num_entries * entry_size; | |
1558 | /* find the possible lowest possible multiplier */ | |
1559 | for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) { | |
1560 | if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i)) | |
1561 | break; | |
1562 | } | |
1563 | if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT) | |
1564 | return -EINVAL; | |
1565 | mem_size = roundup(mem_size, | |
1566 | ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES)); | |
1567 | *num_pages = | |
1568 | mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES); | |
1569 | *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES); | |
1570 | *num_entries = mem_size / entry_size; | |
1571 | return 0; | |
1572 | } | |
1573 | ||
1574 | static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev) | |
1575 | { | |
fad51b7d | 1576 | int i; |
fe2caefc PP |
1577 | int status = 0; |
1578 | int max_ah; | |
1579 | struct ocrdma_create_ah_tbl *cmd; | |
1580 | struct ocrdma_create_ah_tbl_rsp *rsp; | |
1581 | struct pci_dev *pdev = dev->nic_info.pdev; | |
1582 | dma_addr_t pa; | |
1583 | struct ocrdma_pbe *pbes; | |
1584 | ||
1585 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd)); | |
1586 | if (!cmd) | |
1587 | return status; | |
1588 | ||
1589 | max_ah = OCRDMA_MAX_AH; | |
1590 | dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah; | |
1591 | ||
1592 | /* number of PBEs in PBL */ | |
1593 | cmd->ah_conf = (OCRDMA_AH_TBL_PAGES << | |
1594 | OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) & | |
1595 | OCRDMA_CREATE_AH_NUM_PAGES_MASK; | |
1596 | ||
1597 | /* page size */ | |
1598 | for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) { | |
1599 | if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i)) | |
1600 | break; | |
1601 | } | |
1602 | cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) & | |
1603 | OCRDMA_CREATE_AH_PAGE_SIZE_MASK; | |
1604 | ||
1605 | /* ah_entry size */ | |
1606 | cmd->ah_conf |= (sizeof(struct ocrdma_av) << | |
1607 | OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) & | |
1608 | OCRDMA_CREATE_AH_ENTRY_SIZE_MASK; | |
1609 | ||
1610 | dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, | |
1611 | &dev->av_tbl.pbl.pa, | |
1612 | GFP_KERNEL); | |
1613 | if (dev->av_tbl.pbl.va == NULL) | |
1614 | goto mem_err; | |
1615 | ||
1616 | dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size, | |
1617 | &pa, GFP_KERNEL); | |
1618 | if (dev->av_tbl.va == NULL) | |
1619 | goto mem_err_ah; | |
1620 | dev->av_tbl.pa = pa; | |
1621 | dev->av_tbl.num_ah = max_ah; | |
1622 | memset(dev->av_tbl.va, 0, dev->av_tbl.size); | |
1623 | ||
1624 | pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va; | |
1625 | for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) { | |
8ac0c7c7 DS |
1626 | pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff); |
1627 | pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa)); | |
fe2caefc PP |
1628 | pa += PAGE_SIZE; |
1629 | } | |
1630 | cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF); | |
1631 | cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa); | |
1632 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1633 | if (status) | |
1634 | goto mbx_err; | |
1635 | rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd; | |
1636 | dev->av_tbl.ahid = rsp->ahid & 0xFFFF; | |
1637 | kfree(cmd); | |
1638 | return 0; | |
1639 | ||
1640 | mbx_err: | |
1641 | dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va, | |
1642 | dev->av_tbl.pa); | |
1643 | dev->av_tbl.va = NULL; | |
1644 | mem_err_ah: | |
1645 | dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va, | |
1646 | dev->av_tbl.pbl.pa); | |
1647 | dev->av_tbl.pbl.va = NULL; | |
1648 | dev->av_tbl.size = 0; | |
1649 | mem_err: | |
1650 | kfree(cmd); | |
1651 | return status; | |
1652 | } | |
1653 | ||
1654 | static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev) | |
1655 | { | |
1656 | struct ocrdma_delete_ah_tbl *cmd; | |
1657 | struct pci_dev *pdev = dev->nic_info.pdev; | |
1658 | ||
1659 | if (dev->av_tbl.va == NULL) | |
1660 | return; | |
1661 | ||
1662 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd)); | |
1663 | if (!cmd) | |
1664 | return; | |
1665 | cmd->ahid = dev->av_tbl.ahid; | |
1666 | ||
1667 | ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1668 | dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va, | |
1669 | dev->av_tbl.pa); | |
daac9681 | 1670 | dev->av_tbl.va = NULL; |
fe2caefc PP |
1671 | dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va, |
1672 | dev->av_tbl.pbl.pa); | |
1673 | kfree(cmd); | |
1674 | } | |
1675 | ||
1676 | /* Multiple CQs uses the EQ. This routine returns least used | |
1677 | * EQ to associate with CQ. This will distributes the interrupt | |
1678 | * processing and CPU load to associated EQ, vector and so to that CPU. | |
1679 | */ | |
1680 | static u16 ocrdma_bind_eq(struct ocrdma_dev *dev) | |
1681 | { | |
1682 | int i, selected_eq = 0, cq_cnt = 0; | |
1683 | u16 eq_id; | |
1684 | ||
1685 | mutex_lock(&dev->dev_lock); | |
c88bd03f NG |
1686 | cq_cnt = dev->eq_tbl[0].cq_cnt; |
1687 | eq_id = dev->eq_tbl[0].q.id; | |
fe2caefc PP |
1688 | /* find the EQ which is has the least number of |
1689 | * CQs associated with it. | |
1690 | */ | |
1691 | for (i = 0; i < dev->eq_cnt; i++) { | |
c88bd03f NG |
1692 | if (dev->eq_tbl[i].cq_cnt < cq_cnt) { |
1693 | cq_cnt = dev->eq_tbl[i].cq_cnt; | |
1694 | eq_id = dev->eq_tbl[i].q.id; | |
fe2caefc PP |
1695 | selected_eq = i; |
1696 | } | |
1697 | } | |
c88bd03f | 1698 | dev->eq_tbl[selected_eq].cq_cnt += 1; |
fe2caefc PP |
1699 | mutex_unlock(&dev->dev_lock); |
1700 | return eq_id; | |
1701 | } | |
1702 | ||
1703 | static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id) | |
1704 | { | |
1705 | int i; | |
1706 | ||
1707 | mutex_lock(&dev->dev_lock); | |
ea617626 DS |
1708 | i = ocrdma_get_eq_table_index(dev, eq_id); |
1709 | if (i == -EINVAL) | |
1710 | BUG(); | |
1711 | dev->eq_tbl[i].cq_cnt -= 1; | |
fe2caefc PP |
1712 | mutex_unlock(&dev->dev_lock); |
1713 | } | |
1714 | ||
1715 | int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq, | |
cffce990 | 1716 | int entries, int dpp_cq, u16 pd_id) |
fe2caefc PP |
1717 | { |
1718 | int status = -ENOMEM; int max_hw_cqe; | |
1719 | struct pci_dev *pdev = dev->nic_info.pdev; | |
1720 | struct ocrdma_create_cq *cmd; | |
1721 | struct ocrdma_create_cq_rsp *rsp; | |
1722 | u32 hw_pages, cqe_size, page_size, cqe_count; | |
1723 | ||
fe2caefc | 1724 | if (entries > dev->attr.max_cqe) { |
ef99c4c2 NG |
1725 | pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n", |
1726 | __func__, dev->id, dev->attr.max_cqe, entries); | |
fe2caefc PP |
1727 | return -EINVAL; |
1728 | } | |
21c3391a | 1729 | if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R)) |
fe2caefc PP |
1730 | return -EINVAL; |
1731 | ||
1732 | if (dpp_cq) { | |
1733 | cq->max_hw_cqe = 1; | |
1734 | max_hw_cqe = 1; | |
1735 | cqe_size = OCRDMA_DPP_CQE_SIZE; | |
1736 | hw_pages = 1; | |
1737 | } else { | |
1738 | cq->max_hw_cqe = dev->attr.max_cqe; | |
1739 | max_hw_cqe = dev->attr.max_cqe; | |
1740 | cqe_size = sizeof(struct ocrdma_cqe); | |
1741 | hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES; | |
1742 | } | |
1743 | ||
1744 | cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE); | |
1745 | ||
1746 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd)); | |
1747 | if (!cmd) | |
1748 | return -ENOMEM; | |
1749 | ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ, | |
1750 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
1751 | cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL); | |
1752 | if (!cq->va) { | |
1753 | status = -ENOMEM; | |
1754 | goto mem_err; | |
1755 | } | |
1756 | memset(cq->va, 0, cq->len); | |
1757 | page_size = cq->len / hw_pages; | |
1758 | cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) << | |
1759 | OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT; | |
1760 | cmd->cmd.pgsz_pgcnt |= hw_pages; | |
1761 | cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS; | |
1762 | ||
fe2caefc | 1763 | cq->eqn = ocrdma_bind_eq(dev); |
cffce990 | 1764 | cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3; |
fe2caefc | 1765 | cqe_count = cq->len / cqe_size; |
ea617626 | 1766 | cq->cqe_cnt = cqe_count; |
f99b1649 | 1767 | if (cqe_count > 1024) { |
fe2caefc PP |
1768 | /* Set cnt to 3 to indicate more than 1024 cq entries */ |
1769 | cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT); | |
f99b1649 | 1770 | } else { |
fe2caefc PP |
1771 | u8 count = 0; |
1772 | switch (cqe_count) { | |
1773 | case 256: | |
1774 | count = 0; | |
1775 | break; | |
1776 | case 512: | |
1777 | count = 1; | |
1778 | break; | |
1779 | case 1024: | |
1780 | count = 2; | |
1781 | break; | |
1782 | default: | |
1783 | goto mbx_err; | |
1784 | } | |
1785 | cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT); | |
1786 | } | |
1787 | /* shared eq between all the consumer cqs. */ | |
1788 | cmd->cmd.eqn = cq->eqn; | |
21c3391a | 1789 | if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) { |
fe2caefc PP |
1790 | if (dpp_cq) |
1791 | cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP << | |
1792 | OCRDMA_CREATE_CQ_TYPE_SHIFT; | |
1793 | cq->phase_change = false; | |
8ac0c7c7 | 1794 | cmd->cmd.pdid_cqecnt = (cq->len / cqe_size); |
fe2caefc | 1795 | } else { |
8ac0c7c7 | 1796 | cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1; |
fe2caefc PP |
1797 | cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID; |
1798 | cq->phase_change = true; | |
1799 | } | |
1800 | ||
8ac0c7c7 DS |
1801 | /* pd_id valid only for v3 */ |
1802 | cmd->cmd.pdid_cqecnt |= (pd_id << | |
1803 | OCRDMA_CREATE_CQ_CMD_PDID_SHIFT); | |
fe2caefc PP |
1804 | ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size); |
1805 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1806 | if (status) | |
1807 | goto mbx_err; | |
1808 | ||
1809 | rsp = (struct ocrdma_create_cq_rsp *)cmd; | |
1810 | cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK); | |
1811 | kfree(cmd); | |
1812 | return 0; | |
1813 | mbx_err: | |
1814 | ocrdma_unbind_eq(dev, cq->eqn); | |
fe2caefc PP |
1815 | dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa); |
1816 | mem_err: | |
1817 | kfree(cmd); | |
1818 | return status; | |
1819 | } | |
1820 | ||
1821 | int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq) | |
1822 | { | |
1823 | int status = -ENOMEM; | |
1824 | struct ocrdma_destroy_cq *cmd; | |
1825 | ||
1826 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd)); | |
1827 | if (!cmd) | |
1828 | return status; | |
1829 | ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ, | |
1830 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
1831 | ||
1832 | cmd->bypass_flush_qid |= | |
1833 | (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) & | |
1834 | OCRDMA_DESTROY_CQ_QID_MASK; | |
1835 | ||
fe2caefc | 1836 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); |
ea617626 | 1837 | ocrdma_unbind_eq(dev, cq->eqn); |
fe2caefc | 1838 | dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa); |
fe2caefc PP |
1839 | kfree(cmd); |
1840 | return status; | |
1841 | } | |
1842 | ||
1843 | int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr, | |
1844 | u32 pdid, int addr_check) | |
1845 | { | |
1846 | int status = -ENOMEM; | |
1847 | struct ocrdma_alloc_lkey *cmd; | |
1848 | struct ocrdma_alloc_lkey_rsp *rsp; | |
1849 | ||
1850 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd)); | |
1851 | if (!cmd) | |
1852 | return status; | |
1853 | cmd->pdid = pdid; | |
1854 | cmd->pbl_sz_flags |= addr_check; | |
1855 | cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT); | |
1856 | cmd->pbl_sz_flags |= | |
1857 | (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT); | |
1858 | cmd->pbl_sz_flags |= | |
1859 | (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT); | |
1860 | cmd->pbl_sz_flags |= | |
1861 | (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT); | |
1862 | cmd->pbl_sz_flags |= | |
1863 | (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT); | |
1864 | cmd->pbl_sz_flags |= | |
1865 | (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT); | |
1866 | ||
1867 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1868 | if (status) | |
1869 | goto mbx_err; | |
1870 | rsp = (struct ocrdma_alloc_lkey_rsp *)cmd; | |
1871 | hwmr->lkey = rsp->lrkey; | |
1872 | mbx_err: | |
1873 | kfree(cmd); | |
1874 | return status; | |
1875 | } | |
1876 | ||
1877 | int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey) | |
1878 | { | |
1879 | int status = -ENOMEM; | |
1880 | struct ocrdma_dealloc_lkey *cmd; | |
1881 | ||
1882 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd)); | |
1883 | if (!cmd) | |
1884 | return -ENOMEM; | |
1885 | cmd->lkey = lkey; | |
1886 | cmd->rsvd_frmr = fr_mr ? 1 : 0; | |
1887 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1888 | if (status) | |
1889 | goto mbx_err; | |
1890 | mbx_err: | |
1891 | kfree(cmd); | |
1892 | return status; | |
1893 | } | |
1894 | ||
1895 | static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr, | |
1896 | u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last) | |
1897 | { | |
1898 | int status = -ENOMEM; | |
1899 | int i; | |
1900 | struct ocrdma_reg_nsmr *cmd; | |
1901 | struct ocrdma_reg_nsmr_rsp *rsp; | |
1902 | ||
1903 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd)); | |
1904 | if (!cmd) | |
1905 | return -ENOMEM; | |
1906 | cmd->num_pbl_pdid = | |
1907 | pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT); | |
2b51a9b9 | 1908 | cmd->fr_mr = hwmr->fr_mr; |
fe2caefc PP |
1909 | |
1910 | cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr << | |
1911 | OCRDMA_REG_NSMR_REMOTE_WR_SHIFT); | |
1912 | cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd << | |
1913 | OCRDMA_REG_NSMR_REMOTE_RD_SHIFT); | |
1914 | cmd->flags_hpage_pbe_sz |= (hwmr->local_wr << | |
1915 | OCRDMA_REG_NSMR_LOCAL_WR_SHIFT); | |
1916 | cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic << | |
1917 | OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT); | |
1918 | cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind << | |
1919 | OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT); | |
1920 | cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT); | |
1921 | ||
1922 | cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE); | |
1923 | cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) << | |
1924 | OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT; | |
1925 | cmd->totlen_low = hwmr->len; | |
1926 | cmd->totlen_high = upper_32_bits(hwmr->len); | |
1927 | cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff); | |
1928 | cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo); | |
1929 | cmd->va_loaddr = (u32) hwmr->va; | |
1930 | cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va); | |
1931 | ||
1932 | for (i = 0; i < pbl_cnt; i++) { | |
1933 | cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff); | |
1934 | cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa); | |
1935 | } | |
1936 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1937 | if (status) | |
1938 | goto mbx_err; | |
1939 | rsp = (struct ocrdma_reg_nsmr_rsp *)cmd; | |
1940 | hwmr->lkey = rsp->lrkey; | |
1941 | mbx_err: | |
1942 | kfree(cmd); | |
1943 | return status; | |
1944 | } | |
1945 | ||
1946 | static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev, | |
1947 | struct ocrdma_hw_mr *hwmr, u32 pbl_cnt, | |
1948 | u32 pbl_offset, u32 last) | |
1949 | { | |
1950 | int status = -ENOMEM; | |
1951 | int i; | |
1952 | struct ocrdma_reg_nsmr_cont *cmd; | |
1953 | ||
1954 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd)); | |
1955 | if (!cmd) | |
1956 | return -ENOMEM; | |
1957 | cmd->lrkey = hwmr->lkey; | |
1958 | cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) | | |
1959 | (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK); | |
1960 | cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT; | |
1961 | ||
1962 | for (i = 0; i < pbl_cnt; i++) { | |
1963 | cmd->pbl[i].lo = | |
1964 | (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff); | |
1965 | cmd->pbl[i].hi = | |
1966 | upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa); | |
1967 | } | |
1968 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
1969 | if (status) | |
1970 | goto mbx_err; | |
1971 | mbx_err: | |
1972 | kfree(cmd); | |
1973 | return status; | |
1974 | } | |
1975 | ||
1976 | int ocrdma_reg_mr(struct ocrdma_dev *dev, | |
1977 | struct ocrdma_hw_mr *hwmr, u32 pdid, int acc) | |
1978 | { | |
1979 | int status; | |
1980 | u32 last = 0; | |
1981 | u32 cur_pbl_cnt, pbl_offset; | |
1982 | u32 pending_pbl_cnt = hwmr->num_pbls; | |
1983 | ||
1984 | pbl_offset = 0; | |
1985 | cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL); | |
1986 | if (cur_pbl_cnt == pending_pbl_cnt) | |
1987 | last = 1; | |
1988 | ||
1989 | status = ocrdma_mbx_reg_mr(dev, hwmr, pdid, | |
1990 | cur_pbl_cnt, hwmr->pbe_size, last); | |
1991 | if (status) { | |
ef99c4c2 | 1992 | pr_err("%s() status=%d\n", __func__, status); |
fe2caefc PP |
1993 | return status; |
1994 | } | |
1995 | /* if there is no more pbls to register then exit. */ | |
1996 | if (last) | |
1997 | return 0; | |
1998 | ||
1999 | while (!last) { | |
2000 | pbl_offset += cur_pbl_cnt; | |
2001 | pending_pbl_cnt -= cur_pbl_cnt; | |
2002 | cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL); | |
2003 | /* if we reach the end of the pbls, then need to set the last | |
2004 | * bit, indicating no more pbls to register for this memory key. | |
2005 | */ | |
2006 | if (cur_pbl_cnt == pending_pbl_cnt) | |
2007 | last = 1; | |
2008 | ||
2009 | status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt, | |
2010 | pbl_offset, last); | |
2011 | if (status) | |
2012 | break; | |
2013 | } | |
2014 | if (status) | |
ef99c4c2 | 2015 | pr_err("%s() err. status=%d\n", __func__, status); |
fe2caefc PP |
2016 | |
2017 | return status; | |
2018 | } | |
2019 | ||
2020 | bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp) | |
2021 | { | |
2022 | struct ocrdma_qp *tmp; | |
2023 | bool found = false; | |
2024 | list_for_each_entry(tmp, &cq->sq_head, sq_entry) { | |
2025 | if (qp == tmp) { | |
2026 | found = true; | |
2027 | break; | |
2028 | } | |
2029 | } | |
2030 | return found; | |
2031 | } | |
2032 | ||
2033 | bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp) | |
2034 | { | |
2035 | struct ocrdma_qp *tmp; | |
2036 | bool found = false; | |
2037 | list_for_each_entry(tmp, &cq->rq_head, rq_entry) { | |
2038 | if (qp == tmp) { | |
2039 | found = true; | |
2040 | break; | |
2041 | } | |
2042 | } | |
2043 | return found; | |
2044 | } | |
2045 | ||
2046 | void ocrdma_flush_qp(struct ocrdma_qp *qp) | |
2047 | { | |
2048 | bool found; | |
2049 | unsigned long flags; | |
d2b8f7b1 | 2050 | struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device); |
fe2caefc | 2051 | |
d2b8f7b1 | 2052 | spin_lock_irqsave(&dev->flush_q_lock, flags); |
fe2caefc PP |
2053 | found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp); |
2054 | if (!found) | |
2055 | list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head); | |
2056 | if (!qp->srq) { | |
2057 | found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp); | |
2058 | if (!found) | |
2059 | list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head); | |
2060 | } | |
d2b8f7b1 | 2061 | spin_unlock_irqrestore(&dev->flush_q_lock, flags); |
fe2caefc PP |
2062 | } |
2063 | ||
f11220ee NG |
2064 | static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp) |
2065 | { | |
2066 | qp->sq.head = 0; | |
2067 | qp->sq.tail = 0; | |
2068 | qp->rq.head = 0; | |
2069 | qp->rq.tail = 0; | |
2070 | } | |
2071 | ||
057729cb NG |
2072 | int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state, |
2073 | enum ib_qp_state *old_ib_state) | |
fe2caefc PP |
2074 | { |
2075 | unsigned long flags; | |
2076 | int status = 0; | |
2077 | enum ocrdma_qp_state new_state; | |
2078 | new_state = get_ocrdma_qp_state(new_ib_state); | |
2079 | ||
2080 | /* sync with wqe and rqe posting */ | |
2081 | spin_lock_irqsave(&qp->q_lock, flags); | |
2082 | ||
2083 | if (old_ib_state) | |
2084 | *old_ib_state = get_ibqp_state(qp->state); | |
2085 | if (new_state == qp->state) { | |
2086 | spin_unlock_irqrestore(&qp->q_lock, flags); | |
2087 | return 1; | |
2088 | } | |
2089 | ||
057729cb | 2090 | |
f11220ee NG |
2091 | if (new_state == OCRDMA_QPS_INIT) { |
2092 | ocrdma_init_hwq_ptr(qp); | |
2093 | ocrdma_del_flush_qp(qp); | |
2094 | } else if (new_state == OCRDMA_QPS_ERR) { | |
057729cb | 2095 | ocrdma_flush_qp(qp); |
f11220ee | 2096 | } |
057729cb NG |
2097 | |
2098 | qp->state = new_state; | |
fe2caefc PP |
2099 | |
2100 | spin_unlock_irqrestore(&qp->q_lock, flags); | |
2101 | return status; | |
2102 | } | |
2103 | ||
2104 | static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp) | |
2105 | { | |
2106 | u32 flags = 0; | |
2107 | if (qp->cap_flags & OCRDMA_QP_INB_RD) | |
2108 | flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK; | |
2109 | if (qp->cap_flags & OCRDMA_QP_INB_WR) | |
2110 | flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK; | |
2111 | if (qp->cap_flags & OCRDMA_QP_MW_BIND) | |
2112 | flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK; | |
2113 | if (qp->cap_flags & OCRDMA_QP_LKEY0) | |
2114 | flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK; | |
2115 | if (qp->cap_flags & OCRDMA_QP_FAST_REG) | |
2116 | flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK; | |
2117 | return flags; | |
2118 | } | |
2119 | ||
2120 | static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd, | |
2121 | struct ib_qp_init_attr *attrs, | |
2122 | struct ocrdma_qp *qp) | |
2123 | { | |
2124 | int status; | |
2125 | u32 len, hw_pages, hw_page_size; | |
2126 | dma_addr_t pa; | |
d2b8f7b1 MA |
2127 | struct ocrdma_pd *pd = qp->pd; |
2128 | struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device); | |
fe2caefc PP |
2129 | struct pci_dev *pdev = dev->nic_info.pdev; |
2130 | u32 max_wqe_allocated; | |
2131 | u32 max_sges = attrs->cap.max_send_sge; | |
2132 | ||
43a6b402 | 2133 | /* QP1 may exceed 127 */ |
6ebacdfc | 2134 | max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1, |
43a6b402 | 2135 | dev->attr.max_wqe); |
fe2caefc PP |
2136 | |
2137 | status = ocrdma_build_q_conf(&max_wqe_allocated, | |
2138 | dev->attr.wqe_size, &hw_pages, &hw_page_size); | |
2139 | if (status) { | |
ef99c4c2 NG |
2140 | pr_err("%s() req. max_send_wr=0x%x\n", __func__, |
2141 | max_wqe_allocated); | |
fe2caefc PP |
2142 | return -EINVAL; |
2143 | } | |
2144 | qp->sq.max_cnt = max_wqe_allocated; | |
2145 | len = (hw_pages * hw_page_size); | |
2146 | ||
2147 | qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL); | |
2148 | if (!qp->sq.va) | |
2149 | return -EINVAL; | |
2150 | memset(qp->sq.va, 0, len); | |
2151 | qp->sq.len = len; | |
2152 | qp->sq.pa = pa; | |
2153 | qp->sq.entry_size = dev->attr.wqe_size; | |
2154 | ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size); | |
2155 | ||
2156 | cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) | |
2157 | << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT); | |
2158 | cmd->num_wq_rq_pages |= (hw_pages << | |
2159 | OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) & | |
2160 | OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK; | |
2161 | cmd->max_sge_send_write |= (max_sges << | |
2162 | OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) & | |
2163 | OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK; | |
2164 | cmd->max_sge_send_write |= (max_sges << | |
2165 | OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) & | |
2166 | OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK; | |
2167 | cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) << | |
2168 | OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) & | |
2169 | OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK; | |
2170 | cmd->wqe_rqe_size |= (dev->attr.wqe_size << | |
2171 | OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) & | |
2172 | OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK; | |
2173 | return 0; | |
2174 | } | |
2175 | ||
2176 | static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd, | |
2177 | struct ib_qp_init_attr *attrs, | |
2178 | struct ocrdma_qp *qp) | |
2179 | { | |
2180 | int status; | |
2181 | u32 len, hw_pages, hw_page_size; | |
2182 | dma_addr_t pa = 0; | |
d2b8f7b1 MA |
2183 | struct ocrdma_pd *pd = qp->pd; |
2184 | struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device); | |
fe2caefc PP |
2185 | struct pci_dev *pdev = dev->nic_info.pdev; |
2186 | u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1; | |
2187 | ||
2188 | status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size, | |
2189 | &hw_pages, &hw_page_size); | |
2190 | if (status) { | |
ef99c4c2 NG |
2191 | pr_err("%s() req. max_recv_wr=0x%x\n", __func__, |
2192 | attrs->cap.max_recv_wr + 1); | |
fe2caefc PP |
2193 | return status; |
2194 | } | |
2195 | qp->rq.max_cnt = max_rqe_allocated; | |
2196 | len = (hw_pages * hw_page_size); | |
2197 | ||
2198 | qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL); | |
2199 | if (!qp->rq.va) | |
c94e15c5 | 2200 | return -ENOMEM; |
fe2caefc PP |
2201 | memset(qp->rq.va, 0, len); |
2202 | qp->rq.pa = pa; | |
2203 | qp->rq.len = len; | |
2204 | qp->rq.entry_size = dev->attr.rqe_size; | |
2205 | ||
2206 | ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size); | |
2207 | cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) << | |
2208 | OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT); | |
2209 | cmd->num_wq_rq_pages |= | |
2210 | (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) & | |
2211 | OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK; | |
2212 | cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge << | |
2213 | OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) & | |
2214 | OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK; | |
2215 | cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) << | |
2216 | OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) & | |
2217 | OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK; | |
2218 | cmd->wqe_rqe_size |= (dev->attr.rqe_size << | |
2219 | OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) & | |
2220 | OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK; | |
2221 | return 0; | |
2222 | } | |
2223 | ||
2224 | static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd, | |
2225 | struct ocrdma_pd *pd, | |
2226 | struct ocrdma_qp *qp, | |
2227 | u8 enable_dpp_cq, u16 dpp_cq_id) | |
2228 | { | |
2229 | pd->num_dpp_qp--; | |
2230 | qp->dpp_enabled = true; | |
2231 | cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK; | |
2232 | if (!enable_dpp_cq) | |
2233 | return; | |
2234 | cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK; | |
2235 | cmd->dpp_credits_cqid = dpp_cq_id; | |
2236 | cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT << | |
2237 | OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT; | |
2238 | } | |
2239 | ||
2240 | static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd, | |
2241 | struct ocrdma_qp *qp) | |
2242 | { | |
d2b8f7b1 MA |
2243 | struct ocrdma_pd *pd = qp->pd; |
2244 | struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device); | |
fe2caefc PP |
2245 | struct pci_dev *pdev = dev->nic_info.pdev; |
2246 | dma_addr_t pa = 0; | |
2247 | int ird_page_size = dev->attr.ird_page_size; | |
2248 | int ird_q_len = dev->attr.num_ird_pages * ird_page_size; | |
43a6b402 NG |
2249 | struct ocrdma_hdr_wqe *rqe; |
2250 | int i = 0; | |
fe2caefc PP |
2251 | |
2252 | if (dev->attr.ird == 0) | |
2253 | return 0; | |
2254 | ||
2255 | qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len, | |
2256 | &pa, GFP_KERNEL); | |
2257 | if (!qp->ird_q_va) | |
2258 | return -ENOMEM; | |
2259 | memset(qp->ird_q_va, 0, ird_q_len); | |
2260 | ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages, | |
2261 | pa, ird_page_size); | |
43a6b402 NG |
2262 | for (; i < ird_q_len / dev->attr.rqe_size; i++) { |
2263 | rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va + | |
2264 | (i * dev->attr.rqe_size)); | |
2265 | rqe->cw = 0; | |
2266 | rqe->cw |= 2; | |
2267 | rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT); | |
2268 | rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT); | |
2269 | rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT); | |
2270 | } | |
fe2caefc PP |
2271 | return 0; |
2272 | } | |
2273 | ||
2274 | static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp, | |
2275 | struct ocrdma_qp *qp, | |
2276 | struct ib_qp_init_attr *attrs, | |
2277 | u16 *dpp_offset, u16 *dpp_credit_lmt) | |
2278 | { | |
2279 | u32 max_wqe_allocated, max_rqe_allocated; | |
2280 | qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK; | |
2281 | qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK; | |
2282 | qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT; | |
2283 | qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK; | |
2284 | qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT); | |
2285 | qp->dpp_enabled = false; | |
2286 | if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) { | |
2287 | qp->dpp_enabled = true; | |
2288 | *dpp_credit_lmt = (rsp->dpp_response & | |
2289 | OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >> | |
2290 | OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT; | |
2291 | *dpp_offset = (rsp->dpp_response & | |
2292 | OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >> | |
2293 | OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT; | |
2294 | } | |
2295 | max_wqe_allocated = | |
2296 | rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT; | |
2297 | max_wqe_allocated = 1 << max_wqe_allocated; | |
2298 | max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe); | |
2299 | ||
fe2caefc PP |
2300 | qp->sq.max_cnt = max_wqe_allocated; |
2301 | qp->sq.max_wqe_idx = max_wqe_allocated - 1; | |
2302 | ||
2303 | if (!attrs->srq) { | |
2304 | qp->rq.max_cnt = max_rqe_allocated; | |
2305 | qp->rq.max_wqe_idx = max_rqe_allocated - 1; | |
fe2caefc PP |
2306 | } |
2307 | } | |
2308 | ||
2309 | int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs, | |
2310 | u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset, | |
2311 | u16 *dpp_credit_lmt) | |
2312 | { | |
2313 | int status = -ENOMEM; | |
2314 | u32 flags = 0; | |
fe2caefc | 2315 | struct ocrdma_pd *pd = qp->pd; |
d2b8f7b1 | 2316 | struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device); |
fe2caefc PP |
2317 | struct pci_dev *pdev = dev->nic_info.pdev; |
2318 | struct ocrdma_cq *cq; | |
2319 | struct ocrdma_create_qp_req *cmd; | |
2320 | struct ocrdma_create_qp_rsp *rsp; | |
2321 | int qptype; | |
2322 | ||
2323 | switch (attrs->qp_type) { | |
2324 | case IB_QPT_GSI: | |
2325 | qptype = OCRDMA_QPT_GSI; | |
2326 | break; | |
2327 | case IB_QPT_RC: | |
2328 | qptype = OCRDMA_QPT_RC; | |
2329 | break; | |
2330 | case IB_QPT_UD: | |
2331 | qptype = OCRDMA_QPT_UD; | |
2332 | break; | |
2333 | default: | |
2334 | return -EINVAL; | |
2b50176d | 2335 | } |
fe2caefc PP |
2336 | |
2337 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd)); | |
2338 | if (!cmd) | |
2339 | return status; | |
2340 | cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) & | |
2341 | OCRDMA_CREATE_QP_REQ_QPT_MASK; | |
2342 | status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp); | |
2343 | if (status) | |
2344 | goto sq_err; | |
2345 | ||
2346 | if (attrs->srq) { | |
2347 | struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq); | |
2348 | cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK; | |
2349 | cmd->rq_addr[0].lo = srq->id; | |
2350 | qp->srq = srq; | |
2351 | } else { | |
2352 | status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp); | |
2353 | if (status) | |
2354 | goto rq_err; | |
2355 | } | |
2356 | ||
2357 | status = ocrdma_set_create_qp_ird_cmd(cmd, qp); | |
2358 | if (status) | |
2359 | goto mbx_err; | |
2360 | ||
2361 | cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) & | |
2362 | OCRDMA_CREATE_QP_REQ_PD_ID_MASK; | |
2363 | ||
2364 | flags = ocrdma_set_create_qp_mbx_access_flags(qp); | |
2365 | ||
2366 | cmd->max_sge_recv_flags |= flags; | |
2367 | cmd->max_ord_ird |= (dev->attr.max_ord_per_qp << | |
2368 | OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) & | |
2369 | OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK; | |
2370 | cmd->max_ord_ird |= (dev->attr.max_ird_per_qp << | |
2371 | OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) & | |
2372 | OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK; | |
2373 | cq = get_ocrdma_cq(attrs->send_cq); | |
2374 | cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) & | |
2375 | OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK; | |
2376 | qp->sq_cq = cq; | |
2377 | cq = get_ocrdma_cq(attrs->recv_cq); | |
2378 | cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) & | |
2379 | OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK; | |
2380 | qp->rq_cq = cq; | |
2381 | ||
f50f31e4 DS |
2382 | if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp && |
2383 | (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) { | |
fe2caefc PP |
2384 | ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq, |
2385 | dpp_cq_id); | |
f99b1649 | 2386 | } |
fe2caefc PP |
2387 | |
2388 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
2389 | if (status) | |
2390 | goto mbx_err; | |
2391 | rsp = (struct ocrdma_create_qp_rsp *)cmd; | |
2392 | ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt); | |
2393 | qp->state = OCRDMA_QPS_RST; | |
2394 | kfree(cmd); | |
2395 | return 0; | |
2396 | mbx_err: | |
2397 | if (qp->rq.va) | |
2398 | dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa); | |
2399 | rq_err: | |
ef99c4c2 | 2400 | pr_err("%s(%d) rq_err\n", __func__, dev->id); |
fe2caefc PP |
2401 | dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa); |
2402 | sq_err: | |
ef99c4c2 | 2403 | pr_err("%s(%d) sq_err\n", __func__, dev->id); |
fe2caefc PP |
2404 | kfree(cmd); |
2405 | return status; | |
2406 | } | |
2407 | ||
2408 | int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp, | |
2409 | struct ocrdma_qp_params *param) | |
2410 | { | |
2411 | int status = -ENOMEM; | |
2412 | struct ocrdma_query_qp *cmd; | |
2413 | struct ocrdma_query_qp_rsp *rsp; | |
2414 | ||
2415 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd)); | |
2416 | if (!cmd) | |
2417 | return status; | |
2418 | cmd->qp_id = qp->id; | |
2419 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
2420 | if (status) | |
2421 | goto mbx_err; | |
2422 | rsp = (struct ocrdma_query_qp_rsp *)cmd; | |
2423 | memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params)); | |
2424 | mbx_err: | |
2425 | kfree(cmd); | |
2426 | return status; | |
2427 | } | |
2428 | ||
f99b1649 | 2429 | static int ocrdma_set_av_params(struct ocrdma_qp *qp, |
fe2caefc | 2430 | struct ocrdma_modify_qp *cmd, |
bf67472c SX |
2431 | struct ib_qp_attr *attrs, |
2432 | int attr_mask) | |
fe2caefc | 2433 | { |
f99b1649 | 2434 | int status; |
fe2caefc | 2435 | struct ib_ah_attr *ah_attr = &attrs->ah_attr; |
9c58726b | 2436 | union ib_gid sgid, zgid; |
fe2caefc PP |
2437 | u32 vlan_id; |
2438 | u8 mac_addr[6]; | |
d2b8f7b1 | 2439 | struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device); |
9c58726b | 2440 | |
fe2caefc | 2441 | if ((ah_attr->ah_flags & IB_AH_GRH) == 0) |
f99b1649 | 2442 | return -EINVAL; |
d2b8f7b1 MA |
2443 | if (atomic_cmpxchg(&dev->update_sl, 1, 0)) |
2444 | ocrdma_init_service_level(dev); | |
fe2caefc PP |
2445 | cmd->params.tclass_sq_psn |= |
2446 | (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT); | |
2447 | cmd->params.rnt_rc_sl_fl |= | |
2448 | (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK); | |
2b51a9b9 | 2449 | cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT); |
fe2caefc PP |
2450 | cmd->params.hop_lmt_rq_psn |= |
2451 | (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT); | |
2452 | cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID; | |
2453 | memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0], | |
2454 | sizeof(cmd->params.dgid)); | |
d2b8f7b1 | 2455 | status = ocrdma_query_gid(&dev->ibdev, 1, |
fad51b7d | 2456 | ah_attr->grh.sgid_index, &sgid); |
f99b1649 NG |
2457 | if (status) |
2458 | return status; | |
9c58726b NG |
2459 | |
2460 | memset(&zgid, 0, sizeof(zgid)); | |
2461 | if (!memcmp(&sgid, &zgid, sizeof(zgid))) | |
2462 | return -EINVAL; | |
2463 | ||
fe2caefc PP |
2464 | qp->sgid_idx = ah_attr->grh.sgid_index; |
2465 | memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid)); | |
d2b8f7b1 | 2466 | status = ocrdma_resolve_dmac(dev, ah_attr, &mac_addr[0]); |
a601dc77 DS |
2467 | if (status) |
2468 | return status; | |
fe2caefc PP |
2469 | cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) | |
2470 | (mac_addr[2] << 16) | (mac_addr[3] << 24); | |
2471 | /* convert them to LE format. */ | |
2472 | ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid)); | |
2473 | ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid)); | |
2474 | cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8); | |
bf67472c SX |
2475 | if (attr_mask & IB_QP_VID) { |
2476 | vlan_id = attrs->vlan_id; | |
fe2caefc PP |
2477 | cmd->params.vlan_dmac_b4_to_b5 |= |
2478 | vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT; | |
2479 | cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID; | |
31dbdd9a | 2480 | cmd->params.rnt_rc_sl_fl |= |
d2b8f7b1 | 2481 | (dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT; |
fe2caefc | 2482 | } |
f99b1649 | 2483 | return 0; |
fe2caefc PP |
2484 | } |
2485 | ||
2486 | static int ocrdma_set_qp_params(struct ocrdma_qp *qp, | |
2487 | struct ocrdma_modify_qp *cmd, | |
bc1b04ab | 2488 | struct ib_qp_attr *attrs, int attr_mask) |
fe2caefc PP |
2489 | { |
2490 | int status = 0; | |
d2b8f7b1 | 2491 | struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device); |
fe2caefc PP |
2492 | |
2493 | if (attr_mask & IB_QP_PKEY_INDEX) { | |
2494 | cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index & | |
2495 | OCRDMA_QP_PARAMS_PKEY_INDEX_MASK); | |
2496 | cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID; | |
2497 | } | |
2498 | if (attr_mask & IB_QP_QKEY) { | |
2499 | qp->qkey = attrs->qkey; | |
2500 | cmd->params.qkey = attrs->qkey; | |
2501 | cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID; | |
2502 | } | |
f99b1649 | 2503 | if (attr_mask & IB_QP_AV) { |
bf67472c | 2504 | status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask); |
f99b1649 NG |
2505 | if (status) |
2506 | return status; | |
2507 | } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) { | |
fe2caefc | 2508 | /* set the default mac address for UD, GSI QPs */ |
d2b8f7b1 MA |
2509 | cmd->params.dmac_b0_to_b3 = dev->nic_info.mac_addr[0] | |
2510 | (dev->nic_info.mac_addr[1] << 8) | | |
2511 | (dev->nic_info.mac_addr[2] << 16) | | |
2512 | (dev->nic_info.mac_addr[3] << 24); | |
2513 | cmd->params.vlan_dmac_b4_to_b5 = dev->nic_info.mac_addr[4] | | |
2514 | (dev->nic_info.mac_addr[5] << 8); | |
fe2caefc PP |
2515 | } |
2516 | if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) && | |
2517 | attrs->en_sqd_async_notify) { | |
2518 | cmd->params.max_sge_recv_flags |= | |
2519 | OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC; | |
2520 | cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID; | |
2521 | } | |
2522 | if (attr_mask & IB_QP_DEST_QPN) { | |
2523 | cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num & | |
2524 | OCRDMA_QP_PARAMS_DEST_QPN_MASK); | |
2525 | cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID; | |
2526 | } | |
2527 | if (attr_mask & IB_QP_PATH_MTU) { | |
d3cb6c0b NG |
2528 | if (attrs->path_mtu < IB_MTU_256 || |
2529 | attrs->path_mtu > IB_MTU_4096) { | |
fe2caefc PP |
2530 | status = -EINVAL; |
2531 | goto pmtu_err; | |
2532 | } | |
2533 | cmd->params.path_mtu_pkey_indx |= | |
2534 | (ib_mtu_enum_to_int(attrs->path_mtu) << | |
2535 | OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) & | |
2536 | OCRDMA_QP_PARAMS_PATH_MTU_MASK; | |
2537 | cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID; | |
2538 | } | |
2539 | if (attr_mask & IB_QP_TIMEOUT) { | |
2540 | cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout << | |
2541 | OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT; | |
2542 | cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID; | |
2543 | } | |
2544 | if (attr_mask & IB_QP_RETRY_CNT) { | |
2545 | cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt << | |
2546 | OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) & | |
2547 | OCRDMA_QP_PARAMS_RETRY_CNT_MASK; | |
2548 | cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID; | |
2549 | } | |
2550 | if (attr_mask & IB_QP_MIN_RNR_TIMER) { | |
2551 | cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer << | |
2552 | OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) & | |
2553 | OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK; | |
2554 | cmd->flags |= OCRDMA_QP_PARA_RNT_VALID; | |
2555 | } | |
2556 | if (attr_mask & IB_QP_RNR_RETRY) { | |
2557 | cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry << | |
2558 | OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT) | |
2559 | & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK; | |
2560 | cmd->flags |= OCRDMA_QP_PARA_RRC_VALID; | |
2561 | } | |
2562 | if (attr_mask & IB_QP_SQ_PSN) { | |
2563 | cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff); | |
2564 | cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID; | |
2565 | } | |
2566 | if (attr_mask & IB_QP_RQ_PSN) { | |
2567 | cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff); | |
2568 | cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID; | |
2569 | } | |
2570 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { | |
d2b8f7b1 | 2571 | if (attrs->max_rd_atomic > dev->attr.max_ord_per_qp) { |
fe2caefc PP |
2572 | status = -EINVAL; |
2573 | goto pmtu_err; | |
2574 | } | |
2575 | qp->max_ord = attrs->max_rd_atomic; | |
2576 | cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID; | |
2577 | } | |
2578 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { | |
d2b8f7b1 | 2579 | if (attrs->max_dest_rd_atomic > dev->attr.max_ird_per_qp) { |
fe2caefc PP |
2580 | status = -EINVAL; |
2581 | goto pmtu_err; | |
2582 | } | |
2583 | qp->max_ird = attrs->max_dest_rd_atomic; | |
2584 | cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID; | |
2585 | } | |
2586 | cmd->params.max_ord_ird = (qp->max_ord << | |
2587 | OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) | | |
2588 | (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK); | |
2589 | pmtu_err: | |
2590 | return status; | |
2591 | } | |
2592 | ||
2593 | int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp, | |
bc1b04ab | 2594 | struct ib_qp_attr *attrs, int attr_mask) |
fe2caefc PP |
2595 | { |
2596 | int status = -ENOMEM; | |
2597 | struct ocrdma_modify_qp *cmd; | |
fe2caefc PP |
2598 | |
2599 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd)); | |
2600 | if (!cmd) | |
2601 | return status; | |
2602 | ||
2603 | cmd->params.id = qp->id; | |
2604 | cmd->flags = 0; | |
2605 | if (attr_mask & IB_QP_STATE) { | |
2606 | cmd->params.max_sge_recv_flags |= | |
2607 | (get_ocrdma_qp_state(attrs->qp_state) << | |
2608 | OCRDMA_QP_PARAMS_STATE_SHIFT) & | |
2609 | OCRDMA_QP_PARAMS_STATE_MASK; | |
2610 | cmd->flags |= OCRDMA_QP_PARA_QPS_VALID; | |
f99b1649 | 2611 | } else { |
fe2caefc PP |
2612 | cmd->params.max_sge_recv_flags |= |
2613 | (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) & | |
2614 | OCRDMA_QP_PARAMS_STATE_MASK; | |
f99b1649 NG |
2615 | } |
2616 | ||
bc1b04ab | 2617 | status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask); |
fe2caefc PP |
2618 | if (status) |
2619 | goto mbx_err; | |
2620 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
2621 | if (status) | |
2622 | goto mbx_err; | |
c592c423 | 2623 | |
fe2caefc PP |
2624 | mbx_err: |
2625 | kfree(cmd); | |
2626 | return status; | |
2627 | } | |
2628 | ||
2629 | int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp) | |
2630 | { | |
2631 | int status = -ENOMEM; | |
2632 | struct ocrdma_destroy_qp *cmd; | |
fe2caefc PP |
2633 | struct pci_dev *pdev = dev->nic_info.pdev; |
2634 | ||
2635 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd)); | |
2636 | if (!cmd) | |
2637 | return status; | |
2638 | cmd->qp_id = qp->id; | |
2639 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
2640 | if (status) | |
2641 | goto mbx_err; | |
c592c423 | 2642 | |
fe2caefc PP |
2643 | mbx_err: |
2644 | kfree(cmd); | |
2645 | if (qp->sq.va) | |
2646 | dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa); | |
2647 | if (!qp->srq && qp->rq.va) | |
2648 | dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa); | |
2649 | if (qp->dpp_enabled) | |
2650 | qp->pd->num_dpp_qp++; | |
2651 | return status; | |
2652 | } | |
2653 | ||
1afc0454 | 2654 | int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq, |
fe2caefc PP |
2655 | struct ib_srq_init_attr *srq_attr, |
2656 | struct ocrdma_pd *pd) | |
2657 | { | |
2658 | int status = -ENOMEM; | |
2659 | int hw_pages, hw_page_size; | |
2660 | int len; | |
2661 | struct ocrdma_create_srq_rsp *rsp; | |
2662 | struct ocrdma_create_srq *cmd; | |
2663 | dma_addr_t pa; | |
fe2caefc PP |
2664 | struct pci_dev *pdev = dev->nic_info.pdev; |
2665 | u32 max_rqe_allocated; | |
2666 | ||
2667 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd)); | |
2668 | if (!cmd) | |
2669 | return status; | |
2670 | ||
2671 | cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK; | |
2672 | max_rqe_allocated = srq_attr->attr.max_wr + 1; | |
2673 | status = ocrdma_build_q_conf(&max_rqe_allocated, | |
2674 | dev->attr.rqe_size, | |
2675 | &hw_pages, &hw_page_size); | |
2676 | if (status) { | |
ef99c4c2 NG |
2677 | pr_err("%s() req. max_wr=0x%x\n", __func__, |
2678 | srq_attr->attr.max_wr); | |
fe2caefc PP |
2679 | status = -EINVAL; |
2680 | goto ret; | |
2681 | } | |
2682 | len = hw_pages * hw_page_size; | |
2683 | srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL); | |
2684 | if (!srq->rq.va) { | |
2685 | status = -ENOMEM; | |
2686 | goto ret; | |
2687 | } | |
2688 | ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size); | |
2689 | ||
2690 | srq->rq.entry_size = dev->attr.rqe_size; | |
2691 | srq->rq.pa = pa; | |
2692 | srq->rq.len = len; | |
2693 | srq->rq.max_cnt = max_rqe_allocated; | |
2694 | ||
2695 | cmd->max_sge_rqe = ilog2(max_rqe_allocated); | |
2696 | cmd->max_sge_rqe |= srq_attr->attr.max_sge << | |
2697 | OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT; | |
2698 | ||
2699 | cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) | |
2700 | << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT); | |
2701 | cmd->pages_rqe_sz |= (dev->attr.rqe_size | |
2702 | << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT) | |
2703 | & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK; | |
2704 | cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT; | |
2705 | ||
2706 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
2707 | if (status) | |
2708 | goto mbx_err; | |
2709 | rsp = (struct ocrdma_create_srq_rsp *)cmd; | |
2710 | srq->id = rsp->id; | |
2711 | srq->rq.dbid = rsp->id; | |
2712 | max_rqe_allocated = ((rsp->max_sge_rqe_allocated & | |
2713 | OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >> | |
2714 | OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT); | |
2715 | max_rqe_allocated = (1 << max_rqe_allocated); | |
2716 | srq->rq.max_cnt = max_rqe_allocated; | |
2717 | srq->rq.max_wqe_idx = max_rqe_allocated - 1; | |
2718 | srq->rq.max_sges = (rsp->max_sge_rqe_allocated & | |
2719 | OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >> | |
2720 | OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT; | |
2721 | goto ret; | |
2722 | mbx_err: | |
2723 | dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa); | |
2724 | ret: | |
2725 | kfree(cmd); | |
2726 | return status; | |
2727 | } | |
2728 | ||
2729 | int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr) | |
2730 | { | |
2731 | int status = -ENOMEM; | |
2732 | struct ocrdma_modify_srq *cmd; | |
f11220ee NG |
2733 | struct ocrdma_pd *pd = srq->pd; |
2734 | struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device); | |
1afc0454 | 2735 | |
d7e19c0a | 2736 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd)); |
fe2caefc PP |
2737 | if (!cmd) |
2738 | return status; | |
2739 | cmd->id = srq->id; | |
2740 | cmd->limit_max_rqe |= srq_attr->srq_limit << | |
2741 | OCRDMA_MODIFY_SRQ_LIMIT_SHIFT; | |
1afc0454 | 2742 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); |
fe2caefc PP |
2743 | kfree(cmd); |
2744 | return status; | |
2745 | } | |
2746 | ||
2747 | int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr) | |
2748 | { | |
2749 | int status = -ENOMEM; | |
2750 | struct ocrdma_query_srq *cmd; | |
1afc0454 NG |
2751 | struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device); |
2752 | ||
d7e19c0a | 2753 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd)); |
fe2caefc PP |
2754 | if (!cmd) |
2755 | return status; | |
2756 | cmd->id = srq->rq.dbid; | |
1afc0454 | 2757 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); |
fe2caefc PP |
2758 | if (status == 0) { |
2759 | struct ocrdma_query_srq_rsp *rsp = | |
2760 | (struct ocrdma_query_srq_rsp *)cmd; | |
2761 | srq_attr->max_sge = | |
2762 | rsp->srq_lmt_max_sge & | |
2763 | OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK; | |
2764 | srq_attr->max_wr = | |
2765 | rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT; | |
2766 | srq_attr->srq_limit = rsp->srq_lmt_max_sge >> | |
2767 | OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT; | |
2768 | } | |
2769 | kfree(cmd); | |
2770 | return status; | |
2771 | } | |
2772 | ||
2773 | int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq) | |
2774 | { | |
2775 | int status = -ENOMEM; | |
2776 | struct ocrdma_destroy_srq *cmd; | |
2777 | struct pci_dev *pdev = dev->nic_info.pdev; | |
2778 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd)); | |
2779 | if (!cmd) | |
2780 | return status; | |
2781 | cmd->id = srq->id; | |
1afc0454 | 2782 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); |
fe2caefc PP |
2783 | if (srq->rq.va) |
2784 | dma_free_coherent(&pdev->dev, srq->rq.len, | |
2785 | srq->rq.va, srq->rq.pa); | |
2786 | kfree(cmd); | |
2787 | return status; | |
2788 | } | |
2789 | ||
31dbdd9a SX |
2790 | static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype, |
2791 | struct ocrdma_dcbx_cfg *dcbxcfg) | |
2792 | { | |
2793 | int status = 0; | |
2794 | dma_addr_t pa; | |
2795 | struct ocrdma_mqe cmd; | |
2796 | ||
2797 | struct ocrdma_get_dcbx_cfg_req *req = NULL; | |
2798 | struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL; | |
2799 | struct pci_dev *pdev = dev->nic_info.pdev; | |
2800 | struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge; | |
2801 | ||
2802 | memset(&cmd, 0, sizeof(struct ocrdma_mqe)); | |
2803 | cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp), | |
2804 | sizeof(struct ocrdma_get_dcbx_cfg_req)); | |
2805 | req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL); | |
2806 | if (!req) { | |
2807 | status = -ENOMEM; | |
2808 | goto mem_err; | |
2809 | } | |
2810 | ||
2811 | cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) & | |
2812 | OCRDMA_MQE_HDR_SGE_CNT_MASK; | |
2813 | mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL); | |
2814 | mqe_sge->pa_hi = (u32) upper_32_bits(pa); | |
2815 | mqe_sge->len = cmd.hdr.pyld_len; | |
2816 | ||
2817 | memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req)); | |
2818 | ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG, | |
2819 | OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len); | |
2820 | req->param_type = ptype; | |
2821 | ||
2822 | status = ocrdma_mbx_cmd(dev, &cmd); | |
2823 | if (status) | |
2824 | goto mbx_err; | |
2825 | ||
2826 | rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req; | |
2827 | ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp)); | |
2828 | memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg)); | |
2829 | ||
2830 | mbx_err: | |
2831 | dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa); | |
2832 | mem_err: | |
2833 | return status; | |
2834 | } | |
2835 | ||
2836 | #define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08 | |
2837 | #define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05 | |
2838 | ||
2839 | static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype, | |
2840 | struct ocrdma_dcbx_cfg *dcbxcfg, | |
2841 | u8 *srvc_lvl) | |
2842 | { | |
2843 | int status = -EINVAL, indx, slindx; | |
2844 | int ventry_cnt; | |
2845 | struct ocrdma_app_parameter *app_param; | |
2846 | u8 valid, proto_sel; | |
2847 | u8 app_prio, pfc_prio; | |
2848 | u16 proto; | |
2849 | ||
2850 | if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) { | |
2851 | pr_info("%s ocrdma%d DCBX is disabled\n", | |
2852 | dev_name(&dev->nic_info.pdev->dev), dev->id); | |
2853 | goto out; | |
2854 | } | |
2855 | ||
2856 | if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) { | |
2857 | pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n", | |
2858 | dev_name(&dev->nic_info.pdev->dev), dev->id, | |
2859 | (ptype > 0 ? "operational" : "admin"), | |
2860 | (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ? | |
2861 | "enabled" : "disabled", | |
2862 | (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ? | |
2863 | "" : ", not sync'ed"); | |
2864 | goto out; | |
2865 | } else { | |
2866 | pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n", | |
2867 | dev_name(&dev->nic_info.pdev->dev), dev->id); | |
2868 | } | |
2869 | ||
2870 | ventry_cnt = (dcbxcfg->tcv_aev_opv_st >> | |
2871 | OCRDMA_DCBX_APP_ENTRY_SHIFT) | |
2872 | & OCRDMA_DCBX_STATE_MASK; | |
2873 | ||
2874 | for (indx = 0; indx < ventry_cnt; indx++) { | |
2875 | app_param = &dcbxcfg->app_param[indx]; | |
2876 | valid = (app_param->valid_proto_app >> | |
2877 | OCRDMA_APP_PARAM_VALID_SHIFT) | |
2878 | & OCRDMA_APP_PARAM_VALID_MASK; | |
2879 | proto_sel = (app_param->valid_proto_app | |
2880 | >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT) | |
2881 | & OCRDMA_APP_PARAM_PROTO_SEL_MASK; | |
2882 | proto = app_param->valid_proto_app & | |
2883 | OCRDMA_APP_PARAM_APP_PROTO_MASK; | |
2884 | ||
2885 | if ( | |
2886 | valid && proto == OCRDMA_APP_PROTO_ROCE && | |
2887 | proto_sel == OCRDMA_PROTO_SELECT_L2) { | |
2888 | for (slindx = 0; slindx < | |
2889 | OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) { | |
2890 | app_prio = ocrdma_get_app_prio( | |
2891 | (u8 *)app_param->app_prio, | |
2892 | slindx); | |
2893 | pfc_prio = ocrdma_get_pfc_prio( | |
2894 | (u8 *)dcbxcfg->pfc_prio, | |
2895 | slindx); | |
2896 | ||
2897 | if (app_prio && pfc_prio) { | |
2898 | *srvc_lvl = slindx; | |
2899 | status = 0; | |
2900 | goto out; | |
2901 | } | |
2902 | } | |
2903 | if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) { | |
2904 | pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n", | |
2905 | dev_name(&dev->nic_info.pdev->dev), | |
2906 | dev->id, proto); | |
2907 | } | |
2908 | } | |
2909 | } | |
2910 | ||
2911 | out: | |
2912 | return status; | |
2913 | } | |
2914 | ||
2915 | void ocrdma_init_service_level(struct ocrdma_dev *dev) | |
2916 | { | |
2917 | int status = 0, indx; | |
2918 | struct ocrdma_dcbx_cfg dcbxcfg; | |
2919 | u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL; | |
2920 | int ptype = OCRDMA_PARAMETER_TYPE_OPER; | |
2921 | ||
2922 | for (indx = 0; indx < 2; indx++) { | |
2923 | status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg); | |
2924 | if (status) { | |
2925 | pr_err("%s(): status=%d\n", __func__, status); | |
2926 | ptype = OCRDMA_PARAMETER_TYPE_ADMIN; | |
2927 | continue; | |
2928 | } | |
2929 | ||
2930 | status = ocrdma_parse_dcbxcfg_rsp(dev, ptype, | |
2931 | &dcbxcfg, &srvc_lvl); | |
2932 | if (status) { | |
2933 | ptype = OCRDMA_PARAMETER_TYPE_ADMIN; | |
2934 | continue; | |
2935 | } | |
2936 | ||
2937 | break; | |
2938 | } | |
2939 | ||
2940 | if (status) | |
2941 | pr_info("%s ocrdma%d service level default\n", | |
2942 | dev_name(&dev->nic_info.pdev->dev), dev->id); | |
2943 | else | |
2944 | pr_info("%s ocrdma%d service level %d\n", | |
2945 | dev_name(&dev->nic_info.pdev->dev), dev->id, | |
2946 | srvc_lvl); | |
2947 | ||
2948 | dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state); | |
2949 | dev->sl = srvc_lvl; | |
2950 | } | |
2951 | ||
fe2caefc PP |
2952 | int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah) |
2953 | { | |
2954 | int i; | |
2955 | int status = -EINVAL; | |
2956 | struct ocrdma_av *av; | |
2957 | unsigned long flags; | |
2958 | ||
2959 | av = dev->av_tbl.va; | |
2960 | spin_lock_irqsave(&dev->av_tbl.lock, flags); | |
2961 | for (i = 0; i < dev->av_tbl.num_ah; i++) { | |
2962 | if (av->valid == 0) { | |
2963 | av->valid = OCRDMA_AV_VALID; | |
2964 | ah->av = av; | |
2965 | ah->id = i; | |
2966 | status = 0; | |
2967 | break; | |
2968 | } | |
2969 | av++; | |
2970 | } | |
2971 | if (i == dev->av_tbl.num_ah) | |
2972 | status = -EAGAIN; | |
2973 | spin_unlock_irqrestore(&dev->av_tbl.lock, flags); | |
2974 | return status; | |
2975 | } | |
2976 | ||
2977 | int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah) | |
2978 | { | |
2979 | unsigned long flags; | |
2980 | spin_lock_irqsave(&dev->av_tbl.lock, flags); | |
2981 | ah->av->valid = 0; | |
2982 | spin_unlock_irqrestore(&dev->av_tbl.lock, flags); | |
2983 | return 0; | |
2984 | } | |
2985 | ||
c88bd03f | 2986 | static int ocrdma_create_eqs(struct ocrdma_dev *dev) |
fe2caefc | 2987 | { |
da496438 | 2988 | int num_eq, i, status = 0; |
fe2caefc PP |
2989 | int irq; |
2990 | unsigned long flags = 0; | |
2991 | ||
2992 | num_eq = dev->nic_info.msix.num_vectors - | |
2993 | dev->nic_info.msix.start_vector; | |
2994 | if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) { | |
2995 | num_eq = 1; | |
2996 | flags = IRQF_SHARED; | |
f99b1649 | 2997 | } else { |
fe2caefc | 2998 | num_eq = min_t(u32, num_eq, num_online_cpus()); |
f99b1649 NG |
2999 | } |
3000 | ||
c88bd03f NG |
3001 | if (!num_eq) |
3002 | return -EINVAL; | |
3003 | ||
3004 | dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL); | |
3005 | if (!dev->eq_tbl) | |
fe2caefc PP |
3006 | return -ENOMEM; |
3007 | ||
3008 | for (i = 0; i < num_eq; i++) { | |
c88bd03f | 3009 | status = ocrdma_create_eq(dev, &dev->eq_tbl[i], |
fad51b7d | 3010 | OCRDMA_EQ_LEN); |
fe2caefc PP |
3011 | if (status) { |
3012 | status = -EINVAL; | |
3013 | break; | |
3014 | } | |
c88bd03f | 3015 | sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d", |
fe2caefc | 3016 | dev->id, i); |
c88bd03f | 3017 | irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]); |
fe2caefc | 3018 | status = request_irq(irq, ocrdma_irq_handler, flags, |
c88bd03f NG |
3019 | dev->eq_tbl[i].irq_name, |
3020 | &dev->eq_tbl[i]); | |
3021 | if (status) | |
3022 | goto done; | |
fe2caefc PP |
3023 | dev->eq_cnt += 1; |
3024 | } | |
3025 | /* one eq is sufficient for data path to work */ | |
c88bd03f NG |
3026 | return 0; |
3027 | done: | |
3028 | ocrdma_destroy_eqs(dev); | |
fe2caefc PP |
3029 | return status; |
3030 | } | |
3031 | ||
b4dbe8d5 MA |
3032 | static int ocrdma_mbx_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq, |
3033 | int num) | |
3034 | { | |
3035 | int i, status = -ENOMEM; | |
3036 | struct ocrdma_modify_eqd_req *cmd; | |
3037 | ||
3038 | cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY, sizeof(*cmd)); | |
3039 | if (!cmd) | |
3040 | return status; | |
3041 | ||
3042 | ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_MODIFY_EQ_DELAY, | |
3043 | OCRDMA_SUBSYS_COMMON, sizeof(*cmd)); | |
3044 | ||
3045 | cmd->cmd.num_eq = num; | |
3046 | for (i = 0; i < num; i++) { | |
3047 | cmd->cmd.set_eqd[i].eq_id = eq[i].q.id; | |
3048 | cmd->cmd.set_eqd[i].phase = 0; | |
3049 | cmd->cmd.set_eqd[i].delay_multiplier = | |
3050 | (eq[i].aic_obj.prev_eqd * 65)/100; | |
3051 | } | |
3052 | status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd); | |
3053 | if (status) | |
3054 | goto mbx_err; | |
3055 | mbx_err: | |
3056 | kfree(cmd); | |
3057 | return status; | |
3058 | } | |
3059 | ||
3060 | static int ocrdma_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq, | |
3061 | int num) | |
3062 | { | |
3063 | int num_eqs, i = 0; | |
3064 | if (num > 8) { | |
3065 | while (num) { | |
3066 | num_eqs = min(num, 8); | |
3067 | ocrdma_mbx_modify_eqd(dev, &eq[i], num_eqs); | |
3068 | i += num_eqs; | |
3069 | num -= num_eqs; | |
3070 | } | |
3071 | } else { | |
3072 | ocrdma_mbx_modify_eqd(dev, eq, num); | |
3073 | } | |
3074 | return 0; | |
3075 | } | |
3076 | ||
3077 | void ocrdma_eqd_set_task(struct work_struct *work) | |
3078 | { | |
3079 | struct ocrdma_dev *dev = | |
3080 | container_of(work, struct ocrdma_dev, eqd_work.work); | |
3081 | struct ocrdma_eq *eq = 0; | |
3082 | int i, num = 0, status = -EINVAL; | |
3083 | u64 eq_intr; | |
3084 | ||
3085 | for (i = 0; i < dev->eq_cnt; i++) { | |
3086 | eq = &dev->eq_tbl[i]; | |
3087 | if (eq->aic_obj.eq_intr_cnt > eq->aic_obj.prev_eq_intr_cnt) { | |
3088 | eq_intr = eq->aic_obj.eq_intr_cnt - | |
3089 | eq->aic_obj.prev_eq_intr_cnt; | |
3090 | if ((eq_intr > EQ_INTR_PER_SEC_THRSH_HI) && | |
3091 | (eq->aic_obj.prev_eqd == EQ_AIC_MIN_EQD)) { | |
3092 | eq->aic_obj.prev_eqd = EQ_AIC_MAX_EQD; | |
3093 | num++; | |
3094 | } else if ((eq_intr < EQ_INTR_PER_SEC_THRSH_LOW) && | |
3095 | (eq->aic_obj.prev_eqd == EQ_AIC_MAX_EQD)) { | |
3096 | eq->aic_obj.prev_eqd = EQ_AIC_MIN_EQD; | |
3097 | num++; | |
3098 | } | |
3099 | } | |
3100 | eq->aic_obj.prev_eq_intr_cnt = eq->aic_obj.eq_intr_cnt; | |
3101 | } | |
3102 | ||
3103 | if (num) | |
3104 | status = ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num); | |
3105 | schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000)); | |
3106 | } | |
3107 | ||
fe2caefc PP |
3108 | int ocrdma_init_hw(struct ocrdma_dev *dev) |
3109 | { | |
3110 | int status; | |
c88bd03f NG |
3111 | |
3112 | /* create the eqs */ | |
3113 | status = ocrdma_create_eqs(dev); | |
fe2caefc PP |
3114 | if (status) |
3115 | goto qpeq_err; | |
3116 | status = ocrdma_create_mq(dev); | |
3117 | if (status) | |
3118 | goto mq_err; | |
3119 | status = ocrdma_mbx_query_fw_config(dev); | |
3120 | if (status) | |
3121 | goto conf_err; | |
3122 | status = ocrdma_mbx_query_dev(dev); | |
3123 | if (status) | |
3124 | goto conf_err; | |
3125 | status = ocrdma_mbx_query_fw_ver(dev); | |
3126 | if (status) | |
3127 | goto conf_err; | |
3128 | status = ocrdma_mbx_create_ah_tbl(dev); | |
3129 | if (status) | |
3130 | goto conf_err; | |
a51f06e1 SX |
3131 | status = ocrdma_mbx_get_phy_info(dev); |
3132 | if (status) | |
daac9681 | 3133 | goto info_attrb_err; |
a51f06e1 SX |
3134 | status = ocrdma_mbx_get_ctrl_attribs(dev); |
3135 | if (status) | |
daac9681 | 3136 | goto info_attrb_err; |
a51f06e1 | 3137 | |
fe2caefc PP |
3138 | return 0; |
3139 | ||
daac9681 DS |
3140 | info_attrb_err: |
3141 | ocrdma_mbx_delete_ah_tbl(dev); | |
fe2caefc PP |
3142 | conf_err: |
3143 | ocrdma_destroy_mq(dev); | |
3144 | mq_err: | |
c88bd03f | 3145 | ocrdma_destroy_eqs(dev); |
fe2caefc | 3146 | qpeq_err: |
ef99c4c2 | 3147 | pr_err("%s() status=%d\n", __func__, status); |
fe2caefc PP |
3148 | return status; |
3149 | } | |
3150 | ||
3151 | void ocrdma_cleanup_hw(struct ocrdma_dev *dev) | |
3152 | { | |
9ba1377d | 3153 | ocrdma_free_pd_pool(dev); |
fe2caefc PP |
3154 | ocrdma_mbx_delete_ah_tbl(dev); |
3155 | ||
fe2caefc PP |
3156 | /* cleanup the control path */ |
3157 | ocrdma_destroy_mq(dev); | |
314fdf44 SX |
3158 | |
3159 | /* cleanup the eqs */ | |
3160 | ocrdma_destroy_eqs(dev); | |
fe2caefc | 3161 | } |