[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / qedr / qedr.h

/* QLogic qedr NIC Driver
 * Copyright (c) 2015-2016  QLogic Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and /or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __QEDR_H__
#define __QEDR_H__

#include <linux/pci.h>
#include <rdma/ib_addr.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_roce_if.h>
#include <linux/qed/qede_roce.h>
#include "qedr_hsi.h"

#define QEDR_MODULE_VERSION	"8.10.10.0"
#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
#define DP_NAME(dev) ((dev)->ibdev.name)

#define DP_DEBUG(dev, module, fmt, ...)					\
	pr_debug("(%s) " module ": " fmt,				\
		 DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)

#define QEDR_MSG_INIT "INIT"
#define QEDR_MSG_MISC "MISC"
#define QEDR_MSG_CQ   "  CQ"
#define QEDR_MSG_MR   "  MR"
#define QEDR_MSG_RQ   "  RQ"
#define QEDR_MSG_SQ   "  SQ"
#define QEDR_MSG_QP   "  QP"
#define QEDR_MSG_GSI  " GSI"

#define QEDR_CQ_MAGIC_NUMBER   (0x11223344)

struct qedr_dev;

struct qedr_cnq {
	struct qedr_dev		*dev;
	struct qed_chain	pbl;
	struct qed_sb_info	*sb;
	char			name[32];
	u64			n_comp;
	__le16			*hw_cons_ptr;
	u8			index;
};

#define QEDR_MAX_SGID 128

struct qedr_device_attr {
	u32	vendor_id;
	u32	vendor_part_id;
	u32	hw_ver;
	u64	fw_ver;
	u64	node_guid;
	u64	sys_image_guid;
	u8	max_cnq;
	u8	max_sge;
	u16	max_inline;
	u32	max_sqe;
	u32	max_rqe;
	u8	max_qp_resp_rd_atomic_resc;
	u8	max_qp_req_rd_atomic_resc;
	u64	max_dev_resp_rd_atomic_resc;
	u32	max_cq;
	u32	max_qp;
	u32	max_mr;
	u64	max_mr_size;
	u32	max_cqe;
	u32	max_mw;
	u32	max_fmr;
	u32	max_mr_mw_fmr_pbl;
	u64	max_mr_mw_fmr_size;
	u32	max_pd;
	u32	max_ah;
	u8	max_pkey;
	u32	max_srq;
	u32	max_srq_wr;
	u8	max_srq_sge;
	u8	max_stats_queues;
	u32	dev_caps;

	u64	page_size_caps;
	u8	dev_ack_delay;
	u32	reserved_lkey;
	u32	bad_pkey_counter;
	struct qed_rdma_events events;
};

#define QEDR_ENET_STATE_BIT	(0)

struct qedr_dev {
	struct ib_device	ibdev;
	struct qed_dev		*cdev;
	struct pci_dev		*pdev;
	struct net_device	*ndev;

	enum ib_atomic_cap	atomic_cap;

	void *rdma_ctx;
	struct qedr_device_attr attr;

	const struct qed_rdma_ops *ops;
	struct qed_int_info	int_info;

	struct qed_sb_info	*sb_array;
	struct qedr_cnq		*cnq_array;
	int			num_cnq;
	int			sb_start;

	void __iomem		*db_addr;
	u64			db_phys_addr;
	u32			db_size;
	u16			dpi;

	union ib_gid *sgid_tbl;

	/* Lock for sgid table */
	spinlock_t sgid_lock;

	u64			guid;

	u32			dp_module;
	u8			dp_level;
	u8			num_hwfns;
	uint			wq_multiplier;
	u8			gsi_ll2_mac_address[ETH_ALEN];
	int			gsi_qp_created;
	struct qedr_cq		*gsi_sqcq;
	struct qedr_cq		*gsi_rqcq;
	struct qedr_qp		*gsi_qp;

	unsigned long enet_state;
};

#define QEDR_MAX_SQ_PBL			(0x8000)
#define QEDR_MAX_SQ_PBL_ENTRIES		(0x10000 / sizeof(void *))
#define QEDR_SQE_ELEMENT_SIZE		(sizeof(struct rdma_sq_sge))
#define QEDR_MAX_SQE_ELEMENTS_PER_SQE	(ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
					 QEDR_SQE_ELEMENT_SIZE)
#define QEDR_MAX_SQE_ELEMENTS_PER_PAGE	((RDMA_RING_PAGE_SIZE) / \
					 QEDR_SQE_ELEMENT_SIZE)
#define QEDR_MAX_SQE			((QEDR_MAX_SQ_PBL_ENTRIES) *\
					 (RDMA_RING_PAGE_SIZE) / \
					 (QEDR_SQE_ELEMENT_SIZE) /\
					 (QEDR_MAX_SQE_ELEMENTS_PER_SQE))
/* RQ */
#define QEDR_MAX_RQ_PBL			(0x2000)
#define QEDR_MAX_RQ_PBL_ENTRIES		(0x10000 / sizeof(void *))
#define QEDR_RQE_ELEMENT_SIZE		(sizeof(struct rdma_rq_sge))
#define QEDR_MAX_RQE_ELEMENTS_PER_RQE	(RDMA_MAX_SGE_PER_RQ_WQE)
#define QEDR_MAX_RQE_ELEMENTS_PER_PAGE	((RDMA_RING_PAGE_SIZE) / \
					 QEDR_RQE_ELEMENT_SIZE)
#define QEDR_MAX_RQE			((QEDR_MAX_RQ_PBL_ENTRIES) *\
					 (RDMA_RING_PAGE_SIZE) / \
					 (QEDR_RQE_ELEMENT_SIZE) /\
					 (QEDR_MAX_RQE_ELEMENTS_PER_RQE))

#define QEDR_CQE_SIZE	(sizeof(union rdma_cqe))
#define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
#define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
				  sizeof(u64)) - 1)
#define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
			     (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))

#define QEDR_ROCE_MAX_CNQ_SIZE		(0x4000)

#define QEDR_MAX_PORT			(1)
#define QEDR_PORT			(1)

#define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)

#define QEDR_ROCE_PKEY_MAX 1
#define QEDR_ROCE_PKEY_TABLE_LEN 1
#define QEDR_ROCE_PKEY_DEFAULT 0xffff

struct qedr_pbl {
	struct list_head list_entry;
	void *va;
	dma_addr_t pa;
};

struct qedr_ucontext {
	struct ib_ucontext ibucontext;
	struct qedr_dev *dev;
	struct qedr_pd *pd;
	u64 dpi_addr;
	u64 dpi_phys_addr;
	u32 dpi_size;
	u16 dpi;

	struct list_head mm_head;

	/* Lock to protect mm list */
	struct mutex mm_list_lock;
};

union db_prod64 {
	struct rdma_pwm_val32_data data;
	u64 raw;
};

enum qedr_cq_type {
	QEDR_CQ_TYPE_GSI,
	QEDR_CQ_TYPE_KERNEL,
	QEDR_CQ_TYPE_USER,
};

struct qedr_pbl_info {
	u32 num_pbls;
	u32 num_pbes;
	u32 pbl_size;
	u32 pbe_size;
	bool two_layered;
};

struct qedr_userq {
	struct ib_umem *umem;
	struct qedr_pbl_info pbl_info;
	struct qedr_pbl *pbl_tbl;
	u64 buf_addr;
	size_t buf_len;
};

struct qedr_cq {
	struct ib_cq ibcq;

	enum qedr_cq_type cq_type;
	u32 sig;

	u16 icid;

	/* Lock to protect multiplem CQ's */
	spinlock_t cq_lock;
	u8 arm_flags;
	struct qed_chain pbl;

	void __iomem *db_addr;
	union db_prod64 db;

	u8 pbl_toggle;
	union rdma_cqe *latest_cqe;
	union rdma_cqe *toggle_cqe;

	u32 cq_cons;

	struct qedr_userq q;
};

struct qedr_pd {
	struct ib_pd ibpd;
	u32 pd_id;
	struct qedr_ucontext *uctx;
};

struct qedr_mm {
	struct {
		u64 phy_addr;
		unsigned long len;
	} key;
	struct list_head entry;
};

union db_prod32 {
	struct rdma_pwm_val16_data data;
	u32 raw;
};

struct qedr_qp_hwq_info {
	/* WQE Elements */
	struct qed_chain pbl;
	u64 p_phys_addr_tbl;
	u32 max_sges;

	/* WQE */
	u16 prod;
	u16 cons;
	u16 wqe_cons;
	u16 gsi_cons;
	u16 max_wr;

	/* DB */
	void __iomem *db;
	union db_prod32 db_data;
};

#define QEDR_INC_SW_IDX(p_info, index)					\
	do {								\
		p_info->index = (p_info->index + 1) &			\
				qed_chain_get_capacity(p_info->pbl)	\
	} while (0)

enum qedr_qp_err_bitmap {
	QEDR_QP_ERR_SQ_FULL = 1,
	QEDR_QP_ERR_RQ_FULL = 2,
	QEDR_QP_ERR_BAD_SR = 4,
	QEDR_QP_ERR_BAD_RR = 8,
	QEDR_QP_ERR_SQ_PBL_FULL = 16,
	QEDR_QP_ERR_RQ_PBL_FULL = 32,
};

struct qedr_qp {
	struct ib_qp ibqp;	/* must be first */
	struct qedr_dev *dev;

	struct qedr_qp_hwq_info sq;
	struct qedr_qp_hwq_info rq;

	u32 max_inline_data;

	/* Lock for QP's */
	spinlock_t q_lock;
	struct qedr_cq *sq_cq;
	struct qedr_cq *rq_cq;
	struct qedr_srq *srq;
	enum qed_roce_qp_state state;
	u32 id;
	struct qedr_pd *pd;
	enum ib_qp_type qp_type;
	struct qed_rdma_qp *qed_qp;
	u32 qp_id;
	u16 icid;
	u16 mtu;
	int sgid_idx;
	u32 rq_psn;
	u32 sq_psn;
	u32 qkey;
	u32 dest_qp_num;

	/* Relevant to qps created from kernel space only (ULPs) */
	u8 prev_wqe_size;
	u16 wqe_cons;
	u32 err_bitmap;
	bool signaled;

	/* SQ shadow */
	struct {
		u64 wr_id;
		enum ib_wc_opcode opcode;
		u32 bytes_len;
		u8 wqe_size;
		bool signaled;
		dma_addr_t icrc_mapping;
		u32 *icrc;
		struct qedr_mr *mr;
	} *wqe_wr_id;

	/* RQ shadow */
	struct {
		u64 wr_id;
		struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
		u8 wqe_size;

		u8 smac[ETH_ALEN];
		u16 vlan_id;
		int rc;
	} *rqe_wr_id;

	/* Relevant to qps created from user space only (applications) */
	struct qedr_userq usq;
	struct qedr_userq urq;
};

struct qedr_ah {
	struct ib_ah ibah;
	struct ib_ah_attr attr;
};

enum qedr_mr_type {
	QEDR_MR_USER,
	QEDR_MR_KERNEL,
	QEDR_MR_DMA,
	QEDR_MR_FRMR,
};

struct mr_info {
	struct qedr_pbl *pbl_table;
	struct qedr_pbl_info pbl_info;
	struct list_head free_pbl_list;
	struct list_head inuse_pbl_list;
	u32 completed;
	u32 completed_handled;
};

struct qedr_mr {
	struct ib_mr ibmr;
	struct ib_umem *umem;

	struct qed_rdma_register_tid_in_params hw_mr;
	enum qedr_mr_type type;

	struct qedr_dev *dev;
	struct mr_info info;

	u64 *pages;
	u32 npages;
};

#define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))

#define QEDR_RESP_IMM	(RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
			 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
#define QEDR_RESP_RDMA	(RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
			 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
#define QEDR_RESP_RDMA_IMM (QEDR_RESP_IMM | QEDR_RESP_RDMA)

static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
{
	info->cons = (info->cons + 1) % info->max_wr;
	info->wqe_cons++;
}

static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
{
	info->prod = (info->prod + 1) % info->max_wr;
}

static inline int qedr_get_dmac(struct qedr_dev *dev,
				struct ib_ah_attr *ah_attr, u8 *mac_addr)
{
	union ib_gid zero_sgid = { { 0 } };
	struct in6_addr in6;

	if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) {
		DP_ERR(dev, "Local port GID not supported\n");
		eth_zero_addr(mac_addr);
		return -EINVAL;
	}

	memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
	ether_addr_copy(mac_addr, ah_attr->dmac);

	return 0;
}

static inline
struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
{
	return container_of(ibucontext, struct qedr_ucontext, ibucontext);
}

static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
{
	return container_of(ibdev, struct qedr_dev, ibdev);
}

static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
{
	return container_of(ibpd, struct qedr_pd, ibpd);
}

static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
{
	return container_of(ibcq, struct qedr_cq, ibcq);
}

static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
{
	return container_of(ibqp, struct qedr_qp, ibqp);
}

static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah)
{
	return container_of(ibah, struct qedr_ah, ibah);
}

static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
{
	return container_of(ibmr, struct qedr_mr, ibmr);
}
#endif
Commit	Line	Data
2e0cbc4d RA	1	/* QLogic qedr NIC Driver
	2	* Copyright (c) 2015-2016 QLogic Corporation
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and /or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32	#ifndef __QEDR_H__
	33	#define __QEDR_H__
	34
	35	#include <linux/pci.h>
	36	#include <rdma/ib_addr.h>
	37	#include <linux/qed/qed_if.h>
ec72fce4 RA	38	#include <linux/qed/qed_chain.h>
ec72fce4 RA	39	#include <linux/qed/qed_roce_if.h>
2e0cbc4d	40	#include <linux/qed/qede_roce.h>
ec72fce4	41	#include "qedr_hsi.h"
2e0cbc4d RA	42
	43	#define QEDR_MODULE_VERSION "8.10.10.0"
	44	#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
	45	#define DP_NAME(dev) ((dev)->ibdev.name)
	46
	47	#define DP_DEBUG(dev, module, fmt, ...) \
	48	pr_debug("(%s) " module ": " fmt, \
	49	DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
	50
	51	#define QEDR_MSG_INIT "INIT"
ac1b36e5	52	#define QEDR_MSG_MISC "MISC"
a7efd777 RA	53	#define QEDR_MSG_CQ " CQ"
a7efd777 RA	54	#define QEDR_MSG_MR " MR"
cecbcddf RA	55	#define QEDR_MSG_RQ " RQ"
	56	#define QEDR_MSG_SQ " SQ"
	57	#define QEDR_MSG_QP " QP"
04886779	58	#define QEDR_MSG_GSI " GSI"
a7efd777 RA	59
a7efd777 RA	60	#define QEDR_CQ_MAGIC_NUMBER (0x11223344)
2e0cbc4d	61
ec72fce4 RA	62	struct qedr_dev;
	63
	64	struct qedr_cnq {
	65	struct qedr_dev *dev;
	66	struct qed_chain pbl;
	67	struct qed_sb_info *sb;
	68	char name[32];
	69	u64 n_comp;
	70	__le16 *hw_cons_ptr;
	71	u8 index;
	72	};
	73
	74	#define QEDR_MAX_SGID 128
	75
	76	struct qedr_device_attr {
	77	u32 vendor_id;
	78	u32 vendor_part_id;
	79	u32 hw_ver;
	80	u64 fw_ver;
	81	u64 node_guid;
	82	u64 sys_image_guid;
	83	u8 max_cnq;
	84	u8 max_sge;
	85	u16 max_inline;
	86	u32 max_sqe;
	87	u32 max_rqe;
	88	u8 max_qp_resp_rd_atomic_resc;
	89	u8 max_qp_req_rd_atomic_resc;
	90	u64 max_dev_resp_rd_atomic_resc;
	91	u32 max_cq;
	92	u32 max_qp;
	93	u32 max_mr;
	94	u64 max_mr_size;
	95	u32 max_cqe;
	96	u32 max_mw;
	97	u32 max_fmr;
	98	u32 max_mr_mw_fmr_pbl;
	99	u64 max_mr_mw_fmr_size;
	100	u32 max_pd;
	101	u32 max_ah;
	102	u8 max_pkey;
	103	u32 max_srq;
	104	u32 max_srq_wr;
	105	u8 max_srq_sge;
	106	u8 max_stats_queues;
	107	u32 dev_caps;
	108
	109	u64 page_size_caps;
	110	u8 dev_ack_delay;
	111	u32 reserved_lkey;
	112	u32 bad_pkey_counter;
	113	struct qed_rdma_events events;
	114	};
	115
f449c7a2 RA	116	#define QEDR_ENET_STATE_BIT (0)
f449c7a2 RA	117
2e0cbc4d RA	118	struct qedr_dev {
	119	struct ib_device ibdev;
	120	struct qed_dev *cdev;
	121	struct pci_dev *pdev;
	122	struct net_device *ndev;
	123
	124	enum ib_atomic_cap atomic_cap;
	125
ec72fce4 RA	126	void *rdma_ctx;
	127	struct qedr_device_attr attr;
	128
	129	const struct qed_rdma_ops *ops;
	130	struct qed_int_info int_info;
	131
	132	struct qed_sb_info *sb_array;
	133	struct qedr_cnq *cnq_array;
	134	int num_cnq;
	135	int sb_start;
	136
	137	void __iomem *db_addr;
	138	u64 db_phys_addr;
	139	u32 db_size;
	140	u16 dpi;
	141
	142	union ib_gid *sgid_tbl;
	143
	144	/* Lock for sgid table */
	145	spinlock_t sgid_lock;
	146
	147	u64 guid;
	148
2e0cbc4d RA	149	u32 dp_module;
2e0cbc4d RA	150	u8 dp_level;
ec72fce4	151	u8 num_hwfns;
cecbcddf	152	uint wq_multiplier;
1d1424c8	153	u8 gsi_ll2_mac_address[ETH_ALEN];
04886779 RA	154	int gsi_qp_created;
	155	struct qedr_cq *gsi_sqcq;
	156	struct qedr_cq *gsi_rqcq;
	157	struct qedr_qp *gsi_qp;
f449c7a2 RA	158
f449c7a2 RA	159	unsigned long enet_state;
2e0cbc4d	160	};
ec72fce4 RA	161
	162	#define QEDR_MAX_SQ_PBL (0x8000)
	163	#define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
	164	#define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
	165	#define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
	166	QEDR_SQE_ELEMENT_SIZE)
	167	#define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
	168	QEDR_SQE_ELEMENT_SIZE)
	169	#define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
	170	(RDMA_RING_PAGE_SIZE) / \
	171	(QEDR_SQE_ELEMENT_SIZE) /\
	172	(QEDR_MAX_SQE_ELEMENTS_PER_SQE))
	173	/* RQ */
	174	#define QEDR_MAX_RQ_PBL (0x2000)
	175	#define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
	176	#define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
	177	#define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
	178	#define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
	179	QEDR_RQE_ELEMENT_SIZE)
	180	#define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
	181	(RDMA_RING_PAGE_SIZE) / \
	182	(QEDR_RQE_ELEMENT_SIZE) /\
	183	(QEDR_MAX_RQE_ELEMENTS_PER_RQE))
	184
	185	#define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
	186	#define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
	187	#define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
	188	sizeof(u64)) - 1)
	189	#define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
	190	(QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
	191
	192	#define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
	193
	194	#define QEDR_MAX_PORT (1)
f449c7a2	195	#define QEDR_PORT (1)
ec72fce4 RA	196
	197	#define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
	198
ac1b36e5 RA	199	#define QEDR_ROCE_PKEY_MAX 1
	200	#define QEDR_ROCE_PKEY_TABLE_LEN 1
	201	#define QEDR_ROCE_PKEY_DEFAULT 0xffff
	202
a7efd777 RA	203	struct qedr_pbl {
	204	struct list_head list_entry;
	205	void *va;
	206	dma_addr_t pa;
	207	};
	208
ac1b36e5 RA	209	struct qedr_ucontext {
	210	struct ib_ucontext ibucontext;
	211	struct qedr_dev *dev;
	212	struct qedr_pd *pd;
	213	u64 dpi_addr;
	214	u64 dpi_phys_addr;
	215	u32 dpi_size;
	216	u16 dpi;
	217
	218	struct list_head mm_head;
	219
	220	/* Lock to protect mm list */
	221	struct mutex mm_list_lock;
	222	};
	223
a7efd777 RA	224	union db_prod64 {
	225	struct rdma_pwm_val32_data data;
	226	u64 raw;
	227	};
	228
	229	enum qedr_cq_type {
	230	QEDR_CQ_TYPE_GSI,
	231	QEDR_CQ_TYPE_KERNEL,
	232	QEDR_CQ_TYPE_USER,
	233	};
	234
	235	struct qedr_pbl_info {
	236	u32 num_pbls;
	237	u32 num_pbes;
	238	u32 pbl_size;
	239	u32 pbe_size;
	240	bool two_layered;
	241	};
	242
	243	struct qedr_userq {
	244	struct ib_umem *umem;
	245	struct qedr_pbl_info pbl_info;
	246	struct qedr_pbl *pbl_tbl;
	247	u64 buf_addr;
	248	size_t buf_len;
	249	};
	250
	251	struct qedr_cq {
	252	struct ib_cq ibcq;
	253
	254	enum qedr_cq_type cq_type;
	255	u32 sig;
	256
	257	u16 icid;
	258
	259	/* Lock to protect multiplem CQ's */
	260	spinlock_t cq_lock;
	261	u8 arm_flags;
	262	struct qed_chain pbl;
	263
	264	void __iomem *db_addr;
	265	union db_prod64 db;
	266
	267	u8 pbl_toggle;
	268	union rdma_cqe *latest_cqe;
	269	union rdma_cqe *toggle_cqe;
	270
	271	u32 cq_cons;
	272
	273	struct qedr_userq q;
	274	};
	275
	276	struct qedr_pd {
	277	struct ib_pd ibpd;
	278	u32 pd_id;
	279	struct qedr_ucontext *uctx;
	280	};
	281
ac1b36e5 RA	282	struct qedr_mm {
	283	struct {
	284	u64 phy_addr;
	285	unsigned long len;
	286	} key;
	287	struct list_head entry;
	288	};
	289
cecbcddf RA	290	union db_prod32 {
	291	struct rdma_pwm_val16_data data;
	292	u32 raw;
	293	};
	294
	295	struct qedr_qp_hwq_info {
	296	/* WQE Elements */
	297	struct qed_chain pbl;
	298	u64 p_phys_addr_tbl;
	299	u32 max_sges;
	300
	301	/* WQE */
	302	u16 prod;
	303	u16 cons;
	304	u16 wqe_cons;
04886779	305	u16 gsi_cons;
cecbcddf RA	306	u16 max_wr;
	307
	308	/* DB */
	309	void __iomem *db;
	310	union db_prod32 db_data;
	311	};
	312
	313	#define QEDR_INC_SW_IDX(p_info, index) \
	314	do { \
	315	p_info->index = (p_info->index + 1) & \
	316	qed_chain_get_capacity(p_info->pbl) \
	317	} while (0)
	318
	319	enum qedr_qp_err_bitmap {
	320	QEDR_QP_ERR_SQ_FULL = 1,
	321	QEDR_QP_ERR_RQ_FULL = 2,
	322	QEDR_QP_ERR_BAD_SR = 4,
	323	QEDR_QP_ERR_BAD_RR = 8,
	324	QEDR_QP_ERR_SQ_PBL_FULL = 16,
	325	QEDR_QP_ERR_RQ_PBL_FULL = 32,
	326	};
	327
	328	struct qedr_qp {
	329	struct ib_qp ibqp; /* must be first */
	330	struct qedr_dev *dev;
	331
	332	struct qedr_qp_hwq_info sq;
	333	struct qedr_qp_hwq_info rq;
	334
	335	u32 max_inline_data;
	336
	337	/* Lock for QP's */
	338	spinlock_t q_lock;
	339	struct qedr_cq *sq_cq;
	340	struct qedr_cq *rq_cq;
	341	struct qedr_srq *srq;
	342	enum qed_roce_qp_state state;
	343	u32 id;
	344	struct qedr_pd *pd;
	345	enum ib_qp_type qp_type;
	346	struct qed_rdma_qp *qed_qp;
	347	u32 qp_id;
	348	u16 icid;
	349	u16 mtu;
	350	int sgid_idx;
	351	u32 rq_psn;
	352	u32 sq_psn;
	353	u32 qkey;
	354	u32 dest_qp_num;
	355
	356	/* Relevant to qps created from kernel space only (ULPs) */
	357	u8 prev_wqe_size;
	358	u16 wqe_cons;
	359	u32 err_bitmap;
	360	bool signaled;
	361
	362	/* SQ shadow */
	363	struct {
	364	u64 wr_id;
	365	enum ib_wc_opcode opcode;
	366	u32 bytes_len;
	367	u8 wqe_size;
	368	bool signaled;
	369	dma_addr_t icrc_mapping;
370	u32 *icrc;
371	struct qedr_mr *mr;
372	} *wqe_wr_id;
373
374	/* RQ shadow */
375	struct {
376	u64 wr_id;
377	struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
378	u8 wqe_size;
379
04886779	380	u8 smac[ETH_ALEN];
cecbcddf RA	381	u16 vlan_id;
	382	int rc;
	383	} *rqe_wr_id;
	384
	385	/* Relevant to qps created from user space only (applications) */
	386	struct qedr_userq usq;
	387	struct qedr_userq urq;
	388	};
	389
e0290cce RA	390	struct qedr_ah {
	391	struct ib_ah ibah;
	392	struct ib_ah_attr attr;
	393	};
	394
	395	enum qedr_mr_type {
	396	QEDR_MR_USER,
	397	QEDR_MR_KERNEL,
	398	QEDR_MR_DMA,
	399	QEDR_MR_FRMR,
	400	};
	401
	402	struct mr_info {
	403	struct qedr_pbl *pbl_table;
	404	struct qedr_pbl_info pbl_info;
	405	struct list_head free_pbl_list;
	406	struct list_head inuse_pbl_list;
	407	u32 completed;
	408	u32 completed_handled;
	409	};
	410
	411	struct qedr_mr {
	412	struct ib_mr ibmr;
	413	struct ib_umem *umem;
	414
	415	struct qed_rdma_register_tid_in_params hw_mr;
	416	enum qedr_mr_type type;
	417
	418	struct qedr_dev *dev;
	419	struct mr_info info;
	420
	421	u64 *pages;
	422	u32 npages;
	423	};
	424
afa0e13b RA	425	#define SET_FIELD2(value, name, flag) ((value) \|= ((flag) << (name ## _SHIFT)))
	426
	427	#define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
	428	RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
	429	#define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
	430	RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
	431	#define QEDR_RESP_RDMA_IMM (QEDR_RESP_IMM \| QEDR_RESP_RDMA)
	432
	433	static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
	434	{
	435	info->cons = (info->cons + 1) % info->max_wr;
	436	info->wqe_cons++;
	437	}
	438
	439	static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
	440	{
	441	info->prod = (info->prod + 1) % info->max_wr;
	442	}
	443
cecbcddf RA	444	static inline int qedr_get_dmac(struct qedr_dev *dev,
	445	struct ib_ah_attr ah_attr, u8 mac_addr)
	446	{
	447	union ib_gid zero_sgid = { { 0 } };
	448	struct in6_addr in6;
	449
	450	if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) {
	451	DP_ERR(dev, "Local port GID not supported\n");
	452	eth_zero_addr(mac_addr);
	453	return -EINVAL;
	454	}
	455
	456	memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
	457	ether_addr_copy(mac_addr, ah_attr->dmac);
	458
	459	return 0;
	460	}
	461
ac1b36e5 RA	462	static inline
	463	struct qedr_ucontext get_qedr_ucontext(struct ib_ucontext ibucontext)
	464	{
	465	return container_of(ibucontext, struct qedr_ucontext, ibucontext);
	466	}
	467
ec72fce4 RA	468	static inline struct qedr_dev get_qedr_dev(struct ib_device ibdev)
	469	{
	470	return container_of(ibdev, struct qedr_dev, ibdev);
	471	}
	472
a7efd777 RA	473	static inline struct qedr_pd get_qedr_pd(struct ib_pd ibpd)
	474	{
	475	return container_of(ibpd, struct qedr_pd, ibpd);
	476	}
	477
	478	static inline struct qedr_cq get_qedr_cq(struct ib_cq ibcq)
	479	{
	480	return container_of(ibcq, struct qedr_cq, ibcq);
	481	}
	482
cecbcddf RA	483	static inline struct qedr_qp get_qedr_qp(struct ib_qp ibqp)
	484	{
	485	return container_of(ibqp, struct qedr_qp, ibqp);
	486	}
e0290cce	487
04886779 RA	488	static inline struct qedr_ah get_qedr_ah(struct ib_ah ibah)
	489	{
	490	return container_of(ibah, struct qedr_ah, ibah);
	491	}
	492
e0290cce RA	493	static inline struct qedr_mr get_qedr_mr(struct ib_mr ibmr)
	494	{
	495	return container_of(ibmr, struct qedr_mr, ibmr);
	496	}
2e0cbc4d	497	#endif