[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / qedr / qedr_cm.c

/* QLogic qedr NIC Driver
 * Copyright (c) 2015-2016  QLogic Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and /or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#include <linux/dma-mapping.h>
#include <linux/crc32.h>
#include <linux/iommu.h>
#include <net/ip.h>
#include <net/ipv6.h>
#include <net/udp.h>

#include <rdma/ib_verbs.h>
#include <rdma/ib_user_verbs.h>
#include <rdma/iw_cm.h>
#include <rdma/ib_umem.h>
#include <rdma/ib_addr.h>
#include <rdma/ib_cache.h>

#include <linux/qed/qed_if.h>
#include <linux/qed/qed_roce_if.h>
#include "qedr.h"
#include "verbs.h"
#include <rdma/qedr-abi.h>
#include "qedr_cm.h"

void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info)
{
	info->gsi_cons = (info->gsi_cons + 1) % info->max_wr;
}

void qedr_store_gsi_qp_cq(struct qedr_dev *dev, struct qedr_qp *qp,
			  struct ib_qp_init_attr *attrs)
{
	dev->gsi_qp_created = 1;
	dev->gsi_sqcq = get_qedr_cq(attrs->send_cq);
	dev->gsi_rqcq = get_qedr_cq(attrs->recv_cq);
	dev->gsi_qp = qp;
}

void qedr_ll2_tx_cb(void *_qdev, struct qed_roce_ll2_packet *pkt)
{
	struct qedr_dev *dev = (struct qedr_dev *)_qdev;
	struct qedr_cq *cq = dev->gsi_sqcq;
	struct qedr_qp *qp = dev->gsi_qp;
	unsigned long flags;

	DP_DEBUG(dev, QEDR_MSG_GSI,
		 "LL2 TX CB: gsi_sqcq=%p, gsi_rqcq=%p, gsi_cons=%d, ibcq_comp=%s\n",
		 dev->gsi_sqcq, dev->gsi_rqcq, qp->sq.gsi_cons,
		 cq->ibcq.comp_handler ? "Yes" : "No");

	dma_free_coherent(&dev->pdev->dev, pkt->header.len, pkt->header.vaddr,
			  pkt->header.baddr);
	kfree(pkt);

	spin_lock_irqsave(&qp->q_lock, flags);
	qedr_inc_sw_gsi_cons(&qp->sq);
	spin_unlock_irqrestore(&qp->q_lock, flags);

	if (cq->ibcq.comp_handler)
		(*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
}

void qedr_ll2_rx_cb(void *_dev, struct qed_roce_ll2_packet *pkt,
		    struct qed_roce_ll2_rx_params *params)
{
	struct qedr_dev *dev = (struct qedr_dev *)_dev;
	struct qedr_cq *cq = dev->gsi_rqcq;
	struct qedr_qp *qp = dev->gsi_qp;
	unsigned long flags;

	spin_lock_irqsave(&qp->q_lock, flags);

	qp->rqe_wr_id[qp->rq.gsi_cons].rc = params->rc;
	qp->rqe_wr_id[qp->rq.gsi_cons].vlan_id = params->vlan_id;
	qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length = pkt->payload[0].len;
	ether_addr_copy(qp->rqe_wr_id[qp->rq.gsi_cons].smac, params->smac);

	qedr_inc_sw_gsi_cons(&qp->rq);

	spin_unlock_irqrestore(&qp->q_lock, flags);

	if (cq->ibcq.comp_handler)
		(*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
}

static void qedr_destroy_gsi_cq(struct qedr_dev *dev,
				struct ib_qp_init_attr *attrs)
{
	struct qed_rdma_destroy_cq_in_params iparams;
	struct qed_rdma_destroy_cq_out_params oparams;
	struct qedr_cq *cq;

	cq = get_qedr_cq(attrs->send_cq);
	iparams.icid = cq->icid;
	dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
	dev->ops->common->chain_free(dev->cdev, &cq->pbl);

	cq = get_qedr_cq(attrs->recv_cq);
	/* if a dedicated recv_cq was used, delete it too */
	if (iparams.icid != cq->icid) {
		iparams.icid = cq->icid;
		dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
		dev->ops->common->chain_free(dev->cdev, &cq->pbl);
	}
}

static inline int qedr_check_gsi_qp_attrs(struct qedr_dev *dev,
					  struct ib_qp_init_attr *attrs)
{
	if (attrs->cap.max_recv_sge > QEDR_GSI_MAX_RECV_SGE) {
		DP_ERR(dev,
		       " create gsi qp: failed. max_recv_sge is larger the max %d>%d\n",
		       attrs->cap.max_recv_sge, QEDR_GSI_MAX_RECV_SGE);
		return -EINVAL;
	}

	if (attrs->cap.max_recv_wr > QEDR_GSI_MAX_RECV_WR) {
		DP_ERR(dev,
		       " create gsi qp: failed. max_recv_wr is too large %d>%d\n",
		       attrs->cap.max_recv_wr, QEDR_GSI_MAX_RECV_WR);
		return -EINVAL;
	}

	if (attrs->cap.max_send_wr > QEDR_GSI_MAX_SEND_WR) {
		DP_ERR(dev,
		       " create gsi qp: failed. max_send_wr is too large %d>%d\n",
		       attrs->cap.max_send_wr, QEDR_GSI_MAX_SEND_WR);
		return -EINVAL;
	}

	return 0;
}

struct ib_qp *qedr_create_gsi_qp(struct qedr_dev *dev,
				 struct ib_qp_init_attr *attrs,
				 struct qedr_qp *qp)
{
	struct qed_roce_ll2_params ll2_params;
	int rc;

	rc = qedr_check_gsi_qp_attrs(dev, attrs);
	if (rc)
		return ERR_PTR(rc);

	/* configure and start LL2 */
	memset(&ll2_params, 0, sizeof(ll2_params));
	ll2_params.max_tx_buffers = attrs->cap.max_send_wr;
	ll2_params.max_rx_buffers = attrs->cap.max_recv_wr;
	ll2_params.cbs.tx_cb = qedr_ll2_tx_cb;
	ll2_params.cbs.rx_cb = qedr_ll2_rx_cb;
	ll2_params.cb_cookie = (void *)dev;
	ll2_params.mtu = dev->ndev->mtu;
	ether_addr_copy(ll2_params.mac_address, dev->ndev->dev_addr);
	rc = dev->ops->roce_ll2_start(dev->cdev, &ll2_params);
	if (rc) {
		DP_ERR(dev, "create gsi qp: failed on ll2 start. rc=%d\n", rc);
		return ERR_PTR(rc);
	}

	/* create QP */
	qp->ibqp.qp_num = 1;
	qp->rq.max_wr = attrs->cap.max_recv_wr;
	qp->sq.max_wr = attrs->cap.max_send_wr;

	qp->rqe_wr_id = kcalloc(qp->rq.max_wr, sizeof(*qp->rqe_wr_id),
				GFP_KERNEL);
	if (!qp->rqe_wr_id)
		goto err;
	qp->wqe_wr_id = kcalloc(qp->sq.max_wr, sizeof(*qp->wqe_wr_id),
				GFP_KERNEL);
	if (!qp->wqe_wr_id)
		goto err;

	qedr_store_gsi_qp_cq(dev, qp, attrs);
	ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);

	/* the GSI CQ is handled by the driver so remove it from the FW */
	qedr_destroy_gsi_cq(dev, attrs);
	dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
	dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;

	DP_DEBUG(dev, QEDR_MSG_GSI, "created GSI QP %p\n", qp);

	return &qp->ibqp;

err:
	kfree(qp->rqe_wr_id);

	rc = dev->ops->roce_ll2_stop(dev->cdev);
	if (rc)
		DP_ERR(dev, "create gsi qp: failed destroy on create\n");

	return ERR_PTR(-ENOMEM);
}

int qedr_destroy_gsi_qp(struct qedr_dev *dev)
{
	int rc;

	rc = dev->ops->roce_ll2_stop(dev->cdev);
	if (rc)
		DP_ERR(dev, "destroy gsi qp: failed (rc=%d)\n", rc);
	else
		DP_DEBUG(dev, QEDR_MSG_GSI, "destroy gsi qp: success\n");

	return rc;
}

#define QEDR_MAX_UD_HEADER_SIZE	(100)
#define QEDR_GSI_QPN		(1)
static inline int qedr_gsi_build_header(struct qedr_dev *dev,
					struct qedr_qp *qp,
					struct ib_send_wr *swr,
					struct ib_ud_header *udh,
					int *roce_mode)
{
	bool has_vlan = false, has_grh_ipv6 = true;
	struct rdma_ah_attr *ah_attr = &get_qedr_ah(ud_wr(swr)->ah)->attr;
	const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
	union ib_gid sgid;
	int send_size = 0;
	u16 vlan_id = 0;
	u16 ether_type;
	struct ib_gid_attr sgid_attr;
	int rc;
	int ip_ver = 0;

	bool has_udp = false;
	int i;

	send_size = 0;
	for (i = 0; i < swr->num_sge; ++i)
		send_size += swr->sg_list[i].length;

	rc = ib_get_cached_gid(qp->ibqp.device, rdma_ah_get_port_num(ah_attr),
			       grh->sgid_index, &sgid, &sgid_attr);
	if (rc) {
		DP_ERR(dev,
		       "gsi post send: failed to get cached GID (port=%d, ix=%d)\n",
		       rdma_ah_get_port_num(ah_attr),
		       grh->sgid_index);
		return rc;
	}

	if (sgid_attr.ndev) {
		vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
		if (vlan_id < VLAN_CFI_MASK)
			has_vlan = true;

		dev_put(sgid_attr.ndev);
	}

	if (!memcmp(&sgid, &zgid, sizeof(sgid))) {
		DP_ERR(dev, "gsi post send: GID not found GID index %d\n",
		       grh->sgid_index);
		return -ENOENT;
	}

	has_udp = (sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
	if (!has_udp) {
		/* RoCE v1 */
		ether_type = ETH_P_IBOE;
		*roce_mode = ROCE_V1;
	} else if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
		/* RoCE v2 IPv4 */
		ip_ver = 4;
		ether_type = ETH_P_IP;
		has_grh_ipv6 = false;
		*roce_mode = ROCE_V2_IPV4;
	} else {
		/* RoCE v2 IPv6 */
		ip_ver = 6;
		ether_type = ETH_P_IPV6;
		*roce_mode = ROCE_V2_IPV6;
	}

	rc = ib_ud_header_init(send_size, false, true, has_vlan,
			       has_grh_ipv6, ip_ver, has_udp, 0, udh);
	if (rc) {
		DP_ERR(dev, "gsi post send: failed to init header\n");
		return rc;
	}

	/* ENET + VLAN headers */
	ether_addr_copy(udh->eth.dmac_h, ah_attr->roce.dmac);
	ether_addr_copy(udh->eth.smac_h, dev->ndev->dev_addr);
	if (has_vlan) {
		udh->eth.type = htons(ETH_P_8021Q);
		udh->vlan.tag = htons(vlan_id);
		udh->vlan.type = htons(ether_type);
	} else {
		udh->eth.type = htons(ether_type);
	}

	/* BTH */
	udh->bth.solicited_event = !!(swr->send_flags & IB_SEND_SOLICITED);
	udh->bth.pkey = QEDR_ROCE_PKEY_DEFAULT;
	udh->bth.destination_qpn = htonl(ud_wr(swr)->remote_qpn);
	udh->bth.psn = htonl((qp->sq_psn++) & ((1 << 24) - 1));
	udh->bth.opcode = IB_OPCODE_UD_SEND_ONLY;

	/* DETH */
	udh->deth.qkey = htonl(0x80010000);
	udh->deth.source_qpn = htonl(QEDR_GSI_QPN);

	if (has_grh_ipv6) {
		/* GRH / IPv6 header */
		udh->grh.traffic_class = grh->traffic_class;
		udh->grh.flow_label = grh->flow_label;
		udh->grh.hop_limit = grh->hop_limit;
		udh->grh.destination_gid = grh->dgid;
		memcpy(&udh->grh.source_gid.raw, &sgid.raw,
		       sizeof(udh->grh.source_gid.raw));
	} else {
		/* IPv4 header */
		u32 ipv4_addr;

		udh->ip4.protocol = IPPROTO_UDP;
		udh->ip4.tos = htonl(grh->flow_label);
		udh->ip4.frag_off = htons(IP_DF);
		udh->ip4.ttl = grh->hop_limit;

		ipv4_addr = qedr_get_ipv4_from_gid(sgid.raw);
		udh->ip4.saddr = ipv4_addr;
		ipv4_addr = qedr_get_ipv4_from_gid(grh->dgid.raw);
		udh->ip4.daddr = ipv4_addr;
		/* note: checksum is calculated by the device */
	}

	/* UDP */
	if (has_udp) {
		udh->udp.sport = htons(QEDR_ROCE_V2_UDP_SPORT);
		udh->udp.dport = htons(ROCE_V2_UDP_DPORT);
		udh->udp.csum = 0;
		/* UDP length is untouched hence is zero */
	}
	return 0;
}

static inline int qedr_gsi_build_packet(struct qedr_dev *dev,
					struct qedr_qp *qp,
					struct ib_send_wr *swr,
					struct qed_roce_ll2_packet **p_packet)
{
	u8 ud_header_buffer[QEDR_MAX_UD_HEADER_SIZE];
	struct qed_roce_ll2_packet *packet;
	struct pci_dev *pdev = dev->pdev;
	int roce_mode, header_size;
	struct ib_ud_header udh;
	int i, rc;

	*p_packet = NULL;

	rc = qedr_gsi_build_header(dev, qp, swr, &udh, &roce_mode);
	if (rc)
		return rc;

	header_size = ib_ud_header_pack(&udh, &ud_header_buffer);

	packet = kzalloc(sizeof(*packet), GFP_ATOMIC);
	if (!packet)
		return -ENOMEM;

	packet->header.vaddr = dma_alloc_coherent(&pdev->dev, header_size,
						  &packet->header.baddr,
						  GFP_ATOMIC);
	if (!packet->header.vaddr) {
		kfree(packet);
		return -ENOMEM;
	}

	if (ether_addr_equal(udh.eth.smac_h, udh.eth.dmac_h))
		packet->tx_dest = QED_ROCE_LL2_TX_DEST_LB;
	else
		packet->tx_dest = QED_ROCE_LL2_TX_DEST_NW;

	packet->roce_mode = roce_mode;
	memcpy(packet->header.vaddr, ud_header_buffer, header_size);
	packet->header.len = header_size;
	packet->n_seg = swr->num_sge;
	for (i = 0; i < packet->n_seg; i++) {
		packet->payload[i].baddr = swr->sg_list[i].addr;
		packet->payload[i].len = swr->sg_list[i].length;
	}

	*p_packet = packet;

	return 0;
}

int qedr_gsi_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
		       struct ib_send_wr **bad_wr)
{
	struct qed_roce_ll2_packet *pkt = NULL;
	struct qedr_qp *qp = get_qedr_qp(ibqp);
	struct qed_roce_ll2_tx_params params;
	struct qedr_dev *dev = qp->dev;
	unsigned long flags;
	int rc;

	if (qp->state != QED_ROCE_QP_STATE_RTS) {
		*bad_wr = wr;
		DP_ERR(dev,
		       "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n",
		       qp->state);
		return -EINVAL;
	}

	if (wr->num_sge > RDMA_MAX_SGE_PER_SQ_WQE) {
		DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n",
		       wr->num_sge, RDMA_MAX_SGE_PER_SQ_WQE);
		rc = -EINVAL;
		goto err;
	}

	if (wr->opcode != IB_WR_SEND) {
		DP_ERR(dev,
		       "gsi post send: failed due to unsupported opcode %d\n",
		       wr->opcode);
		rc = -EINVAL;
		goto err;
	}

	memset(&params, 0, sizeof(params));

	spin_lock_irqsave(&qp->q_lock, flags);

	rc = qedr_gsi_build_packet(dev, qp, wr, &pkt);
	if (rc) {
		spin_unlock_irqrestore(&qp->q_lock, flags);
		goto err;
	}

	rc = dev->ops->roce_ll2_tx(dev->cdev, pkt, &params);
	if (!rc) {
		qp->wqe_wr_id[qp->sq.prod].wr_id = wr->wr_id;
		qedr_inc_sw_prod(&qp->sq);
		DP_DEBUG(qp->dev, QEDR_MSG_GSI,
			 "gsi post send: opcode=%d, in_irq=%ld, irqs_disabled=%d, wr_id=%llx\n",
			 wr->opcode, in_irq(), irqs_disabled(), wr->wr_id);
	} else {
		if (rc == QED_ROCE_TX_HEAD_FAILURE) {
			/* TX failed while posting header - release resources */
			dma_free_coherent(&dev->pdev->dev, pkt->header.len,
					  pkt->header.vaddr, pkt->header.baddr);
			kfree(pkt);
		} else if (rc == QED_ROCE_TX_FRAG_FAILURE) {
			/* NTD since TX failed while posting a fragment. We will
			 * release the resources on TX callback
			 */
		}

		DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc);
		rc = -EAGAIN;
		*bad_wr = wr;
	}

	spin_unlock_irqrestore(&qp->q_lock, flags);

	if (wr->next) {
		DP_ERR(dev,
		       "gsi post send: failed second WR. Only one WR may be passed at a time\n");
		*bad_wr = wr->next;
		rc = -EINVAL;
	}

	return rc;

err:
	*bad_wr = wr;
	return rc;
}

int qedr_gsi_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
		       struct ib_recv_wr **bad_wr)
{
	struct qedr_dev *dev = get_qedr_dev(ibqp->device);
	struct qedr_qp *qp = get_qedr_qp(ibqp);
	struct qed_roce_ll2_buffer buf;
	unsigned long flags;
	int status = 0;
	int rc;

	if ((qp->state != QED_ROCE_QP_STATE_RTR) &&
	    (qp->state != QED_ROCE_QP_STATE_RTS)) {
		*bad_wr = wr;
		DP_ERR(dev,
		       "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n",
		       qp->state);
		return -EINVAL;
	}

	memset(&buf, 0, sizeof(buf));

	spin_lock_irqsave(&qp->q_lock, flags);

	while (wr) {
		if (wr->num_sge > QEDR_GSI_MAX_RECV_SGE) {
			DP_ERR(dev,
			       "gsi post recv: failed to post rx buffer. too many sges %d>%d\n",
			       wr->num_sge, QEDR_GSI_MAX_RECV_SGE);
			goto err;
		}

		buf.baddr = wr->sg_list[0].addr;
		buf.len = wr->sg_list[0].length;

		rc = dev->ops->roce_ll2_post_rx_buffer(dev->cdev, &buf, 0, 1);
		if (rc) {
			DP_ERR(dev,
			       "gsi post recv: failed to post rx buffer (rc=%d)\n",
			       rc);
			goto err;
		}

		memset(&qp->rqe_wr_id[qp->rq.prod], 0,
		       sizeof(qp->rqe_wr_id[qp->rq.prod]));
		qp->rqe_wr_id[qp->rq.prod].sg_list[0] = wr->sg_list[0];
		qp->rqe_wr_id[qp->rq.prod].wr_id = wr->wr_id;

		qedr_inc_sw_prod(&qp->rq);

		wr = wr->next;
	}

	spin_unlock_irqrestore(&qp->q_lock, flags);

	return status;
err:
	spin_unlock_irqrestore(&qp->q_lock, flags);
	*bad_wr = wr;
	return -ENOMEM;
}

int qedr_gsi_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
{
	struct qedr_dev *dev = get_qedr_dev(ibcq->device);
	struct qedr_cq *cq = get_qedr_cq(ibcq);
	struct qedr_qp *qp = dev->gsi_qp;
	unsigned long flags;
	int i = 0;

	spin_lock_irqsave(&cq->cq_lock, flags);

	while (i < num_entries && qp->rq.cons != qp->rq.gsi_cons) {
		memset(&wc[i], 0, sizeof(*wc));

		wc[i].qp = &qp->ibqp;
		wc[i].wr_id = qp->rqe_wr_id[qp->rq.cons].wr_id;
		wc[i].opcode = IB_WC_RECV;
		wc[i].pkey_index = 0;
		wc[i].status = (qp->rqe_wr_id[qp->rq.cons].rc) ?
		    IB_WC_GENERAL_ERR : IB_WC_SUCCESS;
		/* 0 - currently only one recv sg is supported */
		wc[i].byte_len = qp->rqe_wr_id[qp->rq.cons].sg_list[0].length;
		wc[i].wc_flags |= IB_WC_GRH | IB_WC_IP_CSUM_OK;
		ether_addr_copy(wc[i].smac, qp->rqe_wr_id[qp->rq.cons].smac);
		wc[i].wc_flags |= IB_WC_WITH_SMAC;
		if (qp->rqe_wr_id[qp->rq.cons].vlan_id) {
			wc[i].wc_flags |= IB_WC_WITH_VLAN;
			wc[i].vlan_id = qp->rqe_wr_id[qp->rq.cons].vlan_id;
		}

		qedr_inc_sw_cons(&qp->rq);
		i++;
	}

	while (i < num_entries && qp->sq.cons != qp->sq.gsi_cons) {
		memset(&wc[i], 0, sizeof(*wc));

		wc[i].qp = &qp->ibqp;
		wc[i].wr_id = qp->wqe_wr_id[qp->sq.cons].wr_id;
		wc[i].opcode = IB_WC_SEND;
		wc[i].status = IB_WC_SUCCESS;

		qedr_inc_sw_cons(&qp->sq);
		i++;
	}

	spin_unlock_irqrestore(&cq->cq_lock, flags);

	DP_DEBUG(dev, QEDR_MSG_GSI,
		 "gsi poll_cq: requested entries=%d, actual=%d, qp->rq.cons=%d, qp->rq.gsi_cons=%x, qp->sq.cons=%d, qp->sq.gsi_cons=%d, qp_num=%d\n",
		 num_entries, i, qp->rq.cons, qp->rq.gsi_cons, qp->sq.cons,
		 qp->sq.gsi_cons, qp->ibqp.qp_num);

	return i;
}
Commit	Line	Data
04886779 RA	1	/* QLogic qedr NIC Driver
	2	* Copyright (c) 2015-2016 QLogic Corporation
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and /or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32	#include <linux/dma-mapping.h>
	33	#include <linux/crc32.h>
	34	#include <linux/iommu.h>
	35	#include <net/ip.h>
	36	#include <net/ipv6.h>
	37	#include <net/udp.h>
	38
	39	#include <rdma/ib_verbs.h>
	40	#include <rdma/ib_user_verbs.h>
	41	#include <rdma/iw_cm.h>
	42	#include <rdma/ib_umem.h>
	43	#include <rdma/ib_addr.h>
	44	#include <rdma/ib_cache.h>
	45
04886779 RA	46	#include <linux/qed/qed_if.h>
	47	#include <linux/qed/qed_roce_if.h>
	48	#include "qedr.h"
04886779 RA	49	#include "verbs.h"
04886779 RA	50	#include <rdma/qedr-abi.h>
04886779 RA	51	#include "qedr_cm.h"
	52
	53	void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info)
	54	{
	55	info->gsi_cons = (info->gsi_cons + 1) % info->max_wr;
	56	}
	57
	58	void qedr_store_gsi_qp_cq(struct qedr_dev dev, struct qedr_qp qp,
	59	struct ib_qp_init_attr *attrs)
	60	{
	61	dev->gsi_qp_created = 1;
	62	dev->gsi_sqcq = get_qedr_cq(attrs->send_cq);
	63	dev->gsi_rqcq = get_qedr_cq(attrs->recv_cq);
	64	dev->gsi_qp = qp;
	65	}
	66
	67	void qedr_ll2_tx_cb(void _qdev, struct qed_roce_ll2_packet pkt)
	68	{
	69	struct qedr_dev dev = (struct qedr_dev )_qdev;
	70	struct qedr_cq *cq = dev->gsi_sqcq;
	71	struct qedr_qp *qp = dev->gsi_qp;
	72	unsigned long flags;
	73
	74	DP_DEBUG(dev, QEDR_MSG_GSI,
	75	"LL2 TX CB: gsi_sqcq=%p, gsi_rqcq=%p, gsi_cons=%d, ibcq_comp=%s\n",
	76	dev->gsi_sqcq, dev->gsi_rqcq, qp->sq.gsi_cons,
	77	cq->ibcq.comp_handler ? "Yes" : "No");
	78
	79	dma_free_coherent(&dev->pdev->dev, pkt->header.len, pkt->header.vaddr,
	80	pkt->header.baddr);
	81	kfree(pkt);
	82
	83	spin_lock_irqsave(&qp->q_lock, flags);
	84	qedr_inc_sw_gsi_cons(&qp->sq);
	85	spin_unlock_irqrestore(&qp->q_lock, flags);
	86
91bff997	87	if (cq->ibcq.comp_handler)
04886779	88	(*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
04886779 RA	89	}
	90
	91	void qedr_ll2_rx_cb(void _dev, struct qed_roce_ll2_packet pkt,
	92	struct qed_roce_ll2_rx_params *params)
	93	{
	94	struct qedr_dev dev = (struct qedr_dev )_dev;
	95	struct qedr_cq *cq = dev->gsi_rqcq;
	96	struct qedr_qp *qp = dev->gsi_qp;
	97	unsigned long flags;
	98
	99	spin_lock_irqsave(&qp->q_lock, flags);
	100
	101	qp->rqe_wr_id[qp->rq.gsi_cons].rc = params->rc;
	102	qp->rqe_wr_id[qp->rq.gsi_cons].vlan_id = params->vlan_id;
	103	qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length = pkt->payload[0].len;
	104	ether_addr_copy(qp->rqe_wr_id[qp->rq.gsi_cons].smac, params->smac);
	105
	106	qedr_inc_sw_gsi_cons(&qp->rq);
	107
	108	spin_unlock_irqrestore(&qp->q_lock, flags);
	109
91bff997	110	if (cq->ibcq.comp_handler)
04886779	111	(*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
04886779 RA	112	}
	113
	114	static void qedr_destroy_gsi_cq(struct qedr_dev *dev,
	115	struct ib_qp_init_attr *attrs)
	116	{
	117	struct qed_rdma_destroy_cq_in_params iparams;
	118	struct qed_rdma_destroy_cq_out_params oparams;
	119	struct qedr_cq *cq;
	120
	121	cq = get_qedr_cq(attrs->send_cq);
	122	iparams.icid = cq->icid;
	123	dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
	124	dev->ops->common->chain_free(dev->cdev, &cq->pbl);
	125
	126	cq = get_qedr_cq(attrs->recv_cq);
	127	/* if a dedicated recv_cq was used, delete it too */
	128	if (iparams.icid != cq->icid) {
	129	iparams.icid = cq->icid;
	130	dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
	131	dev->ops->common->chain_free(dev->cdev, &cq->pbl);
	132	}
	133	}
	134
	135	static inline int qedr_check_gsi_qp_attrs(struct qedr_dev *dev,
	136	struct ib_qp_init_attr *attrs)
	137	{
	138	if (attrs->cap.max_recv_sge > QEDR_GSI_MAX_RECV_SGE) {
	139	DP_ERR(dev,
	140	" create gsi qp: failed. max_recv_sge is larger the max %d>%d\n",
	141	attrs->cap.max_recv_sge, QEDR_GSI_MAX_RECV_SGE);
	142	return -EINVAL;
	143	}
	144
	145	if (attrs->cap.max_recv_wr > QEDR_GSI_MAX_RECV_WR) {
	146	DP_ERR(dev,
	147	" create gsi qp: failed. max_recv_wr is too large %d>%d\n",
	148	attrs->cap.max_recv_wr, QEDR_GSI_MAX_RECV_WR);
	149	return -EINVAL;
	150	}
	151
	152	if (attrs->cap.max_send_wr > QEDR_GSI_MAX_SEND_WR) {
	153	DP_ERR(dev,
	154	" create gsi qp: failed. max_send_wr is too large %d>%d\n",
	155	attrs->cap.max_send_wr, QEDR_GSI_MAX_SEND_WR);
	156	return -EINVAL;
	157	}
	158
	159	return 0;
	160	}
	161
	162	struct ib_qp qedr_create_gsi_qp(struct qedr_dev dev,
	163	struct ib_qp_init_attr *attrs,
	164	struct qedr_qp *qp)
	165	{
	166	struct qed_roce_ll2_params ll2_params;
	167	int rc;
	168
	169	rc = qedr_check_gsi_qp_attrs(dev, attrs);
	170	if (rc)
	171	return ERR_PTR(rc);
	172
	173	/* configure and start LL2 */
	174	memset(&ll2_params, 0, sizeof(ll2_params));
	175	ll2_params.max_tx_buffers = attrs->cap.max_send_wr;
176	ll2_params.max_rx_buffers = attrs->cap.max_recv_wr;
177	ll2_params.cbs.tx_cb = qedr_ll2_tx_cb;
178	ll2_params.cbs.rx_cb = qedr_ll2_rx_cb;
179	ll2_params.cb_cookie = (void *)dev;
180	ll2_params.mtu = dev->ndev->mtu;
181	ether_addr_copy(ll2_params.mac_address, dev->ndev->dev_addr);
182	rc = dev->ops->roce_ll2_start(dev->cdev, &ll2_params);
183	if (rc) {
184	DP_ERR(dev, "create gsi qp: failed on ll2 start. rc=%d\n", rc);
185	return ERR_PTR(rc);
186	}
187
188	/* create QP */
189	qp->ibqp.qp_num = 1;
190	qp->rq.max_wr = attrs->cap.max_recv_wr;
191	qp->sq.max_wr = attrs->cap.max_send_wr;
192
193	qp->rqe_wr_id = kcalloc(qp->rq.max_wr, sizeof(*qp->rqe_wr_id),
194	GFP_KERNEL);
195	if (!qp->rqe_wr_id)
196	goto err;
197	qp->wqe_wr_id = kcalloc(qp->sq.max_wr, sizeof(*qp->wqe_wr_id),
198	GFP_KERNEL);
199	if (!qp->wqe_wr_id)
200	goto err;
201
202	qedr_store_gsi_qp_cq(dev, qp, attrs);
203	ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
204
205	/* the GSI CQ is handled by the driver so remove it from the FW */
206	qedr_destroy_gsi_cq(dev, attrs);
207	dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
208	dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
209
210	DP_DEBUG(dev, QEDR_MSG_GSI, "created GSI QP %p\n", qp);
211
212	return &qp->ibqp;
213
214	err:
215	kfree(qp->rqe_wr_id);
216
217	rc = dev->ops->roce_ll2_stop(dev->cdev);
218	if (rc)
219	DP_ERR(dev, "create gsi qp: failed destroy on create\n");
220
221	return ERR_PTR(-ENOMEM);
222	}
223
224	int qedr_destroy_gsi_qp(struct qedr_dev *dev)
225	{
226	int rc;
227
228	rc = dev->ops->roce_ll2_stop(dev->cdev);
229	if (rc)
230	DP_ERR(dev, "destroy gsi qp: failed (rc=%d)\n", rc);
231	else
232	DP_DEBUG(dev, QEDR_MSG_GSI, "destroy gsi qp: success\n");
233
234	return rc;
235	}
236
237	#define QEDR_MAX_UD_HEADER_SIZE (100)
238	#define QEDR_GSI_QPN (1)
239	static inline int qedr_gsi_build_header(struct qedr_dev *dev,
240	struct qedr_qp *qp,
241	struct ib_send_wr *swr,
242	struct ib_ud_header *udh,
243	int *roce_mode)
244	{
245	bool has_vlan = false, has_grh_ipv6 = true;
90898850	246	struct rdma_ah_attr *ah_attr = &get_qedr_ah(ud_wr(swr)->ah)->attr;
d8966fcd	247	const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
04886779 RA	248	union ib_gid sgid;
	249	int send_size = 0;
	250	u16 vlan_id = 0;
	251	u16 ether_type;
	252	struct ib_gid_attr sgid_attr;
	253	int rc;
	254	int ip_ver = 0;
	255
	256	bool has_udp = false;
	257	int i;
	258
	259	send_size = 0;
	260	for (i = 0; i < swr->num_sge; ++i)
	261	send_size += swr->sg_list[i].length;
	262
d8966fcd	263	rc = ib_get_cached_gid(qp->ibqp.device, rdma_ah_get_port_num(ah_attr),
04886779 RA	264	grh->sgid_index, &sgid, &sgid_attr);
	265	if (rc) {
	266	DP_ERR(dev,
	267	"gsi post send: failed to get cached GID (port=%d, ix=%d)\n",
d8966fcd DC	268	rdma_ah_get_port_num(ah_attr),
d8966fcd DC	269	grh->sgid_index);
04886779 RA	270	return rc;
	271	}
	272
d38d7fda GS	273	if (sgid_attr.ndev) {
	274	vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
	275	if (vlan_id < VLAN_CFI_MASK)
	276	has_vlan = true;
	277
04886779	278	dev_put(sgid_attr.ndev);
d38d7fda	279	}
04886779 RA	280
	281	if (!memcmp(&sgid, &zgid, sizeof(sgid))) {
	282	DP_ERR(dev, "gsi post send: GID not found GID index %d\n",
d8966fcd	283	grh->sgid_index);
04886779 RA	284	return -ENOENT;
	285	}
	286
	287	has_udp = (sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
	288	if (!has_udp) {
	289	/* RoCE v1 */
69ae5439	290	ether_type = ETH_P_IBOE;
04886779 RA	291	*roce_mode = ROCE_V1;
	292	} else if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
	293	/* RoCE v2 IPv4 */
	294	ip_ver = 4;
	295	ether_type = ETH_P_IP;
	296	has_grh_ipv6 = false;
	297	*roce_mode = ROCE_V2_IPV4;
	298	} else {
	299	/* RoCE v2 IPv6 */
	300	ip_ver = 6;
	301	ether_type = ETH_P_IPV6;
	302	*roce_mode = ROCE_V2_IPV6;
	303	}
	304
	305	rc = ib_ud_header_init(send_size, false, true, has_vlan,
	306	has_grh_ipv6, ip_ver, has_udp, 0, udh);
	307	if (rc) {
	308	DP_ERR(dev, "gsi post send: failed to init header\n");
	309	return rc;
	310	}
	311
	312	/* ENET + VLAN headers */
44c58487	313	ether_addr_copy(udh->eth.dmac_h, ah_attr->roce.dmac);
04886779 RA	314	ether_addr_copy(udh->eth.smac_h, dev->ndev->dev_addr);
	315	if (has_vlan) {
	316	udh->eth.type = htons(ETH_P_8021Q);
	317	udh->vlan.tag = htons(vlan_id);
	318	udh->vlan.type = htons(ether_type);
	319	} else {
	320	udh->eth.type = htons(ether_type);
	321	}
	322
	323	/* BTH */
	324	udh->bth.solicited_event = !!(swr->send_flags & IB_SEND_SOLICITED);
	325	udh->bth.pkey = QEDR_ROCE_PKEY_DEFAULT;
	326	udh->bth.destination_qpn = htonl(ud_wr(swr)->remote_qpn);
	327	udh->bth.psn = htonl((qp->sq_psn++) & ((1 << 24) - 1));
	328	udh->bth.opcode = IB_OPCODE_UD_SEND_ONLY;
	329
	330	/* DETH */
	331	udh->deth.qkey = htonl(0x80010000);
	332	udh->deth.source_qpn = htonl(QEDR_GSI_QPN);
	333
	334	if (has_grh_ipv6) {
	335	/* GRH / IPv6 header */
	336	udh->grh.traffic_class = grh->traffic_class;
	337	udh->grh.flow_label = grh->flow_label;
	338	udh->grh.hop_limit = grh->hop_limit;
	339	udh->grh.destination_gid = grh->dgid;
	340	memcpy(&udh->grh.source_gid.raw, &sgid.raw,
	341	sizeof(udh->grh.source_gid.raw));
	342	} else {
	343	/* IPv4 header */
	344	u32 ipv4_addr;
	345
	346	udh->ip4.protocol = IPPROTO_UDP;
d8966fcd	347	udh->ip4.tos = htonl(grh->flow_label);
04886779	348	udh->ip4.frag_off = htons(IP_DF);
d8966fcd	349	udh->ip4.ttl = grh->hop_limit;
04886779 RA	350
	351	ipv4_addr = qedr_get_ipv4_from_gid(sgid.raw);
	352	udh->ip4.saddr = ipv4_addr;
d8966fcd	353	ipv4_addr = qedr_get_ipv4_from_gid(grh->dgid.raw);
04886779 RA	354	udh->ip4.daddr = ipv4_addr;
	355	/* note: checksum is calculated by the device */
	356	}
	357
	358	/* UDP */
	359	if (has_udp) {
	360	udh->udp.sport = htons(QEDR_ROCE_V2_UDP_SPORT);
	361	udh->udp.dport = htons(ROCE_V2_UDP_DPORT);
	362	udh->udp.csum = 0;
	363	/* UDP length is untouched hence is zero */
	364	}
	365	return 0;
	366	}
	367
	368	static inline int qedr_gsi_build_packet(struct qedr_dev *dev,
	369	struct qedr_qp *qp,
	370	struct ib_send_wr *swr,
	371	struct qed_roce_ll2_packet **p_packet)
	372	{
	373	u8 ud_header_buffer[QEDR_MAX_UD_HEADER_SIZE];
	374	struct qed_roce_ll2_packet *packet;
	375	struct pci_dev *pdev = dev->pdev;
	376	int roce_mode, header_size;
	377	struct ib_ud_header udh;
	378	int i, rc;
	379
	380	*p_packet = NULL;
	381
	382	rc = qedr_gsi_build_header(dev, qp, swr, &udh, &roce_mode);
	383	if (rc)
	384	return rc;
	385
	386	header_size = ib_ud_header_pack(&udh, &ud_header_buffer);
	387
	388	packet = kzalloc(sizeof(*packet), GFP_ATOMIC);
	389	if (!packet)
	390	return -ENOMEM;
	391
	392	packet->header.vaddr = dma_alloc_coherent(&pdev->dev, header_size,
	393	&packet->header.baddr,
	394	GFP_ATOMIC);
	395	if (!packet->header.vaddr) {
	396	kfree(packet);
	397	return -ENOMEM;
	398	}
	399
	400	if (ether_addr_equal(udh.eth.smac_h, udh.eth.dmac_h))
04886779	401	packet->tx_dest = QED_ROCE_LL2_TX_DEST_LB;
af2b14b8 RA	402	else
af2b14b8 RA	403	packet->tx_dest = QED_ROCE_LL2_TX_DEST_NW;
04886779 RA	404
	405	packet->roce_mode = roce_mode;
	406	memcpy(packet->header.vaddr, ud_header_buffer, header_size);
	407	packet->header.len = header_size;
	408	packet->n_seg = swr->num_sge;
	409	for (i = 0; i < packet->n_seg; i++) {
	410	packet->payload[i].baddr = swr->sg_list[i].addr;
	411	packet->payload[i].len = swr->sg_list[i].length;
	412	}
	413
	414	*p_packet = packet;
	415
	416	return 0;
	417	}
	418
	419	int qedr_gsi_post_send(struct ib_qp ibqp, struct ib_send_wr wr,
	420	struct ib_send_wr **bad_wr)
	421	{
	422	struct qed_roce_ll2_packet *pkt = NULL;
	423	struct qedr_qp *qp = get_qedr_qp(ibqp);
	424	struct qed_roce_ll2_tx_params params;
	425	struct qedr_dev *dev = qp->dev;
	426	unsigned long flags;
	427	int rc;
	428
	429	if (qp->state != QED_ROCE_QP_STATE_RTS) {
	430	*bad_wr = wr;
	431	DP_ERR(dev,
	432	"gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n",
	433	qp->state);
	434	return -EINVAL;
	435	}
	436
	437	if (wr->num_sge > RDMA_MAX_SGE_PER_SQ_WQE) {
	438	DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n",
	439	wr->num_sge, RDMA_MAX_SGE_PER_SQ_WQE);
	440	rc = -EINVAL;
	441	goto err;
	442	}
	443
	444	if (wr->opcode != IB_WR_SEND) {
	445	DP_ERR(dev,
	446	"gsi post send: failed due to unsupported opcode %d\n",
	447	wr->opcode);
	448	rc = -EINVAL;
	449	goto err;
	450	}
	451
	452	memset(&params, 0, sizeof(params));
	453
	454	spin_lock_irqsave(&qp->q_lock, flags);
	455
	456	rc = qedr_gsi_build_packet(dev, qp, wr, &pkt);
	457	if (rc) {
	458	spin_unlock_irqrestore(&qp->q_lock, flags);
	459	goto err;
	460	}
	461
	462	rc = dev->ops->roce_ll2_tx(dev->cdev, pkt, &params);
	463	if (!rc) {
	464	qp->wqe_wr_id[qp->sq.prod].wr_id = wr->wr_id;
	465	qedr_inc_sw_prod(&qp->sq);
	466	DP_DEBUG(qp->dev, QEDR_MSG_GSI,
	467	"gsi post send: opcode=%d, in_irq=%ld, irqs_disabled=%d, wr_id=%llx\n",
468	wr->opcode, in_irq(), irqs_disabled(), wr->wr_id);
469	} else {
470	if (rc == QED_ROCE_TX_HEAD_FAILURE) {
471	/* TX failed while posting header - release resources */
472	dma_free_coherent(&dev->pdev->dev, pkt->header.len,
473	pkt->header.vaddr, pkt->header.baddr);
474	kfree(pkt);
475	} else if (rc == QED_ROCE_TX_FRAG_FAILURE) {
476	/* NTD since TX failed while posting a fragment. We will
477	* release the resources on TX callback
478	*/
479	}
480
481	DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc);
482	rc = -EAGAIN;
483	*bad_wr = wr;
484	}
485
486	spin_unlock_irqrestore(&qp->q_lock, flags);
487
488	if (wr->next) {
489	DP_ERR(dev,
490	"gsi post send: failed second WR. Only one WR may be passed at a time\n");
491	*bad_wr = wr->next;
492	rc = -EINVAL;
493	}
494
495	return rc;
496
497	err:
498	*bad_wr = wr;
499	return rc;
500	}
501
502	int qedr_gsi_post_recv(struct ib_qp ibqp, struct ib_recv_wr wr,
503	struct ib_recv_wr **bad_wr)
504	{
505	struct qedr_dev *dev = get_qedr_dev(ibqp->device);
506	struct qedr_qp *qp = get_qedr_qp(ibqp);
507	struct qed_roce_ll2_buffer buf;
508	unsigned long flags;
509	int status = 0;
510	int rc;
511
512	if ((qp->state != QED_ROCE_QP_STATE_RTR) &&
513	(qp->state != QED_ROCE_QP_STATE_RTS)) {
514	*bad_wr = wr;
515	DP_ERR(dev,
516	"gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n",
517	qp->state);
518	return -EINVAL;
519	}
520
521	memset(&buf, 0, sizeof(buf));
522
523	spin_lock_irqsave(&qp->q_lock, flags);
524
525	while (wr) {
526	if (wr->num_sge > QEDR_GSI_MAX_RECV_SGE) {
527	DP_ERR(dev,
528	"gsi post recv: failed to post rx buffer. too many sges %d>%d\n",
529	wr->num_sge, QEDR_GSI_MAX_RECV_SGE);
530	goto err;
531	}
532
533	buf.baddr = wr->sg_list[0].addr;
534	buf.len = wr->sg_list[0].length;
535
536	rc = dev->ops->roce_ll2_post_rx_buffer(dev->cdev, &buf, 0, 1);
537	if (rc) {
538	DP_ERR(dev,
539	"gsi post recv: failed to post rx buffer (rc=%d)\n",
540	rc);
541	goto err;
542	}
543
544	memset(&qp->rqe_wr_id[qp->rq.prod], 0,
545	sizeof(qp->rqe_wr_id[qp->rq.prod]));
546	qp->rqe_wr_id[qp->rq.prod].sg_list[0] = wr->sg_list[0];
547	qp->rqe_wr_id[qp->rq.prod].wr_id = wr->wr_id;
548
549	qedr_inc_sw_prod(&qp->rq);
550
551	wr = wr->next;
552	}
553
554	spin_unlock_irqrestore(&qp->q_lock, flags);
555
556	return status;
557	err:
558	spin_unlock_irqrestore(&qp->q_lock, flags);
559	*bad_wr = wr;
560	return -ENOMEM;
561	}
562
563	int qedr_gsi_poll_cq(struct ib_cq ibcq, int num_entries, struct ib_wc wc)
564	{
565	struct qedr_dev *dev = get_qedr_dev(ibcq->device);
566	struct qedr_cq *cq = get_qedr_cq(ibcq);
567	struct qedr_qp *qp = dev->gsi_qp;
568	unsigned long flags;
569	int i = 0;
570
571	spin_lock_irqsave(&cq->cq_lock, flags);
572
573	while (i < num_entries && qp->rq.cons != qp->rq.gsi_cons) {
574	memset(&wc[i], 0, sizeof(*wc));
575
576	wc[i].qp = &qp->ibqp;
577	wc[i].wr_id = qp->rqe_wr_id[qp->rq.cons].wr_id;
578	wc[i].opcode = IB_WC_RECV;
579	wc[i].pkey_index = 0;
580	wc[i].status = (qp->rqe_wr_id[qp->rq.cons].rc) ?
581	IB_WC_GENERAL_ERR : IB_WC_SUCCESS;
582	/* 0 - currently only one recv sg is supported */
583	wc[i].byte_len = qp->rqe_wr_id[qp->rq.cons].sg_list[0].length;
584	wc[i].wc_flags \|= IB_WC_GRH \| IB_WC_IP_CSUM_OK;
585	ether_addr_copy(wc[i].smac, qp->rqe_wr_id[qp->rq.cons].smac);
586	wc[i].wc_flags \|= IB_WC_WITH_SMAC;
587	if (qp->rqe_wr_id[qp->rq.cons].vlan_id) {
588	wc[i].wc_flags \|= IB_WC_WITH_VLAN;
589	wc[i].vlan_id = qp->rqe_wr_id[qp->rq.cons].vlan_id;
590	}
591
592	qedr_inc_sw_cons(&qp->rq);
593	i++;
594	}
595
596	while (i < num_entries && qp->sq.cons != qp->sq.gsi_cons) {
597	memset(&wc[i], 0, sizeof(*wc));
598
599	wc[i].qp = &qp->ibqp;
600	wc[i].wr_id = qp->wqe_wr_id[qp->sq.cons].wr_id;
601	wc[i].opcode = IB_WC_SEND;
602	wc[i].status = IB_WC_SUCCESS;
603
604	qedr_inc_sw_cons(&qp->sq);
605	i++;
606	}
607
608	spin_unlock_irqrestore(&cq->cq_lock, flags);
609
610	DP_DEBUG(dev, QEDR_MSG_GSI,
611	"gsi poll_cq: requested entries=%d, actual=%d, qp->rq.cons=%d, qp->rq.gsi_cons=%x, qp->sq.cons=%d, qp->sq.gsi_cons=%d, qp_num=%d\n",
612	num_entries, i, qp->rq.cons, qp->rq.gsi_cons, qp->sq.cons,
613	qp->sq.gsi_cons, qp->ibqp.qp_num);
614
615	return i;
616	}