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f931551b | 1 | /* |
ecd4b48a BH |
2 | * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation. |
3 | * All rights reserved. | |
f931551b RC |
4 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | /* | |
35 | * This file contains all of the code that is specific to the SerDes | |
36 | * on the QLogic_IB 7220 chip. | |
37 | */ | |
38 | ||
39 | #include <linux/pci.h> | |
40 | #include <linux/delay.h> | |
ecd4b48a | 41 | #include <linux/firmware.h> |
f931551b RC |
42 | |
43 | #include "qib.h" | |
44 | #include "qib_7220.h" | |
45 | ||
ecd4b48a BH |
46 | #define SD7220_FW_NAME "qlogic/sd7220.fw" |
47 | MODULE_FIRMWARE(SD7220_FW_NAME); | |
48 | ||
f931551b RC |
49 | /* |
50 | * Same as in qib_iba7220.c, but just the registers needed here. | |
51 | * Could move whole set to qib_7220.h, but decided better to keep | |
52 | * local. | |
53 | */ | |
54 | #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64)) | |
55 | #define kr_hwerrclear KREG_IDX(HwErrClear) | |
56 | #define kr_hwerrmask KREG_IDX(HwErrMask) | |
57 | #define kr_hwerrstatus KREG_IDX(HwErrStatus) | |
58 | #define kr_ibcstatus KREG_IDX(IBCStatus) | |
59 | #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl) | |
60 | #define kr_scratch KREG_IDX(Scratch) | |
61 | #define kr_xgxs_cfg KREG_IDX(XGXSCfg) | |
62 | /* these are used only here, not in qib_iba7220.c */ | |
63 | #define kr_ibsd_epb_access_ctrl KREG_IDX(ibsd_epb_access_ctrl) | |
64 | #define kr_ibsd_epb_transaction_reg KREG_IDX(ibsd_epb_transaction_reg) | |
65 | #define kr_pciesd_epb_transaction_reg KREG_IDX(pciesd_epb_transaction_reg) | |
66 | #define kr_pciesd_epb_access_ctrl KREG_IDX(pciesd_epb_access_ctrl) | |
67 | #define kr_serdes_ddsrxeq0 KREG_IDX(SerDes_DDSRXEQ0) | |
68 | ||
69 | /* | |
70 | * The IBSerDesMappTable is a memory that holds values to be stored in | |
71 | * various SerDes registers by IBC. | |
72 | */ | |
73 | #define kr_serdes_maptable KREG_IDX(IBSerDesMappTable) | |
74 | ||
75 | /* | |
76 | * Below used for sdnum parameter, selecting one of the two sections | |
77 | * used for PCIe, or the single SerDes used for IB. | |
78 | */ | |
79 | #define PCIE_SERDES0 0 | |
80 | #define PCIE_SERDES1 1 | |
81 | ||
82 | /* | |
83 | * The EPB requires addressing in a particular form. EPB_LOC() is intended | |
84 | * to make #definitions a little more readable. | |
85 | */ | |
86 | #define EPB_ADDR_SHF 8 | |
87 | #define EPB_LOC(chn, elt, reg) \ | |
88 | (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \ | |
89 | EPB_ADDR_SHF) | |
90 | #define EPB_IB_QUAD0_CS_SHF (25) | |
91 | #define EPB_IB_QUAD0_CS (1U << EPB_IB_QUAD0_CS_SHF) | |
92 | #define EPB_IB_UC_CS_SHF (26) | |
93 | #define EPB_PCIE_UC_CS_SHF (27) | |
94 | #define EPB_GLOBAL_WR (1U << (EPB_ADDR_SHF + 8)) | |
95 | ||
96 | /* Forward declarations. */ | |
97 | static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc, | |
98 | u32 data, u32 mask); | |
99 | static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, | |
100 | int mask); | |
101 | static int qib_sd_trimdone_poll(struct qib_devdata *dd); | |
102 | static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where); | |
103 | static int qib_sd_setvals(struct qib_devdata *dd); | |
104 | static int qib_sd_early(struct qib_devdata *dd); | |
105 | static int qib_sd_dactrim(struct qib_devdata *dd); | |
106 | static int qib_internal_presets(struct qib_devdata *dd); | |
107 | /* Tweak the register (CMUCTRL5) that contains the TRIMSELF controls */ | |
108 | static int qib_sd_trimself(struct qib_devdata *dd, int val); | |
109 | static int epb_access(struct qib_devdata *dd, int sdnum, int claim); | |
ecd4b48a BH |
110 | static int qib_sd7220_ib_load(struct qib_devdata *dd, |
111 | const struct firmware *fw); | |
112 | static int qib_sd7220_ib_vfy(struct qib_devdata *dd, | |
113 | const struct firmware *fw); | |
f931551b RC |
114 | |
115 | /* | |
116 | * Below keeps track of whether the "once per power-on" initialization has | |
117 | * been done, because uC code Version 1.32.17 or higher allows the uC to | |
118 | * be reset at will, and Automatic Equalization may require it. So the | |
119 | * state of the reset "pin", is no longer valid. Instead, we check for the | |
120 | * actual uC code having been loaded. | |
121 | */ | |
ecd4b48a BH |
122 | static int qib_ibsd_ucode_loaded(struct qib_pportdata *ppd, |
123 | const struct firmware *fw) | |
f931551b RC |
124 | { |
125 | struct qib_devdata *dd = ppd->dd; | |
ecd4b48a BH |
126 | |
127 | if (!dd->cspec->serdes_first_init_done && | |
128 | qib_sd7220_ib_vfy(dd, fw) > 0) | |
f931551b RC |
129 | dd->cspec->serdes_first_init_done = 1; |
130 | return dd->cspec->serdes_first_init_done; | |
131 | } | |
132 | ||
133 | /* repeat #define for local use. "Real" #define is in qib_iba7220.c */ | |
134 | #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL | |
135 | #define IB_MPREG5 (EPB_LOC(6, 0, 0xE) | (1L << EPB_IB_UC_CS_SHF)) | |
136 | #define IB_MPREG6 (EPB_LOC(6, 0, 0xF) | (1U << EPB_IB_UC_CS_SHF)) | |
137 | #define UC_PAR_CLR_D 8 | |
138 | #define UC_PAR_CLR_M 0xC | |
139 | #define IB_CTRL2(chn) (EPB_LOC(chn, 7, 3) | EPB_IB_QUAD0_CS) | |
140 | #define START_EQ1(chan) EPB_LOC(chan, 7, 0x27) | |
141 | ||
142 | void qib_sd7220_clr_ibpar(struct qib_devdata *dd) | |
143 | { | |
144 | int ret; | |
145 | ||
146 | /* clear, then re-enable parity errs */ | |
147 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, | |
148 | UC_PAR_CLR_D, UC_PAR_CLR_M); | |
149 | if (ret < 0) { | |
150 | qib_dev_err(dd, "Failed clearing IBSerDes Parity err\n"); | |
151 | goto bail; | |
152 | } | |
153 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0, | |
154 | UC_PAR_CLR_M); | |
155 | ||
156 | qib_read_kreg32(dd, kr_scratch); | |
157 | udelay(4); | |
158 | qib_write_kreg(dd, kr_hwerrclear, | |
159 | QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR); | |
160 | qib_read_kreg32(dd, kr_scratch); | |
161 | bail: | |
162 | return; | |
163 | } | |
164 | ||
165 | /* | |
166 | * After a reset or other unusual event, the epb interface may need | |
167 | * to be re-synchronized, between the host and the uC. | |
168 | * returns <0 for failure to resync within IBSD_RESYNC_TRIES (not expected) | |
169 | */ | |
170 | #define IBSD_RESYNC_TRIES 3 | |
171 | #define IB_PGUDP(chn) (EPB_LOC((chn), 2, 1) | EPB_IB_QUAD0_CS) | |
172 | #define IB_CMUDONE(chn) (EPB_LOC((chn), 7, 0xF) | EPB_IB_QUAD0_CS) | |
173 | ||
174 | static int qib_resync_ibepb(struct qib_devdata *dd) | |
175 | { | |
176 | int ret, pat, tries, chn; | |
177 | u32 loc; | |
178 | ||
179 | ret = -1; | |
180 | chn = 0; | |
181 | for (tries = 0; tries < (4 * IBSD_RESYNC_TRIES); ++tries) { | |
182 | loc = IB_PGUDP(chn); | |
183 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0); | |
184 | if (ret < 0) { | |
185 | qib_dev_err(dd, "Failed read in resync\n"); | |
186 | continue; | |
187 | } | |
188 | if (ret != 0xF0 && ret != 0x55 && tries == 0) | |
189 | qib_dev_err(dd, "unexpected pattern in resync\n"); | |
190 | pat = ret ^ 0xA5; /* alternate F0 and 55 */ | |
191 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, pat, 0xFF); | |
192 | if (ret < 0) { | |
193 | qib_dev_err(dd, "Failed write in resync\n"); | |
194 | continue; | |
195 | } | |
196 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0); | |
197 | if (ret < 0) { | |
198 | qib_dev_err(dd, "Failed re-read in resync\n"); | |
199 | continue; | |
200 | } | |
201 | if (ret != pat) { | |
202 | qib_dev_err(dd, "Failed compare1 in resync\n"); | |
203 | continue; | |
204 | } | |
205 | loc = IB_CMUDONE(chn); | |
206 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0); | |
207 | if (ret < 0) { | |
208 | qib_dev_err(dd, "Failed CMUDONE rd in resync\n"); | |
209 | continue; | |
210 | } | |
211 | if ((ret & 0x70) != ((chn << 4) | 0x40)) { | |
212 | qib_dev_err(dd, "Bad CMUDONE value %02X, chn %d\n", | |
213 | ret, chn); | |
214 | continue; | |
215 | } | |
216 | if (++chn == 4) | |
217 | break; /* Success */ | |
218 | } | |
219 | return (ret > 0) ? 0 : ret; | |
220 | } | |
221 | ||
222 | /* | |
223 | * Localize the stuff that should be done to change IB uC reset | |
224 | * returns <0 for errors. | |
225 | */ | |
226 | static int qib_ibsd_reset(struct qib_devdata *dd, int assert_rst) | |
227 | { | |
228 | u64 rst_val; | |
229 | int ret = 0; | |
230 | unsigned long flags; | |
231 | ||
232 | rst_val = qib_read_kreg64(dd, kr_ibserdesctrl); | |
233 | if (assert_rst) { | |
234 | /* | |
235 | * Vendor recommends "interrupting" uC before reset, to | |
236 | * minimize possible glitches. | |
237 | */ | |
238 | spin_lock_irqsave(&dd->cspec->sdepb_lock, flags); | |
239 | epb_access(dd, IB_7220_SERDES, 1); | |
240 | rst_val |= 1ULL; | |
241 | /* Squelch possible parity error from _asserting_ reset */ | |
242 | qib_write_kreg(dd, kr_hwerrmask, | |
243 | dd->cspec->hwerrmask & | |
244 | ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR); | |
245 | qib_write_kreg(dd, kr_ibserdesctrl, rst_val); | |
246 | /* flush write, delay to ensure it took effect */ | |
247 | qib_read_kreg32(dd, kr_scratch); | |
248 | udelay(2); | |
249 | /* once it's reset, can remove interrupt */ | |
250 | epb_access(dd, IB_7220_SERDES, -1); | |
251 | spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); | |
252 | } else { | |
253 | /* | |
254 | * Before we de-assert reset, we need to deal with | |
255 | * possible glitch on the Parity-error line. | |
256 | * Suppress it around the reset, both in chip-level | |
257 | * hwerrmask and in IB uC control reg. uC will allow | |
258 | * it again during startup. | |
259 | */ | |
260 | u64 val; | |
261 | rst_val &= ~(1ULL); | |
262 | qib_write_kreg(dd, kr_hwerrmask, | |
263 | dd->cspec->hwerrmask & | |
264 | ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR); | |
265 | ||
266 | ret = qib_resync_ibepb(dd); | |
267 | if (ret < 0) | |
268 | qib_dev_err(dd, "unable to re-sync IB EPB\n"); | |
269 | ||
270 | /* set uC control regs to suppress parity errs */ | |
271 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG5, 1, 1); | |
272 | if (ret < 0) | |
273 | goto bail; | |
274 | /* IB uC code past Version 1.32.17 allow suppression of wdog */ | |
275 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, | |
276 | 0x80); | |
277 | if (ret < 0) { | |
278 | qib_dev_err(dd, "Failed to set WDOG disable\n"); | |
279 | goto bail; | |
280 | } | |
281 | qib_write_kreg(dd, kr_ibserdesctrl, rst_val); | |
282 | /* flush write, delay for startup */ | |
283 | qib_read_kreg32(dd, kr_scratch); | |
284 | udelay(1); | |
285 | /* clear, then re-enable parity errs */ | |
286 | qib_sd7220_clr_ibpar(dd); | |
287 | val = qib_read_kreg64(dd, kr_hwerrstatus); | |
288 | if (val & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR) { | |
289 | qib_dev_err(dd, "IBUC Parity still set after RST\n"); | |
290 | dd->cspec->hwerrmask &= | |
291 | ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR; | |
292 | } | |
293 | qib_write_kreg(dd, kr_hwerrmask, | |
294 | dd->cspec->hwerrmask); | |
295 | } | |
296 | ||
297 | bail: | |
298 | return ret; | |
299 | } | |
300 | ||
301 | static void qib_sd_trimdone_monitor(struct qib_devdata *dd, | |
302 | const char *where) | |
303 | { | |
304 | int ret, chn, baduns; | |
305 | u64 val; | |
306 | ||
307 | if (!where) | |
308 | where = "?"; | |
309 | ||
310 | /* give time for reset to settle out in EPB */ | |
311 | udelay(2); | |
312 | ||
313 | ret = qib_resync_ibepb(dd); | |
314 | if (ret < 0) | |
315 | qib_dev_err(dd, "not able to re-sync IB EPB (%s)\n", where); | |
316 | ||
317 | /* Do "sacrificial read" to get EPB in sane state after reset */ | |
318 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_CTRL2(0), 0, 0); | |
319 | if (ret < 0) | |
320 | qib_dev_err(dd, "Failed TRIMDONE 1st read, (%s)\n", where); | |
321 | ||
322 | /* Check/show "summary" Trim-done bit in IBCStatus */ | |
323 | val = qib_read_kreg64(dd, kr_ibcstatus); | |
324 | if (!(val & (1ULL << 11))) | |
325 | qib_dev_err(dd, "IBCS TRIMDONE clear (%s)\n", where); | |
326 | /* | |
327 | * Do "dummy read/mod/wr" to get EPB in sane state after reset | |
328 | * The default value for MPREG6 is 0. | |
329 | */ | |
330 | udelay(2); | |
331 | ||
332 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 0x80); | |
333 | if (ret < 0) | |
334 | qib_dev_err(dd, "Failed Dummy RMW, (%s)\n", where); | |
335 | udelay(10); | |
336 | ||
337 | baduns = 0; | |
338 | ||
339 | for (chn = 3; chn >= 0; --chn) { | |
340 | /* Read CTRL reg for each channel to check TRIMDONE */ | |
341 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, | |
342 | IB_CTRL2(chn), 0, 0); | |
343 | if (ret < 0) | |
344 | qib_dev_err(dd, "Failed checking TRIMDONE, chn %d" | |
345 | " (%s)\n", chn, where); | |
346 | ||
347 | if (!(ret & 0x10)) { | |
348 | int probe; | |
349 | ||
350 | baduns |= (1 << chn); | |
351 | qib_dev_err(dd, "TRIMDONE cleared on chn %d (%02X)." | |
352 | " (%s)\n", chn, ret, where); | |
353 | probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES, | |
354 | IB_PGUDP(0), 0, 0); | |
355 | qib_dev_err(dd, "probe is %d (%02X)\n", | |
356 | probe, probe); | |
357 | probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES, | |
358 | IB_CTRL2(chn), 0, 0); | |
359 | qib_dev_err(dd, "re-read: %d (%02X)\n", | |
360 | probe, probe); | |
361 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, | |
362 | IB_CTRL2(chn), 0x10, 0x10); | |
363 | if (ret < 0) | |
364 | qib_dev_err(dd, | |
365 | "Err on TRIMDONE rewrite1\n"); | |
366 | } | |
367 | } | |
368 | for (chn = 3; chn >= 0; --chn) { | |
369 | /* Read CTRL reg for each channel to check TRIMDONE */ | |
370 | if (baduns & (1 << chn)) { | |
371 | qib_dev_err(dd, | |
372 | "Reseting TRIMDONE on chn %d (%s)\n", | |
373 | chn, where); | |
374 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, | |
375 | IB_CTRL2(chn), 0x10, 0x10); | |
376 | if (ret < 0) | |
377 | qib_dev_err(dd, "Failed re-setting " | |
378 | "TRIMDONE, chn %d (%s)\n", | |
379 | chn, where); | |
380 | } | |
381 | } | |
382 | } | |
383 | ||
384 | /* | |
385 | * Below is portion of IBA7220-specific bringup_serdes() that actually | |
386 | * deals with registers and memory within the SerDes itself. | |
387 | * Post IB uC code version 1.32.17, was_reset being 1 is not really | |
388 | * informative, so we double-check. | |
389 | */ | |
390 | int qib_sd7220_init(struct qib_devdata *dd) | |
391 | { | |
ecd4b48a | 392 | const struct firmware *fw; |
f931551b RC |
393 | int ret = 1; /* default to failure */ |
394 | int first_reset, was_reset; | |
395 | ||
396 | /* SERDES MPU reset recorded in D0 */ | |
397 | was_reset = (qib_read_kreg64(dd, kr_ibserdesctrl) & 1); | |
398 | if (!was_reset) { | |
399 | /* entered with reset not asserted, we need to do it */ | |
400 | qib_ibsd_reset(dd, 1); | |
401 | qib_sd_trimdone_monitor(dd, "Driver-reload"); | |
402 | } | |
ecd4b48a BH |
403 | |
404 | ret = request_firmware(&fw, SD7220_FW_NAME, &dd->pcidev->dev); | |
405 | if (ret) { | |
406 | qib_dev_err(dd, "Failed to load IB SERDES image\n"); | |
407 | goto done; | |
408 | } | |
409 | ||
f931551b | 410 | /* Substitute our deduced value for was_reset */ |
ecd4b48a | 411 | ret = qib_ibsd_ucode_loaded(dd->pport, fw); |
f931551b RC |
412 | if (ret < 0) |
413 | goto bail; | |
414 | ||
415 | first_reset = !ret; /* First reset if IBSD uCode not yet loaded */ | |
416 | /* | |
417 | * Alter some regs per vendor latest doc, reset-defaults | |
418 | * are not right for IB. | |
419 | */ | |
420 | ret = qib_sd_early(dd); | |
421 | if (ret < 0) { | |
422 | qib_dev_err(dd, "Failed to set IB SERDES early defaults\n"); | |
423 | goto bail; | |
424 | } | |
425 | /* | |
426 | * Set DAC manual trim IB. | |
427 | * We only do this once after chip has been reset (usually | |
428 | * same as once per system boot). | |
429 | */ | |
430 | if (first_reset) { | |
431 | ret = qib_sd_dactrim(dd); | |
432 | if (ret < 0) { | |
433 | qib_dev_err(dd, "Failed IB SERDES DAC trim\n"); | |
434 | goto bail; | |
435 | } | |
436 | } | |
437 | /* | |
438 | * Set various registers (DDS and RXEQ) that will be | |
439 | * controlled by IBC (in 1.2 mode) to reasonable preset values | |
440 | * Calling the "internal" version avoids the "check for needed" | |
441 | * and "trimdone monitor" that might be counter-productive. | |
442 | */ | |
443 | ret = qib_internal_presets(dd); | |
444 | if (ret < 0) { | |
445 | qib_dev_err(dd, "Failed to set IB SERDES presets\n"); | |
446 | goto bail; | |
447 | } | |
448 | ret = qib_sd_trimself(dd, 0x80); | |
449 | if (ret < 0) { | |
450 | qib_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n"); | |
451 | goto bail; | |
452 | } | |
453 | ||
454 | /* Load image, then try to verify */ | |
455 | ret = 0; /* Assume success */ | |
456 | if (first_reset) { | |
457 | int vfy; | |
458 | int trim_done; | |
459 | ||
ecd4b48a | 460 | ret = qib_sd7220_ib_load(dd, fw); |
f931551b RC |
461 | if (ret < 0) { |
462 | qib_dev_err(dd, "Failed to load IB SERDES image\n"); | |
463 | goto bail; | |
464 | } else { | |
465 | /* Loaded image, try to verify */ | |
ecd4b48a | 466 | vfy = qib_sd7220_ib_vfy(dd, fw); |
f931551b RC |
467 | if (vfy != ret) { |
468 | qib_dev_err(dd, "SERDES PRAM VFY failed\n"); | |
469 | goto bail; | |
470 | } /* end if verified */ | |
471 | } /* end if loaded */ | |
472 | ||
473 | /* | |
474 | * Loaded and verified. Almost good... | |
475 | * hold "success" in ret | |
476 | */ | |
477 | ret = 0; | |
478 | /* | |
479 | * Prev steps all worked, continue bringup | |
480 | * De-assert RESET to uC, only in first reset, to allow | |
481 | * trimming. | |
482 | * | |
483 | * Since our default setup sets START_EQ1 to | |
484 | * PRESET, we need to clear that for this very first run. | |
485 | */ | |
486 | ret = ibsd_mod_allchnls(dd, START_EQ1(0), 0, 0x38); | |
487 | if (ret < 0) { | |
488 | qib_dev_err(dd, "Failed clearing START_EQ1\n"); | |
489 | goto bail; | |
490 | } | |
491 | ||
492 | qib_ibsd_reset(dd, 0); | |
493 | /* | |
494 | * If this is not the first reset, trimdone should be set | |
495 | * already. We may need to check about this. | |
496 | */ | |
497 | trim_done = qib_sd_trimdone_poll(dd); | |
498 | /* | |
499 | * Whether or not trimdone succeeded, we need to put the | |
500 | * uC back into reset to avoid a possible fight with the | |
501 | * IBC state-machine. | |
502 | */ | |
503 | qib_ibsd_reset(dd, 1); | |
504 | ||
505 | if (!trim_done) { | |
506 | qib_dev_err(dd, "No TRIMDONE seen\n"); | |
507 | goto bail; | |
508 | } | |
509 | /* | |
510 | * DEBUG: check each time we reset if trimdone bits have | |
511 | * gotten cleared, and re-set them. | |
512 | */ | |
513 | qib_sd_trimdone_monitor(dd, "First-reset"); | |
514 | /* Remember so we do not re-do the load, dactrim, etc. */ | |
515 | dd->cspec->serdes_first_init_done = 1; | |
516 | } | |
517 | /* | |
518 | * setup for channel training and load values for | |
519 | * RxEq and DDS in tables used by IBC in IB1.2 mode | |
520 | */ | |
521 | ret = 0; | |
522 | if (qib_sd_setvals(dd) >= 0) | |
523 | goto done; | |
524 | bail: | |
525 | ret = 1; | |
526 | done: | |
527 | /* start relock timer regardless, but start at 1 second */ | |
528 | set_7220_relock_poll(dd, -1); | |
ecd4b48a BH |
529 | |
530 | release_firmware(fw); | |
f931551b RC |
531 | return ret; |
532 | } | |
533 | ||
534 | #define EPB_ACC_REQ 1 | |
535 | #define EPB_ACC_GNT 0x100 | |
536 | #define EPB_DATA_MASK 0xFF | |
537 | #define EPB_RD (1ULL << 24) | |
538 | #define EPB_TRANS_RDY (1ULL << 31) | |
539 | #define EPB_TRANS_ERR (1ULL << 30) | |
540 | #define EPB_TRANS_TRIES 5 | |
541 | ||
542 | /* | |
543 | * query, claim, release ownership of the EPB (External Parallel Bus) | |
544 | * for a specified SERDES. | |
545 | * the "claim" parameter is >0 to claim, <0 to release, 0 to query. | |
546 | * Returns <0 for errors, >0 if we had ownership, else 0. | |
547 | */ | |
548 | static int epb_access(struct qib_devdata *dd, int sdnum, int claim) | |
549 | { | |
550 | u16 acc; | |
551 | u64 accval; | |
552 | int owned = 0; | |
553 | u64 oct_sel = 0; | |
554 | ||
555 | switch (sdnum) { | |
556 | case IB_7220_SERDES: | |
557 | /* | |
558 | * The IB SERDES "ownership" is fairly simple. A single each | |
559 | * request/grant. | |
560 | */ | |
561 | acc = kr_ibsd_epb_access_ctrl; | |
562 | break; | |
563 | ||
564 | case PCIE_SERDES0: | |
565 | case PCIE_SERDES1: | |
566 | /* PCIe SERDES has two "octants", need to select which */ | |
567 | acc = kr_pciesd_epb_access_ctrl; | |
568 | oct_sel = (2 << (sdnum - PCIE_SERDES0)); | |
569 | break; | |
570 | ||
571 | default: | |
572 | return 0; | |
573 | } | |
574 | ||
575 | /* Make sure any outstanding transaction was seen */ | |
576 | qib_read_kreg32(dd, kr_scratch); | |
577 | udelay(15); | |
578 | ||
579 | accval = qib_read_kreg32(dd, acc); | |
580 | ||
581 | owned = !!(accval & EPB_ACC_GNT); | |
582 | if (claim < 0) { | |
583 | /* Need to release */ | |
584 | u64 pollval; | |
585 | /* | |
586 | * The only writeable bits are the request and CS. | |
587 | * Both should be clear | |
588 | */ | |
589 | u64 newval = 0; | |
590 | qib_write_kreg(dd, acc, newval); | |
591 | /* First read after write is not trustworthy */ | |
592 | pollval = qib_read_kreg32(dd, acc); | |
593 | udelay(5); | |
594 | pollval = qib_read_kreg32(dd, acc); | |
595 | if (pollval & EPB_ACC_GNT) | |
596 | owned = -1; | |
597 | } else if (claim > 0) { | |
598 | /* Need to claim */ | |
599 | u64 pollval; | |
600 | u64 newval = EPB_ACC_REQ | oct_sel; | |
601 | qib_write_kreg(dd, acc, newval); | |
602 | /* First read after write is not trustworthy */ | |
603 | pollval = qib_read_kreg32(dd, acc); | |
604 | udelay(5); | |
605 | pollval = qib_read_kreg32(dd, acc); | |
606 | if (!(pollval & EPB_ACC_GNT)) | |
607 | owned = -1; | |
608 | } | |
609 | return owned; | |
610 | } | |
611 | ||
612 | /* | |
613 | * Lemma to deal with race condition of write..read to epb regs | |
614 | */ | |
615 | static int epb_trans(struct qib_devdata *dd, u16 reg, u64 i_val, u64 *o_vp) | |
616 | { | |
617 | int tries; | |
618 | u64 transval; | |
619 | ||
620 | qib_write_kreg(dd, reg, i_val); | |
621 | /* Throw away first read, as RDY bit may be stale */ | |
622 | transval = qib_read_kreg64(dd, reg); | |
623 | ||
624 | for (tries = EPB_TRANS_TRIES; tries; --tries) { | |
625 | transval = qib_read_kreg32(dd, reg); | |
626 | if (transval & EPB_TRANS_RDY) | |
627 | break; | |
628 | udelay(5); | |
629 | } | |
630 | if (transval & EPB_TRANS_ERR) | |
631 | return -1; | |
632 | if (tries > 0 && o_vp) | |
633 | *o_vp = transval; | |
634 | return tries; | |
635 | } | |
636 | ||
637 | /** | |
638 | * qib_sd7220_reg_mod - modify SERDES register | |
639 | * @dd: the qlogic_ib device | |
640 | * @sdnum: which SERDES to access | |
641 | * @loc: location - channel, element, register, as packed by EPB_LOC() macro. | |
642 | * @wd: Write Data - value to set in register | |
643 | * @mask: ones where data should be spliced into reg. | |
644 | * | |
645 | * Basic register read/modify/write, with un-needed acesses elided. That is, | |
646 | * a mask of zero will prevent write, while a mask of 0xFF will prevent read. | |
647 | * returns current (presumed, if a write was done) contents of selected | |
648 | * register, or <0 if errors. | |
649 | */ | |
650 | static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc, | |
651 | u32 wd, u32 mask) | |
652 | { | |
653 | u16 trans; | |
654 | u64 transval; | |
655 | int owned; | |
656 | int tries, ret; | |
657 | unsigned long flags; | |
658 | ||
659 | switch (sdnum) { | |
660 | case IB_7220_SERDES: | |
661 | trans = kr_ibsd_epb_transaction_reg; | |
662 | break; | |
663 | ||
664 | case PCIE_SERDES0: | |
665 | case PCIE_SERDES1: | |
666 | trans = kr_pciesd_epb_transaction_reg; | |
667 | break; | |
668 | ||
669 | default: | |
670 | return -1; | |
671 | } | |
672 | ||
673 | /* | |
674 | * All access is locked in software (vs other host threads) and | |
675 | * hardware (vs uC access). | |
676 | */ | |
677 | spin_lock_irqsave(&dd->cspec->sdepb_lock, flags); | |
678 | ||
679 | owned = epb_access(dd, sdnum, 1); | |
680 | if (owned < 0) { | |
681 | spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); | |
682 | return -1; | |
683 | } | |
684 | ret = 0; | |
685 | for (tries = EPB_TRANS_TRIES; tries; --tries) { | |
686 | transval = qib_read_kreg32(dd, trans); | |
687 | if (transval & EPB_TRANS_RDY) | |
688 | break; | |
689 | udelay(5); | |
690 | } | |
691 | ||
692 | if (tries > 0) { | |
693 | tries = 1; /* to make read-skip work */ | |
694 | if (mask != 0xFF) { | |
695 | /* | |
696 | * Not a pure write, so need to read. | |
697 | * loc encodes chip-select as well as address | |
698 | */ | |
699 | transval = loc | EPB_RD; | |
700 | tries = epb_trans(dd, trans, transval, &transval); | |
701 | } | |
702 | if (tries > 0 && mask != 0) { | |
703 | /* | |
704 | * Not a pure read, so need to write. | |
705 | */ | |
706 | wd = (wd & mask) | (transval & ~mask); | |
707 | transval = loc | (wd & EPB_DATA_MASK); | |
708 | tries = epb_trans(dd, trans, transval, &transval); | |
709 | } | |
710 | } | |
711 | /* else, failed to see ready, what error-handling? */ | |
712 | ||
713 | /* | |
714 | * Release bus. Failure is an error. | |
715 | */ | |
716 | if (epb_access(dd, sdnum, -1) < 0) | |
717 | ret = -1; | |
718 | else | |
719 | ret = transval & EPB_DATA_MASK; | |
720 | ||
721 | spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); | |
722 | if (tries <= 0) | |
723 | ret = -1; | |
724 | return ret; | |
725 | } | |
726 | ||
727 | #define EPB_ROM_R (2) | |
728 | #define EPB_ROM_W (1) | |
729 | /* | |
730 | * Below, all uC-related, use appropriate UC_CS, depending | |
731 | * on which SerDes is used. | |
732 | */ | |
733 | #define EPB_UC_CTL EPB_LOC(6, 0, 0) | |
734 | #define EPB_MADDRL EPB_LOC(6, 0, 2) | |
735 | #define EPB_MADDRH EPB_LOC(6, 0, 3) | |
736 | #define EPB_ROMDATA EPB_LOC(6, 0, 4) | |
737 | #define EPB_RAMDATA EPB_LOC(6, 0, 5) | |
738 | ||
739 | /* Transfer date to/from uC Program RAM of IB or PCIe SerDes */ | |
740 | static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc, | |
741 | u8 *buf, int cnt, int rd_notwr) | |
742 | { | |
743 | u16 trans; | |
744 | u64 transval; | |
745 | u64 csbit; | |
746 | int owned; | |
747 | int tries; | |
748 | int sofar; | |
749 | int addr; | |
750 | int ret; | |
751 | unsigned long flags; | |
752 | const char *op; | |
753 | ||
754 | /* Pick appropriate transaction reg and "Chip select" for this serdes */ | |
755 | switch (sdnum) { | |
756 | case IB_7220_SERDES: | |
757 | csbit = 1ULL << EPB_IB_UC_CS_SHF; | |
758 | trans = kr_ibsd_epb_transaction_reg; | |
759 | break; | |
760 | ||
761 | case PCIE_SERDES0: | |
762 | case PCIE_SERDES1: | |
763 | /* PCIe SERDES has uC "chip select" in different bit, too */ | |
764 | csbit = 1ULL << EPB_PCIE_UC_CS_SHF; | |
765 | trans = kr_pciesd_epb_transaction_reg; | |
766 | break; | |
767 | ||
768 | default: | |
769 | return -1; | |
770 | } | |
771 | ||
772 | op = rd_notwr ? "Rd" : "Wr"; | |
773 | spin_lock_irqsave(&dd->cspec->sdepb_lock, flags); | |
774 | ||
775 | owned = epb_access(dd, sdnum, 1); | |
776 | if (owned < 0) { | |
777 | spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); | |
778 | return -1; | |
779 | } | |
780 | ||
781 | /* | |
782 | * In future code, we may need to distinguish several address ranges, | |
783 | * and select various memories based on this. For now, just trim | |
784 | * "loc" (location including address and memory select) to | |
785 | * "addr" (address within memory). we will only support PRAM | |
786 | * The memory is 8KB. | |
787 | */ | |
788 | addr = loc & 0x1FFF; | |
789 | for (tries = EPB_TRANS_TRIES; tries; --tries) { | |
790 | transval = qib_read_kreg32(dd, trans); | |
791 | if (transval & EPB_TRANS_RDY) | |
792 | break; | |
793 | udelay(5); | |
794 | } | |
795 | ||
796 | sofar = 0; | |
797 | if (tries > 0) { | |
798 | /* | |
799 | * Every "memory" access is doubly-indirect. | |
800 | * We set two bytes of address, then read/write | |
801 | * one or mores bytes of data. | |
802 | */ | |
803 | ||
804 | /* First, we set control to "Read" or "Write" */ | |
805 | transval = csbit | EPB_UC_CTL | | |
806 | (rd_notwr ? EPB_ROM_R : EPB_ROM_W); | |
807 | tries = epb_trans(dd, trans, transval, &transval); | |
808 | while (tries > 0 && sofar < cnt) { | |
809 | if (!sofar) { | |
810 | /* Only set address at start of chunk */ | |
811 | int addrbyte = (addr + sofar) >> 8; | |
812 | transval = csbit | EPB_MADDRH | addrbyte; | |
813 | tries = epb_trans(dd, trans, transval, | |
814 | &transval); | |
815 | if (tries <= 0) | |
816 | break; | |
817 | addrbyte = (addr + sofar) & 0xFF; | |
818 | transval = csbit | EPB_MADDRL | addrbyte; | |
819 | tries = epb_trans(dd, trans, transval, | |
820 | &transval); | |
821 | if (tries <= 0) | |
822 | break; | |
823 | } | |
824 | ||
825 | if (rd_notwr) | |
826 | transval = csbit | EPB_ROMDATA | EPB_RD; | |
827 | else | |
828 | transval = csbit | EPB_ROMDATA | buf[sofar]; | |
829 | tries = epb_trans(dd, trans, transval, &transval); | |
830 | if (tries <= 0) | |
831 | break; | |
832 | if (rd_notwr) | |
833 | buf[sofar] = transval & EPB_DATA_MASK; | |
834 | ++sofar; | |
835 | } | |
836 | /* Finally, clear control-bit for Read or Write */ | |
837 | transval = csbit | EPB_UC_CTL; | |
838 | tries = epb_trans(dd, trans, transval, &transval); | |
839 | } | |
840 | ||
841 | ret = sofar; | |
842 | /* Release bus. Failure is an error */ | |
843 | if (epb_access(dd, sdnum, -1) < 0) | |
844 | ret = -1; | |
845 | ||
846 | spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags); | |
847 | if (tries <= 0) | |
848 | ret = -1; | |
849 | return ret; | |
850 | } | |
851 | ||
852 | #define PROG_CHUNK 64 | |
853 | ||
ecd4b48a BH |
854 | static int qib_sd7220_prog_ld(struct qib_devdata *dd, int sdnum, |
855 | const u8 *img, int len, int offset) | |
f931551b RC |
856 | { |
857 | int cnt, sofar, req; | |
858 | ||
859 | sofar = 0; | |
860 | while (sofar < len) { | |
861 | req = len - sofar; | |
862 | if (req > PROG_CHUNK) | |
863 | req = PROG_CHUNK; | |
864 | cnt = qib_sd7220_ram_xfer(dd, sdnum, offset + sofar, | |
ecd4b48a | 865 | (u8 *)img + sofar, req, 0); |
f931551b RC |
866 | if (cnt < req) { |
867 | sofar = -1; | |
868 | break; | |
869 | } | |
870 | sofar += req; | |
871 | } | |
872 | return sofar; | |
873 | } | |
874 | ||
875 | #define VFY_CHUNK 64 | |
876 | #define SD_PRAM_ERROR_LIMIT 42 | |
877 | ||
ecd4b48a BH |
878 | static int qib_sd7220_prog_vfy(struct qib_devdata *dd, int sdnum, |
879 | const u8 *img, int len, int offset) | |
f931551b RC |
880 | { |
881 | int cnt, sofar, req, idx, errors; | |
882 | unsigned char readback[VFY_CHUNK]; | |
883 | ||
884 | errors = 0; | |
885 | sofar = 0; | |
886 | while (sofar < len) { | |
887 | req = len - sofar; | |
888 | if (req > VFY_CHUNK) | |
889 | req = VFY_CHUNK; | |
890 | cnt = qib_sd7220_ram_xfer(dd, sdnum, sofar + offset, | |
891 | readback, req, 1); | |
892 | if (cnt < req) { | |
893 | /* failed in read itself */ | |
894 | sofar = -1; | |
895 | break; | |
896 | } | |
897 | for (idx = 0; idx < cnt; ++idx) { | |
898 | if (readback[idx] != img[idx+sofar]) | |
899 | ++errors; | |
900 | } | |
901 | sofar += cnt; | |
902 | } | |
903 | return errors ? -errors : sofar; | |
904 | } | |
905 | ||
ecd4b48a BH |
906 | static int |
907 | qib_sd7220_ib_load(struct qib_devdata *dd, const struct firmware *fw) | |
908 | { | |
909 | return qib_sd7220_prog_ld(dd, IB_7220_SERDES, fw->data, fw->size, 0); | |
910 | } | |
911 | ||
912 | static int | |
913 | qib_sd7220_ib_vfy(struct qib_devdata *dd, const struct firmware *fw) | |
914 | { | |
915 | return qib_sd7220_prog_vfy(dd, IB_7220_SERDES, fw->data, fw->size, 0); | |
916 | } | |
917 | ||
f931551b RC |
918 | /* |
919 | * IRQ not set up at this point in init, so we poll. | |
920 | */ | |
921 | #define IB_SERDES_TRIM_DONE (1ULL << 11) | |
922 | #define TRIM_TMO (30) | |
923 | ||
924 | static int qib_sd_trimdone_poll(struct qib_devdata *dd) | |
925 | { | |
926 | int trim_tmo, ret; | |
927 | uint64_t val; | |
928 | ||
929 | /* | |
930 | * Default to failure, so IBC will not start | |
931 | * without IB_SERDES_TRIM_DONE. | |
932 | */ | |
933 | ret = 0; | |
934 | for (trim_tmo = 0; trim_tmo < TRIM_TMO; ++trim_tmo) { | |
935 | val = qib_read_kreg64(dd, kr_ibcstatus); | |
936 | if (val & IB_SERDES_TRIM_DONE) { | |
937 | ret = 1; | |
938 | break; | |
939 | } | |
940 | msleep(10); | |
941 | } | |
942 | if (trim_tmo >= TRIM_TMO) { | |
943 | qib_dev_err(dd, "No TRIMDONE in %d tries\n", trim_tmo); | |
944 | ret = 0; | |
945 | } | |
946 | return ret; | |
947 | } | |
948 | ||
949 | #define TX_FAST_ELT (9) | |
950 | ||
951 | /* | |
952 | * Set the "negotiation" values for SERDES. These are used by the IB1.2 | |
953 | * link negotiation. Macros below are attempt to keep the values a | |
954 | * little more human-editable. | |
955 | * First, values related to Drive De-emphasis Settings. | |
956 | */ | |
957 | ||
958 | #define NUM_DDS_REGS 6 | |
959 | #define DDS_REG_MAP 0x76A910 /* LSB-first list of regs (in elt 9) to mod */ | |
960 | ||
961 | #define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) \ | |
962 | { { ((amp_d & 0x1F) << 1) | 1, ((amp_s & 0x1F) << 1) | 1, \ | |
963 | (main_d << 3) | 4 | (ipre_d >> 2), \ | |
964 | (main_s << 3) | 4 | (ipre_s >> 2), \ | |
965 | ((ipst_d & 0xF) << 1) | ((ipre_d & 3) << 6) | 0x21, \ | |
966 | ((ipst_s & 0xF) << 1) | ((ipre_s & 3) << 6) | 0x21 } } | |
967 | ||
968 | static struct dds_init { | |
969 | uint8_t reg_vals[NUM_DDS_REGS]; | |
970 | } dds_init_vals[] = { | |
971 | /* DDR(FDR) SDR(HDR) */ | |
972 | /* Vendor recommends below for 3m cable */ | |
973 | #define DDS_3M 0 | |
974 | DDS_VAL(31, 19, 12, 0, 29, 22, 9, 0), | |
975 | DDS_VAL(31, 12, 15, 4, 31, 15, 15, 1), | |
976 | DDS_VAL(31, 13, 15, 3, 31, 16, 15, 0), | |
977 | DDS_VAL(31, 14, 15, 2, 31, 17, 14, 0), | |
978 | DDS_VAL(31, 15, 15, 1, 31, 18, 13, 0), | |
979 | DDS_VAL(31, 16, 15, 0, 31, 19, 12, 0), | |
980 | DDS_VAL(31, 17, 14, 0, 31, 20, 11, 0), | |
981 | DDS_VAL(31, 18, 13, 0, 30, 21, 10, 0), | |
982 | DDS_VAL(31, 20, 11, 0, 28, 23, 8, 0), | |
983 | DDS_VAL(31, 21, 10, 0, 27, 24, 7, 0), | |
984 | DDS_VAL(31, 22, 9, 0, 26, 25, 6, 0), | |
985 | DDS_VAL(30, 23, 8, 0, 25, 26, 5, 0), | |
986 | DDS_VAL(29, 24, 7, 0, 23, 27, 4, 0), | |
987 | /* Vendor recommends below for 1m cable */ | |
988 | #define DDS_1M 13 | |
989 | DDS_VAL(28, 25, 6, 0, 21, 28, 3, 0), | |
990 | DDS_VAL(27, 26, 5, 0, 19, 29, 2, 0), | |
991 | DDS_VAL(25, 27, 4, 0, 17, 30, 1, 0) | |
992 | }; | |
993 | ||
994 | /* | |
995 | * Now the RXEQ section of the table. | |
996 | */ | |
997 | /* Hardware packs an element number and register address thus: */ | |
998 | #define RXEQ_INIT_RDESC(elt, addr) (((elt) & 0xF) | ((addr) << 4)) | |
999 | #define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \ | |
1000 | {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} } | |
1001 | ||
1002 | #define RXEQ_VAL_ALL(elt, adr, val) \ | |
1003 | {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} } | |
1004 | ||
1005 | #define RXEQ_SDR_DFELTH 0 | |
1006 | #define RXEQ_SDR_TLTH 0 | |
1007 | #define RXEQ_SDR_G1CNT_Z1CNT 0x11 | |
1008 | #define RXEQ_SDR_ZCNT 23 | |
1009 | ||
1010 | static struct rxeq_init { | |
1011 | u16 rdesc; /* in form used in SerDesDDSRXEQ */ | |
1012 | u8 rdata[4]; | |
1013 | } rxeq_init_vals[] = { | |
1014 | /* Set Rcv Eq. to Preset node */ | |
1015 | RXEQ_VAL_ALL(7, 0x27, 0x10), | |
1016 | /* Set DFELTHFDR/HDR thresholds */ | |
1017 | RXEQ_VAL(7, 8, 0, 0, 0, 0), /* FDR, was 0, 1, 2, 3 */ | |
1018 | RXEQ_VAL(7, 0x21, 0, 0, 0, 0), /* HDR */ | |
1019 | /* Set TLTHFDR/HDR theshold */ | |
1020 | RXEQ_VAL(7, 9, 2, 2, 2, 2), /* FDR, was 0, 2, 4, 6 */ | |
1021 | RXEQ_VAL(7, 0x23, 2, 2, 2, 2), /* HDR, was 0, 1, 2, 3 */ | |
1022 | /* Set Preamp setting 2 (ZFR/ZCNT) */ | |
1023 | RXEQ_VAL(7, 0x1B, 12, 12, 12, 12), /* FDR, was 12, 16, 20, 24 */ | |
1024 | RXEQ_VAL(7, 0x1C, 12, 12, 12, 12), /* HDR, was 12, 16, 20, 24 */ | |
1025 | /* Set Preamp DC gain and Setting 1 (GFR/GHR) */ | |
1026 | RXEQ_VAL(7, 0x1E, 16, 16, 16, 16), /* FDR, was 16, 17, 18, 20 */ | |
1027 | RXEQ_VAL(7, 0x1F, 16, 16, 16, 16), /* HDR, was 16, 17, 18, 20 */ | |
1028 | /* Toggle RELOCK (in VCDL_CTRL0) to lock to data */ | |
1029 | RXEQ_VAL_ALL(6, 6, 0x20), /* Set D5 High */ | |
1030 | RXEQ_VAL_ALL(6, 6, 0), /* Set D5 Low */ | |
1031 | }; | |
1032 | ||
1033 | /* There are 17 values from vendor, but IBC only accesses the first 16 */ | |
1034 | #define DDS_ROWS (16) | |
1035 | #define RXEQ_ROWS ARRAY_SIZE(rxeq_init_vals) | |
1036 | ||
1037 | static int qib_sd_setvals(struct qib_devdata *dd) | |
1038 | { | |
1039 | int idx, midx; | |
1040 | int min_idx; /* Minimum index for this portion of table */ | |
1041 | uint32_t dds_reg_map; | |
1042 | u64 __iomem *taddr, *iaddr; | |
1043 | uint64_t data; | |
1044 | uint64_t sdctl; | |
1045 | ||
1046 | taddr = dd->kregbase + kr_serdes_maptable; | |
1047 | iaddr = dd->kregbase + kr_serdes_ddsrxeq0; | |
1048 | ||
1049 | /* | |
1050 | * Init the DDS section of the table. | |
1051 | * Each "row" of the table provokes NUM_DDS_REG writes, to the | |
1052 | * registers indicated in DDS_REG_MAP. | |
1053 | */ | |
1054 | sdctl = qib_read_kreg64(dd, kr_ibserdesctrl); | |
1055 | sdctl = (sdctl & ~(0x1f << 8)) | (NUM_DDS_REGS << 8); | |
1056 | sdctl = (sdctl & ~(0x1f << 13)) | (RXEQ_ROWS << 13); | |
1057 | qib_write_kreg(dd, kr_ibserdesctrl, sdctl); | |
1058 | ||
1059 | /* | |
1060 | * Iterate down table within loop for each register to store. | |
1061 | */ | |
1062 | dds_reg_map = DDS_REG_MAP; | |
1063 | for (idx = 0; idx < NUM_DDS_REGS; ++idx) { | |
1064 | data = ((dds_reg_map & 0xF) << 4) | TX_FAST_ELT; | |
1065 | writeq(data, iaddr + idx); | |
1066 | mmiowb(); | |
1067 | qib_read_kreg32(dd, kr_scratch); | |
1068 | dds_reg_map >>= 4; | |
1069 | for (midx = 0; midx < DDS_ROWS; ++midx) { | |
1070 | u64 __iomem *daddr = taddr + ((midx << 4) + idx); | |
1071 | data = dds_init_vals[midx].reg_vals[idx]; | |
1072 | writeq(data, daddr); | |
1073 | mmiowb(); | |
1074 | qib_read_kreg32(dd, kr_scratch); | |
1075 | } /* End inner for (vals for this reg, each row) */ | |
1076 | } /* end outer for (regs to be stored) */ | |
1077 | ||
1078 | /* | |
1079 | * Init the RXEQ section of the table. | |
1080 | * This runs in a different order, as the pattern of | |
1081 | * register references is more complex, but there are only | |
1082 | * four "data" values per register. | |
1083 | */ | |
1084 | min_idx = idx; /* RXEQ indices pick up where DDS left off */ | |
1085 | taddr += 0x100; /* RXEQ data is in second half of table */ | |
1086 | /* Iterate through RXEQ register addresses */ | |
1087 | for (idx = 0; idx < RXEQ_ROWS; ++idx) { | |
1088 | int didx; /* "destination" */ | |
1089 | int vidx; | |
1090 | ||
1091 | /* didx is offset by min_idx to address RXEQ range of regs */ | |
1092 | didx = idx + min_idx; | |
1093 | /* Store the next RXEQ register address */ | |
1094 | writeq(rxeq_init_vals[idx].rdesc, iaddr + didx); | |
1095 | mmiowb(); | |
1096 | qib_read_kreg32(dd, kr_scratch); | |
1097 | /* Iterate through RXEQ values */ | |
1098 | for (vidx = 0; vidx < 4; vidx++) { | |
1099 | data = rxeq_init_vals[idx].rdata[vidx]; | |
1100 | writeq(data, taddr + (vidx << 6) + idx); | |
1101 | mmiowb(); | |
1102 | qib_read_kreg32(dd, kr_scratch); | |
1103 | } | |
1104 | } /* end outer for (Reg-writes for RXEQ) */ | |
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | #define CMUCTRL5 EPB_LOC(7, 0, 0x15) | |
1109 | #define RXHSCTRL0(chan) EPB_LOC(chan, 6, 0) | |
1110 | #define VCDL_DAC2(chan) EPB_LOC(chan, 6, 5) | |
1111 | #define VCDL_CTRL0(chan) EPB_LOC(chan, 6, 6) | |
1112 | #define VCDL_CTRL2(chan) EPB_LOC(chan, 6, 8) | |
1113 | #define START_EQ2(chan) EPB_LOC(chan, 7, 0x28) | |
1114 | ||
1115 | /* | |
1116 | * Repeat a "store" across all channels of the IB SerDes. | |
1117 | * Although nominally it inherits the "read value" of the last | |
1118 | * channel it modified, the only really useful return is <0 for | |
1119 | * failure, >= 0 for success. The parameter 'loc' is assumed to | |
1120 | * be the location in some channel of the register to be modified | |
1121 | * The caller can specify use of the "gang write" option of EPB, | |
1122 | * in which case we use the specified channel data for any fields | |
1123 | * not explicitely written. | |
1124 | */ | |
1125 | static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val, | |
1126 | int mask) | |
1127 | { | |
1128 | int ret = -1; | |
1129 | int chnl; | |
1130 | ||
1131 | if (loc & EPB_GLOBAL_WR) { | |
1132 | /* | |
1133 | * Our caller has assured us that we can set all four | |
1134 | * channels at once. Trust that. If mask is not 0xFF, | |
1135 | * we will read the _specified_ channel for our starting | |
1136 | * value. | |
1137 | */ | |
1138 | loc |= (1U << EPB_IB_QUAD0_CS_SHF); | |
1139 | chnl = (loc >> (4 + EPB_ADDR_SHF)) & 7; | |
1140 | if (mask != 0xFF) { | |
1141 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, | |
1142 | loc & ~EPB_GLOBAL_WR, 0, 0); | |
1143 | if (ret < 0) { | |
1144 | int sloc = loc >> EPB_ADDR_SHF; | |
1145 | ||
1146 | qib_dev_err(dd, "pre-read failed: elt %d," | |
1147 | " addr 0x%X, chnl %d\n", | |
1148 | (sloc & 0xF), | |
1149 | (sloc >> 9) & 0x3f, chnl); | |
1150 | return ret; | |
1151 | } | |
1152 | val = (ret & ~mask) | (val & mask); | |
1153 | } | |
1154 | loc &= ~(7 << (4+EPB_ADDR_SHF)); | |
1155 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF); | |
1156 | if (ret < 0) { | |
1157 | int sloc = loc >> EPB_ADDR_SHF; | |
1158 | ||
1159 | qib_dev_err(dd, "Global WR failed: elt %d," | |
1160 | " addr 0x%X, val %02X\n", | |
1161 | (sloc & 0xF), (sloc >> 9) & 0x3f, val); | |
1162 | } | |
1163 | return ret; | |
1164 | } | |
1165 | /* Clear "channel" and set CS so we can simply iterate */ | |
1166 | loc &= ~(7 << (4+EPB_ADDR_SHF)); | |
1167 | loc |= (1U << EPB_IB_QUAD0_CS_SHF); | |
1168 | for (chnl = 0; chnl < 4; ++chnl) { | |
1169 | int cloc = loc | (chnl << (4+EPB_ADDR_SHF)); | |
1170 | ||
1171 | ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask); | |
1172 | if (ret < 0) { | |
1173 | int sloc = loc >> EPB_ADDR_SHF; | |
1174 | ||
1175 | qib_dev_err(dd, "Write failed: elt %d," | |
1176 | " addr 0x%X, chnl %d, val 0x%02X," | |
1177 | " mask 0x%02X\n", | |
1178 | (sloc & 0xF), (sloc >> 9) & 0x3f, chnl, | |
1179 | val & 0xFF, mask & 0xFF); | |
1180 | break; | |
1181 | } | |
1182 | } | |
1183 | return ret; | |
1184 | } | |
1185 | ||
1186 | /* | |
1187 | * Set the Tx values normally modified by IBC in IB1.2 mode to default | |
1188 | * values, as gotten from first row of init table. | |
1189 | */ | |
1190 | static int set_dds_vals(struct qib_devdata *dd, struct dds_init *ddi) | |
1191 | { | |
1192 | int ret; | |
1193 | int idx, reg, data; | |
1194 | uint32_t regmap; | |
1195 | ||
1196 | regmap = DDS_REG_MAP; | |
1197 | for (idx = 0; idx < NUM_DDS_REGS; ++idx) { | |
1198 | reg = (regmap & 0xF); | |
1199 | regmap >>= 4; | |
1200 | data = ddi->reg_vals[idx]; | |
1201 | /* Vendor says RMW not needed for these regs, use 0xFF mask */ | |
1202 | ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF); | |
1203 | if (ret < 0) | |
1204 | break; | |
1205 | } | |
1206 | return ret; | |
1207 | } | |
1208 | ||
1209 | /* | |
1210 | * Set the Rx values normally modified by IBC in IB1.2 mode to default | |
1211 | * values, as gotten from selected column of init table. | |
1212 | */ | |
1213 | static int set_rxeq_vals(struct qib_devdata *dd, int vsel) | |
1214 | { | |
1215 | int ret; | |
1216 | int ridx; | |
1217 | int cnt = ARRAY_SIZE(rxeq_init_vals); | |
1218 | ||
1219 | for (ridx = 0; ridx < cnt; ++ridx) { | |
1220 | int elt, reg, val, loc; | |
1221 | ||
1222 | elt = rxeq_init_vals[ridx].rdesc & 0xF; | |
1223 | reg = rxeq_init_vals[ridx].rdesc >> 4; | |
1224 | loc = EPB_LOC(0, elt, reg); | |
1225 | val = rxeq_init_vals[ridx].rdata[vsel]; | |
1226 | /* mask of 0xFF, because hardware does full-byte store. */ | |
1227 | ret = ibsd_mod_allchnls(dd, loc, val, 0xFF); | |
1228 | if (ret < 0) | |
1229 | break; | |
1230 | } | |
1231 | return ret; | |
1232 | } | |
1233 | ||
1234 | /* | |
1235 | * Set the default values (row 0) for DDR Driver Demphasis. | |
1236 | * we do this initially and whenever we turn off IB-1.2 | |
1237 | * | |
1238 | * The "default" values for Rx equalization are also stored to | |
1239 | * SerDes registers. Formerly (and still default), we used set 2. | |
1240 | * For experimenting with cables and link-partners, we allow changing | |
1241 | * that via a module parameter. | |
1242 | */ | |
1243 | static unsigned qib_rxeq_set = 2; | |
1244 | module_param_named(rxeq_default_set, qib_rxeq_set, uint, | |
1245 | S_IWUSR | S_IRUGO); | |
1246 | MODULE_PARM_DESC(rxeq_default_set, | |
1247 | "Which set [0..3] of Rx Equalization values is default"); | |
1248 | ||
1249 | static int qib_internal_presets(struct qib_devdata *dd) | |
1250 | { | |
1251 | int ret = 0; | |
1252 | ||
1253 | ret = set_dds_vals(dd, dds_init_vals + DDS_3M); | |
1254 | ||
1255 | if (ret < 0) | |
1256 | qib_dev_err(dd, "Failed to set default DDS values\n"); | |
1257 | ret = set_rxeq_vals(dd, qib_rxeq_set & 3); | |
1258 | if (ret < 0) | |
1259 | qib_dev_err(dd, "Failed to set default RXEQ values\n"); | |
1260 | return ret; | |
1261 | } | |
1262 | ||
1263 | int qib_sd7220_presets(struct qib_devdata *dd) | |
1264 | { | |
1265 | int ret = 0; | |
1266 | ||
1267 | if (!dd->cspec->presets_needed) | |
1268 | return ret; | |
1269 | dd->cspec->presets_needed = 0; | |
1270 | /* Assert uC reset, so we don't clash with it. */ | |
1271 | qib_ibsd_reset(dd, 1); | |
1272 | udelay(2); | |
1273 | qib_sd_trimdone_monitor(dd, "link-down"); | |
1274 | ||
1275 | ret = qib_internal_presets(dd); | |
1276 | return ret; | |
1277 | } | |
1278 | ||
1279 | static int qib_sd_trimself(struct qib_devdata *dd, int val) | |
1280 | { | |
1281 | int loc = CMUCTRL5 | (1U << EPB_IB_QUAD0_CS_SHF); | |
1282 | ||
1283 | return qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF); | |
1284 | } | |
1285 | ||
1286 | static int qib_sd_early(struct qib_devdata *dd) | |
1287 | { | |
1288 | int ret; | |
1289 | ||
1290 | ret = ibsd_mod_allchnls(dd, RXHSCTRL0(0) | EPB_GLOBAL_WR, 0xD4, 0xFF); | |
1291 | if (ret < 0) | |
1292 | goto bail; | |
1293 | ret = ibsd_mod_allchnls(dd, START_EQ1(0) | EPB_GLOBAL_WR, 0x10, 0xFF); | |
1294 | if (ret < 0) | |
1295 | goto bail; | |
1296 | ret = ibsd_mod_allchnls(dd, START_EQ2(0) | EPB_GLOBAL_WR, 0x30, 0xFF); | |
1297 | bail: | |
1298 | return ret; | |
1299 | } | |
1300 | ||
1301 | #define BACTRL(chnl) EPB_LOC(chnl, 6, 0x0E) | |
1302 | #define LDOUTCTRL1(chnl) EPB_LOC(chnl, 7, 6) | |
1303 | #define RXHSSTATUS(chnl) EPB_LOC(chnl, 6, 0xF) | |
1304 | ||
1305 | static int qib_sd_dactrim(struct qib_devdata *dd) | |
1306 | { | |
1307 | int ret; | |
1308 | ||
1309 | ret = ibsd_mod_allchnls(dd, VCDL_DAC2(0) | EPB_GLOBAL_WR, 0x2D, 0xFF); | |
1310 | if (ret < 0) | |
1311 | goto bail; | |
1312 | ||
1313 | /* more fine-tuning of what will be default */ | |
1314 | ret = ibsd_mod_allchnls(dd, VCDL_CTRL2(0), 3, 0xF); | |
1315 | if (ret < 0) | |
1316 | goto bail; | |
1317 | ||
1318 | ret = ibsd_mod_allchnls(dd, BACTRL(0) | EPB_GLOBAL_WR, 0x40, 0xFF); | |
1319 | if (ret < 0) | |
1320 | goto bail; | |
1321 | ||
1322 | ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x04, 0xFF); | |
1323 | if (ret < 0) | |
1324 | goto bail; | |
1325 | ||
1326 | ret = ibsd_mod_allchnls(dd, RXHSSTATUS(0) | EPB_GLOBAL_WR, 0x04, 0xFF); | |
1327 | if (ret < 0) | |
1328 | goto bail; | |
1329 | ||
1330 | /* | |
1331 | * Delay for max possible number of steps, with slop. | |
1332 | * Each step is about 4usec. | |
1333 | */ | |
1334 | udelay(415); | |
1335 | ||
1336 | ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x00, 0xFF); | |
1337 | ||
1338 | bail: | |
1339 | return ret; | |
1340 | } | |
1341 | ||
1342 | #define RELOCK_FIRST_MS 3 | |
1343 | #define RXLSPPM(chan) EPB_LOC(chan, 0, 2) | |
1344 | void toggle_7220_rclkrls(struct qib_devdata *dd) | |
1345 | { | |
1346 | int loc = RXLSPPM(0) | EPB_GLOBAL_WR; | |
1347 | int ret; | |
1348 | ||
1349 | ret = ibsd_mod_allchnls(dd, loc, 0, 0x80); | |
1350 | if (ret < 0) | |
1351 | qib_dev_err(dd, "RCLKRLS failed to clear D7\n"); | |
1352 | else { | |
1353 | udelay(1); | |
1354 | ibsd_mod_allchnls(dd, loc, 0x80, 0x80); | |
1355 | } | |
1356 | /* And again for good measure */ | |
1357 | udelay(1); | |
1358 | ret = ibsd_mod_allchnls(dd, loc, 0, 0x80); | |
1359 | if (ret < 0) | |
1360 | qib_dev_err(dd, "RCLKRLS failed to clear D7\n"); | |
1361 | else { | |
1362 | udelay(1); | |
1363 | ibsd_mod_allchnls(dd, loc, 0x80, 0x80); | |
1364 | } | |
1365 | /* Now reset xgxs and IBC to complete the recovery */ | |
1366 | dd->f_xgxs_reset(dd->pport); | |
1367 | } | |
1368 | ||
1369 | /* | |
1370 | * Shut down the timer that polls for relock occasions, if needed | |
1371 | * this is "hooked" from qib_7220_quiet_serdes(), which is called | |
1372 | * just before qib_shutdown_device() in qib_driver.c shuts down all | |
1373 | * the other timers | |
1374 | */ | |
1375 | void shutdown_7220_relock_poll(struct qib_devdata *dd) | |
1376 | { | |
1377 | if (dd->cspec->relock_timer_active) | |
1378 | del_timer_sync(&dd->cspec->relock_timer); | |
1379 | } | |
1380 | ||
1381 | static unsigned qib_relock_by_timer = 1; | |
1382 | module_param_named(relock_by_timer, qib_relock_by_timer, uint, | |
1383 | S_IWUSR | S_IRUGO); | |
1384 | MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up"); | |
1385 | ||
1386 | static void qib_run_relock(unsigned long opaque) | |
1387 | { | |
1388 | struct qib_devdata *dd = (struct qib_devdata *)opaque; | |
1389 | struct qib_pportdata *ppd = dd->pport; | |
1390 | struct qib_chip_specific *cs = dd->cspec; | |
1391 | int timeoff; | |
1392 | ||
1393 | /* | |
1394 | * Check link-training state for "stuck" state, when down. | |
1395 | * if found, try relock and schedule another try at | |
1396 | * exponentially growing delay, maxed at one second. | |
1397 | * if not stuck, our work is done. | |
1398 | */ | |
1399 | if ((dd->flags & QIB_INITTED) && !(ppd->lflags & | |
1400 | (QIBL_IB_AUTONEG_INPROG | QIBL_LINKINIT | QIBL_LINKARMED | | |
1401 | QIBL_LINKACTIVE))) { | |
1402 | if (qib_relock_by_timer) { | |
1403 | if (!(ppd->lflags & QIBL_IB_LINK_DISABLED)) | |
1404 | toggle_7220_rclkrls(dd); | |
1405 | } | |
1406 | /* re-set timer for next check */ | |
1407 | timeoff = cs->relock_interval << 1; | |
1408 | if (timeoff > HZ) | |
1409 | timeoff = HZ; | |
1410 | cs->relock_interval = timeoff; | |
1411 | } else | |
1412 | timeoff = HZ; | |
1413 | mod_timer(&cs->relock_timer, jiffies + timeoff); | |
1414 | } | |
1415 | ||
1416 | void set_7220_relock_poll(struct qib_devdata *dd, int ibup) | |
1417 | { | |
1418 | struct qib_chip_specific *cs = dd->cspec; | |
1419 | ||
1420 | if (ibup) { | |
1421 | /* We are now up, relax timer to 1 second interval */ | |
1422 | if (cs->relock_timer_active) { | |
1423 | cs->relock_interval = HZ; | |
1424 | mod_timer(&cs->relock_timer, jiffies + HZ); | |
1425 | } | |
1426 | } else { | |
1427 | /* Transition to down, (re-)set timer to short interval. */ | |
1428 | unsigned int timeout; | |
1429 | ||
1430 | timeout = msecs_to_jiffies(RELOCK_FIRST_MS); | |
1431 | if (timeout == 0) | |
1432 | timeout = 1; | |
1433 | /* If timer has not yet been started, do so. */ | |
1434 | if (!cs->relock_timer_active) { | |
1435 | cs->relock_timer_active = 1; | |
1436 | init_timer(&cs->relock_timer); | |
1437 | cs->relock_timer.function = qib_run_relock; | |
1438 | cs->relock_timer.data = (unsigned long) dd; | |
1439 | cs->relock_interval = timeout; | |
1440 | cs->relock_timer.expires = jiffies + timeout; | |
1441 | add_timer(&cs->relock_timer); | |
1442 | } else { | |
1443 | cs->relock_interval = timeout; | |
1444 | mod_timer(&cs->relock_timer, jiffies + timeout); | |
1445 | } | |
1446 | } | |
1447 | } |