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Commit | Line | Data |
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11f5b30d RI |
1 | /* |
2 | * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix | |
3 | * keyboard controller | |
4 | * | |
5 | * Copyright (c) 2009-2011, NVIDIA Corporation. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | */ | |
21 | ||
3f27757a | 22 | #include <linux/kernel.h> |
11f5b30d RI |
23 | #include <linux/module.h> |
24 | #include <linux/input.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
a445c7f0 | 29 | #include <linux/of.h> |
e10af9e7 | 30 | #include <linux/of_device.h> |
11f5b30d RI |
31 | #include <linux/clk.h> |
32 | #include <linux/slab.h> | |
9eee07d3 | 33 | #include <linux/input/matrix_keypad.h> |
61fd290d | 34 | #include <linux/clk/tegra.h> |
ba52a7fc | 35 | #include <linux/err.h> |
11f5b30d | 36 | |
9eee07d3 SW |
37 | #define KBC_MAX_KPENT 8 |
38 | ||
e10af9e7 LD |
39 | /* Maximum row/column supported by Tegra KBC yet is 16x8 */ |
40 | #define KBC_MAX_GPIO 24 | |
41 | /* Maximum keys supported by Tegra KBC yet is 16 x 8*/ | |
42 | #define KBC_MAX_KEY (16 * 8) | |
9eee07d3 | 43 | |
11f5b30d RI |
44 | #define KBC_MAX_DEBOUNCE_CNT 0x3ffu |
45 | ||
46 | /* KBC row scan time and delay for beginning the row scan. */ | |
47 | #define KBC_ROW_SCAN_TIME 16 | |
48 | #define KBC_ROW_SCAN_DLY 5 | |
49 | ||
50 | /* KBC uses a 32KHz clock so a cycle = 1/32Khz */ | |
3f27757a | 51 | #define KBC_CYCLE_MS 32 |
11f5b30d RI |
52 | |
53 | /* KBC Registers */ | |
54 | ||
55 | /* KBC Control Register */ | |
56 | #define KBC_CONTROL_0 0x0 | |
57 | #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14) | |
58 | #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4) | |
59 | #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) | |
b6834b02 | 60 | #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1) |
11f5b30d RI |
61 | #define KBC_CONTROL_KBC_EN (1 << 0) |
62 | ||
63 | /* KBC Interrupt Register */ | |
64 | #define KBC_INT_0 0x4 | |
65 | #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) | |
fd0fc213 | 66 | #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0) |
11f5b30d RI |
67 | |
68 | #define KBC_ROW_CFG0_0 0x8 | |
69 | #define KBC_COL_CFG0_0 0x18 | |
d0d150ec | 70 | #define KBC_TO_CNT_0 0x24 |
11f5b30d RI |
71 | #define KBC_INIT_DLY_0 0x28 |
72 | #define KBC_RPT_DLY_0 0x2c | |
73 | #define KBC_KP_ENT0_0 0x30 | |
74 | #define KBC_KP_ENT1_0 0x34 | |
75 | #define KBC_ROW0_MASK_0 0x38 | |
76 | ||
77 | #define KBC_ROW_SHIFT 3 | |
78 | ||
9eee07d3 SW |
79 | enum tegra_pin_type { |
80 | PIN_CFG_IGNORE, | |
81 | PIN_CFG_COL, | |
82 | PIN_CFG_ROW, | |
83 | }; | |
84 | ||
e10af9e7 LD |
85 | /* Tegra KBC hw support */ |
86 | struct tegra_kbc_hw_support { | |
87 | int max_rows; | |
88 | int max_columns; | |
89 | }; | |
90 | ||
9eee07d3 SW |
91 | struct tegra_kbc_pin_cfg { |
92 | enum tegra_pin_type type; | |
93 | unsigned char num; | |
94 | }; | |
95 | ||
11f5b30d | 96 | struct tegra_kbc { |
9eee07d3 SW |
97 | struct device *dev; |
98 | unsigned int debounce_cnt; | |
99 | unsigned int repeat_cnt; | |
100 | struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; | |
101 | const struct matrix_keymap_data *keymap_data; | |
102 | bool wakeup; | |
11f5b30d RI |
103 | void __iomem *mmio; |
104 | struct input_dev *idev; | |
9eee07d3 | 105 | int irq; |
11f5b30d RI |
106 | spinlock_t lock; |
107 | unsigned int repoll_dly; | |
108 | unsigned long cp_dly_jiffies; | |
d0d150ec | 109 | unsigned int cp_to_wkup_dly; |
4e8b65f6 | 110 | bool use_fn_map; |
34abeeb2 | 111 | bool use_ghost_filter; |
fd0fc213 | 112 | bool keypress_caused_wake; |
4e8b65f6 | 113 | unsigned short keycode[KBC_MAX_KEY * 2]; |
11f5b30d RI |
114 | unsigned short current_keys[KBC_MAX_KPENT]; |
115 | unsigned int num_pressed_keys; | |
fd0fc213 | 116 | u32 wakeup_key; |
11f5b30d RI |
117 | struct timer_list timer; |
118 | struct clk *clk; | |
e10af9e7 LD |
119 | const struct tegra_kbc_hw_support *hw_support; |
120 | int max_keys; | |
121 | int num_rows_and_columns; | |
11f5b30d RI |
122 | }; |
123 | ||
11f5b30d RI |
124 | static void tegra_kbc_report_released_keys(struct input_dev *input, |
125 | unsigned short old_keycodes[], | |
126 | unsigned int old_num_keys, | |
127 | unsigned short new_keycodes[], | |
128 | unsigned int new_num_keys) | |
129 | { | |
130 | unsigned int i, j; | |
131 | ||
132 | for (i = 0; i < old_num_keys; i++) { | |
133 | for (j = 0; j < new_num_keys; j++) | |
134 | if (old_keycodes[i] == new_keycodes[j]) | |
135 | break; | |
136 | ||
137 | if (j == new_num_keys) | |
138 | input_report_key(input, old_keycodes[i], 0); | |
139 | } | |
140 | } | |
141 | ||
142 | static void tegra_kbc_report_pressed_keys(struct input_dev *input, | |
143 | unsigned char scancodes[], | |
144 | unsigned short keycodes[], | |
145 | unsigned int num_pressed_keys) | |
146 | { | |
147 | unsigned int i; | |
148 | ||
149 | for (i = 0; i < num_pressed_keys; i++) { | |
150 | input_event(input, EV_MSC, MSC_SCAN, scancodes[i]); | |
151 | input_report_key(input, keycodes[i], 1); | |
152 | } | |
153 | } | |
154 | ||
155 | static void tegra_kbc_report_keys(struct tegra_kbc *kbc) | |
156 | { | |
157 | unsigned char scancodes[KBC_MAX_KPENT]; | |
158 | unsigned short keycodes[KBC_MAX_KPENT]; | |
159 | u32 val = 0; | |
160 | unsigned int i; | |
161 | unsigned int num_down = 0; | |
4e8b65f6 | 162 | bool fn_keypress = false; |
34abeeb2 RI |
163 | bool key_in_same_row = false; |
164 | bool key_in_same_col = false; | |
11f5b30d | 165 | |
11f5b30d RI |
166 | for (i = 0; i < KBC_MAX_KPENT; i++) { |
167 | if ((i % 4) == 0) | |
168 | val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); | |
169 | ||
170 | if (val & 0x80) { | |
171 | unsigned int col = val & 0x07; | |
172 | unsigned int row = (val >> 3) & 0x0f; | |
173 | unsigned char scancode = | |
174 | MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT); | |
175 | ||
176 | scancodes[num_down] = scancode; | |
4e8b65f6 RI |
177 | keycodes[num_down] = kbc->keycode[scancode]; |
178 | /* If driver uses Fn map, do not report the Fn key. */ | |
179 | if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) | |
180 | fn_keypress = true; | |
181 | else | |
182 | num_down++; | |
11f5b30d RI |
183 | } |
184 | ||
185 | val >>= 8; | |
186 | } | |
4e8b65f6 | 187 | |
34abeeb2 RI |
188 | /* |
189 | * Matrix keyboard designs are prone to keyboard ghosting. | |
190 | * Ghosting occurs if there are 3 keys such that - | |
191 | * any 2 of the 3 keys share a row, and any 2 of them share a column. | |
192 | * If so ignore the key presses for this iteration. | |
193 | */ | |
95439cba | 194 | if (kbc->use_ghost_filter && num_down >= 3) { |
34abeeb2 RI |
195 | for (i = 0; i < num_down; i++) { |
196 | unsigned int j; | |
197 | u8 curr_col = scancodes[i] & 0x07; | |
198 | u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT; | |
199 | ||
200 | /* | |
201 | * Find 2 keys such that one key is in the same row | |
202 | * and the other is in the same column as the i-th key. | |
203 | */ | |
204 | for (j = i + 1; j < num_down; j++) { | |
205 | u8 col = scancodes[j] & 0x07; | |
206 | u8 row = scancodes[j] >> KBC_ROW_SHIFT; | |
207 | ||
208 | if (col == curr_col) | |
209 | key_in_same_col = true; | |
210 | if (row == curr_row) | |
211 | key_in_same_row = true; | |
212 | } | |
213 | } | |
214 | } | |
215 | ||
4e8b65f6 RI |
216 | /* |
217 | * If the platform uses Fn keymaps, translate keys on a Fn keypress. | |
e10af9e7 | 218 | * Function keycodes are max_keys apart from the plain keycodes. |
4e8b65f6 RI |
219 | */ |
220 | if (fn_keypress) { | |
221 | for (i = 0; i < num_down; i++) { | |
e10af9e7 | 222 | scancodes[i] += kbc->max_keys; |
4e8b65f6 RI |
223 | keycodes[i] = kbc->keycode[scancodes[i]]; |
224 | } | |
225 | } | |
226 | ||
34abeeb2 RI |
227 | /* Ignore the key presses for this iteration? */ |
228 | if (key_in_same_col && key_in_same_row) | |
229 | return; | |
230 | ||
11f5b30d RI |
231 | tegra_kbc_report_released_keys(kbc->idev, |
232 | kbc->current_keys, kbc->num_pressed_keys, | |
233 | keycodes, num_down); | |
234 | tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down); | |
235 | input_sync(kbc->idev); | |
236 | ||
237 | memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys)); | |
238 | kbc->num_pressed_keys = num_down; | |
239 | } | |
240 | ||
d0d150ec RI |
241 | static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable) |
242 | { | |
243 | u32 val; | |
244 | ||
245 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
246 | if (enable) | |
247 | val |= KBC_CONTROL_FIFO_CNT_INT_EN; | |
248 | else | |
249 | val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; | |
250 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
251 | } | |
252 | ||
11f5b30d RI |
253 | static void tegra_kbc_keypress_timer(unsigned long data) |
254 | { | |
255 | struct tegra_kbc *kbc = (struct tegra_kbc *)data; | |
256 | unsigned long flags; | |
257 | u32 val; | |
258 | unsigned int i; | |
259 | ||
95439cba DT |
260 | spin_lock_irqsave(&kbc->lock, flags); |
261 | ||
11f5b30d RI |
262 | val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; |
263 | if (val) { | |
264 | unsigned long dly; | |
265 | ||
266 | tegra_kbc_report_keys(kbc); | |
267 | ||
268 | /* | |
269 | * If more than one keys are pressed we need not wait | |
270 | * for the repoll delay. | |
271 | */ | |
272 | dly = (val == 1) ? kbc->repoll_dly : 1; | |
273 | mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); | |
274 | } else { | |
275 | /* Release any pressed keys and exit the polling loop */ | |
276 | for (i = 0; i < kbc->num_pressed_keys; i++) | |
277 | input_report_key(kbc->idev, kbc->current_keys[i], 0); | |
278 | input_sync(kbc->idev); | |
279 | ||
280 | kbc->num_pressed_keys = 0; | |
281 | ||
282 | /* All keys are released so enable the keypress interrupt */ | |
d0d150ec | 283 | tegra_kbc_set_fifo_interrupt(kbc, true); |
11f5b30d | 284 | } |
95439cba DT |
285 | |
286 | spin_unlock_irqrestore(&kbc->lock, flags); | |
11f5b30d RI |
287 | } |
288 | ||
289 | static irqreturn_t tegra_kbc_isr(int irq, void *args) | |
290 | { | |
291 | struct tegra_kbc *kbc = args; | |
95439cba | 292 | unsigned long flags; |
d0d150ec | 293 | u32 val; |
11f5b30d | 294 | |
95439cba | 295 | spin_lock_irqsave(&kbc->lock, flags); |
11f5b30d RI |
296 | |
297 | /* | |
298 | * Quickly bail out & reenable interrupts if the fifo threshold | |
299 | * count interrupt wasn't the interrupt source | |
300 | */ | |
301 | val = readl(kbc->mmio + KBC_INT_0); | |
302 | writel(val, kbc->mmio + KBC_INT_0); | |
303 | ||
304 | if (val & KBC_INT_FIFO_CNT_INT_STATUS) { | |
305 | /* | |
95439cba DT |
306 | * Until all keys are released, defer further processing to |
307 | * the polling loop in tegra_kbc_keypress_timer. | |
11f5b30d | 308 | */ |
95439cba | 309 | tegra_kbc_set_fifo_interrupt(kbc, false); |
11f5b30d | 310 | mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies); |
fd0fc213 RI |
311 | } else if (val & KBC_INT_KEYPRESS_INT_STATUS) { |
312 | /* We can be here only through system resume path */ | |
313 | kbc->keypress_caused_wake = true; | |
11f5b30d RI |
314 | } |
315 | ||
95439cba DT |
316 | spin_unlock_irqrestore(&kbc->lock, flags); |
317 | ||
11f5b30d RI |
318 | return IRQ_HANDLED; |
319 | } | |
320 | ||
321 | static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter) | |
322 | { | |
11f5b30d RI |
323 | int i; |
324 | unsigned int rst_val; | |
325 | ||
baafb435 | 326 | /* Either mask all keys or none. */ |
9eee07d3 | 327 | rst_val = (filter && !kbc->wakeup) ? ~0 : 0; |
11f5b30d | 328 | |
e10af9e7 | 329 | for (i = 0; i < kbc->hw_support->max_rows; i++) |
11f5b30d | 330 | writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); |
11f5b30d RI |
331 | } |
332 | ||
333 | static void tegra_kbc_config_pins(struct tegra_kbc *kbc) | |
334 | { | |
11f5b30d RI |
335 | int i; |
336 | ||
337 | for (i = 0; i < KBC_MAX_GPIO; i++) { | |
338 | u32 r_shft = 5 * (i % 6); | |
339 | u32 c_shft = 4 * (i % 8); | |
7530c4a1 RI |
340 | u32 r_mask = 0x1f << r_shft; |
341 | u32 c_mask = 0x0f << c_shft; | |
11f5b30d RI |
342 | u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0; |
343 | u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0; | |
344 | u32 row_cfg = readl(kbc->mmio + r_offs); | |
345 | u32 col_cfg = readl(kbc->mmio + c_offs); | |
346 | ||
347 | row_cfg &= ~r_mask; | |
348 | col_cfg &= ~c_mask; | |
349 | ||
9eee07d3 | 350 | switch (kbc->pin_cfg[i].type) { |
023cea0e | 351 | case PIN_CFG_ROW: |
9eee07d3 | 352 | row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft; |
023cea0e SR |
353 | break; |
354 | ||
355 | case PIN_CFG_COL: | |
9eee07d3 | 356 | col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft; |
023cea0e SR |
357 | break; |
358 | ||
359 | case PIN_CFG_IGNORE: | |
360 | break; | |
361 | } | |
11f5b30d RI |
362 | |
363 | writel(row_cfg, kbc->mmio + r_offs); | |
364 | writel(col_cfg, kbc->mmio + c_offs); | |
365 | } | |
366 | } | |
367 | ||
368 | static int tegra_kbc_start(struct tegra_kbc *kbc) | |
369 | { | |
11f5b30d RI |
370 | unsigned int debounce_cnt; |
371 | u32 val = 0; | |
372 | ||
f762470b | 373 | clk_prepare_enable(kbc->clk); |
11f5b30d RI |
374 | |
375 | /* Reset the KBC controller to clear all previous status.*/ | |
376 | tegra_periph_reset_assert(kbc->clk); | |
377 | udelay(100); | |
378 | tegra_periph_reset_deassert(kbc->clk); | |
379 | udelay(100); | |
380 | ||
381 | tegra_kbc_config_pins(kbc); | |
382 | tegra_kbc_setup_wakekeys(kbc, false); | |
383 | ||
9eee07d3 | 384 | writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0); |
11f5b30d RI |
385 | |
386 | /* Keyboard debounce count is maximum of 12 bits. */ | |
9eee07d3 | 387 | debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); |
11f5b30d RI |
388 | val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); |
389 | val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ | |
390 | val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ | |
391 | val |= KBC_CONTROL_KBC_EN; /* enable */ | |
392 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
393 | ||
394 | /* | |
395 | * Compute the delay(ns) from interrupt mode to continuous polling | |
396 | * mode so the timer routine is scheduled appropriately. | |
397 | */ | |
398 | val = readl(kbc->mmio + KBC_INIT_DLY_0); | |
399 | kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); | |
400 | ||
401 | kbc->num_pressed_keys = 0; | |
402 | ||
403 | /* | |
404 | * Atomically clear out any remaining entries in the key FIFO | |
405 | * and enable keyboard interrupts. | |
406 | */ | |
11f5b30d RI |
407 | while (1) { |
408 | val = readl(kbc->mmio + KBC_INT_0); | |
409 | val >>= 4; | |
410 | if (!val) | |
411 | break; | |
412 | ||
413 | val = readl(kbc->mmio + KBC_KP_ENT0_0); | |
414 | val = readl(kbc->mmio + KBC_KP_ENT1_0); | |
415 | } | |
416 | writel(0x7, kbc->mmio + KBC_INT_0); | |
11f5b30d RI |
417 | |
418 | enable_irq(kbc->irq); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | static void tegra_kbc_stop(struct tegra_kbc *kbc) | |
424 | { | |
425 | unsigned long flags; | |
426 | u32 val; | |
427 | ||
428 | spin_lock_irqsave(&kbc->lock, flags); | |
429 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
430 | val &= ~1; | |
431 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
432 | spin_unlock_irqrestore(&kbc->lock, flags); | |
433 | ||
434 | disable_irq(kbc->irq); | |
435 | del_timer_sync(&kbc->timer); | |
436 | ||
f762470b | 437 | clk_disable_unprepare(kbc->clk); |
11f5b30d RI |
438 | } |
439 | ||
440 | static int tegra_kbc_open(struct input_dev *dev) | |
441 | { | |
442 | struct tegra_kbc *kbc = input_get_drvdata(dev); | |
443 | ||
444 | return tegra_kbc_start(kbc); | |
445 | } | |
446 | ||
447 | static void tegra_kbc_close(struct input_dev *dev) | |
448 | { | |
449 | struct tegra_kbc *kbc = input_get_drvdata(dev); | |
450 | ||
451 | return tegra_kbc_stop(kbc); | |
452 | } | |
453 | ||
9eee07d3 SW |
454 | static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc, |
455 | unsigned int *num_rows) | |
11f5b30d RI |
456 | { |
457 | int i; | |
458 | ||
459 | *num_rows = 0; | |
460 | ||
461 | for (i = 0; i < KBC_MAX_GPIO; i++) { | |
9eee07d3 | 462 | const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i]; |
11f5b30d | 463 | |
023cea0e SR |
464 | switch (pin_cfg->type) { |
465 | case PIN_CFG_ROW: | |
e10af9e7 | 466 | if (pin_cfg->num >= kbc->hw_support->max_rows) { |
9eee07d3 | 467 | dev_err(kbc->dev, |
11f5b30d RI |
468 | "pin_cfg[%d]: invalid row number %d\n", |
469 | i, pin_cfg->num); | |
470 | return false; | |
471 | } | |
472 | (*num_rows)++; | |
023cea0e SR |
473 | break; |
474 | ||
475 | case PIN_CFG_COL: | |
e10af9e7 | 476 | if (pin_cfg->num >= kbc->hw_support->max_columns) { |
9eee07d3 | 477 | dev_err(kbc->dev, |
11f5b30d RI |
478 | "pin_cfg[%d]: invalid column number %d\n", |
479 | i, pin_cfg->num); | |
480 | return false; | |
481 | } | |
023cea0e SR |
482 | break; |
483 | ||
484 | case PIN_CFG_IGNORE: | |
485 | break; | |
486 | ||
487 | default: | |
9eee07d3 | 488 | dev_err(kbc->dev, |
023cea0e SR |
489 | "pin_cfg[%d]: invalid entry type %d\n", |
490 | pin_cfg->type, pin_cfg->num); | |
491 | return false; | |
11f5b30d RI |
492 | } |
493 | } | |
494 | ||
495 | return true; | |
496 | } | |
497 | ||
9eee07d3 | 498 | static int tegra_kbc_parse_dt(struct tegra_kbc *kbc) |
a445c7f0 | 499 | { |
9eee07d3 | 500 | struct device_node *np = kbc->dev->of_node; |
145e9734 OJ |
501 | u32 prop; |
502 | int i; | |
88390243 LD |
503 | u32 num_rows = 0; |
504 | u32 num_cols = 0; | |
505 | u32 cols_cfg[KBC_MAX_GPIO]; | |
506 | u32 rows_cfg[KBC_MAX_GPIO]; | |
507 | int proplen; | |
508 | int ret; | |
509 | ||
145e9734 | 510 | if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop)) |
9eee07d3 | 511 | kbc->debounce_cnt = prop; |
a445c7f0 | 512 | |
145e9734 | 513 | if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop)) |
9eee07d3 | 514 | kbc->repeat_cnt = prop; |
a445c7f0 | 515 | |
145e9734 | 516 | if (of_find_property(np, "nvidia,needs-ghost-filter", NULL)) |
9eee07d3 | 517 | kbc->use_ghost_filter = true; |
a445c7f0 | 518 | |
145e9734 | 519 | if (of_find_property(np, "nvidia,wakeup-source", NULL)) |
9eee07d3 | 520 | kbc->wakeup = true; |
a445c7f0 | 521 | |
88390243 | 522 | if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) { |
9eee07d3 SW |
523 | dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n"); |
524 | return -ENOENT; | |
88390243 LD |
525 | } |
526 | num_rows = proplen / sizeof(u32); | |
527 | ||
528 | if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) { | |
9eee07d3 SW |
529 | dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n"); |
530 | return -ENOENT; | |
88390243 LD |
531 | } |
532 | num_cols = proplen / sizeof(u32); | |
533 | ||
e10af9e7 LD |
534 | if (num_rows > kbc->hw_support->max_rows) { |
535 | dev_err(kbc->dev, | |
536 | "Number of rows is more than supported by hardware\n"); | |
537 | return -EINVAL; | |
538 | } | |
539 | ||
540 | if (num_cols > kbc->hw_support->max_columns) { | |
541 | dev_err(kbc->dev, | |
542 | "Number of cols is more than supported by hardware\n"); | |
543 | return -EINVAL; | |
544 | } | |
545 | ||
88390243 | 546 | if (!of_get_property(np, "linux,keymap", &proplen)) { |
9eee07d3 SW |
547 | dev_err(kbc->dev, "property linux,keymap not found\n"); |
548 | return -ENOENT; | |
a445c7f0 OJ |
549 | } |
550 | ||
88390243 | 551 | if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) { |
9eee07d3 | 552 | dev_err(kbc->dev, |
88390243 | 553 | "keypad rows/columns not porperly specified\n"); |
9eee07d3 | 554 | return -EINVAL; |
88390243 LD |
555 | } |
556 | ||
557 | /* Set all pins as non-configured */ | |
e10af9e7 | 558 | for (i = 0; i < kbc->num_rows_and_columns; i++) |
9eee07d3 | 559 | kbc->pin_cfg[i].type = PIN_CFG_IGNORE; |
88390243 LD |
560 | |
561 | ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins", | |
562 | rows_cfg, num_rows); | |
563 | if (ret < 0) { | |
9eee07d3 SW |
564 | dev_err(kbc->dev, "Rows configurations are not proper\n"); |
565 | return -EINVAL; | |
88390243 LD |
566 | } |
567 | ||
568 | ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins", | |
569 | cols_cfg, num_cols); | |
570 | if (ret < 0) { | |
9eee07d3 SW |
571 | dev_err(kbc->dev, "Cols configurations are not proper\n"); |
572 | return -EINVAL; | |
88390243 LD |
573 | } |
574 | ||
575 | for (i = 0; i < num_rows; i++) { | |
9eee07d3 SW |
576 | kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW; |
577 | kbc->pin_cfg[rows_cfg[i]].num = i; | |
88390243 LD |
578 | } |
579 | ||
580 | for (i = 0; i < num_cols; i++) { | |
9eee07d3 SW |
581 | kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL; |
582 | kbc->pin_cfg[cols_cfg[i]].num = i; | |
a445c7f0 OJ |
583 | } |
584 | ||
9eee07d3 | 585 | return 0; |
a445c7f0 | 586 | } |
a445c7f0 | 587 | |
e10af9e7 LD |
588 | static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = { |
589 | .max_rows = 16, | |
590 | .max_columns = 8, | |
591 | }; | |
592 | ||
593 | static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = { | |
594 | .max_rows = 11, | |
595 | .max_columns = 8, | |
596 | }; | |
597 | ||
598 | static const struct of_device_id tegra_kbc_of_match[] = { | |
599 | { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support}, | |
600 | { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support}, | |
601 | { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support}, | |
602 | { }, | |
603 | }; | |
604 | MODULE_DEVICE_TABLE(of, tegra_kbc_of_match); | |
605 | ||
5298cc4c | 606 | static int tegra_kbc_probe(struct platform_device *pdev) |
11f5b30d | 607 | { |
11f5b30d | 608 | struct tegra_kbc *kbc; |
11f5b30d | 609 | struct resource *res; |
11f5b30d | 610 | int err; |
11f5b30d RI |
611 | int num_rows = 0; |
612 | unsigned int debounce_cnt; | |
613 | unsigned int scan_time_rows; | |
e10af9e7 LD |
614 | unsigned int keymap_rows; |
615 | const struct of_device_id *match; | |
616 | ||
617 | match = of_match_device(of_match_ptr(tegra_kbc_of_match), &pdev->dev); | |
11f5b30d | 618 | |
9eee07d3 SW |
619 | kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL); |
620 | if (!kbc) { | |
621 | dev_err(&pdev->dev, "failed to alloc memory for kbc\n"); | |
622 | return -ENOMEM; | |
623 | } | |
624 | ||
625 | kbc->dev = &pdev->dev; | |
e10af9e7 LD |
626 | kbc->hw_support = match->data; |
627 | kbc->max_keys = kbc->hw_support->max_rows * | |
628 | kbc->hw_support->max_columns; | |
629 | kbc->num_rows_and_columns = kbc->hw_support->max_rows + | |
630 | kbc->hw_support->max_columns; | |
631 | keymap_rows = kbc->max_keys; | |
9eee07d3 | 632 | spin_lock_init(&kbc->lock); |
11f5b30d | 633 | |
9eee07d3 SW |
634 | err = tegra_kbc_parse_dt(kbc); |
635 | if (err) | |
636 | return err; | |
a445c7f0 | 637 | |
9eee07d3 | 638 | if (!tegra_kbc_check_pin_cfg(kbc, &num_rows)) |
00eb81e5 LD |
639 | return -EINVAL; |
640 | ||
9eee07d3 SW |
641 | kbc->irq = platform_get_irq(pdev, 0); |
642 | if (kbc->irq < 0) { | |
11f5b30d | 643 | dev_err(&pdev->dev, "failed to get keyboard IRQ\n"); |
00eb81e5 | 644 | return -ENXIO; |
11f5b30d RI |
645 | } |
646 | ||
9eee07d3 SW |
647 | kbc->idev = devm_input_allocate_device(&pdev->dev); |
648 | if (!kbc->idev) { | |
00eb81e5 LD |
649 | dev_err(&pdev->dev, "failed to allocate input device\n"); |
650 | return -ENOMEM; | |
11f5b30d RI |
651 | } |
652 | ||
11f5b30d RI |
653 | setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc); |
654 | ||
eacd0c47 | 655 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
ba52a7fc SK |
656 | kbc->mmio = devm_ioremap_resource(&pdev->dev, res); |
657 | if (IS_ERR(kbc->mmio)) | |
658 | return PTR_ERR(kbc->mmio); | |
11f5b30d | 659 | |
00eb81e5 | 660 | kbc->clk = devm_clk_get(&pdev->dev, NULL); |
11f5b30d RI |
661 | if (IS_ERR(kbc->clk)) { |
662 | dev_err(&pdev->dev, "failed to get keyboard clock\n"); | |
00eb81e5 | 663 | return PTR_ERR(kbc->clk); |
11f5b30d RI |
664 | } |
665 | ||
11f5b30d RI |
666 | /* |
667 | * The time delay between two consecutive reads of the FIFO is | |
668 | * the sum of the repeat time and the time taken for scanning | |
669 | * the rows. There is an additional delay before the row scanning | |
670 | * starts. The repoll delay is computed in milliseconds. | |
671 | */ | |
9eee07d3 | 672 | debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); |
11f5b30d | 673 | scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows; |
9eee07d3 | 674 | kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt; |
3f27757a | 675 | kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS); |
11f5b30d | 676 | |
9eee07d3 SW |
677 | kbc->idev->name = pdev->name; |
678 | kbc->idev->id.bustype = BUS_HOST; | |
679 | kbc->idev->dev.parent = &pdev->dev; | |
680 | kbc->idev->open = tegra_kbc_open; | |
681 | kbc->idev->close = tegra_kbc_close; | |
11f5b30d | 682 | |
9eee07d3 | 683 | if (kbc->keymap_data && kbc->use_fn_map) |
914e5976 LD |
684 | keymap_rows *= 2; |
685 | ||
9eee07d3 | 686 | err = matrix_keypad_build_keymap(kbc->keymap_data, NULL, |
e10af9e7 LD |
687 | keymap_rows, |
688 | kbc->hw_support->max_columns, | |
9eee07d3 | 689 | kbc->keycode, kbc->idev); |
1932811f | 690 | if (err) { |
b45c8f35 | 691 | dev_err(&pdev->dev, "failed to setup keymap\n"); |
00eb81e5 | 692 | return err; |
1932811f DT |
693 | } |
694 | ||
9eee07d3 SW |
695 | __set_bit(EV_REP, kbc->idev->evbit); |
696 | input_set_capability(kbc->idev, EV_MSC, MSC_SCAN); | |
1932811f | 697 | |
9eee07d3 | 698 | input_set_drvdata(kbc->idev, kbc); |
11f5b30d | 699 | |
00eb81e5 | 700 | err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr, |
fd0fc213 | 701 | IRQF_NO_SUSPEND | IRQF_TRIGGER_HIGH, pdev->name, kbc); |
11f5b30d RI |
702 | if (err) { |
703 | dev_err(&pdev->dev, "failed to request keyboard IRQ\n"); | |
00eb81e5 | 704 | return err; |
11f5b30d RI |
705 | } |
706 | ||
707 | disable_irq(kbc->irq); | |
708 | ||
709 | err = input_register_device(kbc->idev); | |
710 | if (err) { | |
711 | dev_err(&pdev->dev, "failed to register input device\n"); | |
00eb81e5 | 712 | return err; |
11f5b30d RI |
713 | } |
714 | ||
715 | platform_set_drvdata(pdev, kbc); | |
9eee07d3 | 716 | device_init_wakeup(&pdev->dev, kbc->wakeup); |
11f5b30d | 717 | |
11f5b30d RI |
718 | return 0; |
719 | } | |
720 | ||
721 | #ifdef CONFIG_PM_SLEEP | |
1c407a1b LD |
722 | static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable) |
723 | { | |
724 | u32 val; | |
725 | ||
726 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
727 | if (enable) | |
728 | val |= KBC_CONTROL_KEYPRESS_INT_EN; | |
729 | else | |
730 | val &= ~KBC_CONTROL_KEYPRESS_INT_EN; | |
731 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
732 | } | |
733 | ||
11f5b30d RI |
734 | static int tegra_kbc_suspend(struct device *dev) |
735 | { | |
736 | struct platform_device *pdev = to_platform_device(dev); | |
737 | struct tegra_kbc *kbc = platform_get_drvdata(pdev); | |
738 | ||
d0d150ec | 739 | mutex_lock(&kbc->idev->mutex); |
11f5b30d | 740 | if (device_may_wakeup(&pdev->dev)) { |
d0d150ec RI |
741 | disable_irq(kbc->irq); |
742 | del_timer_sync(&kbc->timer); | |
743 | tegra_kbc_set_fifo_interrupt(kbc, false); | |
744 | ||
11f5b30d RI |
745 | /* Forcefully clear the interrupt status */ |
746 | writel(0x7, kbc->mmio + KBC_INT_0); | |
d0d150ec RI |
747 | /* |
748 | * Store the previous resident time of continuous polling mode. | |
749 | * Force the keyboard into interrupt mode. | |
750 | */ | |
751 | kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0); | |
752 | writel(0, kbc->mmio + KBC_TO_CNT_0); | |
753 | ||
754 | tegra_kbc_setup_wakekeys(kbc, true); | |
11f5b30d | 755 | msleep(30); |
d0d150ec | 756 | |
fd0fc213 | 757 | kbc->keypress_caused_wake = false; |
b6834b02 RI |
758 | /* Enable keypress interrupt before going into suspend. */ |
759 | tegra_kbc_set_keypress_interrupt(kbc, true); | |
fd0fc213 | 760 | enable_irq(kbc->irq); |
d0d150ec | 761 | enable_irq_wake(kbc->irq); |
11f5b30d | 762 | } else { |
11f5b30d RI |
763 | if (kbc->idev->users) |
764 | tegra_kbc_stop(kbc); | |
11f5b30d | 765 | } |
d0d150ec | 766 | mutex_unlock(&kbc->idev->mutex); |
11f5b30d RI |
767 | |
768 | return 0; | |
769 | } | |
770 | ||
771 | static int tegra_kbc_resume(struct device *dev) | |
772 | { | |
773 | struct platform_device *pdev = to_platform_device(dev); | |
774 | struct tegra_kbc *kbc = platform_get_drvdata(pdev); | |
775 | int err = 0; | |
776 | ||
d0d150ec | 777 | mutex_lock(&kbc->idev->mutex); |
11f5b30d RI |
778 | if (device_may_wakeup(&pdev->dev)) { |
779 | disable_irq_wake(kbc->irq); | |
780 | tegra_kbc_setup_wakekeys(kbc, false); | |
b6834b02 RI |
781 | /* We will use fifo interrupts for key detection. */ |
782 | tegra_kbc_set_keypress_interrupt(kbc, false); | |
d0d150ec RI |
783 | |
784 | /* Restore the resident time of continuous polling mode. */ | |
785 | writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0); | |
786 | ||
787 | tegra_kbc_set_fifo_interrupt(kbc, true); | |
788 | ||
fd0fc213 RI |
789 | if (kbc->keypress_caused_wake && kbc->wakeup_key) { |
790 | /* | |
791 | * We can't report events directly from the ISR | |
792 | * because timekeeping is stopped when processing | |
793 | * wakeup request and we get a nasty warning when | |
794 | * we try to call do_gettimeofday() in evdev | |
795 | * handler. | |
796 | */ | |
797 | input_report_key(kbc->idev, kbc->wakeup_key, 1); | |
798 | input_sync(kbc->idev); | |
799 | input_report_key(kbc->idev, kbc->wakeup_key, 0); | |
800 | input_sync(kbc->idev); | |
801 | } | |
11f5b30d | 802 | } else { |
11f5b30d RI |
803 | if (kbc->idev->users) |
804 | err = tegra_kbc_start(kbc); | |
11f5b30d | 805 | } |
d0d150ec | 806 | mutex_unlock(&kbc->idev->mutex); |
11f5b30d RI |
807 | |
808 | return err; | |
809 | } | |
810 | #endif | |
811 | ||
812 | static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume); | |
813 | ||
814 | static struct platform_driver tegra_kbc_driver = { | |
815 | .probe = tegra_kbc_probe, | |
11f5b30d RI |
816 | .driver = { |
817 | .name = "tegra-kbc", | |
818 | .owner = THIS_MODULE, | |
819 | .pm = &tegra_kbc_pm_ops, | |
a445c7f0 | 820 | .of_match_table = tegra_kbc_of_match, |
11f5b30d RI |
821 | }, |
822 | }; | |
5146c84f | 823 | module_platform_driver(tegra_kbc_driver); |
11f5b30d RI |
824 | |
825 | MODULE_LICENSE("GPL"); | |
826 | MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>"); | |
827 | MODULE_DESCRIPTION("Tegra matrix keyboard controller driver"); | |
828 | MODULE_ALIAS("platform:tegra-kbc"); |