]>
Commit | Line | Data |
---|---|---|
11f5b30d RI |
1 | /* |
2 | * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix | |
3 | * keyboard controller | |
4 | * | |
5 | * Copyright (c) 2009-2011, NVIDIA Corporation. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | */ | |
21 | ||
3f27757a | 22 | #include <linux/kernel.h> |
11f5b30d RI |
23 | #include <linux/module.h> |
24 | #include <linux/input.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
a445c7f0 | 29 | #include <linux/of.h> |
11f5b30d RI |
30 | #include <linux/clk.h> |
31 | #include <linux/slab.h> | |
9eee07d3 | 32 | #include <linux/input/matrix_keypad.h> |
61fd290d | 33 | #include <linux/clk/tegra.h> |
ba52a7fc | 34 | #include <linux/err.h> |
11f5b30d | 35 | |
9eee07d3 SW |
36 | #define KBC_MAX_GPIO 24 |
37 | #define KBC_MAX_KPENT 8 | |
38 | ||
39 | #define KBC_MAX_ROW 16 | |
40 | #define KBC_MAX_COL 8 | |
41 | #define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL) | |
42 | ||
11f5b30d RI |
43 | #define KBC_MAX_DEBOUNCE_CNT 0x3ffu |
44 | ||
45 | /* KBC row scan time and delay for beginning the row scan. */ | |
46 | #define KBC_ROW_SCAN_TIME 16 | |
47 | #define KBC_ROW_SCAN_DLY 5 | |
48 | ||
49 | /* KBC uses a 32KHz clock so a cycle = 1/32Khz */ | |
3f27757a | 50 | #define KBC_CYCLE_MS 32 |
11f5b30d RI |
51 | |
52 | /* KBC Registers */ | |
53 | ||
54 | /* KBC Control Register */ | |
55 | #define KBC_CONTROL_0 0x0 | |
56 | #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14) | |
57 | #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4) | |
58 | #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) | |
b6834b02 | 59 | #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1) |
11f5b30d RI |
60 | #define KBC_CONTROL_KBC_EN (1 << 0) |
61 | ||
62 | /* KBC Interrupt Register */ | |
63 | #define KBC_INT_0 0x4 | |
64 | #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) | |
fd0fc213 | 65 | #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0) |
11f5b30d RI |
66 | |
67 | #define KBC_ROW_CFG0_0 0x8 | |
68 | #define KBC_COL_CFG0_0 0x18 | |
d0d150ec | 69 | #define KBC_TO_CNT_0 0x24 |
11f5b30d RI |
70 | #define KBC_INIT_DLY_0 0x28 |
71 | #define KBC_RPT_DLY_0 0x2c | |
72 | #define KBC_KP_ENT0_0 0x30 | |
73 | #define KBC_KP_ENT1_0 0x34 | |
74 | #define KBC_ROW0_MASK_0 0x38 | |
75 | ||
76 | #define KBC_ROW_SHIFT 3 | |
77 | ||
9eee07d3 SW |
78 | enum tegra_pin_type { |
79 | PIN_CFG_IGNORE, | |
80 | PIN_CFG_COL, | |
81 | PIN_CFG_ROW, | |
82 | }; | |
83 | ||
84 | struct tegra_kbc_pin_cfg { | |
85 | enum tegra_pin_type type; | |
86 | unsigned char num; | |
87 | }; | |
88 | ||
11f5b30d | 89 | struct tegra_kbc { |
9eee07d3 SW |
90 | struct device *dev; |
91 | unsigned int debounce_cnt; | |
92 | unsigned int repeat_cnt; | |
93 | struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; | |
94 | const struct matrix_keymap_data *keymap_data; | |
95 | bool wakeup; | |
11f5b30d RI |
96 | void __iomem *mmio; |
97 | struct input_dev *idev; | |
9eee07d3 | 98 | int irq; |
11f5b30d RI |
99 | spinlock_t lock; |
100 | unsigned int repoll_dly; | |
101 | unsigned long cp_dly_jiffies; | |
d0d150ec | 102 | unsigned int cp_to_wkup_dly; |
4e8b65f6 | 103 | bool use_fn_map; |
34abeeb2 | 104 | bool use_ghost_filter; |
fd0fc213 | 105 | bool keypress_caused_wake; |
4e8b65f6 | 106 | unsigned short keycode[KBC_MAX_KEY * 2]; |
11f5b30d RI |
107 | unsigned short current_keys[KBC_MAX_KPENT]; |
108 | unsigned int num_pressed_keys; | |
fd0fc213 | 109 | u32 wakeup_key; |
11f5b30d RI |
110 | struct timer_list timer; |
111 | struct clk *clk; | |
112 | }; | |
113 | ||
11f5b30d RI |
114 | static void tegra_kbc_report_released_keys(struct input_dev *input, |
115 | unsigned short old_keycodes[], | |
116 | unsigned int old_num_keys, | |
117 | unsigned short new_keycodes[], | |
118 | unsigned int new_num_keys) | |
119 | { | |
120 | unsigned int i, j; | |
121 | ||
122 | for (i = 0; i < old_num_keys; i++) { | |
123 | for (j = 0; j < new_num_keys; j++) | |
124 | if (old_keycodes[i] == new_keycodes[j]) | |
125 | break; | |
126 | ||
127 | if (j == new_num_keys) | |
128 | input_report_key(input, old_keycodes[i], 0); | |
129 | } | |
130 | } | |
131 | ||
132 | static void tegra_kbc_report_pressed_keys(struct input_dev *input, | |
133 | unsigned char scancodes[], | |
134 | unsigned short keycodes[], | |
135 | unsigned int num_pressed_keys) | |
136 | { | |
137 | unsigned int i; | |
138 | ||
139 | for (i = 0; i < num_pressed_keys; i++) { | |
140 | input_event(input, EV_MSC, MSC_SCAN, scancodes[i]); | |
141 | input_report_key(input, keycodes[i], 1); | |
142 | } | |
143 | } | |
144 | ||
145 | static void tegra_kbc_report_keys(struct tegra_kbc *kbc) | |
146 | { | |
147 | unsigned char scancodes[KBC_MAX_KPENT]; | |
148 | unsigned short keycodes[KBC_MAX_KPENT]; | |
149 | u32 val = 0; | |
150 | unsigned int i; | |
151 | unsigned int num_down = 0; | |
4e8b65f6 | 152 | bool fn_keypress = false; |
34abeeb2 RI |
153 | bool key_in_same_row = false; |
154 | bool key_in_same_col = false; | |
11f5b30d | 155 | |
11f5b30d RI |
156 | for (i = 0; i < KBC_MAX_KPENT; i++) { |
157 | if ((i % 4) == 0) | |
158 | val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); | |
159 | ||
160 | if (val & 0x80) { | |
161 | unsigned int col = val & 0x07; | |
162 | unsigned int row = (val >> 3) & 0x0f; | |
163 | unsigned char scancode = | |
164 | MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT); | |
165 | ||
166 | scancodes[num_down] = scancode; | |
4e8b65f6 RI |
167 | keycodes[num_down] = kbc->keycode[scancode]; |
168 | /* If driver uses Fn map, do not report the Fn key. */ | |
169 | if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) | |
170 | fn_keypress = true; | |
171 | else | |
172 | num_down++; | |
11f5b30d RI |
173 | } |
174 | ||
175 | val >>= 8; | |
176 | } | |
4e8b65f6 | 177 | |
34abeeb2 RI |
178 | /* |
179 | * Matrix keyboard designs are prone to keyboard ghosting. | |
180 | * Ghosting occurs if there are 3 keys such that - | |
181 | * any 2 of the 3 keys share a row, and any 2 of them share a column. | |
182 | * If so ignore the key presses for this iteration. | |
183 | */ | |
95439cba | 184 | if (kbc->use_ghost_filter && num_down >= 3) { |
34abeeb2 RI |
185 | for (i = 0; i < num_down; i++) { |
186 | unsigned int j; | |
187 | u8 curr_col = scancodes[i] & 0x07; | |
188 | u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT; | |
189 | ||
190 | /* | |
191 | * Find 2 keys such that one key is in the same row | |
192 | * and the other is in the same column as the i-th key. | |
193 | */ | |
194 | for (j = i + 1; j < num_down; j++) { | |
195 | u8 col = scancodes[j] & 0x07; | |
196 | u8 row = scancodes[j] >> KBC_ROW_SHIFT; | |
197 | ||
198 | if (col == curr_col) | |
199 | key_in_same_col = true; | |
200 | if (row == curr_row) | |
201 | key_in_same_row = true; | |
202 | } | |
203 | } | |
204 | } | |
205 | ||
4e8b65f6 RI |
206 | /* |
207 | * If the platform uses Fn keymaps, translate keys on a Fn keypress. | |
208 | * Function keycodes are KBC_MAX_KEY apart from the plain keycodes. | |
209 | */ | |
210 | if (fn_keypress) { | |
211 | for (i = 0; i < num_down; i++) { | |
212 | scancodes[i] += KBC_MAX_KEY; | |
213 | keycodes[i] = kbc->keycode[scancodes[i]]; | |
214 | } | |
215 | } | |
216 | ||
34abeeb2 RI |
217 | /* Ignore the key presses for this iteration? */ |
218 | if (key_in_same_col && key_in_same_row) | |
219 | return; | |
220 | ||
11f5b30d RI |
221 | tegra_kbc_report_released_keys(kbc->idev, |
222 | kbc->current_keys, kbc->num_pressed_keys, | |
223 | keycodes, num_down); | |
224 | tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down); | |
225 | input_sync(kbc->idev); | |
226 | ||
227 | memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys)); | |
228 | kbc->num_pressed_keys = num_down; | |
229 | } | |
230 | ||
d0d150ec RI |
231 | static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable) |
232 | { | |
233 | u32 val; | |
234 | ||
235 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
236 | if (enable) | |
237 | val |= KBC_CONTROL_FIFO_CNT_INT_EN; | |
238 | else | |
239 | val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; | |
240 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
241 | } | |
242 | ||
11f5b30d RI |
243 | static void tegra_kbc_keypress_timer(unsigned long data) |
244 | { | |
245 | struct tegra_kbc *kbc = (struct tegra_kbc *)data; | |
246 | unsigned long flags; | |
247 | u32 val; | |
248 | unsigned int i; | |
249 | ||
95439cba DT |
250 | spin_lock_irqsave(&kbc->lock, flags); |
251 | ||
11f5b30d RI |
252 | val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; |
253 | if (val) { | |
254 | unsigned long dly; | |
255 | ||
256 | tegra_kbc_report_keys(kbc); | |
257 | ||
258 | /* | |
259 | * If more than one keys are pressed we need not wait | |
260 | * for the repoll delay. | |
261 | */ | |
262 | dly = (val == 1) ? kbc->repoll_dly : 1; | |
263 | mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); | |
264 | } else { | |
265 | /* Release any pressed keys and exit the polling loop */ | |
266 | for (i = 0; i < kbc->num_pressed_keys; i++) | |
267 | input_report_key(kbc->idev, kbc->current_keys[i], 0); | |
268 | input_sync(kbc->idev); | |
269 | ||
270 | kbc->num_pressed_keys = 0; | |
271 | ||
272 | /* All keys are released so enable the keypress interrupt */ | |
d0d150ec | 273 | tegra_kbc_set_fifo_interrupt(kbc, true); |
11f5b30d | 274 | } |
95439cba DT |
275 | |
276 | spin_unlock_irqrestore(&kbc->lock, flags); | |
11f5b30d RI |
277 | } |
278 | ||
279 | static irqreturn_t tegra_kbc_isr(int irq, void *args) | |
280 | { | |
281 | struct tegra_kbc *kbc = args; | |
95439cba | 282 | unsigned long flags; |
d0d150ec | 283 | u32 val; |
11f5b30d | 284 | |
95439cba | 285 | spin_lock_irqsave(&kbc->lock, flags); |
11f5b30d RI |
286 | |
287 | /* | |
288 | * Quickly bail out & reenable interrupts if the fifo threshold | |
289 | * count interrupt wasn't the interrupt source | |
290 | */ | |
291 | val = readl(kbc->mmio + KBC_INT_0); | |
292 | writel(val, kbc->mmio + KBC_INT_0); | |
293 | ||
294 | if (val & KBC_INT_FIFO_CNT_INT_STATUS) { | |
295 | /* | |
95439cba DT |
296 | * Until all keys are released, defer further processing to |
297 | * the polling loop in tegra_kbc_keypress_timer. | |
11f5b30d | 298 | */ |
95439cba | 299 | tegra_kbc_set_fifo_interrupt(kbc, false); |
11f5b30d | 300 | mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies); |
fd0fc213 RI |
301 | } else if (val & KBC_INT_KEYPRESS_INT_STATUS) { |
302 | /* We can be here only through system resume path */ | |
303 | kbc->keypress_caused_wake = true; | |
11f5b30d RI |
304 | } |
305 | ||
95439cba DT |
306 | spin_unlock_irqrestore(&kbc->lock, flags); |
307 | ||
11f5b30d RI |
308 | return IRQ_HANDLED; |
309 | } | |
310 | ||
311 | static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter) | |
312 | { | |
11f5b30d RI |
313 | int i; |
314 | unsigned int rst_val; | |
315 | ||
baafb435 | 316 | /* Either mask all keys or none. */ |
9eee07d3 | 317 | rst_val = (filter && !kbc->wakeup) ? ~0 : 0; |
11f5b30d RI |
318 | |
319 | for (i = 0; i < KBC_MAX_ROW; i++) | |
320 | writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); | |
11f5b30d RI |
321 | } |
322 | ||
323 | static void tegra_kbc_config_pins(struct tegra_kbc *kbc) | |
324 | { | |
11f5b30d RI |
325 | int i; |
326 | ||
327 | for (i = 0; i < KBC_MAX_GPIO; i++) { | |
328 | u32 r_shft = 5 * (i % 6); | |
329 | u32 c_shft = 4 * (i % 8); | |
7530c4a1 RI |
330 | u32 r_mask = 0x1f << r_shft; |
331 | u32 c_mask = 0x0f << c_shft; | |
11f5b30d RI |
332 | u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0; |
333 | u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0; | |
334 | u32 row_cfg = readl(kbc->mmio + r_offs); | |
335 | u32 col_cfg = readl(kbc->mmio + c_offs); | |
336 | ||
337 | row_cfg &= ~r_mask; | |
338 | col_cfg &= ~c_mask; | |
339 | ||
9eee07d3 | 340 | switch (kbc->pin_cfg[i].type) { |
023cea0e | 341 | case PIN_CFG_ROW: |
9eee07d3 | 342 | row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft; |
023cea0e SR |
343 | break; |
344 | ||
345 | case PIN_CFG_COL: | |
9eee07d3 | 346 | col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft; |
023cea0e SR |
347 | break; |
348 | ||
349 | case PIN_CFG_IGNORE: | |
350 | break; | |
351 | } | |
11f5b30d RI |
352 | |
353 | writel(row_cfg, kbc->mmio + r_offs); | |
354 | writel(col_cfg, kbc->mmio + c_offs); | |
355 | } | |
356 | } | |
357 | ||
358 | static int tegra_kbc_start(struct tegra_kbc *kbc) | |
359 | { | |
11f5b30d RI |
360 | unsigned int debounce_cnt; |
361 | u32 val = 0; | |
362 | ||
f762470b | 363 | clk_prepare_enable(kbc->clk); |
11f5b30d RI |
364 | |
365 | /* Reset the KBC controller to clear all previous status.*/ | |
366 | tegra_periph_reset_assert(kbc->clk); | |
367 | udelay(100); | |
368 | tegra_periph_reset_deassert(kbc->clk); | |
369 | udelay(100); | |
370 | ||
371 | tegra_kbc_config_pins(kbc); | |
372 | tegra_kbc_setup_wakekeys(kbc, false); | |
373 | ||
9eee07d3 | 374 | writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0); |
11f5b30d RI |
375 | |
376 | /* Keyboard debounce count is maximum of 12 bits. */ | |
9eee07d3 | 377 | debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); |
11f5b30d RI |
378 | val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); |
379 | val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ | |
380 | val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ | |
381 | val |= KBC_CONTROL_KBC_EN; /* enable */ | |
382 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
383 | ||
384 | /* | |
385 | * Compute the delay(ns) from interrupt mode to continuous polling | |
386 | * mode so the timer routine is scheduled appropriately. | |
387 | */ | |
388 | val = readl(kbc->mmio + KBC_INIT_DLY_0); | |
389 | kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); | |
390 | ||
391 | kbc->num_pressed_keys = 0; | |
392 | ||
393 | /* | |
394 | * Atomically clear out any remaining entries in the key FIFO | |
395 | * and enable keyboard interrupts. | |
396 | */ | |
11f5b30d RI |
397 | while (1) { |
398 | val = readl(kbc->mmio + KBC_INT_0); | |
399 | val >>= 4; | |
400 | if (!val) | |
401 | break; | |
402 | ||
403 | val = readl(kbc->mmio + KBC_KP_ENT0_0); | |
404 | val = readl(kbc->mmio + KBC_KP_ENT1_0); | |
405 | } | |
406 | writel(0x7, kbc->mmio + KBC_INT_0); | |
11f5b30d RI |
407 | |
408 | enable_irq(kbc->irq); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | static void tegra_kbc_stop(struct tegra_kbc *kbc) | |
414 | { | |
415 | unsigned long flags; | |
416 | u32 val; | |
417 | ||
418 | spin_lock_irqsave(&kbc->lock, flags); | |
419 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
420 | val &= ~1; | |
421 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
422 | spin_unlock_irqrestore(&kbc->lock, flags); | |
423 | ||
424 | disable_irq(kbc->irq); | |
425 | del_timer_sync(&kbc->timer); | |
426 | ||
f762470b | 427 | clk_disable_unprepare(kbc->clk); |
11f5b30d RI |
428 | } |
429 | ||
430 | static int tegra_kbc_open(struct input_dev *dev) | |
431 | { | |
432 | struct tegra_kbc *kbc = input_get_drvdata(dev); | |
433 | ||
434 | return tegra_kbc_start(kbc); | |
435 | } | |
436 | ||
437 | static void tegra_kbc_close(struct input_dev *dev) | |
438 | { | |
439 | struct tegra_kbc *kbc = input_get_drvdata(dev); | |
440 | ||
441 | return tegra_kbc_stop(kbc); | |
442 | } | |
443 | ||
9eee07d3 SW |
444 | static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc, |
445 | unsigned int *num_rows) | |
11f5b30d RI |
446 | { |
447 | int i; | |
448 | ||
449 | *num_rows = 0; | |
450 | ||
451 | for (i = 0; i < KBC_MAX_GPIO; i++) { | |
9eee07d3 | 452 | const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i]; |
11f5b30d | 453 | |
023cea0e SR |
454 | switch (pin_cfg->type) { |
455 | case PIN_CFG_ROW: | |
11f5b30d | 456 | if (pin_cfg->num >= KBC_MAX_ROW) { |
9eee07d3 | 457 | dev_err(kbc->dev, |
11f5b30d RI |
458 | "pin_cfg[%d]: invalid row number %d\n", |
459 | i, pin_cfg->num); | |
460 | return false; | |
461 | } | |
462 | (*num_rows)++; | |
023cea0e SR |
463 | break; |
464 | ||
465 | case PIN_CFG_COL: | |
11f5b30d | 466 | if (pin_cfg->num >= KBC_MAX_COL) { |
9eee07d3 | 467 | dev_err(kbc->dev, |
11f5b30d RI |
468 | "pin_cfg[%d]: invalid column number %d\n", |
469 | i, pin_cfg->num); | |
470 | return false; | |
471 | } | |
023cea0e SR |
472 | break; |
473 | ||
474 | case PIN_CFG_IGNORE: | |
475 | break; | |
476 | ||
477 | default: | |
9eee07d3 | 478 | dev_err(kbc->dev, |
023cea0e SR |
479 | "pin_cfg[%d]: invalid entry type %d\n", |
480 | pin_cfg->type, pin_cfg->num); | |
481 | return false; | |
11f5b30d RI |
482 | } |
483 | } | |
484 | ||
485 | return true; | |
486 | } | |
487 | ||
9eee07d3 | 488 | static int tegra_kbc_parse_dt(struct tegra_kbc *kbc) |
a445c7f0 | 489 | { |
9eee07d3 | 490 | struct device_node *np = kbc->dev->of_node; |
145e9734 OJ |
491 | u32 prop; |
492 | int i; | |
88390243 LD |
493 | u32 num_rows = 0; |
494 | u32 num_cols = 0; | |
495 | u32 cols_cfg[KBC_MAX_GPIO]; | |
496 | u32 rows_cfg[KBC_MAX_GPIO]; | |
497 | int proplen; | |
498 | int ret; | |
499 | ||
145e9734 | 500 | if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop)) |
9eee07d3 | 501 | kbc->debounce_cnt = prop; |
a445c7f0 | 502 | |
145e9734 | 503 | if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop)) |
9eee07d3 | 504 | kbc->repeat_cnt = prop; |
a445c7f0 | 505 | |
145e9734 | 506 | if (of_find_property(np, "nvidia,needs-ghost-filter", NULL)) |
9eee07d3 | 507 | kbc->use_ghost_filter = true; |
a445c7f0 | 508 | |
145e9734 | 509 | if (of_find_property(np, "nvidia,wakeup-source", NULL)) |
9eee07d3 | 510 | kbc->wakeup = true; |
a445c7f0 | 511 | |
88390243 | 512 | if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) { |
9eee07d3 SW |
513 | dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n"); |
514 | return -ENOENT; | |
88390243 LD |
515 | } |
516 | num_rows = proplen / sizeof(u32); | |
517 | ||
518 | if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) { | |
9eee07d3 SW |
519 | dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n"); |
520 | return -ENOENT; | |
88390243 LD |
521 | } |
522 | num_cols = proplen / sizeof(u32); | |
523 | ||
524 | if (!of_get_property(np, "linux,keymap", &proplen)) { | |
9eee07d3 SW |
525 | dev_err(kbc->dev, "property linux,keymap not found\n"); |
526 | return -ENOENT; | |
a445c7f0 OJ |
527 | } |
528 | ||
88390243 | 529 | if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) { |
9eee07d3 | 530 | dev_err(kbc->dev, |
88390243 | 531 | "keypad rows/columns not porperly specified\n"); |
9eee07d3 | 532 | return -EINVAL; |
88390243 LD |
533 | } |
534 | ||
535 | /* Set all pins as non-configured */ | |
536 | for (i = 0; i < KBC_MAX_GPIO; i++) | |
9eee07d3 | 537 | kbc->pin_cfg[i].type = PIN_CFG_IGNORE; |
88390243 LD |
538 | |
539 | ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins", | |
540 | rows_cfg, num_rows); | |
541 | if (ret < 0) { | |
9eee07d3 SW |
542 | dev_err(kbc->dev, "Rows configurations are not proper\n"); |
543 | return -EINVAL; | |
88390243 LD |
544 | } |
545 | ||
546 | ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins", | |
547 | cols_cfg, num_cols); | |
548 | if (ret < 0) { | |
9eee07d3 SW |
549 | dev_err(kbc->dev, "Cols configurations are not proper\n"); |
550 | return -EINVAL; | |
88390243 LD |
551 | } |
552 | ||
553 | for (i = 0; i < num_rows; i++) { | |
9eee07d3 SW |
554 | kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW; |
555 | kbc->pin_cfg[rows_cfg[i]].num = i; | |
88390243 LD |
556 | } |
557 | ||
558 | for (i = 0; i < num_cols; i++) { | |
9eee07d3 SW |
559 | kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL; |
560 | kbc->pin_cfg[cols_cfg[i]].num = i; | |
a445c7f0 OJ |
561 | } |
562 | ||
9eee07d3 | 563 | return 0; |
a445c7f0 | 564 | } |
a445c7f0 | 565 | |
5298cc4c | 566 | static int tegra_kbc_probe(struct platform_device *pdev) |
11f5b30d | 567 | { |
11f5b30d | 568 | struct tegra_kbc *kbc; |
11f5b30d | 569 | struct resource *res; |
11f5b30d | 570 | int err; |
11f5b30d RI |
571 | int num_rows = 0; |
572 | unsigned int debounce_cnt; | |
573 | unsigned int scan_time_rows; | |
914e5976 | 574 | unsigned int keymap_rows = KBC_MAX_KEY; |
11f5b30d | 575 | |
9eee07d3 SW |
576 | kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL); |
577 | if (!kbc) { | |
578 | dev_err(&pdev->dev, "failed to alloc memory for kbc\n"); | |
579 | return -ENOMEM; | |
580 | } | |
581 | ||
582 | kbc->dev = &pdev->dev; | |
583 | spin_lock_init(&kbc->lock); | |
11f5b30d | 584 | |
9eee07d3 SW |
585 | err = tegra_kbc_parse_dt(kbc); |
586 | if (err) | |
587 | return err; | |
a445c7f0 | 588 | |
9eee07d3 | 589 | if (!tegra_kbc_check_pin_cfg(kbc, &num_rows)) |
00eb81e5 LD |
590 | return -EINVAL; |
591 | ||
11f5b30d RI |
592 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
593 | if (!res) { | |
594 | dev_err(&pdev->dev, "failed to get I/O memory\n"); | |
00eb81e5 | 595 | return -ENXIO; |
11f5b30d RI |
596 | } |
597 | ||
9eee07d3 SW |
598 | kbc->irq = platform_get_irq(pdev, 0); |
599 | if (kbc->irq < 0) { | |
11f5b30d | 600 | dev_err(&pdev->dev, "failed to get keyboard IRQ\n"); |
00eb81e5 | 601 | return -ENXIO; |
11f5b30d RI |
602 | } |
603 | ||
9eee07d3 SW |
604 | kbc->idev = devm_input_allocate_device(&pdev->dev); |
605 | if (!kbc->idev) { | |
00eb81e5 LD |
606 | dev_err(&pdev->dev, "failed to allocate input device\n"); |
607 | return -ENOMEM; | |
11f5b30d RI |
608 | } |
609 | ||
11f5b30d RI |
610 | setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc); |
611 | ||
ba52a7fc SK |
612 | kbc->mmio = devm_ioremap_resource(&pdev->dev, res); |
613 | if (IS_ERR(kbc->mmio)) | |
614 | return PTR_ERR(kbc->mmio); | |
11f5b30d | 615 | |
00eb81e5 | 616 | kbc->clk = devm_clk_get(&pdev->dev, NULL); |
11f5b30d RI |
617 | if (IS_ERR(kbc->clk)) { |
618 | dev_err(&pdev->dev, "failed to get keyboard clock\n"); | |
00eb81e5 | 619 | return PTR_ERR(kbc->clk); |
11f5b30d RI |
620 | } |
621 | ||
11f5b30d RI |
622 | /* |
623 | * The time delay between two consecutive reads of the FIFO is | |
624 | * the sum of the repeat time and the time taken for scanning | |
625 | * the rows. There is an additional delay before the row scanning | |
626 | * starts. The repoll delay is computed in milliseconds. | |
627 | */ | |
9eee07d3 | 628 | debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); |
11f5b30d | 629 | scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows; |
9eee07d3 | 630 | kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt; |
3f27757a | 631 | kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS); |
11f5b30d | 632 | |
9eee07d3 SW |
633 | kbc->idev->name = pdev->name; |
634 | kbc->idev->id.bustype = BUS_HOST; | |
635 | kbc->idev->dev.parent = &pdev->dev; | |
636 | kbc->idev->open = tegra_kbc_open; | |
637 | kbc->idev->close = tegra_kbc_close; | |
11f5b30d | 638 | |
9eee07d3 | 639 | if (kbc->keymap_data && kbc->use_fn_map) |
914e5976 LD |
640 | keymap_rows *= 2; |
641 | ||
9eee07d3 | 642 | err = matrix_keypad_build_keymap(kbc->keymap_data, NULL, |
914e5976 | 643 | keymap_rows, KBC_MAX_COL, |
9eee07d3 | 644 | kbc->keycode, kbc->idev); |
1932811f | 645 | if (err) { |
b45c8f35 | 646 | dev_err(&pdev->dev, "failed to setup keymap\n"); |
00eb81e5 | 647 | return err; |
1932811f DT |
648 | } |
649 | ||
9eee07d3 SW |
650 | __set_bit(EV_REP, kbc->idev->evbit); |
651 | input_set_capability(kbc->idev, EV_MSC, MSC_SCAN); | |
1932811f | 652 | |
9eee07d3 | 653 | input_set_drvdata(kbc->idev, kbc); |
11f5b30d | 654 | |
00eb81e5 | 655 | err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr, |
fd0fc213 | 656 | IRQF_NO_SUSPEND | IRQF_TRIGGER_HIGH, pdev->name, kbc); |
11f5b30d RI |
657 | if (err) { |
658 | dev_err(&pdev->dev, "failed to request keyboard IRQ\n"); | |
00eb81e5 | 659 | return err; |
11f5b30d RI |
660 | } |
661 | ||
662 | disable_irq(kbc->irq); | |
663 | ||
664 | err = input_register_device(kbc->idev); | |
665 | if (err) { | |
666 | dev_err(&pdev->dev, "failed to register input device\n"); | |
00eb81e5 | 667 | return err; |
11f5b30d RI |
668 | } |
669 | ||
670 | platform_set_drvdata(pdev, kbc); | |
9eee07d3 | 671 | device_init_wakeup(&pdev->dev, kbc->wakeup); |
11f5b30d | 672 | |
11f5b30d RI |
673 | return 0; |
674 | } | |
675 | ||
676 | #ifdef CONFIG_PM_SLEEP | |
1c407a1b LD |
677 | static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable) |
678 | { | |
679 | u32 val; | |
680 | ||
681 | val = readl(kbc->mmio + KBC_CONTROL_0); | |
682 | if (enable) | |
683 | val |= KBC_CONTROL_KEYPRESS_INT_EN; | |
684 | else | |
685 | val &= ~KBC_CONTROL_KEYPRESS_INT_EN; | |
686 | writel(val, kbc->mmio + KBC_CONTROL_0); | |
687 | } | |
688 | ||
11f5b30d RI |
689 | static int tegra_kbc_suspend(struct device *dev) |
690 | { | |
691 | struct platform_device *pdev = to_platform_device(dev); | |
692 | struct tegra_kbc *kbc = platform_get_drvdata(pdev); | |
693 | ||
d0d150ec | 694 | mutex_lock(&kbc->idev->mutex); |
11f5b30d | 695 | if (device_may_wakeup(&pdev->dev)) { |
d0d150ec RI |
696 | disable_irq(kbc->irq); |
697 | del_timer_sync(&kbc->timer); | |
698 | tegra_kbc_set_fifo_interrupt(kbc, false); | |
699 | ||
11f5b30d RI |
700 | /* Forcefully clear the interrupt status */ |
701 | writel(0x7, kbc->mmio + KBC_INT_0); | |
d0d150ec RI |
702 | /* |
703 | * Store the previous resident time of continuous polling mode. | |
704 | * Force the keyboard into interrupt mode. | |
705 | */ | |
706 | kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0); | |
707 | writel(0, kbc->mmio + KBC_TO_CNT_0); | |
708 | ||
709 | tegra_kbc_setup_wakekeys(kbc, true); | |
11f5b30d | 710 | msleep(30); |
d0d150ec | 711 | |
fd0fc213 | 712 | kbc->keypress_caused_wake = false; |
b6834b02 RI |
713 | /* Enable keypress interrupt before going into suspend. */ |
714 | tegra_kbc_set_keypress_interrupt(kbc, true); | |
fd0fc213 | 715 | enable_irq(kbc->irq); |
d0d150ec | 716 | enable_irq_wake(kbc->irq); |
11f5b30d | 717 | } else { |
11f5b30d RI |
718 | if (kbc->idev->users) |
719 | tegra_kbc_stop(kbc); | |
11f5b30d | 720 | } |
d0d150ec | 721 | mutex_unlock(&kbc->idev->mutex); |
11f5b30d RI |
722 | |
723 | return 0; | |
724 | } | |
725 | ||
726 | static int tegra_kbc_resume(struct device *dev) | |
727 | { | |
728 | struct platform_device *pdev = to_platform_device(dev); | |
729 | struct tegra_kbc *kbc = platform_get_drvdata(pdev); | |
730 | int err = 0; | |
731 | ||
d0d150ec | 732 | mutex_lock(&kbc->idev->mutex); |
11f5b30d RI |
733 | if (device_may_wakeup(&pdev->dev)) { |
734 | disable_irq_wake(kbc->irq); | |
735 | tegra_kbc_setup_wakekeys(kbc, false); | |
b6834b02 RI |
736 | /* We will use fifo interrupts for key detection. */ |
737 | tegra_kbc_set_keypress_interrupt(kbc, false); | |
d0d150ec RI |
738 | |
739 | /* Restore the resident time of continuous polling mode. */ | |
740 | writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0); | |
741 | ||
742 | tegra_kbc_set_fifo_interrupt(kbc, true); | |
743 | ||
fd0fc213 RI |
744 | if (kbc->keypress_caused_wake && kbc->wakeup_key) { |
745 | /* | |
746 | * We can't report events directly from the ISR | |
747 | * because timekeeping is stopped when processing | |
748 | * wakeup request and we get a nasty warning when | |
749 | * we try to call do_gettimeofday() in evdev | |
750 | * handler. | |
751 | */ | |
752 | input_report_key(kbc->idev, kbc->wakeup_key, 1); | |
753 | input_sync(kbc->idev); | |
754 | input_report_key(kbc->idev, kbc->wakeup_key, 0); | |
755 | input_sync(kbc->idev); | |
756 | } | |
11f5b30d | 757 | } else { |
11f5b30d RI |
758 | if (kbc->idev->users) |
759 | err = tegra_kbc_start(kbc); | |
11f5b30d | 760 | } |
d0d150ec | 761 | mutex_unlock(&kbc->idev->mutex); |
11f5b30d RI |
762 | |
763 | return err; | |
764 | } | |
765 | #endif | |
766 | ||
767 | static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume); | |
768 | ||
a445c7f0 OJ |
769 | static const struct of_device_id tegra_kbc_of_match[] = { |
770 | { .compatible = "nvidia,tegra20-kbc", }, | |
771 | { }, | |
772 | }; | |
773 | MODULE_DEVICE_TABLE(of, tegra_kbc_of_match); | |
774 | ||
11f5b30d RI |
775 | static struct platform_driver tegra_kbc_driver = { |
776 | .probe = tegra_kbc_probe, | |
11f5b30d RI |
777 | .driver = { |
778 | .name = "tegra-kbc", | |
779 | .owner = THIS_MODULE, | |
780 | .pm = &tegra_kbc_pm_ops, | |
a445c7f0 | 781 | .of_match_table = tegra_kbc_of_match, |
11f5b30d RI |
782 | }, |
783 | }; | |
5146c84f | 784 | module_platform_driver(tegra_kbc_driver); |
11f5b30d RI |
785 | |
786 | MODULE_LICENSE("GPL"); | |
787 | MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>"); | |
788 | MODULE_DESCRIPTION("Tegra matrix keyboard controller driver"); | |
789 | MODULE_ALIAS("platform:tegra-kbc"); |