[mirror_ubuntu-bionic-kernel.git] / drivers / input / misc / sirfsoc-onkey.c

/*
 * Power key driver for SiRF PrimaII
 *
 * Copyright (c) 2013 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
 * company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/rtc/sirfsoc_rtciobrg.h>
#include <linux/of.h>
#include <linux/workqueue.h>

struct sirfsoc_pwrc_drvdata {
	u32			pwrc_base;
	struct input_dev	*input;
	struct delayed_work	work;
};

#define PWRC_ON_KEY_BIT			(1 << 0)

#define PWRC_INT_STATUS			0xc
#define PWRC_INT_MASK			0x10
#define PWRC_PIN_STATUS			0x14
#define PWRC_KEY_DETECT_UP_TIME		20	/* ms*/

static int sirfsoc_pwrc_is_on_key_down(struct sirfsoc_pwrc_drvdata *pwrcdrv)
{
	u32 state = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base +
							PWRC_PIN_STATUS);
	return !(state & PWRC_ON_KEY_BIT); /* ON_KEY is active low */
}

static void sirfsoc_pwrc_report_event(struct work_struct *work)
{
	struct sirfsoc_pwrc_drvdata *pwrcdrv =
		container_of(work, struct sirfsoc_pwrc_drvdata, work.work);

	if (sirfsoc_pwrc_is_on_key_down(pwrcdrv)) {
		schedule_delayed_work(&pwrcdrv->work,
			msecs_to_jiffies(PWRC_KEY_DETECT_UP_TIME));
	} else {
		input_event(pwrcdrv->input, EV_KEY, KEY_POWER, 0);
		input_sync(pwrcdrv->input);
	}
}

static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
{
	struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_id;
	u32 int_status;

	int_status = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base +
							PWRC_INT_STATUS);
	sirfsoc_rtc_iobrg_writel(int_status & ~PWRC_ON_KEY_BIT,
				 pwrcdrv->pwrc_base + PWRC_INT_STATUS);

	input_event(pwrcdrv->input, EV_KEY, KEY_POWER, 1);
	input_sync(pwrcdrv->input);
	schedule_delayed_work(&pwrcdrv->work,
			      msecs_to_jiffies(PWRC_KEY_DETECT_UP_TIME));

	return IRQ_HANDLED;
}

static void sirfsoc_pwrc_toggle_interrupts(struct sirfsoc_pwrc_drvdata *pwrcdrv,
					   bool enable)
{
	u32 int_mask;

	int_mask = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK);
	if (enable)
		int_mask |= PWRC_ON_KEY_BIT;
	else
		int_mask &= ~PWRC_ON_KEY_BIT;
	sirfsoc_rtc_iobrg_writel(int_mask, pwrcdrv->pwrc_base + PWRC_INT_MASK);
}

static int sirfsoc_pwrc_open(struct input_dev *input)
{
	struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);

	sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);

	return 0;
}

static void sirfsoc_pwrc_close(struct input_dev *input)
{
	struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);

	sirfsoc_pwrc_toggle_interrupts(pwrcdrv, false);
	cancel_delayed_work_sync(&pwrcdrv->work);
}

static const struct of_device_id sirfsoc_pwrc_of_match[] = {
	{ .compatible = "sirf,prima2-pwrc" },
	{},
};
MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);

static int sirfsoc_pwrc_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct sirfsoc_pwrc_drvdata *pwrcdrv;
	int irq;
	int error;

	pwrcdrv = devm_kzalloc(&pdev->dev, sizeof(struct sirfsoc_pwrc_drvdata),
			       GFP_KERNEL);
	if (!pwrcdrv) {
		dev_info(&pdev->dev, "Not enough memory for the device data\n");
		return -ENOMEM;
	}

	/*
	 * We can't use of_iomap because pwrc is not mapped in memory,
	 * the so-called base address is only offset in rtciobrg
	 */
	error = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
	if (error) {
		dev_err(&pdev->dev,
			"unable to find base address of pwrc node in dtb\n");
		return error;
	}

	pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
	if (!pwrcdrv->input)
		return -ENOMEM;

	pwrcdrv->input->name = "sirfsoc pwrckey";
	pwrcdrv->input->phys = "pwrc/input0";
	pwrcdrv->input->evbit[0] = BIT_MASK(EV_KEY);
	input_set_capability(pwrcdrv->input, EV_KEY, KEY_POWER);

	INIT_DELAYED_WORK(&pwrcdrv->work, sirfsoc_pwrc_report_event);

	pwrcdrv->input->open = sirfsoc_pwrc_open;
	pwrcdrv->input->close = sirfsoc_pwrc_close;

	input_set_drvdata(pwrcdrv->input, pwrcdrv);

	/* Make sure the device is quiesced */
	sirfsoc_pwrc_toggle_interrupts(pwrcdrv, false);

	irq = platform_get_irq(pdev, 0);
	error = devm_request_irq(&pdev->dev, irq,
				 sirfsoc_pwrc_isr, 0,
				 "sirfsoc_pwrc_int", pwrcdrv);
	if (error) {
		dev_err(&pdev->dev, "unable to claim irq %d, error: %d\n",
			irq, error);
		return error;
	}

	error = input_register_device(pwrcdrv->input);
	if (error) {
		dev_err(&pdev->dev,
			"unable to register input device, error: %d\n",
			error);
		return error;
	}

	dev_set_drvdata(&pdev->dev, pwrcdrv);
	device_init_wakeup(&pdev->dev, 1);

	return 0;
}

static int __maybe_unused sirfsoc_pwrc_resume(struct device *dev)
{
	struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
	struct input_dev *input = pwrcdrv->input;

	/*
	 * Do not mask pwrc interrupt as we want pwrc work as a wakeup source
	 * if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
	 */
	mutex_lock(&input->mutex);
	if (input->users)
		sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);
	mutex_unlock(&input->mutex);

	return 0;
}

static SIMPLE_DEV_PM_OPS(sirfsoc_pwrc_pm_ops, NULL, sirfsoc_pwrc_resume);

static struct platform_driver sirfsoc_pwrc_driver = {
	.probe		= sirfsoc_pwrc_probe,
	.driver		= {
		.name	= "sirfsoc-pwrc",
		.pm	= &sirfsoc_pwrc_pm_ops,
		.of_match_table = sirfsoc_pwrc_of_match,
	}
};

module_platform_driver(sirfsoc_pwrc_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Binghua Duan <Binghua.Duan@csr.com>, Xianglong Du <Xianglong.Du@csr.com>");
MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
MODULE_ALIAS("platform:sirfsoc-pwrc");
Commit	Line	Data
9b5f953d BD	1	/*
	2	* Power key driver for SiRF PrimaII
	3	*
a9728f97 BS	4	* Copyright (c) 2013 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
a9728f97 BS	5	* company.
9b5f953d BD	6	*
	7	* Licensed under GPLv2 or later.
	8	*/
	9
	10	#include <linux/module.h>
9b5f953d BD	11	#include <linux/interrupt.h>
	12	#include <linux/delay.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/input.h>
	15	#include <linux/rtc/sirfsoc_rtciobrg.h>
	16	#include <linux/of.h>
a1a75210	17	#include <linux/workqueue.h>
9b5f953d BD	18
	19	struct sirfsoc_pwrc_drvdata {
	20	u32 pwrc_base;
	21	struct input_dev *input;
a1a75210	22	struct delayed_work work;
9b5f953d BD	23	};
	24
	25	#define PWRC_ON_KEY_BIT (1 << 0)
	26
	27	#define PWRC_INT_STATUS 0xc
	28	#define PWRC_INT_MASK 0x10
a1a75210 XD	29	#define PWRC_PIN_STATUS 0x14
	30	#define PWRC_KEY_DETECT_UP_TIME 20 /* ms*/
	31
	32	static int sirfsoc_pwrc_is_on_key_down(struct sirfsoc_pwrc_drvdata *pwrcdrv)
	33	{
	34	u32 state = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base +
	35	PWRC_PIN_STATUS);
	36	return !(state & PWRC_ON_KEY_BIT); /* ON_KEY is active low */
	37	}
	38
	39	static void sirfsoc_pwrc_report_event(struct work_struct *work)
	40	{
	41	struct sirfsoc_pwrc_drvdata *pwrcdrv =
	42	container_of(work, struct sirfsoc_pwrc_drvdata, work.work);
	43
	44	if (sirfsoc_pwrc_is_on_key_down(pwrcdrv)) {
	45	schedule_delayed_work(&pwrcdrv->work,
	46	msecs_to_jiffies(PWRC_KEY_DETECT_UP_TIME));
	47	} else {
	48	input_event(pwrcdrv->input, EV_KEY, KEY_POWER, 0);
	49	input_sync(pwrcdrv->input);
	50	}
	51	}
9b5f953d BD	52
	53	static irqreturn_t sirfsoc_pwrc_isr(int irq, void *dev_id)
	54	{
	55	struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_id;
	56	u32 int_status;
	57
	58	int_status = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base +
	59	PWRC_INT_STATUS);
	60	sirfsoc_rtc_iobrg_writel(int_status & ~PWRC_ON_KEY_BIT,
	61	pwrcdrv->pwrc_base + PWRC_INT_STATUS);
	62
a1a75210	63	input_event(pwrcdrv->input, EV_KEY, KEY_POWER, 1);
9b5f953d	64	input_sync(pwrcdrv->input);
a1a75210 XD	65	schedule_delayed_work(&pwrcdrv->work,
a1a75210 XD	66	msecs_to_jiffies(PWRC_KEY_DETECT_UP_TIME));
9b5f953d BD	67
	68	return IRQ_HANDLED;
	69	}
	70
864d3c0f DT	71	static void sirfsoc_pwrc_toggle_interrupts(struct sirfsoc_pwrc_drvdata *pwrcdrv,
	72	bool enable)
	73	{
	74	u32 int_mask;
	75
	76	int_mask = sirfsoc_rtc_iobrg_readl(pwrcdrv->pwrc_base + PWRC_INT_MASK);
	77	if (enable)
	78	int_mask \|= PWRC_ON_KEY_BIT;
	79	else
	80	int_mask &= ~PWRC_ON_KEY_BIT;
	81	sirfsoc_rtc_iobrg_writel(int_mask, pwrcdrv->pwrc_base + PWRC_INT_MASK);
	82	}
	83
	84	static int sirfsoc_pwrc_open(struct input_dev *input)
	85	{
	86	struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);
	87
	88	sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);
	89
	90	return 0;
	91	}
	92
	93	static void sirfsoc_pwrc_close(struct input_dev *input)
	94	{
	95	struct sirfsoc_pwrc_drvdata *pwrcdrv = input_get_drvdata(input);
	96
	97	sirfsoc_pwrc_toggle_interrupts(pwrcdrv, false);
a1a75210	98	cancel_delayed_work_sync(&pwrcdrv->work);
864d3c0f DT	99	}
864d3c0f DT	100
9b5f953d BD	101	static const struct of_device_id sirfsoc_pwrc_of_match[] = {
	102	{ .compatible = "sirf,prima2-pwrc" },
	103	{},
af6e9463	104	};
9b5f953d BD	105	MODULE_DEVICE_TABLE(of, sirfsoc_pwrc_of_match);
	106
	107	static int sirfsoc_pwrc_probe(struct platform_device *pdev)
	108	{
	109	struct device_node *np = pdev->dev.of_node;
	110	struct sirfsoc_pwrc_drvdata *pwrcdrv;
	111	int irq;
	112	int error;
	113
	114	pwrcdrv = devm_kzalloc(&pdev->dev, sizeof(struct sirfsoc_pwrc_drvdata),
	115	GFP_KERNEL);
	116	if (!pwrcdrv) {
	117	dev_info(&pdev->dev, "Not enough memory for the device data\n");
	118	return -ENOMEM;
	119	}
	120
	121	/*
864d3c0f	122	* We can't use of_iomap because pwrc is not mapped in memory,
9b5f953d BD	123	* the so-called base address is only offset in rtciobrg
	124	*/
	125	error = of_property_read_u32(np, "reg", &pwrcdrv->pwrc_base);
	126	if (error) {
	127	dev_err(&pdev->dev,
	128	"unable to find base address of pwrc node in dtb\n");
	129	return error;
	130	}
	131
	132	pwrcdrv->input = devm_input_allocate_device(&pdev->dev);
	133	if (!pwrcdrv->input)
	134	return -ENOMEM;
	135
	136	pwrcdrv->input->name = "sirfsoc pwrckey";
	137	pwrcdrv->input->phys = "pwrc/input0";
a1a75210	138	pwrcdrv->input->evbit[0] = BIT_MASK(EV_KEY);
9732e5b0	139	input_set_capability(pwrcdrv->input, EV_KEY, KEY_POWER);
a1a75210 XD	140
a1a75210 XD	141	INIT_DELAYED_WORK(&pwrcdrv->work, sirfsoc_pwrc_report_event);
9b5f953d	142
864d3c0f DT	143	pwrcdrv->input->open = sirfsoc_pwrc_open;
	144	pwrcdrv->input->close = sirfsoc_pwrc_close;
	145
	146	input_set_drvdata(pwrcdrv->input, pwrcdrv);
	147
	148	/* Make sure the device is quiesced */
	149	sirfsoc_pwrc_toggle_interrupts(pwrcdrv, false);
	150
9b5f953d BD	151	irq = platform_get_irq(pdev, 0);
9b5f953d BD	152	error = devm_request_irq(&pdev->dev, irq,
5099817e	153	sirfsoc_pwrc_isr, 0,
9b5f953d BD	154	"sirfsoc_pwrc_int", pwrcdrv);
	155	if (error) {
	156	dev_err(&pdev->dev, "unable to claim irq %d, error: %d\n",
	157	irq, error);
	158	return error;
	159	}
	160
9b5f953d BD	161	error = input_register_device(pwrcdrv->input);
	162	if (error) {
	163	dev_err(&pdev->dev,
	164	"unable to register input device, error: %d\n",
	165	error);
	166	return error;
	167	}
	168
a5e46645	169	dev_set_drvdata(&pdev->dev, pwrcdrv);
9b5f953d BD	170	device_init_wakeup(&pdev->dev, 1);
	171
	172	return 0;
	173	}
	174
97a652a8	175	static int __maybe_unused sirfsoc_pwrc_resume(struct device *dev)
9b5f953d	176	{
a5e46645	177	struct sirfsoc_pwrc_drvdata *pwrcdrv = dev_get_drvdata(dev);
864d3c0f	178	struct input_dev *input = pwrcdrv->input;
9b5f953d BD	179
	180	/*
	181	* Do not mask pwrc interrupt as we want pwrc work as a wakeup source
	182	* if users touch X_ONKEY_B, see arch/arm/mach-prima2/pm.c
	183	*/
864d3c0f DT	184	mutex_lock(&input->mutex);
	185	if (input->users)
	186	sirfsoc_pwrc_toggle_interrupts(pwrcdrv, true);
	187	mutex_unlock(&input->mutex);
9b5f953d BD	188
	189	return 0;
	190	}
9b5f953d	191
3a80035b	192	static SIMPLE_DEV_PM_OPS(sirfsoc_pwrc_pm_ops, NULL, sirfsoc_pwrc_resume);
9b5f953d BD	193
	194	static struct platform_driver sirfsoc_pwrc_driver = {
	195	.probe = sirfsoc_pwrc_probe,
9b5f953d BD	196	.driver = {
9b5f953d BD	197	.name = "sirfsoc-pwrc",
9b5f953d	198	.pm = &sirfsoc_pwrc_pm_ops,
dee964c0	199	.of_match_table = sirfsoc_pwrc_of_match,
9b5f953d BD	200	}
	201	};
	202
	203	module_platform_driver(sirfsoc_pwrc_driver);
	204
67f4aef2	205	MODULE_LICENSE("GPL v2");
9b5f953d BD	206	MODULE_AUTHOR("Binghua Duan <Binghua.Duan@csr.com>, Xianglong Du <Xianglong.Du@csr.com>");
	207	MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
	208	MODULE_ALIAS("platform:sirfsoc-pwrc");