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1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/config.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/serio.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/rcupdate.h> | |
d052d1be | 23 | #include <linux/platform_device.h> |
1da177e4 LT |
24 | |
25 | #include <asm/io.h> | |
26 | ||
27 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
28 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
29 | MODULE_LICENSE("GPL"); | |
30 | ||
945ef0d4 DT |
31 | static unsigned int i8042_nokbd; |
32 | module_param_named(nokbd, i8042_nokbd, bool, 0); | |
33 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
34 | ||
1da177e4 LT |
35 | static unsigned int i8042_noaux; |
36 | module_param_named(noaux, i8042_noaux, bool, 0); | |
37 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
38 | ||
39 | static unsigned int i8042_nomux; | |
40 | module_param_named(nomux, i8042_nomux, bool, 0); | |
41 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); | |
42 | ||
43 | static unsigned int i8042_unlock; | |
44 | module_param_named(unlock, i8042_unlock, bool, 0); | |
45 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
46 | ||
47 | static unsigned int i8042_reset; | |
48 | module_param_named(reset, i8042_reset, bool, 0); | |
49 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
50 | ||
51 | static unsigned int i8042_direct; | |
52 | module_param_named(direct, i8042_direct, bool, 0); | |
53 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
54 | ||
55 | static unsigned int i8042_dumbkbd; | |
56 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); | |
57 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
58 | ||
59 | static unsigned int i8042_noloop; | |
60 | module_param_named(noloop, i8042_noloop, bool, 0); | |
61 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
62 | ||
63 | static unsigned int i8042_blink_frequency = 500; | |
64 | module_param_named(panicblink, i8042_blink_frequency, uint, 0600); | |
65 | MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); | |
66 | ||
67 | #ifdef CONFIG_PNP | |
68 | static int i8042_nopnp; | |
69 | module_param_named(nopnp, i8042_nopnp, bool, 0); | |
70 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
71 | #endif | |
72 | ||
73 | #define DEBUG | |
74 | #ifdef DEBUG | |
75 | static int i8042_debug; | |
76 | module_param_named(debug, i8042_debug, bool, 0600); | |
77 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
78 | #endif | |
79 | ||
80 | __obsolete_setup("i8042_noaux"); | |
81 | __obsolete_setup("i8042_nomux"); | |
82 | __obsolete_setup("i8042_unlock"); | |
83 | __obsolete_setup("i8042_reset"); | |
84 | __obsolete_setup("i8042_direct"); | |
85 | __obsolete_setup("i8042_dumbkbd"); | |
86 | ||
87 | #include "i8042.h" | |
88 | ||
89 | static DEFINE_SPINLOCK(i8042_lock); | |
90 | ||
91 | struct i8042_port { | |
92 | struct serio *serio; | |
93 | int irq; | |
94 | unsigned char disable; | |
95 | unsigned char irqen; | |
96 | unsigned char exists; | |
97 | signed char mux; | |
98 | char name[8]; | |
99 | }; | |
100 | ||
101 | #define I8042_KBD_PORT_NO 0 | |
102 | #define I8042_AUX_PORT_NO 1 | |
103 | #define I8042_MUX_PORT_NO 2 | |
104 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
105 | static struct i8042_port i8042_ports[I8042_NUM_PORTS] = { | |
106 | { | |
107 | .disable = I8042_CTR_KBDDIS, | |
463a4f76 | 108 | .irqen = I8042_CTR_KBDINT, |
1da177e4 LT |
109 | .mux = -1, |
110 | .name = "KBD", | |
111 | }, | |
112 | { | |
113 | .disable = I8042_CTR_AUXDIS, | |
114 | .irqen = I8042_CTR_AUXINT, | |
115 | .mux = -1, | |
116 | .name = "AUX", | |
117 | } | |
118 | }; | |
119 | ||
120 | static unsigned char i8042_initial_ctr; | |
121 | static unsigned char i8042_ctr; | |
122 | static unsigned char i8042_mux_open; | |
123 | static unsigned char i8042_mux_present; | |
124 | static struct timer_list i8042_timer; | |
125 | static struct platform_device *i8042_platform_device; | |
126 | ||
127 | ||
128 | /* | |
129 | * Shared IRQ's require a device pointer, but this driver doesn't support | |
130 | * multiple devices | |
131 | */ | |
132 | #define i8042_request_irq_cookie (&i8042_timer) | |
133 | ||
134 | static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs); | |
135 | ||
136 | /* | |
137 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
138 | * be ready for reading values from it / writing values to it. | |
139 | * Called always with i8042_lock held. | |
140 | */ | |
141 | ||
142 | static int i8042_wait_read(void) | |
143 | { | |
144 | int i = 0; | |
145 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { | |
146 | udelay(50); | |
147 | i++; | |
148 | } | |
149 | return -(i == I8042_CTL_TIMEOUT); | |
150 | } | |
151 | ||
152 | static int i8042_wait_write(void) | |
153 | { | |
154 | int i = 0; | |
155 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { | |
156 | udelay(50); | |
157 | i++; | |
158 | } | |
159 | return -(i == I8042_CTL_TIMEOUT); | |
160 | } | |
161 | ||
162 | /* | |
163 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
164 | * of the i8042 down the toilet. | |
165 | */ | |
166 | ||
167 | static int i8042_flush(void) | |
168 | { | |
169 | unsigned long flags; | |
170 | unsigned char data, str; | |
171 | int i = 0; | |
172 | ||
173 | spin_lock_irqsave(&i8042_lock, flags); | |
174 | ||
175 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
176 | udelay(50); | |
177 | data = i8042_read_data(); | |
178 | i++; | |
179 | dbg("%02x <- i8042 (flush, %s)", data, | |
180 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
181 | } | |
182 | ||
183 | spin_unlock_irqrestore(&i8042_lock, flags); | |
184 | ||
185 | return i; | |
186 | } | |
187 | ||
188 | /* | |
189 | * i8042_command() executes a command on the i8042. It also sends the input | |
190 | * parameter(s) of the commands to it, and receives the output value(s). The | |
191 | * parameters are to be stored in the param array, and the output is placed | |
192 | * into the same array. The number of the parameters and output values is | |
193 | * encoded in bits 8-11 of the command number. | |
194 | */ | |
195 | ||
196 | static int i8042_command(unsigned char *param, int command) | |
197 | { | |
198 | unsigned long flags; | |
463a4f76 | 199 | int i, retval, auxerr = 0; |
1da177e4 LT |
200 | |
201 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
202 | return -1; | |
203 | ||
204 | spin_lock_irqsave(&i8042_lock, flags); | |
205 | ||
463a4f76 DT |
206 | if ((retval = i8042_wait_write())) |
207 | goto out; | |
208 | ||
209 | dbg("%02x -> i8042 (command)", command & 0xff); | |
210 | i8042_write_command(command & 0xff); | |
211 | ||
212 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
213 | if ((retval = i8042_wait_write())) | |
214 | goto out; | |
215 | dbg("%02x -> i8042 (parameter)", param[i]); | |
216 | i8042_write_data(param[i]); | |
1da177e4 LT |
217 | } |
218 | ||
463a4f76 DT |
219 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
220 | if ((retval = i8042_wait_read())) | |
221 | goto out; | |
1da177e4 | 222 | |
463a4f76 DT |
223 | if (command == I8042_CMD_AUX_LOOP && |
224 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
225 | retval = auxerr = -1; | |
226 | goto out; | |
1da177e4 LT |
227 | } |
228 | ||
463a4f76 DT |
229 | param[i] = i8042_read_data(); |
230 | dbg("%02x <- i8042 (return)", param[i]); | |
231 | } | |
1da177e4 LT |
232 | |
233 | if (retval) | |
463a4f76 | 234 | dbg(" -- i8042 (%s)", auxerr ? "auxerr" : "timeout"); |
1da177e4 | 235 | |
463a4f76 DT |
236 | out: |
237 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 LT |
238 | return retval; |
239 | } | |
240 | ||
241 | /* | |
242 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
243 | */ | |
244 | ||
245 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
246 | { | |
247 | unsigned long flags; | |
248 | int retval = 0; | |
249 | ||
250 | spin_lock_irqsave(&i8042_lock, flags); | |
251 | ||
252 | if(!(retval = i8042_wait_write())) { | |
253 | dbg("%02x -> i8042 (kbd-data)", c); | |
254 | i8042_write_data(c); | |
255 | } | |
256 | ||
257 | spin_unlock_irqrestore(&i8042_lock, flags); | |
258 | ||
259 | return retval; | |
260 | } | |
261 | ||
262 | /* | |
263 | * i8042_aux_write() sends a byte out through the aux interface. | |
264 | */ | |
265 | ||
266 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
267 | { | |
268 | struct i8042_port *port = serio->port_data; | |
269 | int retval; | |
270 | ||
271 | /* | |
272 | * Send the byte out. | |
273 | */ | |
274 | ||
275 | if (port->mux == -1) | |
276 | retval = i8042_command(&c, I8042_CMD_AUX_SEND); | |
277 | else | |
278 | retval = i8042_command(&c, I8042_CMD_MUX_SEND + port->mux); | |
279 | ||
280 | /* | |
281 | * Make sure the interrupt happens and the character is received even | |
282 | * in the case the IRQ isn't wired, so that we can receive further | |
283 | * characters later. | |
284 | */ | |
285 | ||
286 | i8042_interrupt(0, NULL, NULL); | |
287 | return retval; | |
288 | } | |
289 | ||
290 | /* | |
291 | * i8042_activate_port() enables port on a chip. | |
292 | */ | |
293 | ||
294 | static int i8042_activate_port(struct i8042_port *port) | |
295 | { | |
296 | if (!port->serio) | |
297 | return -1; | |
298 | ||
299 | i8042_flush(); | |
300 | ||
301 | /* | |
302 | * Enable port again here because it is disabled if we are | |
303 | * resuming (normally it is enabled already). | |
304 | */ | |
305 | i8042_ctr &= ~port->disable; | |
306 | ||
307 | i8042_ctr |= port->irqen; | |
308 | ||
309 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
310 | i8042_ctr &= ~port->irqen; | |
311 | return -1; | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | ||
318 | /* | |
319 | * i8042_open() is called when a port is open by the higher layer. | |
320 | * It allocates the interrupt and calls i8042_enable_port. | |
321 | */ | |
322 | ||
323 | static int i8042_open(struct serio *serio) | |
324 | { | |
325 | struct i8042_port *port = serio->port_data; | |
326 | ||
327 | if (port->mux != -1) | |
328 | if (i8042_mux_open++) | |
329 | return 0; | |
330 | ||
331 | if (request_irq(port->irq, i8042_interrupt, | |
332 | SA_SHIRQ, "i8042", i8042_request_irq_cookie)) { | |
333 | printk(KERN_ERR "i8042.c: Can't get irq %d for %s, unregistering the port.\n", port->irq, port->name); | |
334 | goto irq_fail; | |
335 | } | |
336 | ||
337 | if (i8042_activate_port(port)) { | |
338 | printk(KERN_ERR "i8042.c: Can't activate %s, unregistering the port\n", port->name); | |
339 | goto activate_fail; | |
340 | } | |
341 | ||
342 | i8042_interrupt(0, NULL, NULL); | |
343 | ||
344 | return 0; | |
345 | ||
0854e52d | 346 | activate_fail: |
1da177e4 LT |
347 | free_irq(port->irq, i8042_request_irq_cookie); |
348 | ||
0854e52d | 349 | irq_fail: |
1da177e4 LT |
350 | serio_unregister_port_delayed(serio); |
351 | ||
352 | return -1; | |
353 | } | |
354 | ||
355 | /* | |
356 | * i8042_close() frees the interrupt, so that it can possibly be used | |
357 | * by another driver. We never know - if the user doesn't have a mouse, | |
358 | * the BIOS could have used the AUX interrupt for PCI. | |
359 | */ | |
360 | ||
361 | static void i8042_close(struct serio *serio) | |
362 | { | |
363 | struct i8042_port *port = serio->port_data; | |
364 | ||
365 | if (port->mux != -1) | |
366 | if (--i8042_mux_open) | |
367 | return; | |
368 | ||
369 | i8042_ctr &= ~port->irqen; | |
370 | ||
371 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
372 | printk(KERN_WARNING "i8042.c: Can't write CTR while closing %s.\n", port->name); | |
373 | /* | |
374 | * We still want to continue and free IRQ so if more data keeps coming in | |
375 | * kernel will just ignore the irq. | |
376 | */ | |
377 | } | |
378 | ||
379 | free_irq(port->irq, i8042_request_irq_cookie); | |
380 | ||
381 | i8042_flush(); | |
382 | } | |
383 | ||
384 | /* | |
385 | * i8042_start() is called by serio core when port is about to finish | |
386 | * registering. It will mark port as existing so i8042_interrupt can | |
387 | * start sending data through it. | |
388 | */ | |
389 | static int i8042_start(struct serio *serio) | |
390 | { | |
391 | struct i8042_port *port = serio->port_data; | |
392 | ||
393 | port->exists = 1; | |
394 | mb(); | |
395 | return 0; | |
396 | } | |
397 | ||
398 | /* | |
399 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
400 | * will not try to send data to the port that is about to go away. | |
401 | * The function is called by serio core as part of unregister procedure. | |
402 | */ | |
403 | static void i8042_stop(struct serio *serio) | |
404 | { | |
405 | struct i8042_port *port = serio->port_data; | |
406 | ||
407 | port->exists = 0; | |
b2b18660 | 408 | synchronize_sched(); |
1da177e4 LT |
409 | port->serio = NULL; |
410 | } | |
411 | ||
412 | /* | |
413 | * i8042_interrupt() is the most important function in this driver - | |
414 | * it handles the interrupts from the i8042, and sends incoming bytes | |
415 | * to the upper layers. | |
416 | */ | |
417 | ||
418 | static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
419 | { | |
420 | struct i8042_port *port; | |
421 | unsigned long flags; | |
422 | unsigned char str, data; | |
423 | unsigned int dfl; | |
424 | unsigned int port_no; | |
425 | int ret; | |
426 | ||
427 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
428 | ||
429 | spin_lock_irqsave(&i8042_lock, flags); | |
430 | str = i8042_read_status(); | |
431 | if (unlikely(~str & I8042_STR_OBF)) { | |
432 | spin_unlock_irqrestore(&i8042_lock, flags); | |
433 | if (irq) dbg("Interrupt %d, without any data", irq); | |
434 | ret = 0; | |
435 | goto out; | |
436 | } | |
437 | data = i8042_read_data(); | |
438 | spin_unlock_irqrestore(&i8042_lock, flags); | |
439 | ||
440 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
441 | static unsigned long last_transmit; | |
442 | static unsigned char last_str; | |
443 | ||
444 | dfl = 0; | |
445 | if (str & I8042_STR_MUXERR) { | |
446 | dbg("MUX error, status is %02x, data is %02x", str, data); | |
447 | switch (data) { | |
448 | default: | |
449 | /* | |
450 | * When MUXERR condition is signalled the data register can only contain | |
451 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
452 | * it is not always the case. Some KBC just get confused which port the | |
453 | * data came from and signal error leaving the data intact. They _do not_ | |
454 | * revert to legacy mode (actually I've never seen KBC reverting to legacy | |
455 | * mode yet, when we see one we'll add proper handling). | |
456 | * Anyway, we will assume that the data came from the same serio last byte | |
457 | * was transmitted (if transmission happened not too long ago). | |
458 | */ | |
459 | if (time_before(jiffies, last_transmit + HZ/10)) { | |
460 | str = last_str; | |
461 | break; | |
462 | } | |
463 | /* fall through - report timeout */ | |
464 | case 0xfd: | |
465 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
466 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
467 | } | |
468 | } | |
469 | ||
470 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
471 | last_str = str; | |
472 | last_transmit = jiffies; | |
473 | } else { | |
474 | ||
475 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
476 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | |
477 | ||
478 | port_no = (str & I8042_STR_AUXDATA) ? | |
479 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
480 | } | |
481 | ||
482 | port = &i8042_ports[port_no]; | |
483 | ||
484 | dbg("%02x <- i8042 (interrupt, %s, %d%s%s)", | |
485 | data, port->name, irq, | |
486 | dfl & SERIO_PARITY ? ", bad parity" : "", | |
487 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
488 | ||
489 | if (likely(port->exists)) | |
490 | serio_interrupt(port->serio, data, dfl, regs); | |
491 | ||
492 | ret = 1; | |
0854e52d | 493 | out: |
1da177e4 LT |
494 | return IRQ_RETVAL(ret); |
495 | } | |
496 | ||
497 | /* | |
498 | * i8042_set_mux_mode checks whether the controller has an active | |
499 | * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode. | |
500 | */ | |
501 | ||
502 | static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version) | |
503 | { | |
504 | ||
505 | unsigned char param; | |
506 | /* | |
507 | * Get rid of bytes in the queue. | |
508 | */ | |
509 | ||
510 | i8042_flush(); | |
511 | ||
512 | /* | |
513 | * Internal loopback test - send three bytes, they should come back from the | |
514 | * mouse interface, the last should be version. Note that we negate mouseport | |
515 | * command responses for the i8042_check_aux() routine. | |
516 | */ | |
517 | ||
518 | param = 0xf0; | |
463a4f76 | 519 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xf0) |
1da177e4 LT |
520 | return -1; |
521 | param = mode ? 0x56 : 0xf6; | |
463a4f76 | 522 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6)) |
1da177e4 LT |
523 | return -1; |
524 | param = mode ? 0xa4 : 0xa5; | |
463a4f76 | 525 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5)) |
1da177e4 LT |
526 | return -1; |
527 | ||
528 | if (mux_version) | |
463a4f76 | 529 | *mux_version = param; |
1da177e4 LT |
530 | |
531 | return 0; | |
532 | } | |
533 | ||
534 | ||
535 | /* | |
536 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
537 | * the controller has been switched into Multiplexed mode | |
538 | */ | |
539 | ||
540 | static int i8042_enable_mux_ports(void) | |
541 | { | |
542 | unsigned char param; | |
543 | int i; | |
544 | /* | |
545 | * Disable all muxed ports by disabling AUX. | |
546 | */ | |
547 | ||
548 | i8042_ctr |= I8042_CTR_AUXDIS; | |
549 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
550 | ||
551 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
552 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | |
553 | return -1; | |
554 | } | |
555 | ||
556 | /* | |
557 | * Enable all muxed ports. | |
558 | */ | |
559 | ||
0854e52d | 560 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { |
1da177e4 LT |
561 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); |
562 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
563 | } | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
568 | ||
569 | /* | |
570 | * i8042_check_mux() checks whether the controller supports the PS/2 Active | |
571 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
572 | * LCS/Telegraphics. | |
573 | */ | |
574 | ||
575 | static int __init i8042_check_mux(void) | |
576 | { | |
577 | unsigned char mux_version; | |
578 | ||
579 | if (i8042_set_mux_mode(1, &mux_version)) | |
580 | return -1; | |
581 | ||
582 | /* Workaround for interference with USB Legacy emulation */ | |
583 | /* that causes a v10.12 MUX to be found. */ | |
584 | if (mux_version == 0xAC) | |
585 | return -1; | |
586 | ||
587 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | |
588 | (mux_version >> 4) & 0xf, mux_version & 0xf); | |
589 | ||
590 | if (i8042_enable_mux_ports()) | |
591 | return -1; | |
592 | ||
593 | i8042_mux_present = 1; | |
594 | return 0; | |
595 | } | |
596 | ||
597 | ||
598 | /* | |
599 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
600 | * the presence of an AUX interface. | |
601 | */ | |
602 | ||
603 | static int __init i8042_check_aux(void) | |
604 | { | |
605 | unsigned char param; | |
606 | static int i8042_check_aux_cookie; | |
607 | ||
608 | /* | |
609 | * Check if AUX irq is available. If it isn't, then there is no point | |
610 | * in trying to detect AUX presence. | |
611 | */ | |
612 | ||
613 | if (request_irq(i8042_ports[I8042_AUX_PORT_NO].irq, i8042_interrupt, | |
614 | SA_SHIRQ, "i8042", &i8042_check_aux_cookie)) | |
615 | return -1; | |
616 | free_irq(i8042_ports[I8042_AUX_PORT_NO].irq, &i8042_check_aux_cookie); | |
617 | ||
618 | /* | |
619 | * Get rid of bytes in the queue. | |
620 | */ | |
621 | ||
622 | i8042_flush(); | |
623 | ||
624 | /* | |
625 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
626 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
627 | * though it has an AUX port. | |
628 | */ | |
629 | ||
630 | param = 0x5a; | |
463a4f76 | 631 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0x5a) { |
1da177e4 LT |
632 | |
633 | /* | |
634 | * External connection test - filters out AT-soldered PS/2 i8042's | |
635 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
636 | * 0xfa - no error on some notebooks which ignore the spec | |
637 | * Because it's common for chipsets to return error on perfectly functioning | |
638 | * AUX ports, we test for this only when the LOOP command failed. | |
639 | */ | |
640 | ||
641 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) | |
463a4f76 | 642 | || (param && param != 0xfa && param != 0xff)) |
1da177e4 LT |
643 | return -1; |
644 | } | |
645 | ||
646 | /* | |
647 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
648 | */ | |
649 | ||
650 | if (i8042_command(¶m, I8042_CMD_AUX_DISABLE)) | |
651 | return -1; | |
652 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) { | |
653 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); | |
654 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | |
655 | } | |
656 | ||
657 | if (i8042_command(¶m, I8042_CMD_AUX_ENABLE)) | |
658 | return -1; | |
659 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS)) | |
660 | return -1; | |
661 | ||
662 | /* | |
663 | * Disable the interface. | |
664 | */ | |
665 | ||
666 | i8042_ctr |= I8042_CTR_AUXDIS; | |
667 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
668 | ||
669 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
670 | return -1; | |
671 | ||
672 | return 0; | |
673 | } | |
674 | ||
675 | ||
676 | /* | |
677 | * i8042_port_register() marks the device as existing, | |
678 | * registers it, and reports to the user. | |
679 | */ | |
680 | ||
681 | static int __init i8042_port_register(struct i8042_port *port) | |
682 | { | |
683 | i8042_ctr &= ~port->disable; | |
684 | ||
685 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
686 | printk(KERN_WARNING "i8042.c: Can't write CTR while registering.\n"); | |
687 | kfree(port->serio); | |
688 | port->serio = NULL; | |
689 | i8042_ctr |= port->disable; | |
0854e52d | 690 | return -EIO; |
1da177e4 LT |
691 | } |
692 | ||
693 | printk(KERN_INFO "serio: i8042 %s port at %#lx,%#lx irq %d\n", | |
694 | port->name, | |
695 | (unsigned long) I8042_DATA_REG, | |
696 | (unsigned long) I8042_COMMAND_REG, | |
697 | port->irq); | |
698 | ||
699 | serio_register_port(port->serio); | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
704 | ||
705 | static void i8042_timer_func(unsigned long data) | |
706 | { | |
707 | i8042_interrupt(0, NULL, NULL); | |
708 | } | |
709 | ||
2673c836 VP |
710 | static int i8042_ctl_test(void) |
711 | { | |
712 | unsigned char param; | |
713 | ||
714 | if (!i8042_reset) | |
715 | return 0; | |
716 | ||
717 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
718 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | |
719 | return -1; | |
720 | } | |
721 | ||
722 | if (param != I8042_RET_CTL_TEST) { | |
723 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", | |
724 | param, I8042_RET_CTL_TEST); | |
725 | return -1; | |
726 | } | |
727 | ||
728 | return 0; | |
729 | } | |
1da177e4 LT |
730 | |
731 | /* | |
732 | * i8042_controller init initializes the i8042 controller, and, | |
733 | * most importantly, sets it into non-xlated mode if that's | |
734 | * desired. | |
735 | */ | |
736 | ||
737 | static int i8042_controller_init(void) | |
738 | { | |
739 | unsigned long flags; | |
740 | ||
741 | /* | |
742 | * Test the i8042. We need to know if it thinks it's working correctly | |
743 | * before doing anything else. | |
744 | */ | |
745 | ||
746 | if (i8042_flush() == I8042_BUFFER_SIZE) { | |
747 | printk(KERN_ERR "i8042.c: No controller found.\n"); | |
748 | return -1; | |
749 | } | |
750 | ||
2673c836 VP |
751 | if (i8042_ctl_test()) |
752 | return -1; | |
1da177e4 LT |
753 | |
754 | /* | |
755 | * Save the CTR for restoral on unload / reboot. | |
756 | */ | |
757 | ||
758 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { | |
759 | printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); | |
760 | return -1; | |
761 | } | |
762 | ||
763 | i8042_initial_ctr = i8042_ctr; | |
764 | ||
765 | /* | |
766 | * Disable the keyboard interface and interrupt. | |
767 | */ | |
768 | ||
769 | i8042_ctr |= I8042_CTR_KBDDIS; | |
770 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
771 | ||
772 | /* | |
773 | * Handle keylock. | |
774 | */ | |
775 | ||
776 | spin_lock_irqsave(&i8042_lock, flags); | |
777 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
778 | if (i8042_unlock) | |
779 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
780 | else | |
781 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); | |
782 | } | |
783 | spin_unlock_irqrestore(&i8042_lock, flags); | |
784 | ||
785 | /* | |
786 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
787 | * bother enabling translating and be happy. | |
788 | */ | |
789 | ||
790 | if (~i8042_ctr & I8042_CTR_XLATE) | |
791 | i8042_direct = 1; | |
792 | ||
793 | /* | |
794 | * Set nontranslated mode for the kbd interface if requested by an option. | |
795 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
796 | * interface is. We don't do this by default, since it can confuse notebook | |
797 | * BIOSes. | |
798 | */ | |
799 | ||
800 | if (i8042_direct) | |
801 | i8042_ctr &= ~I8042_CTR_XLATE; | |
802 | ||
803 | /* | |
804 | * Write CTR back. | |
805 | */ | |
806 | ||
807 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
808 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | |
809 | return -1; | |
810 | } | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
815 | ||
816 | /* | |
817 | * Reset the controller. | |
818 | */ | |
819 | static void i8042_controller_reset(void) | |
820 | { | |
1da177e4 LT |
821 | /* |
822 | * Reset the controller if requested. | |
823 | */ | |
824 | ||
2673c836 | 825 | i8042_ctl_test(); |
1da177e4 LT |
826 | |
827 | /* | |
828 | * Disable MUX mode if present. | |
829 | */ | |
830 | ||
831 | if (i8042_mux_present) | |
832 | i8042_set_mux_mode(0, NULL); | |
833 | ||
834 | /* | |
835 | * Restore the original control register setting. | |
836 | */ | |
837 | ||
838 | i8042_ctr = i8042_initial_ctr; | |
839 | ||
840 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
841 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); | |
842 | } | |
843 | ||
844 | ||
845 | /* | |
846 | * Here we try to reset everything back to a state in which the BIOS will be | |
847 | * able to talk to the hardware when rebooting. | |
848 | */ | |
849 | ||
850 | static void i8042_controller_cleanup(void) | |
851 | { | |
852 | int i; | |
853 | ||
854 | i8042_flush(); | |
855 | ||
856 | /* | |
857 | * Reset anything that is connected to the ports. | |
858 | */ | |
859 | ||
860 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
861 | if (i8042_ports[i].exists) | |
862 | serio_cleanup(i8042_ports[i].serio); | |
863 | ||
864 | i8042_controller_reset(); | |
865 | } | |
866 | ||
867 | ||
868 | /* | |
869 | * i8042_panic_blink() will flash the keyboard LEDs and is called when | |
870 | * kernel panics. Flashing LEDs is useful for users running X who may | |
871 | * not see the console and will help distingushing panics from "real" | |
872 | * lockups. | |
873 | * | |
874 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
875 | * waiting for KBC to free up even if KBD interrupt is off | |
876 | */ | |
877 | ||
878 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
879 | ||
880 | static long i8042_panic_blink(long count) | |
881 | { | |
882 | long delay = 0; | |
883 | static long last_blink; | |
884 | static char led; | |
885 | ||
886 | /* | |
887 | * We expect frequency to be about 1/2s. KDB uses about 1s. | |
888 | * Make sure they are different. | |
889 | */ | |
890 | if (!i8042_blink_frequency) | |
891 | return 0; | |
892 | if (count - last_blink < i8042_blink_frequency) | |
893 | return 0; | |
894 | ||
895 | led ^= 0x01 | 0x04; | |
896 | while (i8042_read_status() & I8042_STR_IBF) | |
897 | DELAY; | |
898 | i8042_write_data(0xed); /* set leds */ | |
899 | DELAY; | |
900 | while (i8042_read_status() & I8042_STR_IBF) | |
901 | DELAY; | |
902 | DELAY; | |
903 | i8042_write_data(led); | |
904 | DELAY; | |
905 | last_blink = count; | |
906 | return delay; | |
907 | } | |
908 | ||
909 | #undef DELAY | |
910 | ||
911 | /* | |
912 | * Here we try to restore the original BIOS settings | |
913 | */ | |
914 | ||
9480e307 | 915 | static int i8042_suspend(struct device *dev, pm_message_t state) |
1da177e4 | 916 | { |
9480e307 RK |
917 | del_timer_sync(&i8042_timer); |
918 | i8042_controller_reset(); | |
1da177e4 LT |
919 | |
920 | return 0; | |
921 | } | |
922 | ||
923 | ||
924 | /* | |
925 | * Here we try to reset everything back to a state in which suspended | |
926 | */ | |
927 | ||
9480e307 | 928 | static int i8042_resume(struct device *dev) |
1da177e4 LT |
929 | { |
930 | int i; | |
931 | ||
2673c836 VP |
932 | if (i8042_ctl_test()) |
933 | return -1; | |
934 | ||
935 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
936 | printk(KERN_ERR "i8042: Can't write CTR\n"); | |
1da177e4 LT |
937 | return -1; |
938 | } | |
939 | ||
940 | if (i8042_mux_present) | |
941 | if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports()) | |
942 | printk(KERN_WARNING "i8042: failed to resume active multiplexor, mouse won't work.\n"); | |
943 | ||
944 | /* | |
945 | * Activate all ports. | |
946 | */ | |
947 | ||
948 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
949 | i8042_activate_port(&i8042_ports[i]); | |
950 | ||
951 | /* | |
952 | * Restart timer (for polling "stuck" data) | |
953 | */ | |
954 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
955 | ||
956 | panic_blink = i8042_panic_blink; | |
957 | ||
958 | return 0; | |
959 | ||
960 | } | |
961 | ||
962 | /* | |
963 | * We need to reset the 8042 back to original mode on system shutdown, | |
964 | * because otherwise BIOSes will be confused. | |
965 | */ | |
966 | ||
967 | static void i8042_shutdown(struct device *dev) | |
968 | { | |
969 | i8042_controller_cleanup(); | |
970 | } | |
971 | ||
972 | static struct device_driver i8042_driver = { | |
973 | .name = "i8042", | |
974 | .bus = &platform_bus_type, | |
975 | .suspend = i8042_suspend, | |
976 | .resume = i8042_resume, | |
977 | .shutdown = i8042_shutdown, | |
978 | }; | |
979 | ||
0854e52d | 980 | static int __init i8042_create_kbd_port(void) |
1da177e4 LT |
981 | { |
982 | struct serio *serio; | |
983 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
984 | ||
d39969de | 985 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
986 | if (!serio) |
987 | return -ENOMEM; | |
988 | ||
989 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
990 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
991 | serio->open = i8042_open; | |
992 | serio->close = i8042_close; | |
993 | serio->start = i8042_start; | |
994 | serio->stop = i8042_stop; | |
995 | serio->port_data = port; | |
996 | serio->dev.parent = &i8042_platform_device->dev; | |
997 | strlcpy(serio->name, "i8042 Kbd Port", sizeof(serio->name)); | |
998 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); | |
999 | ||
1000 | port->serio = serio; | |
1001 | ||
1002 | return i8042_port_register(port); | |
1da177e4 LT |
1003 | } |
1004 | ||
0854e52d | 1005 | static int __init i8042_create_aux_port(void) |
1da177e4 LT |
1006 | { |
1007 | struct serio *serio; | |
1008 | struct i8042_port *port = &i8042_ports[I8042_AUX_PORT_NO]; | |
1009 | ||
d39969de | 1010 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1011 | if (!serio) |
1012 | return -ENOMEM; | |
1013 | ||
1014 | serio->id.type = SERIO_8042; | |
1015 | serio->write = i8042_aux_write; | |
1016 | serio->open = i8042_open; | |
1017 | serio->close = i8042_close; | |
1018 | serio->start = i8042_start; | |
1019 | serio->stop = i8042_stop; | |
1020 | serio->port_data = port; | |
1021 | serio->dev.parent = &i8042_platform_device->dev; | |
1022 | strlcpy(serio->name, "i8042 Aux Port", sizeof(serio->name)); | |
1023 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
1024 | ||
1025 | port->serio = serio; | |
1026 | ||
1027 | return i8042_port_register(port); | |
1da177e4 LT |
1028 | } |
1029 | ||
0854e52d | 1030 | static int __init i8042_create_mux_port(int index) |
1da177e4 LT |
1031 | { |
1032 | struct serio *serio; | |
1033 | struct i8042_port *port = &i8042_ports[I8042_MUX_PORT_NO + index]; | |
1034 | ||
d39969de | 1035 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1036 | if (!serio) |
1037 | return -ENOMEM; | |
1038 | ||
1039 | serio->id.type = SERIO_8042; | |
1040 | serio->write = i8042_aux_write; | |
1041 | serio->open = i8042_open; | |
1042 | serio->close = i8042_close; | |
1043 | serio->start = i8042_start; | |
1044 | serio->stop = i8042_stop; | |
1045 | serio->port_data = port; | |
1046 | serio->dev.parent = &i8042_platform_device->dev; | |
1047 | snprintf(serio->name, sizeof(serio->name), "i8042 Aux-%d Port", index); | |
1048 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, index + 1); | |
1049 | ||
1050 | *port = i8042_ports[I8042_AUX_PORT_NO]; | |
1051 | port->exists = 0; | |
1052 | snprintf(port->name, sizeof(port->name), "AUX%d", index); | |
1053 | port->mux = index; | |
1054 | port->serio = serio; | |
1055 | ||
1056 | return i8042_port_register(port); | |
1da177e4 LT |
1057 | } |
1058 | ||
1059 | static int __init i8042_init(void) | |
1060 | { | |
945ef0d4 | 1061 | int i, have_ports = 0; |
1da177e4 LT |
1062 | int err; |
1063 | ||
1064 | dbg_init(); | |
1065 | ||
1066 | init_timer(&i8042_timer); | |
1067 | i8042_timer.function = i8042_timer_func; | |
1068 | ||
8d5987a6 DT |
1069 | err = i8042_platform_init(); |
1070 | if (err) | |
1071 | return err; | |
1da177e4 LT |
1072 | |
1073 | i8042_ports[I8042_AUX_PORT_NO].irq = I8042_AUX_IRQ; | |
1074 | i8042_ports[I8042_KBD_PORT_NO].irq = I8042_KBD_IRQ; | |
1075 | ||
1076 | if (i8042_controller_init()) { | |
0854e52d DT |
1077 | err = -ENODEV; |
1078 | goto err_platform_exit; | |
1da177e4 LT |
1079 | } |
1080 | ||
1081 | err = driver_register(&i8042_driver); | |
0854e52d DT |
1082 | if (err) |
1083 | goto err_controller_cleanup; | |
1da177e4 LT |
1084 | |
1085 | i8042_platform_device = platform_device_register_simple("i8042", -1, NULL, 0); | |
1086 | if (IS_ERR(i8042_platform_device)) { | |
0854e52d DT |
1087 | err = PTR_ERR(i8042_platform_device); |
1088 | goto err_unregister_driver; | |
1da177e4 LT |
1089 | } |
1090 | ||
1091 | if (!i8042_noaux && !i8042_check_aux()) { | |
0854e52d DT |
1092 | if (!i8042_nomux && !i8042_check_mux()) { |
1093 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1094 | err = i8042_create_mux_port(i); | |
1095 | if (err) | |
1096 | goto err_unregister_ports; | |
1097 | } | |
1098 | } else { | |
1099 | err = i8042_create_aux_port(); | |
1100 | if (err) | |
1101 | goto err_unregister_ports; | |
1102 | } | |
945ef0d4 | 1103 | have_ports = 1; |
1da177e4 LT |
1104 | } |
1105 | ||
945ef0d4 DT |
1106 | if (!i8042_nokbd) { |
1107 | err = i8042_create_kbd_port(); | |
1108 | if (err) | |
1109 | goto err_unregister_ports; | |
1110 | have_ports = 1; | |
1111 | } | |
1112 | ||
1113 | if (!have_ports) { | |
1114 | err = -ENODEV; | |
1115 | goto err_unregister_device; | |
1116 | } | |
1da177e4 LT |
1117 | |
1118 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
1119 | ||
1120 | return 0; | |
0854e52d DT |
1121 | |
1122 | err_unregister_ports: | |
1123 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1124 | if (i8042_ports[i].serio) | |
1125 | serio_unregister_port(i8042_ports[i].serio); | |
945ef0d4 | 1126 | err_unregister_device: |
0854e52d DT |
1127 | platform_device_unregister(i8042_platform_device); |
1128 | err_unregister_driver: | |
1129 | driver_unregister(&i8042_driver); | |
1130 | err_controller_cleanup: | |
1131 | i8042_controller_cleanup(); | |
1132 | err_platform_exit: | |
1133 | i8042_platform_exit(); | |
1134 | ||
1135 | return err; | |
1da177e4 LT |
1136 | } |
1137 | ||
1138 | static void __exit i8042_exit(void) | |
1139 | { | |
1140 | int i; | |
1141 | ||
1142 | i8042_controller_cleanup(); | |
1143 | ||
1144 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1145 | if (i8042_ports[i].exists) | |
1146 | serio_unregister_port(i8042_ports[i].serio); | |
1147 | ||
1148 | del_timer_sync(&i8042_timer); | |
1149 | ||
1150 | platform_device_unregister(i8042_platform_device); | |
1151 | driver_unregister(&i8042_driver); | |
1152 | ||
1153 | i8042_platform_exit(); | |
1154 | ||
1155 | panic_blink = NULL; | |
1156 | } | |
1157 | ||
1158 | module_init(i8042_init); | |
1159 | module_exit(i8042_exit); |