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1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/delay.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ioport.h> | |
1da177e4 LT |
18 | #include <linux/init.h> |
19 | #include <linux/serio.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/rcupdate.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | |
24 | #include <asm/io.h> | |
25 | ||
26 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
27 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
28 | MODULE_LICENSE("GPL"); | |
29 | ||
945ef0d4 DT |
30 | static unsigned int i8042_nokbd; |
31 | module_param_named(nokbd, i8042_nokbd, bool, 0); | |
32 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
33 | ||
1da177e4 LT |
34 | static unsigned int i8042_noaux; |
35 | module_param_named(noaux, i8042_noaux, bool, 0); | |
36 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
37 | ||
38 | static unsigned int i8042_nomux; | |
39 | module_param_named(nomux, i8042_nomux, bool, 0); | |
40 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); | |
41 | ||
42 | static unsigned int i8042_unlock; | |
43 | module_param_named(unlock, i8042_unlock, bool, 0); | |
44 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
45 | ||
46 | static unsigned int i8042_reset; | |
47 | module_param_named(reset, i8042_reset, bool, 0); | |
48 | MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); | |
49 | ||
50 | static unsigned int i8042_direct; | |
51 | module_param_named(direct, i8042_direct, bool, 0); | |
52 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
53 | ||
54 | static unsigned int i8042_dumbkbd; | |
55 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); | |
56 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
57 | ||
58 | static unsigned int i8042_noloop; | |
59 | module_param_named(noloop, i8042_noloop, bool, 0); | |
60 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
61 | ||
62 | static unsigned int i8042_blink_frequency = 500; | |
63 | module_param_named(panicblink, i8042_blink_frequency, uint, 0600); | |
64 | MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); | |
65 | ||
66 | #ifdef CONFIG_PNP | |
67 | static int i8042_nopnp; | |
68 | module_param_named(nopnp, i8042_nopnp, bool, 0); | |
69 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
70 | #endif | |
71 | ||
72 | #define DEBUG | |
73 | #ifdef DEBUG | |
74 | static int i8042_debug; | |
75 | module_param_named(debug, i8042_debug, bool, 0600); | |
76 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
77 | #endif | |
78 | ||
79 | __obsolete_setup("i8042_noaux"); | |
80 | __obsolete_setup("i8042_nomux"); | |
81 | __obsolete_setup("i8042_unlock"); | |
82 | __obsolete_setup("i8042_reset"); | |
83 | __obsolete_setup("i8042_direct"); | |
84 | __obsolete_setup("i8042_dumbkbd"); | |
85 | ||
86 | #include "i8042.h" | |
87 | ||
88 | static DEFINE_SPINLOCK(i8042_lock); | |
89 | ||
90 | struct i8042_port { | |
91 | struct serio *serio; | |
92 | int irq; | |
93 | unsigned char disable; | |
94 | unsigned char irqen; | |
95 | unsigned char exists; | |
96 | signed char mux; | |
97 | char name[8]; | |
98 | }; | |
99 | ||
100 | #define I8042_KBD_PORT_NO 0 | |
101 | #define I8042_AUX_PORT_NO 1 | |
102 | #define I8042_MUX_PORT_NO 2 | |
103 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
104 | static struct i8042_port i8042_ports[I8042_NUM_PORTS] = { | |
105 | { | |
106 | .disable = I8042_CTR_KBDDIS, | |
463a4f76 | 107 | .irqen = I8042_CTR_KBDINT, |
1da177e4 LT |
108 | .mux = -1, |
109 | .name = "KBD", | |
110 | }, | |
111 | { | |
112 | .disable = I8042_CTR_AUXDIS, | |
113 | .irqen = I8042_CTR_AUXINT, | |
114 | .mux = -1, | |
115 | .name = "AUX", | |
116 | } | |
117 | }; | |
118 | ||
119 | static unsigned char i8042_initial_ctr; | |
120 | static unsigned char i8042_ctr; | |
121 | static unsigned char i8042_mux_open; | |
122 | static unsigned char i8042_mux_present; | |
123 | static struct timer_list i8042_timer; | |
124 | static struct platform_device *i8042_platform_device; | |
125 | ||
126 | ||
127 | /* | |
128 | * Shared IRQ's require a device pointer, but this driver doesn't support | |
129 | * multiple devices | |
130 | */ | |
131 | #define i8042_request_irq_cookie (&i8042_timer) | |
132 | ||
133 | static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs); | |
134 | ||
135 | /* | |
136 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
137 | * be ready for reading values from it / writing values to it. | |
138 | * Called always with i8042_lock held. | |
139 | */ | |
140 | ||
141 | static int i8042_wait_read(void) | |
142 | { | |
143 | int i = 0; | |
144 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { | |
145 | udelay(50); | |
146 | i++; | |
147 | } | |
148 | return -(i == I8042_CTL_TIMEOUT); | |
149 | } | |
150 | ||
151 | static int i8042_wait_write(void) | |
152 | { | |
153 | int i = 0; | |
154 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { | |
155 | udelay(50); | |
156 | i++; | |
157 | } | |
158 | return -(i == I8042_CTL_TIMEOUT); | |
159 | } | |
160 | ||
161 | /* | |
162 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
163 | * of the i8042 down the toilet. | |
164 | */ | |
165 | ||
166 | static int i8042_flush(void) | |
167 | { | |
168 | unsigned long flags; | |
169 | unsigned char data, str; | |
170 | int i = 0; | |
171 | ||
172 | spin_lock_irqsave(&i8042_lock, flags); | |
173 | ||
174 | while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { | |
175 | udelay(50); | |
176 | data = i8042_read_data(); | |
177 | i++; | |
178 | dbg("%02x <- i8042 (flush, %s)", data, | |
179 | str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
180 | } | |
181 | ||
182 | spin_unlock_irqrestore(&i8042_lock, flags); | |
183 | ||
184 | return i; | |
185 | } | |
186 | ||
187 | /* | |
188 | * i8042_command() executes a command on the i8042. It also sends the input | |
189 | * parameter(s) of the commands to it, and receives the output value(s). The | |
190 | * parameters are to be stored in the param array, and the output is placed | |
191 | * into the same array. The number of the parameters and output values is | |
192 | * encoded in bits 8-11 of the command number. | |
193 | */ | |
194 | ||
195 | static int i8042_command(unsigned char *param, int command) | |
196 | { | |
197 | unsigned long flags; | |
463a4f76 | 198 | int i, retval, auxerr = 0; |
1da177e4 LT |
199 | |
200 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
201 | return -1; | |
202 | ||
203 | spin_lock_irqsave(&i8042_lock, flags); | |
204 | ||
463a4f76 DT |
205 | if ((retval = i8042_wait_write())) |
206 | goto out; | |
207 | ||
208 | dbg("%02x -> i8042 (command)", command & 0xff); | |
209 | i8042_write_command(command & 0xff); | |
210 | ||
211 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
212 | if ((retval = i8042_wait_write())) | |
213 | goto out; | |
214 | dbg("%02x -> i8042 (parameter)", param[i]); | |
215 | i8042_write_data(param[i]); | |
1da177e4 LT |
216 | } |
217 | ||
463a4f76 DT |
218 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
219 | if ((retval = i8042_wait_read())) | |
220 | goto out; | |
1da177e4 | 221 | |
463a4f76 DT |
222 | if (command == I8042_CMD_AUX_LOOP && |
223 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
224 | retval = auxerr = -1; | |
225 | goto out; | |
1da177e4 LT |
226 | } |
227 | ||
463a4f76 DT |
228 | param[i] = i8042_read_data(); |
229 | dbg("%02x <- i8042 (return)", param[i]); | |
230 | } | |
1da177e4 LT |
231 | |
232 | if (retval) | |
463a4f76 | 233 | dbg(" -- i8042 (%s)", auxerr ? "auxerr" : "timeout"); |
1da177e4 | 234 | |
463a4f76 DT |
235 | out: |
236 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 LT |
237 | return retval; |
238 | } | |
239 | ||
240 | /* | |
241 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
242 | */ | |
243 | ||
244 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
245 | { | |
246 | unsigned long flags; | |
247 | int retval = 0; | |
248 | ||
249 | spin_lock_irqsave(&i8042_lock, flags); | |
250 | ||
251 | if(!(retval = i8042_wait_write())) { | |
252 | dbg("%02x -> i8042 (kbd-data)", c); | |
253 | i8042_write_data(c); | |
254 | } | |
255 | ||
256 | spin_unlock_irqrestore(&i8042_lock, flags); | |
257 | ||
258 | return retval; | |
259 | } | |
260 | ||
261 | /* | |
262 | * i8042_aux_write() sends a byte out through the aux interface. | |
263 | */ | |
264 | ||
265 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
266 | { | |
267 | struct i8042_port *port = serio->port_data; | |
268 | int retval; | |
269 | ||
270 | /* | |
271 | * Send the byte out. | |
272 | */ | |
273 | ||
274 | if (port->mux == -1) | |
275 | retval = i8042_command(&c, I8042_CMD_AUX_SEND); | |
276 | else | |
277 | retval = i8042_command(&c, I8042_CMD_MUX_SEND + port->mux); | |
278 | ||
279 | /* | |
280 | * Make sure the interrupt happens and the character is received even | |
281 | * in the case the IRQ isn't wired, so that we can receive further | |
282 | * characters later. | |
283 | */ | |
284 | ||
285 | i8042_interrupt(0, NULL, NULL); | |
286 | return retval; | |
287 | } | |
288 | ||
289 | /* | |
290 | * i8042_activate_port() enables port on a chip. | |
291 | */ | |
292 | ||
293 | static int i8042_activate_port(struct i8042_port *port) | |
294 | { | |
295 | if (!port->serio) | |
296 | return -1; | |
297 | ||
298 | i8042_flush(); | |
299 | ||
300 | /* | |
301 | * Enable port again here because it is disabled if we are | |
302 | * resuming (normally it is enabled already). | |
303 | */ | |
304 | i8042_ctr &= ~port->disable; | |
305 | ||
306 | i8042_ctr |= port->irqen; | |
307 | ||
308 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
309 | i8042_ctr &= ~port->irqen; | |
310 | return -1; | |
311 | } | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | ||
317 | /* | |
318 | * i8042_open() is called when a port is open by the higher layer. | |
319 | * It allocates the interrupt and calls i8042_enable_port. | |
320 | */ | |
321 | ||
322 | static int i8042_open(struct serio *serio) | |
323 | { | |
324 | struct i8042_port *port = serio->port_data; | |
325 | ||
326 | if (port->mux != -1) | |
327 | if (i8042_mux_open++) | |
328 | return 0; | |
329 | ||
330 | if (request_irq(port->irq, i8042_interrupt, | |
331 | SA_SHIRQ, "i8042", i8042_request_irq_cookie)) { | |
332 | printk(KERN_ERR "i8042.c: Can't get irq %d for %s, unregistering the port.\n", port->irq, port->name); | |
333 | goto irq_fail; | |
334 | } | |
335 | ||
336 | if (i8042_activate_port(port)) { | |
337 | printk(KERN_ERR "i8042.c: Can't activate %s, unregistering the port\n", port->name); | |
338 | goto activate_fail; | |
339 | } | |
340 | ||
341 | i8042_interrupt(0, NULL, NULL); | |
342 | ||
343 | return 0; | |
344 | ||
0854e52d | 345 | activate_fail: |
1da177e4 LT |
346 | free_irq(port->irq, i8042_request_irq_cookie); |
347 | ||
0854e52d | 348 | irq_fail: |
1da177e4 LT |
349 | serio_unregister_port_delayed(serio); |
350 | ||
351 | return -1; | |
352 | } | |
353 | ||
354 | /* | |
355 | * i8042_close() frees the interrupt, so that it can possibly be used | |
356 | * by another driver. We never know - if the user doesn't have a mouse, | |
357 | * the BIOS could have used the AUX interrupt for PCI. | |
358 | */ | |
359 | ||
360 | static void i8042_close(struct serio *serio) | |
361 | { | |
362 | struct i8042_port *port = serio->port_data; | |
363 | ||
364 | if (port->mux != -1) | |
365 | if (--i8042_mux_open) | |
366 | return; | |
367 | ||
368 | i8042_ctr &= ~port->irqen; | |
369 | ||
370 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
371 | printk(KERN_WARNING "i8042.c: Can't write CTR while closing %s.\n", port->name); | |
372 | /* | |
373 | * We still want to continue and free IRQ so if more data keeps coming in | |
374 | * kernel will just ignore the irq. | |
375 | */ | |
376 | } | |
377 | ||
378 | free_irq(port->irq, i8042_request_irq_cookie); | |
379 | ||
380 | i8042_flush(); | |
381 | } | |
382 | ||
383 | /* | |
384 | * i8042_start() is called by serio core when port is about to finish | |
385 | * registering. It will mark port as existing so i8042_interrupt can | |
386 | * start sending data through it. | |
387 | */ | |
388 | static int i8042_start(struct serio *serio) | |
389 | { | |
390 | struct i8042_port *port = serio->port_data; | |
391 | ||
392 | port->exists = 1; | |
393 | mb(); | |
394 | return 0; | |
395 | } | |
396 | ||
397 | /* | |
398 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
399 | * will not try to send data to the port that is about to go away. | |
400 | * The function is called by serio core as part of unregister procedure. | |
401 | */ | |
402 | static void i8042_stop(struct serio *serio) | |
403 | { | |
404 | struct i8042_port *port = serio->port_data; | |
405 | ||
406 | port->exists = 0; | |
b2b18660 | 407 | synchronize_sched(); |
1da177e4 LT |
408 | port->serio = NULL; |
409 | } | |
410 | ||
411 | /* | |
412 | * i8042_interrupt() is the most important function in this driver - | |
413 | * it handles the interrupts from the i8042, and sends incoming bytes | |
414 | * to the upper layers. | |
415 | */ | |
416 | ||
417 | static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
418 | { | |
419 | struct i8042_port *port; | |
420 | unsigned long flags; | |
421 | unsigned char str, data; | |
422 | unsigned int dfl; | |
423 | unsigned int port_no; | |
424 | int ret; | |
425 | ||
426 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
427 | ||
428 | spin_lock_irqsave(&i8042_lock, flags); | |
429 | str = i8042_read_status(); | |
430 | if (unlikely(~str & I8042_STR_OBF)) { | |
431 | spin_unlock_irqrestore(&i8042_lock, flags); | |
432 | if (irq) dbg("Interrupt %d, without any data", irq); | |
433 | ret = 0; | |
434 | goto out; | |
435 | } | |
436 | data = i8042_read_data(); | |
437 | spin_unlock_irqrestore(&i8042_lock, flags); | |
438 | ||
439 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
440 | static unsigned long last_transmit; | |
441 | static unsigned char last_str; | |
442 | ||
443 | dfl = 0; | |
444 | if (str & I8042_STR_MUXERR) { | |
445 | dbg("MUX error, status is %02x, data is %02x", str, data); | |
446 | switch (data) { | |
447 | default: | |
448 | /* | |
449 | * When MUXERR condition is signalled the data register can only contain | |
450 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
451 | * it is not always the case. Some KBC just get confused which port the | |
452 | * data came from and signal error leaving the data intact. They _do not_ | |
453 | * revert to legacy mode (actually I've never seen KBC reverting to legacy | |
454 | * mode yet, when we see one we'll add proper handling). | |
455 | * Anyway, we will assume that the data came from the same serio last byte | |
456 | * was transmitted (if transmission happened not too long ago). | |
457 | */ | |
458 | if (time_before(jiffies, last_transmit + HZ/10)) { | |
459 | str = last_str; | |
460 | break; | |
461 | } | |
462 | /* fall through - report timeout */ | |
463 | case 0xfd: | |
464 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
465 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
466 | } | |
467 | } | |
468 | ||
469 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
470 | last_str = str; | |
471 | last_transmit = jiffies; | |
472 | } else { | |
473 | ||
474 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
475 | ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); | |
476 | ||
477 | port_no = (str & I8042_STR_AUXDATA) ? | |
478 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
479 | } | |
480 | ||
481 | port = &i8042_ports[port_no]; | |
482 | ||
483 | dbg("%02x <- i8042 (interrupt, %s, %d%s%s)", | |
484 | data, port->name, irq, | |
485 | dfl & SERIO_PARITY ? ", bad parity" : "", | |
486 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
487 | ||
488 | if (likely(port->exists)) | |
489 | serio_interrupt(port->serio, data, dfl, regs); | |
490 | ||
491 | ret = 1; | |
0854e52d | 492 | out: |
1da177e4 LT |
493 | return IRQ_RETVAL(ret); |
494 | } | |
495 | ||
496 | /* | |
497 | * i8042_set_mux_mode checks whether the controller has an active | |
498 | * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode. | |
499 | */ | |
500 | ||
501 | static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version) | |
502 | { | |
503 | ||
504 | unsigned char param; | |
505 | /* | |
506 | * Get rid of bytes in the queue. | |
507 | */ | |
508 | ||
509 | i8042_flush(); | |
510 | ||
511 | /* | |
512 | * Internal loopback test - send three bytes, they should come back from the | |
513 | * mouse interface, the last should be version. Note that we negate mouseport | |
514 | * command responses for the i8042_check_aux() routine. | |
515 | */ | |
516 | ||
517 | param = 0xf0; | |
463a4f76 | 518 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xf0) |
1da177e4 LT |
519 | return -1; |
520 | param = mode ? 0x56 : 0xf6; | |
463a4f76 | 521 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6)) |
1da177e4 LT |
522 | return -1; |
523 | param = mode ? 0xa4 : 0xa5; | |
463a4f76 | 524 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5)) |
1da177e4 LT |
525 | return -1; |
526 | ||
527 | if (mux_version) | |
463a4f76 | 528 | *mux_version = param; |
1da177e4 LT |
529 | |
530 | return 0; | |
531 | } | |
532 | ||
533 | ||
534 | /* | |
535 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
536 | * the controller has been switched into Multiplexed mode | |
537 | */ | |
538 | ||
539 | static int i8042_enable_mux_ports(void) | |
540 | { | |
541 | unsigned char param; | |
542 | int i; | |
543 | /* | |
544 | * Disable all muxed ports by disabling AUX. | |
545 | */ | |
546 | ||
547 | i8042_ctr |= I8042_CTR_AUXDIS; | |
548 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
549 | ||
550 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
551 | printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); | |
552 | return -1; | |
553 | } | |
554 | ||
555 | /* | |
556 | * Enable all muxed ports. | |
557 | */ | |
558 | ||
0854e52d | 559 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { |
1da177e4 LT |
560 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); |
561 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
562 | } | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
567 | ||
568 | /* | |
569 | * i8042_check_mux() checks whether the controller supports the PS/2 Active | |
570 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
571 | * LCS/Telegraphics. | |
572 | */ | |
573 | ||
87fd6318 | 574 | static int __devinit i8042_check_mux(void) |
1da177e4 LT |
575 | { |
576 | unsigned char mux_version; | |
577 | ||
578 | if (i8042_set_mux_mode(1, &mux_version)) | |
579 | return -1; | |
580 | ||
581 | /* Workaround for interference with USB Legacy emulation */ | |
582 | /* that causes a v10.12 MUX to be found. */ | |
583 | if (mux_version == 0xAC) | |
584 | return -1; | |
585 | ||
586 | printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", | |
587 | (mux_version >> 4) & 0xf, mux_version & 0xf); | |
588 | ||
589 | if (i8042_enable_mux_ports()) | |
590 | return -1; | |
591 | ||
592 | i8042_mux_present = 1; | |
593 | return 0; | |
594 | } | |
595 | ||
596 | ||
597 | /* | |
598 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
599 | * the presence of an AUX interface. | |
600 | */ | |
601 | ||
87fd6318 | 602 | static int __devinit i8042_check_aux(void) |
1da177e4 LT |
603 | { |
604 | unsigned char param; | |
605 | static int i8042_check_aux_cookie; | |
606 | ||
607 | /* | |
608 | * Check if AUX irq is available. If it isn't, then there is no point | |
609 | * in trying to detect AUX presence. | |
610 | */ | |
611 | ||
612 | if (request_irq(i8042_ports[I8042_AUX_PORT_NO].irq, i8042_interrupt, | |
613 | SA_SHIRQ, "i8042", &i8042_check_aux_cookie)) | |
614 | return -1; | |
615 | free_irq(i8042_ports[I8042_AUX_PORT_NO].irq, &i8042_check_aux_cookie); | |
616 | ||
617 | /* | |
618 | * Get rid of bytes in the queue. | |
619 | */ | |
620 | ||
621 | i8042_flush(); | |
622 | ||
623 | /* | |
624 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
625 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
626 | * though it has an AUX port. | |
627 | */ | |
628 | ||
629 | param = 0x5a; | |
463a4f76 | 630 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0x5a) { |
1da177e4 LT |
631 | |
632 | /* | |
633 | * External connection test - filters out AT-soldered PS/2 i8042's | |
634 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
635 | * 0xfa - no error on some notebooks which ignore the spec | |
636 | * Because it's common for chipsets to return error on perfectly functioning | |
637 | * AUX ports, we test for this only when the LOOP command failed. | |
638 | */ | |
639 | ||
640 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) | |
463a4f76 | 641 | || (param && param != 0xfa && param != 0xff)) |
1da177e4 LT |
642 | return -1; |
643 | } | |
644 | ||
645 | /* | |
646 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
647 | */ | |
648 | ||
649 | if (i8042_command(¶m, I8042_CMD_AUX_DISABLE)) | |
650 | return -1; | |
651 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) { | |
652 | printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); | |
653 | printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); | |
654 | } | |
655 | ||
656 | if (i8042_command(¶m, I8042_CMD_AUX_ENABLE)) | |
657 | return -1; | |
658 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS)) | |
659 | return -1; | |
660 | ||
661 | /* | |
662 | * Disable the interface. | |
663 | */ | |
664 | ||
665 | i8042_ctr |= I8042_CTR_AUXDIS; | |
666 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
667 | ||
668 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
669 | return -1; | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | ||
675 | /* | |
676 | * i8042_port_register() marks the device as existing, | |
677 | * registers it, and reports to the user. | |
678 | */ | |
679 | ||
87fd6318 | 680 | static int __devinit i8042_port_register(struct i8042_port *port) |
1da177e4 LT |
681 | { |
682 | i8042_ctr &= ~port->disable; | |
683 | ||
684 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
685 | printk(KERN_WARNING "i8042.c: Can't write CTR while registering.\n"); | |
686 | kfree(port->serio); | |
687 | port->serio = NULL; | |
688 | i8042_ctr |= port->disable; | |
0854e52d | 689 | return -EIO; |
1da177e4 LT |
690 | } |
691 | ||
692 | printk(KERN_INFO "serio: i8042 %s port at %#lx,%#lx irq %d\n", | |
693 | port->name, | |
694 | (unsigned long) I8042_DATA_REG, | |
695 | (unsigned long) I8042_COMMAND_REG, | |
696 | port->irq); | |
697 | ||
698 | serio_register_port(port->serio); | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
703 | ||
704 | static void i8042_timer_func(unsigned long data) | |
705 | { | |
706 | i8042_interrupt(0, NULL, NULL); | |
707 | } | |
708 | ||
2673c836 VP |
709 | static int i8042_ctl_test(void) |
710 | { | |
711 | unsigned char param; | |
712 | ||
713 | if (!i8042_reset) | |
714 | return 0; | |
715 | ||
716 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
717 | printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); | |
718 | return -1; | |
719 | } | |
720 | ||
721 | if (param != I8042_RET_CTL_TEST) { | |
722 | printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", | |
723 | param, I8042_RET_CTL_TEST); | |
724 | return -1; | |
725 | } | |
726 | ||
727 | return 0; | |
728 | } | |
1da177e4 LT |
729 | |
730 | /* | |
731 | * i8042_controller init initializes the i8042 controller, and, | |
732 | * most importantly, sets it into non-xlated mode if that's | |
733 | * desired. | |
734 | */ | |
735 | ||
736 | static int i8042_controller_init(void) | |
737 | { | |
738 | unsigned long flags; | |
739 | ||
740 | /* | |
741 | * Test the i8042. We need to know if it thinks it's working correctly | |
742 | * before doing anything else. | |
743 | */ | |
744 | ||
745 | if (i8042_flush() == I8042_BUFFER_SIZE) { | |
746 | printk(KERN_ERR "i8042.c: No controller found.\n"); | |
747 | return -1; | |
748 | } | |
749 | ||
2673c836 VP |
750 | if (i8042_ctl_test()) |
751 | return -1; | |
1da177e4 LT |
752 | |
753 | /* | |
754 | * Save the CTR for restoral on unload / reboot. | |
755 | */ | |
756 | ||
757 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { | |
758 | printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); | |
759 | return -1; | |
760 | } | |
761 | ||
762 | i8042_initial_ctr = i8042_ctr; | |
763 | ||
764 | /* | |
765 | * Disable the keyboard interface and interrupt. | |
766 | */ | |
767 | ||
768 | i8042_ctr |= I8042_CTR_KBDDIS; | |
769 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
770 | ||
771 | /* | |
772 | * Handle keylock. | |
773 | */ | |
774 | ||
775 | spin_lock_irqsave(&i8042_lock, flags); | |
776 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
777 | if (i8042_unlock) | |
778 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
779 | else | |
780 | printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); | |
781 | } | |
782 | spin_unlock_irqrestore(&i8042_lock, flags); | |
783 | ||
784 | /* | |
785 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
786 | * bother enabling translating and be happy. | |
787 | */ | |
788 | ||
789 | if (~i8042_ctr & I8042_CTR_XLATE) | |
790 | i8042_direct = 1; | |
791 | ||
792 | /* | |
793 | * Set nontranslated mode for the kbd interface if requested by an option. | |
794 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
795 | * interface is. We don't do this by default, since it can confuse notebook | |
796 | * BIOSes. | |
797 | */ | |
798 | ||
799 | if (i8042_direct) | |
800 | i8042_ctr &= ~I8042_CTR_XLATE; | |
801 | ||
802 | /* | |
803 | * Write CTR back. | |
804 | */ | |
805 | ||
806 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
807 | printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); | |
808 | return -1; | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | ||
815 | /* | |
816 | * Reset the controller. | |
817 | */ | |
818 | static void i8042_controller_reset(void) | |
819 | { | |
1da177e4 LT |
820 | /* |
821 | * Reset the controller if requested. | |
822 | */ | |
823 | ||
2673c836 | 824 | i8042_ctl_test(); |
1da177e4 LT |
825 | |
826 | /* | |
827 | * Disable MUX mode if present. | |
828 | */ | |
829 | ||
830 | if (i8042_mux_present) | |
831 | i8042_set_mux_mode(0, NULL); | |
832 | ||
833 | /* | |
834 | * Restore the original control register setting. | |
835 | */ | |
836 | ||
837 | i8042_ctr = i8042_initial_ctr; | |
838 | ||
839 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
840 | printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); | |
841 | } | |
842 | ||
843 | ||
844 | /* | |
845 | * Here we try to reset everything back to a state in which the BIOS will be | |
846 | * able to talk to the hardware when rebooting. | |
847 | */ | |
848 | ||
849 | static void i8042_controller_cleanup(void) | |
850 | { | |
851 | int i; | |
852 | ||
853 | i8042_flush(); | |
854 | ||
855 | /* | |
856 | * Reset anything that is connected to the ports. | |
857 | */ | |
858 | ||
859 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
860 | if (i8042_ports[i].exists) | |
861 | serio_cleanup(i8042_ports[i].serio); | |
862 | ||
863 | i8042_controller_reset(); | |
864 | } | |
865 | ||
866 | ||
867 | /* | |
868 | * i8042_panic_blink() will flash the keyboard LEDs and is called when | |
869 | * kernel panics. Flashing LEDs is useful for users running X who may | |
870 | * not see the console and will help distingushing panics from "real" | |
871 | * lockups. | |
872 | * | |
873 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
874 | * waiting for KBC to free up even if KBD interrupt is off | |
875 | */ | |
876 | ||
877 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
878 | ||
879 | static long i8042_panic_blink(long count) | |
880 | { | |
881 | long delay = 0; | |
882 | static long last_blink; | |
883 | static char led; | |
884 | ||
885 | /* | |
886 | * We expect frequency to be about 1/2s. KDB uses about 1s. | |
887 | * Make sure they are different. | |
888 | */ | |
889 | if (!i8042_blink_frequency) | |
890 | return 0; | |
891 | if (count - last_blink < i8042_blink_frequency) | |
892 | return 0; | |
893 | ||
894 | led ^= 0x01 | 0x04; | |
895 | while (i8042_read_status() & I8042_STR_IBF) | |
896 | DELAY; | |
897 | i8042_write_data(0xed); /* set leds */ | |
898 | DELAY; | |
899 | while (i8042_read_status() & I8042_STR_IBF) | |
900 | DELAY; | |
901 | DELAY; | |
902 | i8042_write_data(led); | |
903 | DELAY; | |
904 | last_blink = count; | |
905 | return delay; | |
906 | } | |
907 | ||
908 | #undef DELAY | |
909 | ||
910 | /* | |
911 | * Here we try to restore the original BIOS settings | |
912 | */ | |
913 | ||
3ae5eaec | 914 | static int i8042_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 915 | { |
9480e307 RK |
916 | del_timer_sync(&i8042_timer); |
917 | i8042_controller_reset(); | |
1da177e4 LT |
918 | |
919 | return 0; | |
920 | } | |
921 | ||
922 | ||
923 | /* | |
924 | * Here we try to reset everything back to a state in which suspended | |
925 | */ | |
926 | ||
3ae5eaec | 927 | static int i8042_resume(struct platform_device *dev) |
1da177e4 LT |
928 | { |
929 | int i; | |
930 | ||
2673c836 VP |
931 | if (i8042_ctl_test()) |
932 | return -1; | |
933 | ||
934 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
935 | printk(KERN_ERR "i8042: Can't write CTR\n"); | |
1da177e4 LT |
936 | return -1; |
937 | } | |
938 | ||
939 | if (i8042_mux_present) | |
940 | if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports()) | |
941 | printk(KERN_WARNING "i8042: failed to resume active multiplexor, mouse won't work.\n"); | |
942 | ||
943 | /* | |
944 | * Activate all ports. | |
945 | */ | |
946 | ||
947 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
948 | i8042_activate_port(&i8042_ports[i]); | |
949 | ||
950 | /* | |
951 | * Restart timer (for polling "stuck" data) | |
952 | */ | |
953 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
954 | ||
955 | panic_blink = i8042_panic_blink; | |
956 | ||
957 | return 0; | |
1da177e4 LT |
958 | } |
959 | ||
960 | /* | |
961 | * We need to reset the 8042 back to original mode on system shutdown, | |
962 | * because otherwise BIOSes will be confused. | |
963 | */ | |
964 | ||
3ae5eaec | 965 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 LT |
966 | { |
967 | i8042_controller_cleanup(); | |
968 | } | |
969 | ||
87fd6318 | 970 | static int __devinit i8042_create_kbd_port(void) |
1da177e4 LT |
971 | { |
972 | struct serio *serio; | |
973 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
974 | ||
d39969de | 975 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
976 | if (!serio) |
977 | return -ENOMEM; | |
978 | ||
979 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
980 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
981 | serio->open = i8042_open; | |
982 | serio->close = i8042_close; | |
983 | serio->start = i8042_start; | |
984 | serio->stop = i8042_stop; | |
985 | serio->port_data = port; | |
986 | serio->dev.parent = &i8042_platform_device->dev; | |
987 | strlcpy(serio->name, "i8042 Kbd Port", sizeof(serio->name)); | |
988 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); | |
989 | ||
990 | port->serio = serio; | |
991 | ||
992 | return i8042_port_register(port); | |
1da177e4 LT |
993 | } |
994 | ||
87fd6318 | 995 | static int __devinit i8042_create_aux_port(void) |
1da177e4 LT |
996 | { |
997 | struct serio *serio; | |
998 | struct i8042_port *port = &i8042_ports[I8042_AUX_PORT_NO]; | |
999 | ||
d39969de | 1000 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1001 | if (!serio) |
1002 | return -ENOMEM; | |
1003 | ||
1004 | serio->id.type = SERIO_8042; | |
1005 | serio->write = i8042_aux_write; | |
1006 | serio->open = i8042_open; | |
1007 | serio->close = i8042_close; | |
1008 | serio->start = i8042_start; | |
1009 | serio->stop = i8042_stop; | |
1010 | serio->port_data = port; | |
1011 | serio->dev.parent = &i8042_platform_device->dev; | |
1012 | strlcpy(serio->name, "i8042 Aux Port", sizeof(serio->name)); | |
1013 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
1014 | ||
1015 | port->serio = serio; | |
1016 | ||
1017 | return i8042_port_register(port); | |
1da177e4 LT |
1018 | } |
1019 | ||
87fd6318 | 1020 | static int __devinit i8042_create_mux_port(int index) |
1da177e4 LT |
1021 | { |
1022 | struct serio *serio; | |
1023 | struct i8042_port *port = &i8042_ports[I8042_MUX_PORT_NO + index]; | |
1024 | ||
d39969de | 1025 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1026 | if (!serio) |
1027 | return -ENOMEM; | |
1028 | ||
1029 | serio->id.type = SERIO_8042; | |
1030 | serio->write = i8042_aux_write; | |
1031 | serio->open = i8042_open; | |
1032 | serio->close = i8042_close; | |
1033 | serio->start = i8042_start; | |
1034 | serio->stop = i8042_stop; | |
1035 | serio->port_data = port; | |
1036 | serio->dev.parent = &i8042_platform_device->dev; | |
1037 | snprintf(serio->name, sizeof(serio->name), "i8042 Aux-%d Port", index); | |
1038 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, index + 1); | |
1039 | ||
1040 | *port = i8042_ports[I8042_AUX_PORT_NO]; | |
1041 | port->exists = 0; | |
1042 | snprintf(port->name, sizeof(port->name), "AUX%d", index); | |
1043 | port->mux = index; | |
1044 | port->serio = serio; | |
1045 | ||
1046 | return i8042_port_register(port); | |
1da177e4 LT |
1047 | } |
1048 | ||
87fd6318 | 1049 | static int __devinit i8042_probe(struct platform_device *dev) |
1da177e4 | 1050 | { |
945ef0d4 | 1051 | int i, have_ports = 0; |
1da177e4 LT |
1052 | int err; |
1053 | ||
1da177e4 LT |
1054 | init_timer(&i8042_timer); |
1055 | i8042_timer.function = i8042_timer_func; | |
1056 | ||
87fd6318 DT |
1057 | if (i8042_controller_init()) |
1058 | return -ENODEV; | |
1da177e4 LT |
1059 | |
1060 | if (!i8042_noaux && !i8042_check_aux()) { | |
0854e52d DT |
1061 | if (!i8042_nomux && !i8042_check_mux()) { |
1062 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1063 | err = i8042_create_mux_port(i); | |
1064 | if (err) | |
1065 | goto err_unregister_ports; | |
1066 | } | |
1067 | } else { | |
1068 | err = i8042_create_aux_port(); | |
1069 | if (err) | |
1070 | goto err_unregister_ports; | |
1071 | } | |
945ef0d4 | 1072 | have_ports = 1; |
1da177e4 LT |
1073 | } |
1074 | ||
945ef0d4 DT |
1075 | if (!i8042_nokbd) { |
1076 | err = i8042_create_kbd_port(); | |
1077 | if (err) | |
1078 | goto err_unregister_ports; | |
1079 | have_ports = 1; | |
1080 | } | |
1081 | ||
1082 | if (!have_ports) { | |
1083 | err = -ENODEV; | |
87fd6318 | 1084 | goto err_controller_cleanup; |
945ef0d4 | 1085 | } |
1da177e4 LT |
1086 | |
1087 | mod_timer(&i8042_timer, jiffies + I8042_POLL_PERIOD); | |
1da177e4 | 1088 | return 0; |
0854e52d DT |
1089 | |
1090 | err_unregister_ports: | |
1091 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1092 | if (i8042_ports[i].serio) | |
1093 | serio_unregister_port(i8042_ports[i].serio); | |
0854e52d DT |
1094 | err_controller_cleanup: |
1095 | i8042_controller_cleanup(); | |
0854e52d DT |
1096 | |
1097 | return err; | |
1da177e4 LT |
1098 | } |
1099 | ||
87fd6318 | 1100 | static int __devexit i8042_remove(struct platform_device *dev) |
1da177e4 LT |
1101 | { |
1102 | int i; | |
1103 | ||
1104 | i8042_controller_cleanup(); | |
1105 | ||
1106 | for (i = 0; i < I8042_NUM_PORTS; i++) | |
1107 | if (i8042_ports[i].exists) | |
1108 | serio_unregister_port(i8042_ports[i].serio); | |
1109 | ||
1110 | del_timer_sync(&i8042_timer); | |
1111 | ||
87fd6318 DT |
1112 | return 0; |
1113 | } | |
1114 | ||
1115 | static struct platform_driver i8042_driver = { | |
1116 | .driver = { | |
1117 | .name = "i8042", | |
1118 | .owner = THIS_MODULE, | |
1119 | }, | |
1120 | .probe = i8042_probe, | |
1121 | .remove = __devexit_p(i8042_remove), | |
1122 | .suspend = i8042_suspend, | |
1123 | .resume = i8042_resume, | |
1124 | .shutdown = i8042_shutdown, | |
1125 | }; | |
1126 | ||
1127 | static int __init i8042_init(void) | |
1128 | { | |
1129 | int err; | |
1130 | ||
1131 | dbg_init(); | |
1132 | ||
1133 | err = i8042_platform_init(); | |
1134 | if (err) | |
1135 | return err; | |
1136 | ||
1137 | i8042_ports[I8042_AUX_PORT_NO].irq = I8042_AUX_IRQ; | |
1138 | i8042_ports[I8042_KBD_PORT_NO].irq = I8042_KBD_IRQ; | |
1139 | ||
1140 | err = platform_driver_register(&i8042_driver); | |
1141 | if (err) | |
1142 | goto err_platform_exit; | |
1143 | ||
1144 | i8042_platform_device = platform_device_alloc("i8042", -1); | |
1145 | if (!i8042_platform_device) { | |
1146 | err = -ENOMEM; | |
1147 | goto err_unregister_driver; | |
1148 | } | |
1149 | ||
1150 | err = platform_device_add(i8042_platform_device); | |
1151 | if (err) | |
1152 | goto err_free_device; | |
1153 | ||
1154 | return 0; | |
1155 | ||
1156 | err_free_device: | |
1157 | platform_device_put(i8042_platform_device); | |
1158 | err_unregister_driver: | |
1159 | platform_driver_unregister(&i8042_driver); | |
1160 | err_platform_exit: | |
1161 | i8042_platform_exit(); | |
1162 | ||
1163 | return err; | |
1164 | } | |
1165 | ||
1166 | static void __exit i8042_exit(void) | |
1167 | { | |
1da177e4 | 1168 | platform_device_unregister(i8042_platform_device); |
3ae5eaec | 1169 | platform_driver_unregister(&i8042_driver); |
1da177e4 LT |
1170 | |
1171 | i8042_platform_exit(); | |
1172 | ||
1173 | panic_blink = NULL; | |
1174 | } | |
1175 | ||
1176 | module_init(i8042_init); | |
1177 | module_exit(i8042_exit); |