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CommitLineData
1da177e4
LT
1/*
2 * i8042 keyboard and mouse controller driver for Linux
3 *
4 * Copyright (c) 1999-2004 Vojtech Pavlik
5 */
6
7/*
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
1da177e4
LT
18#include <linux/init.h>
19#include <linux/serio.h>
20#include <linux/err.h>
21#include <linux/rcupdate.h>
d052d1be 22#include <linux/platform_device.h>
1da177e4
LT
23
24#include <asm/io.h>
25
26MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
27MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
28MODULE_LICENSE("GPL");
29
945ef0d4
DT
30static unsigned int i8042_nokbd;
31module_param_named(nokbd, i8042_nokbd, bool, 0);
32MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
33
1da177e4
LT
34static unsigned int i8042_noaux;
35module_param_named(noaux, i8042_noaux, bool, 0);
36MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
37
38static unsigned int i8042_nomux;
39module_param_named(nomux, i8042_nomux, bool, 0);
40MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present.");
41
42static unsigned int i8042_unlock;
43module_param_named(unlock, i8042_unlock, bool, 0);
44MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
45
46static unsigned int i8042_reset;
47module_param_named(reset, i8042_reset, bool, 0);
48MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
49
50static unsigned int i8042_direct;
51module_param_named(direct, i8042_direct, bool, 0);
52MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
53
54static unsigned int i8042_dumbkbd;
55module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
56MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
57
58static unsigned int i8042_noloop;
59module_param_named(noloop, i8042_noloop, bool, 0);
60MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
61
62static unsigned int i8042_blink_frequency = 500;
63module_param_named(panicblink, i8042_blink_frequency, uint, 0600);
64MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics");
65
66#ifdef CONFIG_PNP
67static int i8042_nopnp;
68module_param_named(nopnp, i8042_nopnp, bool, 0);
69MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
70#endif
71
72#define DEBUG
73#ifdef DEBUG
74static int i8042_debug;
75module_param_named(debug, i8042_debug, bool, 0600);
76MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
77#endif
78
79__obsolete_setup("i8042_noaux");
80__obsolete_setup("i8042_nomux");
81__obsolete_setup("i8042_unlock");
82__obsolete_setup("i8042_reset");
83__obsolete_setup("i8042_direct");
84__obsolete_setup("i8042_dumbkbd");
85
86#include "i8042.h"
87
88static DEFINE_SPINLOCK(i8042_lock);
89
90struct i8042_port {
91 struct serio *serio;
92 int irq;
1da177e4
LT
93 unsigned char exists;
94 signed char mux;
1da177e4
LT
95};
96
97#define I8042_KBD_PORT_NO 0
98#define I8042_AUX_PORT_NO 1
99#define I8042_MUX_PORT_NO 2
100#define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
de9ce703
DT
101
102static struct i8042_port i8042_ports[I8042_NUM_PORTS];
1da177e4
LT
103
104static unsigned char i8042_initial_ctr;
105static unsigned char i8042_ctr;
1da177e4 106static unsigned char i8042_mux_present;
de9ce703
DT
107static unsigned char i8042_kbd_irq_registered;
108static unsigned char i8042_aux_irq_registered;
817e6ba3 109static unsigned char i8042_suppress_kbd_ack;
1da177e4
LT
110static struct platform_device *i8042_platform_device;
111
7d12e780 112static irqreturn_t i8042_interrupt(int irq, void *dev_id);
1da177e4
LT
113
114/*
115 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
116 * be ready for reading values from it / writing values to it.
117 * Called always with i8042_lock held.
118 */
119
120static int i8042_wait_read(void)
121{
122 int i = 0;
de9ce703 123
1da177e4
LT
124 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
125 udelay(50);
126 i++;
127 }
128 return -(i == I8042_CTL_TIMEOUT);
129}
130
131static int i8042_wait_write(void)
132{
133 int i = 0;
de9ce703 134
1da177e4
LT
135 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
136 udelay(50);
137 i++;
138 }
139 return -(i == I8042_CTL_TIMEOUT);
140}
141
142/*
143 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
144 * of the i8042 down the toilet.
145 */
146
147static int i8042_flush(void)
148{
149 unsigned long flags;
150 unsigned char data, str;
151 int i = 0;
152
153 spin_lock_irqsave(&i8042_lock, flags);
154
155 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
156 udelay(50);
157 data = i8042_read_data();
158 i++;
159 dbg("%02x <- i8042 (flush, %s)", data,
160 str & I8042_STR_AUXDATA ? "aux" : "kbd");
161 }
162
163 spin_unlock_irqrestore(&i8042_lock, flags);
164
165 return i;
166}
167
168/*
169 * i8042_command() executes a command on the i8042. It also sends the input
170 * parameter(s) of the commands to it, and receives the output value(s). The
171 * parameters are to be stored in the param array, and the output is placed
172 * into the same array. The number of the parameters and output values is
173 * encoded in bits 8-11 of the command number.
174 */
175
de9ce703 176static int __i8042_command(unsigned char *param, int command)
1da177e4 177{
de9ce703 178 int i, error;
1da177e4
LT
179
180 if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
181 return -1;
182
de9ce703
DT
183 error = i8042_wait_write();
184 if (error)
185 return error;
463a4f76
DT
186
187 dbg("%02x -> i8042 (command)", command & 0xff);
188 i8042_write_command(command & 0xff);
189
190 for (i = 0; i < ((command >> 12) & 0xf); i++) {
de9ce703
DT
191 error = i8042_wait_write();
192 if (error)
193 return error;
463a4f76
DT
194 dbg("%02x -> i8042 (parameter)", param[i]);
195 i8042_write_data(param[i]);
1da177e4
LT
196 }
197
463a4f76 198 for (i = 0; i < ((command >> 8) & 0xf); i++) {
de9ce703
DT
199 error = i8042_wait_read();
200 if (error) {
201 dbg(" -- i8042 (timeout)");
202 return error;
203 }
1da177e4 204
463a4f76
DT
205 if (command == I8042_CMD_AUX_LOOP &&
206 !(i8042_read_status() & I8042_STR_AUXDATA)) {
de9ce703
DT
207 dbg(" -- i8042 (auxerr)");
208 return -1;
1da177e4
LT
209 }
210
463a4f76
DT
211 param[i] = i8042_read_data();
212 dbg("%02x <- i8042 (return)", param[i]);
213 }
1da177e4 214
de9ce703
DT
215 return 0;
216}
1da177e4 217
de9ce703
DT
218static int i8042_command(unsigned char *param, int command)
219{
220 unsigned long flags;
221 int retval;
222
223 spin_lock_irqsave(&i8042_lock, flags);
224 retval = __i8042_command(param, command);
463a4f76 225 spin_unlock_irqrestore(&i8042_lock, flags);
de9ce703 226
1da177e4
LT
227 return retval;
228}
229
230/*
231 * i8042_kbd_write() sends a byte out through the keyboard interface.
232 */
233
234static int i8042_kbd_write(struct serio *port, unsigned char c)
235{
236 unsigned long flags;
237 int retval = 0;
238
239 spin_lock_irqsave(&i8042_lock, flags);
240
de9ce703 241 if (!(retval = i8042_wait_write())) {
1da177e4
LT
242 dbg("%02x -> i8042 (kbd-data)", c);
243 i8042_write_data(c);
244 }
245
246 spin_unlock_irqrestore(&i8042_lock, flags);
247
248 return retval;
249}
250
251/*
252 * i8042_aux_write() sends a byte out through the aux interface.
253 */
254
255static int i8042_aux_write(struct serio *serio, unsigned char c)
256{
257 struct i8042_port *port = serio->port_data;
1da177e4 258
f4e3c711
DT
259 return i8042_command(&c, port->mux == -1 ?
260 I8042_CMD_AUX_SEND :
261 I8042_CMD_MUX_SEND + port->mux);
1da177e4
LT
262}
263
1da177e4
LT
264/*
265 * i8042_start() is called by serio core when port is about to finish
266 * registering. It will mark port as existing so i8042_interrupt can
267 * start sending data through it.
268 */
269static int i8042_start(struct serio *serio)
270{
271 struct i8042_port *port = serio->port_data;
272
273 port->exists = 1;
274 mb();
275 return 0;
276}
277
278/*
279 * i8042_stop() marks serio port as non-existing so i8042_interrupt
280 * will not try to send data to the port that is about to go away.
281 * The function is called by serio core as part of unregister procedure.
282 */
283static void i8042_stop(struct serio *serio)
284{
285 struct i8042_port *port = serio->port_data;
286
287 port->exists = 0;
b2b18660 288 synchronize_sched();
1da177e4
LT
289 port->serio = NULL;
290}
291
292/*
293 * i8042_interrupt() is the most important function in this driver -
294 * it handles the interrupts from the i8042, and sends incoming bytes
295 * to the upper layers.
296 */
297
7d12e780 298static irqreturn_t i8042_interrupt(int irq, void *dev_id)
1da177e4
LT
299{
300 struct i8042_port *port;
301 unsigned long flags;
302 unsigned char str, data;
303 unsigned int dfl;
304 unsigned int port_no;
817e6ba3 305 int ret = 1;
1da177e4 306
1da177e4
LT
307 spin_lock_irqsave(&i8042_lock, flags);
308 str = i8042_read_status();
309 if (unlikely(~str & I8042_STR_OBF)) {
310 spin_unlock_irqrestore(&i8042_lock, flags);
311 if (irq) dbg("Interrupt %d, without any data", irq);
312 ret = 0;
313 goto out;
314 }
315 data = i8042_read_data();
316 spin_unlock_irqrestore(&i8042_lock, flags);
317
318 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
319 static unsigned long last_transmit;
320 static unsigned char last_str;
321
322 dfl = 0;
323 if (str & I8042_STR_MUXERR) {
324 dbg("MUX error, status is %02x, data is %02x", str, data);
1da177e4
LT
325/*
326 * When MUXERR condition is signalled the data register can only contain
327 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
a216a4b6
DT
328 * it is not always the case. Some KBCs also report 0xfc when there is
329 * nothing connected to the port while others sometimes get confused which
330 * port the data came from and signal error leaving the data intact. They
331 * _do not_ revert to legacy mode (actually I've never seen KBC reverting
332 * to legacy mode yet, when we see one we'll add proper handling).
333 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
334 * rest assume that the data came from the same serio last byte
1da177e4
LT
335 * was transmitted (if transmission happened not too long ago).
336 */
a216a4b6
DT
337
338 switch (data) {
339 default:
1da177e4
LT
340 if (time_before(jiffies, last_transmit + HZ/10)) {
341 str = last_str;
342 break;
343 }
344 /* fall through - report timeout */
a216a4b6 345 case 0xfc:
1da177e4
LT
346 case 0xfd:
347 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
348 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
349 }
350 }
351
352 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
353 last_str = str;
354 last_transmit = jiffies;
355 } else {
356
357 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
358 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
359
360 port_no = (str & I8042_STR_AUXDATA) ?
361 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
362 }
363
364 port = &i8042_ports[port_no];
365
de9ce703
DT
366 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)",
367 data, port_no, irq,
1da177e4
LT
368 dfl & SERIO_PARITY ? ", bad parity" : "",
369 dfl & SERIO_TIMEOUT ? ", timeout" : "");
370
817e6ba3
DT
371 if (unlikely(i8042_suppress_kbd_ack))
372 if (port_no == I8042_KBD_PORT_NO &&
373 (data == 0xfa || data == 0xfe)) {
19f3c3e3 374 i8042_suppress_kbd_ack--;
817e6ba3
DT
375 goto out;
376 }
377
1da177e4 378 if (likely(port->exists))
7d12e780 379 serio_interrupt(port->serio, data, dfl);
1da177e4 380
0854e52d 381 out:
1da177e4
LT
382 return IRQ_RETVAL(ret);
383}
384
de9ce703
DT
385/*
386 * i8042_enable_kbd_port enables keybaord port on chip
387 */
388
389static int i8042_enable_kbd_port(void)
390{
391 i8042_ctr &= ~I8042_CTR_KBDDIS;
392 i8042_ctr |= I8042_CTR_KBDINT;
393
394 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
395 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n");
396 return -EIO;
397 }
398
399 return 0;
400}
401
402/*
403 * i8042_enable_aux_port enables AUX (mouse) port on chip
404 */
405
406static int i8042_enable_aux_port(void)
407{
408 i8042_ctr &= ~I8042_CTR_AUXDIS;
409 i8042_ctr |= I8042_CTR_AUXINT;
410
411 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
412 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n");
413 return -EIO;
414 }
415
416 return 0;
417}
418
419/*
420 * i8042_enable_mux_ports enables 4 individual AUX ports after
421 * the controller has been switched into Multiplexed mode
422 */
423
424static int i8042_enable_mux_ports(void)
425{
426 unsigned char param;
427 int i;
428
429 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
430 i8042_command(&param, I8042_CMD_MUX_PFX + i);
431 i8042_command(&param, I8042_CMD_AUX_ENABLE);
432 }
433
434 return i8042_enable_aux_port();
435}
436
1da177e4
LT
437/*
438 * i8042_set_mux_mode checks whether the controller has an active
439 * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode.
440 */
441
442static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version)
443{
444
445 unsigned char param;
446/*
447 * Get rid of bytes in the queue.
448 */
449
450 i8042_flush();
451
452/*
453 * Internal loopback test - send three bytes, they should come back from the
de9ce703 454 * mouse interface, the last should be version.
1da177e4
LT
455 */
456
457 param = 0xf0;
463a4f76 458 if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0xf0)
1da177e4
LT
459 return -1;
460 param = mode ? 0x56 : 0xf6;
463a4f76 461 if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6))
1da177e4
LT
462 return -1;
463 param = mode ? 0xa4 : 0xa5;
463a4f76 464 if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5))
1da177e4
LT
465 return -1;
466
467 if (mux_version)
463a4f76 468 *mux_version = param;
1da177e4
LT
469
470 return 0;
471}
472
1da177e4 473/*
de9ce703
DT
474 * i8042_check_mux() checks whether the controller supports the PS/2 Active
475 * Multiplexing specification by Synaptics, Phoenix, Insyde and
476 * LCS/Telegraphics.
1da177e4
LT
477 */
478
de9ce703 479static int __devinit i8042_check_mux(void)
1da177e4 480{
de9ce703
DT
481 unsigned char mux_version;
482
483 if (i8042_set_mux_mode(1, &mux_version))
484 return -1;
485
1da177e4 486/*
de9ce703
DT
487 * Workaround for interference with USB Legacy emulation
488 * that causes a v10.12 MUX to be found.
1da177e4 489 */
de9ce703
DT
490 if (mux_version == 0xAC)
491 return -1;
492
493 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
494 (mux_version >> 4) & 0xf, mux_version & 0xf);
1da177e4 495
de9ce703
DT
496/*
497 * Disable all muxed ports by disabling AUX.
498 */
1da177e4
LT
499 i8042_ctr |= I8042_CTR_AUXDIS;
500 i8042_ctr &= ~I8042_CTR_AUXINT;
501
502 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
503 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
de9ce703 504 return -EIO;
1da177e4
LT
505 }
506
de9ce703 507 i8042_mux_present = 1;
1da177e4
LT
508
509 return 0;
510}
511
1da177e4 512/*
de9ce703 513 * The following is used to test AUX IRQ delivery.
1da177e4 514 */
de9ce703
DT
515static struct completion i8042_aux_irq_delivered __devinitdata;
516static int i8042_irq_being_tested __devinitdata;
1da177e4 517
7d12e780 518static irqreturn_t __devinit i8042_aux_test_irq(int irq, void *dev_id)
1da177e4 519{
de9ce703
DT
520 unsigned long flags;
521 unsigned char str, data;
1da177e4 522
de9ce703
DT
523 spin_lock_irqsave(&i8042_lock, flags);
524 str = i8042_read_status();
525 if (str & I8042_STR_OBF) {
526 data = i8042_read_data();
527 if (i8042_irq_being_tested &&
528 data == 0xa5 && (str & I8042_STR_AUXDATA))
529 complete(&i8042_aux_irq_delivered);
530 }
531 spin_unlock_irqrestore(&i8042_lock, flags);
1da177e4 532
de9ce703 533 return IRQ_HANDLED;
1da177e4
LT
534}
535
536
537/*
538 * i8042_check_aux() applies as much paranoia as it can at detecting
539 * the presence of an AUX interface.
540 */
541
87fd6318 542static int __devinit i8042_check_aux(void)
1da177e4 543{
de9ce703
DT
544 int retval = -1;
545 int irq_registered = 0;
1e4865f8 546 int aux_loop_broken = 0;
de9ce703 547 unsigned long flags;
1da177e4 548 unsigned char param;
1da177e4
LT
549
550/*
551 * Get rid of bytes in the queue.
552 */
553
554 i8042_flush();
555
556/*
557 * Internal loopback test - filters out AT-type i8042's. Unfortunately
558 * SiS screwed up and their 5597 doesn't support the LOOP command even
559 * though it has an AUX port.
560 */
561
562 param = 0x5a;
463a4f76 563 if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0x5a) {
1da177e4
LT
564
565/*
566 * External connection test - filters out AT-soldered PS/2 i8042's
567 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
568 * 0xfa - no error on some notebooks which ignore the spec
569 * Because it's common for chipsets to return error on perfectly functioning
570 * AUX ports, we test for this only when the LOOP command failed.
571 */
572
de9ce703
DT
573 if (i8042_command(&param, I8042_CMD_AUX_TEST) ||
574 (param && param != 0xfa && param != 0xff))
575 return -1;
1e4865f8
DT
576
577 aux_loop_broken = 1;
1da177e4
LT
578 }
579
580/*
581 * Bit assignment test - filters out PS/2 i8042's in AT mode
582 */
583
584 if (i8042_command(&param, I8042_CMD_AUX_DISABLE))
585 return -1;
586 if (i8042_command(&param, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS)) {
587 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
588 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
589 }
590
591 if (i8042_command(&param, I8042_CMD_AUX_ENABLE))
592 return -1;
593 if (i8042_command(&param, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS))
594 return -1;
595
596/*
de9ce703
DT
597 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
598 * used it for a PCI card or somethig else.
1da177e4
LT
599 */
600
1e4865f8 601 if (i8042_noloop || aux_loop_broken) {
de9ce703
DT
602/*
603 * Without LOOP command we can't test AUX IRQ delivery. Assume the port
604 * is working and hope we are right.
605 */
606 retval = 0;
607 goto out;
608 }
1da177e4 609
de9ce703
DT
610 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
611 "i8042", i8042_platform_device))
612 goto out;
1da177e4 613
de9ce703
DT
614 irq_registered = 1;
615
616 if (i8042_enable_aux_port())
617 goto out;
618
619 spin_lock_irqsave(&i8042_lock, flags);
1da177e4 620
de9ce703
DT
621 init_completion(&i8042_aux_irq_delivered);
622 i8042_irq_being_tested = 1;
623
624 param = 0xa5;
625 retval = __i8042_command(&param, I8042_CMD_AUX_LOOP & 0xf0ff);
626
627 spin_unlock_irqrestore(&i8042_lock, flags);
628
629 if (retval)
630 goto out;
1da177e4 631
de9ce703
DT
632 if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
633 msecs_to_jiffies(250)) == 0) {
1da177e4 634/*
de9ce703
DT
635 * AUX IRQ was never delivered so we need to flush the controller to
636 * get rid of the byte we put there; otherwise keyboard may not work.
1da177e4 637 */
de9ce703
DT
638 i8042_flush();
639 retval = -1;
640 }
1da177e4 641
de9ce703 642 out:
1da177e4 643
de9ce703
DT
644/*
645 * Disable the interface.
646 */
1da177e4 647
de9ce703
DT
648 i8042_ctr |= I8042_CTR_AUXDIS;
649 i8042_ctr &= ~I8042_CTR_AUXINT;
1da177e4 650
de9ce703
DT
651 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
652 retval = -1;
1da177e4 653
de9ce703
DT
654 if (irq_registered)
655 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1da177e4 656
de9ce703
DT
657 return retval;
658}
1da177e4 659
de9ce703 660static int i8042_controller_check(void)
1da177e4 661{
de9ce703
DT
662 if (i8042_flush() == I8042_BUFFER_SIZE) {
663 printk(KERN_ERR "i8042.c: No controller found.\n");
664 return -ENODEV;
665 }
666
667 return 0;
1da177e4
LT
668}
669
de9ce703 670static int i8042_controller_selftest(void)
2673c836
VP
671{
672 unsigned char param;
673
674 if (!i8042_reset)
675 return 0;
676
677 if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
678 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
de9ce703 679 return -ENODEV;
2673c836
VP
680 }
681
682 if (param != I8042_RET_CTL_TEST) {
683 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
684 param, I8042_RET_CTL_TEST);
de9ce703 685 return -EIO;
2673c836
VP
686 }
687
688 return 0;
689}
1da177e4
LT
690
691/*
692 * i8042_controller init initializes the i8042 controller, and,
693 * most importantly, sets it into non-xlated mode if that's
694 * desired.
695 */
696
697static int i8042_controller_init(void)
698{
699 unsigned long flags;
700
1da177e4
LT
701/*
702 * Save the CTR for restoral on unload / reboot.
703 */
704
705 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
706 printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n");
de9ce703 707 return -EIO;
1da177e4
LT
708 }
709
710 i8042_initial_ctr = i8042_ctr;
711
712/*
713 * Disable the keyboard interface and interrupt.
714 */
715
716 i8042_ctr |= I8042_CTR_KBDDIS;
717 i8042_ctr &= ~I8042_CTR_KBDINT;
718
719/*
720 * Handle keylock.
721 */
722
723 spin_lock_irqsave(&i8042_lock, flags);
724 if (~i8042_read_status() & I8042_STR_KEYLOCK) {
725 if (i8042_unlock)
726 i8042_ctr |= I8042_CTR_IGNKEYLOCK;
82dd9eff 727 else
1da177e4
LT
728 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
729 }
730 spin_unlock_irqrestore(&i8042_lock, flags);
731
732/*
733 * If the chip is configured into nontranslated mode by the BIOS, don't
734 * bother enabling translating and be happy.
735 */
736
737 if (~i8042_ctr & I8042_CTR_XLATE)
738 i8042_direct = 1;
739
740/*
741 * Set nontranslated mode for the kbd interface if requested by an option.
742 * After this the kbd interface becomes a simple serial in/out, like the aux
743 * interface is. We don't do this by default, since it can confuse notebook
744 * BIOSes.
745 */
746
747 if (i8042_direct)
748 i8042_ctr &= ~I8042_CTR_XLATE;
749
750/*
751 * Write CTR back.
752 */
753
754 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
755 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
de9ce703 756 return -EIO;
1da177e4
LT
757 }
758
759 return 0;
760}
761
762
763/*
de9ce703 764 * Reset the controller and reset CRT to the original value set by BIOS.
1da177e4 765 */
de9ce703 766
1da177e4
LT
767static void i8042_controller_reset(void)
768{
de9ce703 769 i8042_flush();
1da177e4
LT
770
771/*
772 * Disable MUX mode if present.
773 */
774
775 if (i8042_mux_present)
776 i8042_set_mux_mode(0, NULL);
777
778/*
de9ce703 779 * Reset the controller if requested.
1da177e4
LT
780 */
781
de9ce703 782 i8042_controller_selftest();
1da177e4 783
de9ce703
DT
784/*
785 * Restore the original control register setting.
786 */
787
788 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
1da177e4
LT
789 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
790}
791
792
1da177e4
LT
793/*
794 * i8042_panic_blink() will flash the keyboard LEDs and is called when
795 * kernel panics. Flashing LEDs is useful for users running X who may
796 * not see the console and will help distingushing panics from "real"
797 * lockups.
798 *
799 * Note that DELAY has a limit of 10ms so we will not get stuck here
800 * waiting for KBC to free up even if KBD interrupt is off
801 */
802
803#define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
804
805static long i8042_panic_blink(long count)
806{
807 long delay = 0;
808 static long last_blink;
809 static char led;
810
811 /*
812 * We expect frequency to be about 1/2s. KDB uses about 1s.
813 * Make sure they are different.
814 */
815 if (!i8042_blink_frequency)
816 return 0;
817 if (count - last_blink < i8042_blink_frequency)
818 return 0;
819
820 led ^= 0x01 | 0x04;
821 while (i8042_read_status() & I8042_STR_IBF)
822 DELAY;
19f3c3e3
DT
823 dbg("%02x -> i8042 (panic blink)", 0xed);
824 i8042_suppress_kbd_ack = 2;
1da177e4
LT
825 i8042_write_data(0xed); /* set leds */
826 DELAY;
827 while (i8042_read_status() & I8042_STR_IBF)
828 DELAY;
829 DELAY;
19f3c3e3 830 dbg("%02x -> i8042 (panic blink)", led);
1da177e4
LT
831 i8042_write_data(led);
832 DELAY;
833 last_blink = count;
834 return delay;
835}
836
837#undef DELAY
838
82dd9eff 839#ifdef CONFIG_PM
1da177e4 840/*
82dd9eff
DT
841 * Here we try to restore the original BIOS settings. We only want to
842 * do that once, when we really suspend, not when we taking memory
843 * snapshot for swsusp (in this case we'll perform required cleanup
844 * as part of shutdown process).
1da177e4
LT
845 */
846
3ae5eaec 847static int i8042_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 848{
82dd9eff
DT
849 if (dev->dev.power.power_state.event != state.event) {
850 if (state.event == PM_EVENT_SUSPEND)
851 i8042_controller_reset();
852
853 dev->dev.power.power_state = state;
854 }
1da177e4
LT
855
856 return 0;
857}
858
859
860/*
861 * Here we try to reset everything back to a state in which suspended
862 */
863
3ae5eaec 864static int i8042_resume(struct platform_device *dev)
1da177e4 865{
de9ce703 866 int error;
1da177e4 867
82dd9eff
DT
868/*
869 * Do not bother with restoring state if we haven't suspened yet
870 */
871 if (dev->dev.power.power_state.event == PM_EVENT_ON)
872 return 0;
873
de9ce703
DT
874 error = i8042_controller_check();
875 if (error)
876 return error;
2673c836 877
de9ce703
DT
878 error = i8042_controller_selftest();
879 if (error)
880 return error;
1da177e4
LT
881
882/*
82dd9eff 883 * Restore original CTR value and disable all ports
1da177e4
LT
884 */
885
82dd9eff
DT
886 i8042_ctr = i8042_initial_ctr;
887 if (i8042_direct)
888 i8042_ctr &= ~I8042_CTR_XLATE;
de9ce703
DT
889 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
890 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
891 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
892 printk(KERN_ERR "i8042: Can't write CTR to resume\n");
893 return -EIO;
894 }
1da177e4 895
de9ce703
DT
896 if (i8042_mux_present) {
897 if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports())
898 printk(KERN_WARNING
899 "i8042: failed to resume active multiplexor, "
900 "mouse won't work.\n");
901 } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
902 i8042_enable_aux_port();
1da177e4 903
de9ce703
DT
904 if (i8042_ports[I8042_KBD_PORT_NO].serio)
905 i8042_enable_kbd_port();
906
7d12e780 907 i8042_interrupt(0, NULL);
1da177e4 908
82dd9eff
DT
909 dev->dev.power.power_state = PMSG_ON;
910
1da177e4 911 return 0;
1da177e4 912}
82dd9eff 913#endif /* CONFIG_PM */
1da177e4
LT
914
915/*
916 * We need to reset the 8042 back to original mode on system shutdown,
917 * because otherwise BIOSes will be confused.
918 */
919
3ae5eaec 920static void i8042_shutdown(struct platform_device *dev)
1da177e4 921{
82dd9eff 922 i8042_controller_reset();
1da177e4
LT
923}
924
87fd6318 925static int __devinit i8042_create_kbd_port(void)
1da177e4
LT
926{
927 struct serio *serio;
928 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
929
d39969de 930 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
0854e52d
DT
931 if (!serio)
932 return -ENOMEM;
933
934 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
935 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
0854e52d
DT
936 serio->start = i8042_start;
937 serio->stop = i8042_stop;
938 serio->port_data = port;
939 serio->dev.parent = &i8042_platform_device->dev;
de9ce703 940 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
0854e52d
DT
941 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
942
943 port->serio = serio;
de9ce703 944 port->irq = I8042_KBD_IRQ;
0854e52d 945
de9ce703 946 return 0;
1da177e4
LT
947}
948
de9ce703 949static int __devinit i8042_create_aux_port(int idx)
1da177e4
LT
950{
951 struct serio *serio;
de9ce703
DT
952 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
953 struct i8042_port *port = &i8042_ports[port_no];
1da177e4 954
d39969de 955 serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
0854e52d
DT
956 if (!serio)
957 return -ENOMEM;
958
959 serio->id.type = SERIO_8042;
960 serio->write = i8042_aux_write;
0854e52d
DT
961 serio->start = i8042_start;
962 serio->stop = i8042_stop;
963 serio->port_data = port;
964 serio->dev.parent = &i8042_platform_device->dev;
de9ce703
DT
965 if (idx < 0) {
966 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
967 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
968 } else {
969 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
970 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
971 }
0854e52d
DT
972
973 port->serio = serio;
de9ce703
DT
974 port->mux = idx;
975 port->irq = I8042_AUX_IRQ;
0854e52d 976
de9ce703 977 return 0;
1da177e4
LT
978}
979
de9ce703 980static void __devinit i8042_free_kbd_port(void)
1da177e4 981{
de9ce703
DT
982 kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
983 i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
984}
1da177e4 985
de9ce703
DT
986static void __devinit i8042_free_aux_ports(void)
987{
988 int i;
0854e52d 989
de9ce703
DT
990 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
991 kfree(i8042_ports[i].serio);
992 i8042_ports[i].serio = NULL;
993 }
994}
0854e52d 995
de9ce703
DT
996static void __devinit i8042_register_ports(void)
997{
998 int i;
0854e52d 999
de9ce703
DT
1000 for (i = 0; i < I8042_NUM_PORTS; i++) {
1001 if (i8042_ports[i].serio) {
1002 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
1003 i8042_ports[i].serio->name,
1004 (unsigned long) I8042_DATA_REG,
1005 (unsigned long) I8042_COMMAND_REG,
1006 i8042_ports[i].irq);
1007 serio_register_port(i8042_ports[i].serio);
1008 }
1009 }
1da177e4
LT
1010}
1011
de9ce703 1012static void __devinit i8042_unregister_ports(void)
1da177e4 1013{
de9ce703 1014 int i;
1da177e4 1015
de9ce703
DT
1016 for (i = 0; i < I8042_NUM_PORTS; i++) {
1017 if (i8042_ports[i].serio) {
1018 serio_unregister_port(i8042_ports[i].serio);
1019 i8042_ports[i].serio = NULL;
1020 }
1021 }
1022}
1023
1024static void i8042_free_irqs(void)
1025{
1026 if (i8042_aux_irq_registered)
1027 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1028 if (i8042_kbd_irq_registered)
1029 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1030
1031 i8042_aux_irq_registered = i8042_kbd_irq_registered = 0;
1032}
1033
1034static int __devinit i8042_setup_aux(void)
1035{
1036 int (*aux_enable)(void);
1037 int error;
1038 int i;
1da177e4 1039
de9ce703 1040 if (i8042_check_aux())
87fd6318 1041 return -ENODEV;
1da177e4 1042
de9ce703
DT
1043 if (i8042_nomux || i8042_check_mux()) {
1044 error = i8042_create_aux_port(-1);
1045 if (error)
1046 goto err_free_ports;
1047 aux_enable = i8042_enable_aux_port;
1048 } else {
1049 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
1050 error = i8042_create_aux_port(i);
1051 if (error)
1052 goto err_free_ports;
0854e52d 1053 }
de9ce703 1054 aux_enable = i8042_enable_mux_ports;
1da177e4
LT
1055 }
1056
de9ce703
DT
1057 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
1058 "i8042", i8042_platform_device);
1059 if (error)
1060 goto err_free_ports;
945ef0d4 1061
de9ce703
DT
1062 if (aux_enable())
1063 goto err_free_irq;
1da177e4 1064
de9ce703 1065 i8042_aux_irq_registered = 1;
1da177e4 1066 return 0;
0854e52d 1067
de9ce703
DT
1068 err_free_irq:
1069 free_irq(I8042_AUX_IRQ, i8042_platform_device);
1070 err_free_ports:
1071 i8042_free_aux_ports();
1072 return error;
1073}
0854e52d 1074
de9ce703
DT
1075static int __devinit i8042_setup_kbd(void)
1076{
1077 int error;
1078
1079 error = i8042_create_kbd_port();
1080 if (error)
1081 return error;
1082
1083 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
1084 "i8042", i8042_platform_device);
1085 if (error)
1086 goto err_free_port;
1087
1088 error = i8042_enable_kbd_port();
1089 if (error)
1090 goto err_free_irq;
1091
1092 i8042_kbd_irq_registered = 1;
1093 return 0;
1094
1095 err_free_irq:
1096 free_irq(I8042_KBD_IRQ, i8042_platform_device);
1097 err_free_port:
1098 i8042_free_kbd_port();
1099 return error;
1da177e4
LT
1100}
1101
de9ce703 1102static int __devinit i8042_probe(struct platform_device *dev)
1da177e4 1103{
de9ce703 1104 int error;
1da177e4 1105
de9ce703
DT
1106 error = i8042_controller_selftest();
1107 if (error)
1108 return error;
1da177e4 1109
de9ce703
DT
1110 error = i8042_controller_init();
1111 if (error)
1112 return error;
1113
1114 if (!i8042_noaux) {
1115 error = i8042_setup_aux();
1116 if (error && error != -ENODEV && error != -EBUSY)
1117 goto out_fail;
1118 }
1119
1120 if (!i8042_nokbd) {
1121 error = i8042_setup_kbd();
1122 if (error)
1123 goto out_fail;
1124 }
1da177e4 1125
de9ce703
DT
1126/*
1127 * Ok, everything is ready, let's register all serio ports
1128 */
1129 i8042_register_ports();
1130
1131 return 0;
1132
1133 out_fail:
1134 i8042_free_aux_ports(); /* in case KBD failed but AUX not */
1135 i8042_free_irqs();
1136 i8042_controller_reset();
1137
1138 return error;
1139}
1140
1141static int __devexit i8042_remove(struct platform_device *dev)
1142{
1143 i8042_unregister_ports();
1144 i8042_free_irqs();
1145 i8042_controller_reset();
1da177e4 1146
87fd6318
DT
1147 return 0;
1148}
1149
1150static struct platform_driver i8042_driver = {
1151 .driver = {
1152 .name = "i8042",
1153 .owner = THIS_MODULE,
1154 },
1155 .probe = i8042_probe,
1156 .remove = __devexit_p(i8042_remove),
82dd9eff
DT
1157 .shutdown = i8042_shutdown,
1158#ifdef CONFIG_PM
87fd6318
DT
1159 .suspend = i8042_suspend,
1160 .resume = i8042_resume,
82dd9eff 1161#endif
87fd6318
DT
1162};
1163
1164static int __init i8042_init(void)
1165{
1166 int err;
1167
1168 dbg_init();
1169
1170 err = i8042_platform_init();
1171 if (err)
1172 return err;
1173
de9ce703
DT
1174 err = i8042_controller_check();
1175 if (err)
1176 goto err_platform_exit;
87fd6318
DT
1177
1178 err = platform_driver_register(&i8042_driver);
1179 if (err)
1180 goto err_platform_exit;
1181
1182 i8042_platform_device = platform_device_alloc("i8042", -1);
1183 if (!i8042_platform_device) {
1184 err = -ENOMEM;
1185 goto err_unregister_driver;
1186 }
1187
1188 err = platform_device_add(i8042_platform_device);
1189 if (err)
1190 goto err_free_device;
1191
de9ce703
DT
1192 panic_blink = i8042_panic_blink;
1193
87fd6318
DT
1194 return 0;
1195
1196 err_free_device:
1197 platform_device_put(i8042_platform_device);
1198 err_unregister_driver:
1199 platform_driver_unregister(&i8042_driver);
1200 err_platform_exit:
1201 i8042_platform_exit();
1202
1203 return err;
1204}
1205
1206static void __exit i8042_exit(void)
1207{
1da177e4 1208 platform_device_unregister(i8042_platform_device);
3ae5eaec 1209 platform_driver_unregister(&i8042_driver);
1da177e4
LT
1210 i8042_platform_exit();
1211
1212 panic_blink = NULL;
1213}
1214
1215module_init(i8042_init);
1216module_exit(i8042_exit);