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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * i8042 keyboard and mouse controller driver for Linux | |
3 | * | |
4 | * Copyright (c) 1999-2004 Vojtech Pavlik | |
5 | */ | |
6 | ||
7 | /* | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | */ | |
12 | ||
4eb3c30b JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
7e044e05 | 15 | #include <linux/types.h> |
1da177e4 LT |
16 | #include <linux/delay.h> |
17 | #include <linux/module.h> | |
1da177e4 LT |
18 | #include <linux/interrupt.h> |
19 | #include <linux/ioport.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | #include <linux/serio.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/rcupdate.h> | |
d052d1be | 24 | #include <linux/platform_device.h> |
553a05b8 | 25 | #include <linux/i8042.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
1c5dd134 | 27 | #include <linux/suspend.h> |
1da177e4 LT |
28 | |
29 | #include <asm/io.h> | |
30 | ||
31 | MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); | |
32 | MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); | |
33 | MODULE_LICENSE("GPL"); | |
34 | ||
386b3849 | 35 | static bool i8042_nokbd; |
945ef0d4 DT |
36 | module_param_named(nokbd, i8042_nokbd, bool, 0); |
37 | MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); | |
38 | ||
386b3849 | 39 | static bool i8042_noaux; |
1da177e4 LT |
40 | module_param_named(noaux, i8042_noaux, bool, 0); |
41 | MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); | |
42 | ||
e55a3366 | 43 | static bool i8042_nomux; |
1da177e4 | 44 | module_param_named(nomux, i8042_nomux, bool, 0); |
2c860a11 | 45 | MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); |
1da177e4 | 46 | |
386b3849 | 47 | static bool i8042_unlock; |
1da177e4 LT |
48 | module_param_named(unlock, i8042_unlock, bool, 0); |
49 | MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); | |
50 | ||
930e1924 MPS |
51 | enum i8042_controller_reset_mode { |
52 | I8042_RESET_NEVER, | |
53 | I8042_RESET_ALWAYS, | |
54 | I8042_RESET_ON_S2RAM, | |
55 | #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM | |
56 | }; | |
57 | static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT; | |
58 | static int i8042_set_reset(const char *val, const struct kernel_param *kp) | |
59 | { | |
60 | enum i8042_controller_reset_mode *arg = kp->arg; | |
61 | int error; | |
62 | bool reset; | |
63 | ||
64 | if (val) { | |
65 | error = kstrtobool(val, &reset); | |
66 | if (error) | |
67 | return error; | |
68 | } else { | |
69 | reset = true; | |
70 | } | |
71 | ||
72 | *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER; | |
73 | return 0; | |
74 | } | |
75 | ||
76 | static const struct kernel_param_ops param_ops_reset_param = { | |
77 | .flags = KERNEL_PARAM_OPS_FL_NOARG, | |
78 | .set = i8042_set_reset, | |
79 | }; | |
80 | #define param_check_reset_param(name, p) \ | |
81 | __param_check(name, p, enum i8042_controller_reset_mode) | |
82 | module_param_named(reset, i8042_reset, reset_param, 0); | |
83 | MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both"); | |
1da177e4 | 84 | |
386b3849 | 85 | static bool i8042_direct; |
1da177e4 LT |
86 | module_param_named(direct, i8042_direct, bool, 0); |
87 | MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); | |
88 | ||
386b3849 | 89 | static bool i8042_dumbkbd; |
1da177e4 LT |
90 | module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); |
91 | MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); | |
92 | ||
386b3849 | 93 | static bool i8042_noloop; |
1da177e4 LT |
94 | module_param_named(noloop, i8042_noloop, bool, 0); |
95 | MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); | |
96 | ||
f8313ef1 JK |
97 | static bool i8042_notimeout; |
98 | module_param_named(notimeout, i8042_notimeout, bool, 0); | |
99 | MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); | |
100 | ||
148e9a71 SV |
101 | static bool i8042_kbdreset; |
102 | module_param_named(kbdreset, i8042_kbdreset, bool, 0); | |
103 | MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); | |
104 | ||
8987fec0 | 105 | #ifdef CONFIG_X86 |
386b3849 | 106 | static bool i8042_dritek; |
8987fec0 CC |
107 | module_param_named(dritek, i8042_dritek, bool, 0); |
108 | MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); | |
109 | #endif | |
110 | ||
1da177e4 | 111 | #ifdef CONFIG_PNP |
386b3849 | 112 | static bool i8042_nopnp; |
1da177e4 LT |
113 | module_param_named(nopnp, i8042_nopnp, bool, 0); |
114 | MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); | |
115 | #endif | |
116 | ||
117 | #define DEBUG | |
118 | #ifdef DEBUG | |
386b3849 | 119 | static bool i8042_debug; |
1da177e4 LT |
120 | module_param_named(debug, i8042_debug, bool, 0600); |
121 | MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); | |
e1443d28 SCP |
122 | |
123 | static bool i8042_unmask_kbd_data; | |
124 | module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600); | |
125 | MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]"); | |
1da177e4 LT |
126 | #endif |
127 | ||
1c7827ae | 128 | static bool i8042_bypass_aux_irq_test; |
a7c5868c HG |
129 | static char i8042_kbd_firmware_id[128]; |
130 | static char i8042_aux_firmware_id[128]; | |
1c7827ae | 131 | |
1da177e4 LT |
132 | #include "i8042.h" |
133 | ||
181d683d DT |
134 | /* |
135 | * i8042_lock protects serialization between i8042_command and | |
136 | * the interrupt handler. | |
137 | */ | |
1da177e4 LT |
138 | static DEFINE_SPINLOCK(i8042_lock); |
139 | ||
181d683d DT |
140 | /* |
141 | * Writers to AUX and KBD ports as well as users issuing i8042_command | |
142 | * directly should acquire i8042_mutex (by means of calling | |
143 | * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that | |
144 | * they do not disturb each other (unfortunately in many i8042 | |
145 | * implementations write to one of the ports will immediately abort | |
146 | * command that is being processed by another port). | |
147 | */ | |
148 | static DEFINE_MUTEX(i8042_mutex); | |
149 | ||
1da177e4 LT |
150 | struct i8042_port { |
151 | struct serio *serio; | |
152 | int irq; | |
386b3849 | 153 | bool exists; |
e1443d28 | 154 | bool driver_bound; |
1da177e4 | 155 | signed char mux; |
1da177e4 LT |
156 | }; |
157 | ||
158 | #define I8042_KBD_PORT_NO 0 | |
159 | #define I8042_AUX_PORT_NO 1 | |
160 | #define I8042_MUX_PORT_NO 2 | |
161 | #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) | |
de9ce703 DT |
162 | |
163 | static struct i8042_port i8042_ports[I8042_NUM_PORTS]; | |
1da177e4 LT |
164 | |
165 | static unsigned char i8042_initial_ctr; | |
166 | static unsigned char i8042_ctr; | |
386b3849 DT |
167 | static bool i8042_mux_present; |
168 | static bool i8042_kbd_irq_registered; | |
169 | static bool i8042_aux_irq_registered; | |
817e6ba3 | 170 | static unsigned char i8042_suppress_kbd_ack; |
1da177e4 | 171 | static struct platform_device *i8042_platform_device; |
e1443d28 | 172 | static struct notifier_block i8042_kbd_bind_notifier_block; |
1da177e4 | 173 | |
7d12e780 | 174 | static irqreturn_t i8042_interrupt(int irq, void *dev_id); |
967c9ef9 MG |
175 | static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, |
176 | struct serio *serio); | |
1da177e4 | 177 | |
181d683d DT |
178 | void i8042_lock_chip(void) |
179 | { | |
180 | mutex_lock(&i8042_mutex); | |
181 | } | |
182 | EXPORT_SYMBOL(i8042_lock_chip); | |
183 | ||
184 | void i8042_unlock_chip(void) | |
185 | { | |
186 | mutex_unlock(&i8042_mutex); | |
187 | } | |
188 | EXPORT_SYMBOL(i8042_unlock_chip); | |
189 | ||
967c9ef9 MG |
190 | int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, |
191 | struct serio *serio)) | |
192 | { | |
193 | unsigned long flags; | |
194 | int ret = 0; | |
195 | ||
196 | spin_lock_irqsave(&i8042_lock, flags); | |
197 | ||
198 | if (i8042_platform_filter) { | |
199 | ret = -EBUSY; | |
200 | goto out; | |
201 | } | |
202 | ||
203 | i8042_platform_filter = filter; | |
204 | ||
205 | out: | |
206 | spin_unlock_irqrestore(&i8042_lock, flags); | |
207 | return ret; | |
208 | } | |
209 | EXPORT_SYMBOL(i8042_install_filter); | |
210 | ||
211 | int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, | |
212 | struct serio *port)) | |
213 | { | |
214 | unsigned long flags; | |
215 | int ret = 0; | |
216 | ||
217 | spin_lock_irqsave(&i8042_lock, flags); | |
218 | ||
219 | if (i8042_platform_filter != filter) { | |
220 | ret = -EINVAL; | |
221 | goto out; | |
222 | } | |
223 | ||
224 | i8042_platform_filter = NULL; | |
225 | ||
226 | out: | |
227 | spin_unlock_irqrestore(&i8042_lock, flags); | |
228 | return ret; | |
229 | } | |
230 | EXPORT_SYMBOL(i8042_remove_filter); | |
231 | ||
1da177e4 LT |
232 | /* |
233 | * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to | |
234 | * be ready for reading values from it / writing values to it. | |
235 | * Called always with i8042_lock held. | |
236 | */ | |
237 | ||
238 | static int i8042_wait_read(void) | |
239 | { | |
240 | int i = 0; | |
de9ce703 | 241 | |
1da177e4 LT |
242 | while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { |
243 | udelay(50); | |
244 | i++; | |
245 | } | |
246 | return -(i == I8042_CTL_TIMEOUT); | |
247 | } | |
248 | ||
249 | static int i8042_wait_write(void) | |
250 | { | |
251 | int i = 0; | |
de9ce703 | 252 | |
1da177e4 LT |
253 | while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { |
254 | udelay(50); | |
255 | i++; | |
256 | } | |
257 | return -(i == I8042_CTL_TIMEOUT); | |
258 | } | |
259 | ||
260 | /* | |
261 | * i8042_flush() flushes all data that may be in the keyboard and mouse buffers | |
262 | * of the i8042 down the toilet. | |
263 | */ | |
264 | ||
265 | static int i8042_flush(void) | |
266 | { | |
267 | unsigned long flags; | |
268 | unsigned char data, str; | |
2f0d2604 AM |
269 | int count = 0; |
270 | int retval = 0; | |
1da177e4 LT |
271 | |
272 | spin_lock_irqsave(&i8042_lock, flags); | |
273 | ||
2f0d2604 AM |
274 | while ((str = i8042_read_status()) & I8042_STR_OBF) { |
275 | if (count++ < I8042_BUFFER_SIZE) { | |
276 | udelay(50); | |
277 | data = i8042_read_data(); | |
278 | dbg("%02x <- i8042 (flush, %s)\n", | |
279 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
280 | } else { | |
281 | retval = -EIO; | |
282 | break; | |
283 | } | |
1da177e4 LT |
284 | } |
285 | ||
286 | spin_unlock_irqrestore(&i8042_lock, flags); | |
287 | ||
2f0d2604 | 288 | return retval; |
1da177e4 LT |
289 | } |
290 | ||
291 | /* | |
292 | * i8042_command() executes a command on the i8042. It also sends the input | |
293 | * parameter(s) of the commands to it, and receives the output value(s). The | |
294 | * parameters are to be stored in the param array, and the output is placed | |
295 | * into the same array. The number of the parameters and output values is | |
296 | * encoded in bits 8-11 of the command number. | |
297 | */ | |
298 | ||
de9ce703 | 299 | static int __i8042_command(unsigned char *param, int command) |
1da177e4 | 300 | { |
de9ce703 | 301 | int i, error; |
1da177e4 LT |
302 | |
303 | if (i8042_noloop && command == I8042_CMD_AUX_LOOP) | |
304 | return -1; | |
305 | ||
de9ce703 DT |
306 | error = i8042_wait_write(); |
307 | if (error) | |
308 | return error; | |
463a4f76 | 309 | |
4eb3c30b | 310 | dbg("%02x -> i8042 (command)\n", command & 0xff); |
463a4f76 DT |
311 | i8042_write_command(command & 0xff); |
312 | ||
313 | for (i = 0; i < ((command >> 12) & 0xf); i++) { | |
de9ce703 | 314 | error = i8042_wait_write(); |
2ea9c236 MPS |
315 | if (error) { |
316 | dbg(" -- i8042 (wait write timeout)\n"); | |
de9ce703 | 317 | return error; |
2ea9c236 | 318 | } |
4eb3c30b | 319 | dbg("%02x -> i8042 (parameter)\n", param[i]); |
463a4f76 | 320 | i8042_write_data(param[i]); |
1da177e4 LT |
321 | } |
322 | ||
463a4f76 | 323 | for (i = 0; i < ((command >> 8) & 0xf); i++) { |
de9ce703 DT |
324 | error = i8042_wait_read(); |
325 | if (error) { | |
2ea9c236 | 326 | dbg(" -- i8042 (wait read timeout)\n"); |
de9ce703 DT |
327 | return error; |
328 | } | |
1da177e4 | 329 | |
463a4f76 DT |
330 | if (command == I8042_CMD_AUX_LOOP && |
331 | !(i8042_read_status() & I8042_STR_AUXDATA)) { | |
4eb3c30b | 332 | dbg(" -- i8042 (auxerr)\n"); |
de9ce703 | 333 | return -1; |
1da177e4 LT |
334 | } |
335 | ||
463a4f76 | 336 | param[i] = i8042_read_data(); |
4eb3c30b | 337 | dbg("%02x <- i8042 (return)\n", param[i]); |
463a4f76 | 338 | } |
1da177e4 | 339 | |
de9ce703 DT |
340 | return 0; |
341 | } | |
1da177e4 | 342 | |
553a05b8 | 343 | int i8042_command(unsigned char *param, int command) |
de9ce703 DT |
344 | { |
345 | unsigned long flags; | |
346 | int retval; | |
347 | ||
348 | spin_lock_irqsave(&i8042_lock, flags); | |
349 | retval = __i8042_command(param, command); | |
463a4f76 | 350 | spin_unlock_irqrestore(&i8042_lock, flags); |
de9ce703 | 351 | |
1da177e4 LT |
352 | return retval; |
353 | } | |
553a05b8 | 354 | EXPORT_SYMBOL(i8042_command); |
1da177e4 LT |
355 | |
356 | /* | |
357 | * i8042_kbd_write() sends a byte out through the keyboard interface. | |
358 | */ | |
359 | ||
360 | static int i8042_kbd_write(struct serio *port, unsigned char c) | |
361 | { | |
362 | unsigned long flags; | |
363 | int retval = 0; | |
364 | ||
365 | spin_lock_irqsave(&i8042_lock, flags); | |
366 | ||
de9ce703 | 367 | if (!(retval = i8042_wait_write())) { |
4eb3c30b | 368 | dbg("%02x -> i8042 (kbd-data)\n", c); |
1da177e4 LT |
369 | i8042_write_data(c); |
370 | } | |
371 | ||
372 | spin_unlock_irqrestore(&i8042_lock, flags); | |
373 | ||
374 | return retval; | |
375 | } | |
376 | ||
377 | /* | |
378 | * i8042_aux_write() sends a byte out through the aux interface. | |
379 | */ | |
380 | ||
381 | static int i8042_aux_write(struct serio *serio, unsigned char c) | |
382 | { | |
383 | struct i8042_port *port = serio->port_data; | |
1da177e4 | 384 | |
f4e3c711 DT |
385 | return i8042_command(&c, port->mux == -1 ? |
386 | I8042_CMD_AUX_SEND : | |
387 | I8042_CMD_MUX_SEND + port->mux); | |
1da177e4 LT |
388 | } |
389 | ||
5ddbc77c DT |
390 | |
391 | /* | |
0e2b4458 | 392 | * i8042_port_close attempts to clear AUX or KBD port state by disabling |
5ddbc77c DT |
393 | * and then re-enabling it. |
394 | */ | |
395 | ||
396 | static void i8042_port_close(struct serio *serio) | |
397 | { | |
398 | int irq_bit; | |
399 | int disable_bit; | |
400 | const char *port_name; | |
401 | ||
402 | if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { | |
403 | irq_bit = I8042_CTR_AUXINT; | |
404 | disable_bit = I8042_CTR_AUXDIS; | |
405 | port_name = "AUX"; | |
406 | } else { | |
407 | irq_bit = I8042_CTR_KBDINT; | |
408 | disable_bit = I8042_CTR_KBDDIS; | |
409 | port_name = "KBD"; | |
410 | } | |
411 | ||
412 | i8042_ctr &= ~irq_bit; | |
413 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 414 | pr_warn("Can't write CTR while closing %s port\n", port_name); |
5ddbc77c DT |
415 | |
416 | udelay(50); | |
417 | ||
418 | i8042_ctr &= ~disable_bit; | |
419 | i8042_ctr |= irq_bit; | |
420 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 421 | pr_err("Can't reactivate %s port\n", port_name); |
5ddbc77c DT |
422 | |
423 | /* | |
424 | * See if there is any data appeared while we were messing with | |
425 | * port state. | |
426 | */ | |
427 | i8042_interrupt(0, NULL); | |
428 | } | |
429 | ||
1da177e4 LT |
430 | /* |
431 | * i8042_start() is called by serio core when port is about to finish | |
432 | * registering. It will mark port as existing so i8042_interrupt can | |
433 | * start sending data through it. | |
434 | */ | |
435 | static int i8042_start(struct serio *serio) | |
436 | { | |
437 | struct i8042_port *port = serio->port_data; | |
438 | ||
340d394a | 439 | spin_lock_irq(&i8042_lock); |
386b3849 | 440 | port->exists = true; |
340d394a CH |
441 | spin_unlock_irq(&i8042_lock); |
442 | ||
1da177e4 LT |
443 | return 0; |
444 | } | |
445 | ||
446 | /* | |
447 | * i8042_stop() marks serio port as non-existing so i8042_interrupt | |
448 | * will not try to send data to the port that is about to go away. | |
449 | * The function is called by serio core as part of unregister procedure. | |
450 | */ | |
451 | static void i8042_stop(struct serio *serio) | |
452 | { | |
453 | struct i8042_port *port = serio->port_data; | |
454 | ||
340d394a | 455 | spin_lock_irq(&i8042_lock); |
386b3849 | 456 | port->exists = false; |
340d394a CH |
457 | port->serio = NULL; |
458 | spin_unlock_irq(&i8042_lock); | |
a8399c51 DT |
459 | |
460 | /* | |
340d394a CH |
461 | * We need to make sure that interrupt handler finishes using |
462 | * our serio port before we return from this function. | |
a8399c51 DT |
463 | * We synchronize with both AUX and KBD IRQs because there is |
464 | * a (very unlikely) chance that AUX IRQ is raised for KBD port | |
465 | * and vice versa. | |
466 | */ | |
467 | synchronize_irq(I8042_AUX_IRQ); | |
468 | synchronize_irq(I8042_KBD_IRQ); | |
1da177e4 LT |
469 | } |
470 | ||
4e8d340d DT |
471 | /* |
472 | * i8042_filter() filters out unwanted bytes from the input data stream. | |
473 | * It is called from i8042_interrupt and thus is running with interrupts | |
474 | * off and i8042_lock held. | |
475 | */ | |
967c9ef9 MG |
476 | static bool i8042_filter(unsigned char data, unsigned char str, |
477 | struct serio *serio) | |
4e8d340d DT |
478 | { |
479 | if (unlikely(i8042_suppress_kbd_ack)) { | |
480 | if ((~str & I8042_STR_AUXDATA) && | |
481 | (data == 0xfa || data == 0xfe)) { | |
482 | i8042_suppress_kbd_ack--; | |
483 | dbg("Extra keyboard ACK - filtered out\n"); | |
484 | return true; | |
485 | } | |
486 | } | |
487 | ||
967c9ef9 | 488 | if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { |
0747e3bc | 489 | dbg("Filtered out by platform filter\n"); |
967c9ef9 MG |
490 | return true; |
491 | } | |
492 | ||
4e8d340d DT |
493 | return false; |
494 | } | |
495 | ||
1da177e4 LT |
496 | /* |
497 | * i8042_interrupt() is the most important function in this driver - | |
498 | * it handles the interrupts from the i8042, and sends incoming bytes | |
499 | * to the upper layers. | |
500 | */ | |
501 | ||
7d12e780 | 502 | static irqreturn_t i8042_interrupt(int irq, void *dev_id) |
1da177e4 LT |
503 | { |
504 | struct i8042_port *port; | |
967c9ef9 | 505 | struct serio *serio; |
1da177e4 LT |
506 | unsigned long flags; |
507 | unsigned char str, data; | |
508 | unsigned int dfl; | |
509 | unsigned int port_no; | |
4e8d340d | 510 | bool filtered; |
817e6ba3 | 511 | int ret = 1; |
1da177e4 | 512 | |
1da177e4 | 513 | spin_lock_irqsave(&i8042_lock, flags); |
4e8d340d | 514 | |
1da177e4 LT |
515 | str = i8042_read_status(); |
516 | if (unlikely(~str & I8042_STR_OBF)) { | |
517 | spin_unlock_irqrestore(&i8042_lock, flags); | |
4eb3c30b JP |
518 | if (irq) |
519 | dbg("Interrupt %d, without any data\n", irq); | |
1da177e4 LT |
520 | ret = 0; |
521 | goto out; | |
522 | } | |
4e8d340d | 523 | |
1da177e4 | 524 | data = i8042_read_data(); |
1da177e4 LT |
525 | |
526 | if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { | |
527 | static unsigned long last_transmit; | |
528 | static unsigned char last_str; | |
529 | ||
530 | dfl = 0; | |
531 | if (str & I8042_STR_MUXERR) { | |
4eb3c30b JP |
532 | dbg("MUX error, status is %02x, data is %02x\n", |
533 | str, data); | |
1da177e4 LT |
534 | /* |
535 | * When MUXERR condition is signalled the data register can only contain | |
536 | * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately | |
a216a4b6 DT |
537 | * it is not always the case. Some KBCs also report 0xfc when there is |
538 | * nothing connected to the port while others sometimes get confused which | |
539 | * port the data came from and signal error leaving the data intact. They | |
540 | * _do not_ revert to legacy mode (actually I've never seen KBC reverting | |
541 | * to legacy mode yet, when we see one we'll add proper handling). | |
542 | * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the | |
543 | * rest assume that the data came from the same serio last byte | |
1da177e4 LT |
544 | * was transmitted (if transmission happened not too long ago). |
545 | */ | |
a216a4b6 DT |
546 | |
547 | switch (data) { | |
548 | default: | |
1da177e4 LT |
549 | if (time_before(jiffies, last_transmit + HZ/10)) { |
550 | str = last_str; | |
551 | break; | |
552 | } | |
553 | /* fall through - report timeout */ | |
a216a4b6 | 554 | case 0xfc: |
1da177e4 LT |
555 | case 0xfd: |
556 | case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; | |
557 | case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; | |
558 | } | |
559 | } | |
560 | ||
561 | port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); | |
562 | last_str = str; | |
563 | last_transmit = jiffies; | |
564 | } else { | |
565 | ||
566 | dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | | |
f8313ef1 | 567 | ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); |
1da177e4 LT |
568 | |
569 | port_no = (str & I8042_STR_AUXDATA) ? | |
570 | I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; | |
571 | } | |
572 | ||
573 | port = &i8042_ports[port_no]; | |
967c9ef9 | 574 | serio = port->exists ? port->serio : NULL; |
1da177e4 | 575 | |
e1443d28 SCP |
576 | filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n", |
577 | port_no, irq, | |
578 | dfl & SERIO_PARITY ? ", bad parity" : "", | |
579 | dfl & SERIO_TIMEOUT ? ", timeout" : ""); | |
1da177e4 | 580 | |
967c9ef9 | 581 | filtered = i8042_filter(data, str, serio); |
4e8d340d DT |
582 | |
583 | spin_unlock_irqrestore(&i8042_lock, flags); | |
817e6ba3 | 584 | |
340d394a | 585 | if (likely(serio && !filtered)) |
967c9ef9 | 586 | serio_interrupt(serio, data, dfl); |
1da177e4 | 587 | |
0854e52d | 588 | out: |
1da177e4 LT |
589 | return IRQ_RETVAL(ret); |
590 | } | |
591 | ||
de9ce703 | 592 | /* |
5ddbc77c | 593 | * i8042_enable_kbd_port enables keyboard port on chip |
de9ce703 DT |
594 | */ |
595 | ||
596 | static int i8042_enable_kbd_port(void) | |
597 | { | |
598 | i8042_ctr &= ~I8042_CTR_KBDDIS; | |
599 | i8042_ctr |= I8042_CTR_KBDINT; | |
600 | ||
601 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
602 | i8042_ctr &= ~I8042_CTR_KBDINT; |
603 | i8042_ctr |= I8042_CTR_KBDDIS; | |
4eb3c30b | 604 | pr_err("Failed to enable KBD port\n"); |
de9ce703 DT |
605 | return -EIO; |
606 | } | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | /* | |
612 | * i8042_enable_aux_port enables AUX (mouse) port on chip | |
613 | */ | |
614 | ||
615 | static int i8042_enable_aux_port(void) | |
616 | { | |
617 | i8042_ctr &= ~I8042_CTR_AUXDIS; | |
618 | i8042_ctr |= I8042_CTR_AUXINT; | |
619 | ||
620 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
018db6bb MA |
621 | i8042_ctr &= ~I8042_CTR_AUXINT; |
622 | i8042_ctr |= I8042_CTR_AUXDIS; | |
4eb3c30b | 623 | pr_err("Failed to enable AUX port\n"); |
de9ce703 DT |
624 | return -EIO; |
625 | } | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | /* | |
631 | * i8042_enable_mux_ports enables 4 individual AUX ports after | |
632 | * the controller has been switched into Multiplexed mode | |
633 | */ | |
634 | ||
635 | static int i8042_enable_mux_ports(void) | |
636 | { | |
637 | unsigned char param; | |
638 | int i; | |
639 | ||
640 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
641 | i8042_command(¶m, I8042_CMD_MUX_PFX + i); | |
642 | i8042_command(¶m, I8042_CMD_AUX_ENABLE); | |
643 | } | |
644 | ||
645 | return i8042_enable_aux_port(); | |
646 | } | |
647 | ||
1da177e4 | 648 | /* |
386b3849 DT |
649 | * i8042_set_mux_mode checks whether the controller has an |
650 | * active multiplexor and puts the chip into Multiplexed (true) | |
651 | * or Legacy (false) mode. | |
1da177e4 LT |
652 | */ |
653 | ||
386b3849 | 654 | static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) |
1da177e4 LT |
655 | { |
656 | ||
386b3849 | 657 | unsigned char param, val; |
1da177e4 LT |
658 | /* |
659 | * Get rid of bytes in the queue. | |
660 | */ | |
661 | ||
662 | i8042_flush(); | |
663 | ||
664 | /* | |
665 | * Internal loopback test - send three bytes, they should come back from the | |
de9ce703 | 666 | * mouse interface, the last should be version. |
1da177e4 LT |
667 | */ |
668 | ||
386b3849 DT |
669 | param = val = 0xf0; |
670 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
671 | return -1; | |
672 | param = val = multiplex ? 0x56 : 0xf6; | |
673 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) | |
1da177e4 | 674 | return -1; |
386b3849 DT |
675 | param = val = multiplex ? 0xa4 : 0xa5; |
676 | if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) | |
1da177e4 | 677 | return -1; |
386b3849 DT |
678 | |
679 | /* | |
680 | * Workaround for interference with USB Legacy emulation | |
681 | * that causes a v10.12 MUX to be found. | |
682 | */ | |
683 | if (param == 0xac) | |
1da177e4 LT |
684 | return -1; |
685 | ||
686 | if (mux_version) | |
463a4f76 | 687 | *mux_version = param; |
1da177e4 LT |
688 | |
689 | return 0; | |
690 | } | |
691 | ||
1da177e4 | 692 | /* |
de9ce703 DT |
693 | * i8042_check_mux() checks whether the controller supports the PS/2 Active |
694 | * Multiplexing specification by Synaptics, Phoenix, Insyde and | |
695 | * LCS/Telegraphics. | |
1da177e4 LT |
696 | */ |
697 | ||
f8113416 | 698 | static int __init i8042_check_mux(void) |
1da177e4 | 699 | { |
de9ce703 DT |
700 | unsigned char mux_version; |
701 | ||
386b3849 | 702 | if (i8042_set_mux_mode(true, &mux_version)) |
de9ce703 DT |
703 | return -1; |
704 | ||
4eb3c30b | 705 | pr_info("Detected active multiplexing controller, rev %d.%d\n", |
de9ce703 | 706 | (mux_version >> 4) & 0xf, mux_version & 0xf); |
1da177e4 | 707 | |
de9ce703 DT |
708 | /* |
709 | * Disable all muxed ports by disabling AUX. | |
710 | */ | |
1da177e4 LT |
711 | i8042_ctr |= I8042_CTR_AUXDIS; |
712 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
713 | ||
714 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 715 | pr_err("Failed to disable AUX port, can't use MUX\n"); |
de9ce703 | 716 | return -EIO; |
1da177e4 LT |
717 | } |
718 | ||
386b3849 | 719 | i8042_mux_present = true; |
1da177e4 LT |
720 | |
721 | return 0; | |
722 | } | |
723 | ||
1da177e4 | 724 | /* |
de9ce703 | 725 | * The following is used to test AUX IRQ delivery. |
1da177e4 | 726 | */ |
f8113416 DT |
727 | static struct completion i8042_aux_irq_delivered __initdata; |
728 | static bool i8042_irq_being_tested __initdata; | |
1da177e4 | 729 | |
f8113416 | 730 | static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) |
1da177e4 | 731 | { |
de9ce703 DT |
732 | unsigned long flags; |
733 | unsigned char str, data; | |
e3758b2a | 734 | int ret = 0; |
1da177e4 | 735 | |
de9ce703 DT |
736 | spin_lock_irqsave(&i8042_lock, flags); |
737 | str = i8042_read_status(); | |
738 | if (str & I8042_STR_OBF) { | |
739 | data = i8042_read_data(); | |
4eb3c30b JP |
740 | dbg("%02x <- i8042 (aux_test_irq, %s)\n", |
741 | data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); | |
de9ce703 DT |
742 | if (i8042_irq_being_tested && |
743 | data == 0xa5 && (str & I8042_STR_AUXDATA)) | |
744 | complete(&i8042_aux_irq_delivered); | |
e3758b2a | 745 | ret = 1; |
de9ce703 DT |
746 | } |
747 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1da177e4 | 748 | |
e3758b2a | 749 | return IRQ_RETVAL(ret); |
1da177e4 LT |
750 | } |
751 | ||
d2ada559 RS |
752 | /* |
753 | * i8042_toggle_aux - enables or disables AUX port on i8042 via command and | |
754 | * verifies success by readinng CTR. Used when testing for presence of AUX | |
755 | * port. | |
756 | */ | |
f8113416 | 757 | static int __init i8042_toggle_aux(bool on) |
d2ada559 RS |
758 | { |
759 | unsigned char param; | |
760 | int i; | |
761 | ||
762 | if (i8042_command(¶m, | |
763 | on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) | |
764 | return -1; | |
765 | ||
766 | /* some chips need some time to set the I8042_CTR_AUXDIS bit */ | |
767 | for (i = 0; i < 100; i++) { | |
768 | udelay(50); | |
769 | ||
770 | if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) | |
771 | return -1; | |
772 | ||
773 | if (!(param & I8042_CTR_AUXDIS) == on) | |
774 | return 0; | |
775 | } | |
776 | ||
777 | return -1; | |
778 | } | |
1da177e4 LT |
779 | |
780 | /* | |
781 | * i8042_check_aux() applies as much paranoia as it can at detecting | |
782 | * the presence of an AUX interface. | |
783 | */ | |
784 | ||
f8113416 | 785 | static int __init i8042_check_aux(void) |
1da177e4 | 786 | { |
de9ce703 | 787 | int retval = -1; |
386b3849 DT |
788 | bool irq_registered = false; |
789 | bool aux_loop_broken = false; | |
de9ce703 | 790 | unsigned long flags; |
1da177e4 | 791 | unsigned char param; |
1da177e4 LT |
792 | |
793 | /* | |
794 | * Get rid of bytes in the queue. | |
795 | */ | |
796 | ||
797 | i8042_flush(); | |
798 | ||
799 | /* | |
800 | * Internal loopback test - filters out AT-type i8042's. Unfortunately | |
801 | * SiS screwed up and their 5597 doesn't support the LOOP command even | |
802 | * though it has an AUX port. | |
803 | */ | |
804 | ||
805 | param = 0x5a; | |
3ca5de6d DT |
806 | retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); |
807 | if (retval || param != 0x5a) { | |
1da177e4 LT |
808 | |
809 | /* | |
810 | * External connection test - filters out AT-soldered PS/2 i8042's | |
811 | * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error | |
812 | * 0xfa - no error on some notebooks which ignore the spec | |
813 | * Because it's common for chipsets to return error on perfectly functioning | |
814 | * AUX ports, we test for this only when the LOOP command failed. | |
815 | */ | |
816 | ||
de9ce703 DT |
817 | if (i8042_command(¶m, I8042_CMD_AUX_TEST) || |
818 | (param && param != 0xfa && param != 0xff)) | |
819 | return -1; | |
1e4865f8 | 820 | |
3ca5de6d DT |
821 | /* |
822 | * If AUX_LOOP completed without error but returned unexpected data | |
823 | * mark it as broken | |
824 | */ | |
825 | if (!retval) | |
386b3849 | 826 | aux_loop_broken = true; |
1da177e4 LT |
827 | } |
828 | ||
829 | /* | |
830 | * Bit assignment test - filters out PS/2 i8042's in AT mode | |
831 | */ | |
832 | ||
386b3849 | 833 | if (i8042_toggle_aux(false)) { |
4eb3c30b JP |
834 | pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); |
835 | pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); | |
1da177e4 LT |
836 | } |
837 | ||
386b3849 | 838 | if (i8042_toggle_aux(true)) |
1da177e4 LT |
839 | return -1; |
840 | ||
148e9a71 SV |
841 | /* |
842 | * Reset keyboard (needed on some laptops to successfully detect | |
843 | * touchpad, e.g., some Gigabyte laptop models with Elantech | |
844 | * touchpads). | |
845 | */ | |
846 | if (i8042_kbdreset) { | |
847 | pr_warn("Attempting to reset device connected to KBD port\n"); | |
848 | i8042_kbd_write(NULL, (unsigned char) 0xff); | |
849 | } | |
850 | ||
1da177e4 | 851 | /* |
de9ce703 DT |
852 | * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and |
853 | * used it for a PCI card or somethig else. | |
1da177e4 LT |
854 | */ |
855 | ||
1c7827ae | 856 | if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { |
de9ce703 DT |
857 | /* |
858 | * Without LOOP command we can't test AUX IRQ delivery. Assume the port | |
859 | * is working and hope we are right. | |
860 | */ | |
861 | retval = 0; | |
862 | goto out; | |
863 | } | |
1da177e4 | 864 | |
de9ce703 DT |
865 | if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, |
866 | "i8042", i8042_platform_device)) | |
867 | goto out; | |
1da177e4 | 868 | |
386b3849 | 869 | irq_registered = true; |
de9ce703 DT |
870 | |
871 | if (i8042_enable_aux_port()) | |
872 | goto out; | |
873 | ||
874 | spin_lock_irqsave(&i8042_lock, flags); | |
1da177e4 | 875 | |
de9ce703 | 876 | init_completion(&i8042_aux_irq_delivered); |
386b3849 | 877 | i8042_irq_being_tested = true; |
de9ce703 DT |
878 | |
879 | param = 0xa5; | |
880 | retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); | |
881 | ||
882 | spin_unlock_irqrestore(&i8042_lock, flags); | |
883 | ||
884 | if (retval) | |
885 | goto out; | |
1da177e4 | 886 | |
de9ce703 DT |
887 | if (wait_for_completion_timeout(&i8042_aux_irq_delivered, |
888 | msecs_to_jiffies(250)) == 0) { | |
1da177e4 | 889 | /* |
de9ce703 DT |
890 | * AUX IRQ was never delivered so we need to flush the controller to |
891 | * get rid of the byte we put there; otherwise keyboard may not work. | |
1da177e4 | 892 | */ |
4eb3c30b | 893 | dbg(" -- i8042 (aux irq test timeout)\n"); |
de9ce703 DT |
894 | i8042_flush(); |
895 | retval = -1; | |
896 | } | |
1da177e4 | 897 | |
de9ce703 | 898 | out: |
1da177e4 | 899 | |
de9ce703 DT |
900 | /* |
901 | * Disable the interface. | |
902 | */ | |
1da177e4 | 903 | |
de9ce703 DT |
904 | i8042_ctr |= I8042_CTR_AUXDIS; |
905 | i8042_ctr &= ~I8042_CTR_AUXINT; | |
1da177e4 | 906 | |
de9ce703 DT |
907 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
908 | retval = -1; | |
1da177e4 | 909 | |
de9ce703 DT |
910 | if (irq_registered) |
911 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1da177e4 | 912 | |
de9ce703 DT |
913 | return retval; |
914 | } | |
1da177e4 | 915 | |
de9ce703 | 916 | static int i8042_controller_check(void) |
1da177e4 | 917 | { |
2f0d2604 | 918 | if (i8042_flush()) { |
f5d75341 | 919 | pr_info("No controller found\n"); |
de9ce703 DT |
920 | return -ENODEV; |
921 | } | |
922 | ||
923 | return 0; | |
1da177e4 LT |
924 | } |
925 | ||
de9ce703 | 926 | static int i8042_controller_selftest(void) |
2673c836 VP |
927 | { |
928 | unsigned char param; | |
5ea2fc64 | 929 | int i = 0; |
2673c836 | 930 | |
5ea2fc64 AV |
931 | /* |
932 | * We try this 5 times; on some really fragile systems this does not | |
933 | * take the first time... | |
934 | */ | |
935 | do { | |
936 | ||
937 | if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { | |
a2a94e73 | 938 | pr_err("i8042 controller selftest timeout\n"); |
5ea2fc64 AV |
939 | return -ENODEV; |
940 | } | |
941 | ||
942 | if (param == I8042_RET_CTL_TEST) | |
943 | return 0; | |
2673c836 | 944 | |
a2a94e73 PB |
945 | dbg("i8042 controller selftest: %#x != %#x\n", |
946 | param, I8042_RET_CTL_TEST); | |
5ea2fc64 AV |
947 | msleep(50); |
948 | } while (i++ < 5); | |
2673c836 | 949 | |
5ea2fc64 AV |
950 | #ifdef CONFIG_X86 |
951 | /* | |
952 | * On x86, we don't fail entire i8042 initialization if controller | |
953 | * reset fails in hopes that keyboard port will still be functional | |
954 | * and user will still get a working keyboard. This is especially | |
955 | * important on netbooks. On other arches we trust hardware more. | |
956 | */ | |
4eb3c30b | 957 | pr_info("giving up on controller selftest, continuing anyway...\n"); |
2673c836 | 958 | return 0; |
5ea2fc64 | 959 | #else |
a2a94e73 | 960 | pr_err("i8042 controller selftest failed\n"); |
5ea2fc64 AV |
961 | return -EIO; |
962 | #endif | |
2673c836 | 963 | } |
1da177e4 LT |
964 | |
965 | /* | |
966 | * i8042_controller init initializes the i8042 controller, and, | |
967 | * most importantly, sets it into non-xlated mode if that's | |
968 | * desired. | |
969 | */ | |
970 | ||
971 | static int i8042_controller_init(void) | |
972 | { | |
973 | unsigned long flags; | |
ee1e82ce DT |
974 | int n = 0; |
975 | unsigned char ctr[2]; | |
1da177e4 | 976 | |
1da177e4 | 977 | /* |
ee1e82ce | 978 | * Save the CTR for restore on unload / reboot. |
1da177e4 LT |
979 | */ |
980 | ||
ee1e82ce DT |
981 | do { |
982 | if (n >= 10) { | |
4eb3c30b | 983 | pr_err("Unable to get stable CTR read\n"); |
ee1e82ce DT |
984 | return -EIO; |
985 | } | |
986 | ||
987 | if (n != 0) | |
988 | udelay(50); | |
989 | ||
990 | if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { | |
4eb3c30b | 991 | pr_err("Can't read CTR while initializing i8042\n"); |
ee1e82ce DT |
992 | return -EIO; |
993 | } | |
994 | ||
995 | } while (n < 2 || ctr[0] != ctr[1]); | |
1da177e4 | 996 | |
ee1e82ce | 997 | i8042_initial_ctr = i8042_ctr = ctr[0]; |
1da177e4 LT |
998 | |
999 | /* | |
1000 | * Disable the keyboard interface and interrupt. | |
1001 | */ | |
1002 | ||
1003 | i8042_ctr |= I8042_CTR_KBDDIS; | |
1004 | i8042_ctr &= ~I8042_CTR_KBDINT; | |
1005 | ||
1006 | /* | |
1007 | * Handle keylock. | |
1008 | */ | |
1009 | ||
1010 | spin_lock_irqsave(&i8042_lock, flags); | |
1011 | if (~i8042_read_status() & I8042_STR_KEYLOCK) { | |
1012 | if (i8042_unlock) | |
1013 | i8042_ctr |= I8042_CTR_IGNKEYLOCK; | |
82dd9eff | 1014 | else |
4eb3c30b | 1015 | pr_warn("Warning: Keylock active\n"); |
1da177e4 LT |
1016 | } |
1017 | spin_unlock_irqrestore(&i8042_lock, flags); | |
1018 | ||
1019 | /* | |
1020 | * If the chip is configured into nontranslated mode by the BIOS, don't | |
1021 | * bother enabling translating and be happy. | |
1022 | */ | |
1023 | ||
1024 | if (~i8042_ctr & I8042_CTR_XLATE) | |
386b3849 | 1025 | i8042_direct = true; |
1da177e4 LT |
1026 | |
1027 | /* | |
1028 | * Set nontranslated mode for the kbd interface if requested by an option. | |
1029 | * After this the kbd interface becomes a simple serial in/out, like the aux | |
1030 | * interface is. We don't do this by default, since it can confuse notebook | |
1031 | * BIOSes. | |
1032 | */ | |
1033 | ||
1034 | if (i8042_direct) | |
1035 | i8042_ctr &= ~I8042_CTR_XLATE; | |
1036 | ||
1037 | /* | |
1038 | * Write CTR back. | |
1039 | */ | |
1040 | ||
1041 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1042 | pr_err("Can't write CTR while initializing i8042\n"); |
de9ce703 | 1043 | return -EIO; |
1da177e4 LT |
1044 | } |
1045 | ||
ee1e82ce DT |
1046 | /* |
1047 | * Flush whatever accumulated while we were disabling keyboard port. | |
1048 | */ | |
1049 | ||
1050 | i8042_flush(); | |
1051 | ||
1da177e4 LT |
1052 | return 0; |
1053 | } | |
1054 | ||
1055 | ||
1056 | /* | |
de9ce703 | 1057 | * Reset the controller and reset CRT to the original value set by BIOS. |
1da177e4 | 1058 | */ |
de9ce703 | 1059 | |
930e1924 | 1060 | static void i8042_controller_reset(bool s2r_wants_reset) |
1da177e4 | 1061 | { |
de9ce703 | 1062 | i8042_flush(); |
1da177e4 | 1063 | |
8d04ddb6 DT |
1064 | /* |
1065 | * Disable both KBD and AUX interfaces so they don't get in the way | |
1066 | */ | |
1067 | ||
1068 | i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; | |
1069 | i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); | |
1070 | ||
ee1e82ce | 1071 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) |
4eb3c30b | 1072 | pr_warn("Can't write CTR while resetting\n"); |
5ddbc77c | 1073 | |
1da177e4 LT |
1074 | /* |
1075 | * Disable MUX mode if present. | |
1076 | */ | |
1077 | ||
1078 | if (i8042_mux_present) | |
386b3849 | 1079 | i8042_set_mux_mode(false, NULL); |
1da177e4 LT |
1080 | |
1081 | /* | |
de9ce703 | 1082 | * Reset the controller if requested. |
1da177e4 LT |
1083 | */ |
1084 | ||
930e1924 MPS |
1085 | if (i8042_reset == I8042_RESET_ALWAYS || |
1086 | (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { | |
1ca56e51 | 1087 | i8042_controller_selftest(); |
930e1924 | 1088 | } |
1da177e4 | 1089 | |
de9ce703 DT |
1090 | /* |
1091 | * Restore the original control register setting. | |
1092 | */ | |
1093 | ||
1094 | if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) | |
4eb3c30b | 1095 | pr_warn("Can't restore CTR\n"); |
1da177e4 LT |
1096 | } |
1097 | ||
1098 | ||
1da177e4 | 1099 | /* |
c7ff0d9c TS |
1100 | * i8042_panic_blink() will turn the keyboard LEDs on or off and is called |
1101 | * when kernel panics. Flashing LEDs is useful for users running X who may | |
aa5e5dc2 | 1102 | * not see the console and will help distinguishing panics from "real" |
1da177e4 LT |
1103 | * lockups. |
1104 | * | |
1105 | * Note that DELAY has a limit of 10ms so we will not get stuck here | |
1106 | * waiting for KBC to free up even if KBD interrupt is off | |
1107 | */ | |
1108 | ||
1109 | #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) | |
1110 | ||
c7ff0d9c | 1111 | static long i8042_panic_blink(int state) |
1da177e4 LT |
1112 | { |
1113 | long delay = 0; | |
c7ff0d9c | 1114 | char led; |
1da177e4 | 1115 | |
c7ff0d9c | 1116 | led = (state) ? 0x01 | 0x04 : 0; |
1da177e4 LT |
1117 | while (i8042_read_status() & I8042_STR_IBF) |
1118 | DELAY; | |
4eb3c30b | 1119 | dbg("%02x -> i8042 (panic blink)\n", 0xed); |
19f3c3e3 | 1120 | i8042_suppress_kbd_ack = 2; |
1da177e4 LT |
1121 | i8042_write_data(0xed); /* set leds */ |
1122 | DELAY; | |
1123 | while (i8042_read_status() & I8042_STR_IBF) | |
1124 | DELAY; | |
1125 | DELAY; | |
4eb3c30b | 1126 | dbg("%02x -> i8042 (panic blink)\n", led); |
1da177e4 LT |
1127 | i8042_write_data(led); |
1128 | DELAY; | |
1da177e4 LT |
1129 | return delay; |
1130 | } | |
1131 | ||
1132 | #undef DELAY | |
1133 | ||
d35895db BP |
1134 | #ifdef CONFIG_X86 |
1135 | static void i8042_dritek_enable(void) | |
1136 | { | |
594d6363 | 1137 | unsigned char param = 0x90; |
d35895db BP |
1138 | int error; |
1139 | ||
1140 | error = i8042_command(¶m, 0x1059); | |
1141 | if (error) | |
4eb3c30b | 1142 | pr_warn("Failed to enable DRITEK extension: %d\n", error); |
d35895db BP |
1143 | } |
1144 | #endif | |
1145 | ||
82dd9eff | 1146 | #ifdef CONFIG_PM |
7e044e05 | 1147 | |
1da177e4 | 1148 | /* |
ebd7768d DT |
1149 | * Here we try to reset everything back to a state we had |
1150 | * before suspending. | |
1da177e4 LT |
1151 | */ |
1152 | ||
930e1924 | 1153 | static int i8042_controller_resume(bool s2r_wants_reset) |
1da177e4 | 1154 | { |
de9ce703 | 1155 | int error; |
1da177e4 | 1156 | |
de9ce703 DT |
1157 | error = i8042_controller_check(); |
1158 | if (error) | |
1159 | return error; | |
2673c836 | 1160 | |
930e1924 MPS |
1161 | if (i8042_reset == I8042_RESET_ALWAYS || |
1162 | (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { | |
1ca56e51 DT |
1163 | error = i8042_controller_selftest(); |
1164 | if (error) | |
1165 | return error; | |
1166 | } | |
1da177e4 LT |
1167 | |
1168 | /* | |
82dd9eff | 1169 | * Restore original CTR value and disable all ports |
1da177e4 LT |
1170 | */ |
1171 | ||
82dd9eff DT |
1172 | i8042_ctr = i8042_initial_ctr; |
1173 | if (i8042_direct) | |
1174 | i8042_ctr &= ~I8042_CTR_XLATE; | |
de9ce703 DT |
1175 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
1176 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | |
1177 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1178 | pr_warn("Can't write CTR to resume, retrying...\n"); |
2f6a77d5 JK |
1179 | msleep(50); |
1180 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | |
4eb3c30b | 1181 | pr_err("CTR write retry failed\n"); |
2f6a77d5 JK |
1182 | return -EIO; |
1183 | } | |
de9ce703 | 1184 | } |
1da177e4 | 1185 | |
d35895db BP |
1186 | |
1187 | #ifdef CONFIG_X86 | |
1188 | if (i8042_dritek) | |
1189 | i8042_dritek_enable(); | |
1190 | #endif | |
1191 | ||
de9ce703 | 1192 | if (i8042_mux_present) { |
386b3849 | 1193 | if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) |
4eb3c30b | 1194 | pr_warn("failed to resume active multiplexor, mouse won't work\n"); |
de9ce703 DT |
1195 | } else if (i8042_ports[I8042_AUX_PORT_NO].serio) |
1196 | i8042_enable_aux_port(); | |
1da177e4 | 1197 | |
de9ce703 DT |
1198 | if (i8042_ports[I8042_KBD_PORT_NO].serio) |
1199 | i8042_enable_kbd_port(); | |
1200 | ||
7d12e780 | 1201 | i8042_interrupt(0, NULL); |
1da177e4 LT |
1202 | |
1203 | return 0; | |
1da177e4 | 1204 | } |
ebd7768d | 1205 | |
1ca56e51 DT |
1206 | /* |
1207 | * Here we try to restore the original BIOS settings to avoid | |
1208 | * upsetting it. | |
1209 | */ | |
1210 | ||
1729ad1f | 1211 | static int i8042_pm_suspend(struct device *dev) |
1ca56e51 | 1212 | { |
f13b2065 RW |
1213 | int i; |
1214 | ||
1c5dd134 RW |
1215 | if (pm_suspend_via_firmware()) |
1216 | i8042_controller_reset(true); | |
1ca56e51 | 1217 | |
f13b2065 RW |
1218 | /* Set up serio interrupts for system wakeup. */ |
1219 | for (i = 0; i < I8042_NUM_PORTS; i++) { | |
1220 | struct serio *serio = i8042_ports[i].serio; | |
1221 | ||
1222 | if (serio && device_may_wakeup(&serio->dev)) | |
1223 | enable_irq_wake(i8042_ports[i].irq); | |
1224 | } | |
1225 | ||
1ca56e51 DT |
1226 | return 0; |
1227 | } | |
1228 | ||
1c5dd134 RW |
1229 | static int i8042_pm_resume_noirq(struct device *dev) |
1230 | { | |
1231 | if (!pm_resume_via_firmware()) | |
1232 | i8042_interrupt(0, NULL); | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
1ca56e51 DT |
1237 | static int i8042_pm_resume(struct device *dev) |
1238 | { | |
930e1924 | 1239 | bool want_reset; |
f13b2065 RW |
1240 | int i; |
1241 | ||
1242 | for (i = 0; i < I8042_NUM_PORTS; i++) { | |
1243 | struct serio *serio = i8042_ports[i].serio; | |
1244 | ||
1245 | if (serio && device_may_wakeup(&serio->dev)) | |
1246 | disable_irq_wake(i8042_ports[i].irq); | |
1247 | } | |
1248 | ||
1ca56e51 | 1249 | /* |
1c5dd134 RW |
1250 | * If platform firmware was not going to be involved in suspend, we did |
1251 | * not restore the controller state to whatever it had been at boot | |
1252 | * time, so we do not need to do anything. | |
1ca56e51 | 1253 | */ |
1c5dd134 RW |
1254 | if (!pm_suspend_via_firmware()) |
1255 | return 0; | |
1256 | ||
1257 | /* | |
1258 | * We only need to reset the controller if we are resuming after handing | |
1259 | * off control to the platform firmware, otherwise we can simply restore | |
1260 | * the mode. | |
1261 | */ | |
930e1924 | 1262 | want_reset = pm_resume_via_firmware(); |
1c5dd134 | 1263 | |
930e1924 | 1264 | return i8042_controller_resume(want_reset); |
1ca56e51 DT |
1265 | } |
1266 | ||
c2d1a2a1 AJ |
1267 | static int i8042_pm_thaw(struct device *dev) |
1268 | { | |
1269 | i8042_interrupt(0, NULL); | |
1270 | ||
1271 | return 0; | |
1272 | } | |
1273 | ||
1729ad1f DT |
1274 | static int i8042_pm_reset(struct device *dev) |
1275 | { | |
1276 | i8042_controller_reset(false); | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
1ca56e51 DT |
1281 | static int i8042_pm_restore(struct device *dev) |
1282 | { | |
1283 | return i8042_controller_resume(false); | |
1284 | } | |
1285 | ||
ebd7768d | 1286 | static const struct dev_pm_ops i8042_pm_ops = { |
1729ad1f | 1287 | .suspend = i8042_pm_suspend, |
1c5dd134 | 1288 | .resume_noirq = i8042_pm_resume_noirq, |
1ca56e51 | 1289 | .resume = i8042_pm_resume, |
c2d1a2a1 | 1290 | .thaw = i8042_pm_thaw, |
ebd7768d DT |
1291 | .poweroff = i8042_pm_reset, |
1292 | .restore = i8042_pm_restore, | |
1293 | }; | |
1294 | ||
82dd9eff | 1295 | #endif /* CONFIG_PM */ |
1da177e4 LT |
1296 | |
1297 | /* | |
1298 | * We need to reset the 8042 back to original mode on system shutdown, | |
1299 | * because otherwise BIOSes will be confused. | |
1300 | */ | |
1301 | ||
3ae5eaec | 1302 | static void i8042_shutdown(struct platform_device *dev) |
1da177e4 | 1303 | { |
1729ad1f | 1304 | i8042_controller_reset(false); |
1da177e4 LT |
1305 | } |
1306 | ||
f8113416 | 1307 | static int __init i8042_create_kbd_port(void) |
1da177e4 LT |
1308 | { |
1309 | struct serio *serio; | |
1310 | struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; | |
1311 | ||
d39969de | 1312 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1313 | if (!serio) |
1314 | return -ENOMEM; | |
1315 | ||
1316 | serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; | |
1317 | serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; | |
0854e52d DT |
1318 | serio->start = i8042_start; |
1319 | serio->stop = i8042_stop; | |
5ddbc77c | 1320 | serio->close = i8042_port_close; |
40974618 | 1321 | serio->ps2_cmd_mutex = &i8042_mutex; |
0854e52d DT |
1322 | serio->port_data = port; |
1323 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 | 1324 | strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); |
0854e52d | 1325 | strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); |
a7c5868c HG |
1326 | strlcpy(serio->firmware_id, i8042_kbd_firmware_id, |
1327 | sizeof(serio->firmware_id)); | |
0854e52d DT |
1328 | |
1329 | port->serio = serio; | |
de9ce703 | 1330 | port->irq = I8042_KBD_IRQ; |
0854e52d | 1331 | |
de9ce703 | 1332 | return 0; |
1da177e4 LT |
1333 | } |
1334 | ||
f8113416 | 1335 | static int __init i8042_create_aux_port(int idx) |
1da177e4 LT |
1336 | { |
1337 | struct serio *serio; | |
de9ce703 DT |
1338 | int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; |
1339 | struct i8042_port *port = &i8042_ports[port_no]; | |
1da177e4 | 1340 | |
d39969de | 1341 | serio = kzalloc(sizeof(struct serio), GFP_KERNEL); |
0854e52d DT |
1342 | if (!serio) |
1343 | return -ENOMEM; | |
1344 | ||
1345 | serio->id.type = SERIO_8042; | |
1346 | serio->write = i8042_aux_write; | |
0854e52d DT |
1347 | serio->start = i8042_start; |
1348 | serio->stop = i8042_stop; | |
47af45d6 | 1349 | serio->ps2_cmd_mutex = &i8042_mutex; |
0854e52d DT |
1350 | serio->port_data = port; |
1351 | serio->dev.parent = &i8042_platform_device->dev; | |
de9ce703 DT |
1352 | if (idx < 0) { |
1353 | strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); | |
1354 | strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); | |
a7c5868c HG |
1355 | strlcpy(serio->firmware_id, i8042_aux_firmware_id, |
1356 | sizeof(serio->firmware_id)); | |
5ddbc77c | 1357 | serio->close = i8042_port_close; |
de9ce703 DT |
1358 | } else { |
1359 | snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); | |
1360 | snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); | |
266e43c4 HG |
1361 | strlcpy(serio->firmware_id, i8042_aux_firmware_id, |
1362 | sizeof(serio->firmware_id)); | |
de9ce703 | 1363 | } |
0854e52d DT |
1364 | |
1365 | port->serio = serio; | |
de9ce703 DT |
1366 | port->mux = idx; |
1367 | port->irq = I8042_AUX_IRQ; | |
0854e52d | 1368 | |
de9ce703 | 1369 | return 0; |
1da177e4 LT |
1370 | } |
1371 | ||
f8113416 | 1372 | static void __init i8042_free_kbd_port(void) |
1da177e4 | 1373 | { |
de9ce703 DT |
1374 | kfree(i8042_ports[I8042_KBD_PORT_NO].serio); |
1375 | i8042_ports[I8042_KBD_PORT_NO].serio = NULL; | |
1376 | } | |
1da177e4 | 1377 | |
f8113416 | 1378 | static void __init i8042_free_aux_ports(void) |
de9ce703 DT |
1379 | { |
1380 | int i; | |
0854e52d | 1381 | |
de9ce703 DT |
1382 | for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { |
1383 | kfree(i8042_ports[i].serio); | |
1384 | i8042_ports[i].serio = NULL; | |
1385 | } | |
1386 | } | |
0854e52d | 1387 | |
f8113416 | 1388 | static void __init i8042_register_ports(void) |
de9ce703 DT |
1389 | { |
1390 | int i; | |
0854e52d | 1391 | |
de9ce703 | 1392 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
f13b2065 RW |
1393 | struct serio *serio = i8042_ports[i].serio; |
1394 | ||
1395 | if (serio) { | |
de9ce703 | 1396 | printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", |
f13b2065 | 1397 | serio->name, |
de9ce703 DT |
1398 | (unsigned long) I8042_DATA_REG, |
1399 | (unsigned long) I8042_COMMAND_REG, | |
1400 | i8042_ports[i].irq); | |
f13b2065 RW |
1401 | serio_register_port(serio); |
1402 | device_set_wakeup_capable(&serio->dev, true); | |
de9ce703 DT |
1403 | } |
1404 | } | |
1da177e4 LT |
1405 | } |
1406 | ||
e2619cf7 | 1407 | static void i8042_unregister_ports(void) |
1da177e4 | 1408 | { |
de9ce703 | 1409 | int i; |
1da177e4 | 1410 | |
de9ce703 DT |
1411 | for (i = 0; i < I8042_NUM_PORTS; i++) { |
1412 | if (i8042_ports[i].serio) { | |
1413 | serio_unregister_port(i8042_ports[i].serio); | |
1414 | i8042_ports[i].serio = NULL; | |
1415 | } | |
1416 | } | |
1417 | } | |
1418 | ||
1419 | static void i8042_free_irqs(void) | |
1420 | { | |
1421 | if (i8042_aux_irq_registered) | |
1422 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1423 | if (i8042_kbd_irq_registered) | |
1424 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1425 | ||
386b3849 | 1426 | i8042_aux_irq_registered = i8042_kbd_irq_registered = false; |
de9ce703 DT |
1427 | } |
1428 | ||
f8113416 | 1429 | static int __init i8042_setup_aux(void) |
de9ce703 DT |
1430 | { |
1431 | int (*aux_enable)(void); | |
1432 | int error; | |
1433 | int i; | |
1da177e4 | 1434 | |
de9ce703 | 1435 | if (i8042_check_aux()) |
87fd6318 | 1436 | return -ENODEV; |
1da177e4 | 1437 | |
de9ce703 DT |
1438 | if (i8042_nomux || i8042_check_mux()) { |
1439 | error = i8042_create_aux_port(-1); | |
1440 | if (error) | |
1441 | goto err_free_ports; | |
1442 | aux_enable = i8042_enable_aux_port; | |
1443 | } else { | |
1444 | for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { | |
1445 | error = i8042_create_aux_port(i); | |
1446 | if (error) | |
1447 | goto err_free_ports; | |
0854e52d | 1448 | } |
de9ce703 | 1449 | aux_enable = i8042_enable_mux_ports; |
1da177e4 LT |
1450 | } |
1451 | ||
de9ce703 DT |
1452 | error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, |
1453 | "i8042", i8042_platform_device); | |
1454 | if (error) | |
1455 | goto err_free_ports; | |
945ef0d4 | 1456 | |
de9ce703 DT |
1457 | if (aux_enable()) |
1458 | goto err_free_irq; | |
1da177e4 | 1459 | |
386b3849 | 1460 | i8042_aux_irq_registered = true; |
1da177e4 | 1461 | return 0; |
0854e52d | 1462 | |
de9ce703 DT |
1463 | err_free_irq: |
1464 | free_irq(I8042_AUX_IRQ, i8042_platform_device); | |
1465 | err_free_ports: | |
1466 | i8042_free_aux_ports(); | |
1467 | return error; | |
1468 | } | |
0854e52d | 1469 | |
f8113416 | 1470 | static int __init i8042_setup_kbd(void) |
de9ce703 DT |
1471 | { |
1472 | int error; | |
1473 | ||
1474 | error = i8042_create_kbd_port(); | |
1475 | if (error) | |
1476 | return error; | |
1477 | ||
1478 | error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, | |
1479 | "i8042", i8042_platform_device); | |
1480 | if (error) | |
1481 | goto err_free_port; | |
1482 | ||
1483 | error = i8042_enable_kbd_port(); | |
1484 | if (error) | |
1485 | goto err_free_irq; | |
1486 | ||
386b3849 | 1487 | i8042_kbd_irq_registered = true; |
de9ce703 DT |
1488 | return 0; |
1489 | ||
1490 | err_free_irq: | |
1491 | free_irq(I8042_KBD_IRQ, i8042_platform_device); | |
1492 | err_free_port: | |
1493 | i8042_free_kbd_port(); | |
1494 | return error; | |
1da177e4 LT |
1495 | } |
1496 | ||
e1443d28 SCP |
1497 | static int i8042_kbd_bind_notifier(struct notifier_block *nb, |
1498 | unsigned long action, void *data) | |
1499 | { | |
1500 | struct device *dev = data; | |
1501 | struct serio *serio = to_serio_port(dev); | |
1502 | struct i8042_port *port = serio->port_data; | |
1503 | ||
1504 | if (serio != i8042_ports[I8042_KBD_PORT_NO].serio) | |
1505 | return 0; | |
1506 | ||
1507 | switch (action) { | |
1508 | case BUS_NOTIFY_BOUND_DRIVER: | |
1509 | port->driver_bound = true; | |
1510 | break; | |
1511 | ||
1512 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1513 | port->driver_bound = false; | |
1514 | break; | |
1515 | } | |
1516 | ||
1517 | return 0; | |
1518 | } | |
1519 | ||
f8113416 | 1520 | static int __init i8042_probe(struct platform_device *dev) |
1da177e4 | 1521 | { |
de9ce703 | 1522 | int error; |
1da177e4 | 1523 | |
ec62e1c8 DT |
1524 | i8042_platform_device = dev; |
1525 | ||
930e1924 | 1526 | if (i8042_reset == I8042_RESET_ALWAYS) { |
1ca56e51 DT |
1527 | error = i8042_controller_selftest(); |
1528 | if (error) | |
1529 | return error; | |
1530 | } | |
1da177e4 | 1531 | |
de9ce703 DT |
1532 | error = i8042_controller_init(); |
1533 | if (error) | |
1534 | return error; | |
1535 | ||
d35895db BP |
1536 | #ifdef CONFIG_X86 |
1537 | if (i8042_dritek) | |
1538 | i8042_dritek_enable(); | |
1539 | #endif | |
1540 | ||
de9ce703 DT |
1541 | if (!i8042_noaux) { |
1542 | error = i8042_setup_aux(); | |
1543 | if (error && error != -ENODEV && error != -EBUSY) | |
1544 | goto out_fail; | |
1545 | } | |
1546 | ||
1547 | if (!i8042_nokbd) { | |
1548 | error = i8042_setup_kbd(); | |
1549 | if (error) | |
1550 | goto out_fail; | |
1551 | } | |
de9ce703 DT |
1552 | /* |
1553 | * Ok, everything is ready, let's register all serio ports | |
1554 | */ | |
1555 | i8042_register_ports(); | |
1556 | ||
1557 | return 0; | |
1558 | ||
1559 | out_fail: | |
1560 | i8042_free_aux_ports(); /* in case KBD failed but AUX not */ | |
1561 | i8042_free_irqs(); | |
1729ad1f | 1562 | i8042_controller_reset(false); |
ec62e1c8 | 1563 | i8042_platform_device = NULL; |
de9ce703 DT |
1564 | |
1565 | return error; | |
1566 | } | |
1567 | ||
e2619cf7 | 1568 | static int i8042_remove(struct platform_device *dev) |
de9ce703 DT |
1569 | { |
1570 | i8042_unregister_ports(); | |
1571 | i8042_free_irqs(); | |
1729ad1f | 1572 | i8042_controller_reset(false); |
ec62e1c8 | 1573 | i8042_platform_device = NULL; |
1da177e4 | 1574 | |
87fd6318 DT |
1575 | return 0; |
1576 | } | |
1577 | ||
1578 | static struct platform_driver i8042_driver = { | |
1579 | .driver = { | |
1580 | .name = "i8042", | |
ebd7768d DT |
1581 | #ifdef CONFIG_PM |
1582 | .pm = &i8042_pm_ops, | |
1583 | #endif | |
87fd6318 | 1584 | }, |
1cb0aa88 | 1585 | .remove = i8042_remove, |
82dd9eff | 1586 | .shutdown = i8042_shutdown, |
87fd6318 DT |
1587 | }; |
1588 | ||
e1443d28 SCP |
1589 | static struct notifier_block i8042_kbd_bind_notifier_block = { |
1590 | .notifier_call = i8042_kbd_bind_notifier, | |
1591 | }; | |
1592 | ||
87fd6318 DT |
1593 | static int __init i8042_init(void) |
1594 | { | |
ec62e1c8 | 1595 | struct platform_device *pdev; |
87fd6318 DT |
1596 | int err; |
1597 | ||
1598 | dbg_init(); | |
1599 | ||
1600 | err = i8042_platform_init(); | |
1601 | if (err) | |
1602 | return err; | |
1603 | ||
de9ce703 DT |
1604 | err = i8042_controller_check(); |
1605 | if (err) | |
1606 | goto err_platform_exit; | |
87fd6318 | 1607 | |
ec62e1c8 DT |
1608 | pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); |
1609 | if (IS_ERR(pdev)) { | |
1610 | err = PTR_ERR(pdev); | |
f8113416 | 1611 | goto err_platform_exit; |
87fd6318 DT |
1612 | } |
1613 | ||
e1443d28 | 1614 | bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); |
de9ce703 DT |
1615 | panic_blink = i8042_panic_blink; |
1616 | ||
87fd6318 DT |
1617 | return 0; |
1618 | ||
87fd6318 DT |
1619 | err_platform_exit: |
1620 | i8042_platform_exit(); | |
87fd6318 DT |
1621 | return err; |
1622 | } | |
1623 | ||
1624 | static void __exit i8042_exit(void) | |
1625 | { | |
f8113416 | 1626 | platform_device_unregister(i8042_platform_device); |
af045b86 | 1627 | platform_driver_unregister(&i8042_driver); |
1da177e4 LT |
1628 | i8042_platform_exit(); |
1629 | ||
e1443d28 | 1630 | bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); |
1da177e4 LT |
1631 | panic_blink = NULL; |
1632 | } | |
1633 | ||
1634 | module_init(i8042_init); | |
1635 | module_exit(i8042_exit); |